From f5df2927b7fd0134113e6eeb84676e61775caa85 Mon Sep 17 00:00:00 2001 From: Marco Vogt Date: Mon, 28 Oct 2024 08:43:08 +0100 Subject: [PATCH] FIX: deprecation warning, new assignment syntax --- basil/utils/sim/BasilBusDriver.py | 52 +++++++++++++++---------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/basil/utils/sim/BasilBusDriver.py b/basil/utils/sim/BasilBusDriver.py index 461c30aa..864403ab 100644 --- a/basil/utils/sim/BasilBusDriver.py +++ b/basil/utils/sim/BasilBusDriver.py @@ -36,16 +36,16 @@ def __init__(self, entity): async def init(self): # Defaults - self.bus.BUS_RST <= 1 - self.bus.BUS_RD <= 0 - self.bus.BUS_WR <= 0 - self.bus.BUS_ADD <= self._x - self.bus.BUS_DATA <= self._high_impedence + self.bus.BUS_RST.value = 1 + self.bus.BUS_RD.value = 0 + self.bus.BUS_WR.value = 0 + self.bus.BUS_ADD.value = self._x + self.bus.BUS_DATA.value = self._high_impedence for _ in range(8): await RisingEdge(self.clock) - self.bus.BUS_RST <= 0 + self.bus.BUS_RST.value = 0 for _ in range(2): await RisingEdge(self.clock) @@ -61,20 +61,20 @@ async def init(self): async def read(self, address, size): result = [] - self.bus.BUS_DATA <= self._high_impedence - self.bus.BUS_ADD <= self._x - self.bus.BUS_RD <= 0 + self.bus.BUS_DATA.value = self._high_impedence + self.bus.BUS_ADD.value = self._x + self.bus.BUS_RD.value = 0 await RisingEdge(self.clock) byte = 0 while byte <= size: if byte == size: - self.bus.BUS_RD <= 0 + self.bus.BUS_RD.value = 0 else: - self.bus.BUS_RD <= 1 + self.bus.BUS_RD.value = 1 - self.bus.BUS_ADD <= address + byte + self.bus.BUS_ADD.value = address + byte await RisingEdge(self.clock) @@ -96,36 +96,36 @@ async def read(self, address, size): else: byte += 1 - self.bus.BUS_ADD <= self._x - self.bus.BUS_DATA <= self._high_impedence + self.bus.BUS_ADD.value = self._x + self.bus.BUS_DATA.value = self._high_impedence await RisingEdge(self.clock) return result async def write(self, address, data): - self.bus.BUS_ADD <= self._x - self.bus.BUS_DATA <= self._high_impedence - self.bus.BUS_WR <= 0 + self.bus.BUS_ADD.value = self._x + self.bus.BUS_DATA.value = self._high_impedence + self.bus.BUS_WR.value = 0 await RisingEdge(self.clock) for index, byte in enumerate(data): - self.bus.BUS_DATA <= byte - self.bus.BUS_WR <= 1 - self.bus.BUS_ADD <= address + index + self.bus.BUS_DATA.value = byte + self.bus.BUS_WR.value = 1 + self.bus.BUS_ADD.value = address + index await Timer(1) # This is hack for iverilog - self.bus.BUS_DATA <= byte - self.bus.BUS_WR <= 1 - self.bus.BUS_ADD <= address + index + self.bus.BUS_DATA.value = byte + self.bus.BUS_WR.value = 1 + self.bus.BUS_ADD.value = address + index await RisingEdge(self.clock) if self._has_byte_acces and self.bus.BUS_BYTE_ACCESS.value.integer == 0: raise NotImplementedError("BUS_BYTE_ACCESS for write to be implemented.") - self.bus.BUS_DATA <= self._high_impedence - self.bus.BUS_ADD <= self._x - self.bus.BUS_WR <= 0 + self.bus.BUS_DATA.value = self._high_impedence + self.bus.BUS_ADD.value = self._x + self.bus.BUS_WR.value = 0 await RisingEdge(self.clock)