diff --git a/tests/test_SimSpi.py b/tests/test_SimSpi.py
index 4fb63468..6e41073d 100644
--- a/tests/test_SimSpi.py
+++ b/tests/test_SimSpi.py
@@ -64,8 +64,19 @@
 
 
 class TestSimSpi(unittest.TestCase):
+    def __init__(self, testname, tb='test_SimSpi.v', bus_drv='basil.utils.sim.BasilBusDriver', bus_split=False):
+        super(TestSimSpi, self).__init__(testname)
+        self._test_tb = tb
+        self._sim_bus = bus_drv
+        self._bus_split_def = ()
+        if bus_split is not False:
+            if bus_split == 'sbus':
+                self._bus_split_def = ("BASIL_SBUS",)
+            elif bus_split == 'top':
+                self._bus_split_def = ("BASIL_TOPSBUS",)
+
     def setUp(self):
-        cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimSpi.v')])
+        cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus, extra_defines=self._bus_split_def)
 
         self.chip = Dut(cnfg_yaml)
         self.chip.init()
diff --git a/tests/test_SimSpi.v b/tests/test_SimSpi.v
index faedb949..a21bbeff 100644
--- a/tests/test_SimSpi.v
+++ b/tests/test_SimSpi.v
@@ -7,37 +7,51 @@
 
 `timescale 1ps / 1ps
 
-
-`include "utils/bus_to_ip.v"
-`include "gpio/gpio_core.v"
-`include "gpio/gpio.v"
-
-`include "spi/spi.v"
-`include "spi/spi_core.v"
-`include "spi/blk_mem_gen_8_to_1_2k.v"
-
-`include "pulse_gen/pulse_gen.v"
-`include "pulse_gen/pulse_gen_core.v"
-
-`include "bram_fifo/bram_fifo_core.v"
-`include "bram_fifo/bram_fifo.v"
-
-`include "fast_spi_rx/fast_spi_rx.v"
-`include "fast_spi_rx/fast_spi_rx_core.v"
-
-`include "utils/cdc_syncfifo.v"
-`include "utils/generic_fifo.v"
-`include "utils/cdc_pulse_sync.v"
-`include "utils/CG_MOD_pos.v"
-`include "utils/clock_divider.v"
-`include "utils/3_stage_synchronizer.v"
-`include "utils/RAMB16_S1_S9_sim.v"
+`ifdef BASIL_SBUS
+    `define SPLIT_BUS
+`elsif BASIL_TOPSBUS
+    `define SPLIT_BUS
+`endif
+
+`ifndef BASIL_SBUS
+    `include "utils/bus_to_ip.v"
+    `include "gpio/gpio_core.v"
+    `include "gpio/gpio.v"
+
+    `include "spi/spi.v"
+    `include "spi/spi_core.v"
+    `include "spi/blk_mem_gen_8_to_1_2k.v"
+
+    `include "pulse_gen/pulse_gen.v"
+    `include "pulse_gen/pulse_gen_core.v"
+
+    `include "bram_fifo/bram_fifo_core.v"
+    `include "bram_fifo/bram_fifo.v"
+
+    `include "fast_spi_rx/fast_spi_rx.v"
+    `include "fast_spi_rx/fast_spi_rx_core.v"
+
+    `include "utils/cdc_syncfifo.v"
+    `include "utils/generic_fifo.v"
+    `include "utils/cdc_pulse_sync.v"
+    `include "utils/CG_MOD_pos.v"
+    `include "utils/clock_divider.v"
+    `include "utils/3_stage_synchronizer.v"
+    `include "utils/RAMB16_S1_S9_sim.v"
+`else
+    $fatal("Sbus modules not implemented yet");
+`endif
 
 module tb (
     input wire          BUS_CLK,
     input wire          BUS_RST,
     input wire  [31:0]  BUS_ADD,
-    inout wire  [31:0]  BUS_DATA,
+`ifndef SPLIT_BUS
+    inout wire  [31:0]   BUS_DATA,
+`else
+    input wire  [31:0]   BUS_DATA_IN,
+    output wire [31:0]   BUS_DATA_OUT,
+`endif
     input wire          BUS_RD,
     input wire          BUS_WR,
     output wire         BUS_BYTE_ACCESS
@@ -65,8 +79,28 @@ localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
 localparam ABUSWIDTH = 32;
 assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
 
+// BUS/SBUS //
+
+// Connect tb internal bus to external split bus
+`ifdef BASIL_TOPSBUS
+    wire [31:0] BUS_DATA;
+    assign BUS_DATA = BUS_DATA_IN;
+    assign BUS_DATA_OUT = BUS_DATA;
+`elsif BASIL_SBUS
+    wire [31:0] BUS_DATA_OUT_1;
+    wire [31:0] BUS_DATA_OUT_2;
+    wire [31:0] BUS_DATA_OUT_3;
+    wire [31:0] BUS_DATA_OUT_4;
+    wire [31:0] BUS_DATA_OUT_5;
+    assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2 | BUS_DATA_OUT_3 | BUS_DATA_OUT_4 | BUS_DATA_OUT_5;
+`endif
+
 // MODULES //
+`ifndef BASIL_SBUS
 gpio #(
+`else
+gpio_sbus #(
+`endif
     .BASEADDR(GPIO_BASEADDR),
     .HIGHADDR(GPIO_HIGHADDR),
     .ABUSWIDTH(ABUSWIDTH),
@@ -76,7 +110,12 @@ gpio #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA[7:0]),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN[7:0]),
+    .BUS_DATA_OUT(BUS_DATA_OUT_1[7:0]),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
     .IO()
@@ -84,7 +123,11 @@ gpio #(
 
 wire SPI_CLK;
 wire EX_START_PULSE;
+`ifndef BASIL_SBUS
 pulse_gen #(
+`else
+pulse_gen_sbus #(
+`endif
     .BASEADDR(PULSE_BASEADDR),
     .HIGHADDR(PULSE_HIGHADDR),
     .ABUSWIDTH(ABUSWIDTH)
@@ -92,7 +135,12 @@ pulse_gen #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA[7:0]),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN[7:0]),
+    .BUS_DATA_OUT(BUS_DATA_OUT_2[7:0]),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -112,7 +160,11 @@ clock_divider #(
 
 wire SCLK, SDI, SDO, SEN, SLD;
 
+`ifndef BASIL_SBUS
 spi #(
+`else
+spi_sbus #(
+`endif
     .BASEADDR(SPI_BASEADDR),
     .HIGHADDR(SPI_HIGHADDR),
     .ABUSWIDTH(ABUSWIDTH),
@@ -121,7 +173,12 @@ spi #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA[7:0]),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN[7:0]),
+    .BUS_DATA_OUT(BUS_DATA_OUT_3[7:0]),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -141,7 +198,11 @@ wire FIFO_READ_SPI_RX;
 wire FIFO_EMPTY_SPI_RX;
 wire [31:0] FIFO_DATA_SPI_RX;
 
+`ifndef BASIL_SBUS
 fast_spi_rx #(
+`else
+fast_spi_rx_sbus #(
+`endif
     .BASEADDR(FAST_SR_AQ_BASEADDR),
     .HIGHADDR(FAST_SR_AQ_HIGHADDR),
     .ABUSWIDTH(ABUSWIDTH)
@@ -149,7 +210,12 @@ fast_spi_rx #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA[7:0]),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN[7:0]),
+    .BUS_DATA_OUT(BUS_DATA_OUT_4[7:0]),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -168,7 +234,11 @@ assign FIFO_DATA = FIFO_DATA_SPI_RX;
 assign FIFO_EMPTY = FIFO_EMPTY_SPI_RX;
 assign FIFO_READ_SPI_RX = FIFO_READ;
 
+`ifndef BASIL_SBUS
 bram_fifo #(
+`else
+bram_fifo_sbus #(
+`endif
     .BASEADDR(FIFO_BASEADDR),
     .HIGHADDR(FIFO_HIGHADDR),
     .BASEADDR_DATA(FIFO_BASEADDR_DATA),
@@ -178,7 +248,12 @@ bram_fifo #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_5),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -192,9 +267,11 @@ bram_fifo #(
     .FIFO_READ_ERROR()
 );
 
+`ifndef VERILATOR_SIM
 initial begin
     $dumpfile("spi.vcd");
     $dumpvars(0);
 end
+`endif
 
 endmodule
diff --git a/tests/test_SimSpi_sbus.py b/tests/test_SimSpi_sbus.py
new file mode 100644
index 00000000..b6cd9a22
--- /dev/null
+++ b/tests/test_SimSpi_sbus.py
@@ -0,0 +1,28 @@
+#
+# ------------------------------------------------------------
+# Copyright (c) All rights reserved
+# SiLab, Institute of Physics, University of Bonn
+# ------------------------------------------------------------
+#
+
+import unittest
+import sys
+
+from tests.test_SimSpi import TestSimSpi
+
+
+if __name__ == '__main__':
+    # https://stackoverflow.com/a/2081750
+    test_loader = unittest.TestLoader()
+    test_names = test_loader.getTestCaseNames(TestSimSpi)
+
+    suite = unittest.TestSuite()
+
+# TODO: add sbus versions of used modules
+#    for test_name in test_names:
+#        suite.addTest(TestSimSpi(testname=test_name, tb='test_SimSpi.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='sbus'))
+    for test_name in test_names:
+        suite.addTest(TestSimSpi(testname=test_name, tb='test_SimSpi.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='top'))
+
+    result = unittest.TextTestRunner().run(suite)
+    sys.exit(not result.wasSuccessful())