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ism330dhcx_reg.h
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ism330dhcx_reg.h
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/**
******************************************************************************
* @file ism330dhcx_reg.h
* @author Sensor Solutions Software Team
* @brief This file contains all the functions prototypes for the
* ism330dhcx_reg.c driver.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef ISM330DHCX_REGS_H
#define ISM330DHCX_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
#include <stddef.h>
#include <math.h>
/** @addtogroup ISM330DHCX
* @{
*
*/
/** @defgroup Endianness definitions
* @{
*
*/
#ifndef DRV_BYTE_ORDER
#ifndef __BYTE_ORDER__
#define DRV_LITTLE_ENDIAN 1234
#define DRV_BIG_ENDIAN 4321
/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
* by uncommenting the define which fits your platform endianness
*/
/* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */
#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
#else /* defined __BYTE_ORDER__ */
#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
#define DRV_BYTE_ORDER __BYTE_ORDER__
#endif /* __BYTE_ORDER__*/
#endif /* DRV_BYTE_ORDER */
/**
* @}
*
*/
/** @defgroup STMicroelectronics sensors common types
* @{
*
*/
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
uint8_t bit3 : 1;
uint8_t bit4 : 1;
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t bit7 : 1;
uint8_t bit6 : 1;
uint8_t bit5 : 1;
uint8_t bit4 : 1;
uint8_t bit3 : 1;
uint8_t bit2 : 1;
uint8_t bit1 : 1;
uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
#define PROPERTY_ENABLE (1U)
/** @addtogroup Interfaces_Functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
* MANDATORY: return 0 -> no Error.
* @{
*
*/
typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t *, uint16_t);
typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
typedef void (*stmdev_mdelay_ptr)(uint32_t millisec);
typedef struct
{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
/** Component optional fields **/
stmdev_mdelay_ptr mdelay;
/** Customizable optional pointer **/
void *handle;
} stmdev_ctx_t;
/**
* @}
*
*/
#endif /* MEMS_SHARED_TYPES */
#ifndef MEMS_UCF_SHARED_TYPES
#define MEMS_UCF_SHARED_TYPES
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
* You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
* @{
*
*/
typedef struct
{
uint8_t address;
uint8_t data;
} ucf_line_t;
/**
* @}
*
*/
#endif /* MEMS_UCF_SHARED_TYPES */
/**
* @}
*
*/
/** @defgroup ISM330DHCX Infos
* @{
*
*/
/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/
#define ISM330DHCX_I2C_ADD_L 0xD5U
#define ISM330DHCX_I2C_ADD_H 0xD7U
/** Device Identification (Who am I) **/
#define ISM330DHCX_ID 0x6BU
/**
* @}
*
*/
#define ISM330DHCX_FUNC_CFG_ACCESS 0x01U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t reg_access :
2; /* shub_reg_access + func_cfg_access */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t reg_access :
2; /* shub_reg_access + func_cfg_access */
uint8_t not_used_01 : 6;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_func_cfg_access_t;
#define ISM330DHCX_PIN_CTRL 0x02U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 6;
uint8_t sdo_pu_en : 1;
uint8_t ois_pu_dis : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ois_pu_dis : 1;
uint8_t sdo_pu_en : 1;
uint8_t not_used_01 : 6;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_pin_ctrl_t;
#define ISM330DHCX_FIFO_CTRL1 0x07U
typedef struct
{
uint8_t wtm : 8;
} ism330dhcx_fifo_ctrl1_t;
#define ISM330DHCX_FIFO_CTRL2 0x08U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 1;
uint8_t uncoptr_rate : 2;
uint8_t not_used_01 : 1;
uint8_t odrchg_en : 1;
uint8_t not_used_02 : 1;
uint8_t fifo_compr_rt_en : 1;
uint8_t stop_on_wtm : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t stop_on_wtm : 1;
uint8_t fifo_compr_rt_en : 1;
uint8_t not_used_02 : 1;
uint8_t odrchg_en : 1;
uint8_t not_used_01 : 1;
uint8_t uncoptr_rate : 2;
uint8_t wtm : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_fifo_ctrl2_t;
#define ISM330DHCX_FIFO_CTRL3 0x09U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t bdr_gy : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t bdr_gy : 4;
uint8_t bdr_xl : 4;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_fifo_ctrl3_t;
#define ISM330DHCX_FIFO_CTRL4 0x0AU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used_01 : 1;
uint8_t odr_t_batch : 2;
uint8_t odr_ts_batch : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t odr_ts_batch : 2;
uint8_t odr_t_batch : 2;
uint8_t not_used_01 : 1;
uint8_t fifo_mode : 3;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_fifo_ctrl4_t;
#define ISM330DHCX_COUNTER_BDR_REG1 0x0BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 3;
uint8_t not_used_01 : 2;
uint8_t trig_counter_bdr : 1;
uint8_t rst_counter_bdr : 1;
uint8_t dataready_pulsed : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t dataready_pulsed : 1;
uint8_t rst_counter_bdr : 1;
uint8_t trig_counter_bdr : 1;
uint8_t not_used_01 : 2;
uint8_t cnt_bdr_th : 3;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_counter_bdr_reg1_t;
#define ISM330DHCX_COUNTER_BDR_REG2 0x0CU
typedef struct
{
uint8_t cnt_bdr_th : 8;
} ism330dhcx_counter_bdr_reg2_t;
#define ISM330DHCX_INT1_CTRL 0x0DU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_boot : 1;
uint8_t int1_fifo_th : 1;
uint8_t int1_fifo_ovr : 1;
uint8_t int1_fifo_full : 1;
uint8_t int1_cnt_bdr : 1;
uint8_t den_drdy_flag : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t den_drdy_flag : 1;
uint8_t int1_cnt_bdr : 1;
uint8_t int1_fifo_full : 1;
uint8_t int1_fifo_ovr : 1;
uint8_t int1_fifo_th : 1;
uint8_t int1_boot : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_drdy_xl : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_int1_ctrl_t;
#define ISM330DHCX_INT2_CTRL 0x0EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_temp : 1;
uint8_t int2_fifo_th : 1;
uint8_t int2_fifo_ovr : 1;
uint8_t int2_fifo_full : 1;
uint8_t int2_cnt_bdr : 1;
uint8_t not_used_01 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 1;
uint8_t int2_cnt_bdr : 1;
uint8_t int2_fifo_full : 1;
uint8_t int2_fifo_ovr : 1;
uint8_t int2_fifo_th : 1;
uint8_t int2_drdy_temp : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_xl : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_int2_ctrl_t;
#define ISM330DHCX_WHO_AM_I 0x0FU
#define ISM330DHCX_CTRL1_XL 0x10U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf2_xl_en : 1;
uint8_t fs_xl : 2;
uint8_t odr_xl : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t odr_xl : 4;
uint8_t fs_xl : 2;
uint8_t lpf2_xl_en : 1;
uint8_t not_used_01 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl1_xl_t;
#define ISM330DHCX_CTRL2_G 0x11U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */
uint8_t odr_g : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t odr_g : 4;
uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl2_g_t;
#define ISM330DHCX_CTRL3_C 0x12U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used_01 : 1;
uint8_t if_inc : 1;
uint8_t sim : 1;
uint8_t pp_od : 1;
uint8_t h_lactive : 1;
uint8_t bdu : 1;
uint8_t boot : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t boot : 1;
uint8_t bdu : 1;
uint8_t h_lactive : 1;
uint8_t pp_od : 1;
uint8_t sim : 1;
uint8_t if_inc : 1;
uint8_t not_used_01 : 1;
uint8_t sw_reset : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl3_c_t;
#define ISM330DHCX_CTRL4_C 0x13U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t lpf1_sel_g : 1;
uint8_t i2c_disable : 1;
uint8_t drdy_mask : 1;
uint8_t not_used_02 : 1;
uint8_t int2_on_int1 : 1;
uint8_t sleep_g : 1;
uint8_t not_used_03 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_03 : 1;
uint8_t sleep_g : 1;
uint8_t int2_on_int1 : 1;
uint8_t not_used_02 : 1;
uint8_t drdy_mask : 1;
uint8_t i2c_disable : 1;
uint8_t lpf1_sel_g : 1;
uint8_t not_used_01 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl4_c_t;
#define ISM330DHCX_CTRL5_C 0x14U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t not_used_01 : 1;
uint8_t rounding : 2;
uint8_t not_used_02 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_02 : 1;
uint8_t rounding : 2;
uint8_t not_used_01 : 1;
uint8_t st_g : 2;
uint8_t st_xl : 2;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl5_c_t;
#define ISM330DHCX_CTRL6_C 0x15U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ftype : 3;
uint8_t usr_off_w : 1;
uint8_t xl_hm_mode : 1;
uint8_t den_mode :
3; /* trig_en + lvl1_en + lvl2_en */
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t den_mode :
3; /* trig_en + lvl1_en + lvl2_en */
uint8_t xl_hm_mode : 1;
uint8_t usr_off_w : 1;
uint8_t ftype : 3;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl6_c_t;
#define ISM330DHCX_CTRL7_G 0x16U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ois_on : 1;
uint8_t usr_off_on_out : 1;
uint8_t ois_on_en : 1;
uint8_t not_used_01 : 1;
uint8_t hpm_g : 2;
uint8_t hp_en_g : 1;
uint8_t g_hm_mode : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t g_hm_mode : 1;
uint8_t hp_en_g : 1;
uint8_t hpm_g : 2;
uint8_t not_used_01 : 1;
uint8_t ois_on_en : 1;
uint8_t usr_off_on_out : 1;
uint8_t ois_on : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl7_g_t;
#define ISM330DHCX_CTRL8_XL 0x17U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t low_pass_on_6d : 1;
uint8_t not_used_01 : 1;
uint8_t hp_slope_xl_en : 1;
uint8_t fastsettl_mode_xl : 1;
uint8_t hp_ref_mode_xl : 1;
uint8_t hpcf_xl : 3;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t hpcf_xl : 3;
uint8_t hp_ref_mode_xl : 1;
uint8_t fastsettl_mode_xl : 1;
uint8_t hp_slope_xl_en : 1;
uint8_t not_used_01 : 1;
uint8_t low_pass_on_6d : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl8_xl_t;
#define ISM330DHCX_CTRL9_XL 0x18U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 1;
uint8_t device_conf : 1;
uint8_t den_lh : 1;
uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
uint8_t den_z : 1;
uint8_t den_y : 1;
uint8_t den_x : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t den_x : 1;
uint8_t den_y : 1;
uint8_t den_z : 1;
uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */
uint8_t den_lh : 1;
uint8_t device_conf : 1;
uint8_t not_used_01 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl9_xl_t;
#define ISM330DHCX_CTRL10_C 0x19U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 5;
uint8_t timestamp_en : 1;
uint8_t not_used_02 : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_02 : 2;
uint8_t timestamp_en : 1;
uint8_t not_used_01 : 5;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_ctrl10_c_t;
#define ISM330DHCX_ALL_INT_SRC 0x1AU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
uint8_t single_tap : 1;
uint8_t double_tap : 1;
uint8_t d6d_ia : 1;
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 1;
uint8_t timestamp_endcount : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t timestamp_endcount : 1;
uint8_t not_used_01 : 1;
uint8_t sleep_change_ia : 1;
uint8_t d6d_ia : 1;
uint8_t double_tap : 1;
uint8_t single_tap : 1;
uint8_t wu_ia : 1;
uint8_t ff_ia : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_all_int_src_t;
#define ISM330DHCX_WAKE_UP_SRC 0x1BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
uint8_t wu_ia : 1;
uint8_t sleep_state : 1;
uint8_t ff_ia : 1;
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 1;
uint8_t sleep_change_ia : 1;
uint8_t ff_ia : 1;
uint8_t sleep_state : 1;
uint8_t wu_ia : 1;
uint8_t x_wu : 1;
uint8_t y_wu : 1;
uint8_t z_wu : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_wake_up_src_t;
#define ISM330DHCX_TAP_SRC 0x1CU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
uint8_t tap_sign : 1;
uint8_t double_tap : 1;
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_01 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 1;
uint8_t tap_ia : 1;
uint8_t single_tap : 1;
uint8_t double_tap : 1;
uint8_t tap_sign : 1;
uint8_t x_tap : 1;
uint8_t y_tap : 1;
uint8_t z_tap : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_tap_src_t;
#define ISM330DHCX_D6D_SRC 0x1DU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
uint8_t yh : 1;
uint8_t zl : 1;
uint8_t zh : 1;
uint8_t d6d_ia : 1;
uint8_t den_drdy : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t den_drdy : 1;
uint8_t d6d_ia : 1;
uint8_t zh : 1;
uint8_t zl : 1;
uint8_t yh : 1;
uint8_t yl : 1;
uint8_t xh : 1;
uint8_t xl : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_d6d_src_t;
#define ISM330DHCX_STATUS_REG 0x1EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t not_used_01 : 5;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 5;
uint8_t tda : 1;
uint8_t gda : 1;
uint8_t xlda : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_status_reg_t;
#define ISM330DHCX_STATUS_SPIAUX 0x1EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t gyro_settling : 1;
uint8_t not_used_01 : 5;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 5;
uint8_t gyro_settling : 1;
uint8_t gda : 1;
uint8_t xlda : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_status_spiaux_t;
#define ISM330DHCX_OUT_TEMP_L 0x20U
#define ISM330DHCX_OUT_TEMP_H 0x21U
#define ISM330DHCX_OUTX_L_G 0x22U
#define ISM330DHCX_OUTX_H_G 0x23U
#define ISM330DHCX_OUTY_L_G 0x24U
#define ISM330DHCX_OUTY_H_G 0x25U
#define ISM330DHCX_OUTZ_L_G 0x26U
#define ISM330DHCX_OUTZ_H_G 0x27U
#define ISM330DHCX_OUTX_L_A 0x28U
#define ISM330DHCX_OUTX_H_A 0x29U
#define ISM330DHCX_OUTY_L_A 0x2AU
#define ISM330DHCX_OUTY_H_A 0x2BU
#define ISM330DHCX_OUTZ_L_A 0x2CU
#define ISM330DHCX_OUTZ_H_A 0x2DU
#define ISM330DHCX_EMB_FUNC_STATUS_MAINPAGE 0x35U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;
uint8_t is_sigmot : 1;
uint8_t not_used_02 : 1;
uint8_t is_fsm_lc : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t is_fsm_lc : 1;
uint8_t not_used_02 : 1;
uint8_t is_sigmot : 1;
uint8_t is_tilt : 1;
uint8_t is_step_det : 1;
uint8_t not_used_01 : 3;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_emb_func_status_mainpage_t;
#define ISM330DHCX_FSM_STATUS_A_MAINPAGE 0x36U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm1 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm3 : 1;
uint8_t is_fsm4 : 1;
uint8_t is_fsm5 : 1;
uint8_t is_fsm6 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm8 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t is_fsm8 : 1;
uint8_t is_fsm7 : 1;
uint8_t is_fsm6 : 1;
uint8_t is_fsm5 : 1;
uint8_t is_fsm4 : 1;
uint8_t is_fsm3 : 1;
uint8_t is_fsm2 : 1;
uint8_t is_fsm1 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_fsm_status_a_mainpage_t;
#define ISM330DHCX_FSM_STATUS_B_MAINPAGE 0x37U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_fsm9 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm11 : 1;
uint8_t is_fsm12 : 1;
uint8_t is_fsm13 : 1;
uint8_t is_fsm14 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm16 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t is_fsm16 : 1;
uint8_t is_fsm15 : 1;
uint8_t is_fsm14 : 1;
uint8_t is_fsm13 : 1;
uint8_t is_fsm12 : 1;
uint8_t is_fsm11 : 1;
uint8_t is_fsm10 : 1;
uint8_t is_fsm9 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_fsm_status_b_mainpage_t;
#define ISM330DHCX_MLC_STATUS_MAINPAGE 0x38U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t is_mlc1 : 1;
uint8_t is_mlc2 : 1;
uint8_t is_mlc3 : 1;
uint8_t is_mlc4 : 1;
uint8_t is_mlc5 : 1;
uint8_t is_mlc6 : 1;
uint8_t is_mlc7 : 1;
uint8_t is_mlc8 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t is_mlc8 : 1;
uint8_t is_mlc7 : 1;
uint8_t is_mlc6 : 1;
uint8_t is_mlc5 : 1;
uint8_t is_mlc4 : 1;
uint8_t is_mlc3 : 1;
uint8_t is_mlc2 : 1;
uint8_t is_mlc1 : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_mlc_status_mainpage_t;
#define ISM330DHCX_STATUS_MASTER_MAINPAGE 0x39U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sens_hub_endop : 1;
uint8_t not_used_01 : 2;
uint8_t slave0_nack : 1;
uint8_t slave1_nack : 1;
uint8_t slave2_nack : 1;
uint8_t slave3_nack : 1;
uint8_t wr_once_done : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t wr_once_done : 1;
uint8_t slave3_nack : 1;
uint8_t slave2_nack : 1;
uint8_t slave1_nack : 1;
uint8_t slave0_nack : 1;
uint8_t not_used_01 : 2;
uint8_t sens_hub_endop : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_status_master_mainpage_t;
#define ISM330DHCX_FIFO_STATUS1 0x3AU
typedef struct
{
uint8_t diff_fifo : 8;
} ism330dhcx_fifo_status1_t;
#define ISM330DHCX_FIFO_STATUS2 0x3BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 2;
uint8_t not_used_01 : 1;
uint8_t over_run_latched : 1;
uint8_t counter_bdr_ia : 1;
uint8_t fifo_full_ia : 1;
uint8_t fifo_ovr_ia : 1;
uint8_t fifo_wtm_ia : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_wtm_ia : 1;
uint8_t fifo_ovr_ia : 1;
uint8_t fifo_full_ia : 1;
uint8_t counter_bdr_ia : 1;
uint8_t over_run_latched : 1;
uint8_t not_used_01 : 1;
uint8_t diff_fifo : 2;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_fifo_status2_t;
#define ISM330DHCX_TIMESTAMP0 0x40U
#define ISM330DHCX_TIMESTAMP1 0x41U
#define ISM330DHCX_TIMESTAMP2 0x42U
#define ISM330DHCX_TIMESTAMP3 0x43U
#define ISM330DHCX_TAP_CFG0 0x56U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lir : 1;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
uint8_t tap_x_en : 1;
uint8_t slope_fds : 1;
uint8_t sleep_status_on_int : 1;
uint8_t int_clr_on_read : 1;
uint8_t not_used_01 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 1;
uint8_t int_clr_on_read : 1;
uint8_t sleep_status_on_int : 1;
uint8_t slope_fds : 1;
uint8_t tap_x_en : 1;
uint8_t tap_y_en : 1;
uint8_t tap_z_en : 1;
uint8_t lir : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_tap_cfg0_t;
#define ISM330DHCX_TAP_CFG1 0x57U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_x : 5;
uint8_t tap_priority : 3;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t tap_priority : 3;
uint8_t tap_ths_x : 5;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_tap_cfg1_t;
#define ISM330DHCX_TAP_CFG2 0x58U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_y : 5;
uint8_t inact_en : 2;
uint8_t interrupts_enable : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t interrupts_enable : 1;
uint8_t inact_en : 2;
uint8_t tap_ths_y : 5;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_tap_cfg2_t;
#define ISM330DHCX_TAP_THS_6D 0x59U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_ths_z : 5;
uint8_t sixd_ths : 2;
uint8_t d4d_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t d4d_en : 1;
uint8_t sixd_ths : 2;
uint8_t tap_ths_z : 5;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_tap_ths_6d_t;
#define ISM330DHCX_INT_DUR2 0x5AU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t dur : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t dur : 4;
uint8_t quiet : 2;
uint8_t shock : 2;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_int_dur2_t;
#define ISM330DHCX_WAKE_UP_THS 0x5BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t usr_off_on_wu : 1;
uint8_t single_double_tap : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t single_double_tap : 1;
uint8_t usr_off_on_wu : 1;
uint8_t wk_ths : 6;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_wake_up_ths_t;
#define ISM330DHCX_WAKE_UP_DUR 0x5CU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t wake_ths_w : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ff_dur : 1;
uint8_t wake_dur : 2;
uint8_t wake_ths_w : 1;
uint8_t sleep_dur : 4;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_wake_up_dur_t;
#define ISM330DHCX_FREE_FALL 0x5DU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ff_dur : 5;
uint8_t ff_ths : 3;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_free_fall_t;
#define ISM330DHCX_MD1_CFG 0x5EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_shub : 1;
uint8_t int1_emb_func : 1;
uint8_t int1_6d : 1;
uint8_t int1_double_tap : 1;
uint8_t int1_ff : 1;
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_sleep_change : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t int1_sleep_change : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_wu : 1;
uint8_t int1_ff : 1;
uint8_t int1_double_tap : 1;
uint8_t int1_6d : 1;
uint8_t int1_emb_func : 1;
uint8_t int1_shub : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_md1_cfg_t;
#define ISM330DHCX_MD2_CFG 0x5FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_timestamp : 1;
uint8_t int2_emb_func : 1;
uint8_t int2_6d : 1;
uint8_t int2_double_tap : 1;
uint8_t int2_ff : 1;
uint8_t int2_wu : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_sleep_change : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t int2_sleep_change : 1;
uint8_t int2_single_tap : 1;
uint8_t int2_wu : 1;
uint8_t int2_ff : 1;
uint8_t int2_double_tap : 1;
uint8_t int2_6d : 1;
uint8_t int2_emb_func : 1;
uint8_t int2_timestamp : 1;
#endif /* DRV_BYTE_ORDER */
} ism330dhcx_md2_cfg_t;
#define ISM330DHCX_INTERNAL_FREQ_FINE 0x63U
typedef struct
{
uint8_t freq_fine : 8;
} ism330dhcx_internal_freq_fine_t;
#define ISM330DHCX_INT_OIS 0x6FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl_ois : 2;
uint8_t not_used_01 : 3;
uint8_t den_lh_ois : 1;
uint8_t lvl2_ois : 1;
uint8_t int2_drdy_ois : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN