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hstructs.h
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/* HSTRUCTS.H (C) Copyright Roger Bowler, 1999-2012 */
/* (C) Copyright TurboHercules, SAS 2011 */
/* Hercules Structure Definitions */
/* */
/* Released under "The Q Public License Version 1" */
/* (http://www.hercules-390.org/herclic.html) as modifications to */
/* Hercules. */
// This header auto-#included by 'hercules.h'...
//
// The <config.h> header and other required headers are
// presumed to have already been #included ahead of it...
#ifndef _HSTRUCTS_H
#define _HSTRUCTS_H
#include "hercules.h"
#include "opcode.h"
#include "telnet.h" // Need telnet_t
#include "stfl.h" // Need STFL_HERC_BY_SIZE
#include "cckd.h" // Need CCKD structs
#include "transact.h" // Need Transactional Execution Facility
/*-------------------------------------------------------------------*/
/* Typedefs for CPU bitmap fields */
/*-------------------------------------------------------------------*/
/* A CPU bitmap contains one bit for each processing engine. The */
/* width of the bitmap depends on the maximum number of processing */
/* engines that was selected at build time. */
/* */
/* Due to GCC and MSVC limitations, a 'MAX_CPU_ENGS' value greater */
/* than 64 (e.g. 128) is only supported on platforms whose long long */
/* integer size is actually 128 bits: */
/* */
/* "As an extension the integer scalar type __int128 is supported */
/* for targets which have an integer mode wide enough to hold 128 */
/* bits. ... There is no support in GCC for expressing an integer */
/* constant of type __int128 for targets with long long integer */
/* less than 128 bits wide." */
/*-------------------------------------------------------------------*/
#if MAX_CPU_ENGS <= 0
#error MAX_CPU_ENGS must be greater than zero!
#elif MAX_CPU_ENGS <= 32
typedef U32 CPU_BITMAP;
#define F_CPU_BITMAP "%8.8"PRIX32
#elif MAX_CPU_ENGS <= 64
typedef U64 CPU_BITMAP;
#define F_CPU_BITMAP "%16.16"PRIX64
#elif MAX_CPU_ENGS <= 128
typedef __uint128_t CPU_BITMAP;
// ZZ FIXME: No printf format support for __uint128_t yet, so we will incorrectly display...
#define SUPPRESS_128BIT_PRINTF_FORMAT_WARNING
#define F_CPU_BITMAP "%16.16"PRIX64
#else
#error MAX_CPU_ENGS cannot exceed 128
#endif
/*-------------------------------------------------------------------*/
/* Structure definition for CPU register context */
/*-------------------------------------------------------------------*/
/* */
/* Note: REGS is very susceptable to performance problems due to */
/* key fields either crossing or split across cache line */
/* boundaries. In addition, if allocated in the stack, the */
/* allocation unit is frequently on an 8-byte boundary rather */
/* than on a cache-line boundary. Consequently, extreme */
/* attention is paid to the cache line boundaries in the REGS */
/* structure to ensure that fields don't cross 64-byte */
/* boundaries and as much attention as possible to ensure */
/* 32-byte boundaries are not crossed. */
/* */
/*-------------------------------------------------------------------*/
struct REGS { /* Processor registers */
#define HDL_NAME_REGS "REGS" /* Eye-Catch NAME */
#define HDL_VERS_REGS "SDL 4.00" /* Internal Version Number */
#define HDL_SIZE_REGS sizeof(REGS)
/*000*/ BLOCK_HEADER; /* Name of block REGS_CP00 */
/*030*/ U64 cpuid; /* Formatted CPU ID */
/*038*/ U32 cpuserial; /* CPU serial number */
/*03C*/ U16 cpumodel; /* CPU model number */
/*03E*/ U8 cpuversion; /* CPU version code */
/*03F*/ U8 _cpu_reserved; /* Reserved for future use */
/* --- 64-byte cache line -- */
/*040*/ SYSBLK *sysblk; /* Pointer to sysblk */
ALIGN_8
/*048*/ U32 ints_state; /* CPU Interrupts Status */
/*04C*/ U32 ints_mask; /* Respective Interrupts Mask*/
/*050*/ CPU_BITMAP cpubit; /* Only this CPU's bit is 1 */
ALIGN_16
/*060*/ BYTE cpustate; /* CPU stopped/started state */
/*061*/ BYTE _cpu_reserved2; /* Available... */
/*062*/ U16 extccpu; /* CPU causing external call */
/*064*/ int arch_mode; /* Architectural mode */
/*068*/ BYTE *ip; /* Mainstor inst address */
/*070*/ DW px; /* Prefix register */
/* --- 64-byte cache line -- */
/*080*/ PSW psw; /* Program status word */
/*0E8-0FF*/ /* Available... */
ALIGN_128 /* --- 64-byte cache line -- */
/*100*/ BYTE malfcpu /* Malfuction alert flags */
[ MAX_CPU_ENGS ]; /* for each CPU (1=pending) */
ALIGN_128
/*180*/ BYTE emercpu /* Emergency signal flags */
[ MAX_CPU_ENGS ]; /* for each CPU (1=pending) */
/* AIA - Instruction fetch accelerator */
/*200*/ ALIGN_128
BYTE *aip; /* Mainstor page address */
uintptr_t unused; /* Available */
/*210*/ ALIGN_8
BYTE *aie; /* Mainstor page end address */
/*218*/ DW aiv; /* Virtual page address */
/*220*/ U64 bear; /* Breaking event address reg*/
/*228*/ U64 bear_ex; /* (same, but for EX/EXRL) */
/*230-27F*/ /* Available... */
/*280*/ ALIGN_128
DW gr[16]; /* General registers */
/*300*/ U32 ar[16]; /* Access registers */
/*340*/ U32 fpr[32]; /* Floating point registers */
/*380*/ U32 fpc; /* IEEE Floating Point
Control Register */
/*384*/ BYTE __reserved_space[52]; /* Available... */
#define CR_ASD_REAL -1
#define CR_ALB_OFFSET 16
/*3B8*/ DW cr_struct[1+16+16];
#define XR(_crn) cr_struct[1+(_crn)]
/*4C0*/ U32 dxc; /* Data exception code */
/*4C4*/ /* Available... */
/*4C8*/ DW mc; /* Monitor Code */
/*4D0*/ DW ea; /* Exception address */
/*4D8*/ DW et; /* Execute Target address */
unsigned int /* Flags (cpu thread only) */
execflag:1, /* 1=EXecuted instruction */
exrl:1, /* 1=EXRL, 0=EX instruction */
permode:1, /* 1=PER active */
instinvalid:1, /* 1=Inst field is invalid */
opinterv:1, /* 1=Operator intervening */
checkstop:1, /* 1=CPU is checkstop-ed */
hostint:1, /* 1=Host generated interrupt*/
host:1, /* REGS are hostregs */
guest:1, /* REGS are guestregs */
diagnose:1; /* Diagnose instr executing */
unsigned int /* Flags (intlock serialized)*/
dummy:1, /* 1=Dummy regs structure */
configured:1, /* 1=CPU is online */
loadstate:1, /* 1=CPU is in load state */
ghostregs:1, /* 1=Ghost registers (panel) */
invalidate:1, /* 1=Do AIA/AEA invalidation */
breakortrace:1, /* 1=Inst break/trace active */
stepping:1, /* 1=Inst stepping is active */
stepwait:1, /* 1=Wait in inst stepping */
sigp_reset:1, /* 1=SIGP cpu reset received */
sigp_ini_reset:1; /* 1=SIGP initial cpu reset */
CACHE_ALIGN /* --- 64-byte cache line -- */
S64 tod_epoch; /* TOD epoch for this CPU */
TOD clkc; /* 0-7=Clock comparator epoch,
8-63=Comparator bits 0-55 */
S64 cpu_timer; /* CPU timer */
U32 todpr; /* TOD programmable register */
S64 int_timer; /* S/370 Interval timer */
S64 ecps_vtimer; /* ECPS Virtual Int. timer */
S32 old_timer; /* S/370 Interval timer int */
S32 ecps_oldtmr; /* ECPS Virtual Int. tmr int */
/* --- 64-byte cache line -- */
BYTE *ecps_vtmrpt; /* Pointer to VTMR or zero */
U64 rcputime; /* Real CPU time used (us) */
U64 bcputime; /* Base (reset) CPU time (us)*/
U64 prevcount; /* Previous instruction count*/
U32 instcount; /* Instruction counter */
U32 mipsrate; /* Instructions per second */
U32 siocount; /* SIO/SSCH counter */
U32 siosrate; /* IOs per second */
U64 siototal; /* Total SIO/SSCH count */
/* --- 64-byte cache line -- */
int cpupct; /* Percent CPU busy */
U64 waittod; /* Time of day last wait */
U64 waittime; /* Wait time in interval */
U64 waittime_accumulated; /* Wait time accumulated */
CACHE_ALIGN /* --- 64-byte cache line -- */
DAT dat; /* Fields for DAT use */
#define GR_G(_r) gr[(_r)].D
#define GR_H(_r) gr[(_r)].F.H.F /* Fullword bits 0-31 */
#define GR_HHH(_r) gr[(_r)].F.H.H.H.H /* Halfword bits 0-15 */
#define GR_HHL(_r) gr[(_r)].F.H.H.L.H /* Halfword low, bits 16-31 */
#define GR_HHLCL(_r) gr[(_r)].F.H.H.L.B.L /* Character, bits 24-31 */
#define GR_L(_r) gr[(_r)].F.L.F /* Fullword low, bits 32-63 */
#define GR_LHH(_r) gr[(_r)].F.L.H.H.H /* Halfword bits 32-47 */
#define GR_LHL(_r) gr[(_r)].F.L.H.L.H /* Halfword low, bits 48-63 */
#define GR_LHHCH(_r) gr[(_r)].F.L.H.H.B.H /* Character, bits 32-39 */
#define GR_LA24(_r) gr[(_r)].F.L.A.A /* 24 bit addr, bits 40-63 */
#define GR_LA8(_r) gr[(_r)].F.L.A.B /* 24 bit addr, unused bits */
#define GR_LHLCL(_r) gr[(_r)].F.L.H.L.B.L /* Character, bits 56-63 */
#define GR_LHLCH(_r) gr[(_r)].F.L.H.L.B.H /* Character, bits 48-55 */
#define CR_G(_r) XR((_r)).D /* Bits 0-63 */
#define CR_H(_r) XR((_r)).F.H.F /* Fullword bits 0-31 */
#define CR_HHH(_r) XR((_r)).F.H.H.H.H /* Halfword bits 0-15 */
#define CR_HHL(_r) XR((_r)).F.H.H.L.H /* Halfword low, bits 16-31 */
#define CR_L(_r) XR((_r)).F.L.F /* Fullword low, bits 32-63 */
#define CR_LHH(_r) XR((_r)).F.L.H.H.H /* Halfword bits 32-47 */
#define CR_LHHCH(_r) XR((_r)).F.L.H.H.B.H /* Character, bits 32-39 */
#define CR_LHL(_r) XR((_r)).F.L.H.L.H /* Halfword low, bits 48-63 */
#define MC_G mc.D
#define MC_L mc.F.L.F
#define EA_G ea.D
#define EA_L ea.F.L.F
#define ET_G et.D
#define ET_L et.F.L.F
#define PX_G px.D
#define PX_L px.F.L.F
#define AIV_G aiv.D
#define AIV_L aiv.F.L.F
#define AR(_r) ar[(_r)]
U16 chanset; /* Connected channel set */
U16 monclass; /* Monitor event class */
U16 cpuad; /* CPU address for STAP */
BYTE excarid; /* Exception access register */
BYTE opndrid; /* Operand access register */
BYTE exinst[8]; /* Target of Execute (EX) */
BYTE *mainstor; /* -> Main storage */
BYTE *storkeys; /* -> Main storage key array */
RADR mainlim; /* Central Storage limit or */
/* guest storage limit (SIE) */
union
{
PSA_3XX *psa; /* -> PSA for this CPU 370 and ESA */
PSA_900 *zpsa; /* -> PSA for this CPU when in z arch */
};
/*---------------------------------------------------------------*/
/* PROGRAMMING NOTE */
/*---------------------------------------------------------------*/
/* The fields 'hostregs' and 'guestregs' have been moved outside */
/* the scope of _FEATURE_SIE to reduce conditional code. */
/* */
/* 'sysblk.regs[i]' ALWAYS points to the host regs */
/* */
/* 'hostregs' ALWAYS = sysblk.regs[i] */
/* in BOTH host regs and guest regs */
/* */
/* 'guestregs' ALWAYS = sysblk.regs[i]->guestregs */
/* in BOTH host regs and guest regs, */
/* but will be NULL until the first SIE */
/* instruction is executed on that CPU. */
/* */
/* 'host' ALWAYS 1 in host regs ONLY */
/* 'sie_active' ALWAYS 1 in host regs ONLY whenever */
/* the SIE instruction is executing. */
/* */
/* 'guest' ALWAYS 1 in guest regs ONLY */
/* 'sie_mode' ALWAYS 1 in guest regs ONLY */
/* */
/* 'sie_state' host real address of the SIEBK */
/* 'siebk' mainstor address of the SIEBK */
/* */
/*---------------------------------------------------------------*/
REGS *hostregs; /* Pointer to the hypervisor
register context */
REGS *guestregs; /* Pointer to the guest
register context */
#if defined(_FEATURE_SIE)
CACHE_ALIGN /* --- 64-byte cache line -- */
RADR sie_state; /* Address of the SIE state
descriptor block or 0 when
not running under SIE */
SIEBK *siebk; /* SIE State Desc structure */
RADR sie_px; /* Host address of guest px */
RADR sie_mso; /* Main Storage Origin */
RADR sie_xso; /* eXpanded Storage Origin */
RADR sie_xsl; /* eXpanded Storage Limit */
RADR sie_rcpo; /* Ref and Change Preserv. */
RADR sie_scao; /* System Contol Area */
S64 sie_epoch; /* TOD offset in state desc. */
#endif
unsigned int
sie_active:1, /* SIE active (host only) */
sie_mode:1, /* In SIE mode (guest only) */
sie_pref:1; /* Preferred-storage mode */
// #if defined(FEATURE_PER)
ALIGN_16
U16 perc; /* PER code */
RADR peradr; /* PER address */
BYTE peraid; /* PER access id */
// #endif /*defined(FEATURE_PER)*/
/*
* Making the following flags 'stand-alone' (instead of bit-
* flags like they were) addresses a compiler bit-flag serial-
* ization issue that occurs with the 'SYNCHRONIZE_CPUS' macro
* used during synchronize broadcast (cpu<->cpu communication)
*/
ALIGN_8
bool intwait; /* true = Waiting on intlock */
BYTE inst[8]; /* Fetched instruction when
instruction crosses a page
boundary */
BYTE *invalidate_main; /* Mainstor addr to invalidat*/
CACHE_ALIGN /* --- 64-byte cache line -- */
PSW captured_zpsw; /* Captured-z/Arch PSW reg */
#if defined( _FEATURE_S370_S390_VECTOR_FACILITY )
CACHE_ALIGN
VFREGS *vf; /* Vector Facility */
#endif
CACHE_ALIGN
jmp_buf progjmp; /* longjmp destination for
program check return */
jmp_buf archjmp; /* longjmp destination to
switch architecture mode */
jmp_buf exitjmp; /* longjmp destination for
CPU thread exit */
COND intcond; /* CPU interrupt condition */
LOCK *cpulock; /* CPU lock for this CPU */
/* Mainstor address lookup accelerator */
BYTE aea_mode; /* aea addressing mode */
int aea_ar_struct[5+16];
#define AEA_AR(_arn) aea_ar_struct[5+(_arn)]
BYTE aea_common_struct[1+16+16];
#define AEA_COMMON(_asd) aea_common_struct[1+(_asd)]
BYTE aea_aleprot[16]; /* ale protected */
/* Function pointers */
pi_func program_interrupt;
/* Active Facility List */
BYTE facility_list[ STFL_HERC_BY_SIZE ];
#if defined( _FEATURE_073_TRANSACT_EXEC_FACILITY )
/*---------------------------------------------------------------*/
/* Transactional-Execution Facility control fields */
/*---------------------------------------------------------------*/
TDB txf_tdb; /* Internal TDB */
bool txf_NTSTG; /* true == NTSTG instruction */
bool txf_contran; /* true == CONSTRAINED mode */
bool txf_UPGM_abort; /* true == transaction was
aborted due to TAC_UPGM */
int txf_aborts; /* Abort count */
BYTE txf_tnd; /* Transaction nesting depth.
Use txf_lock to access! */
BYTE txf_ctlflag; /* Flags for access mode
change, float allowed */
#define TXF_CTL_AR 0x08 /* AR reg changes allowed
in transaction mode */
#define TXF_CTL_FLOAT 0x04 /* Float and vector allowed
in transaction mode */
#define TXF_CTL_PIFC 0x03 /* PROG 'rupt filtering ctl. */
U16 txf_higharchange; /* Highest level that
AR change is active */
U16 txf_highfloat; /* Highest level that
float is active */
U16 txf_instctr; /* Instruction counter for
contran and auto abort*/
U16 txf_abortctr; /* If non-zero, abort when
txf_instctr >= this value */
U16 txf_pifc; /* Program-Interruption
Filtering Control (PIFC) */
#define TXF_PIFC_NONE 0 /* Exception conditions having
classes 1, 2 or 3 always
result in an interruption */
#define TXF_PIFC_LIMITED 1 /* Exception conditions having
classes 1 or 2 result in an
interruption; conditions
having class 3 do not result
in an interruption. */
#define TXF_PIFC_MODERATE 2 /* Only exception conditions
having class 1 result in an
interruption; conditions
having classes 2 or 3 do not
result in an interruption */
#define TXF_PIFC_RESERVED 3 /* Reserved (invalid) */
U64 txf_tdba; /* TBEGIN TDB address */
int txf_tdba_b1; /* TBEGIN op1 base address */
U64 txf_conflict; /* Logical address where
conflict was detected */
TPAGEMAP txf_pagesmap[ MAX_TXF_PAGES ]; /* Page addresses */
int txf_pgcnt; /* Entries in TPAGEMAP table */
BYTE txf_gprmask; /* GPR register restore mask */
DW txf_savedgr[16]; /* Saved gpr register values */
int txf_tac; /* Transaction abort code.
Use txf_lock to access! */
int txf_random_tac; /* Random abort code */
/* --------------- TXF debugging --------------------------- */
int txf_who; /* CPU doing delayed abort */
const char* txf_loc; /* Where the abort occurred */
/*-----------------------------------------------------------*/
/* Transaction Abort PSW fields */
PSW txf_tapsw; /* Transaction abort PSW */
BYTE* txf_ip; /* AIA Mainstor inst address */
BYTE* txf_aip; /* AIA Mainstor page address */
uintptr_t txf_aim; /* AIA Mainstor xor address */
DW txf_aiv; /* AIA Virtual page address */
/*-----------------------------------------------------------*/
/* CONSTRAINED transaction instruction fetching constraint */
BYTE* txf_aie; /* Maximum trans ip address */
U64 txf_aie_aiv; /* Virtual page address */
U64 txf_aie_aiv2; /* 2nd page if trans crosses */
int txf_aie_off2; /* Offset into 2nd page */
/*-----------------------------------------------------------*/
U32 txf_piid; /* Transaction Program
Interrupt Identifier */
BYTE txf_dxc_vxc; /* Data/Vector Exception Code*/
U32 txf_why; /* why transaction aborted */
/* see transact.h for codes */
int txf_lastarn; /* Last access arn */
U16 txf_pifctab[ MAX_TXF_TND ]; /* PIFC control table */
#endif /* defined( _FEATURE_073_TRANSACT_EXEC_FACILITY ) */
/* ------------------------------------------------------------ */
U64 regs_copy_end; /* Copy regs to here */
/* ------------------------------------------------------------ */
/* Runtime opcode tables. Use 'replace_opcode' to modify */
const INSTR_FUNC *s370_runtime_opcode_xxxx,
*s370_runtime_opcode_e3________xx,
*s370_runtime_opcode_eb________xx,
*s370_runtime_opcode_ec________xx,
*s370_runtime_opcode_ed________xx;
const INSTR_FUNC *s390_runtime_opcode_xxxx,
*s390_runtime_opcode_e3________xx,
*s390_runtime_opcode_eb________xx,
*s390_runtime_opcode_ec________xx,
*s390_runtime_opcode_ed________xx;
const INSTR_FUNC *z900_runtime_opcode_xxxx,
*z900_runtime_opcode_e3________xx,
*z900_runtime_opcode_eb________xx,
*z900_runtime_opcode_ec________xx,
*z900_runtime_opcode_ed________xx;
#if !defined( OPTION_NO_E3_OPTINST )
const INSTR_FUNC *s370_runtime_opcode_e3_0______xx,
*s390_runtime_opcode_e3_0______xx,
*z900_runtime_opcode_e3_0______xx;
#endif
/* TLB - Translation lookaside buffer */
unsigned int tlbID; /* Validation identifier */
TLB tlb; /* Translation lookaside buf */
BLOCK_TRAILER; /* Name of block END */
};
// end REGS
/*-------------------------------------------------------------------*/
/* Structure definition for the Vector Facility */
/*-------------------------------------------------------------------*/
#if defined( _FEATURE_S370_S390_VECTOR_FACILITY )
struct VFREGS { /* Vector Facility Registers*/
unsigned int
online:1; /* 1=VF is online */
U64 vsr; /* Vector Status Register */
U64 vac; /* Vector Activity Count */
BYTE vmr[VECTOR_SECTION_SIZE/8]; /* Vector Mask Register */
U32 vr[16][VECTOR_SECTION_SIZE]; /* Vector Registers */
};
#endif /* defined( _FEATURE_S370_S390_VECTOR_FACILITY ) */
// #if defined(FEATURE_REGION_RELOCATE)
/*-------------------------------------------------------------------*/
/* Zone Parameter Block */
/*-------------------------------------------------------------------*/
struct ZPBLK {
RADR mso; /* Main Storage Origin */
RADR msl; /* Main Storage Length */
RADR eso; /* Expanded Storage Origin */
RADR esl; /* Expanded Storage Length */
RADR mbo; /* Measurement block origin */
BYTE mbk; /* Measurement block key */
int mbm; /* Measurement block mode */
int mbd; /* Device connect time mode */
};
// #endif /*defined(FEATURE_REGION_RELOCATE)*/
/*-------------------------------------------------------------------*/
/* Guest System Information block EBCDIC DATA */
/*-------------------------------------------------------------------*/
struct GSYSINFO {
BYTE loadparm[8];
BYTE lparname[8];
BYTE manufact[16];
BYTE plant[4];
BYTE model[16];
BYTE modelcapa[16];
BYTE modelperm[16];
BYTE modeltemp[16];
BYTE systype[8];
BYTE sysname[8];
BYTE sysplex[8];
BYTE cpid[16];
BYTE vmid[8];
};
/*-------------------------------------------------------------------*/
/* Operation Modes */
/*-------------------------------------------------------------------*/
enum OPERATION_MODE
{
om_basic = 0, /* lparmode = 0 */
om_mif = 1, /* lparmode = 1; cpuidfmt = 0; partitions 1-16 */
om_emif = 2 /* lparmode = 1; cpuidfmt = 1; partitions 0-255 */
};
/*-------------------------------------------------------------------*/
/* System configuration block */
/*-------------------------------------------------------------------*/
struct SYSBLK {
#define HDL_NAME_SYSBLK "SYSBLK"
#define HDL_VERS_SYSBLK "SDL 4.2" /* Internal Version Number */
#define HDL_SIZE_SYSBLK sizeof(SYSBLK)
BLOCK_HEADER; /* Name of block - SYSBLK */
char *hercules_pgmname; /* Starting program name */
char *hercules_pgmpath; /* Starting pgm path name */
char *hercules_cmdline; /* Hercules Command line */
char *netdev; /* Network device name */
#define DEF_NETDEV init_sysblk_netdev() /* Retrieve sysblk.netdev */
const char **vers_info; /* Version information */
const char **bld_opts; /* Build options */
const char **extpkg_vers; /* External Package versions */
pid_t hercules_pid; /* Process Id of Hercules */
time_t impltime; /* TOD system was IMPL'ed */
LOCK bindlock; /* Sockdev bind lock */
LOCK config; /* (Re)Configuration Lock */
int arch_mode; /* Architecturual mode */
/* 0 == S/370 (ARCH_370_IDX) */
/* 1 == ESA/390 (ARCH_390_IDX) */
/* 2 == ESAME (ARCH_900_IDX) */
RADR mainsize; /* Main storage size (bytes) */
BYTE *mainstor; /* -> Main storage */
BYTE *storkeys; /* -> Main storage key array */
u_int lock_mainstor:1; /* Request mainstor to lock */
u_int mainstor_locked:1; /* Main storage locked */
U32 xpndsize; /* Expanded size in 4K pages */
BYTE *xpndstor; /* -> Expanded storage */
u_int lock_xpndstor:1; /* Request xpndstor to lock */
u_int xpndstor_locked:1; /* Expanded storage locked */
U64 todstart; /* Time of initialisation */
U64 cpuid; /* CPU identifier for STIDP */
U32 cpuserial; /* CPU serial number */
U16 cpumodel; /* CPU model number */
BYTE cpuversion; /* CPU version code */
BYTE cpuidfmt; /* STIDP format 0|1 */
TID impltid; /* Thread-id for main progr. */
TID loggertid; /* logger_thread Thread-id */
#if defined( OPTION_WATCHDOG )
TID wdtid; /* Thread-id for watchdog */
#endif
enum OPERATION_MODE operation_mode; /* CPU operation mode */
u_int lparmode:1; /* LPAR mode active */
U16 lparnum; /* LPAR identification number*/
U16 ipldev; /* IPL device */
int iplcpu; /* IPL cpu */
int ipllcss; /* IPL lcss */
int numvec; /* Number vector processors */
int maxcpu; /* Max number of CPUs */
int cpus; /* Number CPUs configured */
int hicpu; /* Highest online cpunum + 1 */
int topology; /* Configuration topology... */
#define TOPOLOGY_HORIZ 0 /* ...horizontal polarization*/
#define TOPOLOGY_VERT 1 /* ...vertical polarization */
int topchnge; /* 1 = Topology Change Report
pending (CPU cfg on/off) */
U32 cpmcr; /* Dynamic CP model rating */
U32 cpmpcr; /* ... Permanent */
U32 cpmtcr; /* ... Temporary */
U32 cpncr; /* Dynamic CP nominal rating */
U32 cpnpcr; /* ... Permanent */
U32 cpntcr; /* ... Temporary */
U32 cpmcap; /* Dynamic CP model capacity */
U32 cpncap; /* Dynamic CP nominal cap. */
U32 cpscap; /* Dynamic CP secondary cap. */
U32 cpacap; /* Dynamic CP alternate cap. */
U8 cpccr; /* Dynamic CP change reason */
U8 cpcai; /* Dynamic CP capacity adj. */
U8 hhc_111_112; /* HHC00111/HHC00112 issued */
U8 unused1; /* (pad/align/unused/avail) */
COND cpucond; /* CPU config/deconfig cond */
LOCK cpulock[ MAX_CPU_ENGS ];/* CPU lock */
#if defined( _FEATURE_073_TRANSACT_EXEC_FACILITY )
/* Transactional-Execution Facility locks */
LOCK txf_lock[ MAX_CPU_ENGS ]; /* CPU transaction lock for
txf_tnd/txf_tac access */
#define OBTAIN_TXFLOCK( regs ) obtain_lock ( &sysblk.txf_lock[ (regs)->cpuad ])
#define RELEASE_TXFLOCK( regs ) release_lock( &sysblk.txf_lock[ (regs)->cpuad ])
// PROGRAMMING NOTE: we purposely define the below count
// as a signed value (rather than unsigned) so that we can
// detect if, due to a bug, it ever goes negative (which
// would indicate a serious logic error!). This is checked
// by the UPDATE_SYSBLK_TRANSCPUS macro, which should be
// the only way this field is ever updated.
S32 txf_transcpus; /* Counts transacting CPUs */
/* Transactional-Execution Facility debugging flags */
U32 txf_tracing; /* TXF tracing control; */
/* see #defines below. */
U32 txf_why_mask; /* (only when TXF_TR_WHY) */
int txf_tac; /* (only when TXF_TR_TAC) */
int txf_tnd; /* (only when TXF_TR_TND) */
int txf_fails; /* (only when TXF_TR_FAILS) */
int txf_cpuad; /* (only when TXF_TR_CPU) */
#define TXF_TR_INSTR 0x80000000 // instructions
#define TXF_TR_C 0x08000000 // constrained
#define TXF_TR_U 0x04000000 // unconstrained
#define TXF_TR_SUCCESS 0x00800000 // success
#define TXF_TR_FAILURE 0x00400000 // failure
#define TXF_TR_WHY 0x00200000 // why mask
#define TXF_TR_TAC 0x00100000 // TAC
#define TXF_TR_TND 0x00080000 // TND
#define TXF_TR_CPU 0x00040000 // specific CPU
#define TXF_TR_FAILS 0x00020000 // aborted count
#define TXF_TR_TDB 0x00000800 // tdb
#define TXF_TR_PAGES 0x00000080 // page information
#define TXF_TR_LINES 0x00000040 // cache lines too
TXFSTATS txf_stats[2]; /* Transactional statistics
(slot 0 = unconstrained) */
#define TXF_STATS( ctr, contran ) \
\
atomic_update64( &sysblk.txf_stats[ contran ? 1 : 0 ].txf_ ## ctr, +1 )
#define TXF_CONSTRAINED( contran ) (contran ? "CONSTRAINED" : "UNconstrained" )
#endif /* defined( _FEATURE_073_TRANSACT_EXEC_FACILITY ) */
TOD cpucreateTOD[ MAX_CPU_ENGS ]; /* CPU creation time */
TID cputid[ MAX_CPU_ENGS ]; /* CPU thread ids */
clockid_t /* CPU clock */
cpuclockid[ MAX_CPU_ENGS ]; /* identifiers */
BYTE ptyp[ MAX_CPU_ENGS ]; /* SCCB ptyp for each engine */
LOCK todlock; /* TOD clock update lock */
TID todtid; /* Thread-id for TOD update */
REGS *regs[ MAX_CPU_ENGS + 1];/* Registers for each CPU */
/* Active Facility List */
BYTE facility_list[ NUM_GEN_ARCHS ][ STFL_HERC_DW_SIZE * sizeof( DW ) ];
/* CPU Measurement Counter facility
CPU Measurement Sampling facility
Load Program Parameter facility */
U64 program_parameter; /* Program Parameter Register*/
#if defined( _FEATURE_076_MSA_EXTENSION_FACILITY_3 )
HRANDHAND wkrandhand; /* secure random api handle */
BYTE wkaes_reg[32]; /* Wrapping-key registers */
BYTE wkdea_reg[24];
BYTE wkvpaes_reg[32]; /* Wrapping-key Verification */
BYTE wkvpdea_reg[24]; /* Pattern registers */
bool use_def_crypt; /* true = use srand()/rand() */
#endif /* defined( _FEATURE_076_MSA_EXTENSION_FACILITY_3 ) */
#if defined( _FEATURE_047_CMPSC_ENH_FACILITY )
BYTE zpbits; /* Zeropad alignment bits */
#define MIN_CMPSC_ZP_BITS 1 /* align to half word bndry */
#define DEF_CMPSC_ZP_BITS 8 /* align to 256 byte bndry */
#define MAX_CMPSC_ZP_BITS 12 /* align to 4096 page bndry */
#define CMPSC_ZP_BITS ((U8)sysblk.zpbits)
#define CMPSC_ZP_BYTES ((U16)1 << CMPSC_ZP_BITS)
#define CMPSC_ZP_MASK (((U64)-1) >> (64 - CMPSC_ZP_BITS))
#endif
#if defined( _FEATURE_S370_S390_VECTOR_FACILITY )
VFREGS vf[ MAX_CPU_ENGS ]; /* Vector Facility */
#endif
#if defined(_FEATURE_SIE)
ZPBLK zpb[FEATURE_SIE_MAXZONES]; /* SIE Zone Parameter Blk*/
#endif /*defined(_FEATURE_SIE)*/
#if defined(OPTION_FOOTPRINT_BUFFER)
REGS footprregs[ MAX_CPU_ENGS ][OPTION_FOOTPRINT_BUFFER];
U32 footprptr[ MAX_CPU_ENGS ];
#endif
#define LOCK_OWNER_NONE 0xFFFF
#define LOCK_OWNER_OTHER 0xFFFE
U16 mainowner; /* Mainlock owner */
U16 intowner; /* Intlock owner */
LOCK mainlock; /* Main storage lock */
LOCK intlock; /* Interrupt lock */
LOCK iointqlk; /* I/O Interrupt Queue lock */
LOCK sigplock; /* Signal processor lock */
ATTR detattr; /* Detached thread attribute */
ATTR joinattr; /* Joinable thread attribute */
#define DETACHED &sysblk.detattr /* (helper macro) */
#define JOINABLE &sysblk.joinattr /* (helper macro) */
TID cnsltid; /* Thread-id for console */
TID socktid; /* Thread-id for sockdev */
/* 3270 Console keepalive: */
int kaidle; /* keepalive idle seconds */
int kaintv; /* keepalive probe interval */
int kacnt; /* keepalive probe count */
LOCK cnslpipe_lock; /* signaled flag access lock */
int cnslpipe_flag; /* 1 == already signaled */
int cnslwpipe; /* fd for sending signal */
int cnslrpipe; /* fd for receiving signal */
LOCK sockpipe_lock; /* signaled flag access lock */
int sockpipe_flag; /* 1 == already signaled */
int sockwpipe; /* fd for sending signal */
int sockrpipe; /* fd for receiving signal */
RADR mbo; /* Measurement block origin */
BYTE mbk; /* Measurement block key */
int mbm; /* Measurement block mode */
int mbd; /* Device connect time mode */
LOCK scrlock; /* Script processing lock */
COND scrcond; /* Test script condition */
int scrtest; /* 1 == test mode active */
double scrfactor; /* Testing timeout factor */
TID cmdtid; /* Active command thread */
char cmdsep; /* Command Separator char */
BYTE sysgroup; /* Panel Command grouping */
#define SYSGROUP_SYSOPER 0x01 /* Computer operator group */
#define SYSGROUP_SYSMAINT 0x02 /* System Maintainer group */
#define SYSGROUP_SYSPROG 0x04 /* System Programmer group */
#define SYSGROUP_SYSNONE 0x08 /* Command valid w/no group */
#define SYSGROUP_SYSCONFIG 0x10 /* System Configuration group*/
#define SYSGROUP_SYSDEVEL 0x20 /* Hercules Developer group */
#define SYSGROUP_SYSDEBUG 0x40 /* Internal Debug group */
#define SYSGROUP_SYSNDIAG 0x80 /* Not supported by DIAG008 */
#define SYSGROUP_SYSALL 0x7F /* All groups but no DIAG008 */
#define SYSGROUP_PROGDEVELDEBUG ( SYSGROUP_SYSPROG | \
SYSGROUP_SYSDEVEL | \
SYSGROUP_SYSDEBUG )
#if defined(_DEBUG) || defined(DEBUG)
#define DEFAULT_SYSGROUP SYSGROUP_SYSALL
#else
#define DEFAULT_SYSGROUP (0 \
| SYSGROUP_SYSOPER \
| SYSGROUP_SYSMAINT \
| SYSGROUP_SYSPROG \
| SYSGROUP_SYSNONE \
| SYSGROUP_SYSCONFIG \
)
#endif
BYTE diag8opt; /* Diagnose 8 option */
#define DIAG8CMD_ENABLE 0x01 /* Enable DIAG8 interface */
#define DIAG8CMD_ECHO 0x80 /* Echo command to console */
BYTE shcmdopt; /* Host shell access option */
#define SHCMDOPT_ENABLE 0x01 /* Allow host shell access */
#define SHCMDOPT_DIAG8 0x02 /* Allow for DIAG8 as well */
int panrate; /* Panel refresh rate */
int pan_colors; /* Panel colors option: */
#define PANC_NONE 0 /* No colors (default) */
#define PANC_DARK 1 /* Dark background scheme */
#define PANC_LIGHT 2 /* Light/white background */
int pan_color[5][2]; /* Panel message colors: */
#define PANC_X_IDX 0 /* (default) */
#define PANC_I_IDX 1 /* 'I'nformational */
#define PANC_E_IDX 2 /* 'E'rror */
#define PANC_W_IDX 3 /* 'W'arning */
#define PANC_D_IDX 4 /* 'D'ebug */
#define PANC_FG_IDX 0 /* Foreground */
#define PANC_BG_IDX 1 /* Background */
int timerint; /* microsecs timer interval */
char *pantitle; /* Alt console panel title */
#if defined( OPTION_SCSI_TAPE )
/* Access to all SCSI fields controlled by sysblk.stape_lock */
LOCK stape_lock; /* LOCK for all SCSI fields */
int auto_scsi_mount_secs; /* scsimount frequency: #of */
/* seconds; 0 == disabled */
#define DEF_SCSIMOUNT_SECS (5) /* Default scsimount value */
TID stape_getstat_tid; /* Tape-status worker thread */
TID stape_mountmon_tid; /* Tape-mount worker thread */
COND stape_getstat_cond; /* Tape-status thread COND */
u_int stape_getstat_busy:1; /* 1=Status thread is busy */
LIST_ENTRY stape_status_link; /* get status request chain */
LIST_ENTRY stape_mount_link; /* scsimount request chain */
struct timeval
stape_query_status_tod; /* TOD of last status query */
#endif // defined( OPTION_SCSI_TAPE )
/*-----------------------------------------------------------*/
/* Control Units */
/*-----------------------------------------------------------*/
U16 cuhigh; /* Highest used CU number */
CHAINBLK cuchain; /* -> CU chain */
/*-----------------------------------------------------------*/
/* Devices */
/*-----------------------------------------------------------*/
DEVBLK *firstdev; /* -> First device block */
DEVBLK *sysgdev; /* -> devblk for SYSG console*/
DEVBLK ***devnum_fl; /* 1st level table for fast */
/* devnum lookup */
DEVBLK ***subchan_fl; /* Subchannel table fast */
/* lookup table */
int highsubchan[FEATURE_LCSS_MAX]; /* Highest subchan+1 */
CHPBLK *firstchp; /* -> First channel path */
LOCK dasdcache_lock; /* Global DASD caching lock */
/*-----------------------------------------------------------*/
/* I/O Management */
/*-----------------------------------------------------------*/
int mss; /* Multiple CSS enabled */
int lcssmax; /* Maximum Subchannel-Set Id */
LOCK crwlock; /* CRW queue lock */
U32 *crwarray; /* CRW queue */
U32 crwalloc; /* #of entries allocated */
U32 crwcount; /* #of entries queued */
U32 crwindex; /* CRW queue index */
IOINT *iointq; /* I/O interrupt queue */
DEVBLK *ioq; /* I/O queue */
LOCK ioqlock; /* I/O queue lock */
COND ioqcond; /* I/O queue condition */
int devtwait; /* Device threads waiting */
int devtnbr; /* Number of device threads */
int devtmax; /* Max device threads */
int devthwm; /* High water mark */
int devtunavail; /* Count thread unavailable */
RADR addrlimval; /* Address limit value (SAL) */
#if defined(_FEATURE_VM_BLOCKIO)
U16 servcode; /* External interrupt code */
BYTE biosubcd; /* Block I/O sub int. code */
BYTE biostat; /* Block I/O status */
U64 bioparm; /* Block I/O interrupt parm */
DEVBLK *biodev; /* Block I/O device */
/* Note: biodev is only used to detect BIO interrupt tracing */
#endif /* defined(FEATURE_VM_BLOCKIO) */
TAMDIR *tamdir; /* Acc/Rej AUTOMOUNT dir ctl */
char *defdir; /* Default AUTOMOUNT dir */
U32 servparm; /* Service signal parameter */
unsigned int /* Flags */
sys_reset:1, /* 1 = system in reset state */
ipled:1, /* 1 = guest has been IPL'ed */
daemon_mode:1, /* Daemon mode active */
panel_init:1, /* Panel display initialized */
npquiet:1, /* New Panel quiet indicator */
#if defined(_FEATURE_SYSTEM_CONSOLE)
scpecho:1, /* scp echo mode indicator */
scpimply:1, /* scp imply mode indicator */
#endif
sigintreq:1, /* 1 = SIGINT request pending*/
insttrace:1, /* 1 = Inst trace enabled */
instbreak:1, /* 1 = Inst break enabled */
shutdown:1, /* 1 = shutdown requested */
shutfini:1, /* 1 = shutdown complete */
shutimmed:1, /* 1 = shutdown req immed */
main_clear:1, /* 1 = mainstor is cleared */
xpnd_clear:1, /* 1 = xpndstor is cleared */
showregsfirst:1, /* 1 = show regs before inst */
showregsnone:1, /* 1 = show no registers */
nomountedtapereinit:1, /* 1 = disallow tape devinit
if tape already mounted */
auto_tape_create:1, /* 1=Automatically do minimal
'hetinit' at tape open to
create the tape file if it
does not yet exist. */
#define DEF_AUTO_TAPE_CREATE TRUE /* Default auto_tape_create */
legacysenseid:1, /* ena/disa senseid on */
/* legacy devices */
haveiplparm:1, /* IPL PARM a la VM */
logoptnodate:1, /* 1 = don't datestamp log */
logoptnotime:1, /* 1 = don't timestamp log */
nolrasoe:1, /* 1 = No trace LRA Special */
/* Operation Exceptions */
noch9oflow:1, /* Suppress CH9 O'Flow trace */
devnameonly:1; /* Display only dev filename */
U32 ints_state; /* Common Interrupts Status */
CPU_BITMAP config_mask; /* Configured CPUs */
CPU_BITMAP started_mask; /* Started CPUs */
CPU_BITMAP waiting_mask; /* Waiting CPUs */
U16 breakasid; /* Break ASID */
U64 breakaddr[2]; /* Break address range */
U64 traceaddr[2]; /* Tracing address range */
U64 auto_trace_beg; /* Automatic t+ instcount */
U64 auto_trace_amt; /* Automatic tracing amount */
BYTE iplparmstring[64]; /* 64 bytes loadable at IPL */
char loadparm[8+1]; /* Default LOADPARM */
#ifdef _FEATURE_ECPSVM
//
/* ECPS:VM */
struct {
u_int level:16;
u_int debug:1;
u_int available:1;
u_int enabletrap:1;
u_int freetrap:1;
} ecpsvm; /* ECPS:VM structure */
//
#endif
U64 pgminttr; /* Program int trace mask */
int pcpu; /* Tgt CPU panel cmd & displ */
int hercnice; /* Herc. process NICE value */
int minprio; /* pthread minimum priority */
int maxprio; /* pthread maximum priority */
int hercprio; /* Hercules THREAD priority */
int todprio; /* TOD Clock thread priority */
int cpuprio; /* CPU thread priority */
int devprio; /* Device thread priority */
int srvprio; /* Listeners thread priority */
TID httptid; /* HTTP listener thread id */
/* Fields used by SYNCHRONIZE_CPUS */
bool syncing; /* 1=Sync in progress */
CPU_BITMAP sync_mask; /* CPU mask for syncing CPUs */
COND all_synced_cond; /* Sync in progress COND */
COND sync_done_cond; /* Synchronization done COND */
#if defined( OPTION_SHARED_DEVICES )
LOCK shrdlock; /* shrdport LOCK */
COND shrdcond; /* shrdport COND */
TID shrdtid; /* Shared device listener */
U16 shrdport; /* Shared device server port */
U32 shrdcount; /* IO count */
LOCK shrdtracelock; /* Trace table LOCK */
SHRD_TRACE *shrdtrace; /* Internal trace table */
SHRD_TRACE *shrdtracep; /* Current pointer */
SHRD_TRACE *shrdtracex; /* End of trace table */
int shrdtracen; /* Number of entries */
bool shrddtax; /* true=dump table at exit */
#endif
#ifdef OPTION_IODELAY_KLUDGE
int iodelay; /* I/O delay kludge for linux*/
#endif /*OPTION_IODELAY_KLUDGE*/
#if !defined(NO_SETUID)
uid_t ruid, euid, suid;
gid_t rgid, egid, sgid;
#endif /*!defined(NO_SETUID)*/
#if defined( OPTION_INSTRUCTION_COUNTING )