diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index a193000aeaf7..562bc53fcf04 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -480,6 +480,12 @@ class Qualifiers {
            // Otherwise in OpenCLC v2.0 s6.5.5: every address space except
            // for __constant can be used as __generic.
            (A == LangAS::opencl_generic && B != LangAS::opencl_constant) ||
+           // We also define global_device and global_host address spaces,
+           // to distinguish global pointers allocated on host from pointers
+           // allocated on device, which are a subset of __global.
+           // FIXME: add a reference to spec when ready
+           (A == LangAS::opencl_global && (B == LangAS::opencl_global_device ||
+                                           B == LangAS::opencl_global_host)) ||
            // Consider pointer size address spaces to be equivalent to default.
            ((isPtrSizeAddressSpace(A) || A == LangAS::Default) &&
             (isPtrSizeAddressSpace(B) || B == LangAS::Default));
@@ -493,7 +499,9 @@ class Qualifiers {
            (!hasAddressSpace() &&
             (other.getAddressSpace() == LangAS::opencl_private ||
              other.getAddressSpace() == LangAS::opencl_local ||
-             other.getAddressSpace() == LangAS::opencl_global));
+             other.getAddressSpace() == LangAS::opencl_global ||
+             other.getAddressSpace() == LangAS::opencl_global_device ||
+             other.getAddressSpace() == LangAS::opencl_global_host));
   }
 
   /// Determines if these qualifiers compatibly include another set.
diff --git a/clang/include/clang/Basic/AddressSpaces.h b/clang/include/clang/Basic/AddressSpaces.h
index faf7f303aa2d..a9db52dfcc9c 100644
--- a/clang/include/clang/Basic/AddressSpaces.h
+++ b/clang/include/clang/Basic/AddressSpaces.h
@@ -36,6 +36,8 @@ enum class LangAS : unsigned {
   opencl_constant,
   opencl_private,
   opencl_generic,
+  opencl_global_device,
+  opencl_global_host,
 
   // CUDA specific address spaces.
   cuda_device,
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index 053b3eb4fd38..b65c2697dd1a 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -326,6 +326,7 @@ def CUDA : LangOpt<"CUDA">;
 def SYCLIsDevice : LangOpt<"SYCLIsDevice">;
 def SYCL : LangOpt<"SYCLIsDevice">;
 def SYCLIsHost : LangOpt<"SYCLIsHost">;
+def SYCLExplicitSIMD : LangOpt<"SYCLExplicitSIMD">;
 def HIP : LangOpt<"HIP">;
 def COnly : LangOpt<"", "!LangOpts.CPlusPlus">;
 def CPlusPlus : LangOpt<"CPlusPlus">;
@@ -1124,6 +1125,7 @@ def SYCLDevice : InheritableAttr {
   let Subjects = SubjectList<[Function]>;
   let LangOpts = [SYCLIsDevice];
   let Documentation = [SYCLDeviceDocs];
+  let PragmaAttributeSupport = 0;
 }
 
 def SYCLKernel : InheritableAttr {
@@ -1159,6 +1161,7 @@ def SYCLDeviceIndirectlyCallable : InheritableAttr {
   let Subjects = SubjectList<[Function]>;
   let LangOpts = [SYCLIsDevice];
   let Documentation = [SYCLDeviceIndirectlyCallableDocs];
+  let PragmaAttributeSupport = 0;
 }
 
 def SYCLIntelKernelArgsRestrict : InheritableAttr {
@@ -1167,6 +1170,7 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr {
   let LangOpts = [ SYCLIsDevice, SYCLIsHost ];
   let Documentation = [ SYCLIntelKernelArgsRestrictDocs ];
   let SimpleHandler = 1;
+  let PragmaAttributeSupport = 0;
 }
 
 def SYCLIntelNumSimdWorkItems : InheritableAttr {
@@ -1265,6 +1269,7 @@ def IntelReqdSubGroupSize: InheritableAttr {
   let Subjects = SubjectList<[Function, CXXMethod], ErrorDiag>;
   let Documentation = [IntelReqdSubGroupSizeDocs];
   let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost];
+  let PragmaAttributeSupport = 0;
 }
 
 // This attribute is both a type attribute, and a declaration attribute (for
@@ -1293,6 +1298,16 @@ def OpenCLGlobalAddressSpace : TypeAttr {
   let Documentation = [OpenCLAddressSpaceGlobalDocs];
 }
 
+def OpenCLGlobalDeviceAddressSpace : TypeAttr {
+  let Spellings = [Clang<"opencl_global_device">];
+  let Documentation = [OpenCLGlobalAddressSpacesDocs];
+}
+
+def OpenCLGlobalHostAddressSpace : TypeAttr {
+  let Spellings = [Clang<"opencl_global_host">];
+  let Documentation = [OpenCLGlobalAddressSpacesDocs];
+}
+
 def OpenCLLocalAddressSpace : TypeAttr {
   let Spellings = [Keyword<"__local">, Keyword<"local">, Clang<"opencl_local">];
   let Documentation = [OpenCLAddressSpaceLocalDocs];
diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td
index a942c9011bb4..eafcc37e8bc5 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -3561,6 +3561,17 @@ scope) variables and static local variable as well.
   }];
 }
 
+def OpenCLGlobalAddressSpacesDocs : Documentation {
+  let Category = DocOpenCLAddressSpaces;
+  let Heading = "[[clang::opencl_global_device]], [[clang::opencl_global_host]]";
+  let Content = [{
+The (global_device) and (global_host) address space attributes specify that an
+object is allocated in global memory on the device/host. It helps distinguishing
+USM pointers that access device memory and accessors that access global memory
+from those that access host memory.
+  }];
+}
+
 def OpenCLAddressSpaceLocalDocs : Documentation {
   let Category = DocOpenCLAddressSpaces;
   let Heading = "__local, local, [[clang::opencl_local]]";
diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def
index d1074e0da4f0..6d4c77fca5a9 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -248,6 +248,7 @@ LANGOPT(SYCLStdLayoutKernelParams, 1, 0, "Enable standard layout requirement for
 LANGOPT(SYCLUnnamedLambda , 1, 0, "Allow unnamed lambda SYCL kernels")
 LANGOPT(SYCLVersion       , 32, 0, "Version of the SYCL standard used")
 LANGOPT(DeclareSPIRVBuiltins, 1, 0, "Declare SPIR-V builtin functions")
+LANGOPT(SYCLExplicitSIMD  , 1, 0, "SYCL compilation with explicit SIMD extension")
 
 LANGOPT(HIPUseNewLaunchAPI, 1, 0, "Use new kernel launching API for HIP")
 
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 8f15ebf76282..55431a0fed32 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3576,6 +3576,10 @@ def fno_sycl : Flag<["-"], "fno-sycl">, Group<sycl_Group>, Flags<[CoreOption]>,
   HelpText<"Disable SYCL kernels compilation for device">;
 def sycl_std_EQ : Joined<["-"], "sycl-std=">, Group<sycl_Group>, Flags<[CC1Option, NoArgumentUnused, CoreOption]>,
   HelpText<"SYCL language standard to compile for.">, Values<"2017, 121, 1.2.1, sycl-1.2.1">;
+def fsycl_esimd : Flag<["-"], "fsycl-explicit-simd">, Group<sycl_Group>, Flags<[CC1Option, NoArgumentUnused, CoreOption]>,
+  HelpText<"Enable SYCL explicit SIMD extension">;
+def fno_sycl_esimd : Flag<["-"], "fno-sycl-explicit-simd">, Group<sycl_Group>,
+  HelpText<"Disable SYCL explicit SIMD extension">, Flags<[NoArgumentUnused, CoreOption]>;
 
 include "CC1Options.td"
 
diff --git a/clang/include/clang/Sema/ParsedAttr.h b/clang/include/clang/Sema/ParsedAttr.h
index 21e030fe5134..8946b12ee03f 100644
--- a/clang/include/clang/Sema/ParsedAttr.h
+++ b/clang/include/clang/Sema/ParsedAttr.h
@@ -606,6 +606,10 @@ class ParsedAttr final
       return LangAS::opencl_constant;
     case ParsedAttr::AT_OpenCLGlobalAddressSpace:
       return LangAS::opencl_global;
+    case ParsedAttr::AT_OpenCLGlobalDeviceAddressSpace:
+      return LangAS::opencl_global_device;
+    case ParsedAttr::AT_OpenCLGlobalHostAddressSpace:
+      return LangAS::opencl_global_host;
     case ParsedAttr::AT_OpenCLLocalAddressSpace:
       return LangAS::opencl_local;
     case ParsedAttr::AT_OpenCLPrivateAddressSpace:
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 7244e063c7a6..12f33edb24ef 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -919,18 +919,20 @@ static const LangASMap *getAddressSpaceMap(const TargetInfo &T,
     // The fake address space map must have a distinct entry for each
     // language-specific address space.
     static const unsigned FakeAddrSpaceMap[] = {
-        0, // Default
-        1, // opencl_global
-        3, // opencl_local
-        2, // opencl_constant
-        0, // opencl_private
-        4, // opencl_generic
-        5, // cuda_device
-        6, // cuda_constant
-        7, // cuda_shared
-        8, // ptr32_sptr
-        9, // ptr32_uptr
-        10 // ptr64
+        0,  // Default
+        1,  // opencl_global
+        3,  // opencl_local
+        2,  // opencl_constant
+        0,  // opencl_private
+        4,  // opencl_generic
+        11, // opencl_global_device
+        12, // opencl_global_host
+        5,  // cuda_device
+        6,  // cuda_constant
+        7,  // cuda_shared
+        8,  // ptr32_sptr
+        9,  // ptr32_uptr
+        10  // ptr64
     };
     return &FakeAddrSpaceMap;
   } else {
@@ -2067,7 +2069,9 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T) const {
       Align = Target->getDoubleAlign();
       break;
     case BuiltinType::LongDouble:
-      if (getLangOpts().OpenMP && getLangOpts().OpenMPIsDevice &&
+      if (((getLangOpts().SYCL && getLangOpts().SYCLIsDevice) ||
+           (getLangOpts().OpenMP && getLangOpts().OpenMPIsDevice)) &&
+          AuxTarget != nullptr &&
           (Target->getLongDoubleWidth() != AuxTarget->getLongDoubleWidth() ||
            Target->getLongDoubleAlign() != AuxTarget->getLongDoubleAlign())) {
         Width = AuxTarget->getLongDoubleWidth();
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 3710b95bb340..9164921c9716 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -2387,16 +2387,39 @@ void CXXNameMangler::mangleQualifiers(Qualifiers Quals, const DependentAddressSp
       switch (AS) {
       default: llvm_unreachable("Not a language specific address space");
       //  <OpenCL-addrspace> ::= "CL" [ "global" | "local" | "constant" |
-      //                                "private"| "generic" ]
-      case LangAS::opencl_global:   ASString = "CLglobal";   break;
-      case LangAS::opencl_local:    ASString = "CLlocal";    break;
-      case LangAS::opencl_constant: ASString = "CLconstant"; break;
-      case LangAS::opencl_private:  ASString = "CLprivate";  break;
-      case LangAS::opencl_generic:  ASString = "CLgeneric";  break;
+      //                                "private"| "generic" | "global_device" |
+      //                                "global_host" ]
+      case LangAS::opencl_global:
+        ASString = "CLglobal";
+        break;
+      case LangAS::opencl_global_device:
+        ASString = "CLDevice";
+        break;
+      case LangAS::opencl_global_host:
+        ASString = "CLHost";
+        break;
+      case LangAS::opencl_local:
+        ASString = "CLlocal";
+        break;
+      case LangAS::opencl_constant:
+        ASString = "CLconstant";
+        break;
+      case LangAS::opencl_private:
+        ASString = "CLprivate";
+        break;
+      case LangAS::opencl_generic:
+        ASString = "CLgeneric";
+        break;
       //  <CUDA-addrspace> ::= "CU" [ "device" | "constant" | "shared" ]
-      case LangAS::cuda_device:     ASString = "CUdevice";   break;
-      case LangAS::cuda_constant:   ASString = "CUconstant"; break;
-      case LangAS::cuda_shared:     ASString = "CUshared";   break;
+      case LangAS::cuda_device:
+        ASString = "CUdevice";
+        break;
+      case LangAS::cuda_constant:
+        ASString = "CUconstant";
+        break;
+      case LangAS::cuda_shared:
+        ASString = "CUshared";
+        break;
       //  <ptrsize-addrspace> ::= [ "ptr32_sptr" | "ptr32_uptr" | "ptr64" ]
       case LangAS::ptr32_sptr:
         ASString = "ptr32_sptr";
diff --git a/clang/lib/AST/MicrosoftMangle.cpp b/clang/lib/AST/MicrosoftMangle.cpp
index e3796accb26e..7e6cf7bdd2be 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -1823,6 +1823,12 @@ void MicrosoftCXXNameMangler::mangleAddressSpaceType(QualType T,
     case LangAS::opencl_global:
       Extra.mangleSourceName("_ASCLglobal");
       break;
+    case LangAS::opencl_global_device:
+      Extra.mangleSourceName("_ASCLDevice");
+      break;
+    case LangAS::opencl_global_host:
+      Extra.mangleSourceName("_ASCLHost");
+      break;
     case LangAS::opencl_local:
       Extra.mangleSourceName("_ASCLlocal");
       break;
diff --git a/clang/lib/AST/TypePrinter.cpp b/clang/lib/AST/TypePrinter.cpp
index 87b273234ad9..0505d53d6f99 100644
--- a/clang/lib/AST/TypePrinter.cpp
+++ b/clang/lib/AST/TypePrinter.cpp
@@ -1577,6 +1577,8 @@ void TypePrinter::printAttributedAfter(const AttributedType *T,
 
   case attr::OpenCLPrivateAddressSpace:
   case attr::OpenCLGlobalAddressSpace:
+  case attr::OpenCLGlobalDeviceAddressSpace:
+  case attr::OpenCLGlobalHostAddressSpace:
   case attr::OpenCLLocalAddressSpace:
   case attr::OpenCLConstantAddressSpace:
   case attr::OpenCLGenericAddressSpace:
@@ -1880,6 +1882,10 @@ std::string Qualifiers::getAddrSpaceAsString(LangAS AS) {
     return "__constant";
   case LangAS::opencl_generic:
     return "__generic";
+  case LangAS::opencl_global_device:
+    return "__global_device";
+  case LangAS::opencl_global_host:
+    return "__global_host";
   case LangAS::cuda_device:
     return "__device__";
   case LangAS::cuda_constant:
diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp
index da7bd34c9532..d5af8c396535 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -45,6 +45,8 @@ const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
     Constant, // opencl_constant
     Private,  // opencl_private
     Generic,  // opencl_generic
+    Global,   // opencl_global_device
+    Global,   // opencl_global_host
     Global,   // cuda_device
     Constant, // cuda_constant
     Local,    // cuda_shared
@@ -60,6 +62,8 @@ const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
     Constant, // opencl_constant
     Private,  // opencl_private
     Generic,  // opencl_generic
+    Global,   // opencl_global_device
+    Global,   // opencl_global_host
     Global,   // cuda_device
     Constant, // cuda_constant
     Local,    // cuda_shared
diff --git a/clang/lib/Basic/Targets/NVPTX.h b/clang/lib/Basic/Targets/NVPTX.h
index fc8c832641ad..194baa411d62 100644
--- a/clang/lib/Basic/Targets/NVPTX.h
+++ b/clang/lib/Basic/Targets/NVPTX.h
@@ -30,6 +30,8 @@ static const unsigned NVPTXAddrSpaceMap[] = {
     0, // opencl_private
     // FIXME: generic has to be added to the target
     0, // opencl_generic
+    1, // opencl_global_device
+    1, // opencl_global_host
     1, // cuda_device
     4, // cuda_constant
     3, // cuda_shared
diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h
index dcaabec66536..49d6d840566d 100644
--- a/clang/lib/Basic/Targets/SPIR.h
+++ b/clang/lib/Basic/Targets/SPIR.h
@@ -24,33 +24,37 @@ namespace clang {
 namespace targets {
 
 static const unsigned SPIRAddrSpaceMap[] = {
-    0, // Default
-    1, // opencl_global
-    3, // opencl_local
-    2, // opencl_constant
-    0, // opencl_private
-    4, // opencl_generic
-    0, // cuda_device
-    0, // cuda_constant
-    0, // cuda_shared
-    0, // ptr32_sptr
-    0, // ptr32_uptr
-    0  // ptr64
+    0,  // Default
+    1,  // opencl_global
+    3,  // opencl_local
+    2,  // opencl_constant
+    0,  // opencl_private
+    4,  // opencl_generic
+    11, // opencl_global_device
+    12, // opencl_global_host
+    0,  // cuda_device
+    0,  // cuda_constant
+    0,  // cuda_shared
+    0,  // ptr32_sptr
+    0,  // ptr32_uptr
+    0   // ptr64
 };
 
 static const unsigned SYCLAddrSpaceMap[] = {
-    4, // Default
-    1, // opencl_global
-    3, // opencl_local
-    2, // opencl_constant
-    0, // opencl_private
-    4, // opencl_generic
-    0, // cuda_device
-    0, // cuda_constant
-    0, // cuda_shared
-    0, // ptr32_sptr
-    0, // ptr32_uptr
-    0  // ptr64
+    4,  // Default
+    1,  // opencl_global
+    3,  // opencl_local
+    2,  // opencl_constant
+    0,  // opencl_private
+    4,  // opencl_generic
+    11, // opencl_global_device
+    12, // opencl_global_host
+    0,  // cuda_device
+    0,  // cuda_constant
+    0,  // cuda_shared
+    0,  // ptr32_sptr
+    0,  // ptr32_uptr
+    0   // ptr64
 };
 
 class LLVM_LIBRARY_VISIBILITY SPIRTargetInfo : public TargetInfo {
@@ -209,8 +213,6 @@ class LLVM_LIBRARY_VISIBILITY MicrosoftX86_32SPIRTargetInfo
   MicrosoftX86_32SPIRTargetInfo(const llvm::Triple &Triple,
                             const TargetOptions &Opts)
       : WindowsX86_32SPIRTargetInfo(Triple, Opts) {
-    LongDoubleWidth = LongDoubleAlign = 64;
-    LongDoubleFormat = &llvm::APFloat::IEEEdouble();
     assert(DataLayout->getPointerSizeInBits() == 32);
   }
 
@@ -261,8 +263,6 @@ class LLVM_LIBRARY_VISIBILITY MicrosoftX86_64_SPIR64TargetInfo
   MicrosoftX86_64_SPIR64TargetInfo(const llvm::Triple &Triple,
                             const TargetOptions &Opts)
       : WindowsX86_64_SPIR64TargetInfo(Triple, Opts) {
-    LongDoubleWidth = LongDoubleAlign = 64;
-    LongDoubleFormat = &llvm::APFloat::IEEEdouble();
     assert(DataLayout->getPointerSizeInBits() == 64);
   }
 
diff --git a/clang/lib/Basic/Targets/TCE.h b/clang/lib/Basic/Targets/TCE.h
index 9cbf2a3688a2..445fe4fe7293 100644
--- a/clang/lib/Basic/Targets/TCE.h
+++ b/clang/lib/Basic/Targets/TCE.h
@@ -35,6 +35,8 @@ static const unsigned TCEOpenCLAddrSpaceMap[] = {
     4, // opencl_local
     5, // opencl_constant
     0, // opencl_private
+    1, // opencl_global_device
+    1, // opencl_global_host
     // FIXME: generic has to be added to the target
     0, // opencl_generic
     0, // cuda_device
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index 39ccac96a49d..2b2462f97af8 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -29,6 +29,8 @@ static const unsigned X86AddrSpaceMap[] = {
     0,   // opencl_constant
     0,   // opencl_private
     0,   // opencl_generic
+    0,   // opencl_global_device
+    0,   // opencl_global_host
     0,   // cuda_device
     0,   // cuda_constant
     0,   // cuda_shared
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index 775fdd42edae..c656e2d10f21 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1363,10 +1363,18 @@ static void removeImageAccessQualifier(std::string& TyName) {
 // (basically all single AS CPUs).
 static unsigned ArgInfoAddressSpace(LangAS AS) {
   switch (AS) {
-  case LangAS::opencl_global:   return 1;
-  case LangAS::opencl_constant: return 2;
-  case LangAS::opencl_local:    return 3;
-  case LangAS::opencl_generic:  return 4; // Not in SPIR 2.0 specs.
+  case LangAS::opencl_global:
+    return 1;
+  case LangAS::opencl_constant:
+    return 2;
+  case LangAS::opencl_local:
+    return 3;
+  case LangAS::opencl_generic:
+    return 4; // Not in SPIR 2.0 specs.
+  case LangAS::opencl_global_device:
+    return 11;
+  case LangAS::opencl_global_host:
+    return 12;
   default:
     return 0; // Assume private.
   }
@@ -3861,6 +3869,8 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const VarDecl *D) {
   if (LangOpts.OpenCL) {
     AddrSpace = D ? D->getType().getAddressSpace() : LangAS::opencl_global;
     assert(AddrSpace == LangAS::opencl_global ||
+           AddrSpace == LangAS::opencl_global_device ||
+           AddrSpace == LangAS::opencl_global_host ||
            AddrSpace == LangAS::opencl_constant ||
            AddrSpace == LangAS::opencl_local ||
            AddrSpace >= LangAS::FirstTargetAddressSpace);
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 6d95f062907b..e808b1376cc2 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -4085,6 +4085,10 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
     CmdArgs.push_back("-fsycl");
     CmdArgs.push_back("-fsycl-is-device");
     CmdArgs.push_back("-fdeclare-spirv-builtins");
+
+    if (Args.hasFlag(options::OPT_fsycl_esimd, options::OPT_fno_sycl_esimd,
+                     false))
+      CmdArgs.push_back("-fsycl-explicit-simd");
     // Pass the triple of host when doing SYCL
     auto AuxT = llvm::Triple(llvm::sys::getProcessTriple());
     std::string NormalizedTriple = AuxT.normalize();
@@ -6132,6 +6136,10 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
       // doing the host pass.
       CmdArgs.push_back("-fsycl");
       CmdArgs.push_back("-fsycl-is-host");
+
+      if (Args.hasFlag(options::OPT_fsycl_esimd, options::OPT_fno_sycl_esimd,
+                       false))
+        CmdArgs.push_back("-fsycl-explicit-simd");
     }
     if (IsSYCLOffloadDevice && JA.getType() == types::TY_SYCL_Header) {
       // Generating a SYCL Header
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index 6e26d1bbd354..636430f6e9ee 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -2553,6 +2553,7 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
             << A->getAsString(Args) << A->getValue();
       }
     }
+    Opts.SYCLExplicitSIMD = Args.hasArg(options::OPT_fsycl_esimd);
   }
 
   Opts.IncludeDefaultHeader = Args.hasArg(OPT_finclude_default_header);
diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp
index f5bd8a32954f..52f0ffc02c77 100644
--- a/clang/lib/Frontend/InitPreprocessor.cpp
+++ b/clang/lib/Frontend/InitPreprocessor.cpp
@@ -1113,6 +1113,8 @@ static void InitializePredefinedMacros(const TargetInfo &TI,
         Builder.defineMacro("__SYCL_NVPTX__", "1");
     }
   }
+  if (LangOpts.SYCLExplicitSIMD)
+    Builder.defineMacro("__SYCL_EXPLICIT_SIMD__", "1");
   if (LangOpts.SYCLUnnamedLambda)
     Builder.defineMacro("__SYCL_UNNAMED_LAMBDA__", "1");
 
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index 882048d766b0..6b6b5a239dbf 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -1753,7 +1753,12 @@ void Sema::checkDeviceDecl(const ValueDecl *D, SourceLocation Loc) {
     if (Ty->isDependentType())
       return;
 
-    if ((Ty->isFloat16Type() && !Context.getTargetInfo().hasFloat16Type()) ||
+    auto IsSYCLDeviceCuda = getLangOpts().SYCLIsDevice &&
+                            Context.getTargetInfo().getTriple().isNVPTX();
+    if ((Ty->isFloat16Type() && !Context.getTargetInfo().hasFloat16Type() &&
+         // Disable check for SYCL CUDA BE until FP16 support is properly
+         // reported there (issue#1799)
+         !IsSYCLDeviceCuda) ||
         ((Ty->isFloat128Type() ||
           (Ty->isRealFloatingType() && Context.getTypeSize(Ty) == 128)) &&
          !Context.getTargetInfo().hasFloat128Type()) ||
diff --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp
index 05bfbba231a9..2304ce856539 100644
--- a/clang/lib/Sema/SemaLookup.cpp
+++ b/clang/lib/Sema/SemaLookup.cpp
@@ -908,8 +908,11 @@ bool Sema::LookupBuiltin(LookupResult &R) {
               *this, 0, R, II, Index.first - 1, Index.second,
               [this](const SPIRVBuiltin::BuiltinStruct &,
                      FunctionDecl &NewBuiltin) {
-                NewBuiltin.addAttr(
-                    SYCLDeviceAttr::CreateImplicit(this->Context));
+                if (!this->getLangOpts().CPlusPlus)
+                  NewBuiltin.addAttr(OverloadableAttr::CreateImplicit(Context));
+                if (this->getLangOpts().SYCLIsDevice)
+                  NewBuiltin.addAttr(
+                      SYCLDeviceAttr::CreateImplicit(this->Context));
               });
           return true;
         }
diff --git a/clang/lib/Sema/SemaSYCL.cpp b/clang/lib/Sema/SemaSYCL.cpp
index b83ee3c864bc..cb3c2a2c78dd 100644
--- a/clang/lib/Sema/SemaSYCL.cpp
+++ b/clang/lib/Sema/SemaSYCL.cpp
@@ -1857,6 +1857,38 @@ void SYCLIntegrationHeader::emitForwardClassDecls(
         // template class Foo specialized by class Baz<Bar>, not a template
         // class template <template <typename> class> class T as it should.
         TemplateDecl *TD = Arg.getAsTemplate().getAsTemplateDecl();
+        TemplateParameterList *TemplateParams = TD->getTemplateParameters();
+        for (NamedDecl *P : *TemplateParams) {
+          // If template template paramter type has an enum value template
+          // parameter, forward declaration of enum type is required. Only enum
+          // values (not types) need to be handled. For example, consider the
+          // following kernel name type:
+          //
+          // template <typename EnumTypeOut, template <EnumValueIn EnumValue,
+          // typename TypeIn> class T> class Foo;
+          //
+          // The correct specialization for Foo (with enum type) is:
+          // Foo<EnumTypeOut, Baz>, where Baz is a template class.
+          //
+          // Therefore the forward class declarations generated in the
+          // integration header are:
+          // template <EnumValueIn EnumValue, typename TypeIn> class Baz;
+          // template <typename EnumTypeOut, template <EnumValueIn EnumValue,
+          // typename EnumTypeIn> class T> class Foo;
+          //
+          // This requires the following enum forward declarations:
+          // enum class EnumTypeOut : int; (Used to template Foo)
+          // enum class EnumValueIn : int; (Used to template Baz)
+          if (NonTypeTemplateParmDecl *TemplateParam =
+                  dyn_cast<NonTypeTemplateParmDecl>(P)) {
+            QualType T = TemplateParam->getType();
+            if (const auto *ET = T->getAs<EnumType>()) {
+              const EnumDecl *ED = ET->getDecl();
+              if (!checkEnumTemplateParameter(ED, Diag, KernelLocation))
+                emitFwdDecl(O, ED, KernelLocation);
+            }
+          }
+        }
         if (Printed.insert(TD).second) {
           emitFwdDecl(O, TD, KernelLocation);
         }
@@ -1923,6 +1955,11 @@ static void printArgument(ASTContext &Ctx, raw_ostream &ArgOS,
     ArgOS << getKernelNameTypeString(T, Ctx, TypePolicy);
     break;
   }
+  case TemplateArgument::ArgKind::Template: {
+    TemplateDecl *TD = Arg.getAsTemplate().getAsTemplateDecl();
+    ArgOS << TD->getQualifiedNameAsString();
+    break;
+  }
   default:
     Arg.print(P, ArgOS);
   }
diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index 0908218e98b8..b4f1a7bfb01b 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -7967,6 +7967,8 @@ static bool isAddressSpaceKind(const ParsedAttr &attr) {
   return attrKind == ParsedAttr::AT_AddressSpace ||
          attrKind == ParsedAttr::AT_OpenCLPrivateAddressSpace ||
          attrKind == ParsedAttr::AT_OpenCLGlobalAddressSpace ||
+         attrKind == ParsedAttr::AT_OpenCLGlobalDeviceAddressSpace ||
+         attrKind == ParsedAttr::AT_OpenCLGlobalHostAddressSpace ||
          attrKind == ParsedAttr::AT_OpenCLLocalAddressSpace ||
          attrKind == ParsedAttr::AT_OpenCLConstantAddressSpace ||
          attrKind == ParsedAttr::AT_OpenCLGenericAddressSpace;
@@ -8048,6 +8050,8 @@ static void processTypeAttrs(TypeProcessingState &state, QualType &type,
       break;
     case ParsedAttr::AT_OpenCLPrivateAddressSpace:
     case ParsedAttr::AT_OpenCLGlobalAddressSpace:
+    case ParsedAttr::AT_OpenCLGlobalDeviceAddressSpace:
+    case ParsedAttr::AT_OpenCLGlobalHostAddressSpace:
     case ParsedAttr::AT_OpenCLLocalAddressSpace:
     case ParsedAttr::AT_OpenCLConstantAddressSpace:
     case ParsedAttr::AT_OpenCLGenericAddressSpace:
diff --git a/clang/test/AST/language_address_space_attribute.cpp b/clang/test/AST/language_address_space_attribute.cpp
index f9ab4612320b..c6977212e60f 100644
--- a/clang/test/AST/language_address_space_attribute.cpp
+++ b/clang/test/AST/language_address_space_attribute.cpp
@@ -10,6 +10,18 @@ void langas() {
   // CHECK: VarDecl {{.*}} z_global '__global int *'
   [[clang::opencl_global]] int *z_global;
 
+  // CHECK: VarDecl {{.*}} x_global_device '__global_device int *'
+  __attribute__((opencl_global_device)) int *x_global_device;
+
+  // CHECK: VarDecl {{.*}} z_global_device '__global_device int *'
+  [[clang::opencl_global_device]] int *z_global_device;
+
+  // CHECK: VarDecl {{.*}} x_global_host '__global_host int *'
+  __attribute__((opencl_global_host)) int *x_global_host;
+
+  // CHECK: VarDecl {{.*}} z_global_host '__global_host int *'
+  [[clang::opencl_global_host]] int *z_global_host;
+
   // CHECK: VarDecl {{.*}} x_local '__local int *'
   __attribute__((opencl_local)) int *x_local;
 
diff --git a/clang/test/CodeGenCXX/mangle-address-space.cpp b/clang/test/CodeGenCXX/mangle-address-space.cpp
index 2c5cdfc3dadb..71bfb68b9a4a 100644
--- a/clang/test/CodeGenCXX/mangle-address-space.cpp
+++ b/clang/test/CodeGenCXX/mangle-address-space.cpp
@@ -43,6 +43,10 @@ void ocl_f0(char __private *p) { }
 
 struct ocl_OpaqueType;
 typedef ocl_OpaqueType __global * ocl_OpaqueTypePtr;
+typedef ocl_OpaqueType __attribute__((opencl_global_host)) * ocl_OpaqueTypePtrH;
+typedef ocl_OpaqueType
+    __attribute__((opencl_global_device)) *
+    ocl_OpaqueTypePtrD;
 
 // CHECKOCL-LABEL: define {{.*}}void @_Z6ocl_f0PU8CLglobal14ocl_OpaqueType
 // WINOCL-LABEL: define {{.*}}void @"?ocl_f0@@YAXPEAU?$_ASCLglobal@$$CAUocl_OpaqueType@@@__clang@@@Z"
@@ -61,4 +65,12 @@ __constant float *ocl_f1(char __generic const *p) { return 0;}
 // CHECKOCL-LABEL: define {{.*}}float* @_Z6ocl_f2PU9CLgenericKc
 // WINOCL-LABEL: define {{.*}}float* @"?ocl_f2@@YAPEAU?$_ASCLgeneric@$$CAM@__clang@@QEAU?$_ASCLgeneric@$$CBD@2@@Z"
 __generic float *ocl_f2(__generic char const * const p) { return 0;}
+
+// CHECKOCL-LABEL: define {{.*}}void @_Z6ocl_f3PU6CLHost14ocl_OpaqueType
+// WINOCL-LABEL: define {{.*}}void @"?ocl_f3@@YAXPEAU?$_ASCLHost@$$CAUocl_OpaqueType@@@__clang@@@Z"
+void ocl_f3(ocl_OpaqueTypePtrH) {}
+
+// CHECKOCL-LABEL: define {{.*}}void @_Z6ocl_f4PU8CLDevice14ocl_OpaqueType
+// WINOCL-LABEL: define {{.*}}void @"?ocl_f4@@YAXPEAU?$_ASCLDevice@$$CAUocl_OpaqueType@@@__clang@@@Z"
+void ocl_f4(ocl_OpaqueTypePtrD) {}
 #endif
diff --git a/clang/test/CodeGenSYCL/address-space-parameter-conversions.cpp b/clang/test/CodeGenSYCL/address-space-parameter-conversions.cpp
index 264e787a80d2..f62c6c8b1071 100644
--- a/clang/test/CodeGenSYCL/address-space-parameter-conversions.cpp
+++ b/clang/test/CodeGenSYCL/address-space-parameter-conversions.cpp
@@ -5,12 +5,16 @@ void bar2(int & Data) {}
 // CHECK-DAG: define spir_func void @[[RAW_REF2:[a-zA-Z0-9_]+]](i32 addrspace(4)* align 4 dereferenceable(4) %
 void bar(__attribute__((opencl_local)) int &Data) {}
 // CHECK-DAG: define spir_func void [[LOC_REF:@[a-zA-Z0-9_]+]](i32 addrspace(3)* align 4 dereferenceable(4) %
+void bar3(__attribute__((opencl_global)) int &Data) {}
+// CHECK-DAG: define spir_func void @[[GLOB_REF:[a-zA-Z0-9_]+]](i32 addrspace(1)* align 4 dereferenceable(4) %
 void foo(int * Data) {}
 // CHECK-DAG: define spir_func void @[[RAW_PTR:[a-zA-Z0-9_]+]](i32 addrspace(4)* %
 void foo2(int * Data) {}
 // CHECK-DAG: define spir_func void @[[RAW_PTR2:[a-zA-Z0-9_]+]](i32 addrspace(4)* %
 void foo(__attribute__((opencl_local)) int *Data) {}
 // CHECK-DAG: define spir_func void [[LOC_PTR:@[a-zA-Z0-9_]+]](i32 addrspace(3)* %
+void foo3(__attribute__((opencl_global)) int *Data) {}
+// CHECK-DAG: define spir_func void @[[GLOB_PTR:[a-zA-Z0-9_]+]](i32 addrspace(1)* %
 
 template<typename T>
 void tmpl(T t){}
@@ -19,6 +23,10 @@ void tmpl(T t){}
 void usages() {
   // CHECK-DAG: [[GLOB:%[a-zA-Z0-9]+]] = alloca i32 addrspace(1)*
   __attribute__((opencl_global)) int *GLOB;
+  // CHECK-DAG: [[GLOBDEV:%[a-zA-Z0-9]+]] = alloca i32 addrspace(11)*
+  __attribute__((opencl_global_device)) int *GLOBDEV;
+  // CHECK-DAG: [[GLOBHOST:%[a-zA-Z0-9]+]] = alloca i32 addrspace(12)*
+  __attribute__((opencl_global_host)) int *GLOBHOST;
   // CHECK-DAG: [[LOC:%[a-zA-Z0-9]+]] = alloca i32 addrspace(3)*
   __attribute__((opencl_local)) int *LOC;
   // CHECK-DAG: [[NoAS:%[a-zA-Z0-9]+]] = alloca i32 addrspace(4)*
@@ -35,6 +43,32 @@ void usages() {
   // CHECK-DAG: [[GLOB_CAST2:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD2]] to i32 addrspace(4)*
   // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOB_CAST2]])
 
+  bar(*GLOBDEV);
+  // CHECK-DAG: [[GLOBDEV_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(11)*, i32 addrspace(11)** [[GLOBDEV]]
+  // CHECK-DAG: [[GLOBDEV_CAST:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(11)* [[GLOBDEV_LOAD]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOBDEV_CAST]])
+  bar2(*GLOBDEV);
+  // CHECK-DAG: [[GLOBDEV_LOAD2:%[a-zA-Z0-9]+]] = load i32 addrspace(11)*, i32 addrspace(11)** [[GLOBDEV]]
+  // CHECK-DAG: [[GLOBDEV_CAST2:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(11)* [[GLOBDEV_LOAD2]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOBDEV_CAST2]])
+  bar3(*GLOBDEV);
+  // CHECK-DAG: [[GLOBDEV_LOAD3:%[a-zA-Z0-9]+]] = load i32 addrspace(11)*, i32 addrspace(11)** [[GLOBDEV]]
+  // CHECK-DAG: [[GLOBDEV_CAST3:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(11)* [[GLOBDEV_LOAD3]] to i32 addrspace(1)*
+  // CHECK-DAG: call spir_func void @[[GLOB_REF]](i32 addrspace(1)* align 4 dereferenceable(4) [[GLOBDEV_CAST3]])
+
+  bar(*GLOBHOST);
+  // CHECK-DAG: [[GLOBHOST_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(12)*, i32 addrspace(12)** [[GLOBHOST]]
+  // CHECK-DAG: [[GLOBHOST_CAST:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(12)* [[GLOBHOST_LOAD]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOBHOST_CAST]])
+  bar2(*GLOBHOST);
+  // CHECK-DAG: [[GLOBHOST_LOAD2:%[a-zA-Z0-9]+]] = load i32 addrspace(12)*, i32 addrspace(12)** [[GLOBHOST]]
+  // CHECK-DAG: [[GLOBHOST_CAST2:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(12)* [[GLOBHOST_LOAD2]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOBHOST_CAST2]])
+  bar3(*GLOBHOST);
+  // CHECK-DAG: [[GLOBHOST_LOAD3:%[a-zA-Z0-9]+]] = load i32 addrspace(12)*, i32 addrspace(12)** [[GLOBHOST]]
+  // CHECK-DAG: [[GLOBHOST_CAST3:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(12)* [[GLOBHOST_LOAD3]] to i32 addrspace(1)*
+  // CHECK-DAG: call spir_func void @[[GLOB_REF]](i32 addrspace(1)* align 4 dereferenceable(4) [[GLOBHOST_CAST3]])
+
   bar(*LOC);
   // CHECK-DAG: [[LOC_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)** [[LOC]]
   // CHECK-DAG: call spir_func void [[LOC_REF]](i32 addrspace(3)* align 4 dereferenceable(4) [[LOC_LOAD]])
@@ -58,6 +92,30 @@ void usages() {
   // CHECK-DAG: [[GLOB_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)** [[GLOB]]
   // CHECK-DAG: [[GLOB_CAST4:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD4]] to i32 addrspace(4)*
   // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[GLOB_CAST4]])
+  foo(GLOBDEV);
+  // CHECK-DAG: [[GLOBDEV_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(11)*, i32 addrspace(11)** [[GLOBDEV]]
+  // CHECK-DAG: [[GLOBDEV_CAST4:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(11)* [[GLOBDEV_LOAD4]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* [[GLOBDEV_CAST4]])
+  foo2(GLOBDEV);
+  // CHECK-DAG: [[GLOBDEV_LOAD5:%[a-zA-Z0-9]+]] = load i32 addrspace(11)*, i32 addrspace(11)** [[GLOBDEV]]
+  // CHECK-DAG: [[GLOBDEV_CAST5:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(11)* [[GLOBDEV_LOAD5]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[GLOBDEV_CAST5]])
+  foo3(GLOBDEV);
+  // CHECK-DAG: [[GLOBDEV_LOAD6:%[a-zA-Z0-9]+]] = load i32 addrspace(11)*, i32 addrspace(11)** [[GLOBDEV]]
+  // CHECK-DAG: [[GLOBDEV_CAST6:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(11)* [[GLOBDEV_LOAD6]] to i32 addrspace(1)*
+  // CHECK-DAG: call spir_func void @[[GLOB_PTR]](i32 addrspace(1)* [[GLOBDEV_CAST6]])
+  foo(GLOBHOST);
+  // CHECK-DAG: [[GLOBHOST_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(12)*, i32 addrspace(12)** [[GLOBHOST]]
+  // CHECK-DAG: [[GLOBHOST_CAST4:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(12)* [[GLOBHOST_LOAD4]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* [[GLOBHOST_CAST4]])
+  foo2(GLOBHOST);
+  // CHECK-DAG: [[GLOBHOST_LOAD5:%[a-zA-Z0-9]+]] = load i32 addrspace(12)*, i32 addrspace(12)** [[GLOBHOST]]
+  // CHECK-DAG: [[GLOBHOST_CAST5:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(12)* [[GLOBHOST_LOAD5]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[GLOBHOST_CAST5]])
+  foo3(GLOBHOST);
+  // CHECK-DAG: [[GLOBHOST_LOAD6:%[a-zA-Z0-9]+]] = load i32 addrspace(12)*, i32 addrspace(12)** [[GLOBHOST]]
+  // CHECK-DAG: [[GLOBHOST_CAST6:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(12)* [[GLOBHOST_LOAD6]] to i32 addrspace(1)*
+  // CHECK-DAG: call spir_func void @[[GLOB_PTR]](i32 addrspace(1)* [[GLOBHOST_CAST6]])
   foo(LOC);
   // CHECK-DAG: [[LOC_LOAD3:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)** [[LOC]]
   // CHECK-DAG: call spir_func void [[LOC_PTR]](i32 addrspace(3)* [[LOC_LOAD3]])
@@ -72,10 +130,16 @@ void usages() {
   // CHECK-DAG: [[NoAS_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)** [[NoAS]]
   // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[NoAS_LOAD4]])
 
-  // Ensure that we still get 3 different template instantiations.
+  // Ensure that we still get 5 different template instantiations.
   tmpl(GLOB);
   // CHECK-DAG: [[GLOB_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)** [[GLOB]]
   // CHECK-DAG: call spir_func void [[GLOB_TMPL:@[a-zA-Z0-9_]+]](i32 addrspace(1)* [[GLOB_LOAD4]])
+  tmpl(GLOBDEV);
+  // CHECK-DAG: [[GLOBDEV_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(11)*, i32 addrspace(11)** [[GLOBDEV]]
+  // CHECK-DAG: call spir_func void [[GLOBDEV_TMPL:@[a-zA-Z0-9_]+]](i32 addrspace(11)* [[GLOBDEV_LOAD4]])
+  tmpl(GLOBHOST);
+  // CHECK-DAG: [[GLOBHOST_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(12)*, i32 addrspace(12)** [[GLOBHOST]]
+  // CHECK-DAG: call spir_func void [[GLOBHOST_TMPL:@[a-zA-Z0-9_]+]](i32 addrspace(12)* [[GLOBHOST_LOAD4]])
   tmpl(LOC);
   // CHECK-DAG: [[LOC_LOAD5:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)** [[LOC]]
   // CHECK-DAG: call spir_func void [[LOC_TMPL:@[a-zA-Z0-9_]+]](i32 addrspace(3)* [[LOC_LOAD5]])
@@ -88,6 +152,8 @@ void usages() {
 }
 
 // CHECK-DAG: define linkonce_odr spir_func void [[GLOB_TMPL]](i32 addrspace(1)* %
+// CHECK-DAG: define linkonce_odr spir_func void [[GLOBDEV_TMPL]](i32 addrspace(11)* %
+// CHECK-DAG: define linkonce_odr spir_func void [[GLOBHOST_TMPL]](i32 addrspace(12)* %
 // CHECK-DAG: define linkonce_odr spir_func void [[LOC_TMPL]](i32 addrspace(3)* %
 // CHECK-DAG: define linkonce_odr spir_func void [[PRIV_TMPL]](i32* %
 // CHECK-DAG: define linkonce_odr spir_func void [[GEN_TMPL]](i32 addrspace(4)* %
@@ -97,6 +163,10 @@ void usages2() {
   // CHECK-DAG: [[PRIV:%[a-zA-Z0-9_]+]] = alloca i32*
   __attribute__((opencl_global)) int *GLOB;
   // CHECK-DAG: [[GLOB:%[a-zA-Z0-9_]+]] = alloca i32 addrspace(1)*
+  __attribute__((opencl_global_device)) int *GLOBDEV;
+  // CHECK-DAG: [[GLOBDEV:%[a-zA-Z0-9_]+]] = alloca i32 addrspace(11)*
+  __attribute__((opencl_global_host)) int *GLOBHOST;
+  // CHECK-DAG: [[GLOBHOST:%[a-zA-Z0-9_]+]] = alloca i32 addrspace(12)*
   __attribute__((opencl_constant)) int *CONST;
   // CHECK-DAG: [[CONST:%[a-zA-Z0-9_]+]] = alloca i32 addrspace(2)*
   __attribute__((opencl_local)) int *LOCAL;
@@ -110,6 +180,14 @@ void usages2() {
   // CHECK-DAG: [[GLOB_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)** [[GLOB]]
   // CHECK-DAG: [[GLOB_CAST:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD]] to i32 addrspace(4)*
   // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOB_CAST]])
+  bar(*GLOBDEV);
+  // CHECK-DAG: [[GLOBDEV_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(11)*, i32 addrspace(11)** [[GLOBDEV]]
+  // CHECK-DAG: [[GLOBDEV_CAST:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(11)* [[GLOBDEV_LOAD]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOBDEV_CAST]])
+  bar(*GLOBHOST);
+  // CHECK-DAG: [[GLOBHOST_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(12)*, i32 addrspace(12)** [[GLOBHOST]]
+  // CHECK-DAG: [[GLOBHOST_CAST:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(12)* [[GLOBHOST_LOAD]] to i32 addrspace(4)*
+  // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOBHOST_CAST]])
   bar2(*LOCAL);
   // CHECK-DAG: [[LOCAL_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)** [[LOCAL]]
   // CHECK-DAG: [[LOCAL_CAST:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(3)* [[LOCAL_LOAD]] to i32 addrspace(4)*
diff --git a/clang/test/CodeGenSYCL/kernelname-enum.cpp b/clang/test/CodeGenSYCL/kernelname-enum.cpp
index 38200b50ada7..381067451d7e 100644
--- a/clang/test/CodeGenSYCL/kernelname-enum.cpp
+++ b/clang/test/CodeGenSYCL/kernelname-enum.cpp
@@ -94,6 +94,20 @@ class T2 {};
 template <typename EnumType>
 class T3 {};
 
+enum class EnumTypeOut : int { A,
+                               B,
+};
+enum class EnumValueIn : int { A,
+                               B,
+};
+template <EnumValueIn EnumValue, typename EnumTypeIn>
+class Baz;
+template <typename EnumTypeOut, template <EnumValueIn EnumValue, typename EnumTypeIn> class T>
+class dummy_functor_8 {
+public:
+  void operator()() {}
+};
+
 int main() {
 
   dummy_functor_1<no_namespace_int::val_1> f1;
@@ -104,6 +118,7 @@ int main() {
   dummy_functor_6<unscoped_enum::val_1> f6;
   dummy_functor_7<no_namespace_int> f7;
   dummy_functor_7<internal::namespace_short> f8;
+  dummy_functor_8<EnumTypeOut, Baz> f9;
 
   cl::sycl::queue q;
 
@@ -147,6 +162,10 @@ int main() {
     cgh.single_task<T1<T3<type_argument_template_enum::E>>>([=]() {});
   });
 
+  q.submit([&](cl::sycl::handler &cgh) {
+    cgh.single_task(f9);
+  });
+
   return 0;
 }
 
@@ -173,6 +192,10 @@ int main() {
 // CHECK-NEXT: }
 // CHECK: template <type_argument_template_enum::E EnumValue> class T2;
 // CHECK: template <typename T> class T1;
+// CHECK: enum class EnumTypeOut : int;
+// CHECK: enum class EnumValueIn : int;
+// CHECK: template <EnumValueIn EnumValue, typename EnumTypeIn> class Baz;
+// CHECK: template <typename EnumTypeOut, template <EnumValueIn EnumValue, typename EnumTypeIn> class T> class dummy_functor_8;
 // CHECK: Specializations of KernelInfo for kernel function types:
 // CHECK: template <> struct KernelInfo<::dummy_functor_1<(no_namespace_int)0>>
 // CHECK: template <> struct KernelInfo<::dummy_functor_2<(no_namespace_short)1>>
@@ -184,3 +207,4 @@ int main() {
 // CHECK: template <> struct KernelInfo<::dummy_functor_7<::internal::namespace_short>>
 // CHECK: template <> struct KernelInfo<::T1<::T2<(type_argument_template_enum::E)0>>>
 // CHECK: template <> struct KernelInfo<::T1<::T3<::type_argument_template_enum::E>>>
+// CHECK: template <> struct KernelInfo<::dummy_functor_8<::EnumTypeOut, Baz>>
diff --git a/clang/test/Driver/sycl-esimd.cpp b/clang/test/Driver/sycl-esimd.cpp
new file mode 100644
index 000000000000..762905196681
--- /dev/null
+++ b/clang/test/Driver/sycl-esimd.cpp
@@ -0,0 +1,10 @@
+/// Check that explicit SIMD extension is disabled by default:
+// RUN: %clang -### %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-DEFAULT %s
+// CHECK-DEFAULT-NOT: "-fsycl-explicit-simd"
+
+/// Check "-fsycl-explicit-simd" is passed when compiling for device and host:
+// RUN: %clang -### -fsycl -fsycl-explicit-simd %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-SYCL-ESIMD %s
+// CHECK-SYCL-ESIMD: "-cc1"{{.*}} "-fsycl-explicit-simd"{{.*}}
+// CHECK-SYCL-ESIMD: "-cc1"{{.*}} "-fsycl-explicit-simd"{{.*}}
diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
index f41956cf663a..63619e6e2051 100644
--- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test
+++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
@@ -66,7 +66,6 @@
 // CHECK-NEXT: IBAction (SubjectMatchRule_objc_method_is_instance)
 // CHECK-NEXT: IFunc (SubjectMatchRule_function)
 // CHECK-NEXT: InitPriority (SubjectMatchRule_variable)
-// CHECK-NEXT: IntelReqdSubGroupSize (SubjectMatchRule_function, SubjectMatchRule_function_is_member)
 // CHECK-NEXT: InternalLinkage (SubjectMatchRule_variable, SubjectMatchRule_function, SubjectMatchRule_record)
 // CHECK-NEXT: LTOVisibilityPublic (SubjectMatchRule_record)
 // CHECK-NEXT: LoaderUninitialized (SubjectMatchRule_variable_is_global)
@@ -141,9 +140,6 @@
 // CHECK-NEXT: ReturnTypestate (SubjectMatchRule_function, SubjectMatchRule_variable_is_parameter)
 // CHECK-NEXT: ReturnsNonNull (SubjectMatchRule_objc_method, SubjectMatchRule_function)
 // CHECK-NEXT: ReturnsTwice (SubjectMatchRule_function)
-// CHECK-NEXT: SYCLDevice (SubjectMatchRule_function)
-// CHECK-NEXT: SYCLDeviceIndirectlyCallable (SubjectMatchRule_function)
-// CHECK-NEXT: SYCLIntelKernelArgsRestrict (SubjectMatchRule_function)
 // CHECK-NEXT: ScopedLockable (SubjectMatchRule_record)
 // CHECK-NEXT: Section (SubjectMatchRule_function, SubjectMatchRule_variable_is_global, SubjectMatchRule_objc_method, SubjectMatchRule_objc_property)
 // CHECK-NEXT: SetTypestate (SubjectMatchRule_function_is_member)
diff --git a/clang/test/SemaSYCL/address-space-parameter-conversions.cpp b/clang/test/SemaSYCL/address-space-parameter-conversions.cpp
index 3f2be32d76fc..8dd54d3db23b 100644
--- a/clang/test/SemaSYCL/address-space-parameter-conversions.cpp
+++ b/clang/test/SemaSYCL/address-space-parameter-conversions.cpp
@@ -3,15 +3,19 @@
 void bar(int & Data) {}
 void bar2(int & Data) {}
 void bar(__attribute__((opencl_private)) int  & Data) {}
+void bar3(__attribute__((opencl_global)) int &Data) {}
 void foo(int * Data) {}
 void foo2(int * Data) {}
 void foo(__attribute__((opencl_private)) int * Data) {}
+void foo3(__attribute__((opencl_global)) int *Data) {}
 
 template<typename T>
 void tmpl(T *t){}
 
 void usages() {
   __attribute__((opencl_global)) int *GLOB;
+  __attribute__((opencl_global_device)) int *GLOBDEV;
+  __attribute__((opencl_global_host)) int *GLOBHOST;
   __attribute__((opencl_private)) int *PRIV;
   __attribute__((opencl_local)) int *LOC;
   int *NoAS;
@@ -19,6 +23,14 @@ void usages() {
   bar(*GLOB);
   bar2(*GLOB);
 
+  bar(*GLOBDEV);
+  bar2(*GLOBDEV);
+  bar3(*GLOBDEV);
+
+  bar(*GLOBHOST);
+  bar2(*GLOBHOST);
+  bar3(*GLOBHOST);
+
   bar(*PRIV);
   bar2(*PRIV);
 
@@ -30,6 +42,12 @@ void usages() {
 
   foo(GLOB);
   foo2(GLOB);
+  foo(GLOBDEV);
+  foo2(GLOBDEV);
+  foo3(GLOBDEV);
+  foo(GLOBDEV);
+  foo2(GLOBHOST);
+  foo3(GLOBHOST);
   foo(PRIV);
   foo2(PRIV);
   foo(NoAS);
@@ -38,12 +56,18 @@ void usages() {
   foo2(LOC);
 
   tmpl(GLOB);
+  tmpl(GLOBDEV);
+  tmpl(GLOBHOST);
   tmpl(PRIV);
   tmpl(NoAS);
   tmpl(LOC);
 
   (void)static_cast<int*>(GLOB);
   (void)static_cast<void*>(GLOB);
+  (void)static_cast<int *>(GLOBDEV);
+  (void)static_cast<void *>(GLOBDEV);
+  (void)static_cast<int *>(GLOBHOST);
+  (void)static_cast<void *>(GLOBHOST);
   // FIXME: determine if we can warn on the below conversions.
   int *i = GLOB;
   void *v = GLOB;
diff --git a/clang/test/SemaSYCL/check-long-double-size.cpp b/clang/test/SemaSYCL/check-long-double-size.cpp
new file mode 100644
index 000000000000..62ec21b36fca
--- /dev/null
+++ b/clang/test/SemaSYCL/check-long-double-size.cpp
@@ -0,0 +1,7 @@
+// RUN: %clang_cc1 -fsycl -fsycl-is-device -triple spir64-unknown-unknown-sycldevice -aux-triple x86_64-unknown-linux-gnu -fsyntax-only -DLONG_DOUBLE_SIZE=16 -verify %s
+// RUN: %clang_cc1 -fsycl -fsycl-is-device -triple spir-unknown-unknown-sycldevice -aux-triple i386-pc-linux-gnu -fsyntax-only -DLONG_DOUBLE_SIZE=12 -verify %s
+// RUN: %clang_cc1 -fsycl -fsycl-is-device -triple spir64-unknown-windows-sycldevice -aux-triple x86_64-pc-windows-msvc -fsyntax-only -DLONG_DOUBLE_SIZE=8 -verify %s
+// RUN: %clang_cc1 -fsycl -fsycl-is-device -triple spir-unknown-windows-sycldevice -aux-triple i686-pc-windows-msvc -fsyntax-only -DLONG_DOUBLE_SIZE=8 -verify %s
+// expected-no-diagnostics
+
+static_assert(sizeof(long double) == LONG_DOUBLE_SIZE, "wrong sizeof long double");
diff --git a/clang/test/SemaTemplate/address_space-dependent.cpp b/clang/test/SemaTemplate/address_space-dependent.cpp
index 76cd338769ea..fa6cc68bba41 100644
--- a/clang/test/SemaTemplate/address_space-dependent.cpp
+++ b/clang/test/SemaTemplate/address_space-dependent.cpp
@@ -43,7 +43,7 @@ void neg() {
 
 template <long int I>
 void tooBig() {
-  __attribute__((address_space(I))) int *bounds; // expected-error {{address space is larger than the maximum supported (8388595)}}
+  __attribute__((address_space(I))) int *bounds; // expected-error {{address space is larger than the maximum supported (8388593)}}
 }
 
 template <long int I>
diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt
index 88ace62145e0..471ef36d1230 100644
--- a/libclc/CMakeLists.txt
+++ b/libclc/CMakeLists.txt
@@ -45,8 +45,13 @@ set( LIBCLC_TARGETS_ALL
   nvptx--nvidiacl
   nvptx64--nvidiacl
 )
+set( LIBCLC_TEST_TARGETS_ALL
+  nvptx--nvidiacl
+  nvptx64--nvidiacl
+)
 
 set( LIBCLC_ROOT_DIR ${CMAKE_CURRENT_SOURCE_DIR} )
+set( LIBCLC_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR} )
 
 set( LIBCLC_TARGETS_TO_BUILD "all"
     CACHE STRING "Semicolon-separated list of targets to build, or 'all'." )
@@ -65,6 +70,14 @@ endif()
 
 list( SORT LIBCLC_TARGETS_TO_BUILD )
 
+set(LIBCLC_TARGET_TO_TEST)
+
+foreach ( t ${LIBCLC_TEST_TARGETS_ALL})
+	if( ${t} IN_LIST LIBCLC_TARGETS_TO_BUILD )
+		list( APPEND LIBCLC_TARGET_TO_TEST "${t}" )
+	endif(t)
+endforeach(t)
+
 execute_process( COMMAND ${LLVM_CONFIG} "--system-libs"
 	OUTPUT_VARIABLE LLVM_SYSTEM_LIBS
 	OUTPUT_STRIP_TRAILING_WHITESPACE )
@@ -261,3 +274,5 @@ install(DIRECTORY ${LIBCLC_LIBRARY_OUTPUT_INTDIR}
 				DESTINATION lib${LLVM_LIBDIR_SUFFIX}
 				COMPONENT clc-builtins
 				FILES_MATCHING PATTERN "clc-*")
+
+add_subdirectory(test)
diff --git a/libclc/generic/include/clc/async/gentype.inc b/libclc/generic/include/clc/async/gentype.inc
index c570608f7a80..2af91bfb9641 100644
--- a/libclc/generic/include/clc/async/gentype.inc
+++ b/libclc/generic/include/clc/async/gentype.inc
@@ -11,6 +11,16 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE char3
+#define __CLC_GENTYPE_U uchar3
+#define __CLC_GENTYPE_MANGLED Dv3_c
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE_U
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE char4
 #define __CLC_GENTYPE_MANGLED Dv4_c
 #include __CLC_BODY
@@ -29,6 +39,46 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifndef __CLC_NO_SCHAR
+#define __CLC_GENTYPE schar
+#define __CLC_GENTYPE_MANGLED a
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+
+#define __CLC_GENTYPE schar2
+#define __CLC_GENTYPE_MANGLED Dv2_a
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE schar3
+#define __CLC_GENTYPE_MANGLED Dv3_a
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
+#define __CLC_GENTYPE schar4
+#define __CLC_GENTYPE_MANGLED Dv4_a
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+
+#define __CLC_GENTYPE schar8
+#define __CLC_GENTYPE_MANGLED Dv8_a
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+
+#define __CLC_GENTYPE schar16
+#define __CLC_GENTYPE_MANGLED Dv16_a
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE uchar
 #define __CLC_GENTYPE_MANGLED h
 #include __CLC_BODY
@@ -41,6 +91,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE uchar3
+#define __CLC_GENTYPE_MANGLED Dv3_h
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE uchar4
 #define __CLC_GENTYPE_MANGLED Dv4_h
 #include __CLC_BODY
@@ -71,6 +129,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE short3
+#define __CLC_GENTYPE_MANGLED Dv3_s
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE short4
 #define __CLC_GENTYPE_MANGLED Dv4_s
 #include __CLC_BODY
@@ -101,6 +167,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE ushort3
+#define __CLC_GENTYPE_MANGLED Dv3_t
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE ushort4
 #define __CLC_GENTYPE_MANGLED Dv4_t
 #include __CLC_BODY
@@ -131,6 +205,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE int3
+#define __CLC_GENTYPE_MANGLED Dv3_i
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE int4
 #define __CLC_GENTYPE_MANGLED Dv4_i
 #include __CLC_BODY
@@ -161,6 +243,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE uint3
+#define __CLC_GENTYPE_MANGLED Dv3_j
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE uint4
 #define __CLC_GENTYPE_MANGLED Dv4_j
 #include __CLC_BODY
@@ -191,6 +281,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE float3
+#define __CLC_GENTYPE_MANGLED Dv3_f
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE float4
 #define __CLC_GENTYPE_MANGLED Dv4_f
 #include __CLC_BODY
@@ -221,6 +319,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE long3
+#define __CLC_GENTYPE_MANGLED Dv3_l
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE long4
 #define __CLC_GENTYPE_MANGLED Dv4_l
 #include __CLC_BODY
@@ -251,6 +357,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE ulong3
+#define __CLC_GENTYPE_MANGLED Dv3_m
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE ulong4
 #define __CLC_GENTYPE_MANGLED Dv4_m
 #include __CLC_BODY
@@ -284,6 +398,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE double3
+#define __CLC_GENTYPE_MANGLED Dv3_d
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE double4
 #define __CLC_GENTYPE_MANGLED Dv4_d
 #include __CLC_BODY
@@ -319,6 +441,14 @@
 #undef __CLC_GENTYPE_MANGLED
 #undef __CLC_GENTYPE
 
+#ifdef __CLC_GEN_VEC3
+#define __CLC_GENTYPE half3
+#define __CLC_GENTYPE_MANGLED Dv3_h
+#include __CLC_BODY
+#undef __CLC_GENTYPE_MANGLED
+#undef __CLC_GENTYPE
+#endif
+
 #define __CLC_GENTYPE half4
 #define __CLC_GENTYPE_MANGLED Dv4_Dh
 #include __CLC_BODY
diff --git a/libclc/generic/include/spirv/async/async_work_group_strided_copy.h b/libclc/generic/include/spirv/async/async_work_group_strided_copy.h
deleted file mode 100644
index 3b068241266f..000000000000
--- a/libclc/generic/include/spirv/async/async_work_group_strided_copy.h
+++ /dev/null
@@ -1,38 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#define __CLC_CONCAT(a, b, c, d, e, f, g) a ## b ## c ## d ## e ## f ## g
-#define __CLC_XCONCAT(a, b, c, d, e, f, g) __CLC_CONCAT(a, b, c, d, e, f, g)
-
-
-#define __SPIRV_DST_ADDR_SPACE local
-#define __SPIRV_DST_ADDR_SPACE_MANGLED AS3
-#define __SPIRV_SRC_ADDR_SPACE global
-#define __SPIRV_SRC_ADDR_SPACE_MANGLED AS1
-#define __SPIRV_BODY <spirv/async/async_work_group_strided_copy.inc>
-#include <spirv/async/gentype.inc>
-#undef __SPIRV_DST_ADDR_SPACE
-#undef __SPIRV_DST_ADDR_SPACE_MANGLED
-#undef __SPIRV_SRC_ADDR_SPACE
-#undef __SPIRV_SRC_ADDR_SPACE_MANGLED
-#undef __SPIRV_BODY
-
-#define __SPIRV_DST_ADDR_SPACE global
-#define __SPIRV_DST_ADDR_SPACE_MANGLED AS1
-#define __SPIRV_SRC_ADDR_SPACE local
-#define __SPIRV_SRC_ADDR_SPACE_MANGLED AS3
-#define __SPIRV_BODY <spirv/async/async_work_group_strided_copy.inc>
-#include <spirv/async/gentype.inc>
-#undef __SPIRV_DST_ADDR_SPACE
-#undef __SPIRV_DST_ADDR_SPACE_MANGLED
-#undef __SPIRV_SRC_ADDR_SPACE
-#undef __SPIRV_SRC_ADDR_SPACE_MANGLED
-#undef __SPIRV_BODY
-
-#undef __CLC_XCONCAT
-#undef __CLC_CONCAT
diff --git a/libclc/generic/include/spirv/async/async_work_group_strided_copy.inc b/libclc/generic/include/spirv/async/async_work_group_strided_copy.inc
deleted file mode 100644
index 175167103c2a..000000000000
--- a/libclc/generic/include/spirv/async/async_work_group_strided_copy.inc
+++ /dev/null
@@ -1,12 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-_CLC_OVERLOAD _CLC_DECL event_t __spirv_GroupAsyncCopy(
-    unsigned int scope, __SPIRV_DST_ADDR_SPACE __SPIRV_GENTYPE *dst,
-    const __SPIRV_SRC_ADDR_SPACE __SPIRV_GENTYPE *src, size_t num_elements,
-    size_t stride, event_t event);
diff --git a/libclc/generic/include/spirv/async/prefetch.h b/libclc/generic/include/spirv/async/prefetch.h
deleted file mode 100644
index de482347ae9a..000000000000
--- a/libclc/generic/include/spirv/async/prefetch.h
+++ /dev/null
@@ -1,11 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#define __SPIRV_BODY <spirv/async/prefetch.inc>
-#include <spirv/async/gentype.inc>
-#undef __SPIRV_BODY
diff --git a/libclc/generic/include/spirv/async/prefetch.inc b/libclc/generic/include/spirv/async/prefetch.inc
deleted file mode 100644
index 42ae7efb0939..000000000000
--- a/libclc/generic/include/spirv/async/prefetch.inc
+++ /dev/null
@@ -1,9 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_prefetch(const global __SPIRV_GENTYPE *p, size_t num_gentypes);
diff --git a/libclc/generic/include/spirv/explicit_fence/explicit_memory_fence.h b/libclc/generic/include/spirv/explicit_fence/explicit_memory_fence.h
deleted file mode 100644
index 866b5e584b9f..000000000000
--- a/libclc/generic/include/spirv/explicit_fence/explicit_memory_fence.h
+++ /dev/null
@@ -1,9 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-_CLC_DEF void __spirv_MemoryBarrier(int memory, int semantics);
diff --git a/libclc/generic/include/spirv/spirv.h b/libclc/generic/include/spirv/spirv.h
index de9c3722b985..ad30de4b187c 100644
--- a/libclc/generic/include/spirv/spirv.h
+++ b/libclc/generic/include/spirv/spirv.h
@@ -196,18 +196,6 @@
 #include <spirv/relational/select.h>
 #include <spirv/relational/signbit.h>
 
-/* 6.11.8 Synchronization Functions */
-#include <spirv/synchronization/barrier.h>
-
-/* 6.11.9 Explicit Memory Fence Functions */
-#include <spirv/explicit_fence/explicit_memory_fence.h>
-
-/* 6.11.10 Async Copy and Prefetch Functions */
-/* #include <spirv/async/async_work_group_copy.h> -- Explicitly omitted from SPIR-V interface. */
-#include <spirv/async/async_work_group_strided_copy.h>
-#include <spirv/async/prefetch.h>
-#include <spirv/async/wait_group_events.h>
-
 /* 6.11.11 Atomic Functions */
 #include <spirv/atomic/atomic_add.h>
 #include <spirv/atomic/atomic_and.h>
diff --git a/libclc/generic/include/spirv/spirv_builtins.h b/libclc/generic/include/spirv/spirv_builtins.h
index 049f60d00a8d..946bbbf7bc72 100644
--- a/libclc/generic/include/spirv/spirv_builtins.h
+++ b/libclc/generic/include/spirv/spirv_builtins.h
@@ -12,6 +12,9 @@
 #ifndef CLC_SPIRV_BINDING
 #define CLC_SPIRV_BINDING
 
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT void
+    __spirv_ControlBarrier(__clc_uint32_t, __clc_uint32_t, __clc_uint32_t);
+
 _CLC_OVERLOAD
 _CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_ConvertFToS_Rchar(__clc_fp32_t);
 
@@ -9132,6 +9135,571 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t
 #endif
 #endif
 
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_char_t __local *, __clc_char_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_char_t __global *, __clc_char_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_char_t __local *,
+                       __clc_vec2_char_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_char_t __global *,
+                       __clc_vec2_char_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_char_t __local *,
+                       __clc_vec3_char_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_char_t __global *,
+                       __clc_vec3_char_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_char_t __local *,
+                       __clc_vec4_char_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_char_t __global *,
+                       __clc_vec4_char_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_char_t __local *,
+                       __clc_vec8_char_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_char_t __global *,
+                       __clc_vec8_char_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_char_t __local *,
+                       __clc_vec16_char_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_char_t __global *,
+                       __clc_vec16_char_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_int8_t __local *, __clc_int8_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_int8_t __global *, __clc_int8_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int8_t __local *,
+                       __clc_vec2_int8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int8_t __global *,
+                       __clc_vec2_int8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int8_t __local *,
+                       __clc_vec3_int8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int8_t __global *,
+                       __clc_vec3_int8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int8_t __local *,
+                       __clc_vec4_int8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int8_t __global *,
+                       __clc_vec4_int8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int8_t __local *,
+                       __clc_vec8_int8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int8_t __global *,
+                       __clc_vec8_int8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int8_t __local *,
+                       __clc_vec16_int8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int8_t __global *,
+                       __clc_vec16_int8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_int16_t __local *, __clc_int16_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_int16_t __global *, __clc_int16_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int16_t __local *,
+                       __clc_vec2_int16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int16_t __global *,
+                       __clc_vec2_int16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int16_t __local *,
+                       __clc_vec3_int16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int16_t __global *,
+                       __clc_vec3_int16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int16_t __local *,
+                       __clc_vec4_int16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int16_t __global *,
+                       __clc_vec4_int16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int16_t __local *,
+                       __clc_vec8_int16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int16_t __global *,
+                       __clc_vec8_int16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int16_t __local *,
+                       __clc_vec16_int16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int16_t __global *,
+                       __clc_vec16_int16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_int32_t __local *, __clc_int32_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_int32_t __global *, __clc_int32_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int32_t __local *,
+                       __clc_vec2_int32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int32_t __global *,
+                       __clc_vec2_int32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int32_t __local *,
+                       __clc_vec3_int32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int32_t __global *,
+                       __clc_vec3_int32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int32_t __local *,
+                       __clc_vec4_int32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int32_t __global *,
+                       __clc_vec4_int32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int32_t __local *,
+                       __clc_vec8_int32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int32_t __global *,
+                       __clc_vec8_int32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int32_t __local *,
+                       __clc_vec16_int32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int32_t __global *,
+                       __clc_vec16_int32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_int64_t __local *, __clc_int64_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_int64_t __global *, __clc_int64_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int64_t __local *,
+                       __clc_vec2_int64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int64_t __global *,
+                       __clc_vec2_int64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int64_t __local *,
+                       __clc_vec3_int64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int64_t __global *,
+                       __clc_vec3_int64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int64_t __local *,
+                       __clc_vec4_int64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int64_t __global *,
+                       __clc_vec4_int64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int64_t __local *,
+                       __clc_vec8_int64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int64_t __global *,
+                       __clc_vec8_int64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int64_t __local *,
+                       __clc_vec16_int64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int64_t __global *,
+                       __clc_vec16_int64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_uint8_t __local *, __clc_uint8_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_uint8_t __global *, __clc_uint8_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_uint8_t __local *,
+                       __clc_vec2_uint8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_uint8_t __global *,
+                       __clc_vec2_uint8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_uint8_t __local *,
+                       __clc_vec3_uint8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_uint8_t __global *,
+                       __clc_vec3_uint8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_uint8_t __local *,
+                       __clc_vec4_uint8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_uint8_t __global *,
+                       __clc_vec4_uint8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_uint8_t __local *,
+                       __clc_vec8_uint8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_uint8_t __global *,
+                       __clc_vec8_uint8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_uint8_t __local *,
+                       __clc_vec16_uint8_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_uint8_t __global *,
+                       __clc_vec16_uint8_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_uint16_t __local *, __clc_uint16_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_uint16_t __global *, __clc_uint16_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_uint16_t __local *,
+                       __clc_vec2_uint16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_uint16_t __global *,
+                       __clc_vec2_uint16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_uint16_t __local *,
+                       __clc_vec3_uint16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_uint16_t __global *,
+                       __clc_vec3_uint16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_uint16_t __local *,
+                       __clc_vec4_uint16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_uint16_t __global *,
+                       __clc_vec4_uint16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_uint16_t __local *,
+                       __clc_vec8_uint16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_uint16_t __global *,
+                       __clc_vec8_uint16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_uint16_t __local *,
+                       __clc_vec16_uint16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_uint16_t __global *,
+                       __clc_vec16_uint16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_uint32_t __local *, __clc_uint32_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_uint32_t __global *, __clc_uint32_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_uint32_t __local *,
+                       __clc_vec2_uint32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_uint32_t __global *,
+                       __clc_vec2_uint32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_uint32_t __local *,
+                       __clc_vec3_uint32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_uint32_t __global *,
+                       __clc_vec3_uint32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_uint32_t __local *,
+                       __clc_vec4_uint32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_uint32_t __global *,
+                       __clc_vec4_uint32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_uint32_t __local *,
+                       __clc_vec8_uint32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_uint32_t __global *,
+                       __clc_vec8_uint32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_uint32_t __local *,
+                       __clc_vec16_uint32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_uint32_t __global *,
+                       __clc_vec16_uint32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_uint64_t __local *, __clc_uint64_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_uint64_t __global *, __clc_uint64_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_uint64_t __local *,
+                       __clc_vec2_uint64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_uint64_t __global *,
+                       __clc_vec2_uint64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_uint64_t __local *,
+                       __clc_vec3_uint64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_uint64_t __global *,
+                       __clc_vec3_uint64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_uint64_t __local *,
+                       __clc_vec4_uint64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_uint64_t __global *,
+                       __clc_vec4_uint64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_uint64_t __local *,
+                       __clc_vec8_uint64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_uint64_t __global *,
+                       __clc_vec8_uint64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_uint64_t __local *,
+                       __clc_vec16_uint64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_uint64_t __global *,
+                       __clc_vec16_uint64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_fp32_t __local *, __clc_fp32_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_fp32_t __global *, __clc_fp32_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_fp32_t __local *,
+                       __clc_vec2_fp32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_fp32_t __global *,
+                       __clc_vec2_fp32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_fp32_t __local *,
+                       __clc_vec3_fp32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_fp32_t __global *,
+                       __clc_vec3_fp32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_fp32_t __local *,
+                       __clc_vec4_fp32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_fp32_t __global *,
+                       __clc_vec4_fp32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_fp32_t __local *,
+                       __clc_vec8_fp32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_fp32_t __global *,
+                       __clc_vec8_fp32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_fp32_t __local *,
+                       __clc_vec16_fp32_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_fp32_t __global *,
+                       __clc_vec16_fp32_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+
+#ifdef cl_khr_fp64
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_fp64_t __local *, __clc_fp64_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_fp64_t __global *, __clc_fp64_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_fp64_t __local *,
+                       __clc_vec2_fp64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_fp64_t __global *,
+                       __clc_vec2_fp64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_fp64_t __local *,
+                       __clc_vec3_fp64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_fp64_t __global *,
+                       __clc_vec3_fp64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_fp64_t __local *,
+                       __clc_vec4_fp64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_fp64_t __global *,
+                       __clc_vec4_fp64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_fp64_t __local *,
+                       __clc_vec8_fp64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_fp64_t __global *,
+                       __clc_vec8_fp64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_fp64_t __local *,
+                       __clc_vec16_fp64_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_fp64_t __global *,
+                       __clc_vec16_fp64_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+#endif
+
+#ifdef cl_khr_fp16
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_fp16_t __local *, __clc_fp16_t const __global *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy(
+    __clc_uint32_t, __clc_fp16_t __global *, __clc_fp16_t const __local *,
+    __clc_size_t, __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_fp16_t __local *,
+                       __clc_vec2_fp16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_fp16_t __global *,
+                       __clc_vec2_fp16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_fp16_t __local *,
+                       __clc_vec3_fp16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_fp16_t __global *,
+                       __clc_vec3_fp16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_fp16_t __local *,
+                       __clc_vec4_fp16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_fp16_t __global *,
+                       __clc_vec4_fp16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_fp16_t __local *,
+                       __clc_vec8_fp16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_fp16_t __global *,
+                       __clc_vec8_fp16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_fp16_t __local *,
+                       __clc_vec16_fp16_t const __global *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t
+__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_fp16_t __global *,
+                       __clc_vec16_fp16_t const __local *, __clc_size_t,
+                       __clc_size_t, __clc_event_t);
+#endif
+
+_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT void
+__spirv_GroupWaitEvents(__clc_uint32_t, __clc_int32_t, __clc_event_t *);
+
+_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(__clc_uint32_t,
+                                                   __clc_uint32_t);
+
 _CLC_OVERLOAD
 _CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_SConvert_Rchar(__clc_int16_t);
 _CLC_OVERLOAD
@@ -10855,6 +11423,159 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_fclamp(
     __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t);
 #endif
 
+_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_prefetch(__clc_char_t const __global *,
+                                                  __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_char_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_char_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_char_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_char_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_char_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_prefetch(__clc_int8_t const __global *,
+                                                  __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_int8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_int8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_int8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_int8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_int8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_int16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_int16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_int16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_int16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_int16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_int16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_int32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_int32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_int32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_int32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_int32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_int32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_int64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_int64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_int64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_int64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_int64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_int64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_uint8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_uint8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_uint8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_uint8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_uint8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_uint8_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_uint16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_uint16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_uint16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_uint16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_uint16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_uint16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_uint32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_uint32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_uint32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_uint32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_uint32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_uint32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_uint64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_uint64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_uint64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_uint64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_uint64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_uint64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_prefetch(__clc_fp32_t const __global *,
+                                                  __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_fp32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_fp32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_fp32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_fp32_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_fp32_t const __global *, __clc_size_t);
+
+#ifdef cl_khr_fp64
+_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_prefetch(__clc_fp64_t const __global *,
+                                                  __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_fp64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_fp64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_fp64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_fp64_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_fp64_t const __global *, __clc_size_t);
+#endif
+
+#ifdef cl_khr_fp16
+_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_prefetch(__clc_fp16_t const __global *,
+                                                  __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec2_fp16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec3_fp16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec4_fp16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec8_fp16_t const __global *, __clc_size_t);
+_CLC_OVERLOAD _CLC_DECL void
+__spirv_ocl_prefetch(__clc_vec16_fp16_t const __global *, __clc_size_t);
+#endif
+
+_CLC_OVERLOAD
+_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_s_abs(__clc_char_t);
 _CLC_OVERLOAD
 _CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_s_abs(__clc_int8_t);
 _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t
diff --git a/libclc/generic/include/spirv/synchronization/barrier.h b/libclc/generic/include/spirv/synchronization/barrier.h
deleted file mode 100644
index 476a4f4e7d99..000000000000
--- a/libclc/generic/include/spirv/synchronization/barrier.h
+++ /dev/null
@@ -1,13 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-_CLC_OVERLOAD _CLC_DECL void __spirv_ControlBarrier(unsigned int scope,
-                                                    unsigned int memory,
-                                                    unsigned int semantics);
-_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int scope,
-                                                   unsigned int semantics);
diff --git a/libclc/generic/libspirv/async/async_work_group_strided_copy.cl b/libclc/generic/libspirv/async/async_work_group_strided_copy.cl
index 1f7ae5fc46b5..656f844bee39 100644
--- a/libclc/generic/libspirv/async/async_work_group_strided_copy.cl
+++ b/libclc/generic/libspirv/async/async_work_group_strided_copy.cl
@@ -9,4 +9,5 @@
 #include <spirv/spirv.h>
 
 #define __CLC_BODY <async_work_group_strided_copy.inc>
+#define __CLC_GEN_VEC3
 #include <clc/async/gentype.inc>
diff --git a/libclc/generic/libspirv/async/prefetch.cl b/libclc/generic/libspirv/async/prefetch.cl
index 85dd2ab21dff..9a12b02d2870 100644
--- a/libclc/generic/libspirv/async/prefetch.cl
+++ b/libclc/generic/libspirv/async/prefetch.cl
@@ -9,4 +9,5 @@
 #include <spirv/spirv.h>
 
 #define __CLC_BODY <prefetch.inc>
+#define __CLC_GEN_VEC3
 #include <clc/async/gentype.inc>
diff --git a/libclc/test/CMakeLists.txt b/libclc/test/CMakeLists.txt
new file mode 100644
index 000000000000..de7f7803d40b
--- /dev/null
+++ b/libclc/test/CMakeLists.txt
@@ -0,0 +1,44 @@
+# required by lit.site.cfg.py.in
+set(LIBCLC_TEST_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
+
+configure_lit_site_cfg(
+  ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.py.in
+  ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg.py
+  MAIN_CONFIG
+    ${CMAKE_CURRENT_SOURCE_DIR}/lit.cfg.py
+)
+
+set(LIBCLC_TEST_DEPS
+  FileCheck
+  llvm-dis
+  not
+  clang
+)
+
+add_custom_target(check-libclc)
+
+foreach( t ${LIBCLC_TARGET_TO_TEST} )
+	foreach( d ${${t}_devices} )
+    if( ${d} STREQUAL "none" )
+      set( mcpu )
+      set( arch_suffix "${t}" )
+    else()
+      set( mcpu "cpu=${d}" )
+      set( arch_suffix "${d}-${t}" )
+    endif()
+    message( " Testing : ${arch_suffix}" )
+
+    add_lit_testsuite(check-libclc-spirv-${arch_suffix} "Running libclc spirv-${arch_suffix} regression tests"
+      ${CMAKE_CURRENT_BINARY_DIR}
+      ARGS
+        --verbose
+      PARAMS "target=${t}" ${mcpu} "builtins=libspirv-${arch_suffix}.bc"
+      DEPENDS
+        ${LIBCLC_TEST_DEPS}
+        libspirv-builtins
+      )
+
+    add_dependencies(check-libclc check-libclc-spirv-${arch_suffix})
+
+  endforeach( d )
+endforeach( t )
diff --git a/libclc/test/binding/core/ControlBarrier.cl b/libclc/test/binding/core/ControlBarrier.cl
new file mode 100644
index 000000000000..6db6e514b12e
--- /dev/null
+++ b/libclc/test/binding/core/ControlBarrier.cl
@@ -0,0 +1,22 @@
+
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// Autogenerated by gen-libclc-test.py
+
+// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s
+
+#include <spirv/spirv_types.h>
+
+// CHECK-NOT: declare {{.*}} @_Z
+// CHECK-NOT: call {{[^ ]*}} bitcast
+__attribute__((overloadable)) void
+test___spirv_ControlBarrier(__clc_uint32_t args_0, __clc_uint32_t args_1,
+                            __clc_uint32_t args_2) {
+  __spirv_ControlBarrier(args_0, args_1, args_2);
+}
diff --git a/libclc/test/binding/core/GroupAsyncCopy.cl b/libclc/test/binding/core/GroupAsyncCopy.cl
new file mode 100644
index 000000000000..90c912016945
--- /dev/null
+++ b/libclc/test/binding/core/GroupAsyncCopy.cl
@@ -0,0 +1,993 @@
+
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// Autogenerated by gen-libclc-test.py
+
+// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s
+
+#include <spirv/spirv_types.h>
+
+// CHECK-NOT: declare {{.*}} @_Z
+// CHECK-NOT: call {{[^ ]*}} bitcast
+__attribute__((overloadable)) __clc_event_t
+test___spirv_GroupAsyncCopy(__clc_uint32_t args_0, __clc_int8_t __local *args_1,
+                            __clc_int8_t const __global *args_2,
+                            __clc_size_t args_3, __clc_size_t args_4,
+                            __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_int8_t __local *args_1,
+    __clc_vec2_int8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_int8_t __local *args_1,
+    __clc_vec3_int8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_int8_t __local *args_1,
+    __clc_vec4_int8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_int8_t __local *args_1,
+    __clc_vec8_int8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_int8_t __local *args_1,
+    __clc_vec16_int8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_uint8_t __local *args_1,
+    __clc_uint8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_uint8_t __local *args_1,
+    __clc_vec2_uint8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_uint8_t __local *args_1,
+    __clc_vec3_uint8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_uint8_t __local *args_1,
+    __clc_vec4_uint8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_uint8_t __local *args_1,
+    __clc_vec8_uint8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_uint8_t __local *args_1,
+    __clc_vec16_uint8_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_int16_t __local *args_1,
+    __clc_int16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_int16_t __local *args_1,
+    __clc_vec2_int16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_int16_t __local *args_1,
+    __clc_vec3_int16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_int16_t __local *args_1,
+    __clc_vec4_int16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_int16_t __local *args_1,
+    __clc_vec8_int16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_int16_t __local *args_1,
+    __clc_vec16_int16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_uint16_t __local *args_1,
+    __clc_uint16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_uint16_t __local *args_1,
+    __clc_vec2_uint16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_uint16_t __local *args_1,
+    __clc_vec3_uint16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_uint16_t __local *args_1,
+    __clc_vec4_uint16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_uint16_t __local *args_1,
+    __clc_vec8_uint16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_uint16_t __local *args_1,
+    __clc_vec16_uint16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_int32_t __local *args_1,
+    __clc_int32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_int32_t __local *args_1,
+    __clc_vec2_int32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_int32_t __local *args_1,
+    __clc_vec3_int32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_int32_t __local *args_1,
+    __clc_vec4_int32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_int32_t __local *args_1,
+    __clc_vec8_int32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_int32_t __local *args_1,
+    __clc_vec16_int32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_uint32_t __local *args_1,
+    __clc_uint32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_uint32_t __local *args_1,
+    __clc_vec2_uint32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_uint32_t __local *args_1,
+    __clc_vec3_uint32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_uint32_t __local *args_1,
+    __clc_vec4_uint32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_uint32_t __local *args_1,
+    __clc_vec8_uint32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_uint32_t __local *args_1,
+    __clc_vec16_uint32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_int64_t __local *args_1,
+    __clc_int64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_int64_t __local *args_1,
+    __clc_vec2_int64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_int64_t __local *args_1,
+    __clc_vec3_int64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_int64_t __local *args_1,
+    __clc_vec4_int64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_int64_t __local *args_1,
+    __clc_vec8_int64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_int64_t __local *args_1,
+    __clc_vec16_int64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_uint64_t __local *args_1,
+    __clc_uint64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_uint64_t __local *args_1,
+    __clc_vec2_uint64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_uint64_t __local *args_1,
+    __clc_vec3_uint64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_uint64_t __local *args_1,
+    __clc_vec4_uint64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_uint64_t __local *args_1,
+    __clc_vec8_uint64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_uint64_t __local *args_1,
+    __clc_vec16_uint64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t
+test___spirv_GroupAsyncCopy(__clc_uint32_t args_0, __clc_fp32_t __local *args_1,
+                            __clc_fp32_t const __global *args_2,
+                            __clc_size_t args_3, __clc_size_t args_4,
+                            __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_fp32_t __local *args_1,
+    __clc_vec2_fp32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_fp32_t __local *args_1,
+    __clc_vec3_fp32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_fp32_t __local *args_1,
+    __clc_vec4_fp32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_fp32_t __local *args_1,
+    __clc_vec8_fp32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_fp32_t __local *args_1,
+    __clc_vec16_fp32_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t
+test___spirv_GroupAsyncCopy(__clc_uint32_t args_0, __clc_fp64_t __local *args_1,
+                            __clc_fp64_t const __global *args_2,
+                            __clc_size_t args_3, __clc_size_t args_4,
+                            __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_fp64_t __local *args_1,
+    __clc_vec2_fp64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_fp64_t __local *args_1,
+    __clc_vec3_fp64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_fp64_t __local *args_1,
+    __clc_vec4_fp64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_fp64_t __local *args_1,
+    __clc_vec8_fp64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_fp64_t __local *args_1,
+    __clc_vec16_fp64_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t
+test___spirv_GroupAsyncCopy(__clc_uint32_t args_0, __clc_fp16_t __local *args_1,
+                            __clc_fp16_t const __global *args_2,
+                            __clc_size_t args_3, __clc_size_t args_4,
+                            __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_fp16_t __local *args_1,
+    __clc_vec2_fp16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_fp16_t __local *args_1,
+    __clc_vec3_fp16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_fp16_t __local *args_1,
+    __clc_vec4_fp16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_fp16_t __local *args_1,
+    __clc_vec8_fp16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_fp16_t __local *args_1,
+    __clc_vec16_fp16_t const __global *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_int8_t __global *args_1,
+    __clc_int8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_int8_t __global *args_1,
+    __clc_vec2_int8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_int8_t __global *args_1,
+    __clc_vec3_int8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_int8_t __global *args_1,
+    __clc_vec4_int8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_int8_t __global *args_1,
+    __clc_vec8_int8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_int8_t __global *args_1,
+    __clc_vec16_int8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_uint8_t __global *args_1,
+    __clc_uint8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_uint8_t __global *args_1,
+    __clc_vec2_uint8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_uint8_t __global *args_1,
+    __clc_vec3_uint8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_uint8_t __global *args_1,
+    __clc_vec4_uint8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_uint8_t __global *args_1,
+    __clc_vec8_uint8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_uint8_t __global *args_1,
+    __clc_vec16_uint8_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_int16_t __global *args_1,
+    __clc_int16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_int16_t __global *args_1,
+    __clc_vec2_int16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_int16_t __global *args_1,
+    __clc_vec3_int16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_int16_t __global *args_1,
+    __clc_vec4_int16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_int16_t __global *args_1,
+    __clc_vec8_int16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_int16_t __global *args_1,
+    __clc_vec16_int16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_uint16_t __global *args_1,
+    __clc_uint16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_uint16_t __global *args_1,
+    __clc_vec2_uint16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_uint16_t __global *args_1,
+    __clc_vec3_uint16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_uint16_t __global *args_1,
+    __clc_vec4_uint16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_uint16_t __global *args_1,
+    __clc_vec8_uint16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_uint16_t __global *args_1,
+    __clc_vec16_uint16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_int32_t __global *args_1,
+    __clc_int32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_int32_t __global *args_1,
+    __clc_vec2_int32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_int32_t __global *args_1,
+    __clc_vec3_int32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_int32_t __global *args_1,
+    __clc_vec4_int32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_int32_t __global *args_1,
+    __clc_vec8_int32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_int32_t __global *args_1,
+    __clc_vec16_int32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_uint32_t __global *args_1,
+    __clc_uint32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_uint32_t __global *args_1,
+    __clc_vec2_uint32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_uint32_t __global *args_1,
+    __clc_vec3_uint32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_uint32_t __global *args_1,
+    __clc_vec4_uint32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_uint32_t __global *args_1,
+    __clc_vec8_uint32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_uint32_t __global *args_1,
+    __clc_vec16_uint32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_int64_t __global *args_1,
+    __clc_int64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_int64_t __global *args_1,
+    __clc_vec2_int64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_int64_t __global *args_1,
+    __clc_vec3_int64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_int64_t __global *args_1,
+    __clc_vec4_int64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_int64_t __global *args_1,
+    __clc_vec8_int64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_int64_t __global *args_1,
+    __clc_vec16_int64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_uint64_t __global *args_1,
+    __clc_uint64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_uint64_t __global *args_1,
+    __clc_vec2_uint64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_uint64_t __global *args_1,
+    __clc_vec3_uint64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_uint64_t __global *args_1,
+    __clc_vec4_uint64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_uint64_t __global *args_1,
+    __clc_vec8_uint64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_uint64_t __global *args_1,
+    __clc_vec16_uint64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_fp32_t __global *args_1,
+    __clc_fp32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_fp32_t __global *args_1,
+    __clc_vec2_fp32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_fp32_t __global *args_1,
+    __clc_vec3_fp32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_fp32_t __global *args_1,
+    __clc_vec4_fp32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_fp32_t __global *args_1,
+    __clc_vec8_fp32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_fp32_t __global *args_1,
+    __clc_vec16_fp32_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_fp64_t __global *args_1,
+    __clc_fp64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_fp64_t __global *args_1,
+    __clc_vec2_fp64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_fp64_t __global *args_1,
+    __clc_vec3_fp64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_fp64_t __global *args_1,
+    __clc_vec4_fp64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_fp64_t __global *args_1,
+    __clc_vec8_fp64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_fp64_t __global *args_1,
+    __clc_vec16_fp64_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_fp16_t __global *args_1,
+    __clc_fp16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec2_fp16_t __global *args_1,
+    __clc_vec2_fp16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec3_fp16_t __global *args_1,
+    __clc_vec3_fp16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec4_fp16_t __global *args_1,
+    __clc_vec4_fp16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec8_fp16_t __global *args_1,
+    __clc_vec8_fp16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) __clc_event_t test___spirv_GroupAsyncCopy(
+    __clc_uint32_t args_0, __clc_vec16_fp16_t __global *args_1,
+    __clc_vec16_fp16_t const __local *args_2, __clc_size_t args_3,
+    __clc_size_t args_4, __clc_event_t args_5) {
+  return __spirv_GroupAsyncCopy(args_0, args_1, args_2, args_3, args_4, args_5);
+}
+
+#endif
diff --git a/libclc/test/binding/core/GroupWaitEvents.cl b/libclc/test/binding/core/GroupWaitEvents.cl
new file mode 100644
index 000000000000..6787c6a28e75
--- /dev/null
+++ b/libclc/test/binding/core/GroupWaitEvents.cl
@@ -0,0 +1,22 @@
+
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// Autogenerated by gen-libclc-test.py
+
+// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s
+
+#include <spirv/spirv_types.h>
+
+// CHECK-NOT: declare {{.*}} @_Z
+// CHECK-NOT: call {{[^ ]*}} bitcast
+__attribute__((overloadable)) void
+test___spirv_GroupWaitEvents(__clc_uint32_t args_0, __clc_int32_t args_1,
+                             __clc_event_t *args_2) {
+  __spirv_GroupWaitEvents(args_0, args_1, args_2);
+}
diff --git a/libclc/generic/include/spirv/async/wait_group_events.h b/libclc/test/binding/core/MemoryBarrier.cl
similarity index 51%
rename from libclc/generic/include/spirv/async/wait_group_events.h
rename to libclc/test/binding/core/MemoryBarrier.cl
index 4b0ab2e87a84..e01734376d38 100644
--- a/libclc/generic/include/spirv/async/wait_group_events.h
+++ b/libclc/test/binding/core/MemoryBarrier.cl
@@ -1,3 +1,4 @@
+
 //===----------------------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
@@ -6,6 +7,15 @@
 //
 //===----------------------------------------------------------------------===//
 
-_CLC_OVERLOAD _CLC_DEF void __spirv_GroupWaitEvents(unsigned int scope,
-                                                    int num_events,
-                                                    event_t *event_list);
+// Autogenerated by gen-libclc-test.py
+
+// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s
+
+#include <spirv/spirv_types.h>
+
+// CHECK-NOT: declare {{.*}} @_Z
+// CHECK-NOT: call {{[^ ]*}} bitcast
+__attribute__((overloadable)) void
+test___spirv_MemoryBarrier(__clc_uint32_t args_0, __clc_uint32_t args_1) {
+  __spirv_MemoryBarrier(args_0, args_1);
+}
diff --git a/libclc/test/binding/ocl/prefetch.cl b/libclc/test/binding/ocl/prefetch.cl
new file mode 100644
index 000000000000..1665c32b4ba7
--- /dev/null
+++ b/libclc/test/binding/ocl/prefetch.cl
@@ -0,0 +1,437 @@
+
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// Autogenerated by gen-libclc-test.py
+
+// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s
+
+#include <spirv/spirv_types.h>
+
+// CHECK-NOT: declare {{.*}} @_Z
+// CHECK-NOT: call {{[^ ]*}} bitcast
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_int8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_int8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_int8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_int8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_int8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_int8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_uint8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_uint8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_uint8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_uint8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_uint8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_uint8_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_int16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_int16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_int16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_int16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_int16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_int16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_uint16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_uint16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_uint16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_uint16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_uint16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_uint16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_int32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_int32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_int32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_int32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_int32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_int32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_uint32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_uint32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_uint32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_uint32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_uint32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_uint32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_int64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_int64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_int64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_int64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_int64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_int64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_uint64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_uint64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_uint64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_uint64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_uint64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_uint64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_fp32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_fp32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_fp32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_fp32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_fp32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_fp32_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_fp64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_fp64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_fp64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_fp64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_fp64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp64
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_fp64_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_fp16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec2_fp16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec3_fp16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec4_fp16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec8_fp16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
+#ifdef cl_khr_fp16
+__attribute__((overloadable)) void
+test___spirv_ocl_prefetch(__clc_vec16_fp16_t const __global *args_0,
+                          __clc_size_t args_1) {
+  __spirv_ocl_prefetch(args_0, args_1);
+}
+
+#endif
diff --git a/libclc/test/lit.cfg.py b/libclc/test/lit.cfg.py
new file mode 100644
index 000000000000..98261f1b590b
--- /dev/null
+++ b/libclc/test/lit.cfg.py
@@ -0,0 +1,59 @@
+# -*- Python -*-
+
+import os
+
+import lit.formats
+import lit.util
+
+from lit.llvm import llvm_config
+from lit.llvm.subst import ToolSubst
+from lit.llvm.subst import FindTool
+
+# Configuration file for the 'lit' test runner.
+
+# name: The name of this test suite.
+config.name = 'LIBCLC'
+
+# testFormat: The test format to use to interpret tests.
+config.test_format = lit.formats.ShTest(not llvm_config.use_lit_shell)
+
+# suffixes: A list of file extensions to treat as test files.
+config.suffixes = ['.cl', '.cpp']
+
+# excludes: A list of directories  and fles to exclude from the testsuite.
+config.excludes = ['CMakeLists.txt']
+
+# test_source_root: The root path where tests are located.
+config.test_source_root = os.path.join(os.path.dirname(__file__), 'binding')
+
+# test_exec_root: The root path where tests should be run.
+config.test_exec_root = os.path.join(config.test_run_dir, 'test')
+
+libclc_inc = os.path.join(config.libclc_root, 'generic', 'include')
+
+target = lit_config.params.get('target', '')
+builtins = lit_config.params.get('builtins', '')
+cpu = lit_config.params.get('cpu', '')
+cpu = [] if cpu == '' else ["-mcpu=" + cpu]
+
+llvm_config.use_default_substitutions()
+
+llvm_config.use_clang(additional_flags=["-fno-builtin",
+                                        "-I", libclc_inc,
+                                        "-target", target,
+                                        "-Xclang",
+                                        "-fdeclare-spirv-builtins",
+                                        "-Xclang",
+                                        "-mlink-builtin-bitcode",
+                                        "-Xclang",
+                                        os.path.join(config.llvm_libs_dir,
+                                                     "clc",
+                                                     builtins)] + cpu)
+
+config.substitutions.append(('%PATH%', config.environment['PATH']))
+
+tool_dirs = [config.llvm_tools_dir]
+
+tools = ['llvm-dis', 'not']
+
+llvm_config.add_tool_substitutions(tools, tool_dirs)
diff --git a/libclc/test/lit.site.cfg.py.in b/libclc/test/lit.site.cfg.py.in
new file mode 100644
index 000000000000..adf6e0907555
--- /dev/null
+++ b/libclc/test/lit.site.cfg.py.in
@@ -0,0 +1,23 @@
+@LIT_SITE_CFG_IN_HEADER@
+
+import sys
+
+config.llvm_src_root = "@LLVM_SOURCE_DIR@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
+config.llvm_tools_dir = "@LLVM_TOOLS_DIR@"
+config.llvm_libs_dir = "@LLVM_LIBS_DIR@"
+config.llvm_shlib_dir = "@SHLIBDIR@"
+config.llvm_plugin_ext = "@LLVM_PLUGIN_EXT@"
+config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"
+config.host_triple = "@LLVM_HOST_TRIPLE@"
+config.target_triple = "@TARGET_TRIPLE@"
+config.host_arch = "@HOST_ARCH@"
+config.python_executable = "@PYTHON_EXECUTABLE@"
+config.libclc_root = "@LIBCLC_ROOT_DIR@"
+config.test_run_dir = "@LIBCLC_BINARY_DIR@"
+
+import lit.llvm
+lit.llvm.initialize(lit_config, config)
+
+# Let the main config do the real work.
+lit_config.load_config(config, "@LIBCLC_TEST_SOURCE_DIR@/lit.cfg.py")
diff --git a/libclc/utils/gen-libclc-test.py b/libclc/utils/gen-libclc-test.py
new file mode 100755
index 000000000000..0a9d51dea660
--- /dev/null
+++ b/libclc/utils/gen-libclc-test.py
@@ -0,0 +1,103 @@
+#!/usr/bin/env python3
+import argparse
+from itertools import takewhile
+import json
+import os
+import sys
+from typing import Callable, Dict, IO, List
+import io
+from string import Template
+import re
+
+from spirv_common import ignore_overload, emit_guards, close_guards, clang_format
+
+def ignore_function(fun):
+    whitelist = [
+        "ControlBarrier",
+        "GroupAsyncCopy",
+        "GroupWaitEvents",
+        "MemoryBarrier",
+        "prefetch"
+    ]
+
+    return not any([fun.find(b) != -1 for b in whitelist])
+
+def get_builtin_name(func):
+    func = func.replace("__spirv_", "")
+    builtin = func.replace("ocl_", "")
+    kind = "core" if builtin == func else "ocl"
+    return (kind, builtin)
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(
+        description="""
+Generate SPIR-V interface check tests.
+Typical usage:
+ clang-tblgen --gen-clang-progmodel-builtins-as-json path/to/SPIRVBuiltins.td \
+   -o builtin.json
+ generate-test-libclc.py builtin.json -format clang-format -o spirv_builtin.h
+""")
+    parser.add_argument("input",
+                        metavar="MAPPING",
+                        type=argparse.FileType('r'),
+                        help="Path to mapping.json")
+    parser.add_argument("-format",
+                        metavar="clang-format",
+                        nargs='?',
+                        help="clang-format the output file")
+    parser.add_argument("-o", help="Folder to write the tests to")
+    args = parser.parse_args()
+
+    with args.input as f:
+        mapping = json.load(f)
+    keys = list(mapping.keys())
+    keys.sort()
+    for k in keys:
+        if ignore_function(k):
+            continue
+        overloads = mapping[k]
+        kind, builtin = get_builtin_name(k)
+        test_file = os.path.join(args.o, kind, builtin  + ".cl")
+        if not os.path.exists(os.path.join(args.o, kind)):
+            os.makedirs(os.path.join(args.o, kind))
+        with open(test_file, "w") as out_fd:
+            print("gen: " + test_file)
+            out_fd.write("""
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// Autogenerated by gen-libclc-test.py
+
+// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s
+
+#include <spirv/spirv_types.h>
+
+// CHECK-NOT: declare {{.*}} @_Z
+// CHECK-NOT: call {{[^ ]*}} bitcast
+""")
+            for proto, _ in overloads:
+                if ignore_overload(proto):
+                    continue
+                nb_guards = emit_guards(out_fd, proto)
+                ret = proto[0]
+                proto = proto[1:]
+                param = {
+                    "RET" : ret,
+                    "FN"  : k,
+                    "PARAM" : ", ".join(["{} args_{}".format(ty, str(i)) for i, ty in enumerate(proto)]),
+                    "RETURN" : "return" if ret != "void" else "",
+                    "ARG" : ", ".join(["args_{}".format(str(i)) for i, _ in enumerate(proto)])
+                }
+                out_fd.write("""__attribute__((overloadable)) {RET} test_{FN}({PARAM}) {{
+  {RETURN} {FN}({ARG});
+}}
+
+""".format(**param))
+                close_guards(out_fd, nb_guards)
+        if args.format:
+            clang_format(args.format, test_file)
diff --git a/libclc/utils/spirv_common.py b/libclc/utils/spirv_common.py
new file mode 100644
index 000000000000..17ca6834ff57
--- /dev/null
+++ b/libclc/utils/spirv_common.py
@@ -0,0 +1,58 @@
+#!/usr/bin/env python3
+#===----------------------------------------------------------------------===
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+#===----------------------------------------------------------------------===
+
+import subprocess
+
+def ignore_overload(overload):
+    blacklist = ["__generic", "__private"]
+
+    def is_black_listed(s):
+        return any([s.find(b) != -1 for b in blacklist])
+
+    return any([is_black_listed(s) for s in overload])
+
+def overload_requires(overload, ext):
+    return any([ty.find(ext) != -1 for ty in overload])
+
+
+def overload_requires_fp64(overload):
+    return overload_requires(overload, "fp64")
+
+
+def overload_requires_fp16(overload):
+    return overload_requires(overload, "fp16")
+
+def emit_guards(fd, overload):
+    """
+    Emits guards according the function type.
+    Returns the number of emitted guards.
+    """
+    requires_half = overload_requires_fp16(overload)
+    requires_double = overload_requires_fp64(overload)
+    nb_guards = 0
+    if requires_half:
+        nb_guards += 1
+        fd.write("#ifdef cl_khr_fp16\n")
+    if requires_double:
+        nb_guards += 1
+        fd.write("#ifdef cl_khr_fp64\n")
+    return nb_guards
+
+
+def close_guards(fd, nb_guards):
+    """
+    Emits 'nb_guards' guards closing statement.
+    """
+    for _ in range(nb_guards):
+        fd.write("#endif\n")
+
+def clang_format(format_tool, out_file):
+    # The ouput of clang-format is not stable, so we have to run the format twice
+    subprocess.check_output([format_tool, "-i", out_file])
+    subprocess.check_output([format_tool, "-i", out_file])
diff --git a/llvm-spirv/include/LLVMSPIRVExtensions.inc b/llvm-spirv/include/LLVMSPIRVExtensions.inc
index 8fcaaeaed1a5..a0cbcd97aa57 100644
--- a/llvm-spirv/include/LLVMSPIRVExtensions.inc
+++ b/llvm-spirv/include/LLVMSPIRVExtensions.inc
@@ -4,6 +4,7 @@
 #endif
 
 EXT(SPV_KHR_no_integer_wrap_decoration)
+EXT(SPV_KHR_float_controls)
 EXT(SPV_INTEL_subgroups)
 EXT(SPV_INTEL_media_block_io)
 EXT(SPV_INTEL_device_side_avc_motion_estimation)
diff --git a/llvm-spirv/include/LLVMSPIRVOpts.h b/llvm-spirv/include/LLVMSPIRVOpts.h
index 02230c4374ac..62831d0c4b6b 100644
--- a/llvm-spirv/include/LLVMSPIRVOpts.h
+++ b/llvm-spirv/include/LLVMSPIRVOpts.h
@@ -51,10 +51,12 @@ enum class VersionNumber : uint32_t {
   // Instruction
   SPIRV_1_0 = 0x00010000,
   SPIRV_1_1 = 0x00010100,
-  // TODO: populate this enum with the latest versions (up to 1.4) once
-  // translator get support of correponding features
+  SPIRV_1_2 = 0x00010200,
+  SPIRV_1_3 = 0x00010300,
+  // TODO: populate this enum with the latest versions (up to 1.5) once
+  // translator get support of corresponding features
   MinimumVersion = SPIRV_1_0,
-  MaximumVersion = SPIRV_1_1
+  MaximumVersion = SPIRV_1_3
 };
 
 enum class ExtensionID : uint32_t {
diff --git a/llvm-spirv/lib/SPIRV/OCL20ToSPIRV.cpp b/llvm-spirv/lib/SPIRV/OCL20ToSPIRV.cpp
index 33fe7e8e7e05..b51f8e2dcbf6 100644
--- a/llvm-spirv/lib/SPIRV/OCL20ToSPIRV.cpp
+++ b/llvm-spirv/lib/SPIRV/OCL20ToSPIRV.cpp
@@ -931,25 +931,46 @@ void OCL20ToSPIRV::visitCallGroupBuiltin(CallInst *CI,
     return;
 
   if (DemangledName != kOCLBuiltinName::WaitGroupEvent) {
-    StringRef GroupOp = DemangledName;
-    GroupOp = GroupOp.drop_front(strlen(kSPIRVName::GroupPrefix));
+    StringRef FuncName = DemangledName;
+    FuncName = FuncName.drop_front(strlen(kSPIRVName::GroupPrefix));
     SPIRSPIRVGroupOperationMap::foreachConditional(
         [&](const std::string &S, SPIRVGroupOperationKind G) {
-          if (!GroupOp.startswith(S))
+          if (!FuncName.startswith(S))
             return true; // continue
           PreOps.push_back(G);
-          StringRef Op = GroupOp.drop_front(S.size() + 1);
-          assert(!Op.empty() && "Invalid OpenCL group builtin function");
+          StringRef Op =
+              StringSwitch<StringRef>(FuncName)
+                  .StartsWith("ballot", "group_ballot_bit_count_")
+                  .StartsWith("non_uniform", kSPIRVName::GroupNonUniformPrefix)
+                  .Default(kSPIRVName::GroupPrefix);
+          // clustered functions are handled with non uniform group opcodes
+          StringRef ClusteredOp =
+              FuncName.contains("clustered_") ? "non_uniform_" : "";
+          StringRef LogicalOp = FuncName.contains("logical_") ? "logical_" : "";
+          StringRef GroupOp = StringSwitch<StringRef>(FuncName)
+                                  .Case("ballot_bit_count", "add")
+                                  .Case("ballot_inclusive_scan", "add")
+                                  .Case("ballot_exclusive_scan", "add")
+                                  .Default(FuncName.take_back(
+                                      3)); // assumes op is three characters
+          GroupOp.consume_front("_");      // when op is two characters
+          assert(!GroupOp.empty() && "Invalid OpenCL group builtin function");
           char OpTyC = 0;
-          auto NeedSign = Op == "max" || Op == "min";
           auto OpTy = F->getReturnType();
           if (OpTy->isFloatingPointTy())
             OpTyC = 'f';
           else if (OpTy->isIntegerTy()) {
+            auto NeedSign = GroupOp == "max" || GroupOp == "min";
             if (!NeedSign)
               OpTyC = 'i';
             else {
-              if (isLastFuncParamSigned(F->getName()))
+              // clustered reduce args are (type, uint)
+              // other operation args are (type)
+              auto MangledName = F->getName();
+              auto MangledTyC = ClusteredOp.empty()
+                                    ? MangledName.back()
+                                    : MangledName.take_back(2).front();
+              if (isMangledTypeSigned(MangledTyC))
                 OpTyC = 's';
               else
                 OpTyC = 'u';
@@ -957,22 +978,33 @@ void OCL20ToSPIRV::visitCallGroupBuiltin(CallInst *CI,
           } else
             llvm_unreachable("Invalid OpenCL group builtin argument type");
 
-          DemangledName =
-              std::string(kSPIRVName::GroupPrefix) + OpTyC + Op.str();
+          DemangledName = Op.str() + ClusteredOp.str() + LogicalOp.str() +
+                          OpTyC + GroupOp.str();
           return false; // break out of loop
         });
   }
 
-  bool IsGroupAllAny = (DemangledName.find("_all") != std::string::npos ||
-                        DemangledName.find("_any") != std::string::npos);
+  const bool IsElect = DemangledName == "group_elect";
+  const bool IsAllOrAny = (DemangledName.find("_all") != std::string::npos ||
+                           DemangledName.find("_any") != std::string::npos);
+  const bool IsAllEqual = DemangledName.find("_all_equal") != std::string::npos;
+  const bool IsBallot = DemangledName == "group_ballot";
+  const bool IsInverseBallot = DemangledName == "group_inverse_ballot";
+  const bool IsBallotBitExtract = DemangledName == "group_ballot_bit_extract";
+  const bool IsLogical = DemangledName.find("_logical") != std::string::npos;
+
+  const bool HasBoolReturnType = IsElect || IsAllOrAny || IsAllEqual ||
+                                 IsInverseBallot || IsBallotBitExtract ||
+                                 IsLogical;
+  const bool HasBoolArg = (IsAllOrAny && !IsAllEqual) || IsBallot || IsLogical;
 
   auto Consts = getInt32(M, PreOps);
   OCLBuiltinTransInfo Info;
-  if (IsGroupAllAny)
+  if (HasBoolReturnType)
     Info.RetTy = Type::getInt1Ty(*Ctx);
   Info.UniqName = DemangledName;
   Info.PostProc = [=](std::vector<Value *> &Ops) {
-    if (IsGroupAllAny) {
+    if (HasBoolArg) {
       IRBuilder<> IRB(CI);
       Ops[0] =
           IRB.CreateICmpNE(Ops[0], ConstantInt::get(Type::getInt32Ty(*Ctx), 0));
diff --git a/llvm-spirv/lib/SPIRV/OCLUtil.h b/llvm-spirv/lib/SPIRV/OCLUtil.h
index 6acbc7de83b7..d91316e0a310 100644
--- a/llvm-spirv/lib/SPIRV/OCLUtil.h
+++ b/llvm-spirv/lib/SPIRV/OCLUtil.h
@@ -627,6 +627,16 @@ template <> inline void SPIRVMap<std::string, SPIRVGroupOperationKind>::init() {
   add("reduce", GroupOperationReduce);
   add("scan_inclusive", GroupOperationInclusiveScan);
   add("scan_exclusive", GroupOperationExclusiveScan);
+  add("ballot_bit_count", GroupOperationReduce);
+  add("ballot_inclusive_scan", GroupOperationInclusiveScan);
+  add("ballot_exclusive_scan", GroupOperationExclusiveScan);
+  add("non_uniform_reduce", GroupOperationReduce);
+  add("non_uniform_scan_inclusive", GroupOperationInclusiveScan);
+  add("non_uniform_scan_exclusive", GroupOperationExclusiveScan);
+  add("non_uniform_reduce_logical", GroupOperationReduce);
+  add("non_uniform_scan_inclusive_logical", GroupOperationInclusiveScan);
+  add("non_uniform_scan_exclusive_logical", GroupOperationExclusiveScan);
+  add("clustered_reduce", GroupOperationClusteredReduce);
 }
 
 template <> inline void SPIRVMap<std::string, SPIRVFPRoundingModeKind>::init() {
@@ -690,12 +700,19 @@ inline void SPIRVMap<std::string, SPIRVBuiltinVariableKind>::init() {
   add("get_group_id", BuiltInWorkgroupId);
   add("get_global_linear_id", BuiltInGlobalLinearId);
   add("get_local_linear_id", BuiltInLocalInvocationIndex);
+  // cl_khr_subgroups
   add("get_sub_group_size", BuiltInSubgroupSize);
   add("get_max_sub_group_size", BuiltInSubgroupMaxSize);
   add("get_num_sub_groups", BuiltInNumSubgroups);
   add("get_enqueued_num_sub_groups", BuiltInNumEnqueuedSubgroups);
   add("get_sub_group_id", BuiltInSubgroupId);
   add("get_sub_group_local_id", BuiltInSubgroupLocalInvocationId);
+  // cl_khr_subgroup_ballot
+  add("get_sub_group_eq_mask", BuiltInSubgroupEqMask);
+  add("get_sub_group_ge_mask", BuiltInSubgroupGeMask);
+  add("get_sub_group_gt_mask", BuiltInSubgroupGtMask);
+  add("get_sub_group_le_mask", BuiltInSubgroupLeMask);
+  add("get_sub_group_lt_mask", BuiltInSubgroupLtMask);
 }
 
 // Maps uniqued OCL builtin function name to SPIR-V op code.
@@ -719,7 +736,7 @@ template <> inline void SPIRVMap<std::string, Op, SPIRVInstruction>::init() {
   _SPIRV_OP(max, SMax)
   _SPIRV_OP(and, And)
   _SPIRV_OP(or, Or)
-  _SPIRV_OP (xor, Xor)
+  _SPIRV_OP(xor, Xor)
 #undef _SPIRV_OP
 #define _SPIRV_OP(x, y) add("atomic_" #x, Op##y);
   // CL 2.0 atomic builtins
@@ -839,6 +856,43 @@ template <> inline void SPIRVMap<std::string, Op, SPIRVInstruction>::init() {
   _SPIRV_OP(intel_sub_group_media_block_read, SubgroupImageMediaBlockReadINTEL)
   _SPIRV_OP(intel_sub_group_media_block_write,
             SubgroupImageMediaBlockWriteINTEL)
+  // cl_khr_subgroup_non_uniform_vote
+  _SPIRV_OP(group_elect, GroupNonUniformElect)
+  _SPIRV_OP(group_non_uniform_all, GroupNonUniformAll)
+  _SPIRV_OP(group_non_uniform_any, GroupNonUniformAny)
+  _SPIRV_OP(group_non_uniform_all_equal, GroupNonUniformAllEqual)
+  // cl_khr_subgroup_ballot
+  _SPIRV_OP(group_non_uniform_broadcast, GroupNonUniformBroadcast)
+  _SPIRV_OP(group_broadcast_first, GroupNonUniformBroadcastFirst)
+  _SPIRV_OP(group_ballot, GroupNonUniformBallot)
+  _SPIRV_OP(group_inverse_ballot, GroupNonUniformInverseBallot)
+  _SPIRV_OP(group_ballot_bit_extract, GroupNonUniformBallotBitExtract)
+  _SPIRV_OP(group_ballot_bit_count_iadd, GroupNonUniformBallotBitCount)
+  _SPIRV_OP(group_ballot_find_lsb, GroupNonUniformBallotFindLSB)
+  _SPIRV_OP(group_ballot_find_msb, GroupNonUniformBallotFindMSB)
+  // cl_khr_subgroup_non_uniform_arithmetic
+  _SPIRV_OP(group_non_uniform_iadd, GroupNonUniformIAdd)
+  _SPIRV_OP(group_non_uniform_fadd, GroupNonUniformFAdd)
+  _SPIRV_OP(group_non_uniform_imul, GroupNonUniformIMul)
+  _SPIRV_OP(group_non_uniform_fmul, GroupNonUniformFMul)
+  _SPIRV_OP(group_non_uniform_smin, GroupNonUniformSMin)
+  _SPIRV_OP(group_non_uniform_umin, GroupNonUniformUMin)
+  _SPIRV_OP(group_non_uniform_fmin, GroupNonUniformFMin)
+  _SPIRV_OP(group_non_uniform_smax, GroupNonUniformSMax)
+  _SPIRV_OP(group_non_uniform_umax, GroupNonUniformUMax)
+  _SPIRV_OP(group_non_uniform_fmax, GroupNonUniformFMax)
+  _SPIRV_OP(group_non_uniform_iand, GroupNonUniformBitwiseAnd)
+  _SPIRV_OP(group_non_uniform_ior, GroupNonUniformBitwiseOr)
+  _SPIRV_OP(group_non_uniform_ixor, GroupNonUniformBitwiseXor)
+  _SPIRV_OP(group_non_uniform_logical_iand, GroupNonUniformLogicalAnd)
+  _SPIRV_OP(group_non_uniform_logical_ior, GroupNonUniformLogicalOr)
+  _SPIRV_OP(group_non_uniform_logical_ixor, GroupNonUniformLogicalXor)
+  // cl_khr_subgroup_shuffle
+  _SPIRV_OP(group_shuffle, GroupNonUniformShuffle)
+  _SPIRV_OP(group_shuffle_xor, GroupNonUniformShuffleXor)
+  // cl_khr_subgroup_shuffle_relative
+  _SPIRV_OP(group_shuffle_up, GroupNonUniformShuffleUp)
+  _SPIRV_OP(group_shuffle_down, GroupNonUniformShuffleDown)
 #undef _SPIRV_OP
 }
 
diff --git a/llvm-spirv/lib/SPIRV/SPIRVInternal.h b/llvm-spirv/lib/SPIRV/SPIRVInternal.h
index 0853281a2e89..0275a5e21f02 100644
--- a/llvm-spirv/lib/SPIRV/SPIRVInternal.h
+++ b/llvm-spirv/lib/SPIRV/SPIRVInternal.h
@@ -330,6 +330,7 @@ const static char AtomicPrefixInternal[] = "atomic_";
 
 namespace kSPIRVName {
 const static char GroupPrefix[] = "group_";
+const static char GroupNonUniformPrefix[] = "group_non_uniform_";
 const static char Prefix[] = "__spirv_";
 const static char Postfix[] = "__";
 const static char ImageQuerySize[] = "ImageQuerySize";
diff --git a/llvm-spirv/lib/SPIRV/SPIRVReader.cpp b/llvm-spirv/lib/SPIRV/SPIRVReader.cpp
index a677986195ee..d0c8a8ea64b1 100644
--- a/llvm-spirv/lib/SPIRV/SPIRVReader.cpp
+++ b/llvm-spirv/lib/SPIRV/SPIRVReader.cpp
@@ -837,6 +837,10 @@ void SPIRVToLLVM::transLLVMLoopMetadata(const Function *F) {
   if (FuncLoopMetadataMap.empty())
     return;
 
+  // Function declaration doesn't contain loop metadata.
+  if (F->isDeclaration())
+    return;
+
   DominatorTree DomTree(*(const_cast<Function *>(F)));
   LoopInfo LI(DomTree);
 
@@ -3341,6 +3345,11 @@ bool SPIRVToLLVM::transMetadata() {
                      getMDNodeStringIntVec(Context, EM->getLiterals()));
     }
   }
+  NamedMDNode *MemoryModelMD =
+      M->getOrInsertNamedMetadata(kSPIRVMD::MemoryModel);
+  MemoryModelMD->addOperand(
+      getMDTwoInt(Context, static_cast<unsigned>(BM->getAddressingModel()),
+                  static_cast<unsigned>(BM->getMemoryModel())));
   return true;
 }
 
diff --git a/llvm-spirv/lib/SPIRV/SPIRVToOCL.cpp b/llvm-spirv/lib/SPIRV/SPIRVToOCL.cpp
index 1c09fc76a5ef..74fff6c5b02f 100644
--- a/llvm-spirv/lib/SPIRV/SPIRVToOCL.cpp
+++ b/llvm-spirv/lib/SPIRV/SPIRVToOCL.cpp
@@ -257,14 +257,29 @@ void SPIRVToOCL::visitCallSPIRVGroupBuiltin(CallInst *CI, Op OC) {
   if (!HasGroupOperation) {
     DemangledName = Prefix + DemangledName;
   } else {
-    auto GO = getArgAs<spv::GroupOperation>(CI, 1);
     StringRef Op = DemangledName;
     Op = Op.drop_front(strlen(kSPIRVName::GroupPrefix));
     bool Unsigned = Op.front() == 'u';
     if (!Unsigned)
       Op = Op.drop_front(1);
-    DemangledName = Prefix + kSPIRVName::GroupPrefix +
-                    SPIRSPIRVGroupOperationMap::rmap(GO) + '_' + Op.str();
+
+    auto GO = getArgAs<spv::GroupOperation>(CI, 1);
+    std::string GroupOp = "";
+    switch (GO) {
+    case GroupOperationReduce:
+      GroupOp = "reduce";
+      break;
+    case GroupOperationInclusiveScan:
+      GroupOp = "scan_inclusive";
+      break;
+    case GroupOperationExclusiveScan:
+      GroupOp = "scan_exclusive";
+      break;
+    default:
+      assert(!"Unsupported group operation");
+      break;
+    }
+    DemangledName = Prefix + kSPIRVName::GroupPrefix + GroupOp + '_' + Op.str();
   }
   assert(CI->getCalledFunction() && "Unexpected indirect call");
   AttributeList Attrs = CI->getCalledFunction()->getAttributes();
diff --git a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp
index b5528a25457f..b19a11665e74 100644
--- a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp
+++ b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp
@@ -105,6 +105,22 @@ static void foreachKernelArgMD(
   }
 }
 
+static SPIRVMemoryModelKind getMemoryModel(Module &M) {
+  auto *MemoryModelMD = M.getNamedMetadata(kSPIRVMD::MemoryModel);
+  if (MemoryModelMD && (MemoryModelMD->getNumOperands() > 0)) {
+    auto *Ref0 = MemoryModelMD->getOperand(0);
+    if (Ref0 && Ref0->getNumOperands() > 1) {
+      auto &&ModelOp = Ref0->getOperand(1);
+      auto *ModelCI = mdconst::dyn_extract<ConstantInt>(ModelOp);
+      if (ModelCI && (ModelCI->getValue().getActiveBits() <= 64)) {
+        auto Model = static_cast<SPIRVMemoryModelKind>(ModelCI->getZExtValue());
+        return Model;
+      }
+    }
+  }
+  return SPIRVMemoryModelKind::MemoryModelMax;
+}
+
 LLVMToSPIRV::LLVMToSPIRV(SPIRVModule *SMod)
     : ModulePass(ID), M(nullptr), Ctx(nullptr), BM(SMod), SrcLang(0),
       SrcLangVer(0) {
@@ -1079,11 +1095,30 @@ SPIRVValue *LLVMToSPIRV::transValueWithoutDecoration(Value *V,
     return mapValue(V, BI);
   }
 
-  if (SelectInst *Sel = dyn_cast<SelectInst>(V))
+  if (SelectInst *Sel = dyn_cast<SelectInst>(V)) {
+    SPIRVValue *TrueValue = nullptr;
+    SPIRVValue *FalseValue = nullptr;
+    if (isa<Function>(Sel->getTrueValue())) {
+      if (!BM->checkExtension(ExtensionID::SPV_INTEL_function_pointers,
+                              SPIRVEC_FunctionPointers, toString(Sel)))
+        return nullptr;
+
+      // select with function pointers
+      auto *TrueF = cast<Function>(Sel->getTrueValue());
+      TrueValue = BM->addFunctionPointerINTELInst(
+          transType(TrueF->getType()),
+          static_cast<SPIRVFunction *>(transValue(TrueF, BB)), BB);
+      auto *FalseF = cast<Function>(Sel->getFalseValue());
+      FalseValue = BM->addFunctionPointerINTELInst(
+          transType(FalseF->getType()),
+          static_cast<SPIRVFunction *>(transValue(FalseF, BB)), BB);
+    } else {
+      TrueValue = transValue(Sel->getTrueValue(), BB);
+      FalseValue = transValue(Sel->getFalseValue(), BB);
+    }
     return mapValue(V, BM->addSelectInst(transValue(Sel->getCondition(), BB),
-                                         transValue(Sel->getTrueValue(), BB),
-                                         transValue(Sel->getFalseValue(), BB),
-                                         BB));
+                                         TrueValue, FalseValue, BB));
+  }
 
   if (AllocaInst *Alc = dyn_cast<AllocaInst>(V))
     return mapValue(
@@ -1904,6 +1939,9 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
   case Intrinsic::invariant_start:
   case Intrinsic::invariant_end:
   case Intrinsic::dbg_label:
+  case Intrinsic::trap:
+    // llvm.trap intrinsic is not implemented. But for now don't crash. This
+    // change is pending the trap/abort intrisinc implementation.
     return nullptr;
   default:
     if (SPIRVAllowUnknownIntrinsics)
@@ -2340,7 +2378,7 @@ bool LLVMToSPIRV::translate() {
   for (auto I : Defs)
     transFunction(I);
 
-  if (!transOCLKernelMetadata())
+  if (!transMetadata())
     return false;
   if (!transExecutionMode())
     return false;
@@ -2481,6 +2519,19 @@ bool LLVMToSPIRV::transExecutionMode() {
           BM->addCapability(CapabilityFPGAKernelAttributesINTEL);
         }
       } break;
+
+      case spv::ExecutionModeDenormPreserve:
+      case spv::ExecutionModeDenormFlushToZero:
+      case spv::ExecutionModeSignedZeroInfNanPreserve:
+      case spv::ExecutionModeRoundingModeRTE:
+      case spv::ExecutionModeRoundingModeRTZ: {
+        if (!BM->isAllowedToUseExtension(ExtensionID::SPV_KHR_float_controls))
+          break;
+        unsigned TargetWidth;
+        N.get(TargetWidth);
+        BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
+            BF, static_cast<ExecutionMode>(EMode), TargetWidth)));
+      } break;
       default:
         llvm_unreachable("invalid execution mode");
       }
@@ -2530,7 +2581,18 @@ void LLVMToSPIRV::transFPContract() {
   }
 }
 
-bool LLVMToSPIRV::transOCLKernelMetadata() {
+bool LLVMToSPIRV::transMetadata() {
+  if (!transOCLMetadata())
+    return false;
+
+  auto Model = getMemoryModel(*M);
+  if (Model != SPIRVMemoryModelKind::MemoryModelMax)
+    BM->setMemoryModel(static_cast<SPIRVMemoryModelKind>(Model));
+
+  return true;
+}
+
+bool LLVMToSPIRV::transOCLMetadata() {
   for (auto &F : *M) {
     if (F.getCallingConv() != CallingConv::SPIR_KERNEL)
       continue;
@@ -2764,6 +2826,7 @@ bool LLVMToSPIRV::joinFPContract(Function *F, FPContract C) {
   case FPContract::DISABLED:
     return false;
   }
+  llvm_unreachable("Unhandled FPContract value.");
 }
 
 } // namespace SPIRV
diff --git a/llvm-spirv/lib/SPIRV/SPIRVWriter.h b/llvm-spirv/lib/SPIRV/SPIRVWriter.h
index 68bf0229513b..743044ee3ecb 100644
--- a/llvm-spirv/lib/SPIRV/SPIRVWriter.h
+++ b/llvm-spirv/lib/SPIRV/SPIRVWriter.h
@@ -173,7 +173,8 @@ class LLVMToSPIRV : public ModulePass {
                                SPIRVWord *EntryPoint = nullptr,
                                SmallVectorImpl<std::string> *Dec = nullptr);
   bool oclIsKernel(Function *F);
-  bool transOCLKernelMetadata();
+  bool transMetadata();
+  bool transOCLMetadata();
   SPIRVInstruction *transBuiltinToInst(StringRef DemangledName, CallInst *CI,
                                        SPIRVBasicBlock *BB);
   SPIRVValue *transBuiltinToConstant(StringRef DemangledName, CallInst *CI);
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.cpp b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
index 28bacfdb46d2..d5609726be14 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
@@ -482,6 +482,11 @@ void SPIRVExecutionMode::decode(std::istream &I) {
   case ExecutionModeInvocations:
   case ExecutionModeOutputVertices:
   case ExecutionModeVecTypeHint:
+  case ExecutionModeDenormPreserve:
+  case ExecutionModeDenormFlushToZero:
+  case ExecutionModeSignedZeroInfNanPreserve:
+  case ExecutionModeRoundingModeRTE:
+  case ExecutionModeRoundingModeRTZ:
   case ExecutionModeSubgroupSize:
   case ExecutionModeMaxWorkDimINTEL:
   case ExecutionModeNumSIMDWorkitemsINTEL:
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.h
index 772a9e7dc355..a734f1037929 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.h
@@ -665,12 +665,52 @@ class SPIRVExecutionMode : public SPIRVAnnotation<OpExecutionMode> {
 };
 
 class SPIRVComponentExecutionModes {
-  typedef std::map<SPIRVExecutionModeKind, SPIRVExecutionMode *>
+  typedef std::multimap<SPIRVExecutionModeKind, SPIRVExecutionMode *>
       SPIRVExecutionModeMap;
+  typedef std::pair<SPIRVExecutionModeMap::const_iterator,
+                    SPIRVExecutionModeMap::const_iterator>
+      SPIRVExecutionModeRange;
 
 public:
   void addExecutionMode(SPIRVExecutionMode *ExecMode) {
-    ExecModes[ExecMode->getExecutionMode()] = ExecMode;
+    // There should not be more than 1 execution mode kind except the ones
+    // mentioned in SPV_KHR_float_controls.
+#ifndef NDEBUG
+    auto IsDenorm = [](auto EMK) {
+      return EMK == ExecutionModeDenormPreserve ||
+             EMK == ExecutionModeDenormFlushToZero;
+    };
+    auto IsRoundingMode = [](auto EMK) {
+      return EMK == ExecutionModeRoundingModeRTE ||
+             EMK == ExecutionModeRoundingModeRTZ;
+    };
+    auto IsOtherFP = [](auto EMK) {
+      return EMK == ExecutionModeSignedZeroInfNanPreserve;
+    };
+    auto IsFloatControl = [&](auto EMK) {
+      return IsDenorm(EMK) || IsRoundingMode(EMK) || IsOtherFP(EMK);
+    };
+    auto IsCompatible = [&](SPIRVExecutionMode *EM0, SPIRVExecutionMode *EM1) {
+      if (EM0->getTargetId() != EM1->getTargetId())
+        return true;
+      auto EMK0 = EM0->getExecutionMode();
+      auto EMK1 = EM1->getExecutionMode();
+      if (!IsFloatControl(EMK0) || !IsFloatControl(EMK1))
+        return EMK0 != EMK1;
+      auto TW0 = EM0->getLiterals().at(0);
+      auto TW1 = EM1->getLiterals().at(0);
+      if (TW0 != TW1)
+        return true;
+      return !(IsDenorm(EMK0) && IsDenorm(EMK1)) &&
+             !(IsRoundingMode(EMK0) && IsRoundingMode(EMK1));
+    };
+    for (auto I = ExecModes.begin(); I != ExecModes.end(); ++I) {
+      assert(IsCompatible(ExecMode, (*I).second) &&
+             "Found incompatible execution modes");
+    }
+#endif // !NDEBUG
+    SPIRVExecutionModeKind EMK = ExecMode->getExecutionMode();
+    ExecModes.emplace(EMK, ExecMode);
   }
   SPIRVExecutionMode *getExecutionMode(SPIRVExecutionModeKind EMK) const {
     auto Loc = ExecModes.find(EMK);
@@ -678,6 +718,10 @@ class SPIRVComponentExecutionModes {
       return nullptr;
     return Loc->second;
   }
+  SPIRVExecutionModeRange
+  getExecutionModeRange(SPIRVExecutionModeKind EMK) const {
+    return ExecModes.equal_range(EMK);
+  }
 
 protected:
   SPIRVExecutionModeMap ExecModes;
@@ -743,6 +787,15 @@ class SPIRVCapability : public SPIRVEntryNoId<OpCapability> {
 
   SPIRVWord getRequiredSPIRVVersion() const override {
     switch (Kind) {
+    case CapabilityGroupNonUniform:
+    case CapabilityGroupNonUniformVote:
+    case CapabilityGroupNonUniformArithmetic:
+    case CapabilityGroupNonUniformBallot:
+    case CapabilityGroupNonUniformShuffle:
+    case CapabilityGroupNonUniformShuffleRelative:
+    case CapabilityGroupNonUniformClustered:
+      return static_cast<SPIRVWord>(VersionNumber::SPIRV_1_3);
+
     case CapabilityNamedBarrier:
     case CapabilitySubgroupDispatch:
     case CapabilityPipeStorage:
@@ -753,6 +806,19 @@ class SPIRVCapability : public SPIRVEntryNoId<OpCapability> {
     }
   }
 
+  SPIRVExtSet getRequiredExtensions() const override {
+    switch (Kind) {
+    case CapabilityDenormPreserve:
+    case CapabilityDenormFlushToZero:
+    case CapabilitySignedZeroInfNanPreserve:
+    case CapabilityRoundingModeRTE:
+    case CapabilityRoundingModeRTZ:
+      return getSet(ExtensionID::SPV_KHR_float_controls);
+    default:
+      return SPIRVExtSet();
+    }
+  }
+
 private:
   SPIRVCapabilityKind Kind;
 };
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h
index 2fbd8d2603f1..6d24877a0230 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h
@@ -237,6 +237,13 @@ template <> inline void SPIRVMap<SPIRVExecutionModeKind, SPIRVCapVec>::init() {
   ADD_VEC_INIT(ExecutionModeOutputTriangleStrip, {CapabilityGeometry});
   ADD_VEC_INIT(ExecutionModeVecTypeHint, {CapabilityKernel});
   ADD_VEC_INIT(ExecutionModeContractionOff, {CapabilityKernel});
+  ADD_VEC_INIT(ExecutionModeSubgroupSize, {CapabilitySubgroupDispatch});
+  ADD_VEC_INIT(ExecutionModeDenormPreserve, {CapabilityDenormPreserve});
+  ADD_VEC_INIT(ExecutionModeDenormFlushToZero, {CapabilityDenormFlushToZero});
+  ADD_VEC_INIT(ExecutionModeSignedZeroInfNanPreserve,
+               {CapabilitySignedZeroInfNanPreserve});
+  ADD_VEC_INIT(ExecutionModeRoundingModeRTE, {CapabilityRoundingModeRTE});
+  ADD_VEC_INIT(ExecutionModeRoundingModeRTZ, {CapabilityRoundingModeRTZ});
 }
 
 template <> inline void SPIRVMap<SPIRVMemoryModelKind, SPIRVCapVec>::init() {
@@ -407,6 +414,11 @@ template <> inline void SPIRVMap<BuiltIn, SPIRVCapVec>::init() {
   ADD_VEC_INIT(BuiltInNumEnqueuedSubgroups, {CapabilityKernel});
   ADD_VEC_INIT(BuiltInSubgroupId, {CapabilityKernel});
   ADD_VEC_INIT(BuiltInSubgroupLocalInvocationId, {CapabilityKernel});
+  ADD_VEC_INIT(BuiltInSubgroupEqMask, {CapabilityGroupNonUniformBallot});
+  ADD_VEC_INIT(BuiltInSubgroupGeMask, {CapabilityGroupNonUniformBallot});
+  ADD_VEC_INIT(BuiltInSubgroupGtMask, {CapabilityGroupNonUniformBallot});
+  ADD_VEC_INIT(BuiltInSubgroupLeMask, {CapabilityGroupNonUniformBallot});
+  ADD_VEC_INIT(BuiltInSubgroupLtMask, {CapabilityGroupNonUniformBallot});
   ADD_VEC_INIT(BuiltInVertexIndex, {CapabilityShader});
   ADD_VEC_INIT(BuiltInInstanceIndex, {CapabilityShader});
 }
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h
index 8f28bd326555..c20ad86fd3c9 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h
@@ -2275,7 +2275,6 @@ class SPIRVVectorShuffle : public SPIRVInstruction {
       return;
     assert(getValueType(Vector1) == getValueType(Vector2));
     assert(Components.size() == Type->getVectorComponentCount());
-    assert(Components.size() > 1);
   }
   SPIRVId Vector1;
   SPIRVId Vector2;
@@ -2518,6 +2517,123 @@ _SPIRV_OP(GroupCommitReadPipe, false, 6)
 _SPIRV_OP(GroupCommitWritePipe, false, 6)
 #undef _SPIRV_OP
 
+class SPIRVGroupNonUniformElectInst : public SPIRVInstTemplateBase {
+public:
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityGroupNonUniform);
+  }
+};
+
+#define _SPIRV_OP(x, ...)                                                      \
+  typedef SPIRVInstTemplate<SPIRVGroupNonUniformElectInst, Op##x, __VA_ARGS__> \
+      SPIRV##x;
+_SPIRV_OP(GroupNonUniformElect, true, 4)
+#undef _SPIRV_OP
+
+class SPIRVGroupNonUniformVoteInst : public SPIRVInstTemplateBase {
+public:
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityGroupNonUniformVote);
+  }
+};
+
+#define _SPIRV_OP(x, ...)                                                      \
+  typedef SPIRVInstTemplate<SPIRVGroupNonUniformVoteInst, Op##x, __VA_ARGS__>  \
+      SPIRV##x;
+_SPIRV_OP(GroupNonUniformAll, true, 5)
+_SPIRV_OP(GroupNonUniformAny, true, 5)
+_SPIRV_OP(GroupNonUniformAllEqual, true, 5)
+#undef _SPIRV_OP
+
+class SPIRVGroupNonUniformBallotInst : public SPIRVInstTemplateBase {
+public:
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityGroupNonUniformBallot);
+  }
+};
+
+#define _SPIRV_OP(x, ...)                                                      \
+  typedef SPIRVInstTemplate<SPIRVGroupNonUniformBallotInst, Op##x,             \
+                            __VA_ARGS__>                                       \
+      SPIRV##x;
+_SPIRV_OP(GroupNonUniformBroadcast, true, 6)
+_SPIRV_OP(GroupNonUniformBroadcastFirst, true, 5)
+_SPIRV_OP(GroupNonUniformBallot, true, 5)
+_SPIRV_OP(GroupNonUniformInverseBallot, true, 5)
+_SPIRV_OP(GroupNonUniformBallotBitExtract, true, 6)
+_SPIRV_OP(GroupNonUniformBallotBitCount, true, 6, false, 1)
+_SPIRV_OP(GroupNonUniformBallotFindLSB, true, 5)
+_SPIRV_OP(GroupNonUniformBallotFindMSB, true, 5)
+#undef _SPIRV_OP
+
+class SPIRVGroupNonUniformArithmeticInst : public SPIRVInstTemplateBase {
+public:
+  void setOpWords(const std::vector<SPIRVWord> &Ops) override {
+    SPIRVInstTemplateBase::setOpWords(Ops);
+    SPIRVGroupOperationKind GroupOp;
+    if (getSPIRVGroupOperation(GroupOp)) {
+      if (GroupOp == GroupOperationClusteredReduce)
+        Module->addCapability(CapabilityGroupNonUniformClustered);
+      else
+        Module->addCapability(CapabilityGroupNonUniformArithmetic);
+    } else
+      llvm_unreachable(
+          "GroupNonUniformArithmeticInst has no group operation operand!");
+  }
+};
+
+#define _SPIRV_OP(x, ...)                                                      \
+  typedef SPIRVInstTemplate<SPIRVGroupNonUniformArithmeticInst, Op##x,         \
+                            __VA_ARGS__>                                       \
+      SPIRV##x;
+_SPIRV_OP(GroupNonUniformIAdd, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformFAdd, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformIMul, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformFMul, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformSMin, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformUMin, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformFMin, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformSMax, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformUMax, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformFMax, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformBitwiseAnd, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformBitwiseOr, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformBitwiseXor, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformLogicalAnd, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformLogicalOr, true, 6, true, 1)
+_SPIRV_OP(GroupNonUniformLogicalXor, true, 6, true, 1)
+#undef _SPIRV_OP
+
+class SPIRVGroupNonUniformShuffleInst : public SPIRVInstTemplateBase {
+public:
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityGroupNonUniformShuffle);
+  }
+};
+
+#define _SPIRV_OP(x, ...)                                                      \
+  typedef SPIRVInstTemplate<SPIRVGroupNonUniformShuffleInst, Op##x,            \
+                            __VA_ARGS__>                                       \
+      SPIRV##x;
+_SPIRV_OP(GroupNonUniformShuffle, true, 6)
+_SPIRV_OP(GroupNonUniformShuffleXor, true, 6)
+#undef _SPIRV_OP
+
+class SPIRVGroupNonUniformShuffleRelativeInst : public SPIRVInstTemplateBase {
+public:
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityGroupNonUniformShuffleRelative);
+  }
+};
+
+#define _SPIRV_OP(x, ...)                                                      \
+  typedef SPIRVInstTemplate<SPIRVGroupNonUniformShuffleRelativeInst, Op##x,    \
+                            __VA_ARGS__>                                       \
+      SPIRV##x;
+_SPIRV_OP(GroupNonUniformShuffleUp, true, 6)
+_SPIRV_OP(GroupNonUniformShuffleDown, true, 6)
+#undef _SPIRV_OP
+
 class SPIRVBlockingPipesIntelInst : public SPIRVInstTemplateBase {
 protected:
   SPIRVCapVec getRequiredCapability() const override {
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
index 393471b87471..3db6bb9f8a59 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
@@ -144,6 +144,11 @@ inline bool isValid(spv::ExecutionMode V) {
   case ExecutionModeNoGlobalOffsetINTEL:
   case ExecutionModeMaxWorkDimINTEL:
   case ExecutionModeNumSIMDWorkitemsINTEL:
+  case ExecutionModeDenormPreserve:
+  case ExecutionModeDenormFlushToZero:
+  case ExecutionModeSignedZeroInfNanPreserve:
+  case ExecutionModeRoundingModeRTE:
+  case ExecutionModeRoundingModeRTZ:
     return true;
   default:
     return false;
@@ -459,6 +464,11 @@ inline bool isValid(spv::BuiltIn V) {
   case BuiltInNumEnqueuedSubgroups:
   case BuiltInSubgroupId:
   case BuiltInSubgroupLocalInvocationId:
+  case BuiltInSubgroupEqMask:
+  case BuiltInSubgroupGeMask:
+  case BuiltInSubgroupGtMask:
+  case BuiltInSubgroupLeMask:
+  case BuiltInSubgroupLtMask:
   case BuiltInVertexIndex:
   case BuiltInInstanceIndex:
     return true;
@@ -563,6 +573,19 @@ inline bool isValid(spv::Capability V) {
   case CapabilitySubgroupDispatch:
   case CapabilityNamedBarrier:
   case CapabilityPipeStorage:
+  case CapabilityGroupNonUniform:
+  case CapabilityGroupNonUniformVote:
+  case CapabilityGroupNonUniformArithmetic:
+  case CapabilityGroupNonUniformBallot:
+  case CapabilityGroupNonUniformShuffle:
+  case CapabilityGroupNonUniformShuffleRelative:
+  case CapabilityGroupNonUniformClustered:
+  case CapabilityGroupNonUniformQuad:
+  case CapabilityDenormPreserve:
+  case CapabilityDenormFlushToZero:
+  case CapabilitySignedZeroInfNanPreserve:
+  case CapabilityRoundingModeRTE:
+  case CapabilityRoundingModeRTZ:
   case CapabilityFPGAMemoryAttributesINTEL:
   case CapabilityArbitraryPrecisionIntegersINTEL:
   case CapabilityFPGALoopControlsINTEL:
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp
index 2cc1120f4e22..de2f3b574647 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp
@@ -600,7 +600,16 @@ void SPIRVModuleImpl::addCapability(SPIRVCapabilityKind Cap) {
   if (hasCapability(Cap))
     return;
 
-  CapMap.insert(std::make_pair(Cap, new SPIRVCapability(this, Cap)));
+  auto *CapObj = new SPIRVCapability(this, Cap);
+  if (AutoAddExtensions) {
+    // While we are reading existing SPIR-V we need to read it as-is and don't
+    // add required extensions for each entry automatically
+    for (auto &E : CapObj->getRequiredExtensions()) {
+      addExtension(E);
+    }
+  }
+
+  CapMap.insert(std::make_pair(Cap, CapObj));
 }
 
 void SPIRVModuleImpl::addCapabilityInternal(SPIRVCapabilityKind Cap) {
@@ -1758,6 +1767,12 @@ static std::string to_string(uint32_t Version) {
   case static_cast<uint32_t>(VersionNumber::SPIRV_1_1):
     Res = "1.1";
     break;
+  case static_cast<uint32_t>(VersionNumber::SPIRV_1_2):
+    Res = "1.2";
+    break;
+  case static_cast<uint32_t>(VersionNumber::SPIRV_1_3):
+    Res = "1.3";
+    break;
   default:
     Res = "unknown";
   }
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
index 909ee6454179..0a62838dff76 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
@@ -123,6 +123,11 @@ template <> inline void SPIRVMap<ExecutionMode, std::string>::init() {
   add(ExecutionModeNoGlobalOffsetINTEL, "NoGlobalOffsetINTEL");
   add(ExecutionModeMaxWorkDimINTEL, "MaxWorkDimINTEL");
   add(ExecutionModeNumSIMDWorkitemsINTEL, "NumSIMDWorkitemsINTEL");
+  add(ExecutionModeDenormPreserve, "DenormPreserve");
+  add(ExecutionModeDenormFlushToZero, "DenormFlushToZero");
+  add(ExecutionModeSignedZeroInfNanPreserve, "SignedZeroInfNanPreserve");
+  add(ExecutionModeRoundingModeRTE, "RoundingModeRTE");
+  add(ExecutionModeRoundingModeRTZ, "RoundingModeRTZ");
 }
 SPIRV_DEF_NAMEMAP(ExecutionMode, SPIRVExecutionModeNameMap)
 
@@ -394,6 +399,11 @@ template <> inline void SPIRVMap<BuiltIn, std::string>::init() {
   add(BuiltInNumEnqueuedSubgroups, "BuiltInNumEnqueuedSubgroups");
   add(BuiltInSubgroupId, "BuiltInSubgroupId");
   add(BuiltInSubgroupLocalInvocationId, "BuiltInSubgroupLocalInvocationId");
+  add(BuiltInSubgroupEqMask, "BuiltInSubgroupEqMask");
+  add(BuiltInSubgroupGeMask, "BuiltInSubgroupGeMask");
+  add(BuiltInSubgroupGtMask, "BuiltInSubgroupGtMask");
+  add(BuiltInSubgroupLeMask, "BuiltInSubgroupLeMask");
+  add(BuiltInSubgroupLtMask, "BuiltInSubgroupLtMask");
   add(BuiltInVertexIndex, "BuiltInVertexIndex");
   add(BuiltInInstanceIndex, "BuiltInInstanceIndex");
 }
@@ -485,6 +495,12 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
   add(CapabilityStorageImageWriteWithoutFormat,
       "StorageImageWriteWithoutFormat");
   add(CapabilityMultiViewport, "MultiViewport");
+  add(CapabilitySubgroupDispatch, "CapabilitySubgroupDispatch");
+  add(CapabilityDenormPreserve, "DenormPreserve");
+  add(CapabilityDenormFlushToZero, "DenormFlushToZero");
+  add(CapabilitySignedZeroInfNanPreserve, "SignedZeroInfNanPreserve");
+  add(CapabilityRoundingModeRTE, "RoundingModeRTE");
+  add(CapabilityRoundingModeRTZ, "RoundingModeRTZ");
   add(CapabilitySubgroupShuffleINTEL, "SubgroupShuffleINTEL");
   add(CapabilitySubgroupBufferBlockIOINTEL, "SubgroupBufferBlockIOINTEL");
   add(CapabilitySubgroupImageBlockIOINTEL, "SubgroupImageBlockIOINTEL");
@@ -510,6 +526,14 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
   add(CapabilityFPGAKernelAttributesINTEL, "FPGAKernelAttributesINTEL");
   add(CapabilityIOPipeINTEL, "IOPipeINTEL");
   add(CapabilityOptimizationHintsINTEL, "OptimizationHintsINTEL");
+  add(CapabilityGroupNonUniform, "GroupNonUniform");
+  add(CapabilityGroupNonUniformVote, "GroupNonUniformVote");
+  add(CapabilityGroupNonUniformArithmetic, "GroupNonUniformArithmetic");
+  add(CapabilityGroupNonUniformBallot, "GroupNonUniformBallot");
+  add(CapabilityGroupNonUniformShuffle, "GroupNonUniformShuffle");
+  add(CapabilityGroupNonUniformShuffleRelative,
+      "GroupNonUniformShuffleRelative");
+  add(CapabilityGroupNonUniformClustered, "GroupNonUniformClustered");
 }
 SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
 
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCode.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCode.h
index 271378eba11b..f7a4c7c85457 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCode.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCode.h
@@ -131,7 +131,9 @@ inline bool hasExecScope(Op OpCode) {
 
 inline bool hasGroupOperation(Op OpCode) {
   unsigned OC = OpCode;
-  return OpGroupIAdd <= OC && OC <= OpGroupSMax;
+  return (OpGroupIAdd <= OC && OC <= OpGroupSMax) ||
+         (OpGroupNonUniformBallotBitCount == OC) ||
+         (OpGroupNonUniformIAdd <= OC && OC <= OpGroupNonUniformLogicalXor);
 }
 
 inline bool isGroupOpCode(Op OpCode) {
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
index e5f02881bdfb..a0e6643b98f0 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
@@ -294,6 +294,38 @@ _SPIRV_OP(AtomicFlagClear, 319)
 _SPIRV_OP(TypePipeStorage, 322)
 _SPIRV_OP(ConstantPipeStorage, 323)
 _SPIRV_OP(CreatePipeFromPipeStorage, 324)
+_SPIRV_OP(GroupNonUniformElect, 333)
+_SPIRV_OP(GroupNonUniformAll, 334)
+_SPIRV_OP(GroupNonUniformAny, 335)
+_SPIRV_OP(GroupNonUniformAllEqual, 336)
+_SPIRV_OP(GroupNonUniformBroadcast, 337)
+_SPIRV_OP(GroupNonUniformBroadcastFirst, 338)
+_SPIRV_OP(GroupNonUniformBallot, 339)
+_SPIRV_OP(GroupNonUniformInverseBallot, 340)
+_SPIRV_OP(GroupNonUniformBallotBitExtract, 341)
+_SPIRV_OP(GroupNonUniformBallotBitCount, 342)
+_SPIRV_OP(GroupNonUniformBallotFindLSB, 343)
+_SPIRV_OP(GroupNonUniformBallotFindMSB, 344)
+_SPIRV_OP(GroupNonUniformShuffle, 345)
+_SPIRV_OP(GroupNonUniformShuffleXor, 346)
+_SPIRV_OP(GroupNonUniformShuffleUp, 347)
+_SPIRV_OP(GroupNonUniformShuffleDown, 348)
+_SPIRV_OP(GroupNonUniformIAdd, 349)
+_SPIRV_OP(GroupNonUniformFAdd, 350)
+_SPIRV_OP(GroupNonUniformIMul, 351)
+_SPIRV_OP(GroupNonUniformFMul, 352)
+_SPIRV_OP(GroupNonUniformSMin, 353)
+_SPIRV_OP(GroupNonUniformUMin, 354)
+_SPIRV_OP(GroupNonUniformFMin, 355)
+_SPIRV_OP(GroupNonUniformSMax, 356)
+_SPIRV_OP(GroupNonUniformUMax, 357)
+_SPIRV_OP(GroupNonUniformFMax, 358)
+_SPIRV_OP(GroupNonUniformBitwiseAnd, 359)
+_SPIRV_OP(GroupNonUniformBitwiseOr, 360)
+_SPIRV_OP(GroupNonUniformBitwiseXor, 361)
+_SPIRV_OP(GroupNonUniformLogicalAnd, 362)
+_SPIRV_OP(GroupNonUniformLogicalOr, 363)
+_SPIRV_OP(GroupNonUniformLogicalXor, 364)
 _SPIRV_OP(Forward, 1024)
 _SPIRV_OP(SubgroupShuffleINTEL, 5571)
 _SPIRV_OP(SubgroupShuffleDownINTEL, 5572)
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVType.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVType.h
index c717bc005f1b..1ce1d3058fcf 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVType.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVType.h
@@ -305,7 +305,7 @@ class SPIRVTypeVector : public SPIRVType {
     SPIRVCapVec V(getComponentType()->getRequiredCapability());
     // Even though the capability name is "Vector16", it describes
     // usage of 8-component or 16-component vectors.
-    if (CompCount >= 8)
+    if (CompCount == 8 || CompCount == 16)
       V.push_back(CapabilityVector16);
     return V;
   }
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp b/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp
index 1db39409e510..cb4cacb7c0c6 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp
@@ -1,19 +1,19 @@
-// Copyright (c) 2014-2017 The Khronos Group Inc.
-//
+// Copyright (c) 2014-2019 The Khronos Group Inc.
+// 
 // Permission is hereby granted, free of charge, to any person obtaining a copy
 // of this software and/or associated documentation files (the "Materials"),
 // to deal in the Materials without restriction, including without limitation
 // the rights to use, copy, modify, merge, publish, distribute, sublicense,
 // and/or sell copies of the Materials, and to permit persons to whom the
 // Materials are furnished to do so, subject to the following conditions:
-//
+// 
 // The above copyright notice and this permission notice shall be included in
 // all copies or substantial portions of the Materials.
-//
+// 
 // MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS KHRONOS
 // STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS SPECIFICATIONS AND
-// HEADER INFORMATION ARE LOCATED AT https://www.khronos.org/registry/
-//
+// HEADER INFORMATION ARE LOCATED AT https://www.khronos.org/registry/ 
+// 
 // THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 // OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -26,14 +26,17 @@
 // the Binary Section of the SPIR-V specification.
 
 // Enumeration tokens for SPIR-V, in various styles:
-//   C, C++, C++11, JSON, Lua, Python
-//
+//   C, C++, C++11, JSON, Lua, Python, C#, D
+// 
 // - C will have tokens with a "Spv" prefix, e.g.: SpvSourceLanguageGLSL
 // - C++ will have tokens in the "spv" name space, e.g.: spv::SourceLanguageGLSL
 // - C++11 will use enum classes in the spv namespace, e.g.: spv::SourceLanguage::GLSL
 // - Lua will use tables, e.g.: spv.SourceLanguage.GLSL
 // - Python will use dictionaries, e.g.: spv['SourceLanguage']['GLSL']
-//
+// - C# will use enum classes in the Specification class located in the "Spv" namespace,
+//     e.g.: Spv.Specification.SourceLanguage.GLSL
+// - D will have tokens under the "spv" module, e.g: spv.SourceLanguage.GLSL
+// 
 // Some tokens act like mask values, which can be OR'd together,
 // while others are mutually exclusive.  The mask-like ones have
 // "Mask" in their name, and a parallel enum that has the shift
@@ -46,12 +49,12 @@ namespace spv {
 
 typedef unsigned int Id;
 
-#define SPV_VERSION 0x10100
-#define SPV_REVISION 7
+#define SPV_VERSION 0x10500
+#define SPV_REVISION 1
 
 static const unsigned int MagicNumber = 0x07230203;
-static const unsigned int Version = 0x00010100;
-static const unsigned int Revision = 7;
+static const unsigned int Version = 0x00010500;
+static const unsigned int Revision = 1;
 static const unsigned int OpCodeMask = 0xffff;
 static const unsigned int WordCountShift = 16;
 
@@ -73,6 +76,14 @@ enum ExecutionModel {
     ExecutionModelFragment = 4,
     ExecutionModelGLCompute = 5,
     ExecutionModelKernel = 6,
+    ExecutionModelTaskNV = 5267,
+    ExecutionModelMeshNV = 5268,
+    ExecutionModelRayGenerationNV = 5313,
+    ExecutionModelIntersectionNV = 5314,
+    ExecutionModelAnyHitNV = 5315,
+    ExecutionModelClosestHitNV = 5316,
+    ExecutionModelMissNV = 5317,
+    ExecutionModelCallableNV = 5318,
     ExecutionModelMax = 0x7fffffff,
 };
 
@@ -80,6 +91,8 @@ enum AddressingModel {
     AddressingModelLogical = 0,
     AddressingModelPhysical32 = 1,
     AddressingModelPhysical64 = 2,
+    AddressingModelPhysicalStorageBuffer64 = 5348,
+    AddressingModelPhysicalStorageBuffer64EXT = 5348,
     AddressingModelMax = 0x7fffffff,
 };
 
@@ -87,6 +100,8 @@ enum MemoryModel {
     MemoryModelSimple = 0,
     MemoryModelGLSL450 = 1,
     MemoryModelOpenCL = 2,
+    MemoryModelVulkan = 3,
+    MemoryModelVulkanKHR = 3,
     MemoryModelMax = 0x7fffffff,
 };
 
@@ -126,6 +141,27 @@ enum ExecutionMode {
     ExecutionModeFinalizer = 34,
     ExecutionModeSubgroupSize = 35,
     ExecutionModeSubgroupsPerWorkgroup = 36,
+    ExecutionModeSubgroupsPerWorkgroupId = 37,
+    ExecutionModeLocalSizeId = 38,
+    ExecutionModeLocalSizeHintId = 39,
+    ExecutionModePostDepthCoverage = 4446,
+    ExecutionModeDenormPreserve = 4459,
+    ExecutionModeDenormFlushToZero = 4460,
+    ExecutionModeSignedZeroInfNanPreserve = 4461,
+    ExecutionModeRoundingModeRTE = 4462,
+    ExecutionModeRoundingModeRTZ = 4463,
+    ExecutionModeStencilRefReplacingEXT = 5027,
+    ExecutionModeOutputLinesNV = 5269,
+    ExecutionModeOutputPrimitivesNV = 5270,
+    ExecutionModeDerivativeGroupQuadsNV = 5289,
+    ExecutionModeDerivativeGroupLinearNV = 5290,
+    ExecutionModeOutputTrianglesNV = 5298,
+    ExecutionModePixelInterlockOrderedEXT = 5366,
+    ExecutionModePixelInterlockUnorderedEXT = 5367,
+    ExecutionModeSampleInterlockOrderedEXT = 5368,
+    ExecutionModeSampleInterlockUnorderedEXT = 5369,
+    ExecutionModeShadingRateInterlockOrderedEXT = 5370,
+    ExecutionModeShadingRateInterlockUnorderedEXT = 5371,
     ExecutionModeMaxWorkgroupSizeINTEL = 5893,
     ExecutionModeMaxWorkDimINTEL = 5894,
     ExecutionModeNoGlobalOffsetINTEL = 5895,
@@ -147,6 +183,14 @@ enum StorageClass {
     StorageClassAtomicCounter = 10,
     StorageClassImage = 11,
     StorageClassStorageBuffer = 12,
+    StorageClassCallableDataNV = 5328,
+    StorageClassIncomingCallableDataNV = 5329,
+    StorageClassRayPayloadNV = 5338,
+    StorageClassHitAttributeNV = 5339,
+    StorageClassIncomingRayPayloadNV = 5342,
+    StorageClassShaderRecordBufferNV = 5343,
+    StorageClassPhysicalStorageBuffer = 5349,
+    StorageClassPhysicalStorageBufferEXT = 5349,
     StorageClassMax = 0x7fffffff,
 };
 
@@ -274,6 +318,16 @@ enum ImageOperandsShift {
     ImageOperandsConstOffsetsShift = 5,
     ImageOperandsSampleShift = 6,
     ImageOperandsMinLodShift = 7,
+    ImageOperandsMakeTexelAvailableShift = 8,
+    ImageOperandsMakeTexelAvailableKHRShift = 8,
+    ImageOperandsMakeTexelVisibleShift = 9,
+    ImageOperandsMakeTexelVisibleKHRShift = 9,
+    ImageOperandsNonPrivateTexelShift = 10,
+    ImageOperandsNonPrivateTexelKHRShift = 10,
+    ImageOperandsVolatileTexelShift = 11,
+    ImageOperandsVolatileTexelKHRShift = 11,
+    ImageOperandsSignExtendShift = 12,
+    ImageOperandsZeroExtendShift = 13,
     ImageOperandsMax = 0x7fffffff,
 };
 
@@ -287,6 +341,16 @@ enum ImageOperandsMask {
     ImageOperandsConstOffsetsMask = 0x00000020,
     ImageOperandsSampleMask = 0x00000040,
     ImageOperandsMinLodMask = 0x00000080,
+    ImageOperandsMakeTexelAvailableMask = 0x00000100,
+    ImageOperandsMakeTexelAvailableKHRMask = 0x00000100,
+    ImageOperandsMakeTexelVisibleMask = 0x00000200,
+    ImageOperandsMakeTexelVisibleKHRMask = 0x00000200,
+    ImageOperandsNonPrivateTexelMask = 0x00000400,
+    ImageOperandsNonPrivateTexelKHRMask = 0x00000400,
+    ImageOperandsVolatileTexelMask = 0x00000800,
+    ImageOperandsVolatileTexelKHRMask = 0x00000800,
+    ImageOperandsSignExtendMask = 0x00001000,
+    ImageOperandsZeroExtendMask = 0x00002000,
 };
 
 enum FPFastMathModeShift {
@@ -368,6 +432,7 @@ enum Decoration {
   DecorationNonWritable = 24,
   DecorationNonReadable = 25,
   DecorationUniform = 26,
+  DecorationUniformId = 27,
   DecorationSaturatedConversion = 28,
   DecorationStream = 29,
   DecorationLocation = 30,
@@ -386,15 +451,32 @@ enum Decoration {
   DecorationInputAttachmentIndex = 43,
   DecorationAlignment = 44,
   DecorationMaxByteOffset = 45,
+  DecorationAlignmentId = 46,
+  DecorationMaxByteOffsetId = 47,
   DecorationNoSignedWrap = 4469,
   DecorationNoUnsignedWrap = 4470,
+  DecorationExplicitInterpAMD = 4999,
   DecorationOverrideCoverageNV = 5248,
   DecorationPassthroughNV = 5250,
   DecorationViewportRelativeNV = 5252,
   DecorationSecondaryViewportRelativeNV = 5256,
+  DecorationPerPrimitiveNV = 5271,
+  DecorationPerViewNV = 5272,
+  DecorationPerTaskNV = 5273,
+  DecorationPerVertexNV = 5285,
+  DecorationNonUniform = 5300,
+  DecorationNonUniformEXT = 5300,
+  DecorationRestrictPointer = 5355,
+  DecorationRestrictPointerEXT = 5355,
+  DecorationAliasedPointer = 5356,
+  DecorationAliasedPointerEXT = 5356,
   DecorationReferencedIndirectlyINTEL = 5602,
   DecorationSideEffectsINTEL = 5608,
+  DecorationCounterBuffer = 5634,
+  DecorationHlslCounterBufferGOOGLE = 5634,
+  DecorationHlslSemanticGOOGLE = 5635,
   DecorationUserSemantic = 5635,
+  DecorationUserTypeGOOGLE = 5636,
   DecorationRegisterINTEL = 5825,
   DecorationMemoryINTEL = 5826,
   DecorationNumbanksINTEL = 5827,
@@ -453,21 +535,67 @@ enum BuiltIn {
     BuiltInSubgroupLocalInvocationId = 41,
     BuiltInVertexIndex = 42,
     BuiltInInstanceIndex = 43,
+    BuiltInSubgroupEqMask = 4416,
     BuiltInSubgroupEqMaskKHR = 4416,
+    BuiltInSubgroupGeMask = 4417,
     BuiltInSubgroupGeMaskKHR = 4417,
+    BuiltInSubgroupGtMask = 4418,
     BuiltInSubgroupGtMaskKHR = 4418,
+    BuiltInSubgroupLeMask = 4419,
     BuiltInSubgroupLeMaskKHR = 4419,
+    BuiltInSubgroupLtMask = 4420,
     BuiltInSubgroupLtMaskKHR = 4420,
     BuiltInBaseVertex = 4424,
     BuiltInBaseInstance = 4425,
     BuiltInDrawIndex = 4426,
     BuiltInDeviceIndex = 4438,
     BuiltInViewIndex = 4440,
+    BuiltInBaryCoordNoPerspAMD = 4992,
+    BuiltInBaryCoordNoPerspCentroidAMD = 4993,
+    BuiltInBaryCoordNoPerspSampleAMD = 4994,
+    BuiltInBaryCoordSmoothAMD = 4995,
+    BuiltInBaryCoordSmoothCentroidAMD = 4996,
+    BuiltInBaryCoordSmoothSampleAMD = 4997,
+    BuiltInBaryCoordPullModelAMD = 4998,
+    BuiltInFragStencilRefEXT = 5014,
     BuiltInViewportMaskNV = 5253,
     BuiltInSecondaryPositionNV = 5257,
     BuiltInSecondaryViewportMaskNV = 5258,
     BuiltInPositionPerViewNV = 5261,
     BuiltInViewportMaskPerViewNV = 5262,
+    BuiltInFullyCoveredEXT = 5264,
+    BuiltInTaskCountNV = 5274,
+    BuiltInPrimitiveCountNV = 5275,
+    BuiltInPrimitiveIndicesNV = 5276,
+    BuiltInClipDistancePerViewNV = 5277,
+    BuiltInCullDistancePerViewNV = 5278,
+    BuiltInLayerPerViewNV = 5279,
+    BuiltInMeshViewCountNV = 5280,
+    BuiltInMeshViewIndicesNV = 5281,
+    BuiltInBaryCoordNV = 5286,
+    BuiltInBaryCoordNoPerspNV = 5287,
+    BuiltInFragSizeEXT = 5292,
+    BuiltInFragmentSizeNV = 5292,
+    BuiltInFragInvocationCountEXT = 5293,
+    BuiltInInvocationsPerPixelNV = 5293,
+    BuiltInLaunchIdNV = 5319,
+    BuiltInLaunchSizeNV = 5320,
+    BuiltInWorldRayOriginNV = 5321,
+    BuiltInWorldRayDirectionNV = 5322,
+    BuiltInObjectRayOriginNV = 5323,
+    BuiltInObjectRayDirectionNV = 5324,
+    BuiltInRayTminNV = 5325,
+    BuiltInRayTmaxNV = 5326,
+    BuiltInInstanceCustomIndexNV = 5327,
+    BuiltInObjectToWorldNV = 5330,
+    BuiltInWorldToObjectNV = 5331,
+    BuiltInHitTNV = 5332,
+    BuiltInHitKindNV = 5333,
+    BuiltInIncomingRayFlagsNV = 5351,
+    BuiltInWarpsPerSMNV = 5374,
+    BuiltInSMCountNV = 5375,
+    BuiltInWarpIDNV = 5376,
+    BuiltInSMIDNV = 5377,
     BuiltInMax = 0x7fffffff,
 };
 
@@ -488,6 +616,11 @@ enum LoopControlShift {
     LoopControlDontUnrollShift = 1,
     LoopControlDependencyInfiniteShift = 2,
     LoopControlDependencyLengthShift = 3,
+    LoopControlMinIterationsShift = 4,
+    LoopControlMaxIterationsShift = 5,
+    LoopControlIterationMultipleShift = 6,
+    LoopControlPeelCountShift = 7,
+    LoopControlPartialCountShift = 8,
     LoopControlMax = 0x7fffffff,
 };
 
@@ -538,6 +671,13 @@ enum MemorySemanticsShift {
     MemorySemanticsCrossWorkgroupMemoryShift = 9,
     MemorySemanticsAtomicCounterMemoryShift = 10,
     MemorySemanticsImageMemoryShift = 11,
+    MemorySemanticsOutputMemoryShift = 12,
+    MemorySemanticsOutputMemoryKHRShift = 12,
+    MemorySemanticsMakeAvailableShift = 13,
+    MemorySemanticsMakeAvailableKHRShift = 13,
+    MemorySemanticsMakeVisibleShift = 14,
+    MemorySemanticsMakeVisibleKHRShift = 14,
+    MemorySemanticsVolatileShift = 15,
     MemorySemanticsMax = 0x7fffffff,
 };
 
@@ -553,12 +693,25 @@ enum MemorySemanticsMask {
     MemorySemanticsCrossWorkgroupMemoryMask = 0x00000200,
     MemorySemanticsAtomicCounterMemoryMask = 0x00000400,
     MemorySemanticsImageMemoryMask = 0x00000800,
+    MemorySemanticsOutputMemoryMask = 0x00001000,
+    MemorySemanticsOutputMemoryKHRMask = 0x00001000,
+    MemorySemanticsMakeAvailableMask = 0x00002000,
+    MemorySemanticsMakeAvailableKHRMask = 0x00002000,
+    MemorySemanticsMakeVisibleMask = 0x00004000,
+    MemorySemanticsMakeVisibleKHRMask = 0x00004000,
+    MemorySemanticsVolatileMask = 0x00008000,
 };
 
 enum MemoryAccessShift {
     MemoryAccessVolatileShift = 0,
     MemoryAccessAlignedShift = 1,
     MemoryAccessNontemporalShift = 2,
+    MemoryAccessMakePointerAvailableShift = 3,
+    MemoryAccessMakePointerAvailableKHRShift = 3,
+    MemoryAccessMakePointerVisibleShift = 4,
+    MemoryAccessMakePointerVisibleKHRShift = 4,
+    MemoryAccessNonPrivatePointerShift = 5,
+    MemoryAccessNonPrivatePointerKHRShift = 5,
     MemoryAccessMax = 0x7fffffff,
 };
 
@@ -567,6 +720,12 @@ enum MemoryAccessMask {
     MemoryAccessVolatileMask = 0x00000001,
     MemoryAccessAlignedMask = 0x00000002,
     MemoryAccessNontemporalMask = 0x00000004,
+    MemoryAccessMakePointerAvailableMask = 0x00000008,
+    MemoryAccessMakePointerAvailableKHRMask = 0x00000008,
+    MemoryAccessMakePointerVisibleMask = 0x00000010,
+    MemoryAccessMakePointerVisibleKHRMask = 0x00000010,
+    MemoryAccessNonPrivatePointerMask = 0x00000020,
+    MemoryAccessNonPrivatePointerKHRMask = 0x00000020,
 };
 
 enum Scope {
@@ -575,6 +734,8 @@ enum Scope {
     ScopeWorkgroup = 2,
     ScopeSubgroup = 3,
     ScopeInvocation = 4,
+    ScopeQueueFamily = 5,
+    ScopeQueueFamilyKHR = 5,
     ScopeMax = 0x7fffffff,
 };
 
@@ -582,6 +743,10 @@ enum GroupOperation {
     GroupOperationReduce = 0,
     GroupOperationInclusiveScan = 1,
     GroupOperationExclusiveScan = 2,
+    GroupOperationClusteredReduce = 3,
+    GroupOperationPartitionedReduceNV = 6,
+    GroupOperationPartitionedInclusiveScanNV = 7,
+    GroupOperationPartitionedExclusiveScanNV = 8,
     GroupOperationMax = 0x7fffffff,
 };
 
@@ -662,6 +827,16 @@ enum Capability {
   CapabilitySubgroupDispatch = 58,
   CapabilityNamedBarrier = 59,
   CapabilityPipeStorage = 60,
+  CapabilityGroupNonUniform = 61,
+  CapabilityGroupNonUniformVote = 62,
+  CapabilityGroupNonUniformArithmetic = 63,
+  CapabilityGroupNonUniformBallot = 64,
+  CapabilityGroupNonUniformShuffle = 65,
+  CapabilityGroupNonUniformShuffleRelative = 66,
+  CapabilityGroupNonUniformClustered = 67,
+  CapabilityGroupNonUniformQuad = 68,
+  CapabilityShaderLayer = 69,
+  CapabilityShaderViewportIndex = 70,
   CapabilitySubgroupBallotKHR = 4423,
   CapabilityDrawParameters = 4427,
   CapabilitySubgroupVoteKHR = 4431,
@@ -675,16 +850,80 @@ enum Capability {
   CapabilityMultiView = 4439,
   CapabilityVariablePointersStorageBuffer = 4441,
   CapabilityVariablePointers = 4442,
+  CapabilityAtomicStorageOps = 4445,
+  CapabilitySampleMaskPostDepthCoverage = 4447,
+  CapabilityStorageBuffer8BitAccess = 4448,
+  CapabilityUniformAndStorageBuffer8BitAccess = 4449,
+  CapabilityStoragePushConstant8 = 4450,
+  CapabilityDenormPreserve = 4464,
+  CapabilityDenormFlushToZero = 4465,
+  CapabilitySignedZeroInfNanPreserve = 4466,
+  CapabilityRoundingModeRTE = 4467,
+  CapabilityRoundingModeRTZ = 4468,
+  CapabilityFloat16ImageAMD = 5008,
+  CapabilityImageGatherBiasLodAMD = 5009,
+  CapabilityFragmentMaskAMD = 5010,
+  CapabilityStencilExportEXT = 5013,
+  CapabilityImageReadWriteLodAMD = 5015,
+  CapabilityShaderClockKHR = 5055,
   CapabilitySampleMaskOverrideCoverageNV = 5249,
   CapabilityGeometryShaderPassthroughNV = 5251,
+  CapabilityShaderViewportIndexLayerEXT = 5254,
   CapabilityShaderViewportIndexLayerNV = 5254,
   CapabilityShaderViewportMaskNV = 5255,
   CapabilityShaderStereoViewNV = 5259,
   CapabilityPerViewAttributesNV = 5260,
+  CapabilityFragmentFullyCoveredEXT = 5265,
+  CapabilityMeshShadingNV = 5266,
+  CapabilityImageFootprintNV = 5282,
+  CapabilityFragmentBarycentricNV = 5284,
+  CapabilityComputeDerivativeGroupQuadsNV = 5288,
+  CapabilityFragmentDensityEXT = 5291,
+  CapabilityShadingRateNV = 5291,
+  CapabilityGroupNonUniformPartitionedNV = 5297,
+  CapabilityShaderNonUniform = 5301,
+  CapabilityShaderNonUniformEXT = 5301,
+  CapabilityRuntimeDescriptorArray = 5302,
+  CapabilityRuntimeDescriptorArrayEXT = 5302,
+  CapabilityInputAttachmentArrayDynamicIndexing = 5303,
+  CapabilityInputAttachmentArrayDynamicIndexingEXT = 5303,
+  CapabilityUniformTexelBufferArrayDynamicIndexing = 5304,
+  CapabilityUniformTexelBufferArrayDynamicIndexingEXT = 5304,
+  CapabilityStorageTexelBufferArrayDynamicIndexing = 5305,
+  CapabilityStorageTexelBufferArrayDynamicIndexingEXT = 5305,
+  CapabilityUniformBufferArrayNonUniformIndexing = 5306,
+  CapabilityUniformBufferArrayNonUniformIndexingEXT = 5306,
+  CapabilitySampledImageArrayNonUniformIndexing = 5307,
+  CapabilitySampledImageArrayNonUniformIndexingEXT = 5307,
+  CapabilityStorageBufferArrayNonUniformIndexing = 5308,
+  CapabilityStorageBufferArrayNonUniformIndexingEXT = 5308,
+  CapabilityStorageImageArrayNonUniformIndexing = 5309,
+  CapabilityStorageImageArrayNonUniformIndexingEXT = 5309,
+  CapabilityInputAttachmentArrayNonUniformIndexing = 5310,
+  CapabilityInputAttachmentArrayNonUniformIndexingEXT = 5310,
+  CapabilityUniformTexelBufferArrayNonUniformIndexing = 5311,
+  CapabilityUniformTexelBufferArrayNonUniformIndexingEXT = 5311,
+  CapabilityStorageTexelBufferArrayNonUniformIndexing = 5312,
+  CapabilityStorageTexelBufferArrayNonUniformIndexingEXT = 5312,
+  CapabilityRayTracingNV = 5340,
+  CapabilityVulkanMemoryModel = 5345,
+  CapabilityVulkanMemoryModelKHR = 5345,
+  CapabilityVulkanMemoryModelDeviceScope = 5346,
+  CapabilityVulkanMemoryModelDeviceScopeKHR = 5346,
+  CapabilityPhysicalStorageBufferAddresses = 5347,
+  CapabilityPhysicalStorageBufferAddressesEXT = 5347,
+  CapabilityComputeDerivativeGroupLinearNV = 5350,
+  CapabilityCooperativeMatrixNV = 5357,
+  CapabilityFragmentShaderSampleInterlockEXT = 5363,
+  CapabilityFragmentShaderShadingRateInterlockEXT = 5372,
+  CapabilityShaderSMBuiltinsNV = 5373,
+  CapabilityFragmentShaderPixelInterlockEXT = 5378,
+  CapabilityDemoteToHelperInvocationEXT = 5379,
   CapabilitySubgroupShuffleINTEL = 5568,
   CapabilitySubgroupBufferBlockIOINTEL = 5569,
   CapabilitySubgroupImageBlockIOINTEL = 5570,
   CapabilitySubgroupImageMediaBlockIOINTEL = 5579,
+  CapabilityIntegerFunctions2INTEL = 5584,
   CapabilityFunctionPointersINTEL = 5603,
   CapabilityIndirectReferencesINTEL = 5604,
   CapabilityAsmINTEL = 5606,
@@ -1009,6 +1248,46 @@ enum Op {
   OpNamedBarrierInitialize = 328,
   OpMemoryNamedBarrier = 329,
   OpModuleProcessed = 330,
+  OpExecutionModeId = 331,
+  OpDecorateId = 332,
+  OpGroupNonUniformElect = 333,
+  OpGroupNonUniformAll = 334,
+  OpGroupNonUniformAny = 335,
+  OpGroupNonUniformAllEqual = 336,
+  OpGroupNonUniformBroadcast = 337,
+  OpGroupNonUniformBroadcastFirst = 338,
+  OpGroupNonUniformBallot = 339,
+  OpGroupNonUniformInverseBallot = 340,
+  OpGroupNonUniformBallotBitExtract = 341,
+  OpGroupNonUniformBallotBitCount = 342,
+  OpGroupNonUniformBallotFindLSB = 343,
+  OpGroupNonUniformBallotFindMSB = 344,
+  OpGroupNonUniformShuffle = 345,
+  OpGroupNonUniformShuffleXor = 346,
+  OpGroupNonUniformShuffleUp = 347,
+  OpGroupNonUniformShuffleDown = 348,
+  OpGroupNonUniformIAdd = 349,
+  OpGroupNonUniformFAdd = 350,
+  OpGroupNonUniformIMul = 351,
+  OpGroupNonUniformFMul = 352,
+  OpGroupNonUniformSMin = 353,
+  OpGroupNonUniformUMin = 354,
+  OpGroupNonUniformFMin = 355,
+  OpGroupNonUniformSMax = 356,
+  OpGroupNonUniformUMax = 357,
+  OpGroupNonUniformFMax = 358,
+  OpGroupNonUniformBitwiseAnd = 359,
+  OpGroupNonUniformBitwiseOr = 360,
+  OpGroupNonUniformBitwiseXor = 361,
+  OpGroupNonUniformLogicalAnd = 362,
+  OpGroupNonUniformLogicalOr = 363,
+  OpGroupNonUniformLogicalXor = 364,
+  OpGroupNonUniformQuadBroadcast = 365,
+  OpGroupNonUniformQuadSwap = 366,
+  OpCopyLogical = 400,
+  OpPtrEqual = 401,
+  OpPtrNotEqual = 402,
+  OpPtrDiff = 403,
   OpForward = 1024, /* internal use only */
   OpSubgroupBallotKHR = 4421,
   OpSubgroupFirstInvocationKHR = 4422,
@@ -1016,6 +1295,35 @@ enum Op {
   OpSubgroupAnyKHR = 4429,
   OpSubgroupAllEqualKHR = 4430,
   OpSubgroupReadInvocationKHR = 4432,
+  OpGroupIAddNonUniformAMD = 5000,
+  OpGroupFAddNonUniformAMD = 5001,
+  OpGroupFMinNonUniformAMD = 5002,
+  OpGroupUMinNonUniformAMD = 5003,
+  OpGroupSMinNonUniformAMD = 5004,
+  OpGroupFMaxNonUniformAMD = 5005,
+  OpGroupUMaxNonUniformAMD = 5006,
+  OpGroupSMaxNonUniformAMD = 5007,
+  OpFragmentMaskFetchAMD = 5011,
+  OpFragmentFetchAMD = 5012,
+  OpReadClockKHR = 5056,
+  OpImageSampleFootprintNV = 5283,
+  OpGroupNonUniformPartitionNV = 5296,
+  OpWritePackedPrimitiveIndices4x8NV = 5299,
+  OpReportIntersectionNV = 5334,
+  OpIgnoreIntersectionNV = 5335,
+  OpTerminateRayNV = 5336,
+  OpTraceNV = 5337,
+  OpTypeAccelerationStructureNV = 5341,
+  OpExecuteCallableNV = 5344,
+  OpTypeCooperativeMatrixNV = 5358,
+  OpCooperativeMatrixLoadNV = 5359,
+  OpCooperativeMatrixStoreNV = 5360,
+  OpCooperativeMatrixMulAddNV = 5361,
+  OpCooperativeMatrixLengthNV = 5362,
+  OpBeginInvocationInterlockEXT = 5364,
+  OpEndInvocationInterlockEXT = 5365,
+  OpDemoteToHelperInvocationEXT = 5380,
+  OpIsHelperInvocationEXT = 5381,
   OpSubgroupShuffleINTEL = 5571,
   OpSubgroupShuffleDownINTEL = 5572,
   OpSubgroupShuffleUpINTEL = 5573,
@@ -1026,6 +1334,20 @@ enum Op {
   OpSubgroupImageBlockWriteINTEL = 5578,
   OpSubgroupImageMediaBlockReadINTEL = 5580,
   OpSubgroupImageMediaBlockWriteINTEL = 5581,
+  OpUCountLeadingZerosINTEL = 5585,
+  OpUCountTrailingZerosINTEL = 5586,
+  OpAbsISubINTEL = 5587,
+  OpAbsUSubINTEL = 5588,
+  OpIAddSatINTEL = 5589,
+  OpUAddSatINTEL = 5590,
+  OpIAverageINTEL = 5591,
+  OpUAverageINTEL = 5592,
+  OpIAverageRoundedINTEL = 5593,
+  OpUAverageRoundedINTEL = 5594,
+  OpISubSatINTEL = 5595,
+  OpUSubSatINTEL = 5596,
+  OpIMul32x16INTEL = 5597,
+  OpUMul32x16INTEL = 5598,
   OpFunctionPointerINTEL = 5600,
   OpFunctionPointerCallINTEL = 5601,
   OpAsmTargetINTEL = 5609,
@@ -1033,6 +1355,10 @@ enum Op {
   OpAsmCallINTEL = 5611,
   OpAssumeTrueINTEL = 5630,
   OpExpectINTEL = 5631,
+  OpDecorateString = 5632,
+  OpDecorateStringGOOGLE = 5632,
+  OpMemberDecorateString = 5633,
+  OpMemberDecorateStringGOOGLE = 5633,
   OpVmeImageINTEL = 5699,
   OpTypeVmeImageINTEL = 5700,
   OpTypeAvcImePayloadINTEL = 5701,
@@ -1159,6 +1485,538 @@ enum Op {
   OpMax = 0x7fffffff,
 };
 
+#ifdef SPV_ENABLE_UTILITY_CODE
+inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
+    *hasResult = *hasResultType = false;
+    switch (opcode) {
+    default: /* unknown opcode */ break;
+    case OpNop: *hasResult = false; *hasResultType = false; break;
+    case OpUndef: *hasResult = true; *hasResultType = true; break;
+    case OpSourceContinued: *hasResult = false; *hasResultType = false; break;
+    case OpSource: *hasResult = false; *hasResultType = false; break;
+    case OpSourceExtension: *hasResult = false; *hasResultType = false; break;
+    case OpName: *hasResult = false; *hasResultType = false; break;
+    case OpMemberName: *hasResult = false; *hasResultType = false; break;
+    case OpString: *hasResult = true; *hasResultType = false; break;
+    case OpLine: *hasResult = false; *hasResultType = false; break;
+    case OpExtension: *hasResult = false; *hasResultType = false; break;
+    case OpExtInstImport: *hasResult = true; *hasResultType = false; break;
+    case OpExtInst: *hasResult = true; *hasResultType = true; break;
+    case OpMemoryModel: *hasResult = false; *hasResultType = false; break;
+    case OpEntryPoint: *hasResult = false; *hasResultType = false; break;
+    case OpExecutionMode: *hasResult = false; *hasResultType = false; break;
+    case OpCapability: *hasResult = false; *hasResultType = false; break;
+    case OpTypeVoid: *hasResult = true; *hasResultType = false; break;
+    case OpTypeBool: *hasResult = true; *hasResultType = false; break;
+    case OpTypeInt: *hasResult = true; *hasResultType = false; break;
+    case OpTypeFloat: *hasResult = true; *hasResultType = false; break;
+    case OpTypeVector: *hasResult = true; *hasResultType = false; break;
+    case OpTypeMatrix: *hasResult = true; *hasResultType = false; break;
+    case OpTypeImage: *hasResult = true; *hasResultType = false; break;
+    case OpTypeSampler: *hasResult = true; *hasResultType = false; break;
+    case OpTypeSampledImage: *hasResult = true; *hasResultType = false; break;
+    case OpTypeArray: *hasResult = true; *hasResultType = false; break;
+    case OpTypeRuntimeArray: *hasResult = true; *hasResultType = false; break;
+    case OpTypeStruct: *hasResult = true; *hasResultType = false; break;
+    case OpTypeOpaque: *hasResult = true; *hasResultType = false; break;
+    case OpTypePointer: *hasResult = true; *hasResultType = false; break;
+    case OpTypeFunction: *hasResult = true; *hasResultType = false; break;
+    case OpTypeEvent: *hasResult = true; *hasResultType = false; break;
+    case OpTypeDeviceEvent: *hasResult = true; *hasResultType = false; break;
+    case OpTypeReserveId: *hasResult = true; *hasResultType = false; break;
+    case OpTypeQueue: *hasResult = true; *hasResultType = false; break;
+    case OpTypePipe: *hasResult = true; *hasResultType = false; break;
+    case OpTypeForwardPointer: *hasResult = false; *hasResultType = false; break;
+    case OpConstantTrue: *hasResult = true; *hasResultType = true; break;
+    case OpConstantFalse: *hasResult = true; *hasResultType = true; break;
+    case OpConstant: *hasResult = true; *hasResultType = true; break;
+    case OpConstantComposite: *hasResult = true; *hasResultType = true; break;
+    case OpConstantSampler: *hasResult = true; *hasResultType = true; break;
+    case OpConstantNull: *hasResult = true; *hasResultType = true; break;
+    case OpSpecConstantTrue: *hasResult = true; *hasResultType = true; break;
+    case OpSpecConstantFalse: *hasResult = true; *hasResultType = true; break;
+    case OpSpecConstant: *hasResult = true; *hasResultType = true; break;
+    case OpSpecConstantComposite: *hasResult = true; *hasResultType = true; break;
+    case OpSpecConstantOp: *hasResult = true; *hasResultType = true; break;
+    case OpFunction: *hasResult = true; *hasResultType = true; break;
+    case OpFunctionParameter: *hasResult = true; *hasResultType = true; break;
+    case OpFunctionEnd: *hasResult = false; *hasResultType = false; break;
+    case OpFunctionCall: *hasResult = true; *hasResultType = true; break;
+    case OpVariable: *hasResult = true; *hasResultType = true; break;
+    case OpImageTexelPointer: *hasResult = true; *hasResultType = true; break;
+    case OpLoad: *hasResult = true; *hasResultType = true; break;
+    case OpStore: *hasResult = false; *hasResultType = false; break;
+    case OpCopyMemory: *hasResult = false; *hasResultType = false; break;
+    case OpCopyMemorySized: *hasResult = false; *hasResultType = false; break;
+    case OpAccessChain: *hasResult = true; *hasResultType = true; break;
+    case OpInBoundsAccessChain: *hasResult = true; *hasResultType = true; break;
+    case OpPtrAccessChain: *hasResult = true; *hasResultType = true; break;
+    case OpArrayLength: *hasResult = true; *hasResultType = true; break;
+    case OpGenericPtrMemSemantics: *hasResult = true; *hasResultType = true; break;
+    case OpInBoundsPtrAccessChain: *hasResult = true; *hasResultType = true; break;
+    case OpDecorate: *hasResult = false; *hasResultType = false; break;
+    case OpMemberDecorate: *hasResult = false; *hasResultType = false; break;
+    case OpDecorationGroup: *hasResult = true; *hasResultType = false; break;
+    case OpGroupDecorate: *hasResult = false; *hasResultType = false; break;
+    case OpGroupMemberDecorate: *hasResult = false; *hasResultType = false; break;
+    case OpVectorExtractDynamic: *hasResult = true; *hasResultType = true; break;
+    case OpVectorInsertDynamic: *hasResult = true; *hasResultType = true; break;
+    case OpVectorShuffle: *hasResult = true; *hasResultType = true; break;
+    case OpCompositeConstruct: *hasResult = true; *hasResultType = true; break;
+    case OpCompositeExtract: *hasResult = true; *hasResultType = true; break;
+    case OpCompositeInsert: *hasResult = true; *hasResultType = true; break;
+    case OpCopyObject: *hasResult = true; *hasResultType = true; break;
+    case OpTranspose: *hasResult = true; *hasResultType = true; break;
+    case OpSampledImage: *hasResult = true; *hasResultType = true; break;
+    case OpImageSampleImplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSampleExplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSampleDrefImplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSampleDrefExplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSampleProjImplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSampleProjExplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSampleProjDrefImplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSampleProjDrefExplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageFetch: *hasResult = true; *hasResultType = true; break;
+    case OpImageGather: *hasResult = true; *hasResultType = true; break;
+    case OpImageDrefGather: *hasResult = true; *hasResultType = true; break;
+    case OpImageRead: *hasResult = true; *hasResultType = true; break;
+    case OpImageWrite: *hasResult = false; *hasResultType = false; break;
+    case OpImage: *hasResult = true; *hasResultType = true; break;
+    case OpImageQueryFormat: *hasResult = true; *hasResultType = true; break;
+    case OpImageQueryOrder: *hasResult = true; *hasResultType = true; break;
+    case OpImageQuerySizeLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageQuerySize: *hasResult = true; *hasResultType = true; break;
+    case OpImageQueryLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageQueryLevels: *hasResult = true; *hasResultType = true; break;
+    case OpImageQuerySamples: *hasResult = true; *hasResultType = true; break;
+    case OpConvertFToU: *hasResult = true; *hasResultType = true; break;
+    case OpConvertFToS: *hasResult = true; *hasResultType = true; break;
+    case OpConvertSToF: *hasResult = true; *hasResultType = true; break;
+    case OpConvertUToF: *hasResult = true; *hasResultType = true; break;
+    case OpUConvert: *hasResult = true; *hasResultType = true; break;
+    case OpSConvert: *hasResult = true; *hasResultType = true; break;
+    case OpFConvert: *hasResult = true; *hasResultType = true; break;
+    case OpQuantizeToF16: *hasResult = true; *hasResultType = true; break;
+    case OpConvertPtrToU: *hasResult = true; *hasResultType = true; break;
+    case OpSatConvertSToU: *hasResult = true; *hasResultType = true; break;
+    case OpSatConvertUToS: *hasResult = true; *hasResultType = true; break;
+    case OpConvertUToPtr: *hasResult = true; *hasResultType = true; break;
+    case OpPtrCastToGeneric: *hasResult = true; *hasResultType = true; break;
+    case OpGenericCastToPtr: *hasResult = true; *hasResultType = true; break;
+    case OpGenericCastToPtrExplicit: *hasResult = true; *hasResultType = true; break;
+    case OpBitcast: *hasResult = true; *hasResultType = true; break;
+    case OpSNegate: *hasResult = true; *hasResultType = true; break;
+    case OpFNegate: *hasResult = true; *hasResultType = true; break;
+    case OpIAdd: *hasResult = true; *hasResultType = true; break;
+    case OpFAdd: *hasResult = true; *hasResultType = true; break;
+    case OpISub: *hasResult = true; *hasResultType = true; break;
+    case OpFSub: *hasResult = true; *hasResultType = true; break;
+    case OpIMul: *hasResult = true; *hasResultType = true; break;
+    case OpFMul: *hasResult = true; *hasResultType = true; break;
+    case OpUDiv: *hasResult = true; *hasResultType = true; break;
+    case OpSDiv: *hasResult = true; *hasResultType = true; break;
+    case OpFDiv: *hasResult = true; *hasResultType = true; break;
+    case OpUMod: *hasResult = true; *hasResultType = true; break;
+    case OpSRem: *hasResult = true; *hasResultType = true; break;
+    case OpSMod: *hasResult = true; *hasResultType = true; break;
+    case OpFRem: *hasResult = true; *hasResultType = true; break;
+    case OpFMod: *hasResult = true; *hasResultType = true; break;
+    case OpVectorTimesScalar: *hasResult = true; *hasResultType = true; break;
+    case OpMatrixTimesScalar: *hasResult = true; *hasResultType = true; break;
+    case OpVectorTimesMatrix: *hasResult = true; *hasResultType = true; break;
+    case OpMatrixTimesVector: *hasResult = true; *hasResultType = true; break;
+    case OpMatrixTimesMatrix: *hasResult = true; *hasResultType = true; break;
+    case OpOuterProduct: *hasResult = true; *hasResultType = true; break;
+    case OpDot: *hasResult = true; *hasResultType = true; break;
+    case OpIAddCarry: *hasResult = true; *hasResultType = true; break;
+    case OpISubBorrow: *hasResult = true; *hasResultType = true; break;
+    case OpUMulExtended: *hasResult = true; *hasResultType = true; break;
+    case OpSMulExtended: *hasResult = true; *hasResultType = true; break;
+    case OpAny: *hasResult = true; *hasResultType = true; break;
+    case OpAll: *hasResult = true; *hasResultType = true; break;
+    case OpIsNan: *hasResult = true; *hasResultType = true; break;
+    case OpIsInf: *hasResult = true; *hasResultType = true; break;
+    case OpIsFinite: *hasResult = true; *hasResultType = true; break;
+    case OpIsNormal: *hasResult = true; *hasResultType = true; break;
+    case OpSignBitSet: *hasResult = true; *hasResultType = true; break;
+    case OpLessOrGreater: *hasResult = true; *hasResultType = true; break;
+    case OpOrdered: *hasResult = true; *hasResultType = true; break;
+    case OpUnordered: *hasResult = true; *hasResultType = true; break;
+    case OpLogicalEqual: *hasResult = true; *hasResultType = true; break;
+    case OpLogicalNotEqual: *hasResult = true; *hasResultType = true; break;
+    case OpLogicalOr: *hasResult = true; *hasResultType = true; break;
+    case OpLogicalAnd: *hasResult = true; *hasResultType = true; break;
+    case OpLogicalNot: *hasResult = true; *hasResultType = true; break;
+    case OpSelect: *hasResult = true; *hasResultType = true; break;
+    case OpIEqual: *hasResult = true; *hasResultType = true; break;
+    case OpINotEqual: *hasResult = true; *hasResultType = true; break;
+    case OpUGreaterThan: *hasResult = true; *hasResultType = true; break;
+    case OpSGreaterThan: *hasResult = true; *hasResultType = true; break;
+    case OpUGreaterThanEqual: *hasResult = true; *hasResultType = true; break;
+    case OpSGreaterThanEqual: *hasResult = true; *hasResultType = true; break;
+    case OpULessThan: *hasResult = true; *hasResultType = true; break;
+    case OpSLessThan: *hasResult = true; *hasResultType = true; break;
+    case OpULessThanEqual: *hasResult = true; *hasResultType = true; break;
+    case OpSLessThanEqual: *hasResult = true; *hasResultType = true; break;
+    case OpFOrdEqual: *hasResult = true; *hasResultType = true; break;
+    case OpFUnordEqual: *hasResult = true; *hasResultType = true; break;
+    case OpFOrdNotEqual: *hasResult = true; *hasResultType = true; break;
+    case OpFUnordNotEqual: *hasResult = true; *hasResultType = true; break;
+    case OpFOrdLessThan: *hasResult = true; *hasResultType = true; break;
+    case OpFUnordLessThan: *hasResult = true; *hasResultType = true; break;
+    case OpFOrdGreaterThan: *hasResult = true; *hasResultType = true; break;
+    case OpFUnordGreaterThan: *hasResult = true; *hasResultType = true; break;
+    case OpFOrdLessThanEqual: *hasResult = true; *hasResultType = true; break;
+    case OpFUnordLessThanEqual: *hasResult = true; *hasResultType = true; break;
+    case OpFOrdGreaterThanEqual: *hasResult = true; *hasResultType = true; break;
+    case OpFUnordGreaterThanEqual: *hasResult = true; *hasResultType = true; break;
+    case OpShiftRightLogical: *hasResult = true; *hasResultType = true; break;
+    case OpShiftRightArithmetic: *hasResult = true; *hasResultType = true; break;
+    case OpShiftLeftLogical: *hasResult = true; *hasResultType = true; break;
+    case OpBitwiseOr: *hasResult = true; *hasResultType = true; break;
+    case OpBitwiseXor: *hasResult = true; *hasResultType = true; break;
+    case OpBitwiseAnd: *hasResult = true; *hasResultType = true; break;
+    case OpNot: *hasResult = true; *hasResultType = true; break;
+    case OpBitFieldInsert: *hasResult = true; *hasResultType = true; break;
+    case OpBitFieldSExtract: *hasResult = true; *hasResultType = true; break;
+    case OpBitFieldUExtract: *hasResult = true; *hasResultType = true; break;
+    case OpBitReverse: *hasResult = true; *hasResultType = true; break;
+    case OpBitCount: *hasResult = true; *hasResultType = true; break;
+    case OpDPdx: *hasResult = true; *hasResultType = true; break;
+    case OpDPdy: *hasResult = true; *hasResultType = true; break;
+    case OpFwidth: *hasResult = true; *hasResultType = true; break;
+    case OpDPdxFine: *hasResult = true; *hasResultType = true; break;
+    case OpDPdyFine: *hasResult = true; *hasResultType = true; break;
+    case OpFwidthFine: *hasResult = true; *hasResultType = true; break;
+    case OpDPdxCoarse: *hasResult = true; *hasResultType = true; break;
+    case OpDPdyCoarse: *hasResult = true; *hasResultType = true; break;
+    case OpFwidthCoarse: *hasResult = true; *hasResultType = true; break;
+    case OpEmitVertex: *hasResult = false; *hasResultType = false; break;
+    case OpEndPrimitive: *hasResult = false; *hasResultType = false; break;
+    case OpEmitStreamVertex: *hasResult = false; *hasResultType = false; break;
+    case OpEndStreamPrimitive: *hasResult = false; *hasResultType = false; break;
+    case OpControlBarrier: *hasResult = false; *hasResultType = false; break;
+    case OpMemoryBarrier: *hasResult = false; *hasResultType = false; break;
+    case OpAtomicLoad: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicStore: *hasResult = false; *hasResultType = false; break;
+    case OpAtomicExchange: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicCompareExchange: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicCompareExchangeWeak: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicIIncrement: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicIDecrement: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicIAdd: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicISub: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicSMin: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicUMin: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicSMax: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicUMax: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicAnd: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicOr: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicXor: *hasResult = true; *hasResultType = true; break;
+    case OpPhi: *hasResult = true; *hasResultType = true; break;
+    case OpLoopMerge: *hasResult = false; *hasResultType = false; break;
+    case OpSelectionMerge: *hasResult = false; *hasResultType = false; break;
+    case OpLabel: *hasResult = true; *hasResultType = false; break;
+    case OpBranch: *hasResult = false; *hasResultType = false; break;
+    case OpBranchConditional: *hasResult = false; *hasResultType = false; break;
+    case OpSwitch: *hasResult = false; *hasResultType = false; break;
+    case OpKill: *hasResult = false; *hasResultType = false; break;
+    case OpReturn: *hasResult = false; *hasResultType = false; break;
+    case OpReturnValue: *hasResult = false; *hasResultType = false; break;
+    case OpUnreachable: *hasResult = false; *hasResultType = false; break;
+    case OpLifetimeStart: *hasResult = false; *hasResultType = false; break;
+    case OpLifetimeStop: *hasResult = false; *hasResultType = false; break;
+    case OpGroupAsyncCopy: *hasResult = true; *hasResultType = true; break;
+    case OpGroupWaitEvents: *hasResult = false; *hasResultType = false; break;
+    case OpGroupAll: *hasResult = true; *hasResultType = true; break;
+    case OpGroupAny: *hasResult = true; *hasResultType = true; break;
+    case OpGroupBroadcast: *hasResult = true; *hasResultType = true; break;
+    case OpGroupIAdd: *hasResult = true; *hasResultType = true; break;
+    case OpGroupFAdd: *hasResult = true; *hasResultType = true; break;
+    case OpGroupFMin: *hasResult = true; *hasResultType = true; break;
+    case OpGroupUMin: *hasResult = true; *hasResultType = true; break;
+    case OpGroupSMin: *hasResult = true; *hasResultType = true; break;
+    case OpGroupFMax: *hasResult = true; *hasResultType = true; break;
+    case OpGroupUMax: *hasResult = true; *hasResultType = true; break;
+    case OpGroupSMax: *hasResult = true; *hasResultType = true; break;
+    case OpReadPipe: *hasResult = true; *hasResultType = true; break;
+    case OpWritePipe: *hasResult = true; *hasResultType = true; break;
+    case OpReservedReadPipe: *hasResult = true; *hasResultType = true; break;
+    case OpReservedWritePipe: *hasResult = true; *hasResultType = true; break;
+    case OpReserveReadPipePackets: *hasResult = true; *hasResultType = true; break;
+    case OpReserveWritePipePackets: *hasResult = true; *hasResultType = true; break;
+    case OpCommitReadPipe: *hasResult = false; *hasResultType = false; break;
+    case OpCommitWritePipe: *hasResult = false; *hasResultType = false; break;
+    case OpIsValidReserveId: *hasResult = true; *hasResultType = true; break;
+    case OpGetNumPipePackets: *hasResult = true; *hasResultType = true; break;
+    case OpGetMaxPipePackets: *hasResult = true; *hasResultType = true; break;
+    case OpGroupReserveReadPipePackets: *hasResult = true; *hasResultType = true; break;
+    case OpGroupReserveWritePipePackets: *hasResult = true; *hasResultType = true; break;
+    case OpGroupCommitReadPipe: *hasResult = false; *hasResultType = false; break;
+    case OpGroupCommitWritePipe: *hasResult = false; *hasResultType = false; break;
+    case OpEnqueueMarker: *hasResult = true; *hasResultType = true; break;
+    case OpEnqueueKernel: *hasResult = true; *hasResultType = true; break;
+    case OpGetKernelNDrangeSubGroupCount: *hasResult = true; *hasResultType = true; break;
+    case OpGetKernelNDrangeMaxSubGroupSize: *hasResult = true; *hasResultType = true; break;
+    case OpGetKernelWorkGroupSize: *hasResult = true; *hasResultType = true; break;
+    case OpGetKernelPreferredWorkGroupSizeMultiple: *hasResult = true; *hasResultType = true; break;
+    case OpRetainEvent: *hasResult = false; *hasResultType = false; break;
+    case OpReleaseEvent: *hasResult = false; *hasResultType = false; break;
+    case OpCreateUserEvent: *hasResult = true; *hasResultType = true; break;
+    case OpIsValidEvent: *hasResult = true; *hasResultType = true; break;
+    case OpSetUserEventStatus: *hasResult = false; *hasResultType = false; break;
+    case OpCaptureEventProfilingInfo: *hasResult = false; *hasResultType = false; break;
+    case OpGetDefaultQueue: *hasResult = true; *hasResultType = true; break;
+    case OpBuildNDRange: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseSampleImplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseSampleExplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseSampleDrefImplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseSampleDrefExplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseSampleProjImplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseSampleProjExplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseSampleProjDrefImplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseSampleProjDrefExplicitLod: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseFetch: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseGather: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseDrefGather: *hasResult = true; *hasResultType = true; break;
+    case OpImageSparseTexelsResident: *hasResult = true; *hasResultType = true; break;
+    case OpNoLine: *hasResult = false; *hasResultType = false; break;
+    case OpAtomicFlagTestAndSet: *hasResult = true; *hasResultType = true; break;
+    case OpAtomicFlagClear: *hasResult = false; *hasResultType = false; break;
+    case OpImageSparseRead: *hasResult = true; *hasResultType = true; break;
+    case OpSizeOf: *hasResult = true; *hasResultType = true; break;
+    case OpTypePipeStorage: *hasResult = true; *hasResultType = false; break;
+    case OpConstantPipeStorage: *hasResult = true; *hasResultType = true; break;
+    case OpCreatePipeFromPipeStorage: *hasResult = true; *hasResultType = true; break;
+    case OpGetKernelLocalSizeForSubgroupCount: *hasResult = true; *hasResultType = true; break;
+    case OpGetKernelMaxNumSubgroups: *hasResult = true; *hasResultType = true; break;
+    case OpTypeNamedBarrier: *hasResult = true; *hasResultType = false; break;
+    case OpNamedBarrierInitialize: *hasResult = true; *hasResultType = true; break;
+    case OpMemoryNamedBarrier: *hasResult = false; *hasResultType = false; break;
+    case OpModuleProcessed: *hasResult = false; *hasResultType = false; break;
+    case OpExecutionModeId: *hasResult = false; *hasResultType = false; break;
+    case OpDecorateId: *hasResult = false; *hasResultType = false; break;
+    case OpGroupNonUniformElect: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformAll: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformAny: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformAllEqual: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBroadcast: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBroadcastFirst: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBallot: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformInverseBallot: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBallotBitExtract: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBallotBitCount: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBallotFindLSB: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBallotFindMSB: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformShuffle: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformShuffleXor: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformShuffleUp: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformShuffleDown: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformIAdd: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformFAdd: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformIMul: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformFMul: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformSMin: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformUMin: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformFMin: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformSMax: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformUMax: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformFMax: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBitwiseAnd: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBitwiseOr: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformBitwiseXor: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformLogicalAnd: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformLogicalOr: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformLogicalXor: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformQuadBroadcast: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformQuadSwap: *hasResult = true; *hasResultType = true; break;
+    case OpCopyLogical: *hasResult = true; *hasResultType = true; break;
+    case OpPtrEqual: *hasResult = true; *hasResultType = true; break;
+    case OpPtrNotEqual: *hasResult = true; *hasResultType = true; break;
+    case OpPtrDiff: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupBallotKHR: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupFirstInvocationKHR: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAllKHR: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAnyKHR: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAllEqualKHR: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupReadInvocationKHR: *hasResult = true; *hasResultType = true; break;
+    case OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
+    case OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
+    case OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break;
+    case OpGroupUMinNonUniformAMD: *hasResult = true; *hasResultType = true; break;
+    case OpGroupSMinNonUniformAMD: *hasResult = true; *hasResultType = true; break;
+    case OpGroupFMaxNonUniformAMD: *hasResult = true; *hasResultType = true; break;
+    case OpGroupUMaxNonUniformAMD: *hasResult = true; *hasResultType = true; break;
+    case OpGroupSMaxNonUniformAMD: *hasResult = true; *hasResultType = true; break;
+    case OpFragmentMaskFetchAMD: *hasResult = true; *hasResultType = true; break;
+    case OpFragmentFetchAMD: *hasResult = true; *hasResultType = true; break;
+    case OpReadClockKHR: *hasResult = true; *hasResultType = true; break;
+    case OpImageSampleFootprintNV: *hasResult = true; *hasResultType = true; break;
+    case OpGroupNonUniformPartitionNV: *hasResult = true; *hasResultType = true; break;
+    case OpWritePackedPrimitiveIndices4x8NV: *hasResult = false; *hasResultType = false; break;
+    case OpReportIntersectionNV: *hasResult = true; *hasResultType = true; break;
+    case OpIgnoreIntersectionNV: *hasResult = false; *hasResultType = false; break;
+    case OpTerminateRayNV: *hasResult = false; *hasResultType = false; break;
+    case OpTraceNV: *hasResult = false; *hasResultType = false; break;
+    case OpTypeAccelerationStructureNV: *hasResult = true; *hasResultType = false; break;
+    case OpExecuteCallableNV: *hasResult = false; *hasResultType = false; break;
+    case OpTypeCooperativeMatrixNV: *hasResult = true; *hasResultType = false; break;
+    case OpCooperativeMatrixLoadNV: *hasResult = true; *hasResultType = true; break;
+    case OpCooperativeMatrixStoreNV: *hasResult = false; *hasResultType = false; break;
+    case OpCooperativeMatrixMulAddNV: *hasResult = true; *hasResultType = true; break;
+    case OpCooperativeMatrixLengthNV: *hasResult = true; *hasResultType = true; break;
+    case OpBeginInvocationInterlockEXT: *hasResult = false; *hasResultType = false; break;
+    case OpEndInvocationInterlockEXT: *hasResult = false; *hasResultType = false; break;
+    case OpDemoteToHelperInvocationEXT: *hasResult = false; *hasResultType = false; break;
+    case OpIsHelperInvocationEXT: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupShuffleINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupShuffleDownINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupShuffleUpINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupShuffleXorINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupBlockReadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupBlockWriteINTEL: *hasResult = false; *hasResultType = false; break;
+    case OpSubgroupImageBlockReadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupImageBlockWriteINTEL: *hasResult = false; *hasResultType = false; break;
+    case OpSubgroupImageMediaBlockReadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupImageMediaBlockWriteINTEL: *hasResult = false; *hasResultType = false; break;
+    case OpUCountLeadingZerosINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpUCountTrailingZerosINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpAbsISubINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpAbsUSubINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpIAddSatINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpUAddSatINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpIAverageINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpUAverageINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpIAverageRoundedINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpUAverageRoundedINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpISubSatINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpUSubSatINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpIMul32x16INTEL: *hasResult = true; *hasResultType = true; break;
+    case OpUMul32x16INTEL: *hasResult = true; *hasResultType = true; break;
+    case OpDecorateString: *hasResult = false; *hasResultType = false; break;
+    case OpMemberDecorateString: *hasResult = false; *hasResultType = false; break;
+    case OpVmeImageINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpTypeVmeImageINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcImePayloadINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcRefPayloadINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcSicPayloadINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcMcePayloadINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcMceResultINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcImeResultINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcImeResultSingleReferenceStreamoutINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcImeResultDualReferenceStreamoutINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcImeSingleReferenceStreaminINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcImeDualReferenceStreaminINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcRefResultINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpTypeAvcSicResultINTEL: *hasResult = true; *hasResultType = false; break;
+    case OpSubgroupAvcMceGetDefaultInterBaseMultiReferencePenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultInterShapePenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceSetInterShapePenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultInterDirectionPenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceSetInterDirectionPenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultIntraLumaShapePenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultInterMotionVectorCostTableINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultHighPenaltyCostTableINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultMediumPenaltyCostTableINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultLowPenaltyCostTableINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultIntraLumaModePenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultNonDcLumaIntraPenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetDefaultIntraChromaModeBasePenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceSetAcOnlyHaarINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceSetSourceInterlacedFieldPolarityINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceSetSingleReferenceInterlacedFieldPolarityINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceSetDualReferenceInterlacedFieldPolaritiesINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceConvertToImePayloadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceConvertToImeResultINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceConvertToRefPayloadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceConvertToRefResultINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceConvertToSicPayloadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceConvertToSicResultINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetMotionVectorsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetInterDistortionsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetBestInterDistortionsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetInterMajorShapeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetInterMinorShapeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetInterDirectionsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetInterMotionVectorCountINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetInterReferenceIdsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcMceGetInterReferenceInterlacedFieldPolaritiesINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeInitializeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeSetSingleReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeSetDualReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeRefWindowSizeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeAdjustRefOffsetINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeConvertToMcePayloadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeSetMaxMotionVectorCountINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeSetUnidirectionalMixDisableINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeSetEarlySearchTerminationThresholdINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeSetWeightedSadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeEvaluateWithSingleReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeEvaluateWithDualReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeEvaluateWithDualReferenceStreaminINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeEvaluateWithSingleReferenceStreamoutINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeEvaluateWithDualReferenceStreamoutINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminoutINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeEvaluateWithDualReferenceStreaminoutINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeConvertToMceResultINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetSingleReferenceStreaminINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetDualReferenceStreaminINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeStripSingleReferenceStreamoutINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeStripDualReferenceStreamoutINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeMotionVectorsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeDistortionsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeReferenceIdsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeMotionVectorsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeDistortionsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeReferenceIdsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetBorderReachedINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetTruncatedSearchIndicationINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetUnidirectionalEarlySearchTerminationINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetWeightingPatternMinimumMotionVectorINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcImeGetWeightingPatternMinimumDistortionINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcFmeInitializeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcBmeInitializeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcRefConvertToMcePayloadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcRefSetBidirectionalMixDisableINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcRefSetBilinearFilterEnableINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcRefEvaluateWithSingleReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcRefEvaluateWithDualReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcRefEvaluateWithMultiReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcRefEvaluateWithMultiReferenceInterlacedINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcRefConvertToMceResultINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicInitializeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicConfigureSkcINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicConfigureIpeLumaINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicConfigureIpeLumaChromaINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicGetMotionVectorMaskINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicConvertToMcePayloadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicSetIntraLumaShapePenaltyINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicSetIntraChromaModeCostFunctionINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicSetBilinearFilterEnableINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicSetSkcForwardTransformEnableINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicSetBlockBasedRawSkipSadINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicEvaluateIpeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicEvaluateWithSingleReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicEvaluateWithDualReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicEvaluateWithMultiReferenceINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicEvaluateWithMultiReferenceInterlacedINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicConvertToMceResultINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicGetIpeLumaShapeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicGetBestIpeLumaDistortionINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicGetBestIpeChromaDistortionINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicGetPackedIpeLumaModesINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicGetIpeChromaModeINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpSubgroupAvcSicGetInterRawSadsINTEL: *hasResult = true; *hasResultType = true; break;
+    }
+}
+#endif /* SPV_ENABLE_UTILITY_CODE */
+
 // Overload operator| for mask bit combining
 
 inline ImageOperandsMask operator|(ImageOperandsMask a, ImageOperandsMask b) { return ImageOperandsMask(unsigned(a) | unsigned(b)); }
diff --git a/llvm-spirv/test/DebugInfo/Generic/undef-func-call.ll b/llvm-spirv/test/DebugInfo/Generic/undef-func-call.ll
new file mode 100644
index 000000000000..315a01d3bbcf
--- /dev/null
+++ b/llvm-spirv/test/DebugInfo/Generic/undef-func-call.ll
@@ -0,0 +1,100 @@
+; RUN: llvm-as < %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv -r %t.spv
+
+; This is a regression test for reported issue https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/524.
+; Test checks that reverse translation will not fail with assertion.
+
+; Build from the following source with clang -c -emit-llvm -O0 -target spir64 -gline-tables-only
+; float bar(int x);
+
+; __kernel void foo(__global float* outPtr, int i) {
+; #pragma clang loop unroll(enable)
+;   for (int j = 0; j < i; ++j) {
+;     outPtr[j] = bar(j);
+;   }
+; }
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+; Function Attrs: convergent noinline norecurse nounwind optnone
+define dso_local spir_kernel void @foo(float addrspace(1)* %outPtr, i32 %i) #0 !dbg !9 !kernel_arg_addr_space !6 !kernel_arg_access_qual !11 !kernel_arg_type !12 !kernel_arg_base_type !12 !kernel_arg_type_qual !13 {
+entry:
+  %outPtr.addr = alloca float addrspace(1)*, align 8
+  %i.addr = alloca i32, align 4
+  %j = alloca i32, align 4
+  store float addrspace(1)* %outPtr, float addrspace(1)** %outPtr.addr, align 8
+  store i32 %i, i32* %i.addr, align 4
+  store i32 0, i32* %j, align 4, !dbg !14
+  br label %for.cond, !dbg !15
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %0 = load i32, i32* %j, align 4, !dbg !16
+  %1 = load i32, i32* %i.addr, align 4, !dbg !17
+  %cmp = icmp slt i32 %0, %1, !dbg !18
+  br i1 %cmp, label %for.body, label %for.end, !dbg !19
+
+for.body:                                         ; preds = %for.cond
+  %2 = load i32, i32* %j, align 4, !dbg !20
+  %call = call spir_func float @bar(i32 %2) #2, !dbg !21
+  %3 = load float addrspace(1)*, float addrspace(1)** %outPtr.addr, align 8, !dbg !22
+  %4 = load i32, i32* %j, align 4, !dbg !23
+  %idxprom = sext i32 %4 to i64, !dbg !22
+  %arrayidx = getelementptr inbounds float, float addrspace(1)* %3, i64 %idxprom, !dbg !22
+  store float %call, float addrspace(1)* %arrayidx, align 4, !dbg !24
+  br label %for.inc, !dbg !25
+
+for.inc:                                          ; preds = %for.body
+  %5 = load i32, i32* %j, align 4, !dbg !26
+  %inc = add nsw i32 %5, 1, !dbg !26
+  store i32 %inc, i32* %j, align 4, !dbg !26
+  br label %for.cond, !dbg !19, !llvm.loop !27
+
+for.end:                                          ; preds = %for.cond
+  ret void, !dbg !29
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func float @bar(i32) #1
+
+attributes #0 = { convergent noinline norecurse nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { convergent }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5}
+!opencl.ocl.version = !{!6}
+!opencl.spir.version = !{!7}
+!llvm.ident = !{!8}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 6671a81bc71cc2635c5a10d6f688fea46ca4e5d6)", isOptimized: false, runtimeVersion: 0, emissionKind: LineTablesOnly, enums: !2, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "loop.cl", directory: "/export/users/work/khr_spirv/llvm/build/bin")
+!2 = !{}
+!3 = !{i32 7, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"wchar_size", i32 4}
+!6 = !{i32 1, i32 0}
+!7 = !{i32 1, i32 2}
+!8 = !{!"clang version 11.0.0"}
+!9 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !10, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
+!10 = !DISubroutineType(types: !2)
+!11 = !{!"none", !"none"}
+!12 = !{!"float*", !"int"}
+!13 = !{!"", !""}
+!14 = !DILocation(line: 5, column: 12, scope: !9)
+!15 = !DILocation(line: 5, column: 8, scope: !9)
+!16 = !DILocation(line: 5, column: 19, scope: !9)
+!17 = !DILocation(line: 5, column: 23, scope: !9)
+!18 = !DILocation(line: 5, column: 21, scope: !9)
+!19 = !DILocation(line: 5, column: 3, scope: !9)
+!20 = !DILocation(line: 6, column: 21, scope: !9)
+!21 = !DILocation(line: 6, column: 17, scope: !9)
+!22 = !DILocation(line: 6, column: 5, scope: !9)
+!23 = !DILocation(line: 6, column: 12, scope: !9)
+!24 = !DILocation(line: 6, column: 15, scope: !9)
+!25 = !DILocation(line: 7, column: 3, scope: !9)
+!26 = !DILocation(line: 5, column: 26, scope: !9)
+!27 = distinct !{!27, !19, !25, !28}
+!28 = !{!"llvm.loop.unroll.enable"}
+!29 = !DILocation(line: 8, column: 1, scope: !9)
diff --git a/llvm-spirv/test/DebugInfo/X86/default-subrange-array.ll b/llvm-spirv/test/DebugInfo/X86/default-subrange-array.ll
index 6509c92cf707..0222363439a2 100644
--- a/llvm-spirv/test/DebugInfo/X86/default-subrange-array.ll
+++ b/llvm-spirv/test/DebugInfo/X86/default-subrange-array.ll
@@ -31,7 +31,7 @@ source_filename = "test/DebugInfo/X86/default-subrange-array.ll"
 ; CHECK-NEXT:         DW_AT_type
 ; CHECK:            DW_TAG_subrange_type
 ; CHECK-NEXT:         DW_AT_type
-; DWARF4-NEXT:        DW_AT_lower_bound [DW_FORM_data1] (0x00)
+; DWARF4-NEXT:        DW_AT_lower_bound [DW_FORM_sdata] (0)
 ; CHECK-NEXT:         DW_AT_count [DW_FORM_data1]       (0x2a)
 ; DWARF5-NOT:         DW_AT_lower_bound
 
diff --git a/llvm-spirv/test/exec_mode_float_control_khr.ll b/llvm-spirv/test/exec_mode_float_control_khr.ll
new file mode 100755
index 000000000000..e1b1768995e4
--- /dev/null
+++ b/llvm-spirv/test/exec_mode_float_control_khr.ll
@@ -0,0 +1,94 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_KHR_float_controls
+; RUN: llvm-spirv %t.spv -o %t.spt --to-text
+; RUN: FileCheck %s --input-file %t.spt -check-prefix=SPV
+
+; ModuleID = 'float_control.bc'
+source_filename = "float_control.cpp"
+target datalayout = "e-p:64:64-i64:64-n8:16:32"
+target triple = "spir"
+
+; Function Attrs: noinline norecurse nounwind readnone
+define dso_local dllexport spir_kernel void @k_float_controls_0(i32 %ibuf, i32 %obuf) local_unnamed_addr {
+entry:
+  ret void
+}
+
+; Function Attrs: noinline norecurse nounwind readnone
+define dso_local dllexport spir_kernel void @k_float_controls_1(i32 %ibuf, i32 %obuf) local_unnamed_addr {
+entry:
+  ret void
+}
+
+; Function Attrs: noinline norecurse nounwind readnone
+define dso_local dllexport spir_kernel void @k_float_controls_2(i32 %ibuf, i32 %obuf) local_unnamed_addr {
+entry:
+  ret void
+}
+
+; Function Attrs: noinline norecurse nounwind readnone
+define dso_local dllexport spir_kernel void @k_float_controls_3(i32 %ibuf, i32 %obuf) local_unnamed_addr {
+entry:
+  ret void
+}
+
+; Function Attrs: noinline norecurse nounwind readnone
+define dso_local dllexport spir_kernel void @k_float_controls_4(i32 %ibuf, i32 %obuf) local_unnamed_addr {
+entry:
+  ret void
+}
+
+
+!llvm.module.flags = !{!12}
+!llvm.ident = !{!13}
+!spirv.EntryPoint = !{}
+!spirv.ExecutionMode = !{!15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29}
+
+; SPV-DAG: EntryPoint {{[0-9]+}} [[KERNEL0:[0-9]+]] "k_float_controls_0"
+; SPV-DAG: EntryPoint {{[0-9]+}} [[KERNEL1:[0-9]+]] "k_float_controls_1"
+; SPV-DAG: EntryPoint {{[0-9]+}} [[KERNEL2:[0-9]+]] "k_float_controls_2"
+; SPV-DAG: EntryPoint {{[0-9]+}} [[KERNEL3:[0-9]+]] "k_float_controls_3"
+; SPV-DAG: EntryPoint {{[0-9]+}} [[KERNEL4:[0-9]+]] "k_float_controls_4"
+!0 = !{void (i32, i32)* @k_float_controls_0, !"k_float_controls_0", !1, i32 0, !2, !3, !4, i32 0, i32 0}
+!1 = !{i32 2, i32 2}
+!2 = !{i32 32, i32 36}
+!3 = !{i32 0, i32 0}
+!4 = !{!"", !""}
+!12 = !{i32 1, !"wchar_size", i32 4}
+!13 = !{!"clang version 8.0.1"}
+!14 = !{i32 1, i32 0}
+
+; SPV-DAG: ExecutionMode [[KERNEL0]] 4459 64
+!15 = !{void (i32, i32)* @k_float_controls_0, i32 4459, i32 64}
+; SPV-DAG: ExecutionMode [[KERNEL0]] 4459 32
+!16 = !{void (i32, i32)* @k_float_controls_0, i32 4459, i32 32}
+; SPV-DAG: ExecutionMode [[KERNEL0]] 4459 16
+!17 = !{void (i32, i32)* @k_float_controls_0, i32 4459, i32 16}
+
+; SPV-DAG: ExecutionMode [[KERNEL1]] 4460 64
+!18 = !{void (i32, i32)* @k_float_controls_1, i32 4460, i32 64}
+; SPV-DAG: ExecutionMode [[KERNEL1]] 4460 32
+!19 = !{void (i32, i32)* @k_float_controls_1, i32 4460, i32 32}
+; SPV-DAG: ExecutionMode [[KERNEL1]] 4460 16
+!20 = !{void (i32, i32)* @k_float_controls_1, i32 4460, i32 16}
+
+; SPV-DAG: ExecutionMode [[KERNEL2]] 4461 64
+!21 = !{void (i32, i32)* @k_float_controls_2, i32 4461, i32 64}
+; SPV-DAG: ExecutionMode [[KERNEL2]] 4461 32
+!22 = !{void (i32, i32)* @k_float_controls_2, i32 4461, i32 32}
+; SPV-DAG: ExecutionMode [[KERNEL2]] 4461 16
+!23 = !{void (i32, i32)* @k_float_controls_2, i32 4461, i32 16}
+
+; SPV-DAG: ExecutionMode [[KERNEL3]] 4462 64
+!24 = !{void (i32, i32)* @k_float_controls_3, i32 4462, i32 64}
+; SPV-DAG: ExecutionMode [[KERNEL3]] 4462 32
+!25 = !{void (i32, i32)* @k_float_controls_3, i32 4462, i32 32}
+; SPV-DAG: ExecutionMode [[KERNEL3]] 4462 16
+!26 = !{void (i32, i32)* @k_float_controls_3, i32 4462, i32 16}
+
+; SPV-DAG: ExecutionMode [[KERNEL4]] 4463 64
+!27 = !{void (i32, i32)* @k_float_controls_4, i32 4463, i32 64}
+; SPV-DAG: ExecutionMode [[KERNEL4]] 4463 32
+!28 = !{void (i32, i32)* @k_float_controls_4, i32 4463, i32 32}
+; SPV-DAG: ExecutionMode [[KERNEL4]] 4463 16
+!29 = !{void (i32, i32)* @k_float_controls_4, i32 4463, i32 16}
diff --git a/llvm-spirv/test/memory_model_md.ll b/llvm-spirv/test/memory_model_md.ll
new file mode 100755
index 000000000000..a90354ca245f
--- /dev/null
+++ b/llvm-spirv/test/memory_model_md.ll
@@ -0,0 +1,31 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -o %t.spt --to-text
+; RUN: llvm-spirv -r %t.spv -o %t.bc
+; RUN: llvm-dis %t.bc -o %t.ll
+; RUN: FileCheck %s --input-file %t.ll  -check-prefix=LLVM
+; RUN: FileCheck %s --input-file %t.spt -check-prefix=SPV
+
+; ModuleID = 'float_control_empty.bc'
+source_filename = "float_control_empty.cpp"
+target datalayout = "e-p:64:64-i64:64-n8:16:32"
+target triple = "spir"
+
+; LLVM: !spirv.MemoryModel = !{![[MMMD:[0-9]+]]}
+; LLVM: ![[MMMD]] = !{i32 {{[0-9]+}}, i32 0}
+; SPV: MemoryModel 1 0
+; Function Attrs: noinline norecurse nounwind readnone
+define dso_local dllexport void @k_no_fc(i32 %ibuf, i32 %obuf) local_unnamed_addr #16 {
+entry:
+  ret void
+}
+
+attributes #16 = { noinline norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!1}
+!llvm.ident = !{!2}
+!spirv.MemoryModel = !{!0}
+
+!0 = !{i32 1, i32 0}
+!1 = !{i32 1, !"wchar_size", i32 4}
+!2 = !{!"clang version 8.0.1"}
diff --git a/llvm-spirv/test/spirv-version-controls-negative-1.spt b/llvm-spirv/test/spirv-version-controls-negative-1.spt
index f47dac3000f2..778015c75437 100644
--- a/llvm-spirv/test/spirv-version-controls-negative-1.spt
+++ b/llvm-spirv/test/spirv-version-controls-negative-1.spt
@@ -29,5 +29,5 @@
 
 ; RUN: not --crash llvm-spirv %s -to-binary -o - 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
 ;
-; CHECK-ERROR: Invalid SPIR-V module: unsupported SPIR-V version number 'unknown (66560)'. Range of supported/known SPIR-V versions is 1.0 (65536) - 1.1 (65792)
+; CHECK-ERROR: Invalid SPIR-V module: unsupported SPIR-V version number 'unknown (66560)'. Range of supported/known SPIR-V versions is 1.0 (65536) - 1.3 (66304)
 
diff --git a/llvm-spirv/test/spirv-version-controls-negative-2.spt b/llvm-spirv/test/spirv-version-controls-negative-2.spt
index ce0d9deb7a8d..fc7b8c36fc67 100644
--- a/llvm-spirv/test/spirv-version-controls-negative-2.spt
+++ b/llvm-spirv/test/spirv-version-controls-negative-2.spt
@@ -29,6 +29,6 @@
 
 ; RUN: not --crash llvm-spirv %s -to-binary -o - 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
 ;
-; CHECK-ERROR: Invalid SPIR-V module: unsupported SPIR-V version number 'unknown (1024)'. Range of supported/known SPIR-V versions is 1.0 (65536) - 1.1 (65792)
+; CHECK-ERROR: Invalid SPIR-V module: unsupported SPIR-V version number 'unknown (1024)'. Range of supported/known SPIR-V versions is 1.0 (65536) - 1.3 (66304)
 
 
diff --git a/llvm-spirv/test/transcoding/ReqdSubgroupSize.ll b/llvm-spirv/test/transcoding/ReqdSubgroupSize.ll
index 703a87f5e673..6978c3d42425 100644
--- a/llvm-spirv/test/transcoding/ReqdSubgroupSize.ll
+++ b/llvm-spirv/test/transcoding/ReqdSubgroupSize.ll
@@ -7,6 +7,7 @@
 ; RUN: llvm-spirv %t.spv -to-text -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 ; RUN: llvm-spirv %t.spv -r -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM
 
+; CHECK-SPIRV: Capability CapabilitySubgroupDispatch
 ; CHECK-SPIRV: EntryPoint 6 [[kernel:[0-9]+]] "foo"
 ; CHECK-SPIRV: ExecutionMode [[kernel]] 35 8
 
diff --git a/llvm-spirv/test/transcoding/SPV_INTEL_function_pointers/select.ll b/llvm-spirv/test/transcoding/SPV_INTEL_function_pointers/select.ll
new file mode 100644
index 000000000000..163fc17e78d3
--- /dev/null
+++ b/llvm-spirv/test/transcoding/SPV_INTEL_function_pointers/select.ll
@@ -0,0 +1,147 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_function_pointers -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv -r %t.spv -o %t.r.bc
+; RUN: llvm-dis %t.r.bc -o %t.r.ll
+; RUN: FileCheck < %t.r.ll %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV: EntryPoint 6 [[#KERNEL_ID:]] "_ZTS6kernel"
+; CHECK-SPIRV-DAG: Name [[#BAR:]] "_Z3barii"
+; CHECK-SPIRV-DAG: Name [[#BAZ:]] "_Z3bazii"
+; CHECK-SPIRV: TypeInt [[#INT32:]] 32
+; CHECK-SPIRV: TypeFunction [[#FUNC_TYPE:]] [[#INT32]] [[#INT32]]
+; CHECK-SPIRV: TypePointer [[#FUNC_PTR_TYPE:]] [[#]] [[#FUNC_TYPE]]
+; CHECK-SPIRV: TypePointer [[#FUNC_PTR_ALLOCA_TYPE:]] [[#]] [[#FUNC_PTR_TYPE]]
+; CHECK-SPIRV: Function [[#]] [[#KERNEL_ID]]
+; CHECK-SPIRV: Variable [[#FUNC_PTR_ALLOCA_TYPE]] [[#FPTR:]]
+; CHECK-SPIRV-DAG: FunctionPointerINTEL [[#FUNC_PTR_TYPE]] [[#BARPTR:]] [[#BAR]]
+; CHECK-SPIRV-DAG: FunctionPointerINTEL [[#FUNC_PTR_TYPE]] [[#BAZPTR:]] [[#BAZ]]
+; CHECK-SPIRV: Select [[#FUNC_PTR_TYPE]] [[#SELECT:]] [[#]] [[#BARPTR]] [[#BAZPTR]]
+; CHECK-SPIRV: Store [[#FPTR]] [[#SELECT]]
+; CHECK-SPIRV: Load [[#FUNC_PTR_TYPE]] [[#LOAD:]] [[#FPTR]]
+; CHECK-SPIRV: FunctionPointerCallINTEL [[#]] [[#]] [[#LOAD]]
+
+; CHECK-LLVM: define spir_kernel void @_ZTS6kernel
+; CHECK-LLVM: %[[FPTR_ALLOCA:.*]] = alloca i32 (i32, i32)*
+; CHECK-LLVM: %[[SELECT:.*]] = select i1 %{{.*}}, i32 (i32, i32)* @_Z3barii, i32 (i32, i32)* @_Z3bazii
+; CHECK-LLVM: store i32 (i32, i32)* %[[SELECT]], i32 (i32, i32)** %[[FPTR_ALLOCA]]
+; CHECK-LLVM: %[[FPTR:.*]] = load i32 (i32, i32)*, i32 (i32, i32)** %[[FPTR_ALLOCA]]
+; CHECK-LLVM: call spir_func i32 %[[FPTR]](
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
+target triple = "spir64-unknown-unknown"
+
+%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" }
+%"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" = type { [1 x i64] }
+%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" }
+
+$_ZTS6kernel = comdat any
+
+@__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(1) constant <3 x i64>, align 32
+
+; Function Attrs: norecurse
+define weak_odr dso_local spir_kernel void @_ZTS6kernel(i32 addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3) local_unnamed_addr #0 comdat !kernel_arg_addr_space !4 !kernel_arg_access_qual !5 !kernel_arg_type !6 !kernel_arg_base_type !6 !kernel_arg_type_qual !7 {
+entry:
+  %fptr.alloca = alloca i32 (i32, i32)*, align 8
+  %ref.tmp.i = alloca %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", align 8
+  %agg.tmp2.i = alloca %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range", align 8
+  %agg.tmp3.i = alloca %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range", align 8
+  %agg.tmp6 = alloca %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", align 8
+  %0 = bitcast %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* %agg.tmp2.i to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  %1 = bitcast %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* %agg.tmp3.i to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %1)
+  %2 = addrspacecast %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* %agg.tmp2.i to %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" addrspace(4)*
+  %ptrint4.i = ptrtoint %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" addrspace(4)* %2 to i64
+  %maskedptr5.i = and i64 %ptrint4.i, 7
+  %maskcond6.i = icmp eq i64 %maskedptr5.i, 0
+  %3 = addrspacecast %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* %agg.tmp3.i to %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" addrspace(4)*
+  %ptrint.i = ptrtoint %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" addrspace(4)* %3 to i64
+  %maskedptr.i = and i64 %ptrint.i, 7
+  %maskcond.i = icmp eq i64 %maskedptr.i, 0
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %1)
+  %4 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0
+  %5 = load i64, i64* %4, align 8
+  %add.ptr.i = getelementptr inbounds i32, i32 addrspace(1)* %_arg_, i64 %5
+  %6 = addrspacecast %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %agg.tmp6 to %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" addrspace(4)*
+  %ptrint = ptrtoint %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" addrspace(4)* %6 to i64
+  %maskedptr = and i64 %ptrint, 7
+  %maskcond = icmp eq i64 %maskedptr, 0
+  %7 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast (<3 x i64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x i64> addrspace(4)*), align 32, !noalias !8
+  %8 = extractelement <3 x i64> %7, i64 0
+  %arrayinit.begin.i.i.i.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" addrspace(4)* %6, i64 0, i32 0, i32 0, i64 0
+  store i64 %8, i64 addrspace(4)* %arrayinit.begin.i.i.i.i.i, align 8, !tbaa !15, !alias.scope !8
+  %9 = bitcast %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %ref.tmp.i to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %9) #4
+  %10 = addrspacecast %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %ref.tmp.i to %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" addrspace(4)*
+  %ptrint.i2 = ptrtoint %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" addrspace(4)* %10 to i64
+  %maskedptr.i3 = and i64 %ptrint.i2, 7
+  %maskcond.i4 = icmp eq i64 %maskedptr.i3, 0
+  %rem.i.i = and i64 %8, 1
+  %cmp.i.i = icmp eq i64 %rem.i.i, 0
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %9) #4
+  %_Z3barii._Z3bazii.i = select i1 %cmp.i.i, i32 (i32, i32)* @_Z3barii, i32 (i32, i32)* @_Z3bazii
+  store i32 (i32, i32)* %_Z3barii._Z3bazii.i, i32 (i32, i32)** %fptr.alloca, align 8
+  %fptr = load i32 (i32, i32)*, i32 (i32, i32)** %fptr.alloca, align 8
+  %call4.i = call spir_func i32 %fptr(i32 10, i32 10), !callees !19
+  %arrayidx.i3.i = getelementptr inbounds i32, i32 addrspace(1)* %add.ptr.i, i64 %8
+  %arrayidx.ascast.i.i = addrspacecast i32 addrspace(1)* %arrayidx.i3.i to i32 addrspace(4)*
+  store i32 %call4.i, i32 addrspace(4)* %arrayidx.ascast.i.i, align 4, !tbaa !20
+  ret void
+}
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+
+; Function Attrs: norecurse nounwind readnone
+define dso_local spir_func i32 @_Z3barii(i32 %a, i32 %b) local_unnamed_addr #2 {
+entry:
+  %add = add nsw i32 %b, %a
+  ret i32 %add
+}
+
+; Function Attrs: norecurse nounwind readnone
+define dso_local spir_func i32 @_Z3bazii(i32 %a, i32 %b) local_unnamed_addr #2 {
+entry:
+  %sub = sub nsw i32 %a, %b
+  ret i32 %sub
+}
+
+attributes #0 = { norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "sycl-module-id"="f.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { argmemonly nounwind willreturn }
+attributes #2 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind willreturn }
+attributes #4 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.spir.version = !{!1}
+!spirv.Source = !{!2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{i32 4, i32 100000}
+!3 = !{!"clang version 11.0.0 "}
+!4 = !{i32 1, i32 0, i32 0, i32 0}
+!5 = !{!"none", !"none", !"none", !"none"}
+!6 = !{!"int*", !"cl::sycl::range<1>", !"cl::sycl::range<1>", !"cl::sycl::id<1>"}
+!7 = !{!"", !"", !"", !""}
+!8 = !{!9, !11, !13}
+!9 = distinct !{!9, !10, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv: %agg.result"}
+!10 = distinct !{!10, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv"}
+!11 = distinct !{!11, !12, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v: %agg.result"}
+!12 = distinct !{!12, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v"}
+!13 = distinct !{!13, !14, !"_ZN2cl4sycl6detail7Builder5getIdILi1EEEKNS0_2idIXT_EEEv: %agg.result"}
+!14 = distinct !{!14, !"_ZN2cl4sycl6detail7Builder5getIdILi1EEEKNS0_2idIXT_EEEv"}
+!15 = !{!16, !16, i64 0}
+!16 = !{!"long", !17, i64 0}
+!17 = !{!"omnipotent char", !18, i64 0}
+!18 = !{!"Simple C++ TBAA"}
+!19 = !{i32 (i32, i32)* @_Z3barii, i32 (i32, i32)* @_Z3bazii}
+!20 = !{!21, !21, i64 0}
+!21 = !{!"int", !17, i64 0}
diff --git a/llvm-spirv/test/transcoding/sub_group_ballot.ll b/llvm-spirv/test/transcoding/sub_group_ballot.ll
new file mode 100644
index 000000000000..2092f9544912
--- /dev/null
+++ b/llvm-spirv/test/transcoding/sub_group_ballot.ll
@@ -0,0 +1,1194 @@
+;; #pragma OPENCL EXTENSION cl_khr_subgroup_ballot : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp16 : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp64 : enable
+;; 
+;; kernel void testNonUniformBroadcastChars()
+;; {
+;;     char16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastUChars()
+;; {
+;;     uchar16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastShorts()
+;; {
+;;     short16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastUShorts()
+;; {
+;;     ushort16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastInts()
+;; {
+;;     int16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastUInts()
+;; {
+;;     uint16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastLongs()
+;; {
+;;     long16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastULongs()
+;; {
+;;     ulong16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastFloats()
+;; {
+;;     float16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastHalfs()
+;; {
+;;     half16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testNonUniformBroadcastDoubles()
+;; {
+;;     double16 v = 0;
+;;     v.s0 = sub_group_non_uniform_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_non_uniform_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_non_uniform_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_non_uniform_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_non_uniform_broadcast(v.s01234567, 0);
+;;     v = sub_group_non_uniform_broadcast(v, 0);
+;;     v.s0 = sub_group_broadcast_first(v.s0);
+;; }
+;; 
+;; kernel void testBallotOperations(global uint* dst)
+;; {
+;;     uint4 v = sub_group_ballot(0);
+;;     dst[0] = sub_group_inverse_ballot(v);
+;;     dst[1] = sub_group_ballot_bit_extract(v, 0);
+;;     dst[2] = sub_group_ballot_bit_count(v);
+;;     dst[3] = sub_group_ballot_inclusive_scan(v);
+;;     dst[4] = sub_group_ballot_exclusive_scan(v);
+;;     dst[5] = sub_group_ballot_find_lsb(v);
+;;     dst[6] = sub_group_ballot_find_msb(v);
+;; }
+;; 
+;; kernel void testSubgroupMasks(global uint4* dst)
+;; {
+;;     dst[0] = get_sub_group_eq_mask();
+;;     dst[1] = get_sub_group_ge_mask();
+;;     dst[2] = get_sub_group_gt_mask();
+;;     dst[3] = get_sub_group_le_mask();
+;;     dst[4] = get_sub_group_lt_mask();
+;; }
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; Change DISABLED to RUN once SPIRV->LLVM translation is implemented
+; DISABLED: llvm-spirv -r %t.spv -o %t.rev.bc
+; DISABLED: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; ModuleID = 'subgroup_ballot.cl'
+source_filename = "subgroup_ballot.cl"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+; CHECK-SPIRV-DAG: {{[0-9]*}} Capability GroupNonUniformBallot
+
+; CHECK-SPIRV-DAG: Decorate [[eqMask:[0-9]+]] BuiltIn 4416
+; CHECK-SPIRV-DAG: Decorate [[geMask:[0-9]+]] BuiltIn 4417
+; CHECK-SPIRV-DAG: Decorate [[gtMask:[0-9]+]] BuiltIn 4418
+; CHECK-SPIRV-DAG: Decorate [[leMask:[0-9]+]] BuiltIn 4419
+; CHECK-SPIRV-DAG: Decorate [[ltMask:[0-9]+]] BuiltIn 4420
+
+; CHECK-SPIRV-DAG: TypeBool  [[bool:[0-9]+]]
+; CHECK-SPIRV-DAG: TypeInt   [[char:[0-9]+]]   8  0
+; CHECK-SPIRV-DAG: TypeInt   [[short:[0-9]+]]  16 0
+; CHECK-SPIRV-DAG: TypeInt   [[int:[0-9]+]]    32 0
+; CHECK-SPIRV-DAG: TypeInt   [[long:[0-9]+]]   64 0
+; CHECK-SPIRV-DAG: TypeFloat [[half:[0-9]+]]   16
+; CHECK-SPIRV-DAG: TypeFloat [[float:[0-9]+]]  32
+; CHECK-SPIRV-DAG: TypeFloat [[double:[0-9]+]] 64
+
+; CHECK-SPIRV-DAG: TypeVector [[char2:[0-9]+]]  [[char]] 2
+; CHECK-SPIRV-DAG: TypeVector [[char3:[0-9]+]]  [[char]] 3
+; CHECK-SPIRV-DAG: TypeVector [[char4:[0-9]+]]  [[char]] 4
+; CHECK-SPIRV-DAG: TypeVector [[char8:[0-9]+]]  [[char]] 8
+; CHECK-SPIRV-DAG: TypeVector [[char16:[0-9]+]] [[char]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[short2:[0-9]+]]  [[short]] 2
+; CHECK-SPIRV-DAG: TypeVector [[short3:[0-9]+]]  [[short]] 3
+; CHECK-SPIRV-DAG: TypeVector [[short4:[0-9]+]]  [[short]] 4
+; CHECK-SPIRV-DAG: TypeVector [[short8:[0-9]+]]  [[short]] 8
+; CHECK-SPIRV-DAG: TypeVector [[short16:[0-9]+]] [[short]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[int2:[0-9]+]]  [[int]] 2
+; CHECK-SPIRV-DAG: TypeVector [[int3:[0-9]+]]  [[int]] 3
+; CHECK-SPIRV-DAG: TypeVector [[int4:[0-9]+]]  [[int]] 4
+; CHECK-SPIRV-DAG: TypeVector [[int8:[0-9]+]]  [[int]] 8
+; CHECK-SPIRV-DAG: TypeVector [[int16:[0-9]+]] [[int]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[long2:[0-9]+]]  [[long]] 2
+; CHECK-SPIRV-DAG: TypeVector [[long3:[0-9]+]]  [[long]] 3
+; CHECK-SPIRV-DAG: TypeVector [[long4:[0-9]+]]  [[long]] 4
+; CHECK-SPIRV-DAG: TypeVector [[long8:[0-9]+]]  [[long]] 8
+; CHECK-SPIRV-DAG: TypeVector [[long16:[0-9]+]] [[long]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[float2:[0-9]+]]  [[float]] 2
+; CHECK-SPIRV-DAG: TypeVector [[float3:[0-9]+]]  [[float]] 3
+; CHECK-SPIRV-DAG: TypeVector [[float4:[0-9]+]]  [[float]] 4
+; CHECK-SPIRV-DAG: TypeVector [[float8:[0-9]+]]  [[float]] 8
+; CHECK-SPIRV-DAG: TypeVector [[float16:[0-9]+]] [[float]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[half2:[0-9]+]]  [[half]] 2
+; CHECK-SPIRV-DAG: TypeVector [[half3:[0-9]+]]  [[half]] 3
+; CHECK-SPIRV-DAG: TypeVector [[half4:[0-9]+]]  [[half]] 4
+; CHECK-SPIRV-DAG: TypeVector [[half8:[0-9]+]]  [[half]] 8
+; CHECK-SPIRV-DAG: TypeVector [[half16:[0-9]+]] [[half]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[double2:[0-9]+]]  [[double]] 2
+; CHECK-SPIRV-DAG: TypeVector [[double3:[0-9]+]]  [[double]] 3
+; CHECK-SPIRV-DAG: TypeVector [[double4:[0-9]+]]  [[double]] 4
+; CHECK-SPIRV-DAG: TypeVector [[double8:[0-9]+]]  [[double]] 8
+; CHECK-SPIRV-DAG: TypeVector [[double16:[0-9]+]] [[double]] 16
+
+; CHECK-SPIRV-DAG: ConstantFalse [[bool]] [[false:[0-9]+]]
+; CHECK-SPIRV-DAG: Constant [[int]]    [[ScopeSubgroup:[0-9]+]] 3
+; CHECK-SPIRV-DAG: Constant [[char]]   [[char_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[short]]  [[short_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[int]]    [[int_0:[0-9]+]]         0
+; CHECK-SPIRV-DAG: Constant [[long]]   [[long_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[half]]   [[half_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[float]]  [[float_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[double]] [[double_0:[0-9]+]]      0
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char2]] [[char2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char2]] {{[0-9]+}} [[ScopeSubgroup]] [[char2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char3]] [[char3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char3]] {{[0-9]+}} [[ScopeSubgroup]] [[char3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char4]] [[char4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char4]] {{[0-9]+}} [[ScopeSubgroup]] [[char4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char8]] [[char8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char8]] {{[0-9]+}} [[ScopeSubgroup]] [[char8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[char16]] [[char16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char16]] {{[0-9]+}} [[ScopeSubgroup]] [[char16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[char]] [[char_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastChars
+; CHECK-LLVM: call spir_func i8 @_Z31sub_group_non_uniform_broadcasthj(i8 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i8> @_Z31sub_group_non_uniform_broadcastDv2_hj(<2 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i8> @_Z31sub_group_non_uniform_broadcastDv3_hj(<3 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i8> @_Z31sub_group_non_uniform_broadcastDv4_hj(<4 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i8> @_Z31sub_group_non_uniform_broadcastDv8_hj(<8 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i8> @_Z31sub_group_non_uniform_broadcastDv16_hj(<16 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func i8 @_Z25sub_group_broadcast_firsth(i8 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastChars() local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func signext i8 @_Z31sub_group_non_uniform_broadcastcj(i8 signext 0, i32 0) #7
+  %2 = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %1, i64 0
+  %3 = shufflevector <16 x i8> %2, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i8> @_Z31sub_group_non_uniform_broadcastDv2_cj(<2 x i8> %3, i32 0) #7
+  %5 = shufflevector <2 x i8> %4, <2 x i8> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i8> %5, <16 x i8> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i8> %6, <16 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i8> @_Z31sub_group_non_uniform_broadcastDv3_cj(<3 x i8> %7, i32 0) #7
+  %9 = shufflevector <3 x i8> %8, <3 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i8> %9, <16 x i8> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i8> %10, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i8> @_Z31sub_group_non_uniform_broadcastDv4_cj(<4 x i8> %11, i32 0) #7
+  %13 = shufflevector <4 x i8> %12, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i8> %13, <16 x i8> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i8> %14, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i8> @_Z31sub_group_non_uniform_broadcastDv8_cj(<8 x i8> %15, i32 0) #7
+  %17 = shufflevector <8 x i8> %16, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i8> %17, <16 x i8> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i8> @_Z31sub_group_non_uniform_broadcastDv16_cj(<16 x i8> %18, i32 0) #7
+  %20 = extractelement <16 x i8> %19, i64 0
+  %21 = tail call spir_func signext i8 @_Z25sub_group_broadcast_firstc(i8 signext %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z31sub_group_non_uniform_broadcastcj(i8 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i8> @_Z31sub_group_non_uniform_broadcastDv2_cj(<2 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i8> @_Z31sub_group_non_uniform_broadcastDv3_cj(<3 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i8> @_Z31sub_group_non_uniform_broadcastDv4_cj(<4 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i8> @_Z31sub_group_non_uniform_broadcastDv8_cj(<8 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i8> @_Z31sub_group_non_uniform_broadcastDv16_cj(<16 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z25sub_group_broadcast_firstc(i8 signext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char2]] [[char2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char2]] {{[0-9]+}} [[ScopeSubgroup]] [[char2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char3]] [[char3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char3]] {{[0-9]+}} [[ScopeSubgroup]] [[char3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char4]] [[char4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char4]] {{[0-9]+}} [[ScopeSubgroup]] [[char4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char8]] [[char8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char8]] {{[0-9]+}} [[ScopeSubgroup]] [[char8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[char16]] [[char16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[char16]] {{[0-9]+}} [[ScopeSubgroup]] [[char16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[char]] [[char_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastUChars
+; CHECK-LLVM: call spir_func i8 @_Z31sub_group_non_uniform_broadcasthj(i8 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i8> @_Z31sub_group_non_uniform_broadcastDv2_hj(<2 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i8> @_Z31sub_group_non_uniform_broadcastDv3_hj(<3 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i8> @_Z31sub_group_non_uniform_broadcastDv4_hj(<4 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i8> @_Z31sub_group_non_uniform_broadcastDv8_hj(<8 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i8> @_Z31sub_group_non_uniform_broadcastDv16_hj(<16 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func i8 @_Z25sub_group_broadcast_firsth(i8 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastUChars() local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func zeroext i8 @_Z31sub_group_non_uniform_broadcasthj(i8 zeroext 0, i32 0) #7
+  %2 = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %1, i64 0
+  %3 = shufflevector <16 x i8> %2, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i8> @_Z31sub_group_non_uniform_broadcastDv2_hj(<2 x i8> %3, i32 0) #7
+  %5 = shufflevector <2 x i8> %4, <2 x i8> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i8> %5, <16 x i8> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i8> %6, <16 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i8> @_Z31sub_group_non_uniform_broadcastDv3_hj(<3 x i8> %7, i32 0) #7
+  %9 = shufflevector <3 x i8> %8, <3 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i8> %9, <16 x i8> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i8> %10, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i8> @_Z31sub_group_non_uniform_broadcastDv4_hj(<4 x i8> %11, i32 0) #7
+  %13 = shufflevector <4 x i8> %12, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i8> %13, <16 x i8> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i8> %14, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i8> @_Z31sub_group_non_uniform_broadcastDv8_hj(<8 x i8> %15, i32 0) #7
+  %17 = shufflevector <8 x i8> %16, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i8> %17, <16 x i8> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i8> @_Z31sub_group_non_uniform_broadcastDv16_hj(<16 x i8> %18, i32 0) #7
+  %20 = extractelement <16 x i8> %19, i64 0
+  %21 = tail call spir_func zeroext i8 @_Z25sub_group_broadcast_firsth(i8 zeroext %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z31sub_group_non_uniform_broadcasthj(i8 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i8> @_Z31sub_group_non_uniform_broadcastDv2_hj(<2 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i8> @_Z31sub_group_non_uniform_broadcastDv3_hj(<3 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i8> @_Z31sub_group_non_uniform_broadcastDv4_hj(<4 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i8> @_Z31sub_group_non_uniform_broadcastDv8_hj(<8 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i8> @_Z31sub_group_non_uniform_broadcastDv16_hj(<16 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z25sub_group_broadcast_firsth(i8 zeroext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short2]] [[short2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short2]] {{[0-9]+}} [[ScopeSubgroup]] [[short2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short3]] [[short3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short3]] {{[0-9]+}} [[ScopeSubgroup]] [[short3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short4]] [[short4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short4]] {{[0-9]+}} [[ScopeSubgroup]] [[short4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short8]] [[short8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short8]] {{[0-9]+}} [[ScopeSubgroup]] [[short8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[short16]] [[short16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short16]] {{[0-9]+}} [[ScopeSubgroup]] [[short16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[short]] [[short_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastShorts
+; CHECK-LLVM: call spir_func i16 @_Z31sub_group_non_uniform_broadcasttj(i16 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i16> @_Z31sub_group_non_uniform_broadcastDv2_tj(<2 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i16> @_Z31sub_group_non_uniform_broadcastDv3_tj(<3 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i16> @_Z31sub_group_non_uniform_broadcastDv4_tj(<4 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i16> @_Z31sub_group_non_uniform_broadcastDv8_tj(<8 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i16> @_Z31sub_group_non_uniform_broadcastDv16_tj(<16 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func i16 @_Z25sub_group_broadcast_firstt(i16 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastShorts() local_unnamed_addr #2 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func signext i16 @_Z31sub_group_non_uniform_broadcastsj(i16 signext 0, i32 0) #7
+  %2 = insertelement <16 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 %1, i64 0
+  %3 = shufflevector <16 x i16> %2, <16 x i16> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i16> @_Z31sub_group_non_uniform_broadcastDv2_sj(<2 x i16> %3, i32 0) #7
+  %5 = shufflevector <2 x i16> %4, <2 x i16> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i16> %5, <16 x i16> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i16> %6, <16 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i16> @_Z31sub_group_non_uniform_broadcastDv3_sj(<3 x i16> %7, i32 0) #7
+  %9 = shufflevector <3 x i16> %8, <3 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i16> %9, <16 x i16> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i16> %10, <16 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i16> @_Z31sub_group_non_uniform_broadcastDv4_sj(<4 x i16> %11, i32 0) #7
+  %13 = shufflevector <4 x i16> %12, <4 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i16> %13, <16 x i16> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i16> %14, <16 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i16> @_Z31sub_group_non_uniform_broadcastDv8_sj(<8 x i16> %15, i32 0) #7
+  %17 = shufflevector <8 x i16> %16, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i16> %17, <16 x i16> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i16> @_Z31sub_group_non_uniform_broadcastDv16_sj(<16 x i16> %18, i32 0) #7
+  %20 = extractelement <16 x i16> %19, i64 0
+  %21 = tail call spir_func signext i16 @_Z25sub_group_broadcast_firsts(i16 signext %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z31sub_group_non_uniform_broadcastsj(i16 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i16> @_Z31sub_group_non_uniform_broadcastDv2_sj(<2 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i16> @_Z31sub_group_non_uniform_broadcastDv3_sj(<3 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i16> @_Z31sub_group_non_uniform_broadcastDv4_sj(<4 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i16> @_Z31sub_group_non_uniform_broadcastDv8_sj(<8 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i16> @_Z31sub_group_non_uniform_broadcastDv16_sj(<16 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z25sub_group_broadcast_firsts(i16 signext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short2]] [[short2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short2]] {{[0-9]+}} [[ScopeSubgroup]] [[short2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short3]] [[short3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short3]] {{[0-9]+}} [[ScopeSubgroup]] [[short3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short4]] [[short4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short4]] {{[0-9]+}} [[ScopeSubgroup]] [[short4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short8]] [[short8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short8]] {{[0-9]+}} [[ScopeSubgroup]] [[short8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[short16]] [[short16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[short16]] {{[0-9]+}} [[ScopeSubgroup]] [[short16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[short]] [[short_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastUShorts
+; CHECK-LLVM: call spir_func i16 @_Z31sub_group_non_uniform_broadcasttj(i16 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i16> @_Z31sub_group_non_uniform_broadcastDv2_tj(<2 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i16> @_Z31sub_group_non_uniform_broadcastDv3_tj(<3 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i16> @_Z31sub_group_non_uniform_broadcastDv4_tj(<4 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i16> @_Z31sub_group_non_uniform_broadcastDv8_tj(<8 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i16> @_Z31sub_group_non_uniform_broadcastDv16_tj(<16 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func i16 @_Z25sub_group_broadcast_firstt(i16 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastUShorts() local_unnamed_addr #2 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func zeroext i16 @_Z31sub_group_non_uniform_broadcasttj(i16 zeroext 0, i32 0) #7
+  %2 = insertelement <16 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 %1, i64 0
+  %3 = shufflevector <16 x i16> %2, <16 x i16> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i16> @_Z31sub_group_non_uniform_broadcastDv2_tj(<2 x i16> %3, i32 0) #7
+  %5 = shufflevector <2 x i16> %4, <2 x i16> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i16> %5, <16 x i16> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i16> %6, <16 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i16> @_Z31sub_group_non_uniform_broadcastDv3_tj(<3 x i16> %7, i32 0) #7
+  %9 = shufflevector <3 x i16> %8, <3 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i16> %9, <16 x i16> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i16> %10, <16 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i16> @_Z31sub_group_non_uniform_broadcastDv4_tj(<4 x i16> %11, i32 0) #7
+  %13 = shufflevector <4 x i16> %12, <4 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i16> %13, <16 x i16> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i16> %14, <16 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i16> @_Z31sub_group_non_uniform_broadcastDv8_tj(<8 x i16> %15, i32 0) #7
+  %17 = shufflevector <8 x i16> %16, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i16> %17, <16 x i16> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i16> @_Z31sub_group_non_uniform_broadcastDv16_tj(<16 x i16> %18, i32 0) #7
+  %20 = extractelement <16 x i16> %19, i64 0
+  %21 = tail call spir_func zeroext i16 @_Z25sub_group_broadcast_firstt(i16 zeroext %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z31sub_group_non_uniform_broadcasttj(i16 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i16> @_Z31sub_group_non_uniform_broadcastDv2_tj(<2 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i16> @_Z31sub_group_non_uniform_broadcastDv3_tj(<3 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i16> @_Z31sub_group_non_uniform_broadcastDv4_tj(<4 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i16> @_Z31sub_group_non_uniform_broadcastDv8_tj(<8 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i16> @_Z31sub_group_non_uniform_broadcastDv16_tj(<16 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z25sub_group_broadcast_firstt(i16 zeroext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int2]] [[int2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int2]] {{[0-9]+}} [[ScopeSubgroup]] [[int2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int3]] [[int3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int3]] {{[0-9]+}} [[ScopeSubgroup]] [[int3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int4]] [[int4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int4]] {{[0-9]+}} [[ScopeSubgroup]] [[int4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int8]] [[int8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int8]] {{[0-9]+}} [[ScopeSubgroup]] [[int8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[int16]] [[int16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int16]] {{[0-9]+}} [[ScopeSubgroup]] [[int16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[int]] [[int_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastInts
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_broadcastjj(i32 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i32> @_Z31sub_group_non_uniform_broadcastDv2_jj(<2 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i32> @_Z31sub_group_non_uniform_broadcastDv3_jj(<3 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i32> @_Z31sub_group_non_uniform_broadcastDv4_jj(<4 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i32> @_Z31sub_group_non_uniform_broadcastDv8_jj(<8 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i32> @_Z31sub_group_non_uniform_broadcastDv16_jj(<16 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z25sub_group_broadcast_firstj(i32 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastInts() local_unnamed_addr #3 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func i32 @_Z31sub_group_non_uniform_broadcastij(i32 0, i32 0) #7
+  %2 = insertelement <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 %1, i64 0
+  %3 = shufflevector <16 x i32> %2, <16 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i32> @_Z31sub_group_non_uniform_broadcastDv2_ij(<2 x i32> %3, i32 0) #7
+  %5 = shufflevector <2 x i32> %4, <2 x i32> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i32> %5, <16 x i32> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i32> %6, <16 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i32> @_Z31sub_group_non_uniform_broadcastDv3_ij(<3 x i32> %7, i32 0) #7
+  %9 = shufflevector <3 x i32> %8, <3 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i32> %9, <16 x i32> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i32> %10, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i32> @_Z31sub_group_non_uniform_broadcastDv4_ij(<4 x i32> %11, i32 0) #7
+  %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i32> %13, <16 x i32> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i32> %14, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i32> @_Z31sub_group_non_uniform_broadcastDv8_ij(<8 x i32> %15, i32 0) #7
+  %17 = shufflevector <8 x i32> %16, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i32> %17, <16 x i32> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i32> @_Z31sub_group_non_uniform_broadcastDv16_ij(<16 x i32> %18, i32 0) #7
+  %20 = extractelement <16 x i32> %19, i64 0
+  %21 = tail call spir_func i32 @_Z25sub_group_broadcast_firsti(i32 %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_broadcastij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i32> @_Z31sub_group_non_uniform_broadcastDv2_ij(<2 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i32> @_Z31sub_group_non_uniform_broadcastDv3_ij(<3 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i32> @_Z31sub_group_non_uniform_broadcastDv4_ij(<4 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i32> @_Z31sub_group_non_uniform_broadcastDv8_ij(<8 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i32> @_Z31sub_group_non_uniform_broadcastDv16_ij(<16 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z25sub_group_broadcast_firsti(i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int2]] [[int2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int2]] {{[0-9]+}} [[ScopeSubgroup]] [[int2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int3]] [[int3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int3]] {{[0-9]+}} [[ScopeSubgroup]] [[int3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int4]] [[int4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int4]] {{[0-9]+}} [[ScopeSubgroup]] [[int4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int8]] [[int8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int8]] {{[0-9]+}} [[ScopeSubgroup]] [[int8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[int16]] [[int16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[int16]] {{[0-9]+}} [[ScopeSubgroup]] [[int16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[int]] [[int_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastUInts
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_broadcastjj(i32 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i32> @_Z31sub_group_non_uniform_broadcastDv2_jj(<2 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i32> @_Z31sub_group_non_uniform_broadcastDv3_jj(<3 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i32> @_Z31sub_group_non_uniform_broadcastDv4_jj(<4 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i32> @_Z31sub_group_non_uniform_broadcastDv8_jj(<8 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i32> @_Z31sub_group_non_uniform_broadcastDv16_jj(<16 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z25sub_group_broadcast_firstj(i32 {{.*}})
+
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastUInts() local_unnamed_addr #3 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func i32 @_Z31sub_group_non_uniform_broadcastjj(i32 0, i32 0) #7
+  %2 = insertelement <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 %1, i64 0
+  %3 = shufflevector <16 x i32> %2, <16 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i32> @_Z31sub_group_non_uniform_broadcastDv2_jj(<2 x i32> %3, i32 0) #7
+  %5 = shufflevector <2 x i32> %4, <2 x i32> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i32> %5, <16 x i32> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i32> %6, <16 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i32> @_Z31sub_group_non_uniform_broadcastDv3_jj(<3 x i32> %7, i32 0) #7
+  %9 = shufflevector <3 x i32> %8, <3 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i32> %9, <16 x i32> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i32> %10, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i32> @_Z31sub_group_non_uniform_broadcastDv4_jj(<4 x i32> %11, i32 0) #7
+  %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i32> %13, <16 x i32> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i32> %14, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i32> @_Z31sub_group_non_uniform_broadcastDv8_jj(<8 x i32> %15, i32 0) #7
+  %17 = shufflevector <8 x i32> %16, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i32> %17, <16 x i32> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i32> @_Z31sub_group_non_uniform_broadcastDv16_jj(<16 x i32> %18, i32 0) #7
+  %20 = extractelement <16 x i32> %19, i64 0
+  %21 = tail call spir_func i32 @_Z25sub_group_broadcast_firstj(i32 %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_broadcastjj(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i32> @_Z31sub_group_non_uniform_broadcastDv2_jj(<2 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i32> @_Z31sub_group_non_uniform_broadcastDv3_jj(<3 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i32> @_Z31sub_group_non_uniform_broadcastDv4_jj(<4 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i32> @_Z31sub_group_non_uniform_broadcastDv8_jj(<8 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i32> @_Z31sub_group_non_uniform_broadcastDv16_jj(<16 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z25sub_group_broadcast_firstj(i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long2]] [[long2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long2]] {{[0-9]+}} [[ScopeSubgroup]] [[long2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long3]] [[long3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long3]] {{[0-9]+}} [[ScopeSubgroup]] [[long3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long4]] [[long4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long4]] {{[0-9]+}} [[ScopeSubgroup]] [[long4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long8]] [[long8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long8]] {{[0-9]+}} [[ScopeSubgroup]] [[long8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[long16]] [[long16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long16]] {{[0-9]+}} [[ScopeSubgroup]] [[long16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[long]] [[long_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastLongs
+; CHECK-LLVM: call spir_func i64 @_Z31sub_group_non_uniform_broadcastmj(i64 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i64> @_Z31sub_group_non_uniform_broadcastDv2_mj(<2 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i64> @_Z31sub_group_non_uniform_broadcastDv3_mj(<3 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i64> @_Z31sub_group_non_uniform_broadcastDv4_mj(<4 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i64> @_Z31sub_group_non_uniform_broadcastDv8_mj(<8 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i64> @_Z31sub_group_non_uniform_broadcastDv16_mj(<16 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func i64 @_Z25sub_group_broadcast_firstm(i64 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastLongs() local_unnamed_addr #4 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func i64 @_Z31sub_group_non_uniform_broadcastlj(i64 0, i32 0) #7
+  %2 = insertelement <16 x i64> <i64 undef, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 %1, i64 0
+  %3 = shufflevector <16 x i64> %2, <16 x i64> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i64> @_Z31sub_group_non_uniform_broadcastDv2_lj(<2 x i64> %3, i32 0) #7
+  %5 = shufflevector <2 x i64> %4, <2 x i64> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i64> %5, <16 x i64> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i64> %6, <16 x i64> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i64> @_Z31sub_group_non_uniform_broadcastDv3_lj(<3 x i64> %7, i32 0) #7
+  %9 = shufflevector <3 x i64> %8, <3 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i64> %9, <16 x i64> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i64> %10, <16 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i64> @_Z31sub_group_non_uniform_broadcastDv4_lj(<4 x i64> %11, i32 0) #7
+  %13 = shufflevector <4 x i64> %12, <4 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i64> %13, <16 x i64> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i64> %14, <16 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i64> @_Z31sub_group_non_uniform_broadcastDv8_lj(<8 x i64> %15, i32 0) #7
+  %17 = shufflevector <8 x i64> %16, <8 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i64> %17, <16 x i64> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i64> @_Z31sub_group_non_uniform_broadcastDv16_lj(<16 x i64> %18, i32 0) #7
+  %20 = extractelement <16 x i64> %19, i64 0
+  %21 = tail call spir_func i64 @_Z25sub_group_broadcast_firstl(i64 %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z31sub_group_non_uniform_broadcastlj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i64> @_Z31sub_group_non_uniform_broadcastDv2_lj(<2 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i64> @_Z31sub_group_non_uniform_broadcastDv3_lj(<3 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i64> @_Z31sub_group_non_uniform_broadcastDv4_lj(<4 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i64> @_Z31sub_group_non_uniform_broadcastDv8_lj(<8 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i64> @_Z31sub_group_non_uniform_broadcastDv16_lj(<16 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z25sub_group_broadcast_firstl(i64) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long2]] [[long2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long2]] {{[0-9]+}} [[ScopeSubgroup]] [[long2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long3]] [[long3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long3]] {{[0-9]+}} [[ScopeSubgroup]] [[long3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long4]] [[long4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long4]] {{[0-9]+}} [[ScopeSubgroup]] [[long4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long8]] [[long8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long8]] {{[0-9]+}} [[ScopeSubgroup]] [[long8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[long16]] [[long16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[long16]] {{[0-9]+}} [[ScopeSubgroup]] [[long16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[long]] [[long_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastULongs
+; CHECK-LLVM: call spir_func i64 @_Z31sub_group_non_uniform_broadcastmj(i64 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i64> @_Z31sub_group_non_uniform_broadcastDv2_mj(<2 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i64> @_Z31sub_group_non_uniform_broadcastDv3_mj(<3 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i64> @_Z31sub_group_non_uniform_broadcastDv4_mj(<4 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i64> @_Z31sub_group_non_uniform_broadcastDv8_mj(<8 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i64> @_Z31sub_group_non_uniform_broadcastDv16_mj(<16 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func i64 @_Z25sub_group_broadcast_firstm(i64 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastULongs() local_unnamed_addr #4 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func i64 @_Z31sub_group_non_uniform_broadcastmj(i64 0, i32 0) #7
+  %2 = insertelement <16 x i64> <i64 undef, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 %1, i64 0
+  %3 = shufflevector <16 x i64> %2, <16 x i64> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i64> @_Z31sub_group_non_uniform_broadcastDv2_mj(<2 x i64> %3, i32 0) #7
+  %5 = shufflevector <2 x i64> %4, <2 x i64> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i64> %5, <16 x i64> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i64> %6, <16 x i64> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i64> @_Z31sub_group_non_uniform_broadcastDv3_mj(<3 x i64> %7, i32 0) #7
+  %9 = shufflevector <3 x i64> %8, <3 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i64> %9, <16 x i64> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i64> %10, <16 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i64> @_Z31sub_group_non_uniform_broadcastDv4_mj(<4 x i64> %11, i32 0) #7
+  %13 = shufflevector <4 x i64> %12, <4 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i64> %13, <16 x i64> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i64> %14, <16 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i64> @_Z31sub_group_non_uniform_broadcastDv8_mj(<8 x i64> %15, i32 0) #7
+  %17 = shufflevector <8 x i64> %16, <8 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i64> %17, <16 x i64> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i64> @_Z31sub_group_non_uniform_broadcastDv16_mj(<16 x i64> %18, i32 0) #7
+  %20 = extractelement <16 x i64> %19, i64 0
+  %21 = tail call spir_func i64 @_Z25sub_group_broadcast_firstm(i64 %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z31sub_group_non_uniform_broadcastmj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i64> @_Z31sub_group_non_uniform_broadcastDv2_mj(<2 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i64> @_Z31sub_group_non_uniform_broadcastDv3_mj(<3 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i64> @_Z31sub_group_non_uniform_broadcastDv4_mj(<4 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i64> @_Z31sub_group_non_uniform_broadcastDv8_mj(<8 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i64> @_Z31sub_group_non_uniform_broadcastDv16_mj(<16 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z25sub_group_broadcast_firstm(i64) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[float]] {{[0-9]+}} [[ScopeSubgroup]] [[float_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float2]] [[float2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[float2]] {{[0-9]+}} [[ScopeSubgroup]] [[float2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float3]] [[float3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[float3]] {{[0-9]+}} [[ScopeSubgroup]] [[float3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float4]] [[float4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[float4]] {{[0-9]+}} [[ScopeSubgroup]] [[float4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float8]] [[float8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[float8]] {{[0-9]+}} [[ScopeSubgroup]] [[float8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[float16]] [[float16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[float16]] {{[0-9]+}} [[ScopeSubgroup]] [[float16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[float]] [[float_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[float]] {{[0-9]+}} [[ScopeSubgroup]] [[float_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastFloats
+; CHECK-LLVM: call spir_func float @_Z31sub_group_non_uniform_broadcastfj(float {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x float> @_Z31sub_group_non_uniform_broadcastDv2_fj(<2 x float> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x float> @_Z31sub_group_non_uniform_broadcastDv3_fj(<3 x float> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x float> @_Z31sub_group_non_uniform_broadcastDv4_fj(<4 x float> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x float> @_Z31sub_group_non_uniform_broadcastDv8_fj(<8 x float> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x float> @_Z31sub_group_non_uniform_broadcastDv16_fj(<16 x float> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func float @_Z25sub_group_broadcast_firstf(float {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastFloats() local_unnamed_addr #3 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func float @_Z31sub_group_non_uniform_broadcastfj(float 0.000000e+00, i32 0) #7
+  %2 = insertelement <16 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %1, i64 0
+  %3 = shufflevector <16 x float> %2, <16 x float> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x float> @_Z31sub_group_non_uniform_broadcastDv2_fj(<2 x float> %3, i32 0) #7
+  %5 = shufflevector <2 x float> %4, <2 x float> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x float> %5, <16 x float> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x float> %6, <16 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x float> @_Z31sub_group_non_uniform_broadcastDv3_fj(<3 x float> %7, i32 0) #7
+  %9 = shufflevector <3 x float> %8, <3 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x float> %9, <16 x float> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x float> %10, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x float> @_Z31sub_group_non_uniform_broadcastDv4_fj(<4 x float> %11, i32 0) #7
+  %13 = shufflevector <4 x float> %12, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x float> %13, <16 x float> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x float> %14, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x float> @_Z31sub_group_non_uniform_broadcastDv8_fj(<8 x float> %15, i32 0) #7
+  %17 = shufflevector <8 x float> %16, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x float> %17, <16 x float> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x float> @_Z31sub_group_non_uniform_broadcastDv16_fj(<16 x float> %18, i32 0) #7
+  %20 = extractelement <16 x float> %19, i64 0
+  %21 = tail call spir_func float @_Z25sub_group_broadcast_firstf(float %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z31sub_group_non_uniform_broadcastfj(float, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x float> @_Z31sub_group_non_uniform_broadcastDv2_fj(<2 x float>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x float> @_Z31sub_group_non_uniform_broadcastDv3_fj(<3 x float>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x float> @_Z31sub_group_non_uniform_broadcastDv4_fj(<4 x float>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x float> @_Z31sub_group_non_uniform_broadcastDv8_fj(<8 x float>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x float> @_Z31sub_group_non_uniform_broadcastDv16_fj(<16 x float>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z25sub_group_broadcast_firstf(float) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[half]] {{[0-9]+}} [[ScopeSubgroup]] [[half_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half2]] [[half2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[half2]] {{[0-9]+}} [[ScopeSubgroup]] [[half2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half3]] [[half3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[half3]] {{[0-9]+}} [[ScopeSubgroup]] [[half3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half4]] [[half4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[half4]] {{[0-9]+}} [[ScopeSubgroup]] [[half4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half8]] [[half8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[half8]] {{[0-9]+}} [[ScopeSubgroup]] [[half8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[half16]] [[half16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[half16]] {{[0-9]+}} [[ScopeSubgroup]] [[half16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[half]] [[half_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[half]] {{[0-9]+}} [[ScopeSubgroup]] [[half_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastHalfs
+; CHECK-LLVM: call spir_func half @_Z31sub_group_non_uniform_broadcastDhj(half {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x half> @_Z31sub_group_non_uniform_broadcastDv2_Dhj(<2 x half> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x half> @_Z31sub_group_non_uniform_broadcastDv3_Dhj(<3 x half> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x half> @_Z31sub_group_non_uniform_broadcastDv4_Dhj(<4 x half> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x half> @_Z31sub_group_non_uniform_broadcastDv8_Dhj(<8 x half> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x half> @_Z31sub_group_non_uniform_broadcastDv16_Dhj(<16 x half> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func half @_Z25sub_group_broadcast_firstDh(half {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastHalfs() local_unnamed_addr #2 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func half @_Z31sub_group_non_uniform_broadcastDhj(half 0xH0000, i32 0) #7
+  %2 = insertelement <16 x half> <half undef, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000>, half %1, i64 0
+  %3 = shufflevector <16 x half> %2, <16 x half> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x half> @_Z31sub_group_non_uniform_broadcastDv2_Dhj(<2 x half> %3, i32 0) #7
+  %5 = shufflevector <2 x half> %4, <2 x half> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x half> %5, <16 x half> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x half> %6, <16 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x half> @_Z31sub_group_non_uniform_broadcastDv3_Dhj(<3 x half> %7, i32 0) #7
+  %9 = shufflevector <3 x half> %8, <3 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x half> %9, <16 x half> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x half> %10, <16 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x half> @_Z31sub_group_non_uniform_broadcastDv4_Dhj(<4 x half> %11, i32 0) #7
+  %13 = shufflevector <4 x half> %12, <4 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x half> %13, <16 x half> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x half> %14, <16 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x half> @_Z31sub_group_non_uniform_broadcastDv8_Dhj(<8 x half> %15, i32 0) #7
+  %17 = shufflevector <8 x half> %16, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x half> %17, <16 x half> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x half> @_Z31sub_group_non_uniform_broadcastDv16_Dhj(<16 x half> %18, i32 0) #7
+  %20 = extractelement <16 x half> %19, i64 0
+  %21 = tail call spir_func half @_Z25sub_group_broadcast_firstDh(half %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z31sub_group_non_uniform_broadcastDhj(half, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x half> @_Z31sub_group_non_uniform_broadcastDv2_Dhj(<2 x half>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x half> @_Z31sub_group_non_uniform_broadcastDv3_Dhj(<3 x half>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x half> @_Z31sub_group_non_uniform_broadcastDv4_Dhj(<4 x half>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x half> @_Z31sub_group_non_uniform_broadcastDv8_Dhj(<8 x half>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x half> @_Z31sub_group_non_uniform_broadcastDv16_Dhj(<16 x half>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z25sub_group_broadcast_firstDh(half) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBroadcast [[double]] {{[0-9]+}} [[ScopeSubgroup]] [[double_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double2]] [[double2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[double2]] {{[0-9]+}} [[ScopeSubgroup]] [[double2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double3]] [[double3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[double3]] {{[0-9]+}} [[ScopeSubgroup]] [[double3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double4]] [[double4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[double4]] {{[0-9]+}} [[ScopeSubgroup]] [[double4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double8]] [[double8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[double8]] {{[0-9]+}} [[ScopeSubgroup]] [[double8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[double16]] [[double16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupNonUniformBroadcast [[double16]] {{[0-9]+}} [[ScopeSubgroup]] [[double16_0]] [[int_0]]
+; CHECK-SPIRV: CompositeExtract [[double]] [[double_value:[0-9]+]]
+; CHECK-SPIRV: GroupNonUniformBroadcastFirst [[double]] {{[0-9]+}} [[ScopeSubgroup]] [[double_value]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBroadcastDoubles
+; CHECK-LLVM: call spir_func double @_Z31sub_group_non_uniform_broadcastdj(double {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x double> @_Z31sub_group_non_uniform_broadcastDv2_dj(<2 x double> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x double> @_Z31sub_group_non_uniform_broadcastDv3_dj(<3 x double> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x double> @_Z31sub_group_non_uniform_broadcastDv4_dj(<4 x double> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x double> @_Z31sub_group_non_uniform_broadcastDv8_dj(<8 x double> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x double> @_Z31sub_group_non_uniform_broadcastDv16_dj(<16 x double> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func double @_Z25sub_group_broadcast_firstd(double {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBroadcastDoubles() local_unnamed_addr #4 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func double @_Z31sub_group_non_uniform_broadcastdj(double 0.000000e+00, i32 0) #7
+  %2 = insertelement <16 x double> <double undef, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, double %1, i64 0
+  %3 = shufflevector <16 x double> %2, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x double> @_Z31sub_group_non_uniform_broadcastDv2_dj(<2 x double> %3, i32 0) #7
+  %5 = shufflevector <2 x double> %4, <2 x double> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x double> %5, <16 x double> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x double> %6, <16 x double> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x double> @_Z31sub_group_non_uniform_broadcastDv3_dj(<3 x double> %7, i32 0) #7
+  %9 = shufflevector <3 x double> %8, <3 x double> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x double> %9, <16 x double> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x double> %10, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x double> @_Z31sub_group_non_uniform_broadcastDv4_dj(<4 x double> %11, i32 0) #7
+  %13 = shufflevector <4 x double> %12, <4 x double> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x double> %13, <16 x double> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x double> %14, <16 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x double> @_Z31sub_group_non_uniform_broadcastDv8_dj(<8 x double> %15, i32 0) #7
+  %17 = shufflevector <8 x double> %16, <8 x double> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x double> %17, <16 x double> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x double> @_Z31sub_group_non_uniform_broadcastDv16_dj(<16 x double> %18, i32 0) #7
+  %20 = extractelement <16 x double> %19, i64 0
+  %21 = tail call spir_func double @_Z25sub_group_broadcast_firstd(double %20) #7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z31sub_group_non_uniform_broadcastdj(double, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x double> @_Z31sub_group_non_uniform_broadcastDv2_dj(<2 x double>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x double> @_Z31sub_group_non_uniform_broadcastDv3_dj(<3 x double>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x double> @_Z31sub_group_non_uniform_broadcastDv4_dj(<4 x double>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x double> @_Z31sub_group_non_uniform_broadcastDv8_dj(<8 x double>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x double> @_Z31sub_group_non_uniform_broadcastDv16_dj(<16 x double>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z25sub_group_broadcast_firstd(double) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBallot [[int4]] [[ballot:[0-9]+]] [[ScopeSubgroup]] [[false]]
+; CHECK-SPIRV: GroupNonUniformInverseBallot [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[ballot]]
+; CHECK-SPIRV: GroupNonUniformBallotBitExtract [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[ballot]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBallotBitCount [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[ballot]]
+; CHECK-SPIRV: GroupNonUniformBallotBitCount [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[ballot]]
+; CHECK-SPIRV: GroupNonUniformBallotBitCount [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[ballot]]
+; CHECK-SPIRV: GroupNonUniformBallotFindLSB [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[ballot]]
+; CHECK-SPIRV: GroupNonUniformBallotFindMSB [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[ballot]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBallotOperations
+; CHECK-LLVM: %[[ballot:[0-9]+]] = call spir_func <4 x i32> @_Z16sub_group_balloti(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z24sub_group_inverse_ballotDv4_j(<4 x i32> %[[ballot]])
+; CHECK-LLVM: call spir_func i32 @_Z28sub_group_ballot_bit_extractDv4_jj(<4 x i32> %[[ballot]], i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z26sub_group_ballot_bit_countDv4_j(<4 x i32> %[[ballot]])
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_ballot_inclusive_scanDv4_j(<4 x i32> %[[ballot]])
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_ballot_exclusive_scanDv4_j(<4 x i32> %[[ballot]])
+; CHECK-LLVM: call spir_func i32 @_Z25sub_group_ballot_find_lsbDv4_j(<4 x i32> %[[ballot]])
+; CHECK-LLVM: call spir_func i32 @_Z25sub_group_ballot_find_msbDv4_j(<4 x i32> %[[ballot]])
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBallotOperations(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !5 !kernel_arg_type !6 !kernel_arg_base_type !6 !kernel_arg_type_qual !7 {
+  %2 = tail call spir_func <4 x i32> @_Z16sub_group_balloti(i32 0) #7
+  %3 = tail call spir_func i32 @_Z24sub_group_inverse_ballotDv4_j(<4 x i32> %2) #8
+  store i32 %3, i32 addrspace(1)* %0, align 4, !tbaa !8
+  %4 = tail call spir_func i32 @_Z28sub_group_ballot_bit_extractDv4_jj(<4 x i32> %2, i32 0) #8
+  %5 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %4, i32 addrspace(1)* %5, align 4, !tbaa !8
+  %6 = tail call spir_func i32 @_Z26sub_group_ballot_bit_countDv4_j(<4 x i32> %2) #8
+  %7 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %6, i32 addrspace(1)* %7, align 4, !tbaa !8
+  %8 = tail call spir_func i32 @_Z31sub_group_ballot_inclusive_scanDv4_j(<4 x i32> %2) #7
+  %9 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 3
+  store i32 %8, i32 addrspace(1)* %9, align 4, !tbaa !8
+  %10 = tail call spir_func i32 @_Z31sub_group_ballot_exclusive_scanDv4_j(<4 x i32> %2) #7
+  %11 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 4
+  store i32 %10, i32 addrspace(1)* %11, align 4, !tbaa !8
+  %12 = tail call spir_func i32 @_Z25sub_group_ballot_find_lsbDv4_j(<4 x i32> %2) #7
+  %13 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 5
+  store i32 %12, i32 addrspace(1)* %13, align 4, !tbaa !8
+  %14 = tail call spir_func i32 @_Z25sub_group_ballot_find_msbDv4_j(<4 x i32> %2) #7
+  %15 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 6
+  store i32 %14, i32 addrspace(1)* %15, align 4, !tbaa !8
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i32> @_Z16sub_group_balloti(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent nounwind readnone
+declare dso_local spir_func i32 @_Z24sub_group_inverse_ballotDv4_j(<4 x i32>) local_unnamed_addr #5
+
+; Function Attrs: convergent nounwind readnone
+declare dso_local spir_func i32 @_Z28sub_group_ballot_bit_extractDv4_jj(<4 x i32>, i32) local_unnamed_addr #5
+
+; Function Attrs: convergent nounwind readnone
+declare dso_local spir_func i32 @_Z26sub_group_ballot_bit_countDv4_j(<4 x i32>) local_unnamed_addr #5
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_ballot_inclusive_scanDv4_j(<4 x i32>) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_ballot_exclusive_scanDv4_j(<4 x i32>) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z25sub_group_ballot_find_lsbDv4_j(<4 x i32>) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z25sub_group_ballot_find_msbDv4_j(<4 x i32>) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: Load [[int4]] {{[0-9]+}} [[eqMask]]
+; CHECK-SPIRV: Load [[int4]] {{[0-9]+}} [[geMask]]
+; CHECK-SPIRV: Load [[int4]] {{[0-9]+}} [[gtMask]]
+; CHECK-SPIRV: Load [[int4]] {{[0-9]+}} [[leMask]]
+; CHECK-SPIRV: Load [[int4]] {{[0-9]+}} [[ltMask]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testSubgroupMasks
+; CHECK-LLVM: call spir_func <4 x i32> @_Z21get_sub_group_eq_maskv()
+; CHECK-LLVM: call spir_func <4 x i32> @_Z21get_sub_group_ge_maskv()
+; CHECK-LLVM: call spir_func <4 x i32> @_Z21get_sub_group_gt_maskv()
+; CHECK-LLVM: call spir_func <4 x i32> @_Z21get_sub_group_le_maskv()
+; CHECK-LLVM: call spir_func <4 x i32> @_Z21get_sub_group_lt_maskv()
+
+; Function Attrs: convergent nofree nounwind writeonly
+define dso_local spir_kernel void @testSubgroupMasks(<4 x i32> addrspace(1)* nocapture) local_unnamed_addr #6 !kernel_arg_addr_space !4 !kernel_arg_access_qual !5 !kernel_arg_type !12 !kernel_arg_base_type !13 !kernel_arg_type_qual !7 {
+  %2 = tail call spir_func <4 x i32> @_Z21get_sub_group_eq_maskv() #8
+  store <4 x i32> %2, <4 x i32> addrspace(1)* %0, align 16, !tbaa !14
+  %3 = tail call spir_func <4 x i32> @_Z21get_sub_group_ge_maskv() #8
+  %4 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %0, i64 1
+  store <4 x i32> %3, <4 x i32> addrspace(1)* %4, align 16, !tbaa !14
+  %5 = tail call spir_func <4 x i32> @_Z21get_sub_group_gt_maskv() #8
+  %6 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %0, i64 2
+  store <4 x i32> %5, <4 x i32> addrspace(1)* %6, align 16, !tbaa !14
+  %7 = tail call spir_func <4 x i32> @_Z21get_sub_group_le_maskv() #8
+  %8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %0, i64 3
+  store <4 x i32> %7, <4 x i32> addrspace(1)* %8, align 16, !tbaa !14
+  %9 = tail call spir_func <4 x i32> @_Z21get_sub_group_lt_maskv() #8
+  %10 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %0, i64 4
+  store <4 x i32> %9, <4 x i32> addrspace(1)* %10, align 16, !tbaa !14
+  ret void
+}
+
+; Function Attrs: convergent nounwind readnone
+declare dso_local spir_func <4 x i32> @_Z21get_sub_group_eq_maskv() local_unnamed_addr #5
+
+; Function Attrs: convergent nounwind readnone
+declare dso_local spir_func <4 x i32> @_Z21get_sub_group_ge_maskv() local_unnamed_addr #5
+
+; Function Attrs: convergent nounwind readnone
+declare dso_local spir_func <4 x i32> @_Z21get_sub_group_gt_maskv() local_unnamed_addr #5
+
+; Function Attrs: convergent nounwind readnone
+declare dso_local spir_func <4 x i32> @_Z21get_sub_group_le_maskv() local_unnamed_addr #5
+
+; Function Attrs: convergent nounwind readnone
+declare dso_local spir_func <4 x i32> @_Z21get_sub_group_lt_maskv() local_unnamed_addr #5
+
+attributes #0 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="256" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="512" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="1024" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { convergent nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #6 = { convergent nofree nounwind writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #7 = { convergent nounwind }
+attributes #8 = { convergent nounwind readnone }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{!"clang version 9.0.1 (https://github.com/llvm/llvm-project.git cb6d58d1dcf36a29ae5dd24ff891d6552f00bac7)"}
+!3 = !{}
+!4 = !{i32 1}
+!5 = !{!"none"}
+!6 = !{!"uint*"}
+!7 = !{!""}
+!8 = !{!9, !9, i64 0}
+!9 = !{!"int", !10, i64 0}
+!10 = !{!"omnipotent char", !11, i64 0}
+!11 = !{!"Simple C/C++ TBAA"}
+!12 = !{!"uint4*"}
+!13 = !{!"uint __attribute__((ext_vector_type(4)))*"}
+!14 = !{!10, !10, i64 0}
diff --git a/llvm-spirv/test/transcoding/sub_group_clustered_reduce.ll b/llvm-spirv/test/transcoding/sub_group_clustered_reduce.ll
new file mode 100644
index 000000000000..ca687768360d
--- /dev/null
+++ b/llvm-spirv/test/transcoding/sub_group_clustered_reduce.ll
@@ -0,0 +1,1000 @@
+;; #pragma OPENCL EXTENSION cl_khr_subgroup_clustered_reduce : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp16 : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp64 : enable
+;; 
+;; kernel void testClusteredArithmeticChar(global char* dst)
+;; {
+;;     char v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticUChar(global uchar* dst)
+;; {
+;;     uchar v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticShort(global short* dst)
+;; {
+;;     short v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticUShort(global ushort* dst)
+;; {
+;;     ushort v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticInt(global int* dst)
+;; {
+;;     int v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticUInt(global uint* dst)
+;; {
+;;     uint v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticLong(global long* dst)
+;; {
+;;     long v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticULong(global ulong* dst)
+;; {
+;;     ulong v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticFloat(global float* dst)
+;; {
+;;     float v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticHalf(global half* dst)
+;; {
+;;     half v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredArithmeticDouble(global double* dst)
+;; {
+;;     double v = 0;
+;;     dst[0] = sub_group_clustered_reduce_add(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_mul(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_min(v, 2);
+;;     dst[3] = sub_group_clustered_reduce_max(v, 2);
+;; }
+;; 
+;; kernel void testClusteredBitwiseChar(global char* dst)
+;; {
+;;     char v = 0;
+;;     dst[0] = sub_group_clustered_reduce_and(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_or(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_xor(v, 2);
+;; }
+;; 
+;; kernel void testClusteredBitwiseUChar(global uchar* dst)
+;; {
+;;     uchar v = 0;
+;;     dst[0] = sub_group_clustered_reduce_and(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_or(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_xor(v, 2);
+;; }
+;; 
+;; kernel void testClusteredBitwiseShort(global short* dst)
+;; {
+;;     short v = 0;
+;;     dst[0] = sub_group_clustered_reduce_and(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_or(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_xor(v, 2);
+;; }
+;; 
+;; kernel void testClusteredBitwiseUShort(global ushort* dst)
+;; {
+;;     ushort v = 0;
+;;     dst[0] = sub_group_clustered_reduce_and(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_or(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_xor(v, 2);
+;; }
+;; 
+;; kernel void testClusteredBitwiseInt(global int* dst)
+;; {
+;;     int v = 0;
+;;     dst[0] = sub_group_clustered_reduce_and(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_or(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_xor(v, 2);
+;; }
+;; 
+;; kernel void testClusteredBitwiseUInt(global uint* dst)
+;; {
+;;     uint v = 0;
+;;     dst[0] = sub_group_clustered_reduce_and(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_or(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_xor(v, 2);
+;; }
+;; 
+;; kernel void testClusteredBitwiseLong(global long* dst)
+;; {
+;;     long v = 0;
+;;     dst[0] = sub_group_clustered_reduce_and(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_or(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_xor(v, 2);
+;; }
+;; 
+;; kernel void testClusteredBitwiseULong(global ulong* dst)
+;; {
+;;     ulong v = 0;
+;;     dst[0] = sub_group_clustered_reduce_and(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_or(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_xor(v, 2);
+;; }
+;; 
+;; kernel void testClusteredLogical(global int* dst)
+;; {
+;;     int v = 0;
+;;     dst[0] = sub_group_clustered_reduce_logical_and(v, 2);
+;;     dst[1] = sub_group_clustered_reduce_logical_or(v, 2);
+;;     dst[2] = sub_group_clustered_reduce_logical_xor(v, 2);
+;; }
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; Change DISABLED to RUN once SPIRV->LLVM translation is implemented
+; DISABLED: llvm-spirv -r %t.spv -o %t.rev.bc
+; DISABLED: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV-DAG: {{[0-9]*}} Capability GroupNonUniformClustered
+
+; CHECK-SPIRV-DAG: TypeBool  [[bool:[0-9]+]]
+; CHECK-SPIRV-DAG: TypeInt   [[char:[0-9]+]]   8  0
+; CHECK-SPIRV-DAG: TypeInt   [[short:[0-9]+]]  16 0
+; CHECK-SPIRV-DAG: TypeInt   [[int:[0-9]+]]    32 0
+; CHECK-SPIRV-DAG: TypeInt   [[long:[0-9]+]]   64 0
+; CHECK-SPIRV-DAG: TypeFloat [[half:[0-9]+]]   16
+; CHECK-SPIRV-DAG: TypeFloat [[float:[0-9]+]]  32
+; CHECK-SPIRV-DAG: TypeFloat [[double:[0-9]+]] 64
+
+; CHECK-SPIRV-DAG: ConstantFalse [[bool]] [[false:[0-9]+]]
+; CHECK-SPIRV-DAG: Constant [[int]]    [[ScopeSubgroup:[0-9]+]] 3
+; CHECK-SPIRV-DAG: Constant [[char]]   [[char_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[short]]  [[short_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[int]]    [[int_0:[0-9]+]]         0
+; CHECK-SPIRV-DAG: Constant [[int]]    [[int_2:[0-9]+]]         2
+; CHECK-SPIRV-DAG: Constant [[long]]   [[long_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[half]]   [[half_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[float]]  [[float_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[double]] [[double_0:[0-9]+]]      0
+
+; ModuleID = 'sub_group_clustered_reduce.cl'
+source_filename = "sub_group_clustered_reduce.cl"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformIMul [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformSMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformSMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticChar
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_addcj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_mulcj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_mincj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_maxcj(i8 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i8 @_Z30sub_group_clustered_reduce_addcj(i8 signext 0, i32 2) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func signext i8 @_Z30sub_group_clustered_reduce_mulcj(i8 signext 0, i32 2) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  %5 = tail call spir_func signext i8 @_Z30sub_group_clustered_reduce_mincj(i8 signext 0, i32 2) #2
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !7
+  %7 = tail call spir_func signext i8 @_Z30sub_group_clustered_reduce_maxcj(i8 signext 0, i32 2) #2
+  %8 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 3
+  store i8 %7, i8 addrspace(1)* %8, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z30sub_group_clustered_reduce_addcj(i8 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z30sub_group_clustered_reduce_mulcj(i8 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z30sub_group_clustered_reduce_mincj(i8 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z30sub_group_clustered_reduce_maxcj(i8 signext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformIMul [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformUMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformUMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticUChar
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_addcj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_mulcj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_minhj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_maxhj(i8 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticUChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i8 @_Z30sub_group_clustered_reduce_addhj(i8 zeroext 0, i32 2) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func zeroext i8 @_Z30sub_group_clustered_reduce_mulhj(i8 zeroext 0, i32 2) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  %5 = tail call spir_func zeroext i8 @_Z30sub_group_clustered_reduce_minhj(i8 zeroext 0, i32 2) #2
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !7
+  %7 = tail call spir_func zeroext i8 @_Z30sub_group_clustered_reduce_maxhj(i8 zeroext 0, i32 2) #2
+  %8 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 3
+  store i8 %7, i8 addrspace(1)* %8, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z30sub_group_clustered_reduce_addhj(i8 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z30sub_group_clustered_reduce_mulhj(i8 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z30sub_group_clustered_reduce_minhj(i8 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z30sub_group_clustered_reduce_maxhj(i8 zeroext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformIMul [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformSMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformSMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticShort
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_addsj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_mulsj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_minsj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_maxsj(i16 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !11 !kernel_arg_base_type !11 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i16 @_Z30sub_group_clustered_reduce_addsj(i16 signext 0, i32 2) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func signext i16 @_Z30sub_group_clustered_reduce_mulsj(i16 signext 0, i32 2) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  %5 = tail call spir_func signext i16 @_Z30sub_group_clustered_reduce_minsj(i16 signext 0, i32 2) #2
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !12
+  %7 = tail call spir_func signext i16 @_Z30sub_group_clustered_reduce_maxsj(i16 signext 0, i32 2) #2
+  %8 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 3
+  store i16 %7, i16 addrspace(1)* %8, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z30sub_group_clustered_reduce_addsj(i16 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z30sub_group_clustered_reduce_mulsj(i16 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z30sub_group_clustered_reduce_minsj(i16 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z30sub_group_clustered_reduce_maxsj(i16 signext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformIMul [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformUMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformUMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticUShort
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_addsj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_mulsj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_mintj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_maxtj(i16 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticUShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i16 @_Z30sub_group_clustered_reduce_addtj(i16 zeroext 0, i32 2) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func zeroext i16 @_Z30sub_group_clustered_reduce_multj(i16 zeroext 0, i32 2) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  %5 = tail call spir_func zeroext i16 @_Z30sub_group_clustered_reduce_mintj(i16 zeroext 0, i32 2) #2
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !12
+  %7 = tail call spir_func zeroext i16 @_Z30sub_group_clustered_reduce_maxtj(i16 zeroext 0, i32 2) #2
+  %8 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 3
+  store i16 %7, i16 addrspace(1)* %8, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z30sub_group_clustered_reduce_addtj(i16 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z30sub_group_clustered_reduce_multj(i16 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z30sub_group_clustered_reduce_mintj(i16 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z30sub_group_clustered_reduce_maxtj(i16 zeroext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformIMul [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformSMin [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformSMax [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticInt
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_addij(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_mulij(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_minij(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_maxij(i32 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_addij(i32 0, i32 2) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_mulij(i32 0, i32 2) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_minij(i32 0, i32 2) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  %7 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_maxij(i32 0, i32 2) #2
+  %8 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 3
+  store i32 %7, i32 addrspace(1)* %8, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_addij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_mulij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_minij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_maxij(i32, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformIMul [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformUMin [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformUMax [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticUInt
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_addij(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_mulij(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_minjj(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_maxjj(i32 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticUInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !18 !kernel_arg_base_type !18 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_addjj(i32 0, i32 2) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_muljj(i32 0, i32 2) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_minjj(i32 0, i32 2) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  %7 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_maxjj(i32 0, i32 2) #2
+  %8 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 3
+  store i32 %7, i32 addrspace(1)* %8, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_addjj(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_muljj(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_minjj(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_maxjj(i32, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformIMul [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformSMin [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformSMax [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticLong
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_addlj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_mullj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_minlj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_maxlj(i64 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticLong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !19 !kernel_arg_base_type !19 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_addlj(i64 0, i32 2) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_mullj(i64 0, i32 2) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  %5 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_minlj(i64 0, i32 2) #2
+  %6 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 2
+  store i64 %5, i64 addrspace(1)* %6, align 8, !tbaa !20
+  %7 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_maxlj(i64 0, i32 2) #2
+  %8 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 3
+  store i64 %7, i64 addrspace(1)* %8, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_addlj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_mullj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_minlj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_maxlj(i64, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformIMul [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformUMin [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformUMax [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticULong
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_addlj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_mullj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_minmj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_maxmj(i64 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticULong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !22 !kernel_arg_base_type !22 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_addmj(i64 0, i32 2) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_mulmj(i64 0, i32 2) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  %5 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_minmj(i64 0, i32 2) #2
+  %6 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 2
+  store i64 %5, i64 addrspace(1)* %6, align 8, !tbaa !20
+  %7 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_maxmj(i64 0, i32 2) #2
+  %8 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 3
+  store i64 %7, i64 addrspace(1)* %8, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_addmj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_mulmj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_minmj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_maxmj(i64, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformFAdd [[float]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[float_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformFMul [[float]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[float_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformFMin [[float]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[float_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformFMax [[float]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[float_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticFloat
+; CHECK-LLVM: call spir_func float @_Z30sub_group_clustered_reduce_addfj(float 0.000000e+00, i32 2)
+; CHECK-LLVM: call spir_func float @_Z30sub_group_clustered_reduce_mulfj(float 0.000000e+00, i32 2)
+; CHECK-LLVM: call spir_func float @_Z30sub_group_clustered_reduce_minfj(float 0.000000e+00, i32 2)
+; CHECK-LLVM: call spir_func float @_Z30sub_group_clustered_reduce_maxfj(float 0.000000e+00, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticFloat(float addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !23 !kernel_arg_base_type !23 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func float @_Z30sub_group_clustered_reduce_addfj(float 0.000000e+00, i32 2) #2
+  store float %2, float addrspace(1)* %0, align 4, !tbaa !24
+  %3 = tail call spir_func float @_Z30sub_group_clustered_reduce_mulfj(float 0.000000e+00, i32 2) #2
+  %4 = getelementptr inbounds float, float addrspace(1)* %0, i64 1
+  store float %3, float addrspace(1)* %4, align 4, !tbaa !24
+  %5 = tail call spir_func float @_Z30sub_group_clustered_reduce_minfj(float 0.000000e+00, i32 2) #2
+  %6 = getelementptr inbounds float, float addrspace(1)* %0, i64 2
+  store float %5, float addrspace(1)* %6, align 4, !tbaa !24
+  %7 = tail call spir_func float @_Z30sub_group_clustered_reduce_maxfj(float 0.000000e+00, i32 2) #2
+  %8 = getelementptr inbounds float, float addrspace(1)* %0, i64 3
+  store float %7, float addrspace(1)* %8, align 4, !tbaa !24
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z30sub_group_clustered_reduce_addfj(float, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z30sub_group_clustered_reduce_mulfj(float, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z30sub_group_clustered_reduce_minfj(float, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z30sub_group_clustered_reduce_maxfj(float, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformFAdd [[half]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[half_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformFMul [[half]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[half_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformFMin [[half]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[half_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformFMax [[half]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[half_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticHalf
+; CHECK-LLVM: call spir_func half @_Z30sub_group_clustered_reduce_addDhj(half 0xH0000, i32 2)
+; CHECK-LLVM: call spir_func half @_Z30sub_group_clustered_reduce_mulDhj(half 0xH0000, i32 2)
+; CHECK-LLVM: call spir_func half @_Z30sub_group_clustered_reduce_minDhj(half 0xH0000, i32 2)
+; CHECK-LLVM: call spir_func half @_Z30sub_group_clustered_reduce_maxDhj(half 0xH0000, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticHalf(half addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !26 !kernel_arg_base_type !26 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func half @_Z30sub_group_clustered_reduce_addDhj(half 0xH0000, i32 2) #2
+  store half %2, half addrspace(1)* %0, align 2, !tbaa !27
+  %3 = tail call spir_func half @_Z30sub_group_clustered_reduce_mulDhj(half 0xH0000, i32 2) #2
+  %4 = getelementptr inbounds half, half addrspace(1)* %0, i64 1
+  store half %3, half addrspace(1)* %4, align 2, !tbaa !27
+  %5 = tail call spir_func half @_Z30sub_group_clustered_reduce_minDhj(half 0xH0000, i32 2) #2
+  %6 = getelementptr inbounds half, half addrspace(1)* %0, i64 2
+  store half %5, half addrspace(1)* %6, align 2, !tbaa !27
+  %7 = tail call spir_func half @_Z30sub_group_clustered_reduce_maxDhj(half 0xH0000, i32 2) #2
+  %8 = getelementptr inbounds half, half addrspace(1)* %0, i64 3
+  store half %7, half addrspace(1)* %8, align 2, !tbaa !27
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z30sub_group_clustered_reduce_addDhj(half, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z30sub_group_clustered_reduce_mulDhj(half, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z30sub_group_clustered_reduce_minDhj(half, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z30sub_group_clustered_reduce_maxDhj(half, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformFAdd [[double]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[double_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformFMul [[double]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[double_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformFMin [[double]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[double_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformFMax [[double]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[double_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredArithmeticDouble
+; CHECK-LLVM: call spir_func double @_Z30sub_group_clustered_reduce_adddj(double 0.000000e+00, i32 2)
+; CHECK-LLVM: call spir_func double @_Z30sub_group_clustered_reduce_muldj(double 0.000000e+00, i32 2)
+; CHECK-LLVM: call spir_func double @_Z30sub_group_clustered_reduce_mindj(double 0.000000e+00, i32 2)
+; CHECK-LLVM: call spir_func double @_Z30sub_group_clustered_reduce_maxdj(double 0.000000e+00, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredArithmeticDouble(double addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !29 !kernel_arg_base_type !29 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func double @_Z30sub_group_clustered_reduce_adddj(double 0.000000e+00, i32 2) #2
+  store double %2, double addrspace(1)* %0, align 8, !tbaa !30
+  %3 = tail call spir_func double @_Z30sub_group_clustered_reduce_muldj(double 0.000000e+00, i32 2) #2
+  %4 = getelementptr inbounds double, double addrspace(1)* %0, i64 1
+  store double %3, double addrspace(1)* %4, align 8, !tbaa !30
+  %5 = tail call spir_func double @_Z30sub_group_clustered_reduce_mindj(double 0.000000e+00, i32 2) #2
+  %6 = getelementptr inbounds double, double addrspace(1)* %0, i64 2
+  store double %5, double addrspace(1)* %6, align 8, !tbaa !30
+  %7 = tail call spir_func double @_Z30sub_group_clustered_reduce_maxdj(double 0.000000e+00, i32 2) #2
+  %8 = getelementptr inbounds double, double addrspace(1)* %0, i64 3
+  store double %7, double addrspace(1)* %8, align 8, !tbaa !30
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z30sub_group_clustered_reduce_adddj(double, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z30sub_group_clustered_reduce_muldj(double, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z30sub_group_clustered_reduce_mindj(double, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z30sub_group_clustered_reduce_maxdj(double, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredBitwiseChar
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_andcj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z29sub_group_clustered_reduce_orcj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_xorcj(i8 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredBitwiseChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i8 @_Z30sub_group_clustered_reduce_andcj(i8 signext 0, i32 2) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func signext i8 @_Z29sub_group_clustered_reduce_orcj(i8 signext 0, i32 2) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  %5 = tail call spir_func signext i8 @_Z30sub_group_clustered_reduce_xorcj(i8 signext 0, i32 2) #2
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z30sub_group_clustered_reduce_andcj(i8 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z29sub_group_clustered_reduce_orcj(i8 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z30sub_group_clustered_reduce_xorcj(i8 signext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[char_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredBitwiseUChar
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_andcj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z29sub_group_clustered_reduce_orcj(i8 0, i32 2)
+; CHECK-LLVM: call spir_func i8 @_Z30sub_group_clustered_reduce_xorcj(i8 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredBitwiseUChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i8 @_Z30sub_group_clustered_reduce_andhj(i8 zeroext 0, i32 2) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func zeroext i8 @_Z29sub_group_clustered_reduce_orhj(i8 zeroext 0, i32 2) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  %5 = tail call spir_func zeroext i8 @_Z30sub_group_clustered_reduce_xorhj(i8 zeroext 0, i32 2) #2
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z30sub_group_clustered_reduce_andhj(i8 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z29sub_group_clustered_reduce_orhj(i8 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z30sub_group_clustered_reduce_xorhj(i8 zeroext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredBitwiseShort
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_andsj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z29sub_group_clustered_reduce_orsj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_xorsj(i16 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredBitwiseShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !11 !kernel_arg_base_type !11 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i16 @_Z30sub_group_clustered_reduce_andsj(i16 signext 0, i32 2) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func signext i16 @_Z29sub_group_clustered_reduce_orsj(i16 signext 0, i32 2) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  %5 = tail call spir_func signext i16 @_Z30sub_group_clustered_reduce_xorsj(i16 signext 0, i32 2) #2
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z30sub_group_clustered_reduce_andsj(i16 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z29sub_group_clustered_reduce_orsj(i16 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z30sub_group_clustered_reduce_xorsj(i16 signext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[short_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredBitwiseUShort
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_andsj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z29sub_group_clustered_reduce_orsj(i16 0, i32 2)
+; CHECK-LLVM: call spir_func i16 @_Z30sub_group_clustered_reduce_xorsj(i16 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredBitwiseUShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i16 @_Z30sub_group_clustered_reduce_andtj(i16 zeroext 0, i32 2) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func zeroext i16 @_Z29sub_group_clustered_reduce_ortj(i16 zeroext 0, i32 2) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  %5 = tail call spir_func zeroext i16 @_Z30sub_group_clustered_reduce_xortj(i16 zeroext 0, i32 2) #2
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z30sub_group_clustered_reduce_andtj(i16 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z29sub_group_clustered_reduce_ortj(i16 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z30sub_group_clustered_reduce_xortj(i16 zeroext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredBitwiseInt
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_andij(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z29sub_group_clustered_reduce_orij(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_xorij(i32 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredBitwiseInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_andij(i32 0, i32 2) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z29sub_group_clustered_reduce_orij(i32 0, i32 2) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_xorij(i32 0, i32 2) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_andij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z29sub_group_clustered_reduce_orij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_xorij(i32, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[int_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredBitwiseUInt
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_andij(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z29sub_group_clustered_reduce_orij(i32 0, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z30sub_group_clustered_reduce_xorij(i32 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredBitwiseUInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !18 !kernel_arg_base_type !18 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_andjj(i32 0, i32 2) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z29sub_group_clustered_reduce_orjj(i32 0, i32 2) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z30sub_group_clustered_reduce_xorjj(i32 0, i32 2) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_andjj(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z29sub_group_clustered_reduce_orjj(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z30sub_group_clustered_reduce_xorjj(i32, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredBitwiseLong
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_andlj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z29sub_group_clustered_reduce_orlj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_xorlj(i64 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredBitwiseLong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !19 !kernel_arg_base_type !19 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_andlj(i64 0, i32 2) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z29sub_group_clustered_reduce_orlj(i64 0, i32 2) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  %5 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_xorlj(i64 0, i32 2) #2
+  %6 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 2
+  store i64 %5, i64 addrspace(1)* %6, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_andlj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z29sub_group_clustered_reduce_orlj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_xorlj(i64, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[long_0]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredBitwiseULong
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_andlj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z29sub_group_clustered_reduce_orlj(i64 0, i32 2)
+; CHECK-LLVM: call spir_func i64 @_Z30sub_group_clustered_reduce_xorlj(i64 0, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredBitwiseULong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !22 !kernel_arg_base_type !22 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_andmj(i64 0, i32 2) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z29sub_group_clustered_reduce_ormj(i64 0, i32 2) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  %5 = tail call spir_func i64 @_Z30sub_group_clustered_reduce_xormj(i64 0, i32 2) #2
+  %6 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 2
+  store i64 %5, i64 addrspace(1)* %6, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_andmj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z29sub_group_clustered_reduce_ormj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z30sub_group_clustered_reduce_xormj(i64, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformLogicalAnd [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[false]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformLogicalOr  [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[false]] [[int_2]]
+; CHECK-SPIRV: GroupNonUniformLogicalXor [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 3 [[false]] [[int_2]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testClusteredLogical
+; CHECK-LLVM: call spir_func i32 @_Z38sub_group_clustered_reduce_logical_andij(i32 {{.*}}, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z37sub_group_clustered_reduce_logical_orij(i32 {{.*}}, i32 2)
+; CHECK-LLVM: call spir_func i32 @_Z38sub_group_clustered_reduce_logical_xorij(i32 {{.*}}, i32 2)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testClusteredLogical(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z38sub_group_clustered_reduce_logical_andij(i32 0, i32 2) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z37sub_group_clustered_reduce_logical_orij(i32 0, i32 2) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z38sub_group_clustered_reduce_logical_xorij(i32 0, i32 2) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z38sub_group_clustered_reduce_logical_andij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z37sub_group_clustered_reduce_logical_orij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z38sub_group_clustered_reduce_logical_xorij(i32, i32) local_unnamed_addr #1
+
+attributes #0 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { convergent nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{!"clang version 9.0.1 (https://github.com/llvm/llvm-project.git cb6d58d1dcf36a29ae5dd24ff891d6552f00bac7)"}
+!3 = !{i32 1}
+!4 = !{!"none"}
+!5 = !{!"char*"}
+!6 = !{!""}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"omnipotent char", !9, i64 0}
+!9 = !{!"Simple C/C++ TBAA"}
+!10 = !{!"uchar*"}
+!11 = !{!"short*"}
+!12 = !{!13, !13, i64 0}
+!13 = !{!"short", !8, i64 0}
+!14 = !{!"ushort*"}
+!15 = !{!"int*"}
+!16 = !{!17, !17, i64 0}
+!17 = !{!"int", !8, i64 0}
+!18 = !{!"uint*"}
+!19 = !{!"long*"}
+!20 = !{!21, !21, i64 0}
+!21 = !{!"long", !8, i64 0}
+!22 = !{!"ulong*"}
+!23 = !{!"float*"}
+!24 = !{!25, !25, i64 0}
+!25 = !{!"float", !8, i64 0}
+!26 = !{!"half*"}
+!27 = !{!28, !28, i64 0}
+!28 = !{!"half", !8, i64 0}
+!29 = !{!"double*"}
+!30 = !{!31, !31, i64 0}
+!31 = !{!"double", !8, i64 0}
diff --git a/llvm-spirv/test/transcoding/sub_group_extended_types.ll b/llvm-spirv/test/transcoding/sub_group_extended_types.ll
new file mode 100644
index 000000000000..6f8dcc0331fb
--- /dev/null
+++ b/llvm-spirv/test/transcoding/sub_group_extended_types.ll
@@ -0,0 +1,1322 @@
+;; #pragma OPENCL EXTENSION cl_khr_subgroup_extended_types : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp16 : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp64 : enable
+;; 
+;; kernel void testBroadcastChar()
+;; {
+;;     char16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastUChar()
+;; {
+;;     uchar16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastShort()
+;; {
+;;     short16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastUShort()
+;; {
+;;     ushort16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastInt()
+;; {
+;;     int16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastUInt()
+;; {
+;;     uint16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastLong()
+;; {
+;;     long16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastULong()
+;; {
+;;     ulong16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastFloat()
+;; {
+;;     float16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastHalf()
+;; {
+;;     half16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testBroadcastDouble()
+;; {
+;;     double16 v = 0;
+;;     v.s0 = sub_group_broadcast(v.s0, 0);
+;;     v.s01 = sub_group_broadcast(v.s01, 0);
+;;     v.s012 = sub_group_broadcast(v.s012, 0);
+;;     v.s0123 = sub_group_broadcast(v.s0123, 0);
+;;     v.s01234567 = sub_group_broadcast(v.s01234567, 0);
+;;     v = sub_group_broadcast(v, 0);
+;; }
+;; 
+;; kernel void testReduceScanChar(global char* dst)
+;; {
+;;     char v = 0;
+;;     dst[0] = sub_group_reduce_add(v);
+;;     dst[1] = sub_group_reduce_min(v);
+;;     dst[2] = sub_group_reduce_max(v);
+;;     dst[3] = sub_group_scan_inclusive_add(v);
+;;     dst[4] = sub_group_scan_inclusive_min(v);
+;;     dst[5] = sub_group_scan_inclusive_max(v);
+;;     dst[6] = sub_group_scan_exclusive_add(v);
+;;     dst[7] = sub_group_scan_exclusive_min(v);
+;;     dst[8] = sub_group_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testReduceScanUChar(global uchar* dst)
+;; {
+;;     uchar v = 0;
+;;     dst[0] = sub_group_reduce_add(v);
+;;     dst[1] = sub_group_reduce_min(v);
+;;     dst[2] = sub_group_reduce_max(v);
+;;     dst[3] = sub_group_scan_inclusive_add(v);
+;;     dst[4] = sub_group_scan_inclusive_min(v);
+;;     dst[5] = sub_group_scan_inclusive_max(v);
+;;     dst[6] = sub_group_scan_exclusive_add(v);
+;;     dst[7] = sub_group_scan_exclusive_min(v);
+;;     dst[8] = sub_group_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testReduceScanShort(global short* dst)
+;; {
+;;     short v = 0;
+;;     dst[0] = sub_group_reduce_add(v);
+;;     dst[1] = sub_group_reduce_min(v);
+;;     dst[2] = sub_group_reduce_max(v);
+;;     dst[3] = sub_group_scan_inclusive_add(v);
+;;     dst[4] = sub_group_scan_inclusive_min(v);
+;;     dst[5] = sub_group_scan_inclusive_max(v);
+;;     dst[6] = sub_group_scan_exclusive_add(v);
+;;     dst[7] = sub_group_scan_exclusive_min(v);
+;;     dst[8] = sub_group_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testReduceScanUShort(global ushort* dst)
+;; {
+;;     ushort v = 0;
+;;     dst[0] = sub_group_reduce_add(v);
+;;     dst[1] = sub_group_reduce_min(v);
+;;     dst[2] = sub_group_reduce_max(v);
+;;     dst[3] = sub_group_scan_inclusive_add(v);
+;;     dst[4] = sub_group_scan_inclusive_min(v);
+;;     dst[5] = sub_group_scan_inclusive_max(v);
+;;     dst[6] = sub_group_scan_exclusive_add(v);
+;;     dst[7] = sub_group_scan_exclusive_min(v);
+;;     dst[8] = sub_group_scan_exclusive_max(v);
+;; }
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; Change DISABLED to RUN once SPIRV->LLVM translation is implemented
+; DISABLED: llvm-spirv -r %t.spv -o %t.rev.bc
+; DISABLED: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV-DAG: TypeInt   [[char:[0-9]+]]   8  0
+; CHECK-SPIRV-DAG: TypeInt   [[short:[0-9]+]]  16 0
+; CHECK-SPIRV-DAG: TypeInt   [[int:[0-9]+]]    32 0
+; CHECK-SPIRV-DAG: TypeInt   [[long:[0-9]+]]   64 0
+; CHECK-SPIRV-DAG: TypeFloat [[half:[0-9]+]]   16
+; CHECK-SPIRV-DAG: TypeFloat [[float:[0-9]+]]  32
+; CHECK-SPIRV-DAG: TypeFloat [[double:[0-9]+]] 64
+
+; CHECK-SPIRV-DAG: TypeVector [[char2:[0-9]+]]  [[char]] 2
+; CHECK-SPIRV-DAG: TypeVector [[char3:[0-9]+]]  [[char]] 3
+; CHECK-SPIRV-DAG: TypeVector [[char4:[0-9]+]]  [[char]] 4
+; CHECK-SPIRV-DAG: TypeVector [[char8:[0-9]+]]  [[char]] 8
+; CHECK-SPIRV-DAG: TypeVector [[char16:[0-9]+]] [[char]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[short2:[0-9]+]]  [[short]] 2
+; CHECK-SPIRV-DAG: TypeVector [[short3:[0-9]+]]  [[short]] 3
+; CHECK-SPIRV-DAG: TypeVector [[short4:[0-9]+]]  [[short]] 4
+; CHECK-SPIRV-DAG: TypeVector [[short8:[0-9]+]]  [[short]] 8
+; CHECK-SPIRV-DAG: TypeVector [[short16:[0-9]+]] [[short]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[int2:[0-9]+]]  [[int]] 2
+; CHECK-SPIRV-DAG: TypeVector [[int3:[0-9]+]]  [[int]] 3
+; CHECK-SPIRV-DAG: TypeVector [[int4:[0-9]+]]  [[int]] 4
+; CHECK-SPIRV-DAG: TypeVector [[int8:[0-9]+]]  [[int]] 8
+; CHECK-SPIRV-DAG: TypeVector [[int16:[0-9]+]] [[int]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[long2:[0-9]+]]  [[long]] 2
+; CHECK-SPIRV-DAG: TypeVector [[long3:[0-9]+]]  [[long]] 3
+; CHECK-SPIRV-DAG: TypeVector [[long4:[0-9]+]]  [[long]] 4
+; CHECK-SPIRV-DAG: TypeVector [[long8:[0-9]+]]  [[long]] 8
+; CHECK-SPIRV-DAG: TypeVector [[long16:[0-9]+]] [[long]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[float2:[0-9]+]]  [[float]] 2
+; CHECK-SPIRV-DAG: TypeVector [[float3:[0-9]+]]  [[float]] 3
+; CHECK-SPIRV-DAG: TypeVector [[float4:[0-9]+]]  [[float]] 4
+; CHECK-SPIRV-DAG: TypeVector [[float8:[0-9]+]]  [[float]] 8
+; CHECK-SPIRV-DAG: TypeVector [[float16:[0-9]+]] [[float]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[half2:[0-9]+]]  [[half]] 2
+; CHECK-SPIRV-DAG: TypeVector [[half3:[0-9]+]]  [[half]] 3
+; CHECK-SPIRV-DAG: TypeVector [[half4:[0-9]+]]  [[half]] 4
+; CHECK-SPIRV-DAG: TypeVector [[half8:[0-9]+]]  [[half]] 8
+; CHECK-SPIRV-DAG: TypeVector [[half16:[0-9]+]] [[half]] 16
+
+; CHECK-SPIRV-DAG: TypeVector [[double2:[0-9]+]]  [[double]] 2
+; CHECK-SPIRV-DAG: TypeVector [[double3:[0-9]+]]  [[double]] 3
+; CHECK-SPIRV-DAG: TypeVector [[double4:[0-9]+]]  [[double]] 4
+; CHECK-SPIRV-DAG: TypeVector [[double8:[0-9]+]]  [[double]] 8
+; CHECK-SPIRV-DAG: TypeVector [[double16:[0-9]+]] [[double]] 16
+
+; CHECK-SPIRV-DAG: Constant [[int]]    [[ScopeSubgroup:[0-9]+]] 3
+; CHECK-SPIRV-DAG: Constant [[char]]   [[char_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[short]]  [[short_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[int]]    [[int_0:[0-9]+]]         0
+; CHECK-SPIRV-DAG: Constant [[long]]   [[long_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[half]]   [[half_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[float]]  [[float_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[double]] [[double_0:[0-9]+]]      0
+
+; ModuleID = 'sub_group_extended_types.cl'
+source_filename = "sub_group_extended_types.cl"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char2]] [[char2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char2]] {{[0-9]+}} [[ScopeSubgroup]] [[char2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char3]] [[char3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char3]] {{[0-9]+}} [[ScopeSubgroup]] [[char3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char4]] [[char4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char4]] {{[0-9]+}} [[ScopeSubgroup]] [[char4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char8]] [[char8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char8]] {{[0-9]+}} [[ScopeSubgroup]] [[char8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[char16]] [[char16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char16]] {{[0-9]+}} [[ScopeSubgroup]] [[char16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastChar
+; CHECK-LLVM: call spir_func i8 @_Z19sub_group_broadcasthj(i8 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i8> @_Z19sub_group_broadcastDv2_hj(<2 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i8> @_Z19sub_group_broadcastDv3_hj(<3 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i8> @_Z19sub_group_broadcastDv4_hj(<4 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i8> @_Z19sub_group_broadcastDv8_hj(<8 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i8> @_Z19sub_group_broadcastDv16_hj(<16 x i8> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastChar() local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func signext i8 @_Z19sub_group_broadcastcj(i8 signext 0, i32 0) #6
+  %2 = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %1, i64 0
+  %3 = shufflevector <16 x i8> %2, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i8> @_Z19sub_group_broadcastDv2_cj(<2 x i8> %3, i32 0) #6
+  %5 = shufflevector <2 x i8> %4, <2 x i8> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i8> %5, <16 x i8> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i8> %6, <16 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i8> @_Z19sub_group_broadcastDv3_cj(<3 x i8> %7, i32 0) #6
+  %9 = shufflevector <3 x i8> %8, <3 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i8> %9, <16 x i8> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i8> %10, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i8> @_Z19sub_group_broadcastDv4_cj(<4 x i8> %11, i32 0) #6
+  %13 = shufflevector <4 x i8> %12, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i8> %13, <16 x i8> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i8> %14, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i8> @_Z19sub_group_broadcastDv8_cj(<8 x i8> %15, i32 0) #6
+  %17 = shufflevector <8 x i8> %16, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i8> %17, <16 x i8> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i8> @_Z19sub_group_broadcastDv16_cj(<16 x i8> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z19sub_group_broadcastcj(i8 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i8> @_Z19sub_group_broadcastDv2_cj(<2 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i8> @_Z19sub_group_broadcastDv3_cj(<3 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i8> @_Z19sub_group_broadcastDv4_cj(<4 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i8> @_Z19sub_group_broadcastDv8_cj(<8 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i8> @_Z19sub_group_broadcastDv16_cj(<16 x i8>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char2]] [[char2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char2]] {{[0-9]+}} [[ScopeSubgroup]] [[char2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char3]] [[char3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char3]] {{[0-9]+}} [[ScopeSubgroup]] [[char3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char4]] [[char4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char4]] {{[0-9]+}} [[ScopeSubgroup]] [[char4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char8]] [[char8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char8]] {{[0-9]+}} [[ScopeSubgroup]] [[char8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[char16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[char16]] [[char16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[char16]] {{[0-9]+}} [[ScopeSubgroup]] [[char16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastUChar
+; CHECK-LLVM: call spir_func i8 @_Z19sub_group_broadcasthj(i8 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i8> @_Z19sub_group_broadcastDv2_hj(<2 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i8> @_Z19sub_group_broadcastDv3_hj(<3 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i8> @_Z19sub_group_broadcastDv4_hj(<4 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i8> @_Z19sub_group_broadcastDv8_hj(<8 x i8> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i8> @_Z19sub_group_broadcastDv16_hj(<16 x i8> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastUChar() local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func zeroext i8 @_Z19sub_group_broadcasthj(i8 zeroext 0, i32 0) #6
+  %2 = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %1, i64 0
+  %3 = shufflevector <16 x i8> %2, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i8> @_Z19sub_group_broadcastDv2_hj(<2 x i8> %3, i32 0) #6
+  %5 = shufflevector <2 x i8> %4, <2 x i8> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i8> %5, <16 x i8> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i8> %6, <16 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i8> @_Z19sub_group_broadcastDv3_hj(<3 x i8> %7, i32 0) #6
+  %9 = shufflevector <3 x i8> %8, <3 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i8> %9, <16 x i8> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i8> %10, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i8> @_Z19sub_group_broadcastDv4_hj(<4 x i8> %11, i32 0) #6
+  %13 = shufflevector <4 x i8> %12, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i8> %13, <16 x i8> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i8> %14, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i8> @_Z19sub_group_broadcastDv8_hj(<8 x i8> %15, i32 0) #6
+  %17 = shufflevector <8 x i8> %16, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i8> %17, <16 x i8> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i8> @_Z19sub_group_broadcastDv16_hj(<16 x i8> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z19sub_group_broadcasthj(i8 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i8> @_Z19sub_group_broadcastDv2_hj(<2 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i8> @_Z19sub_group_broadcastDv3_hj(<3 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i8> @_Z19sub_group_broadcastDv4_hj(<4 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i8> @_Z19sub_group_broadcastDv8_hj(<8 x i8>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i8> @_Z19sub_group_broadcastDv16_hj(<16 x i8>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short2]] [[short2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short2]] {{[0-9]+}} [[ScopeSubgroup]] [[short2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short3]] [[short3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short3]] {{[0-9]+}} [[ScopeSubgroup]] [[short3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short4]] [[short4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short4]] {{[0-9]+}} [[ScopeSubgroup]] [[short4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short8]] [[short8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short8]] {{[0-9]+}} [[ScopeSubgroup]] [[short8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[short16]] [[short16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short16]] {{[0-9]+}} [[ScopeSubgroup]] [[short16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastShort
+; CHECK-LLVM: call spir_func i16 @_Z19sub_group_broadcasttj(i16 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i16> @_Z19sub_group_broadcastDv2_tj(<2 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i16> @_Z19sub_group_broadcastDv3_tj(<3 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i16> @_Z19sub_group_broadcastDv4_tj(<4 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i16> @_Z19sub_group_broadcastDv8_tj(<8 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i16> @_Z19sub_group_broadcastDv16_tj(<16 x i16> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastShort() local_unnamed_addr #2 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func signext i16 @_Z19sub_group_broadcastsj(i16 signext 0, i32 0) #6
+  %2 = insertelement <16 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 %1, i64 0
+  %3 = shufflevector <16 x i16> %2, <16 x i16> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i16> @_Z19sub_group_broadcastDv2_sj(<2 x i16> %3, i32 0) #6
+  %5 = shufflevector <2 x i16> %4, <2 x i16> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i16> %5, <16 x i16> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i16> %6, <16 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i16> @_Z19sub_group_broadcastDv3_sj(<3 x i16> %7, i32 0) #6
+  %9 = shufflevector <3 x i16> %8, <3 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i16> %9, <16 x i16> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i16> %10, <16 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i16> @_Z19sub_group_broadcastDv4_sj(<4 x i16> %11, i32 0) #6
+  %13 = shufflevector <4 x i16> %12, <4 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i16> %13, <16 x i16> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i16> %14, <16 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i16> @_Z19sub_group_broadcastDv8_sj(<8 x i16> %15, i32 0) #6
+  %17 = shufflevector <8 x i16> %16, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i16> %17, <16 x i16> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i16> @_Z19sub_group_broadcastDv16_sj(<16 x i16> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z19sub_group_broadcastsj(i16 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i16> @_Z19sub_group_broadcastDv2_sj(<2 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i16> @_Z19sub_group_broadcastDv3_sj(<3 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i16> @_Z19sub_group_broadcastDv4_sj(<4 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i16> @_Z19sub_group_broadcastDv8_sj(<8 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i16> @_Z19sub_group_broadcastDv16_sj(<16 x i16>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short2]] [[short2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short2]] {{[0-9]+}} [[ScopeSubgroup]] [[short2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short3]] [[short3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short3]] {{[0-9]+}} [[ScopeSubgroup]] [[short3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short4]] [[short4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short4]] {{[0-9]+}} [[ScopeSubgroup]] [[short4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short8]] [[short8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short8]] {{[0-9]+}} [[ScopeSubgroup]] [[short8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[short16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[short16]] [[short16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[short16]] {{[0-9]+}} [[ScopeSubgroup]] [[short16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastUShort
+; CHECK-LLVM: call spir_func i16 @_Z19sub_group_broadcasttj(i16 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i16> @_Z19sub_group_broadcastDv2_tj(<2 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i16> @_Z19sub_group_broadcastDv3_tj(<3 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i16> @_Z19sub_group_broadcastDv4_tj(<4 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i16> @_Z19sub_group_broadcastDv8_tj(<8 x i16> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i16> @_Z19sub_group_broadcastDv16_tj(<16 x i16> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastUShort() local_unnamed_addr #2 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func zeroext i16 @_Z19sub_group_broadcasttj(i16 zeroext 0, i32 0) #6
+  %2 = insertelement <16 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 %1, i64 0
+  %3 = shufflevector <16 x i16> %2, <16 x i16> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i16> @_Z19sub_group_broadcastDv2_tj(<2 x i16> %3, i32 0) #6
+  %5 = shufflevector <2 x i16> %4, <2 x i16> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i16> %5, <16 x i16> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i16> %6, <16 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i16> @_Z19sub_group_broadcastDv3_tj(<3 x i16> %7, i32 0) #6
+  %9 = shufflevector <3 x i16> %8, <3 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i16> %9, <16 x i16> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i16> %10, <16 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i16> @_Z19sub_group_broadcastDv4_tj(<4 x i16> %11, i32 0) #6
+  %13 = shufflevector <4 x i16> %12, <4 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i16> %13, <16 x i16> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i16> %14, <16 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i16> @_Z19sub_group_broadcastDv8_tj(<8 x i16> %15, i32 0) #6
+  %17 = shufflevector <8 x i16> %16, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i16> %17, <16 x i16> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i16> @_Z19sub_group_broadcastDv16_tj(<16 x i16> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z19sub_group_broadcasttj(i16 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i16> @_Z19sub_group_broadcastDv2_tj(<2 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i16> @_Z19sub_group_broadcastDv3_tj(<3 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i16> @_Z19sub_group_broadcastDv4_tj(<4 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i16> @_Z19sub_group_broadcastDv8_tj(<8 x i16>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i16> @_Z19sub_group_broadcastDv16_tj(<16 x i16>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int2]] [[int2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int2]] {{[0-9]+}} [[ScopeSubgroup]] [[int2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int3]] [[int3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int3]] {{[0-9]+}} [[ScopeSubgroup]] [[int3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int4]] [[int4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int4]] {{[0-9]+}} [[ScopeSubgroup]] [[int4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int8]] [[int8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int8]] {{[0-9]+}} [[ScopeSubgroup]] [[int8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[int16]] [[int16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int16]] {{[0-9]+}} [[ScopeSubgroup]] [[int16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastInt
+; CHECK-LLVM: call spir_func i32 @_Z19sub_group_broadcastjj(i32 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i32> @_Z19sub_group_broadcastDv2_jj(<2 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i32> @_Z19sub_group_broadcastDv3_jj(<3 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i32> @_Z19sub_group_broadcastDv4_jj(<4 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i32> @_Z19sub_group_broadcastDv8_jj(<8 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i32> @_Z19sub_group_broadcastDv16_jj(<16 x i32> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastInt() local_unnamed_addr #3 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func i32 @_Z19sub_group_broadcastij(i32 0, i32 0) #6
+  %2 = insertelement <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 %1, i64 0
+  %3 = shufflevector <16 x i32> %2, <16 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i32> @_Z19sub_group_broadcastDv2_ij(<2 x i32> %3, i32 0) #6
+  %5 = shufflevector <2 x i32> %4, <2 x i32> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i32> %5, <16 x i32> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i32> %6, <16 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i32> @_Z19sub_group_broadcastDv3_ij(<3 x i32> %7, i32 0) #6
+  %9 = shufflevector <3 x i32> %8, <3 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i32> %9, <16 x i32> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i32> %10, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i32> @_Z19sub_group_broadcastDv4_ij(<4 x i32> %11, i32 0) #6
+  %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i32> %13, <16 x i32> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i32> %14, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i32> @_Z19sub_group_broadcastDv8_ij(<8 x i32> %15, i32 0) #6
+  %17 = shufflevector <8 x i32> %16, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i32> %17, <16 x i32> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i32> @_Z19sub_group_broadcastDv16_ij(<16 x i32> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z19sub_group_broadcastij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i32> @_Z19sub_group_broadcastDv2_ij(<2 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i32> @_Z19sub_group_broadcastDv3_ij(<3 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i32> @_Z19sub_group_broadcastDv4_ij(<4 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i32> @_Z19sub_group_broadcastDv8_ij(<8 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i32> @_Z19sub_group_broadcastDv16_ij(<16 x i32>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int2]] [[int2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int2]] {{[0-9]+}} [[ScopeSubgroup]] [[int2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int3]] [[int3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int3]] {{[0-9]+}} [[ScopeSubgroup]] [[int3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int4]] [[int4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int4]] {{[0-9]+}} [[ScopeSubgroup]] [[int4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int8]] [[int8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int8]] {{[0-9]+}} [[ScopeSubgroup]] [[int8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[int16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[int16]] [[int16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[int16]] {{[0-9]+}} [[ScopeSubgroup]] [[int16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastUInt
+; CHECK-LLVM: call spir_func i32 @_Z19sub_group_broadcastjj(i32 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i32> @_Z19sub_group_broadcastDv2_jj(<2 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i32> @_Z19sub_group_broadcastDv3_jj(<3 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i32> @_Z19sub_group_broadcastDv4_jj(<4 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i32> @_Z19sub_group_broadcastDv8_jj(<8 x i32> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i32> @_Z19sub_group_broadcastDv16_jj(<16 x i32> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastUInt() local_unnamed_addr #3 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func i32 @_Z19sub_group_broadcastjj(i32 0, i32 0) #6
+  %2 = insertelement <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 %1, i64 0
+  %3 = shufflevector <16 x i32> %2, <16 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i32> @_Z19sub_group_broadcastDv2_jj(<2 x i32> %3, i32 0) #6
+  %5 = shufflevector <2 x i32> %4, <2 x i32> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i32> %5, <16 x i32> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i32> %6, <16 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i32> @_Z19sub_group_broadcastDv3_jj(<3 x i32> %7, i32 0) #6
+  %9 = shufflevector <3 x i32> %8, <3 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i32> %9, <16 x i32> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i32> %10, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i32> @_Z19sub_group_broadcastDv4_jj(<4 x i32> %11, i32 0) #6
+  %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i32> %13, <16 x i32> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i32> %14, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i32> @_Z19sub_group_broadcastDv8_jj(<8 x i32> %15, i32 0) #6
+  %17 = shufflevector <8 x i32> %16, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i32> %17, <16 x i32> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i32> @_Z19sub_group_broadcastDv16_jj(<16 x i32> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z19sub_group_broadcastjj(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i32> @_Z19sub_group_broadcastDv2_jj(<2 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i32> @_Z19sub_group_broadcastDv3_jj(<3 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i32> @_Z19sub_group_broadcastDv4_jj(<4 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i32> @_Z19sub_group_broadcastDv8_jj(<8 x i32>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i32> @_Z19sub_group_broadcastDv16_jj(<16 x i32>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long2]] [[long2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long2]] {{[0-9]+}} [[ScopeSubgroup]] [[long2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long3]] [[long3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long3]] {{[0-9]+}} [[ScopeSubgroup]] [[long3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long4]] [[long4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long4]] {{[0-9]+}} [[ScopeSubgroup]] [[long4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long8]] [[long8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long8]] {{[0-9]+}} [[ScopeSubgroup]] [[long8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[long16]] [[long16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long16]] {{[0-9]+}} [[ScopeSubgroup]] [[long16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastLong
+; CHECK-LLVM: call spir_func i64 @_Z19sub_group_broadcastmj(i64 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i64> @_Z19sub_group_broadcastDv2_mj(<2 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i64> @_Z19sub_group_broadcastDv3_mj(<3 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i64> @_Z19sub_group_broadcastDv4_mj(<4 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i64> @_Z19sub_group_broadcastDv8_mj(<8 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i64> @_Z19sub_group_broadcastDv16_mj(<16 x i64> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastLong() local_unnamed_addr #4 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func i64 @_Z19sub_group_broadcastlj(i64 0, i32 0) #6
+  %2 = insertelement <16 x i64> <i64 undef, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 %1, i64 0
+  %3 = shufflevector <16 x i64> %2, <16 x i64> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i64> @_Z19sub_group_broadcastDv2_lj(<2 x i64> %3, i32 0) #6
+  %5 = shufflevector <2 x i64> %4, <2 x i64> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i64> %5, <16 x i64> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i64> %6, <16 x i64> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i64> @_Z19sub_group_broadcastDv3_lj(<3 x i64> %7, i32 0) #6
+  %9 = shufflevector <3 x i64> %8, <3 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i64> %9, <16 x i64> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i64> %10, <16 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i64> @_Z19sub_group_broadcastDv4_lj(<4 x i64> %11, i32 0) #6
+  %13 = shufflevector <4 x i64> %12, <4 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i64> %13, <16 x i64> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i64> %14, <16 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i64> @_Z19sub_group_broadcastDv8_lj(<8 x i64> %15, i32 0) #6
+  %17 = shufflevector <8 x i64> %16, <8 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i64> %17, <16 x i64> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i64> @_Z19sub_group_broadcastDv16_lj(<16 x i64> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z19sub_group_broadcastlj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i64> @_Z19sub_group_broadcastDv2_lj(<2 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i64> @_Z19sub_group_broadcastDv3_lj(<3 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i64> @_Z19sub_group_broadcastDv4_lj(<4 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i64> @_Z19sub_group_broadcastDv8_lj(<8 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i64> @_Z19sub_group_broadcastDv16_lj(<16 x i64>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long2]] [[long2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long2]] {{[0-9]+}} [[ScopeSubgroup]] [[long2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long3]] [[long3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long3]] {{[0-9]+}} [[ScopeSubgroup]] [[long3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long4]] [[long4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long4]] {{[0-9]+}} [[ScopeSubgroup]] [[long4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long8]] [[long8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long8]] {{[0-9]+}} [[ScopeSubgroup]] [[long8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[long16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[long16]] [[long16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[long16]] {{[0-9]+}} [[ScopeSubgroup]] [[long16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastULong
+; CHECK-LLVM: call spir_func i64 @_Z19sub_group_broadcastmj(i64 {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x i64> @_Z19sub_group_broadcastDv2_mj(<2 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x i64> @_Z19sub_group_broadcastDv3_mj(<3 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x i64> @_Z19sub_group_broadcastDv4_mj(<4 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x i64> @_Z19sub_group_broadcastDv8_mj(<8 x i64> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x i64> @_Z19sub_group_broadcastDv16_mj(<16 x i64> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastULong() local_unnamed_addr #4 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func i64 @_Z19sub_group_broadcastmj(i64 0, i32 0) #6
+  %2 = insertelement <16 x i64> <i64 undef, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 %1, i64 0
+  %3 = shufflevector <16 x i64> %2, <16 x i64> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x i64> @_Z19sub_group_broadcastDv2_mj(<2 x i64> %3, i32 0) #6
+  %5 = shufflevector <2 x i64> %4, <2 x i64> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x i64> %5, <16 x i64> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x i64> %6, <16 x i64> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x i64> @_Z19sub_group_broadcastDv3_mj(<3 x i64> %7, i32 0) #6
+  %9 = shufflevector <3 x i64> %8, <3 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x i64> %9, <16 x i64> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x i64> %10, <16 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x i64> @_Z19sub_group_broadcastDv4_mj(<4 x i64> %11, i32 0) #6
+  %13 = shufflevector <4 x i64> %12, <4 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x i64> %13, <16 x i64> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x i64> %14, <16 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x i64> @_Z19sub_group_broadcastDv8_mj(<8 x i64> %15, i32 0) #6
+  %17 = shufflevector <8 x i64> %16, <8 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x i64> %17, <16 x i64> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x i64> @_Z19sub_group_broadcastDv16_mj(<16 x i64> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z19sub_group_broadcastmj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x i64> @_Z19sub_group_broadcastDv2_mj(<2 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x i64> @_Z19sub_group_broadcastDv3_mj(<3 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x i64> @_Z19sub_group_broadcastDv4_mj(<4 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x i64> @_Z19sub_group_broadcastDv8_mj(<8 x i64>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x i64> @_Z19sub_group_broadcastDv16_mj(<16 x i64>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[float]] {{[0-9]+}} [[ScopeSubgroup]] [[float_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float2]] [[float2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[float2]] {{[0-9]+}} [[ScopeSubgroup]] [[float2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float3]] [[float3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[float3]] {{[0-9]+}} [[ScopeSubgroup]] [[float3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float4]] [[float4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[float4]] {{[0-9]+}} [[ScopeSubgroup]] [[float4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float8]] [[float8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[float8]] {{[0-9]+}} [[ScopeSubgroup]] [[float8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[float16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[float16]] [[float16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[float16]] {{[0-9]+}} [[ScopeSubgroup]] [[float16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastFloat
+; CHECK-LLVM: call spir_func float @_Z19sub_group_broadcastfj(float {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x float> @_Z19sub_group_broadcastDv2_fj(<2 x float> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x float> @_Z19sub_group_broadcastDv3_fj(<3 x float> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x float> @_Z19sub_group_broadcastDv4_fj(<4 x float> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x float> @_Z19sub_group_broadcastDv8_fj(<8 x float> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x float> @_Z19sub_group_broadcastDv16_fj(<16 x float> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastFloat() local_unnamed_addr #3 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func float @_Z19sub_group_broadcastfj(float 0.000000e+00, i32 0) #6
+  %2 = insertelement <16 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %1, i64 0
+  %3 = shufflevector <16 x float> %2, <16 x float> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x float> @_Z19sub_group_broadcastDv2_fj(<2 x float> %3, i32 0) #6
+  %5 = shufflevector <2 x float> %4, <2 x float> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x float> %5, <16 x float> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x float> %6, <16 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x float> @_Z19sub_group_broadcastDv3_fj(<3 x float> %7, i32 0) #6
+  %9 = shufflevector <3 x float> %8, <3 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x float> %9, <16 x float> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x float> %10, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x float> @_Z19sub_group_broadcastDv4_fj(<4 x float> %11, i32 0) #6
+  %13 = shufflevector <4 x float> %12, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x float> %13, <16 x float> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x float> %14, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x float> @_Z19sub_group_broadcastDv8_fj(<8 x float> %15, i32 0) #6
+  %17 = shufflevector <8 x float> %16, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x float> %17, <16 x float> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x float> @_Z19sub_group_broadcastDv16_fj(<16 x float> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z19sub_group_broadcastfj(float, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x float> @_Z19sub_group_broadcastDv2_fj(<2 x float>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x float> @_Z19sub_group_broadcastDv3_fj(<3 x float>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x float> @_Z19sub_group_broadcastDv4_fj(<4 x float>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x float> @_Z19sub_group_broadcastDv8_fj(<8 x float>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x float> @_Z19sub_group_broadcastDv16_fj(<16 x float>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[half]] {{[0-9]+}} [[ScopeSubgroup]] [[half_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half2]] [[half2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[half2]] {{[0-9]+}} [[ScopeSubgroup]] [[half2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half3]] [[half3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[half3]] {{[0-9]+}} [[ScopeSubgroup]] [[half3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half4]] [[half4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[half4]] {{[0-9]+}} [[ScopeSubgroup]] [[half4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half8]] [[half8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[half8]] {{[0-9]+}} [[ScopeSubgroup]] [[half8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[half16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[half16]] [[half16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[half16]] {{[0-9]+}} [[ScopeSubgroup]] [[half16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastHalf
+; CHECK-LLVM: call spir_func half @_Z19sub_group_broadcastDhj(half {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x half> @_Z19sub_group_broadcastDv2_Dhj(<2 x half> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x half> @_Z19sub_group_broadcastDv3_Dhj(<3 x half> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x half> @_Z19sub_group_broadcastDv4_Dhj(<4 x half> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x half> @_Z19sub_group_broadcastDv8_Dhj(<8 x half> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x half> @_Z19sub_group_broadcastDv16_Dhj(<16 x half> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastHalf() local_unnamed_addr #2 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func half @_Z19sub_group_broadcastDhj(half 0xH0000, i32 0) #6
+  %2 = insertelement <16 x half> <half undef, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000, half 0xH0000>, half %1, i64 0
+  %3 = shufflevector <16 x half> %2, <16 x half> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x half> @_Z19sub_group_broadcastDv2_Dhj(<2 x half> %3, i32 0) #6
+  %5 = shufflevector <2 x half> %4, <2 x half> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x half> %5, <16 x half> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x half> %6, <16 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x half> @_Z19sub_group_broadcastDv3_Dhj(<3 x half> %7, i32 0) #6
+  %9 = shufflevector <3 x half> %8, <3 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x half> %9, <16 x half> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x half> %10, <16 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x half> @_Z19sub_group_broadcastDv4_Dhj(<4 x half> %11, i32 0) #6
+  %13 = shufflevector <4 x half> %12, <4 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x half> %13, <16 x half> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x half> %14, <16 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x half> @_Z19sub_group_broadcastDv8_Dhj(<8 x half> %15, i32 0) #6
+  %17 = shufflevector <8 x half> %16, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x half> %17, <16 x half> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x half> @_Z19sub_group_broadcastDv16_Dhj(<16 x half> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z19sub_group_broadcastDhj(half, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x half> @_Z19sub_group_broadcastDv2_Dhj(<2 x half>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x half> @_Z19sub_group_broadcastDv3_Dhj(<3 x half>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x half> @_Z19sub_group_broadcastDv4_Dhj(<4 x half>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x half> @_Z19sub_group_broadcastDv8_Dhj(<8 x half>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x half> @_Z19sub_group_broadcastDv16_Dhj(<16 x half>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupBroadcast [[double]] {{[0-9]+}} [[ScopeSubgroup]] [[double_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double2]] [[double2_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[double2]] {{[0-9]+}} [[ScopeSubgroup]] [[double2_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double3]] [[double3_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[double3]] {{[0-9]+}} [[ScopeSubgroup]] [[double3_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double4]] [[double4_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[double4]] {{[0-9]+}} [[ScopeSubgroup]] [[double4_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double8]] [[double8_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[double8]] {{[0-9]+}} [[ScopeSubgroup]] [[double8_0]] [[int_0]]
+; CHECK-SPIRV: VectorShuffle [[double16]] {{[0-9]+}}
+; CHECK-SPIRV: VectorShuffle [[double16]] [[double16_0:[0-9]+]] 
+; CHECK-SPIRV: GroupBroadcast [[double16]] {{[0-9]+}} [[ScopeSubgroup]] [[double16_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testBroadcastDouble
+; CHECK-LLVM: call spir_func double @_Z19sub_group_broadcastdj(double {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <2 x double> @_Z19sub_group_broadcastDv2_dj(<2 x double> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <3 x double> @_Z19sub_group_broadcastDv3_dj(<3 x double> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <4 x double> @_Z19sub_group_broadcastDv4_dj(<4 x double> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <8 x double> @_Z19sub_group_broadcastDv8_dj(<8 x double> {{.*}}, i32 0)
+; CHECK-LLVM: call spir_func <16 x double> @_Z19sub_group_broadcastDv16_dj(<16 x double> {{.*}}, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testBroadcastDouble() local_unnamed_addr #4 !kernel_arg_addr_space !3 !kernel_arg_access_qual !3 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !3 {
+  %1 = tail call spir_func double @_Z19sub_group_broadcastdj(double 0.000000e+00, i32 0) #6
+  %2 = insertelement <16 x double> <double undef, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, double %1, i64 0
+  %3 = shufflevector <16 x double> %2, <16 x double> undef, <2 x i32> <i32 0, i32 1>
+  %4 = tail call spir_func <2 x double> @_Z19sub_group_broadcastDv2_dj(<2 x double> %3, i32 0) #6
+  %5 = shufflevector <2 x double> %4, <2 x double> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %6 = shufflevector <16 x double> %5, <16 x double> %2, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %7 = shufflevector <16 x double> %6, <16 x double> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %8 = tail call spir_func <3 x double> @_Z19sub_group_broadcastDv3_dj(<3 x double> %7, i32 0) #6
+  %9 = shufflevector <3 x double> %8, <3 x double> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %10 = shufflevector <16 x double> %9, <16 x double> %6, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %11 = shufflevector <16 x double> %10, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %12 = tail call spir_func <4 x double> @_Z19sub_group_broadcastDv4_dj(<4 x double> %11, i32 0) #6
+  %13 = shufflevector <4 x double> %12, <4 x double> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %14 = shufflevector <16 x double> %13, <16 x double> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %15 = shufflevector <16 x double> %14, <16 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %16 = tail call spir_func <8 x double> @_Z19sub_group_broadcastDv8_dj(<8 x double> %15, i32 0) #6
+  %17 = shufflevector <8 x double> %16, <8 x double> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %18 = shufflevector <16 x double> %17, <16 x double> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  %19 = tail call spir_func <16 x double> @_Z19sub_group_broadcastDv16_dj(<16 x double> %18, i32 0) #6
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z19sub_group_broadcastdj(double, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <2 x double> @_Z19sub_group_broadcastDv2_dj(<2 x double>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <3 x double> @_Z19sub_group_broadcastDv3_dj(<3 x double>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <4 x double> @_Z19sub_group_broadcastDv4_dj(<4 x double>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <8 x double> @_Z19sub_group_broadcastDv8_dj(<8 x double>, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func <16 x double> @_Z19sub_group_broadcastDv16_dj(<16 x double>, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupSMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupSMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupSMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupSMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupSMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupSMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testReduceScanChar
+; CHECK-LLVM call spir_func i8 @_Z20sub_group_reduce_addc(i8 0)
+; CHECK-LLVM call spir_func i8 @_Z20sub_group_reduce_minc(i8 0)
+; CHECK-LLVM call spir_func i8 @_Z20sub_group_reduce_maxc(i8 0)
+; CHECK-LLVM call spir_func i8 @_Z28sub_group_scan_inclusive_addc(i8 0)
+; CHECK-LLVM call spir_func i8 @_Z28sub_group_scan_inclusive_minc(i8 0)
+; CHECK-LLVM call spir_func i8 @_Z28sub_group_scan_inclusive_maxc(i8 0)
+; CHECK-LLVM call spir_func i8 @_Z28sub_group_scan_exclusive_addc(i8 0)
+; CHECK-LLVM call spir_func i8 @_Z28sub_group_scan_exclusive_minc(i8 0)
+; CHECK-LLVM call spir_func i8 @_Z28sub_group_scan_exclusive_maxc(i8 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testReduceScanChar(i8 addrspace(1)* nocapture) local_unnamed_addr #5 !kernel_arg_addr_space !4 !kernel_arg_access_qual !5 !kernel_arg_type !6 !kernel_arg_base_type !6 !kernel_arg_type_qual !7 {
+  %2 = tail call spir_func signext i8 @_Z20sub_group_reduce_addc(i8 signext 0) #6
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !8
+  %3 = tail call spir_func signext i8 @_Z20sub_group_reduce_minc(i8 signext 0) #6
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !8
+  %5 = tail call spir_func signext i8 @_Z20sub_group_reduce_maxc(i8 signext 0) #6
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !8
+  %7 = tail call spir_func signext i8 @_Z28sub_group_scan_inclusive_addc(i8 signext 0) #6
+  %8 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 3
+  store i8 %7, i8 addrspace(1)* %8, align 1, !tbaa !8
+  %9 = tail call spir_func signext i8 @_Z28sub_group_scan_inclusive_minc(i8 signext 0) #6
+  %10 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 4
+  store i8 %9, i8 addrspace(1)* %10, align 1, !tbaa !8
+  %11 = tail call spir_func signext i8 @_Z28sub_group_scan_inclusive_maxc(i8 signext 0) #6
+  %12 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 5
+  store i8 %11, i8 addrspace(1)* %12, align 1, !tbaa !8
+  %13 = tail call spir_func signext i8 @_Z28sub_group_scan_exclusive_addc(i8 signext 0) #6
+  %14 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 6
+  store i8 %13, i8 addrspace(1)* %14, align 1, !tbaa !8
+  %15 = tail call spir_func signext i8 @_Z28sub_group_scan_exclusive_minc(i8 signext 0) #6
+  %16 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 7
+  store i8 %15, i8 addrspace(1)* %16, align 1, !tbaa !8
+  %17 = tail call spir_func signext i8 @_Z28sub_group_scan_exclusive_maxc(i8 signext 0) #6
+  %18 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 8
+  store i8 %17, i8 addrspace(1)* %18, align 1, !tbaa !8
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z20sub_group_reduce_addc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z20sub_group_reduce_minc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z20sub_group_reduce_maxc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z28sub_group_scan_inclusive_addc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z28sub_group_scan_inclusive_minc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z28sub_group_scan_inclusive_maxc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z28sub_group_scan_exclusive_addc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z28sub_group_scan_exclusive_minc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z28sub_group_scan_exclusive_maxc(i8 signext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupUMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupUMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupUMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupUMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupUMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupUMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testReduceScanUChar
+; CHECK-LLVM: call spir_func i8 @_Z20sub_group_reduce_addc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z20sub_group_reduce_minh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z20sub_group_reduce_maxh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z28sub_group_scan_inclusive_addc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z28sub_group_scan_inclusive_minh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z28sub_group_scan_inclusive_maxh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z28sub_group_scan_exclusive_addc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z28sub_group_scan_exclusive_minh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z28sub_group_scan_exclusive_maxh(i8 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testReduceScanUChar(i8 addrspace(1)* nocapture) local_unnamed_addr #5 !kernel_arg_addr_space !4 !kernel_arg_access_qual !5 !kernel_arg_type !11 !kernel_arg_base_type !11 !kernel_arg_type_qual !7 {
+  %2 = tail call spir_func zeroext i8 @_Z20sub_group_reduce_addh(i8 zeroext 0) #6
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !8
+  %3 = tail call spir_func zeroext i8 @_Z20sub_group_reduce_minh(i8 zeroext 0) #6
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !8
+  %5 = tail call spir_func zeroext i8 @_Z20sub_group_reduce_maxh(i8 zeroext 0) #6
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !8
+  %7 = tail call spir_func zeroext i8 @_Z28sub_group_scan_inclusive_addh(i8 zeroext 0) #6
+  %8 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 3
+  store i8 %7, i8 addrspace(1)* %8, align 1, !tbaa !8
+  %9 = tail call spir_func zeroext i8 @_Z28sub_group_scan_inclusive_minh(i8 zeroext 0) #6
+  %10 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 4
+  store i8 %9, i8 addrspace(1)* %10, align 1, !tbaa !8
+  %11 = tail call spir_func zeroext i8 @_Z28sub_group_scan_inclusive_maxh(i8 zeroext 0) #6
+  %12 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 5
+  store i8 %11, i8 addrspace(1)* %12, align 1, !tbaa !8
+  %13 = tail call spir_func zeroext i8 @_Z28sub_group_scan_exclusive_addh(i8 zeroext 0) #6
+  %14 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 6
+  store i8 %13, i8 addrspace(1)* %14, align 1, !tbaa !8
+  %15 = tail call spir_func zeroext i8 @_Z28sub_group_scan_exclusive_minh(i8 zeroext 0) #6
+  %16 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 7
+  store i8 %15, i8 addrspace(1)* %16, align 1, !tbaa !8
+  %17 = tail call spir_func zeroext i8 @_Z28sub_group_scan_exclusive_maxh(i8 zeroext 0) #6
+  %18 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 8
+  store i8 %17, i8 addrspace(1)* %18, align 1, !tbaa !8
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z20sub_group_reduce_addh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z20sub_group_reduce_minh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z20sub_group_reduce_maxh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z28sub_group_scan_inclusive_addh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z28sub_group_scan_inclusive_minh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z28sub_group_scan_inclusive_maxh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z28sub_group_scan_exclusive_addh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z28sub_group_scan_exclusive_minh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z28sub_group_scan_exclusive_maxh(i8 zeroext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupSMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupSMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupSMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupSMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupSMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupSMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testReduceScanShort
+; CHECK-LLVM: call spir_func i16 @_Z20sub_group_reduce_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z20sub_group_reduce_mins(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z20sub_group_reduce_maxs(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_inclusive_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_inclusive_mins(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_inclusive_maxs(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_exclusive_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_exclusive_mins(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_exclusive_maxs(i16 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testReduceScanShort(i16 addrspace(1)* nocapture) local_unnamed_addr #5 !kernel_arg_addr_space !4 !kernel_arg_access_qual !5 !kernel_arg_type !12 !kernel_arg_base_type !12 !kernel_arg_type_qual !7 {
+  %2 = tail call spir_func signext i16 @_Z20sub_group_reduce_adds(i16 signext 0) #6
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !13
+  %3 = tail call spir_func signext i16 @_Z20sub_group_reduce_mins(i16 signext 0) #6
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !13
+  %5 = tail call spir_func signext i16 @_Z20sub_group_reduce_maxs(i16 signext 0) #6
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !13
+  %7 = tail call spir_func signext i16 @_Z28sub_group_scan_inclusive_adds(i16 signext 0) #6
+  %8 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 3
+  store i16 %7, i16 addrspace(1)* %8, align 2, !tbaa !13
+  %9 = tail call spir_func signext i16 @_Z28sub_group_scan_inclusive_mins(i16 signext 0) #6
+  %10 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 4
+  store i16 %9, i16 addrspace(1)* %10, align 2, !tbaa !13
+  %11 = tail call spir_func signext i16 @_Z28sub_group_scan_inclusive_maxs(i16 signext 0) #6
+  %12 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 5
+  store i16 %11, i16 addrspace(1)* %12, align 2, !tbaa !13
+  %13 = tail call spir_func signext i16 @_Z28sub_group_scan_exclusive_adds(i16 signext 0) #6
+  %14 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 6
+  store i16 %13, i16 addrspace(1)* %14, align 2, !tbaa !13
+  %15 = tail call spir_func signext i16 @_Z28sub_group_scan_exclusive_mins(i16 signext 0) #6
+  %16 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 7
+  store i16 %15, i16 addrspace(1)* %16, align 2, !tbaa !13
+  %17 = tail call spir_func signext i16 @_Z28sub_group_scan_exclusive_maxs(i16 signext 0) #6
+  %18 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 8
+  store i16 %17, i16 addrspace(1)* %18, align 2, !tbaa !13
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z20sub_group_reduce_adds(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z20sub_group_reduce_mins(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z20sub_group_reduce_maxs(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z28sub_group_scan_inclusive_adds(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z28sub_group_scan_inclusive_mins(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z28sub_group_scan_inclusive_maxs(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z28sub_group_scan_exclusive_adds(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z28sub_group_scan_exclusive_mins(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z28sub_group_scan_exclusive_maxs(i16 signext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupUMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupUMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupUMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupUMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupUMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupUMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testReduceScanUShort
+; CHECK-LLVM: call spir_func i16 @_Z20sub_group_reduce_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z20sub_group_reduce_mint(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z20sub_group_reduce_maxt(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_inclusive_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_inclusive_mint(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_inclusive_maxt(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_exclusive_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_exclusive_mint(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z28sub_group_scan_exclusive_maxt(i16 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testReduceScanUShort(i16 addrspace(1)* nocapture) local_unnamed_addr #5 !kernel_arg_addr_space !4 !kernel_arg_access_qual !5 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !7 {
+  %2 = tail call spir_func zeroext i16 @_Z20sub_group_reduce_addt(i16 zeroext 0) #6
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !13
+  %3 = tail call spir_func zeroext i16 @_Z20sub_group_reduce_mint(i16 zeroext 0) #6
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !13
+  %5 = tail call spir_func zeroext i16 @_Z20sub_group_reduce_maxt(i16 zeroext 0) #6
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !13
+  %7 = tail call spir_func zeroext i16 @_Z28sub_group_scan_inclusive_addt(i16 zeroext 0) #6
+  %8 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 3
+  store i16 %7, i16 addrspace(1)* %8, align 2, !tbaa !13
+  %9 = tail call spir_func zeroext i16 @_Z28sub_group_scan_inclusive_mint(i16 zeroext 0) #6
+  %10 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 4
+  store i16 %9, i16 addrspace(1)* %10, align 2, !tbaa !13
+  %11 = tail call spir_func zeroext i16 @_Z28sub_group_scan_inclusive_maxt(i16 zeroext 0) #6
+  %12 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 5
+  store i16 %11, i16 addrspace(1)* %12, align 2, !tbaa !13
+  %13 = tail call spir_func zeroext i16 @_Z28sub_group_scan_exclusive_addt(i16 zeroext 0) #6
+  %14 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 6
+  store i16 %13, i16 addrspace(1)* %14, align 2, !tbaa !13
+  %15 = tail call spir_func zeroext i16 @_Z28sub_group_scan_exclusive_mint(i16 zeroext 0) #6
+  %16 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 7
+  store i16 %15, i16 addrspace(1)* %16, align 2, !tbaa !13
+  %17 = tail call spir_func zeroext i16 @_Z28sub_group_scan_exclusive_maxt(i16 zeroext 0) #6
+  %18 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 8
+  store i16 %17, i16 addrspace(1)* %18, align 2, !tbaa !13
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z20sub_group_reduce_addt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z20sub_group_reduce_mint(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z20sub_group_reduce_maxt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z28sub_group_scan_inclusive_addt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z28sub_group_scan_inclusive_mint(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z28sub_group_scan_inclusive_maxt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z28sub_group_scan_exclusive_addt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z28sub_group_scan_exclusive_mint(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z28sub_group_scan_exclusive_maxt(i16 zeroext) local_unnamed_addr #1
+
+attributes #0 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="256" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="512" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="1024" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #6 = { convergent nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{!"clang version 9.0.1 (https://github.com/llvm/llvm-project.git cb6d58d1dcf36a29ae5dd24ff891d6552f00bac7)"}
+!3 = !{}
+!4 = !{i32 1}
+!5 = !{!"none"}
+!6 = !{!"char*"}
+!7 = !{!""}
+!8 = !{!9, !9, i64 0}
+!9 = !{!"omnipotent char", !10, i64 0}
+!10 = !{!"Simple C/C++ TBAA"}
+!11 = !{!"uchar*"}
+!12 = !{!"short*"}
+!13 = !{!14, !14, i64 0}
+!14 = !{!"short", !9, i64 0}
+!15 = !{!"ushort*"}
\ No newline at end of file
diff --git a/llvm-spirv/test/transcoding/sub_group_non_uniform_arithmetic.ll b/llvm-spirv/test/transcoding/sub_group_non_uniform_arithmetic.ll
new file mode 100644
index 000000000000..82a59bdbbdb1
--- /dev/null
+++ b/llvm-spirv/test/transcoding/sub_group_non_uniform_arithmetic.ll
@@ -0,0 +1,2270 @@
+;; #pragma OPENCL EXTENSION cl_khr_subgroup_non_uniform_arithmetic : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp16 : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp64 : enable
+;; 
+;; kernel void testNonUniformArithmeticChar(global char* dst)
+;; {
+;;     char v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticUChar(global uchar* dst)
+;; {
+;;     uchar v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticShort(global short* dst)
+;; {
+;;     short v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticUShort(global ushort* dst)
+;; {
+;;     ushort v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticInt(global int* dst)
+;; {
+;;     int v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticUInt(global uint* dst)
+;; {
+;;     uint v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticLong(global long* dst)
+;; {
+;;     long v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticULong(global ulong* dst)
+;; {
+;;     ulong v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticFloat(global float* dst)
+;; {
+;;     float v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticHalf(global half* dst)
+;; {
+;;     half v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformArithmeticDouble(global double* dst)
+;; {
+;;     double v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_add(v);
+;;     dst[1] = sub_group_non_uniform_reduce_mul(v);
+;;     dst[2] = sub_group_non_uniform_reduce_min(v);
+;;     dst[3] = sub_group_non_uniform_reduce_max(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_add(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_mul(v);
+;;     dst[6] = sub_group_non_uniform_scan_inclusive_min(v);
+;;     dst[7] = sub_group_non_uniform_scan_inclusive_max(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_add(v);
+;;     dst[9] = sub_group_non_uniform_scan_exclusive_mul(v);
+;;     dst[10] = sub_group_non_uniform_scan_exclusive_min(v);
+;;     dst[11] = sub_group_non_uniform_scan_exclusive_max(v);
+;; }
+;; 
+;; kernel void testNonUniformBitwiseChar(global char* dst)
+;; {
+;;     char v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_and(v);
+;;     dst[1] = sub_group_non_uniform_reduce_or(v);
+;;     dst[2] = sub_group_non_uniform_reduce_xor(v);
+;;     dst[3] = sub_group_non_uniform_scan_inclusive_and(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_or(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_xor(v);
+;;     dst[6] = sub_group_non_uniform_scan_exclusive_and(v);
+;;     dst[7] = sub_group_non_uniform_scan_exclusive_or(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_xor(v);
+;; }
+;; kernel void testNonUniformBitwiseUChar(global uchar* dst)
+;; {
+;;     uchar v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_and(v);
+;;     dst[1] = sub_group_non_uniform_reduce_or(v);
+;;     dst[2] = sub_group_non_uniform_reduce_xor(v);
+;;     dst[3] = sub_group_non_uniform_scan_inclusive_and(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_or(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_xor(v);
+;;     dst[6] = sub_group_non_uniform_scan_exclusive_and(v);
+;;     dst[7] = sub_group_non_uniform_scan_exclusive_or(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_xor(v);
+;; }
+;; kernel void testNonUniformBitwiseShort(global short* dst)
+;; {
+;;     short v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_and(v);
+;;     dst[1] = sub_group_non_uniform_reduce_or(v);
+;;     dst[2] = sub_group_non_uniform_reduce_xor(v);
+;;     dst[3] = sub_group_non_uniform_scan_inclusive_and(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_or(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_xor(v);
+;;     dst[6] = sub_group_non_uniform_scan_exclusive_and(v);
+;;     dst[7] = sub_group_non_uniform_scan_exclusive_or(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_xor(v);
+;; }
+;; kernel void testNonUniformBitwiseUShort(global ushort* dst)
+;; {
+;;     ushort v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_and(v);
+;;     dst[1] = sub_group_non_uniform_reduce_or(v);
+;;     dst[2] = sub_group_non_uniform_reduce_xor(v);
+;;     dst[3] = sub_group_non_uniform_scan_inclusive_and(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_or(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_xor(v);
+;;     dst[6] = sub_group_non_uniform_scan_exclusive_and(v);
+;;     dst[7] = sub_group_non_uniform_scan_exclusive_or(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_xor(v);
+;; }
+;; kernel void testNonUniformBitwiseInt(global int* dst)
+;; {
+;;     int v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_and(v);
+;;     dst[1] = sub_group_non_uniform_reduce_or(v);
+;;     dst[2] = sub_group_non_uniform_reduce_xor(v);
+;;     dst[3] = sub_group_non_uniform_scan_inclusive_and(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_or(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_xor(v);
+;;     dst[6] = sub_group_non_uniform_scan_exclusive_and(v);
+;;     dst[7] = sub_group_non_uniform_scan_exclusive_or(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_xor(v);
+;; }
+;; kernel void testNonUniformBitwiseUInt(global uint* dst)
+;; {
+;;     uint v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_and(v);
+;;     dst[1] = sub_group_non_uniform_reduce_or(v);
+;;     dst[2] = sub_group_non_uniform_reduce_xor(v);
+;;     dst[3] = sub_group_non_uniform_scan_inclusive_and(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_or(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_xor(v);
+;;     dst[6] = sub_group_non_uniform_scan_exclusive_and(v);
+;;     dst[7] = sub_group_non_uniform_scan_exclusive_or(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_xor(v);
+;; }
+;; kernel void testNonUniformBitwiseLong(global long* dst)
+;; {
+;;     long v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_and(v);
+;;     dst[1] = sub_group_non_uniform_reduce_or(v);
+;;     dst[2] = sub_group_non_uniform_reduce_xor(v);
+;;     dst[3] = sub_group_non_uniform_scan_inclusive_and(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_or(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_xor(v);
+;;     dst[6] = sub_group_non_uniform_scan_exclusive_and(v);
+;;     dst[7] = sub_group_non_uniform_scan_exclusive_or(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_xor(v);
+;; }
+;; kernel void testNonUniformBitwiseULong(global ulong* dst)
+;; {
+;;     ulong v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_and(v);
+;;     dst[1] = sub_group_non_uniform_reduce_or(v);
+;;     dst[2] = sub_group_non_uniform_reduce_xor(v);
+;;     dst[3] = sub_group_non_uniform_scan_inclusive_and(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_or(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_xor(v);
+;;     dst[6] = sub_group_non_uniform_scan_exclusive_and(v);
+;;     dst[7] = sub_group_non_uniform_scan_exclusive_or(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_xor(v);
+;; }
+;; 
+;; kernel void testNonUniformLogical(global int* dst)
+;; {
+;;     int v = 0;
+;;     dst[0] = sub_group_non_uniform_reduce_logical_and(v);
+;;     dst[1] = sub_group_non_uniform_reduce_logical_or(v);
+;;     dst[2] = sub_group_non_uniform_reduce_logical_xor(v);
+;;     dst[3] = sub_group_non_uniform_scan_inclusive_logical_and(v);
+;;     dst[4] = sub_group_non_uniform_scan_inclusive_logical_or(v);
+;;     dst[5] = sub_group_non_uniform_scan_inclusive_logical_xor(v);
+;;     dst[6] = sub_group_non_uniform_scan_exclusive_logical_and(v);
+;;     dst[7] = sub_group_non_uniform_scan_exclusive_logical_or(v);
+;;     dst[8] = sub_group_non_uniform_scan_exclusive_logical_xor(v);
+;; }
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; Change DISABLED to RUN once SPIRV->LLVM translation is implemented
+; DISABLED: llvm-spirv -r %t.spv -o %t.rev.bc
+; DISABLED: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV-DAG: {{[0-9]*}} Capability GroupNonUniformArithmetic
+
+; CHECK-SPIRV-DAG: TypeBool  [[bool:[0-9]+]]
+; CHECK-SPIRV-DAG: TypeInt   [[char:[0-9]+]]   8  0
+; CHECK-SPIRV-DAG: TypeInt   [[short:[0-9]+]]  16 0
+; CHECK-SPIRV-DAG: TypeInt   [[int:[0-9]+]]    32 0
+; CHECK-SPIRV-DAG: TypeInt   [[long:[0-9]+]]   64 0
+; CHECK-SPIRV-DAG: TypeFloat [[half:[0-9]+]]   16
+; CHECK-SPIRV-DAG: TypeFloat [[float:[0-9]+]]  32
+; CHECK-SPIRV-DAG: TypeFloat [[double:[0-9]+]] 64
+
+; CHECK-SPIRV-DAG: ConstantFalse [[bool]] [[false:[0-9]+]]
+; CHECK-SPIRV-DAG: Constant [[int]]    [[ScopeSubgroup:[0-9]+]] 3
+; CHECK-SPIRV-DAG: Constant [[char]]   [[char_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[short]]  [[short_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[int]]    [[int_0:[0-9]+]]         0
+; CHECK-SPIRV-DAG: Constant [[long]]   [[long_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[half]]   [[half_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[float]]  [[float_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[double]] [[double_0:[0-9]+]]      0
+
+; ModuleID = 'sub_group_non_uniform_arithmetic.cl'
+source_filename = "sub_group_non_uniform_arithmetic.cl"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticChar
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_addc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_mulc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_minc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_maxc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_addc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_mulc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_minc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_maxc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_addc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_mulc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_minc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_maxc(i8 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i8 @_Z32sub_group_non_uniform_reduce_addc(i8 signext 0) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func signext i8 @_Z32sub_group_non_uniform_reduce_mulc(i8 signext 0) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  %5 = tail call spir_func signext i8 @_Z32sub_group_non_uniform_reduce_minc(i8 signext 0) #2
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !7
+  %7 = tail call spir_func signext i8 @_Z32sub_group_non_uniform_reduce_maxc(i8 signext 0) #2
+  %8 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 3
+  store i8 %7, i8 addrspace(1)* %8, align 1, !tbaa !7
+  %9 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_addc(i8 signext 0) #2
+  %10 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 4
+  store i8 %9, i8 addrspace(1)* %10, align 1, !tbaa !7
+  %11 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_mulc(i8 signext 0) #2
+  %12 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 5
+  store i8 %11, i8 addrspace(1)* %12, align 1, !tbaa !7
+  %13 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_minc(i8 signext 0) #2
+  %14 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 6
+  store i8 %13, i8 addrspace(1)* %14, align 1, !tbaa !7
+  %15 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_maxc(i8 signext 0) #2
+  %16 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 7
+  store i8 %15, i8 addrspace(1)* %16, align 1, !tbaa !7
+  %17 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_addc(i8 signext 0) #2
+  %18 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 8
+  store i8 %17, i8 addrspace(1)* %18, align 1, !tbaa !7
+  %19 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_mulc(i8 signext 0) #2
+  %20 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 9
+  store i8 %19, i8 addrspace(1)* %20, align 1, !tbaa !7
+  %21 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_minc(i8 signext 0) #2
+  %22 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 10
+  store i8 %21, i8 addrspace(1)* %22, align 1, !tbaa !7
+  %23 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_maxc(i8 signext 0) #2
+  %24 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 11
+  store i8 %23, i8 addrspace(1)* %24, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z32sub_group_non_uniform_reduce_addc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z32sub_group_non_uniform_reduce_mulc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z32sub_group_non_uniform_reduce_minc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z32sub_group_non_uniform_reduce_maxc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_addc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_mulc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_minc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_maxc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_addc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_mulc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_minc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_maxc(i8 signext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticUChar
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_addc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_mulc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_minh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_maxh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_addc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_mulc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_minh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_maxh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_addc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_mulc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_minh(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_maxh(i8 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticUChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_addh(i8 zeroext 0) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_mulh(i8 zeroext 0) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  %5 = tail call spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_minh(i8 zeroext 0) #2
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !7
+  %7 = tail call spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_maxh(i8 zeroext 0) #2
+  %8 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 3
+  store i8 %7, i8 addrspace(1)* %8, align 1, !tbaa !7
+  %9 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_addh(i8 zeroext 0) #2
+  %10 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 4
+  store i8 %9, i8 addrspace(1)* %10, align 1, !tbaa !7
+  %11 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_mulh(i8 zeroext 0) #2
+  %12 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 5
+  store i8 %11, i8 addrspace(1)* %12, align 1, !tbaa !7
+  %13 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_minh(i8 zeroext 0) #2
+  %14 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 6
+  store i8 %13, i8 addrspace(1)* %14, align 1, !tbaa !7
+  %15 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_maxh(i8 zeroext 0) #2
+  %16 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 7
+  store i8 %15, i8 addrspace(1)* %16, align 1, !tbaa !7
+  %17 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_addh(i8 zeroext 0) #2
+  %18 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 8
+  store i8 %17, i8 addrspace(1)* %18, align 1, !tbaa !7
+  %19 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_mulh(i8 zeroext 0) #2
+  %20 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 9
+  store i8 %19, i8 addrspace(1)* %20, align 1, !tbaa !7
+  %21 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_minh(i8 zeroext 0) #2
+  %22 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 10
+  store i8 %21, i8 addrspace(1)* %22, align 1, !tbaa !7
+  %23 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_maxh(i8 zeroext 0) #2
+  %24 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 11
+  store i8 %23, i8 addrspace(1)* %24, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_addh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_mulh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_minh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_maxh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_addh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_mulh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_minh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_maxh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_addh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_mulh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_minh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_maxh(i8 zeroext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticShort
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_muls(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_mins(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_maxs(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_muls(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_mins(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_maxs(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_muls(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_mins(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_maxs(i16 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !11 !kernel_arg_base_type !11 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i16 @_Z32sub_group_non_uniform_reduce_adds(i16 signext 0) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func signext i16 @_Z32sub_group_non_uniform_reduce_muls(i16 signext 0) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  %5 = tail call spir_func signext i16 @_Z32sub_group_non_uniform_reduce_mins(i16 signext 0) #2
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !12
+  %7 = tail call spir_func signext i16 @_Z32sub_group_non_uniform_reduce_maxs(i16 signext 0) #2
+  %8 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 3
+  store i16 %7, i16 addrspace(1)* %8, align 2, !tbaa !12
+  %9 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_adds(i16 signext 0) #2
+  %10 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 4
+  store i16 %9, i16 addrspace(1)* %10, align 2, !tbaa !12
+  %11 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_muls(i16 signext 0) #2
+  %12 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 5
+  store i16 %11, i16 addrspace(1)* %12, align 2, !tbaa !12
+  %13 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_mins(i16 signext 0) #2
+  %14 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 6
+  store i16 %13, i16 addrspace(1)* %14, align 2, !tbaa !12
+  %15 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_maxs(i16 signext 0) #2
+  %16 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 7
+  store i16 %15, i16 addrspace(1)* %16, align 2, !tbaa !12
+  %17 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_adds(i16 signext 0) #2
+  %18 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 8
+  store i16 %17, i16 addrspace(1)* %18, align 2, !tbaa !12
+  %19 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_muls(i16 signext 0) #2
+  %20 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 9
+  store i16 %19, i16 addrspace(1)* %20, align 2, !tbaa !12
+  %21 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_mins(i16 signext 0) #2
+  %22 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 10
+  store i16 %21, i16 addrspace(1)* %22, align 2, !tbaa !12
+  %23 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_maxs(i16 signext 0) #2
+  %24 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 11
+  store i16 %23, i16 addrspace(1)* %24, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z32sub_group_non_uniform_reduce_adds(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z32sub_group_non_uniform_reduce_muls(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z32sub_group_non_uniform_reduce_mins(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z32sub_group_non_uniform_reduce_maxs(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_adds(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_muls(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_mins(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_maxs(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_adds(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_muls(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_mins(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_maxs(i16 signext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticUShort
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_muls(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_mint(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_maxt(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_muls(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_mint(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_maxt(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_adds(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_muls(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_mint(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_maxt(i16 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticUShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_addt(i16 zeroext 0) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_mult(i16 zeroext 0) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  %5 = tail call spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_mint(i16 zeroext 0) #2
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !12
+  %7 = tail call spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_maxt(i16 zeroext 0) #2
+  %8 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 3
+  store i16 %7, i16 addrspace(1)* %8, align 2, !tbaa !12
+  %9 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_addt(i16 zeroext 0) #2
+  %10 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 4
+  store i16 %9, i16 addrspace(1)* %10, align 2, !tbaa !12
+  %11 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_mult(i16 zeroext 0) #2
+  %12 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 5
+  store i16 %11, i16 addrspace(1)* %12, align 2, !tbaa !12
+  %13 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_mint(i16 zeroext 0) #2
+  %14 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 6
+  store i16 %13, i16 addrspace(1)* %14, align 2, !tbaa !12
+  %15 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_maxt(i16 zeroext 0) #2
+  %16 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 7
+  store i16 %15, i16 addrspace(1)* %16, align 2, !tbaa !12
+  %17 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_addt(i16 zeroext 0) #2
+  %18 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 8
+  store i16 %17, i16 addrspace(1)* %18, align 2, !tbaa !12
+  %19 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_mult(i16 zeroext 0) #2
+  %20 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 9
+  store i16 %19, i16 addrspace(1)* %20, align 2, !tbaa !12
+  %21 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_mint(i16 zeroext 0) #2
+  %22 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 10
+  store i16 %21, i16 addrspace(1)* %22, align 2, !tbaa !12
+  %23 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_maxt(i16 zeroext 0) #2
+  %24 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 11
+  store i16 %23, i16 addrspace(1)* %24, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_addt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_mult(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_mint(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_maxt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_addt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_mult(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_mint(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_maxt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_addt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_mult(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_mint(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_maxt(i16 zeroext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticInt
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_addi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_muli(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_mini(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_maxi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_addi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_muli(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_mini(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_maxi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_addi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_muli(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_mini(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_maxi(i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_addi(i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_muli(i32 0) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_mini(i32 0) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  %7 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_maxi(i32 0) #2
+  %8 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 3
+  store i32 %7, i32 addrspace(1)* %8, align 4, !tbaa !16
+  %9 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_addi(i32 0) #2
+  %10 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 4
+  store i32 %9, i32 addrspace(1)* %10, align 4, !tbaa !16
+  %11 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_muli(i32 0) #2
+  %12 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 5
+  store i32 %11, i32 addrspace(1)* %12, align 4, !tbaa !16
+  %13 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_mini(i32 0) #2
+  %14 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 6
+  store i32 %13, i32 addrspace(1)* %14, align 4, !tbaa !16
+  %15 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_maxi(i32 0) #2
+  %16 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 7
+  store i32 %15, i32 addrspace(1)* %16, align 4, !tbaa !16
+  %17 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_addi(i32 0) #2
+  %18 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 8
+  store i32 %17, i32 addrspace(1)* %18, align 4, !tbaa !16
+  %19 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_muli(i32 0) #2
+  %20 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 9
+  store i32 %19, i32 addrspace(1)* %20, align 4, !tbaa !16
+  %21 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_mini(i32 0) #2
+  %22 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 10
+  store i32 %21, i32 addrspace(1)* %22, align 4, !tbaa !16
+  %23 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_maxi(i32 0) #2
+  %24 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 11
+  store i32 %23, i32 addrspace(1)* %24, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_addi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_muli(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_mini(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_maxi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_addi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_muli(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_mini(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_maxi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_addi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_muli(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_mini(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_maxi(i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticUInt
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_addi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_muli(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_minj(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_maxj(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_addi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_muli(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_minj(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_maxj(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_addi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_muli(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_minj(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_maxj(i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticUInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !18 !kernel_arg_base_type !18 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_addj(i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_mulj(i32 0) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_minj(i32 0) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  %7 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_maxj(i32 0) #2
+  %8 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 3
+  store i32 %7, i32 addrspace(1)* %8, align 4, !tbaa !16
+  %9 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_addj(i32 0) #2
+  %10 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 4
+  store i32 %9, i32 addrspace(1)* %10, align 4, !tbaa !16
+  %11 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_mulj(i32 0) #2
+  %12 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 5
+  store i32 %11, i32 addrspace(1)* %12, align 4, !tbaa !16
+  %13 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_minj(i32 0) #2
+  %14 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 6
+  store i32 %13, i32 addrspace(1)* %14, align 4, !tbaa !16
+  %15 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_maxj(i32 0) #2
+  %16 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 7
+  store i32 %15, i32 addrspace(1)* %16, align 4, !tbaa !16
+  %17 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_addj(i32 0) #2
+  %18 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 8
+  store i32 %17, i32 addrspace(1)* %18, align 4, !tbaa !16
+  %19 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_mulj(i32 0) #2
+  %20 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 9
+  store i32 %19, i32 addrspace(1)* %20, align 4, !tbaa !16
+  %21 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_minj(i32 0) #2
+  %22 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 10
+  store i32 %21, i32 addrspace(1)* %22, align 4, !tbaa !16
+  %23 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_maxj(i32 0) #2
+  %24 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 11
+  store i32 %23, i32 addrspace(1)* %24, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_addj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_mulj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_minj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_maxj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_addj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_mulj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_minj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_maxj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_addj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_mulj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_minj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_maxj(i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformSMin [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformSMax [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticLong
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_addl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_mull(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_minl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_maxl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_addl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_mull(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_minl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_maxl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_addl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_mull(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_minl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_maxl(i64 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticLong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !19 !kernel_arg_base_type !19 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_addl(i64 0) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_mull(i64 0) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  %5 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_minl(i64 0) #2
+  %6 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 2
+  store i64 %5, i64 addrspace(1)* %6, align 8, !tbaa !20
+  %7 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_maxl(i64 0) #2
+  %8 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 3
+  store i64 %7, i64 addrspace(1)* %8, align 8, !tbaa !20
+  %9 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_addl(i64 0) #2
+  %10 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 4
+  store i64 %9, i64 addrspace(1)* %10, align 8, !tbaa !20
+  %11 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_mull(i64 0) #2
+  %12 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 5
+  store i64 %11, i64 addrspace(1)* %12, align 8, !tbaa !20
+  %13 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_minl(i64 0) #2
+  %14 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 6
+  store i64 %13, i64 addrspace(1)* %14, align 8, !tbaa !20
+  %15 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_maxl(i64 0) #2
+  %16 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 7
+  store i64 %15, i64 addrspace(1)* %16, align 8, !tbaa !20
+  %17 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_addl(i64 0) #2
+  %18 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 8
+  store i64 %17, i64 addrspace(1)* %18, align 8, !tbaa !20
+  %19 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_mull(i64 0) #2
+  %20 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 9
+  store i64 %19, i64 addrspace(1)* %20, align 8, !tbaa !20
+  %21 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_minl(i64 0) #2
+  %22 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 10
+  store i64 %21, i64 addrspace(1)* %22, align 8, !tbaa !20
+  %23 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_maxl(i64 0) #2
+  %24 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 11
+  store i64 %23, i64 addrspace(1)* %24, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_addl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_mull(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_minl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_maxl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_addl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_mull(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_minl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_maxl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_addl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_mull(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_minl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_maxl(i64) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformIAdd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIAdd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformIMul [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformUMin [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformUMax [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticULong
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_addl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_mull(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_minm(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_maxm(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_addl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_mull(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_minm(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_maxm(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_addl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_mull(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_minm(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_maxm(i64 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticULong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !22 !kernel_arg_base_type !22 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_addm(i64 0) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_mulm(i64 0) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  %5 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_minm(i64 0) #2
+  %6 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 2
+  store i64 %5, i64 addrspace(1)* %6, align 8, !tbaa !20
+  %7 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_maxm(i64 0) #2
+  %8 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 3
+  store i64 %7, i64 addrspace(1)* %8, align 8, !tbaa !20
+  %9 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_addm(i64 0) #2
+  %10 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 4
+  store i64 %9, i64 addrspace(1)* %10, align 8, !tbaa !20
+  %11 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_mulm(i64 0) #2
+  %12 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 5
+  store i64 %11, i64 addrspace(1)* %12, align 8, !tbaa !20
+  %13 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_minm(i64 0) #2
+  %14 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 6
+  store i64 %13, i64 addrspace(1)* %14, align 8, !tbaa !20
+  %15 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_maxm(i64 0) #2
+  %16 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 7
+  store i64 %15, i64 addrspace(1)* %16, align 8, !tbaa !20
+  %17 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_addm(i64 0) #2
+  %18 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 8
+  store i64 %17, i64 addrspace(1)* %18, align 8, !tbaa !20
+  %19 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_mulm(i64 0) #2
+  %20 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 9
+  store i64 %19, i64 addrspace(1)* %20, align 8, !tbaa !20
+  %21 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_minm(i64 0) #2
+  %22 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 10
+  store i64 %21, i64 addrspace(1)* %22, align 8, !tbaa !20
+  %23 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_maxm(i64 0) #2
+  %24 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 11
+  store i64 %23, i64 addrspace(1)* %24, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_addm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_mulm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_minm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_maxm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_addm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_mulm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_minm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_maxm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_addm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_mulm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_minm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_maxm(i64) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformFAdd [[float]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFMul [[float]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFMin [[float]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFMax [[float]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFAdd [[float]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFMul [[float]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFMin [[float]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFMax [[float]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFAdd [[float]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFMul [[float]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFMin [[float]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[float_0]]
+; CHECK-SPIRV: GroupNonUniformFMax [[float]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[float_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticFloat
+; CHECK-LLVM: call spir_func float @_Z32sub_group_non_uniform_reduce_addf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z32sub_group_non_uniform_reduce_mulf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z32sub_group_non_uniform_reduce_minf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z32sub_group_non_uniform_reduce_maxf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z40sub_group_non_uniform_scan_inclusive_addf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z40sub_group_non_uniform_scan_inclusive_mulf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z40sub_group_non_uniform_scan_inclusive_minf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z40sub_group_non_uniform_scan_inclusive_maxf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z40sub_group_non_uniform_scan_exclusive_addf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z40sub_group_non_uniform_scan_exclusive_mulf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z40sub_group_non_uniform_scan_exclusive_minf(float 0.000000e+00)
+; CHECK-LLVM: call spir_func float @_Z40sub_group_non_uniform_scan_exclusive_maxf(float 0.000000e+00)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticFloat(float addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !23 !kernel_arg_base_type !23 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func float @_Z32sub_group_non_uniform_reduce_addf(float 0.000000e+00) #2
+  store float %2, float addrspace(1)* %0, align 4, !tbaa !24
+  %3 = tail call spir_func float @_Z32sub_group_non_uniform_reduce_mulf(float 0.000000e+00) #2
+  %4 = getelementptr inbounds float, float addrspace(1)* %0, i64 1
+  store float %3, float addrspace(1)* %4, align 4, !tbaa !24
+  %5 = tail call spir_func float @_Z32sub_group_non_uniform_reduce_minf(float 0.000000e+00) #2
+  %6 = getelementptr inbounds float, float addrspace(1)* %0, i64 2
+  store float %5, float addrspace(1)* %6, align 4, !tbaa !24
+  %7 = tail call spir_func float @_Z32sub_group_non_uniform_reduce_maxf(float 0.000000e+00) #2
+  %8 = getelementptr inbounds float, float addrspace(1)* %0, i64 3
+  store float %7, float addrspace(1)* %8, align 4, !tbaa !24
+  %9 = tail call spir_func float @_Z40sub_group_non_uniform_scan_inclusive_addf(float 0.000000e+00) #2
+  %10 = getelementptr inbounds float, float addrspace(1)* %0, i64 4
+  store float %9, float addrspace(1)* %10, align 4, !tbaa !24
+  %11 = tail call spir_func float @_Z40sub_group_non_uniform_scan_inclusive_mulf(float 0.000000e+00) #2
+  %12 = getelementptr inbounds float, float addrspace(1)* %0, i64 5
+  store float %11, float addrspace(1)* %12, align 4, !tbaa !24
+  %13 = tail call spir_func float @_Z40sub_group_non_uniform_scan_inclusive_minf(float 0.000000e+00) #2
+  %14 = getelementptr inbounds float, float addrspace(1)* %0, i64 6
+  store float %13, float addrspace(1)* %14, align 4, !tbaa !24
+  %15 = tail call spir_func float @_Z40sub_group_non_uniform_scan_inclusive_maxf(float 0.000000e+00) #2
+  %16 = getelementptr inbounds float, float addrspace(1)* %0, i64 7
+  store float %15, float addrspace(1)* %16, align 4, !tbaa !24
+  %17 = tail call spir_func float @_Z40sub_group_non_uniform_scan_exclusive_addf(float 0.000000e+00) #2
+  %18 = getelementptr inbounds float, float addrspace(1)* %0, i64 8
+  store float %17, float addrspace(1)* %18, align 4, !tbaa !24
+  %19 = tail call spir_func float @_Z40sub_group_non_uniform_scan_exclusive_mulf(float 0.000000e+00) #2
+  %20 = getelementptr inbounds float, float addrspace(1)* %0, i64 9
+  store float %19, float addrspace(1)* %20, align 4, !tbaa !24
+  %21 = tail call spir_func float @_Z40sub_group_non_uniform_scan_exclusive_minf(float 0.000000e+00) #2
+  %22 = getelementptr inbounds float, float addrspace(1)* %0, i64 10
+  store float %21, float addrspace(1)* %22, align 4, !tbaa !24
+  %23 = tail call spir_func float @_Z40sub_group_non_uniform_scan_exclusive_maxf(float 0.000000e+00) #2
+  %24 = getelementptr inbounds float, float addrspace(1)* %0, i64 11
+  store float %23, float addrspace(1)* %24, align 4, !tbaa !24
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z32sub_group_non_uniform_reduce_addf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z32sub_group_non_uniform_reduce_mulf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z32sub_group_non_uniform_reduce_minf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z32sub_group_non_uniform_reduce_maxf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z40sub_group_non_uniform_scan_inclusive_addf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z40sub_group_non_uniform_scan_inclusive_mulf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z40sub_group_non_uniform_scan_inclusive_minf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z40sub_group_non_uniform_scan_inclusive_maxf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z40sub_group_non_uniform_scan_exclusive_addf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z40sub_group_non_uniform_scan_exclusive_mulf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z40sub_group_non_uniform_scan_exclusive_minf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z40sub_group_non_uniform_scan_exclusive_maxf(float) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformFAdd [[half]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFMul [[half]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFMin [[half]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFMax [[half]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFAdd [[half]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFMul [[half]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFMin [[half]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFMax [[half]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFAdd [[half]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFMul [[half]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFMin [[half]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[half_0]]
+; CHECK-SPIRV: GroupNonUniformFMax [[half]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[half_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticHalf
+; CHECK-LLVM: call spir_func half @_Z32sub_group_non_uniform_reduce_addDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z32sub_group_non_uniform_reduce_mulDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z32sub_group_non_uniform_reduce_minDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z32sub_group_non_uniform_reduce_maxDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z40sub_group_non_uniform_scan_inclusive_addDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z40sub_group_non_uniform_scan_inclusive_mulDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z40sub_group_non_uniform_scan_inclusive_minDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z40sub_group_non_uniform_scan_inclusive_maxDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z40sub_group_non_uniform_scan_exclusive_addDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z40sub_group_non_uniform_scan_exclusive_mulDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z40sub_group_non_uniform_scan_exclusive_minDh(half 0xH0000)
+; CHECK-LLVM: call spir_func half @_Z40sub_group_non_uniform_scan_exclusive_maxDh(half 0xH0000)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticHalf(half addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !26 !kernel_arg_base_type !26 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func half @_Z32sub_group_non_uniform_reduce_addDh(half 0xH0000) #2
+  store half %2, half addrspace(1)* %0, align 2, !tbaa !27
+  %3 = tail call spir_func half @_Z32sub_group_non_uniform_reduce_mulDh(half 0xH0000) #2
+  %4 = getelementptr inbounds half, half addrspace(1)* %0, i64 1
+  store half %3, half addrspace(1)* %4, align 2, !tbaa !27
+  %5 = tail call spir_func half @_Z32sub_group_non_uniform_reduce_minDh(half 0xH0000) #2
+  %6 = getelementptr inbounds half, half addrspace(1)* %0, i64 2
+  store half %5, half addrspace(1)* %6, align 2, !tbaa !27
+  %7 = tail call spir_func half @_Z32sub_group_non_uniform_reduce_maxDh(half 0xH0000) #2
+  %8 = getelementptr inbounds half, half addrspace(1)* %0, i64 3
+  store half %7, half addrspace(1)* %8, align 2, !tbaa !27
+  %9 = tail call spir_func half @_Z40sub_group_non_uniform_scan_inclusive_addDh(half 0xH0000) #2
+  %10 = getelementptr inbounds half, half addrspace(1)* %0, i64 4
+  store half %9, half addrspace(1)* %10, align 2, !tbaa !27
+  %11 = tail call spir_func half @_Z40sub_group_non_uniform_scan_inclusive_mulDh(half 0xH0000) #2
+  %12 = getelementptr inbounds half, half addrspace(1)* %0, i64 5
+  store half %11, half addrspace(1)* %12, align 2, !tbaa !27
+  %13 = tail call spir_func half @_Z40sub_group_non_uniform_scan_inclusive_minDh(half 0xH0000) #2
+  %14 = getelementptr inbounds half, half addrspace(1)* %0, i64 6
+  store half %13, half addrspace(1)* %14, align 2, !tbaa !27
+  %15 = tail call spir_func half @_Z40sub_group_non_uniform_scan_inclusive_maxDh(half 0xH0000) #2
+  %16 = getelementptr inbounds half, half addrspace(1)* %0, i64 7
+  store half %15, half addrspace(1)* %16, align 2, !tbaa !27
+  %17 = tail call spir_func half @_Z40sub_group_non_uniform_scan_exclusive_addDh(half 0xH0000) #2
+  %18 = getelementptr inbounds half, half addrspace(1)* %0, i64 8
+  store half %17, half addrspace(1)* %18, align 2, !tbaa !27
+  %19 = tail call spir_func half @_Z40sub_group_non_uniform_scan_exclusive_mulDh(half 0xH0000) #2
+  %20 = getelementptr inbounds half, half addrspace(1)* %0, i64 9
+  store half %19, half addrspace(1)* %20, align 2, !tbaa !27
+  %21 = tail call spir_func half @_Z40sub_group_non_uniform_scan_exclusive_minDh(half 0xH0000) #2
+  %22 = getelementptr inbounds half, half addrspace(1)* %0, i64 10
+  store half %21, half addrspace(1)* %22, align 2, !tbaa !27
+  %23 = tail call spir_func half @_Z40sub_group_non_uniform_scan_exclusive_maxDh(half 0xH0000) #2
+  %24 = getelementptr inbounds half, half addrspace(1)* %0, i64 11
+  store half %23, half addrspace(1)* %24, align 2, !tbaa !27
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z32sub_group_non_uniform_reduce_addDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z32sub_group_non_uniform_reduce_mulDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z32sub_group_non_uniform_reduce_minDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z32sub_group_non_uniform_reduce_maxDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z40sub_group_non_uniform_scan_inclusive_addDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z40sub_group_non_uniform_scan_inclusive_mulDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z40sub_group_non_uniform_scan_inclusive_minDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z40sub_group_non_uniform_scan_inclusive_maxDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z40sub_group_non_uniform_scan_exclusive_addDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z40sub_group_non_uniform_scan_exclusive_mulDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z40sub_group_non_uniform_scan_exclusive_minDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z40sub_group_non_uniform_scan_exclusive_maxDh(half) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformFAdd [[double]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFMul [[double]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFMin [[double]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFMax [[double]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFAdd [[double]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFMul [[double]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFMin [[double]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFMax [[double]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFAdd [[double]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFMul [[double]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFMin [[double]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[double_0]]
+; CHECK-SPIRV: GroupNonUniformFMax [[double]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[double_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformArithmeticDouble
+; CHECK-LLVM: call spir_func double @_Z32sub_group_non_uniform_reduce_addd(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z32sub_group_non_uniform_reduce_muld(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z32sub_group_non_uniform_reduce_mind(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z32sub_group_non_uniform_reduce_maxd(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z40sub_group_non_uniform_scan_inclusive_addd(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z40sub_group_non_uniform_scan_inclusive_muld(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z40sub_group_non_uniform_scan_inclusive_mind(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z40sub_group_non_uniform_scan_inclusive_maxd(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z40sub_group_non_uniform_scan_exclusive_addd(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z40sub_group_non_uniform_scan_exclusive_muld(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z40sub_group_non_uniform_scan_exclusive_mind(double 0.000000e+00)
+; CHECK-LLVM: call spir_func double @_Z40sub_group_non_uniform_scan_exclusive_maxd(double 0.000000e+00)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformArithmeticDouble(double addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !29 !kernel_arg_base_type !29 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func double @_Z32sub_group_non_uniform_reduce_addd(double 0.000000e+00) #2
+  store double %2, double addrspace(1)* %0, align 8, !tbaa !30
+  %3 = tail call spir_func double @_Z32sub_group_non_uniform_reduce_muld(double 0.000000e+00) #2
+  %4 = getelementptr inbounds double, double addrspace(1)* %0, i64 1
+  store double %3, double addrspace(1)* %4, align 8, !tbaa !30
+  %5 = tail call spir_func double @_Z32sub_group_non_uniform_reduce_mind(double 0.000000e+00) #2
+  %6 = getelementptr inbounds double, double addrspace(1)* %0, i64 2
+  store double %5, double addrspace(1)* %6, align 8, !tbaa !30
+  %7 = tail call spir_func double @_Z32sub_group_non_uniform_reduce_maxd(double 0.000000e+00) #2
+  %8 = getelementptr inbounds double, double addrspace(1)* %0, i64 3
+  store double %7, double addrspace(1)* %8, align 8, !tbaa !30
+  %9 = tail call spir_func double @_Z40sub_group_non_uniform_scan_inclusive_addd(double 0.000000e+00) #2
+  %10 = getelementptr inbounds double, double addrspace(1)* %0, i64 4
+  store double %9, double addrspace(1)* %10, align 8, !tbaa !30
+  %11 = tail call spir_func double @_Z40sub_group_non_uniform_scan_inclusive_muld(double 0.000000e+00) #2
+  %12 = getelementptr inbounds double, double addrspace(1)* %0, i64 5
+  store double %11, double addrspace(1)* %12, align 8, !tbaa !30
+  %13 = tail call spir_func double @_Z40sub_group_non_uniform_scan_inclusive_mind(double 0.000000e+00) #2
+  %14 = getelementptr inbounds double, double addrspace(1)* %0, i64 6
+  store double %13, double addrspace(1)* %14, align 8, !tbaa !30
+  %15 = tail call spir_func double @_Z40sub_group_non_uniform_scan_inclusive_maxd(double 0.000000e+00) #2
+  %16 = getelementptr inbounds double, double addrspace(1)* %0, i64 7
+  store double %15, double addrspace(1)* %16, align 8, !tbaa !30
+  %17 = tail call spir_func double @_Z40sub_group_non_uniform_scan_exclusive_addd(double 0.000000e+00) #2
+  %18 = getelementptr inbounds double, double addrspace(1)* %0, i64 8
+  store double %17, double addrspace(1)* %18, align 8, !tbaa !30
+  %19 = tail call spir_func double @_Z40sub_group_non_uniform_scan_exclusive_muld(double 0.000000e+00) #2
+  %20 = getelementptr inbounds double, double addrspace(1)* %0, i64 9
+  store double %19, double addrspace(1)* %20, align 8, !tbaa !30
+  %21 = tail call spir_func double @_Z40sub_group_non_uniform_scan_exclusive_mind(double 0.000000e+00) #2
+  %22 = getelementptr inbounds double, double addrspace(1)* %0, i64 10
+  store double %21, double addrspace(1)* %22, align 8, !tbaa !30
+  %23 = tail call spir_func double @_Z40sub_group_non_uniform_scan_exclusive_maxd(double 0.000000e+00) #2
+  %24 = getelementptr inbounds double, double addrspace(1)* %0, i64 11
+  store double %23, double addrspace(1)* %24, align 8, !tbaa !30
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z32sub_group_non_uniform_reduce_addd(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z32sub_group_non_uniform_reduce_muld(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z32sub_group_non_uniform_reduce_mind(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z32sub_group_non_uniform_reduce_maxd(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z40sub_group_non_uniform_scan_inclusive_addd(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z40sub_group_non_uniform_scan_inclusive_muld(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z40sub_group_non_uniform_scan_inclusive_mind(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z40sub_group_non_uniform_scan_inclusive_maxd(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z40sub_group_non_uniform_scan_exclusive_addd(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z40sub_group_non_uniform_scan_exclusive_muld(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z40sub_group_non_uniform_scan_exclusive_mind(double) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z40sub_group_non_uniform_scan_exclusive_maxd(double) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBitwiseChar
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_andc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z31sub_group_non_uniform_reduce_orc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_xorc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_andc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z39sub_group_non_uniform_scan_inclusive_orc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_xorc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_andc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z39sub_group_non_uniform_scan_exclusive_orc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_xorc(i8 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBitwiseChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i8 @_Z32sub_group_non_uniform_reduce_andc(i8 signext 0) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func signext i8 @_Z31sub_group_non_uniform_reduce_orc(i8 signext 0) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  %5 = tail call spir_func signext i8 @_Z32sub_group_non_uniform_reduce_xorc(i8 signext 0) #2
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !7
+  %7 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_andc(i8 signext 0) #2
+  %8 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 3
+  store i8 %7, i8 addrspace(1)* %8, align 1, !tbaa !7
+  %9 = tail call spir_func signext i8 @_Z39sub_group_non_uniform_scan_inclusive_orc(i8 signext 0) #2
+  %10 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 4
+  store i8 %9, i8 addrspace(1)* %10, align 1, !tbaa !7
+  %11 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_xorc(i8 signext 0) #2
+  %12 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 5
+  store i8 %11, i8 addrspace(1)* %12, align 1, !tbaa !7
+  %13 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_andc(i8 signext 0) #2
+  %14 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 6
+  store i8 %13, i8 addrspace(1)* %14, align 1, !tbaa !7
+  %15 = tail call spir_func signext i8 @_Z39sub_group_non_uniform_scan_exclusive_orc(i8 signext 0) #2
+  %16 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 7
+  store i8 %15, i8 addrspace(1)* %16, align 1, !tbaa !7
+  %17 = tail call spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_xorc(i8 signext 0) #2
+  %18 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 8
+  store i8 %17, i8 addrspace(1)* %18, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z32sub_group_non_uniform_reduce_andc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z31sub_group_non_uniform_reduce_orc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z32sub_group_non_uniform_reduce_xorc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_andc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z39sub_group_non_uniform_scan_inclusive_orc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_inclusive_xorc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_andc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z39sub_group_non_uniform_scan_exclusive_orc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z40sub_group_non_uniform_scan_exclusive_xorc(i8 signext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[char_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBitwiseUChar
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_andc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z31sub_group_non_uniform_reduce_orc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z32sub_group_non_uniform_reduce_xorc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_andc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z39sub_group_non_uniform_scan_inclusive_orc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_inclusive_xorc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_andc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z39sub_group_non_uniform_scan_exclusive_orc(i8 0)
+; CHECK-LLVM: call spir_func i8 @_Z40sub_group_non_uniform_scan_exclusive_xorc(i8 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBitwiseUChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_andh(i8 zeroext 0) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func zeroext i8 @_Z31sub_group_non_uniform_reduce_orh(i8 zeroext 0) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  %5 = tail call spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_xorh(i8 zeroext 0) #2
+  %6 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 2
+  store i8 %5, i8 addrspace(1)* %6, align 1, !tbaa !7
+  %7 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_andh(i8 zeroext 0) #2
+  %8 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 3
+  store i8 %7, i8 addrspace(1)* %8, align 1, !tbaa !7
+  %9 = tail call spir_func zeroext i8 @_Z39sub_group_non_uniform_scan_inclusive_orh(i8 zeroext 0) #2
+  %10 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 4
+  store i8 %9, i8 addrspace(1)* %10, align 1, !tbaa !7
+  %11 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_xorh(i8 zeroext 0) #2
+  %12 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 5
+  store i8 %11, i8 addrspace(1)* %12, align 1, !tbaa !7
+  %13 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_andh(i8 zeroext 0) #2
+  %14 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 6
+  store i8 %13, i8 addrspace(1)* %14, align 1, !tbaa !7
+  %15 = tail call spir_func zeroext i8 @_Z39sub_group_non_uniform_scan_exclusive_orh(i8 zeroext 0) #2
+  %16 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 7
+  store i8 %15, i8 addrspace(1)* %16, align 1, !tbaa !7
+  %17 = tail call spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_xorh(i8 zeroext 0) #2
+  %18 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 8
+  store i8 %17, i8 addrspace(1)* %18, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_andh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z31sub_group_non_uniform_reduce_orh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z32sub_group_non_uniform_reduce_xorh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_andh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z39sub_group_non_uniform_scan_inclusive_orh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_inclusive_xorh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_andh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z39sub_group_non_uniform_scan_exclusive_orh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z40sub_group_non_uniform_scan_exclusive_xorh(i8 zeroext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBitwiseShort
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_ands(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z31sub_group_non_uniform_reduce_ors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_xors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_ands(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z39sub_group_non_uniform_scan_inclusive_ors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_xors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_ands(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z39sub_group_non_uniform_scan_exclusive_ors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_xors(i16 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBitwiseShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !11 !kernel_arg_base_type !11 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i16 @_Z32sub_group_non_uniform_reduce_ands(i16 signext 0) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func signext i16 @_Z31sub_group_non_uniform_reduce_ors(i16 signext 0) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  %5 = tail call spir_func signext i16 @_Z32sub_group_non_uniform_reduce_xors(i16 signext 0) #2
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !12
+  %7 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_ands(i16 signext 0) #2
+  %8 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 3
+  store i16 %7, i16 addrspace(1)* %8, align 2, !tbaa !12
+  %9 = tail call spir_func signext i16 @_Z39sub_group_non_uniform_scan_inclusive_ors(i16 signext 0) #2
+  %10 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 4
+  store i16 %9, i16 addrspace(1)* %10, align 2, !tbaa !12
+  %11 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_xors(i16 signext 0) #2
+  %12 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 5
+  store i16 %11, i16 addrspace(1)* %12, align 2, !tbaa !12
+  %13 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_ands(i16 signext 0) #2
+  %14 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 6
+  store i16 %13, i16 addrspace(1)* %14, align 2, !tbaa !12
+  %15 = tail call spir_func signext i16 @_Z39sub_group_non_uniform_scan_exclusive_ors(i16 signext 0) #2
+  %16 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 7
+  store i16 %15, i16 addrspace(1)* %16, align 2, !tbaa !12
+  %17 = tail call spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_xors(i16 signext 0) #2
+  %18 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 8
+  store i16 %17, i16 addrspace(1)* %18, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z32sub_group_non_uniform_reduce_ands(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z31sub_group_non_uniform_reduce_ors(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z32sub_group_non_uniform_reduce_xors(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_ands(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z39sub_group_non_uniform_scan_inclusive_ors(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_inclusive_xors(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_ands(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z39sub_group_non_uniform_scan_exclusive_ors(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z40sub_group_non_uniform_scan_exclusive_xors(i16 signext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[short_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBitwiseUShort
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_ands(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z31sub_group_non_uniform_reduce_ors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z32sub_group_non_uniform_reduce_xors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_ands(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z39sub_group_non_uniform_scan_inclusive_ors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_inclusive_xors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_ands(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z39sub_group_non_uniform_scan_exclusive_ors(i16 0)
+; CHECK-LLVM: call spir_func i16 @_Z40sub_group_non_uniform_scan_exclusive_xors(i16 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBitwiseUShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_andt(i16 zeroext 0) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func zeroext i16 @_Z31sub_group_non_uniform_reduce_ort(i16 zeroext 0) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  %5 = tail call spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_xort(i16 zeroext 0) #2
+  %6 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 2
+  store i16 %5, i16 addrspace(1)* %6, align 2, !tbaa !12
+  %7 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_andt(i16 zeroext 0) #2
+  %8 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 3
+  store i16 %7, i16 addrspace(1)* %8, align 2, !tbaa !12
+  %9 = tail call spir_func zeroext i16 @_Z39sub_group_non_uniform_scan_inclusive_ort(i16 zeroext 0) #2
+  %10 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 4
+  store i16 %9, i16 addrspace(1)* %10, align 2, !tbaa !12
+  %11 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_xort(i16 zeroext 0) #2
+  %12 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 5
+  store i16 %11, i16 addrspace(1)* %12, align 2, !tbaa !12
+  %13 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_andt(i16 zeroext 0) #2
+  %14 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 6
+  store i16 %13, i16 addrspace(1)* %14, align 2, !tbaa !12
+  %15 = tail call spir_func zeroext i16 @_Z39sub_group_non_uniform_scan_exclusive_ort(i16 zeroext 0) #2
+  %16 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 7
+  store i16 %15, i16 addrspace(1)* %16, align 2, !tbaa !12
+  %17 = tail call spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_xort(i16 zeroext 0) #2
+  %18 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 8
+  store i16 %17, i16 addrspace(1)* %18, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_andt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z31sub_group_non_uniform_reduce_ort(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z32sub_group_non_uniform_reduce_xort(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_andt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z39sub_group_non_uniform_scan_inclusive_ort(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_inclusive_xort(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_andt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z39sub_group_non_uniform_scan_exclusive_ort(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z40sub_group_non_uniform_scan_exclusive_xort(i16 zeroext) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBitwiseInt
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_andi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_reduce_ori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_xori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_andi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z39sub_group_non_uniform_scan_inclusive_ori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_xori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_andi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z39sub_group_non_uniform_scan_exclusive_ori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_xori(i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBitwiseInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_andi(i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z31sub_group_non_uniform_reduce_ori(i32 0) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_xori(i32 0) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  %7 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_andi(i32 0) #2
+  %8 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 3
+  store i32 %7, i32 addrspace(1)* %8, align 4, !tbaa !16
+  %9 = tail call spir_func i32 @_Z39sub_group_non_uniform_scan_inclusive_ori(i32 0) #2
+  %10 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 4
+  store i32 %9, i32 addrspace(1)* %10, align 4, !tbaa !16
+  %11 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_xori(i32 0) #2
+  %12 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 5
+  store i32 %11, i32 addrspace(1)* %12, align 4, !tbaa !16
+  %13 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_andi(i32 0) #2
+  %14 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 6
+  store i32 %13, i32 addrspace(1)* %14, align 4, !tbaa !16
+  %15 = tail call spir_func i32 @_Z39sub_group_non_uniform_scan_exclusive_ori(i32 0) #2
+  %16 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 7
+  store i32 %15, i32 addrspace(1)* %16, align 4, !tbaa !16
+  %17 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_xori(i32 0) #2
+  %18 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 8
+  store i32 %17, i32 addrspace(1)* %18, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_andi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_reduce_ori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_xori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_andi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z39sub_group_non_uniform_scan_inclusive_ori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_xori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_andi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z39sub_group_non_uniform_scan_exclusive_ori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_xori(i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBitwiseUInt
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_andi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_reduce_ori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z32sub_group_non_uniform_reduce_xori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_andi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z39sub_group_non_uniform_scan_inclusive_ori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_xori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_andi(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z39sub_group_non_uniform_scan_exclusive_ori(i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_xori(i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBitwiseUInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !18 !kernel_arg_base_type !18 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_andj(i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z31sub_group_non_uniform_reduce_orj(i32 0) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z32sub_group_non_uniform_reduce_xorj(i32 0) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  %7 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_andj(i32 0) #2
+  %8 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 3
+  store i32 %7, i32 addrspace(1)* %8, align 4, !tbaa !16
+  %9 = tail call spir_func i32 @_Z39sub_group_non_uniform_scan_inclusive_orj(i32 0) #2
+  %10 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 4
+  store i32 %9, i32 addrspace(1)* %10, align 4, !tbaa !16
+  %11 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_xorj(i32 0) #2
+  %12 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 5
+  store i32 %11, i32 addrspace(1)* %12, align 4, !tbaa !16
+  %13 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_andj(i32 0) #2
+  %14 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 6
+  store i32 %13, i32 addrspace(1)* %14, align 4, !tbaa !16
+  %15 = tail call spir_func i32 @_Z39sub_group_non_uniform_scan_exclusive_orj(i32 0) #2
+  %16 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 7
+  store i32 %15, i32 addrspace(1)* %16, align 4, !tbaa !16
+  %17 = tail call spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_xorj(i32 0) #2
+  %18 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 8
+  store i32 %17, i32 addrspace(1)* %18, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_andj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_reduce_orj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z32sub_group_non_uniform_reduce_xorj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_andj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z39sub_group_non_uniform_scan_inclusive_orj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_inclusive_xorj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_andj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z39sub_group_non_uniform_scan_exclusive_orj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_scan_exclusive_xorj(i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBitwiseLong
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_andl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z31sub_group_non_uniform_reduce_orl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_xorl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_andl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z39sub_group_non_uniform_scan_inclusive_orl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_xorl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_andl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z39sub_group_non_uniform_scan_exclusive_orl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_xorl(i64 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBitwiseLong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !19 !kernel_arg_base_type !19 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_andl(i64 0) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z31sub_group_non_uniform_reduce_orl(i64 0) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  %5 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_xorl(i64 0) #2
+  %6 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 2
+  store i64 %5, i64 addrspace(1)* %6, align 8, !tbaa !20
+  %7 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_andl(i64 0) #2
+  %8 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 3
+  store i64 %7, i64 addrspace(1)* %8, align 8, !tbaa !20
+  %9 = tail call spir_func i64 @_Z39sub_group_non_uniform_scan_inclusive_orl(i64 0) #2
+  %10 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 4
+  store i64 %9, i64 addrspace(1)* %10, align 8, !tbaa !20
+  %11 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_xorl(i64 0) #2
+  %12 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 5
+  store i64 %11, i64 addrspace(1)* %12, align 8, !tbaa !20
+  %13 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_andl(i64 0) #2
+  %14 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 6
+  store i64 %13, i64 addrspace(1)* %14, align 8, !tbaa !20
+  %15 = tail call spir_func i64 @_Z39sub_group_non_uniform_scan_exclusive_orl(i64 0) #2
+  %16 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 7
+  store i64 %15, i64 addrspace(1)* %16, align 8, !tbaa !20
+  %17 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_xorl(i64 0) #2
+  %18 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 8
+  store i64 %17, i64 addrspace(1)* %18, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_andl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z31sub_group_non_uniform_reduce_orl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_xorl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_andl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z39sub_group_non_uniform_scan_inclusive_orl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_xorl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_andl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z39sub_group_non_uniform_scan_exclusive_orl(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_xorl(i64) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseAnd [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseOr  [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: GroupNonUniformBitwiseXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[long_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformBitwiseULong
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_andl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z31sub_group_non_uniform_reduce_orl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z32sub_group_non_uniform_reduce_xorl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_andl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z39sub_group_non_uniform_scan_inclusive_orl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_xorl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_andl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z39sub_group_non_uniform_scan_exclusive_orl(i64 0)
+; CHECK-LLVM: call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_xorl(i64 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformBitwiseULong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !22 !kernel_arg_base_type !22 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_andm(i64 0) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z31sub_group_non_uniform_reduce_orm(i64 0) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  %5 = tail call spir_func i64 @_Z32sub_group_non_uniform_reduce_xorm(i64 0) #2
+  %6 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 2
+  store i64 %5, i64 addrspace(1)* %6, align 8, !tbaa !20
+  %7 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_andm(i64 0) #2
+  %8 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 3
+  store i64 %7, i64 addrspace(1)* %8, align 8, !tbaa !20
+  %9 = tail call spir_func i64 @_Z39sub_group_non_uniform_scan_inclusive_orm(i64 0) #2
+  %10 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 4
+  store i64 %9, i64 addrspace(1)* %10, align 8, !tbaa !20
+  %11 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_xorm(i64 0) #2
+  %12 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 5
+  store i64 %11, i64 addrspace(1)* %12, align 8, !tbaa !20
+  %13 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_andm(i64 0) #2
+  %14 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 6
+  store i64 %13, i64 addrspace(1)* %14, align 8, !tbaa !20
+  %15 = tail call spir_func i64 @_Z39sub_group_non_uniform_scan_exclusive_orm(i64 0) #2
+  %16 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 7
+  store i64 %15, i64 addrspace(1)* %16, align 8, !tbaa !20
+  %17 = tail call spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_xorm(i64 0) #2
+  %18 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 8
+  store i64 %17, i64 addrspace(1)* %18, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_andm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z31sub_group_non_uniform_reduce_orm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z32sub_group_non_uniform_reduce_xorm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_andm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z39sub_group_non_uniform_scan_inclusive_orm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_inclusive_xorm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_andm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z39sub_group_non_uniform_scan_exclusive_orm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z40sub_group_non_uniform_scan_exclusive_xorm(i64) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformLogicalAnd [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[false]]
+; CHECK-SPIRV: GroupNonUniformLogicalOr  [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[false]]
+; CHECK-SPIRV: GroupNonUniformLogicalXor [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 0 [[false]]
+; CHECK-SPIRV: GroupNonUniformLogicalAnd [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[false]]
+; CHECK-SPIRV: GroupNonUniformLogicalOr  [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[false]]
+; CHECK-SPIRV: GroupNonUniformLogicalXor [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 1 [[false]]
+; CHECK-SPIRV: GroupNonUniformLogicalAnd [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[false]]
+; CHECK-SPIRV: GroupNonUniformLogicalOr  [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[false]]
+; CHECK-SPIRV: GroupNonUniformLogicalXor [[bool]] {{[0-9]+}} [[ScopeSubgroup]] 2 [[false]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testNonUniformLogical
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_reduce_logical_andi(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z39sub_group_non_uniform_reduce_logical_ori(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z40sub_group_non_uniform_reduce_logical_xori(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z48sub_group_non_uniform_scan_inclusive_logical_andi(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z47sub_group_non_uniform_scan_inclusive_logical_ori(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z48sub_group_non_uniform_scan_inclusive_logical_xori(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z48sub_group_non_uniform_scan_exclusive_logical_andi(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z47sub_group_non_uniform_scan_exclusive_logical_ori(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z48sub_group_non_uniform_scan_exclusive_logical_xori(i32 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testNonUniformLogical(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z40sub_group_non_uniform_reduce_logical_andi(i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z39sub_group_non_uniform_reduce_logical_ori(i32 0) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  %5 = tail call spir_func i32 @_Z40sub_group_non_uniform_reduce_logical_xori(i32 0) #2
+  %6 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 2
+  store i32 %5, i32 addrspace(1)* %6, align 4, !tbaa !16
+  %7 = tail call spir_func i32 @_Z48sub_group_non_uniform_scan_inclusive_logical_andi(i32 0) #2
+  %8 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 3
+  store i32 %7, i32 addrspace(1)* %8, align 4, !tbaa !16
+  %9 = tail call spir_func i32 @_Z47sub_group_non_uniform_scan_inclusive_logical_ori(i32 0) #2
+  %10 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 4
+  store i32 %9, i32 addrspace(1)* %10, align 4, !tbaa !16
+  %11 = tail call spir_func i32 @_Z48sub_group_non_uniform_scan_inclusive_logical_xori(i32 0) #2
+  %12 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 5
+  store i32 %11, i32 addrspace(1)* %12, align 4, !tbaa !16
+  %13 = tail call spir_func i32 @_Z48sub_group_non_uniform_scan_exclusive_logical_andi(i32 0) #2
+  %14 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 6
+  store i32 %13, i32 addrspace(1)* %14, align 4, !tbaa !16
+  %15 = tail call spir_func i32 @_Z47sub_group_non_uniform_scan_exclusive_logical_ori(i32 0) #2
+  %16 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 7
+  store i32 %15, i32 addrspace(1)* %16, align 4, !tbaa !16
+  %17 = tail call spir_func i32 @_Z48sub_group_non_uniform_scan_exclusive_logical_xori(i32 0) #2
+  %18 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 8
+  store i32 %17, i32 addrspace(1)* %18, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_reduce_logical_andi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z39sub_group_non_uniform_reduce_logical_ori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z40sub_group_non_uniform_reduce_logical_xori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z48sub_group_non_uniform_scan_inclusive_logical_andi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z47sub_group_non_uniform_scan_inclusive_logical_ori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z48sub_group_non_uniform_scan_inclusive_logical_xori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z48sub_group_non_uniform_scan_exclusive_logical_andi(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z47sub_group_non_uniform_scan_exclusive_logical_ori(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z48sub_group_non_uniform_scan_exclusive_logical_xori(i32) local_unnamed_addr #1
+
+attributes #0 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { convergent nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{!"clang version 9.0.1 (https://github.com/llvm/llvm-project.git cb6d58d1dcf36a29ae5dd24ff891d6552f00bac7)"}
+!3 = !{i32 1}
+!4 = !{!"none"}
+!5 = !{!"char*"}
+!6 = !{!""}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"omnipotent char", !9, i64 0}
+!9 = !{!"Simple C/C++ TBAA"}
+!10 = !{!"uchar*"}
+!11 = !{!"short*"}
+!12 = !{!13, !13, i64 0}
+!13 = !{!"short", !8, i64 0}
+!14 = !{!"ushort*"}
+!15 = !{!"int*"}
+!16 = !{!17, !17, i64 0}
+!17 = !{!"int", !8, i64 0}
+!18 = !{!"uint*"}
+!19 = !{!"long*"}
+!20 = !{!21, !21, i64 0}
+!21 = !{!"long", !8, i64 0}
+!22 = !{!"ulong*"}
+!23 = !{!"float*"}
+!24 = !{!25, !25, i64 0}
+!25 = !{!"float", !8, i64 0}
+!26 = !{!"half*"}
+!27 = !{!28, !28, i64 0}
+!28 = !{!"half", !8, i64 0}
+!29 = !{!"double*"}
+!30 = !{!31, !31, i64 0}
+!31 = !{!"double", !8, i64 0}
\ No newline at end of file
diff --git a/llvm-spirv/test/transcoding/sub_group_non_uniform_vote.ll b/llvm-spirv/test/transcoding/sub_group_non_uniform_vote.ll
new file mode 100644
index 000000000000..5174eae28502
--- /dev/null
+++ b/llvm-spirv/test/transcoding/sub_group_non_uniform_vote.ll
@@ -0,0 +1,257 @@
+;; #pragma OPENCL EXTENSION cl_khr_subgroup_non_uniform_vote : enable
+;; 
+;; kernel void testSubGroupElect(global int* dst){
+;; 	dst[0] = sub_group_elect();
+;; }
+;; 
+;; kernel void testSubGroupNonUniformAll(global int* dst){
+;; 	dst[0] = sub_group_non_uniform_all(0); 
+;; }
+;; 
+;; kernel void testSubGroupNonUniformAny(global int* dst){
+;; 	dst[0] = sub_group_non_uniform_any(0);
+;; }
+;; 
+;; #pragma OPENCL EXTENSION cl_khr_fp16 : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp64 : enable
+;; kernel void testSubGroupNonUniformAllEqual(global int* dst){
+;;     {
+;;         char v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         uchar v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         short v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         ushort v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         int v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         uint v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         long v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         ulong v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         float v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         half v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;;     {
+;;         double v = 0;
+;;         dst[0] = sub_group_non_uniform_all_equal( v );
+;;     }
+;; }
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; Change DISABLED to RUN once SPIRV->LLVM translation is implemented
+; DISABLED: llvm-spirv -r %t.spv -o %t.rev.bc
+; DISABLED: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; ModuleID = 'sub_group_non_uniform_vote.cl'
+source_filename = "sub_group_non_uniform_vote.cl"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+; CHECK-SPIRV-DAG: {{[0-9]*}} Capability GroupNonUniform
+; CHECK-SPIRV-DAG: {{[0-9]*}} Capability GroupNonUniformVote
+
+; CHECK-SPIRV-DAG: TypeBool  [[bool:[0-9]+]]
+; CHECK-SPIRV-DAG: TypeInt   [[char:[0-9]+]]   8  0
+; CHECK-SPIRV-DAG: TypeInt   [[short:[0-9]+]]  16 0
+; CHECK-SPIRV-DAG: TypeInt   [[int:[0-9]+]]    32 0
+; CHECK-SPIRV-DAG: TypeInt   [[long:[0-9]+]]   64 0
+; CHECK-SPIRV-DAG: TypeFloat [[half:[0-9]+]]   16
+; CHECK-SPIRV-DAG: TypeFloat [[float:[0-9]+]]  32
+; CHECK-SPIRV-DAG: TypeFloat [[double:[0-9]+]] 64
+
+; CHECK-SPIRV-DAG: ConstantFalse [[bool]] [[false:[0-9]+]]
+; CHECK-SPIRV-DAG: Constant [[int]]    [[ScopeSubgroup:[0-9]+]] 3
+; CHECK-SPIRV-DAG: Constant [[char]]   [[char_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[short]]  [[short_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[int]]    [[int_0:[0-9]+]]         0
+; CHECK-SPIRV-DAG: Constant [[long]]   [[long_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[half]]   [[half_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[float]]  [[float_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[double]] [[double_0:[0-9]+]]      0
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformElect [[bool]] {{[0-9]+}} [[ScopeSubgroup]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testSubGroupElect
+; CHECK-LLVM: call spir_func i32 @_Z15sub_group_electv()
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testSubGroupElect(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z15sub_group_electv() #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z15sub_group_electv() local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformAll [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[false]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testSubGroupNonUniformAll
+; CHECK-LLVM: call spir_func i32 @_Z25sub_group_non_uniform_alli(i32 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testSubGroupNonUniformAll(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z25sub_group_non_uniform_alli(i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z25sub_group_non_uniform_alli(i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformAny [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[false]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testSubGroupNonUniformAny
+; CHECK-LLVM: call spir_func i32 @_Z25sub_group_non_uniform_anyi(i32 {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testSubGroupNonUniformAny(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z25sub_group_non_uniform_anyi(i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z25sub_group_non_uniform_anyi(i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[float_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[half_0]]
+; CHECK-SPIRV: GroupNonUniformAllEqual [[bool]] {{[0-9]+}} [[ScopeSubgroup]] [[double_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testSubGroupNonUniformAllEqual
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equalc(i8 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equalc(i8 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equals(i16 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equals(i16 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equali(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equali(i32 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equall(i64 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equall(i64 {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equalf(float {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equalDh(half {{.*}})
+; CHECK-LLVM: call spir_func i32 @_Z31sub_group_non_uniform_all_equald(double {{.*}})
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testSubGroupNonUniformAllEqual(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equalc(i8 signext 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %3 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equalh(i8 zeroext 0) #2
+  store i32 %3, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %4 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equals(i16 signext 0) #2
+  store i32 %4, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %5 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equalt(i16 zeroext 0) #2
+  store i32 %5, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %6 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equali(i32 0) #2
+  store i32 %6, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %7 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equalj(i32 0) #2
+  store i32 %7, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %8 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equall(i64 0) #2
+  store i32 %8, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %9 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equalm(i64 0) #2
+  store i32 %9, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %10 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equalf(float 0.000000e+00) #2
+  store i32 %10, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %11 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equalDh(half 0xH0000) #2
+  store i32 %11, i32 addrspace(1)* %0, align 4, !tbaa !7
+  %12 = tail call spir_func i32 @_Z31sub_group_non_uniform_all_equald(double 0.000000e+00) #2
+  store i32 %12, i32 addrspace(1)* %0, align 4, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equalc(i8 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equalh(i8 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equals(i16 signext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equalt(i16 zeroext) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equali(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equalj(i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equall(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equalm(i64) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equalf(float) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equalDh(half) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z31sub_group_non_uniform_all_equald(double) local_unnamed_addr #1
+
+attributes #0 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { convergent nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{!"clang version 9.0.1 (https://github.com/llvm/llvm-project.git cb6d58d1dcf36a29ae5dd24ff891d6552f00bac7)"}
+!3 = !{i32 1}
+!4 = !{!"none"}
+!5 = !{!"int*"}
+!6 = !{!""}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"int", !9, i64 0}
+!9 = !{!"omnipotent char", !10, i64 0}
+!10 = !{!"Simple C/C++ TBAA"}
diff --git a/llvm-spirv/test/transcoding/sub_group_shuffle.ll b/llvm-spirv/test/transcoding/sub_group_shuffle.ll
new file mode 100644
index 000000000000..b25281562af0
--- /dev/null
+++ b/llvm-spirv/test/transcoding/sub_group_shuffle.ll
@@ -0,0 +1,432 @@
+;; #pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp16 : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp64 : enable
+;; 
+;; kernel void testShuffleChar(global char* dst)
+;; {
+;; 	char v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleUChar(global uchar* dst)
+;; {
+;; 	uchar v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleShort(global short* dst)
+;; {
+;; 	short v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleUShort(global ushort* dst)
+;; {
+;; 	ushort v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleInt(global int* dst)
+;; {
+;; 	int v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleUInt(global uint* dst)
+;; {
+;; 	uint v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleLong(global long* dst)
+;; {
+;; 	long v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleULong(global ulong* dst)
+;; {
+;; 	ulong v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleFloat(global float* dst)
+;; {
+;; 	float v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleHalf(global half* dst)
+;; {
+;; 	half v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleDouble(global double* dst)
+;; {
+;; 	double v = 0;
+;;     dst[0] = sub_group_shuffle( v, 0 );
+;;     dst[1] = sub_group_shuffle_xor( v, 0 );
+;; }
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; Change DISABLED to RUN once SPIRV->LLVM translation is implemented
+; DISABLED: llvm-spirv -r %t.spv -o %t.rev.bc
+; DISABLED: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV-DAG: {{[0-9]*}} Capability GroupNonUniformShuffle
+
+; CHECK-SPIRV-DAG: TypeInt   [[char:[0-9]+]]   8  0
+; CHECK-SPIRV-DAG: TypeInt   [[short:[0-9]+]]  16 0
+; CHECK-SPIRV-DAG: TypeInt   [[int:[0-9]+]]    32 0
+; CHECK-SPIRV-DAG: TypeInt   [[long:[0-9]+]]   64 0
+; CHECK-SPIRV-DAG: TypeFloat [[half:[0-9]+]]   16
+; CHECK-SPIRV-DAG: TypeFloat [[float:[0-9]+]]  32
+; CHECK-SPIRV-DAG: TypeFloat [[double:[0-9]+]] 64
+
+; CHECK-SPIRV-DAG: Constant [[int]]    [[ScopeSubgroup:[0-9]+]] 3
+; CHECK-SPIRV-DAG: Constant [[char]]   [[char_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[short]]  [[short_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[int]]    [[int_0:[0-9]+]]         0
+; CHECK-SPIRV-DAG: Constant [[long]]   [[long_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[half]]   [[half_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[float]]  [[float_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[double]] [[double_0:[0-9]+]]      0
+
+; ModuleID = 'sub_group_shuffle.cl'
+source_filename = "sub_group_shuffle.cl"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleChar
+; CHECK-LLVM: call spir_func i8 @_Z17sub_group_shufflecj(i8 0, i32 0)
+; CHECK-LLVM: call spir_func i8 @_Z21sub_group_shuffle_xorcj(i8 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i8 @_Z17sub_group_shufflecj(i8 signext 0, i32 0) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func signext i8 @_Z21sub_group_shuffle_xorcj(i8 signext 0, i32 0) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z17sub_group_shufflecj(i8 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z21sub_group_shuffle_xorcj(i8 signext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleUChar
+; CHECK-LLVM: call spir_func i8 @_Z17sub_group_shufflecj(i8 0, i32 0)
+; CHECK-LLVM: call spir_func i8 @_Z21sub_group_shuffle_xorcj(i8 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleUChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i8 @_Z17sub_group_shufflehj(i8 zeroext 0, i32 0) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func zeroext i8 @_Z21sub_group_shuffle_xorhj(i8 zeroext 0, i32 0) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z17sub_group_shufflehj(i8 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z21sub_group_shuffle_xorhj(i8 zeroext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleShort
+; CHECK-LLVM: call spir_func i16 @_Z17sub_group_shufflesj(i16 0, i32 0)
+; CHECK-LLVM: call spir_func i16 @_Z21sub_group_shuffle_xorsj(i16 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !11 !kernel_arg_base_type !11 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i16 @_Z17sub_group_shufflesj(i16 signext 0, i32 0) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func signext i16 @_Z21sub_group_shuffle_xorsj(i16 signext 0, i32 0) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z17sub_group_shufflesj(i16 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z21sub_group_shuffle_xorsj(i16 signext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleUShort
+; CHECK-LLVM: call spir_func i16 @_Z17sub_group_shufflesj(i16 0, i32 0)
+; CHECK-LLVM: call spir_func i16 @_Z21sub_group_shuffle_xorsj(i16 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleUShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i16 @_Z17sub_group_shuffletj(i16 zeroext 0, i32 0) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func zeroext i16 @_Z21sub_group_shuffle_xortj(i16 zeroext 0, i32 0) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z17sub_group_shuffletj(i16 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z21sub_group_shuffle_xortj(i16 zeroext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleInt
+; CHECK-LLVM: call spir_func i32 @_Z17sub_group_shuffleij(i32 0, i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z21sub_group_shuffle_xorij(i32 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z17sub_group_shuffleij(i32 0, i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z21sub_group_shuffle_xorij(i32 0, i32 0) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z17sub_group_shuffleij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z21sub_group_shuffle_xorij(i32, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleUInt
+; CHECK-LLVM: call spir_func i32 @_Z17sub_group_shuffleij(i32 0, i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z21sub_group_shuffle_xorij(i32 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleUInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !18 !kernel_arg_base_type !18 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z17sub_group_shufflejj(i32 0, i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z21sub_group_shuffle_xorjj(i32 0, i32 0) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z17sub_group_shufflejj(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z21sub_group_shuffle_xorjj(i32, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleLong
+; CHECK-LLVM: call spir_func i64 @_Z17sub_group_shufflelj(i64 0, i32 0)
+; CHECK-LLVM: call spir_func i64 @_Z21sub_group_shuffle_xorlj(i64 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleLong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !19 !kernel_arg_base_type !19 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z17sub_group_shufflelj(i64 0, i32 0) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z21sub_group_shuffle_xorlj(i64 0, i32 0) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z17sub_group_shufflelj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z21sub_group_shuffle_xorlj(i64, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleULong
+; CHECK-LLVM: call spir_func i64 @_Z17sub_group_shufflelj(i64 0, i32 0)
+; CHECK-LLVM: call spir_func i64 @_Z21sub_group_shuffle_xorlj(i64 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleULong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !22 !kernel_arg_base_type !22 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z17sub_group_shufflemj(i64 0, i32 0) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z21sub_group_shuffle_xormj(i64 0, i32 0) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z17sub_group_shufflemj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z21sub_group_shuffle_xormj(i64, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[float]] {{[0-9]+}} [[ScopeSubgroup]] [[float_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[float]] {{[0-9]+}} [[ScopeSubgroup]] [[float_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleFloat
+; CHECK-LLVM: call spir_func float @_Z17sub_group_shufflefj(float 0.000000e+00, i32 0)
+; CHECK-LLVM: call spir_func float @_Z21sub_group_shuffle_xorfj(float 0.000000e+00, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleFloat(float addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !23 !kernel_arg_base_type !23 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func float @_Z17sub_group_shufflefj(float 0.000000e+00, i32 0) #2
+  store float %2, float addrspace(1)* %0, align 4, !tbaa !24
+  %3 = tail call spir_func float @_Z21sub_group_shuffle_xorfj(float 0.000000e+00, i32 0) #2
+  %4 = getelementptr inbounds float, float addrspace(1)* %0, i64 1
+  store float %3, float addrspace(1)* %4, align 4, !tbaa !24
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z17sub_group_shufflefj(float, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z21sub_group_shuffle_xorfj(float, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[half]] {{[0-9]+}} [[ScopeSubgroup]] [[half_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[half]] {{[0-9]+}} [[ScopeSubgroup]] [[half_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleHalf
+; CHECK-LLVM: call spir_func half @_Z17sub_group_shuffleDhj(half 0xH0000, i32 0)
+; CHECK-LLVM: call spir_func half @_Z21sub_group_shuffle_xorDhj(half 0xH0000, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleHalf(half addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !26 !kernel_arg_base_type !26 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func half @_Z17sub_group_shuffleDhj(half 0xH0000, i32 0) #2
+  store half %2, half addrspace(1)* %0, align 2, !tbaa !27
+  %3 = tail call spir_func half @_Z21sub_group_shuffle_xorDhj(half 0xH0000, i32 0) #2
+  %4 = getelementptr inbounds half, half addrspace(1)* %0, i64 1
+  store half %3, half addrspace(1)* %4, align 2, !tbaa !27
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z17sub_group_shuffleDhj(half, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z21sub_group_shuffle_xorDhj(half, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffle [[double]] {{[0-9]+}} [[ScopeSubgroup]] [[double_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleXor [[double]] {{[0-9]+}} [[ScopeSubgroup]] [[double_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleDouble
+; CHECK-LLVM: call spir_func double @_Z17sub_group_shuffledj(double 0.000000e+00, i32 0)
+; CHECK-LLVM: call spir_func double @_Z21sub_group_shuffle_xordj(double 0.000000e+00, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleDouble(double addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !29 !kernel_arg_base_type !29 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func double @_Z17sub_group_shuffledj(double 0.000000e+00, i32 0) #2
+  store double %2, double addrspace(1)* %0, align 8, !tbaa !30
+  %3 = tail call spir_func double @_Z21sub_group_shuffle_xordj(double 0.000000e+00, i32 0) #2
+  %4 = getelementptr inbounds double, double addrspace(1)* %0, i64 1
+  store double %3, double addrspace(1)* %4, align 8, !tbaa !30
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z17sub_group_shuffledj(double, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z21sub_group_shuffle_xordj(double, i32) local_unnamed_addr #1
+
+attributes #0 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { convergent nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{!"clang version 9.0.1 (https://github.com/llvm/llvm-project.git cb6d58d1dcf36a29ae5dd24ff891d6552f00bac7)"}
+!3 = !{i32 1}
+!4 = !{!"none"}
+!5 = !{!"char*"}
+!6 = !{!""}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"omnipotent char", !9, i64 0}
+!9 = !{!"Simple C/C++ TBAA"}
+!10 = !{!"uchar*"}
+!11 = !{!"short*"}
+!12 = !{!13, !13, i64 0}
+!13 = !{!"short", !8, i64 0}
+!14 = !{!"ushort*"}
+!15 = !{!"int*"}
+!16 = !{!17, !17, i64 0}
+!17 = !{!"int", !8, i64 0}
+!18 = !{!"uint*"}
+!19 = !{!"long*"}
+!20 = !{!21, !21, i64 0}
+!21 = !{!"long", !8, i64 0}
+!22 = !{!"ulong*"}
+!23 = !{!"float*"}
+!24 = !{!25, !25, i64 0}
+!25 = !{!"float", !8, i64 0}
+!26 = !{!"half*"}
+!27 = !{!28, !28, i64 0}
+!28 = !{!"half", !8, i64 0}
+!29 = !{!"double*"}
+!30 = !{!31, !31, i64 0}
+!31 = !{!"double", !8, i64 0}
+
+
diff --git a/llvm-spirv/test/transcoding/sub_group_shuffle_relative.ll b/llvm-spirv/test/transcoding/sub_group_shuffle_relative.ll
new file mode 100644
index 000000000000..dd30aa65e11d
--- /dev/null
+++ b/llvm-spirv/test/transcoding/sub_group_shuffle_relative.ll
@@ -0,0 +1,430 @@
+;; #pragma OPENCL EXTENSION cl_khr_subgroup_shuffle_relative : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp16 : enable
+;; #pragma OPENCL EXTENSION cl_khr_fp64 : enable
+;; 
+;; kernel void testShuffleRelativeChar(global char* dst)
+;; {
+;; 	char v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeUChar(global uchar* dst)
+;; {
+;; 	uchar v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeShort(global short* dst)
+;; {
+;; 	short v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeUShort(global ushort* dst)
+;; {
+;; 	ushort v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeInt(global int* dst)
+;; {
+;; 	int v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeUInt(global uint* dst)
+;; {
+;; 	uint v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeLong(global long* dst)
+;; {
+;; 	long v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeULong(global ulong* dst)
+;; {
+;; 	ulong v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeFloat(global float* dst)
+;; {
+;; 	float v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeHalf(global half* dst)
+;; {
+;; 	half v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+;; 
+;; kernel void testShuffleRelativeDouble(global double* dst)
+;; {
+;; 	double v = 0;
+;;     dst[0] = sub_group_shuffle_up( v, 0 );
+;;     dst[1] = sub_group_shuffle_down( v, 0 );
+;; }
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; Change DISABLED to RUN once SPIRV->LLVM translation is implemented
+; DISABLED: llvm-spirv -r %t.spv -o %t.rev.bc
+; DISABLED: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV-DAG: {{[0-9]*}} Capability GroupNonUniformShuffleRelative
+
+; CHECK-SPIRV-DAG: TypeInt   [[char:[0-9]+]]   8  0
+; CHECK-SPIRV-DAG: TypeInt   [[short:[0-9]+]]  16 0
+; CHECK-SPIRV-DAG: TypeInt   [[int:[0-9]+]]    32 0
+; CHECK-SPIRV-DAG: TypeInt   [[long:[0-9]+]]   64 0
+; CHECK-SPIRV-DAG: TypeFloat [[half:[0-9]+]]   16
+; CHECK-SPIRV-DAG: TypeFloat [[float:[0-9]+]]  32
+; CHECK-SPIRV-DAG: TypeFloat [[double:[0-9]+]] 64
+
+; CHECK-SPIRV-DAG: Constant [[int]]    [[ScopeSubgroup:[0-9]+]] 3
+; CHECK-SPIRV-DAG: Constant [[char]]   [[char_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[short]]  [[short_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[int]]    [[int_0:[0-9]+]]         0
+; CHECK-SPIRV-DAG: Constant [[long]]   [[long_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[half]]   [[half_0:[0-9]+]]        0
+; CHECK-SPIRV-DAG: Constant [[float]]  [[float_0:[0-9]+]]       0
+; CHECK-SPIRV-DAG: Constant [[double]] [[double_0:[0-9]+]]      0
+
+; ModuleID = 'sub_group_shuffle_relative.cl'
+source_filename = "sub_group_shuffle_relative.cl"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeChar
+; CHECK-LLVM: call spir_func i8 @_Z20sub_group_shuffle_upcj(i8 0, i32 0)
+; CHECK-LLVM: call spir_func i8 @_Z22sub_group_shuffle_downcj(i8 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i8 @_Z20sub_group_shuffle_upcj(i8 signext 0, i32 0) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func signext i8 @_Z22sub_group_shuffle_downcj(i8 signext 0, i32 0) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z20sub_group_shuffle_upcj(i8 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i8 @_Z22sub_group_shuffle_downcj(i8 signext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[char]] {{[0-9]+}} [[ScopeSubgroup]] [[char_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeUChar
+; CHECK-LLVM: call spir_func i8 @_Z20sub_group_shuffle_upcj(i8 0, i32 0)
+; CHECK-LLVM: call spir_func i8 @_Z22sub_group_shuffle_downcj(i8 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeUChar(i8 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i8 @_Z20sub_group_shuffle_uphj(i8 zeroext 0, i32 0) #2
+  store i8 %2, i8 addrspace(1)* %0, align 1, !tbaa !7
+  %3 = tail call spir_func zeroext i8 @_Z22sub_group_shuffle_downhj(i8 zeroext 0, i32 0) #2
+  %4 = getelementptr inbounds i8, i8 addrspace(1)* %0, i64 1
+  store i8 %3, i8 addrspace(1)* %4, align 1, !tbaa !7
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z20sub_group_shuffle_uphj(i8 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i8 @_Z22sub_group_shuffle_downhj(i8 zeroext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeShort
+; CHECK-LLVM: call spir_func i16 @_Z20sub_group_shuffle_upsj(i16 0, i32 0)
+; CHECK-LLVM: call spir_func i16 @_Z22sub_group_shuffle_downsj(i16 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !11 !kernel_arg_base_type !11 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func signext i16 @_Z20sub_group_shuffle_upsj(i16 signext 0, i32 0) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func signext i16 @_Z22sub_group_shuffle_downsj(i16 signext 0, i32 0) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z20sub_group_shuffle_upsj(i16 signext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func signext i16 @_Z22sub_group_shuffle_downsj(i16 signext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[short]] {{[0-9]+}} [[ScopeSubgroup]] [[short_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeUShort
+; CHECK-LLVM: call spir_func i16 @_Z20sub_group_shuffle_upsj(i16 0, i32 0)
+; CHECK-LLVM: call spir_func i16 @_Z22sub_group_shuffle_downsj(i16 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeUShort(i16 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func zeroext i16 @_Z20sub_group_shuffle_uptj(i16 zeroext 0, i32 0) #2
+  store i16 %2, i16 addrspace(1)* %0, align 2, !tbaa !12
+  %3 = tail call spir_func zeroext i16 @_Z22sub_group_shuffle_downtj(i16 zeroext 0, i32 0) #2
+  %4 = getelementptr inbounds i16, i16 addrspace(1)* %0, i64 1
+  store i16 %3, i16 addrspace(1)* %4, align 2, !tbaa !12
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z20sub_group_shuffle_uptj(i16 zeroext, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func zeroext i16 @_Z22sub_group_shuffle_downtj(i16 zeroext, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeInt
+; CHECK-LLVM: call spir_func i32 @_Z20sub_group_shuffle_upij(i32 0, i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z22sub_group_shuffle_downij(i32 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z20sub_group_shuffle_upij(i32 0, i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z22sub_group_shuffle_downij(i32 0, i32 0) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z20sub_group_shuffle_upij(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z22sub_group_shuffle_downij(i32, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[int]] {{[0-9]+}} [[ScopeSubgroup]] [[int_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeUInt
+; CHECK-LLVM: call spir_func i32 @_Z20sub_group_shuffle_upij(i32 0, i32 0)
+; CHECK-LLVM: call spir_func i32 @_Z22sub_group_shuffle_downij(i32 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeUInt(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !18 !kernel_arg_base_type !18 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i32 @_Z20sub_group_shuffle_upjj(i32 0, i32 0) #2
+  store i32 %2, i32 addrspace(1)* %0, align 4, !tbaa !16
+  %3 = tail call spir_func i32 @_Z22sub_group_shuffle_downjj(i32 0, i32 0) #2
+  %4 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 1
+  store i32 %3, i32 addrspace(1)* %4, align 4, !tbaa !16
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z20sub_group_shuffle_upjj(i32, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i32 @_Z22sub_group_shuffle_downjj(i32, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeLong
+; CHECK-LLVM: call spir_func i64 @_Z20sub_group_shuffle_uplj(i64 0, i32 0)
+; CHECK-LLVM: call spir_func i64 @_Z22sub_group_shuffle_downlj(i64 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeLong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !19 !kernel_arg_base_type !19 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z20sub_group_shuffle_uplj(i64 0, i32 0) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z22sub_group_shuffle_downlj(i64 0, i32 0) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z20sub_group_shuffle_uplj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z22sub_group_shuffle_downlj(i64, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[long]] {{[0-9]+}} [[ScopeSubgroup]] [[long_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeULong
+; CHECK-LLVM: call spir_func i64 @_Z20sub_group_shuffle_uplj(i64 0, i32 0)
+; CHECK-LLVM: call spir_func i64 @_Z22sub_group_shuffle_downlj(i64 0, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeULong(i64 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !22 !kernel_arg_base_type !22 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func i64 @_Z20sub_group_shuffle_upmj(i64 0, i32 0) #2
+  store i64 %2, i64 addrspace(1)* %0, align 8, !tbaa !20
+  %3 = tail call spir_func i64 @_Z22sub_group_shuffle_downmj(i64 0, i32 0) #2
+  %4 = getelementptr inbounds i64, i64 addrspace(1)* %0, i64 1
+  store i64 %3, i64 addrspace(1)* %4, align 8, !tbaa !20
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z20sub_group_shuffle_upmj(i64, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func i64 @_Z22sub_group_shuffle_downmj(i64, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[float]] {{[0-9]+}} [[ScopeSubgroup]] [[float_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[float]] {{[0-9]+}} [[ScopeSubgroup]] [[float_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeFloat
+; CHECK-LLVM: call spir_func float @_Z20sub_group_shuffle_upfj(float 0.000000e+00, i32 0)
+; CHECK-LLVM: call spir_func float @_Z22sub_group_shuffle_downfj(float 0.000000e+00, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeFloat(float addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !23 !kernel_arg_base_type !23 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func float @_Z20sub_group_shuffle_upfj(float 0.000000e+00, i32 0) #2
+  store float %2, float addrspace(1)* %0, align 4, !tbaa !24
+  %3 = tail call spir_func float @_Z22sub_group_shuffle_downfj(float 0.000000e+00, i32 0) #2
+  %4 = getelementptr inbounds float, float addrspace(1)* %0, i64 1
+  store float %3, float addrspace(1)* %4, align 4, !tbaa !24
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z20sub_group_shuffle_upfj(float, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func float @_Z22sub_group_shuffle_downfj(float, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[half]] {{[0-9]+}} [[ScopeSubgroup]] [[half_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[half]] {{[0-9]+}} [[ScopeSubgroup]] [[half_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeHalf
+; CHECK-LLVM: call spir_func half @_Z20sub_group_shuffle_upDhj(half 0xH0000, i32 0)
+; CHECK-LLVM: call spir_func half @_Z22sub_group_shuffle_downDhj(half 0xH0000, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeHalf(half addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !26 !kernel_arg_base_type !26 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func half @_Z20sub_group_shuffle_upDhj(half 0xH0000, i32 0) #2
+  store half %2, half addrspace(1)* %0, align 2, !tbaa !27
+  %3 = tail call spir_func half @_Z22sub_group_shuffle_downDhj(half 0xH0000, i32 0) #2
+  %4 = getelementptr inbounds half, half addrspace(1)* %0, i64 1
+  store half %3, half addrspace(1)* %4, align 2, !tbaa !27
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z20sub_group_shuffle_upDhj(half, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func half @_Z22sub_group_shuffle_downDhj(half, i32) local_unnamed_addr #1
+
+; CHECK-SPIRV-LABEL: 5 Function
+; CHECK-SPIRV: GroupNonUniformShuffleUp [[double]] {{[0-9]+}} [[ScopeSubgroup]] [[double_0]] [[int_0]]
+; CHECK-SPIRV: GroupNonUniformShuffleDown [[double]] {{[0-9]+}} [[ScopeSubgroup]] [[double_0]] [[int_0]]
+; CHECK-SPIRV: FunctionEnd
+
+; CHECK-LLVM-LABEL: @testShuffleRelativeDouble
+; CHECK-LLVM: call spir_func double @_Z20sub_group_shuffle_updj(double 0.000000e+00, i32 0)
+; CHECK-LLVM: call spir_func double @_Z22sub_group_shuffle_downdj(double 0.000000e+00, i32 0)
+
+; Function Attrs: convergent nounwind
+define dso_local spir_kernel void @testShuffleRelativeDouble(double addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !29 !kernel_arg_base_type !29 !kernel_arg_type_qual !6 {
+  %2 = tail call spir_func double @_Z20sub_group_shuffle_updj(double 0.000000e+00, i32 0) #2
+  store double %2, double addrspace(1)* %0, align 8, !tbaa !30
+  %3 = tail call spir_func double @_Z22sub_group_shuffle_downdj(double 0.000000e+00, i32 0) #2
+  %4 = getelementptr inbounds double, double addrspace(1)* %0, i64 1
+  store double %3, double addrspace(1)* %4, align 8, !tbaa !30
+  ret void
+}
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z20sub_group_shuffle_updj(double, i32) local_unnamed_addr #1
+
+; Function Attrs: convergent
+declare dso_local spir_func double @_Z22sub_group_shuffle_downdj(double, i32) local_unnamed_addr #1
+
+attributes #0 = { convergent nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { convergent nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{!"clang version 9.0.1 (https://github.com/llvm/llvm-project.git cb6d58d1dcf36a29ae5dd24ff891d6552f00bac7)"}
+!3 = !{i32 1}
+!4 = !{!"none"}
+!5 = !{!"char*"}
+!6 = !{!""}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"omnipotent char", !9, i64 0}
+!9 = !{!"Simple C/C++ TBAA"}
+!10 = !{!"uchar*"}
+!11 = !{!"short*"}
+!12 = !{!13, !13, i64 0}
+!13 = !{!"short", !8, i64 0}
+!14 = !{!"ushort*"}
+!15 = !{!"int*"}
+!16 = !{!17, !17, i64 0}
+!17 = !{!"int", !8, i64 0}
+!18 = !{!"uint*"}
+!19 = !{!"long*"}
+!20 = !{!21, !21, i64 0}
+!21 = !{!"long", !8, i64 0}
+!22 = !{!"ulong*"}
+!23 = !{!"float*"}
+!24 = !{!25, !25, i64 0}
+!25 = !{!"float", !8, i64 0}
+!26 = !{!"half*"}
+!27 = !{!28, !28, i64 0}
+!28 = !{!"half", !8, i64 0}
+!29 = !{!"double*"}
+!30 = !{!31, !31, i64 0}
+!31 = !{!"double", !8, i64 0}
diff --git a/llvm-spirv/test/trap.ll b/llvm-spirv/test/trap.ll
new file mode 100644
index 000000000000..7366d3298516
--- /dev/null
+++ b/llvm-spirv/test/trap.ll
@@ -0,0 +1,40 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -spirv-text -o %t
+; RUN: FileCheck < %t %s
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: spirv-val %t.spv
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+; Function Attrs: nounwind
+; CHECK: Capability Addresses
+; CHECK: "foo"
+
+; Function Attrs: cold noreturn nounwind
+declare void @llvm.trap() #8
+
+define spir_kernel void @foo(i32 addrspace(1)* %a) #0 !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 {
+entry:
+  %a.addr = alloca i32 addrspace(1)*, align 4
+  store i32 addrspace(1)* %a, i32 addrspace(1)** %a.addr, align 4
+  call void @llvm.trap() #12
+  ret void
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #12 = { noreturn nounwind }
+
+!opencl.enable.FP_CONTRACT = !{}
+!opencl.spir.version = !{!6}
+!opencl.ocl.version = !{!6}
+!opencl.used.extensions = !{!7}
+!opencl.used.optional.core.features = !{!7}
+!opencl.compiler.options = !{!7}
+
+!1 = !{i32 1}
+!2 = !{!"none"}
+!3 = !{!"int*"}
+!4 = !{!"int*"}
+!5 = !{!""}
+!6 = !{i32 1, i32 2}
+!7 = !{}
diff --git a/llvm-spirv/tools/llvm-spirv/llvm-spirv.cpp b/llvm-spirv/tools/llvm-spirv/llvm-spirv.cpp
index 11d7b9533f83..ce4cd190dda3 100644
--- a/llvm-spirv/tools/llvm-spirv/llvm-spirv.cpp
+++ b/llvm-spirv/tools/llvm-spirv/llvm-spirv.cpp
@@ -102,7 +102,9 @@ static cl::opt<VersionNumber> MaxSPIRVVersion(
     "spirv-max-version",
     cl::desc("Choose maximum SPIR-V version which can be emitted"),
     cl::values(clEnumValN(VersionNumber::SPIRV_1_0, "1.0", "SPIR-V 1.0"),
-               clEnumValN(VersionNumber::SPIRV_1_1, "1.1", "SPIR-V 1.1")),
+               clEnumValN(VersionNumber::SPIRV_1_1, "1.1", "SPIR-V 1.1"),
+               clEnumValN(VersionNumber::SPIRV_1_2, "1.2", "SPIR-V 1.2"),
+               clEnumValN(VersionNumber::SPIRV_1_3, "1.3", "SPIR-V 1.3")),
     cl::init(VersionNumber::MaximumVersion));
 
 static cl::list<std::string>
diff --git a/sycl/doc/GetStartedGuide.md b/sycl/doc/GetStartedGuide.md
index 7001745cf919..7a99ab0e5052 100644
--- a/sycl/doc/GetStartedGuide.md
+++ b/sycl/doc/GetStartedGuide.md
@@ -161,16 +161,18 @@ which contains all the symbols required.
 To run DPC++ applications on OpenCL devices, OpenCL implementation(s) must be
 present in the system.
 
-The `GPU` and `CPU` runtimes as well as TBB runtime which are needed to run
-DPC++ application on Intel `GPU` or Intel `CPU` devices can be downloaded using
-links in [the dependency configuration file](../../buildbot/dependency.conf)
-and installed following the instructions below. The same versions are used in PR testing.
-
-Intel `CPU` runtime for OpenCL devices can be switched into Intel FPGA
-Emulation device for OpenCL. The following parameter should be set in `cl.cfg`
-file (available in directory containing CPU runtime for OpenCL) or environment
-variable with the same name. The following value should be set to switch OpenCL device
-mode:
+The OpenCL RT for `GPU`, OpenCL RT for `CPU` and TBB runtime which are needed
+to run DPC++ application on Intel `GPU` or Intel `CPU` devices can be
+downloaded using links in
+[the dependency configuration file](../../buildbot/dependency.conf)
+and installed following the instructions below. The same versions are used in
+PR testing.
+
+Intel OpenCL RT for `CPU` devices can be switched into OpenCL runtime for
+Intel FPGA Emulation. The following parameter should be set in `cl.cfg` file
+(available in directory containing CPU runtime for OpenCL) or environment
+variable with the same name. The following value should be set to switch
+OpenCL device mode:
 
 ```bash
 CL_CONFIG_DEVICES = fpga-emu
@@ -226,18 +228,25 @@ folder:
 
 **Windows (64-bit)**:
 
-1) If you need `GPU` as well, then update/install it first. Do it **before**
-installing `CPU` runtime as `GPU` runtime installer may re-write some important
-files or settings and make existing `CPU` runtime not working properly.
+1) If you need OpenCL runtime for Intel `GPU` as well, then update/install it
+first. Do it **before** installing OpenCL runtime for Intel `CPU` runtime as
+OpenCL runtime for Intel `GPU` installer may re-write some important
+files or settings and make existing OpenCL runtime for Intel `CPU` runtime
+not working properly.
+
+2) Extract the archive with OpenCL runtime for Intel `CPU` using links in
+[the dependency configuration file](../../buildbot/dependency.conf).  For
+example, to `c:\oclcpu_rt_<cpu_version>`.
 
-2) Extract the archive to some folder. For example, to
-`c:\oclcpu_rt_<cpu_version>` and `c:\tbb_<tbb_version>`.
+3) Extract the archive with TBB runtime using links in
+[the dependency configuration file](../../buildbot/dependency.conf).  For
+example, to `c:\tbb_<tbb_version>`.
 
-3) Run `Command Prompt` as `Administrator`. To do that click `Start` button,
+4) Run `Command Prompt` as `Administrator`. To do that click `Start` button,
 type `Command Prompt`, click the Right mouse button on it, then click
 `Run As Administrator`, then click `Yes` to confirm.
 
-4) In the opened windows run `install.bat` provided with the extracted files
+5) In the opened windows run `install.bat` provided with the extracted files
 to install runtime to the system and setup environment variables. So, if the
 extracted files are in `c:\oclcpu_rt_<cpu_version>\` folder, then type the
 command:
diff --git a/sycl/doc/extensions/ExplicitSIMD/ESIMD-TODO-list.md b/sycl/doc/extensions/ExplicitSIMD/ESIMD-TODO-list.md
new file mode 100644
index 000000000000..6ee6cc7fffa9
--- /dev/null
+++ b/sycl/doc/extensions/ExplicitSIMD/ESIMD-TODO-list.md
@@ -0,0 +1,10 @@
+### TODO list for the SYCL Explicit SIMD extension.
+
+A place for TODO items/feedback regarding the extension in addition to the
+github issues mechanism.
+
+#### Front-End
+
+1. Fix a generic (unrelated to ESIMD) issue [1811](https://github.com/intel/llvm/issues/1811) with lambda/functor function
+   detection. Needed to improve diagnostics, fix attribute propagation.  
+   ETA: ???
diff --git a/sycl/doc/extensions/README.md b/sycl/doc/extensions/README.md
index c9f1914a449a..4938fa36b967 100644
--- a/sycl/doc/extensions/README.md
+++ b/sycl/doc/extensions/README.md
@@ -7,7 +7,7 @@ DPC++ extensions status:
 
 |  Extension  |    Status   |   Comment   |
 |-------------|:------------|:------------|
-| [SYCL_INTEL_bitcast](Bitcast/SYCL_INTEL_bitcast.asciidoc)                                                                   | Proposal                                  | |
+| [SYCL_INTEL_bitcast](Bitcast/SYCL_INTEL_bitcast.asciidoc)                                                                   | Supported                                 | As sycl::detail::bit_cast |
 | [C and C++ Standard libraries support](C-CXX-StandardLibrary/C-CXX-StandardLibrary.rst)                                     | Partially supported(OpenCL: CPU, GPU)     | |
 | [SYCL_INTEL_data_flow_pipes](DataFlowPipes/data_flow_pipes.asciidoc)                                                        | Partially supported(OpenCL: ACCELERATOR)  | kernel_host_pipe_support part is not implemented |
 | [SYCL_INTEL_deduction_guides](deduction_guides/SYCL_INTEL_deduction_guides.asciidoc)                                        | Supported                                 | |
diff --git a/sycl/include/CL/sycl/detail/helpers.hpp b/sycl/include/CL/sycl/detail/helpers.hpp
index 024801274b00..d71c5be9e618 100644
--- a/sycl/include/CL/sycl/detail/helpers.hpp
+++ b/sycl/include/CL/sycl/detail/helpers.hpp
@@ -17,6 +17,7 @@
 #include <CL/sycl/detail/type_traits.hpp>
 
 #include <memory>
+#include <numeric> // std::bit_cast
 #include <stdexcept>
 #include <type_traits>
 #include <vector>
@@ -42,6 +43,31 @@ inline void memcpy(void *Dst, const void *Src, size_t Size) {
   }
 }
 
+template <typename To, typename From>
+constexpr To bit_cast(const From &from) noexcept {
+  static_assert(sizeof(To) == sizeof(From),
+                "Sizes of To and From must be equal");
+  static_assert(std::is_trivially_copyable<From>::value,
+                "From must be trivially copyable");
+  static_assert(std::is_trivially_copyable<To>::value,
+                "To must be trivially copyable");
+#if __cpp_lib_bit_cast
+  return std::bit_cast<To>(from);
+#else // __cpp_lib_bit_cast
+
+#if __has_builtin(__builtin_bit_cast)
+  return __builtin_bit_cast(To, from);
+#else  // __has_builtin(__builtin_bit_cast)
+  static_assert(std::is_trivially_default_constructible<To>::value,
+                "To must be trivially default constructible");
+  To to;
+  sycl::detail::memcpy(&to, &from, sizeof(To));
+  return to;
+#endif // __has_builtin(__builtin_bit_cast)
+
+#endif // __cpp_lib_bit_cast
+}
+
 class context_impl;
 // The function returns list of events that can be passed to OpenCL API as
 // dependency list and waits for others.
diff --git a/sycl/include/CL/sycl/detail/image_accessor_util.hpp b/sycl/include/CL/sycl/detail/image_accessor_util.hpp
index 63c805ca7a83..58c0c28c5e37 100644
--- a/sycl/include/CL/sycl/detail/image_accessor_util.hpp
+++ b/sycl/include/CL/sycl/detail/image_accessor_util.hpp
@@ -196,9 +196,6 @@ vec<T, 4> readPixel(T *Ptr, const image_channel_order ChannelOrder,
     Pixel.y() = Ptr[2]; // g
     Pixel.x() = Ptr[3]; // r
     break;
-  default:
-    throw cl::sycl::invalid_parameter_error("Unhandled image channel order",
-                                            PI_INVALID_VALUE);
   }
 
   return Pixel;
@@ -269,9 +266,6 @@ void writePixel(const vec<T, 4> Pixel, T *Ptr,
     Ptr[2] = Pixel.y(); // g
     Ptr[3] = Pixel.x(); // r
     break;
-  default:
-    throw cl::sycl::invalid_parameter_error("Unhandled image channel order",
-                                            PI_INVALID_VALUE);
   }
 }
 
@@ -413,8 +407,6 @@ void convertReadData(const vec<ChannelType, 4> PixelData,
   case image_channel_type::fp32:
     RetData = PixelData.template convert<cl_float>();
     break;
-  default:
-    break;
   }
 }
 
@@ -471,8 +463,6 @@ void convertReadData(const vec<ChannelType, 4> PixelData,
         "Datatype to read - cl_half4 is incompatible with the "
         "image_channel_type of the image.",
         PI_INVALID_VALUE);
-  default:
-    break;
   }
   RetData = RetDataFloat.template convert<cl_half>();
 }
@@ -634,8 +624,6 @@ convertWriteData(const vec<cl_float, 4> WriteData,
     return WriteData.convert<ChannelType>();
   case image_channel_type::fp32:
     return WriteData.convert<ChannelType>();
-  default:
-    break;
   }
 }
 
@@ -685,8 +673,6 @@ convertWriteData(const vec<cl_half, 4> WriteData,
         "Datatype of data to write - cl_float4 is incompatible with the "
         "image_channel_type of the image.",
         PI_INVALID_VALUE);
-  default:
-    break;
   }
 }
 
diff --git a/sycl/include/CL/sycl/handler.hpp b/sycl/include/CL/sycl/handler.hpp
index 180550a1250e..0614ef3105c8 100644
--- a/sycl/include/CL/sycl/handler.hpp
+++ b/sycl/include/CL/sycl/handler.hpp
@@ -1544,8 +1544,8 @@ class __SYCL_EXPORT handler {
     detail::AccessorImplPtr AccImpl = detail::getSyclObjImpl(*AccBase);
 
     MRequirements.push_back(AccImpl.get());
-    MSrcPtr = (void *)Src;
-    MDstPtr = (void *)AccImpl.get();
+    MSrcPtr = const_cast<T_Src *>(Src);
+    MDstPtr = static_cast<void *>(AccImpl.get());
     // Store copy of accessor to the local storage to make sure it is alive
     // until we finish
     MAccStorage.push_back(std::move(AccImpl));
diff --git a/sycl/include/CL/sycl/intel/sub_group.hpp b/sycl/include/CL/sycl/intel/sub_group.hpp
index 268e9b5d23a9..a8de9028ad55 100644
--- a/sycl/include/CL/sycl/intel/sub_group.hpp
+++ b/sycl/include/CL/sycl/intel/sub_group.hpp
@@ -21,7 +21,6 @@
 #include <CL/sycl/range.hpp>
 #include <CL/sycl/types.hpp>
 
-#include <numeric> // std::bit_cast
 #include <type_traits>
 
 #ifdef __SYCL_DEVICE_ONLY__
@@ -72,22 +71,6 @@ using AcceptableForLocalLoadStore =
     bool_constant<!std::is_same<void, SelectBlockT<T>>::value &&
                   Space == access::address_space::local_space>;
 
-// TODO: move this to public cl::sycl::bit_cast as extension?
-template <typename To, typename From> To bit_cast(const From &from) {
-#if __cpp_lib_bit_cast
-  return std::bit_cast<To>(from);
-#else
-
-#if __has_builtin(__builtin_bit_cast)
-  return __builtin_bit_cast(To, from);
-#else
-  To to;
-  sycl::detail::memcpy(&to, &from, sizeof(To));
-  return to;
-#endif // __has_builtin(__builtin_bit_cast)
-#endif // __cpp_lib_bit_cast
-}
-
 template <typename T, access::address_space Space>
 T load(const multi_ptr<T, Space> src) {
   using BlockT = SelectBlockT<T>;
@@ -97,7 +80,7 @@ T load(const multi_ptr<T, Space> src) {
   BlockT Ret =
       __spirv_SubgroupBlockReadINTEL<BlockT>(reinterpret_cast<PtrT>(src.get()));
 
-  return bit_cast<T>(Ret);
+  return sycl::detail::bit_cast<T>(Ret);
 }
 
 template <int N, typename T, access::address_space Space>
@@ -110,7 +93,7 @@ vec<T, N> load(const multi_ptr<T, Space> src) {
   VecT Ret =
       __spirv_SubgroupBlockReadINTEL<VecT>(reinterpret_cast<PtrT>(src.get()));
 
-  return bit_cast<typename vec<T, N>::vector_t>(Ret);
+  return sycl::detail::bit_cast<typename vec<T, N>::vector_t>(Ret);
 }
 
 template <typename T, access::address_space Space>
@@ -119,7 +102,7 @@ void store(multi_ptr<T, Space> dst, const T &x) {
   using PtrT = sycl::detail::ConvertToOpenCLType_t<multi_ptr<BlockT, Space>>;
 
   __spirv_SubgroupBlockWriteINTEL(reinterpret_cast<PtrT>(dst.get()),
-                                  bit_cast<BlockT>(x));
+                                  sycl::detail::bit_cast<BlockT>(x));
 }
 
 template <int N, typename T, access::address_space Space>
@@ -130,7 +113,7 @@ void store(multi_ptr<T, Space> dst, const vec<T, N> &x) {
       sycl::detail::ConvertToOpenCLType_t<const multi_ptr<BlockT, Space>>;
 
   __spirv_SubgroupBlockWriteINTEL(reinterpret_cast<PtrT>(dst.get()),
-                                  bit_cast<VecT>(x));
+                                  sycl::detail::bit_cast<VecT>(x));
 }
 
 } // namespace sub_group
diff --git a/sycl/plugins/cuda/pi_cuda.cpp b/sycl/plugins/cuda/pi_cuda.cpp
index 19ce8c234728..460dbe56ab2e 100644
--- a/sycl/plugins/cuda/pi_cuda.cpp
+++ b/sycl/plugins/cuda/pi_cuda.cpp
@@ -1521,7 +1521,15 @@ pi_result cuda_piMemBufferCreate(pi_context context, pi_mem_flags flags,
       if (piMemObj != nullptr) {
         retMemObj = piMemObj.release();
         if (performInitialCopy) {
+          // Operates on the default stream of the current CUDA context.
           retErr = PI_CHECK_ERROR(cuMemcpyHtoD(ptr, host_ptr, size));
+          // Synchronize with default stream implicitly used by cuMemcpyHtoD
+          // to make buffer data available on device before any other PI call
+          // uses it.
+          if (retErr == PI_SUCCESS) {
+            CUstream defaultStream = 0;
+            retErr = PI_CHECK_ERROR(cuStreamSynchronize(defaultStream));
+          }
         }
       } else {
         retErr = PI_OUT_OF_HOST_MEMORY;
diff --git a/sycl/source/detail/kernel_impl.cpp b/sycl/source/detail/kernel_impl.cpp
index f21d18818dac..1a4bd03d33b7 100644
--- a/sycl/source/detail/kernel_impl.cpp
+++ b/sycl/source/detail/kernel_impl.cpp
@@ -22,7 +22,12 @@ namespace detail {
 kernel_impl::kernel_impl(RT::PiKernel Kernel, ContextImplPtr Context)
     : kernel_impl(Kernel, Context,
                   std::make_shared<program_impl>(Context, Kernel),
-                  /*IsCreatedFromSource*/ true) {}
+                  /*IsCreatedFromSource*/ true) {
+  // This constructor is only called in the interoperability kernel constructor.
+  // Let the runtime caller handle native kernel retaining in other cases if
+  // it's needed.
+  getPlugin().call<PiApiKind::piKernelRetain>(MKernel);
+}
 
 kernel_impl::kernel_impl(RT::PiKernel Kernel, ContextImplPtr ContextImpl,
                          ProgramImplPtr ProgramImpl,
@@ -39,7 +44,6 @@ kernel_impl::kernel_impl(RT::PiKernel Kernel, ContextImplPtr ContextImpl,
     throw cl::sycl::invalid_parameter_error(
         "Input context must be the same as the context of cl_kernel",
         PI_INVALID_CONTEXT);
-  getPlugin().call<PiApiKind::piKernelRetain>(MKernel);
 }
 
 kernel_impl::kernel_impl(ContextImplPtr Context,
diff --git a/sycl/source/detail/kernel_info.hpp b/sycl/source/detail/kernel_info.hpp
index 99b51339cbeb..d7514b1522b5 100644
--- a/sycl/source/detail/kernel_info.hpp
+++ b/sycl/source/detail/kernel_info.hpp
@@ -85,7 +85,7 @@ get_kernel_work_group_info_host(const cl::sycl::device &Device);
 template <>
 inline cl::sycl::range<3>
 get_kernel_work_group_info_host<info::kernel_work_group::global_work_size>(
-    const cl::sycl::device &Dev) {
+    const cl::sycl::device &) {
   throw invalid_object_error("This instance of kernel is a host instance",
                              PI_INVALID_KERNEL);
 }
@@ -100,7 +100,7 @@ get_kernel_work_group_info_host<info::kernel_work_group::work_group_size>(
 template <>
 inline cl::sycl::range<3> get_kernel_work_group_info_host<
     info::kernel_work_group::compile_work_group_size>(
-    const cl::sycl::device &Dev) {
+    const cl::sycl::device &) {
   return {0, 0, 0};
 }
 
@@ -115,7 +115,7 @@ inline size_t get_kernel_work_group_info_host<
 template <>
 inline cl_ulong
 get_kernel_work_group_info_host<info::kernel_work_group::private_mem_size>(
-    const cl::sycl::device &Dev) {
+    const cl::sycl::device &) {
   return 0;
 }
 // The kernel sub-group methods
diff --git a/sycl/source/detail/memory_manager.cpp b/sycl/source/detail/memory_manager.cpp
index c2718d7ae05c..31948be77f8f 100644
--- a/sycl/source/detail/memory_manager.cpp
+++ b/sycl/source/detail/memory_manager.cpp
@@ -107,7 +107,7 @@ void *MemoryManager::allocateInteropMemObject(
     return UserPtr;
   }
   // Allocate new cl_mem and initialize from user provided one.
-  assert(!"Not implemented");
+  assert(false && "Not implemented");
   return nullptr;
 }
 
@@ -203,7 +203,7 @@ void *MemoryManager::allocateMemSubBuffer(ContextImplPtr TargetContext,
   return NewMem;
 }
 
-void copyH2D(SYCLMemObjI *SYCLMemObj, char *SrcMem, QueueImplPtr SrcQueue,
+void copyH2D(SYCLMemObjI *SYCLMemObj, char *SrcMem, QueueImplPtr,
              unsigned int DimSrc, sycl::range<3> SrcSize,
              sycl::range<3> SrcAccessRange, sycl::id<3> SrcOffset,
              unsigned int SrcElemSize, RT::PiMem DstMem, QueueImplPtr TgtQueue,
@@ -255,11 +255,11 @@ void copyH2D(SYCLMemObjI *SYCLMemObj, char *SrcMem, QueueImplPtr SrcQueue,
 void copyD2H(SYCLMemObjI *SYCLMemObj, RT::PiMem SrcMem, QueueImplPtr SrcQueue,
              unsigned int DimSrc, sycl::range<3> SrcSize,
              sycl::range<3> SrcAccessRange, sycl::id<3> SrcOffset,
-             unsigned int SrcElemSize, char *DstMem, QueueImplPtr TgtQueue,
+             unsigned int SrcElemSize, char *DstMem, QueueImplPtr,
              unsigned int DimDst, sycl::range<3> DstSize,
              sycl::range<3> DstAccessRange, sycl::id<3> DstOffset,
              unsigned int DstElemSize, std::vector<RT::PiEvent> DepEvents,
-              RT::PiEvent &OutEvent) {
+             RT::PiEvent &OutEvent) {
   assert(SYCLMemObj && "The SYCLMemObj is nullptr");
 
   const RT::PiQueue Queue = SrcQueue->getHandleRef();
@@ -302,11 +302,10 @@ void copyD2H(SYCLMemObjI *SYCLMemObj, RT::PiMem SrcMem, QueueImplPtr SrcQueue,
 void copyD2D(SYCLMemObjI *SYCLMemObj, RT::PiMem SrcMem, QueueImplPtr SrcQueue,
              unsigned int DimSrc, sycl::range<3> SrcSize,
              sycl::range<3> SrcAccessRange, sycl::id<3> SrcOffset,
-             unsigned int SrcElemSize, RT::PiMem DstMem, QueueImplPtr TgtQueue,
-             unsigned int DimDst, sycl::range<3> DstSize,
-             sycl::range<3> DstAccessRange, sycl::id<3> DstOffset,
-             unsigned int DstElemSize, std::vector<RT::PiEvent> DepEvents,
-             RT::PiEvent &OutEvent) {
+             unsigned int SrcElemSize, RT::PiMem DstMem, QueueImplPtr,
+             unsigned int DimDst, sycl::range<3> DstSize, sycl::range<3>,
+             sycl::id<3> DstOffset, unsigned int DstElemSize,
+             std::vector<RT::PiEvent> DepEvents, RT::PiEvent &OutEvent) {
   assert(SYCLMemObj && "The SYCLMemObj is nullptr");
 
   const RT::PiQueue Queue = SrcQueue->getHandleRef();
@@ -341,18 +340,17 @@ void copyD2D(SYCLMemObjI *SYCLMemObj, RT::PiMem SrcMem, QueueImplPtr SrcQueue,
   }
 }
 
-static void copyH2H(SYCLMemObjI *SYCLMemObj, char *SrcMem,
-                    QueueImplPtr SrcQueue, unsigned int DimSrc,
-                    sycl::range<3> SrcSize, sycl::range<3> SrcAccessRange,
-                    sycl::id<3> SrcOffset, unsigned int SrcElemSize,
-                    char *DstMem, QueueImplPtr TgtQueue, unsigned int DimDst,
-                    sycl::range<3> DstSize, sycl::range<3> DstAccessRange,
-                    sycl::id<3> DstOffset, unsigned int DstElemSize,
-                    std::vector<RT::PiEvent> DepEvents, RT::PiEvent &OutEvent) {
+static void copyH2H(SYCLMemObjI *, char *SrcMem, QueueImplPtr,
+                    unsigned int DimSrc, sycl::range<3> SrcSize,
+                    sycl::range<3> SrcAccessRange, sycl::id<3> SrcOffset,
+                    unsigned int SrcElemSize, char *DstMem, QueueImplPtr,
+                    unsigned int DimDst, sycl::range<3> DstSize,
+                    sycl::range<3> DstAccessRange, sycl::id<3> DstOffset,
+                    unsigned int DstElemSize, std::vector<RT::PiEvent>,
+                    RT::PiEvent &) {
   if ((DimSrc != 1 || DimDst != 1) &&
       (SrcOffset != id<3>{0, 0, 0} || DstOffset != id<3>{0, 0, 0} ||
        SrcSize != SrcAccessRange || DstSize != DstAccessRange)) {
-    assert(!"Not supported configuration of memcpy requested");
     throw runtime_error("Not supported configuration of memcpy requested",
                         PI_INVALID_OPERATION);
   }
@@ -412,9 +410,8 @@ void MemoryManager::copy(SYCLMemObjI *SYCLMemObj, void *SrcMem,
 
 void MemoryManager::fill(SYCLMemObjI *SYCLMemObj, void *Mem, QueueImplPtr Queue,
                          size_t PatternSize, const char *Pattern,
-                         unsigned int Dim, sycl::range<3> Size,
-                         sycl::range<3> Range, sycl::id<3> Offset,
-                         unsigned int ElementSize,
+                         unsigned int Dim, sycl::range<3>, sycl::range<3> Range,
+                         sycl::id<3> Offset, unsigned int ElementSize,
                          std::vector<RT::PiEvent> DepEvents,
                          RT::PiEvent &OutEvent) {
   assert(SYCLMemObj && "The SYCLMemObj is nullptr");
@@ -428,7 +425,6 @@ void MemoryManager::fill(SYCLMemObjI *SYCLMemObj, void *Mem, QueueImplPtr Queue,
           &DepEvents[0], &OutEvent);
       return;
     }
-    assert(!"Not supported configuration of fill requested");
     throw runtime_error("Not supported configuration of fill requested",
                         PI_INVALID_OPERATION);
   } else {
@@ -438,14 +434,13 @@ void MemoryManager::fill(SYCLMemObjI *SYCLMemObj, void *Mem, QueueImplPtr Queue,
   }
 }
 
-void *MemoryManager::map(SYCLMemObjI *SYCLMemObj, void *Mem, QueueImplPtr Queue,
-                         access::mode AccessMode, unsigned int Dim,
-                         sycl::range<3> Size, sycl::range<3> AccessRange,
-                         sycl::id<3> AccessOffset, unsigned int ElementSize,
+void *MemoryManager::map(SYCLMemObjI *, void *Mem, QueueImplPtr Queue,
+                         access::mode AccessMode, unsigned int, sycl::range<3>,
+                         sycl::range<3> AccessRange, sycl::id<3> AccessOffset,
+                         unsigned int ElementSize,
                          std::vector<RT::PiEvent> DepEvents,
                          RT::PiEvent &OutEvent) {
   if (Queue->is_host()) {
-    assert(!"Not supported configuration of map requested");
     throw runtime_error("Not supported configuration of map requested",
                         PI_INVALID_OPERATION);
   }
@@ -485,13 +480,12 @@ void *MemoryManager::map(SYCLMemObjI *SYCLMemObj, void *Mem, QueueImplPtr Queue,
   return MappedPtr;
 }
 
-void MemoryManager::unmap(SYCLMemObjI *SYCLMemObj, void *Mem,
-                          QueueImplPtr Queue, void *MappedPtr,
-                          std::vector<RT::PiEvent> DepEvents,
+void MemoryManager::unmap(SYCLMemObjI *, void *Mem, QueueImplPtr Queue,
+                          void *MappedPtr, std::vector<RT::PiEvent> DepEvents,
                           RT::PiEvent &OutEvent) {
 
   // Host queue is not supported here.
-  // All DepEvents are to the same Context. 
+  // All DepEvents are to the same Context.
   // Using the plugin of the Queue.
 
   const detail::plugin &Plugin = Queue->getPlugin();
diff --git a/sycl/source/detail/os_util.cpp b/sycl/source/detail/os_util.cpp
index 181323f528bc..c47b81f2caa4 100644
--- a/sycl/source/detail/os_util.cpp
+++ b/sycl/source/detail/os_util.cpp
@@ -200,10 +200,10 @@ std::string OSUtil::getCurrentDSODir() {
   char Path[MAX_PATH];
   Path[0] = '\0';
   Path[sizeof(Path) - 1] = '\0';
+  auto Handle = getOSModuleHandle(&getCurrentDSODir);
   DWORD Ret = GetModuleFileNameA(
-    reinterpret_cast<HMODULE>(getOSModuleHandle(&getCurrentDSODir)),
-    reinterpret_cast<LPSTR>(&Path),
-    sizeof(Path));
+      reinterpret_cast<HMODULE>(OSUtil::ExeModuleHandle == Handle ? 0 : Handle),
+      reinterpret_cast<LPSTR>(&Path), sizeof(Path));
   assert(Ret < sizeof(Path) && "Path is longer than PATH_MAX?");
   assert(Ret > 0 && "GetModuleFileNameA failed");
   (void)Ret;
diff --git a/sycl/source/detail/program_impl.cpp b/sycl/source/detail/program_impl.cpp
index e6a03be30e34..a423b2fac9f4 100644
--- a/sycl/source/detail/program_impl.cpp
+++ b/sycl/source/detail/program_impl.cpp
@@ -398,6 +398,7 @@ RT::PiKernel program_impl::get_pi_kernel(const string_class &KernelName) const {
   if (is_cacheable()) {
     Kernel = ProgramManager::getInstance().getOrCreateKernel(
         MProgramModuleHandle, get_context(), KernelName, this);
+    getPlugin().call<PiApiKind::piKernelRetain>(Kernel);
   } else {
     const detail::plugin &Plugin = getPlugin();
     RT::PiResult Err = Plugin.call_nocheck<PiApiKind::piKernelCreate>(
diff --git a/sycl/source/detail/scheduler/commands.cpp b/sycl/source/detail/scheduler/commands.cpp
index 2609af09f566..a58c28f1487b 100644
--- a/sycl/source/detail/scheduler/commands.cpp
+++ b/sycl/source/detail/scheduler/commands.cpp
@@ -1641,7 +1641,6 @@ cl_int ExecCGCommand::enqueueImp() {
   switch (MCommandGroup->getType()) {
 
   case CG::CGTYPE::UPDATE_HOST: {
-    assert(!"Update host should be handled by the Scheduler.");
     throw runtime_error("Update host should be handled by the Scheduler.",
                         PI_INVALID_OPERATION);
   }
@@ -1843,8 +1842,6 @@ cl_int ExecCGCommand::enqueueImp() {
                                                          Arg.MSize, Arg.MPtr);
         break;
       }
-      default:
-        assert(!"Unhandled");
       }
     }
 
@@ -1946,17 +1943,16 @@ cl_int ExecCGCommand::enqueueImp() {
       }
     }
 
-    MQueue->getThreadPool().submit<DispatchHostTask>(
-        std::move(DispatchHostTask(this)));
+    MQueue->getThreadPool().submit<DispatchHostTask>(DispatchHostTask(this));
 
     MShouldCompleteEventIfPossible = false;
 
     return CL_SUCCESS;
   }
   case CG::CGTYPE::NONE:
-  default:
     throw runtime_error("CG type not implemented.", PI_INVALID_OPERATION);
   }
+  return PI_INVALID_OPERATION;
 }
 
 } // namespace detail
diff --git a/sycl/source/detail/scheduler/commands.hpp b/sycl/source/detail/scheduler/commands.hpp
index 37880f41d162..b809c1503a39 100644
--- a/sycl/source/detail/scheduler/commands.hpp
+++ b/sycl/source/detail/scheduler/commands.hpp
@@ -165,7 +165,7 @@ class Command {
   virtual void printDot(std::ostream &Stream) const = 0;
 
   virtual const Requirement *getRequirement() const {
-    assert(!"Internal Error. The command has no stored requirement");
+    assert(false && "Internal Error. The command has no stored requirement");
     return nullptr;
   }
 
@@ -422,8 +422,8 @@ class MemCpyCommand : public Command {
 
   void printDot(std::ostream &Stream) const final;
   const Requirement *getRequirement() const final { return &MDstReq; }
-  void emitInstrumentationData();
-  ContextImplPtr getContext() const override final;
+  void emitInstrumentationData() final;
+  ContextImplPtr getContext() const final;
 
 private:
   cl_int enqueueImp() final;
@@ -445,8 +445,8 @@ class MemCpyCommandHost : public Command {
 
   void printDot(std::ostream &Stream) const final;
   const Requirement *getRequirement() const final { return &MDstReq; }
-  void emitInstrumentationData();
-  ContextImplPtr getContext() const override final;
+  void emitInstrumentationData() final;
+  ContextImplPtr getContext() const final;
 
 private:
   cl_int enqueueImp() final;
@@ -467,7 +467,7 @@ class ExecCGCommand : public Command {
   void flushStreams();
 
   void printDot(std::ostream &Stream) const final;
-  void emitInstrumentationData();
+  void emitInstrumentationData() final;
 
   detail::CG &getCG() const { return *MCommandGroup; }
 
@@ -494,7 +494,7 @@ class UpdateHostRequirementCommand : public Command {
 
   void printDot(std::ostream &Stream) const final;
   const Requirement *getRequirement() const final { return &MDstReq; }
-  void emitInstrumentationData();
+  void emitInstrumentationData() final;
 
 private:
   cl_int enqueueImp() final;
diff --git a/sycl/test/bit_cast/bit_cast.cpp b/sycl/test/bit_cast/bit_cast.cpp
new file mode 100644
index 000000000000..fcca0a8b2bfd
--- /dev/null
+++ b/sycl/test/bit_cast/bit_cast.cpp
@@ -0,0 +1,84 @@
+// RUN: %clangxx -fsycl -fsycl-targets=%sycl_triple %s -o %t.out
+// RUN: env SYCL_DEVICE_TYPE=HOST %t.out
+// RUN: %CPU_RUN_PLACEHOLDER %t.out
+// RUN: %GPU_RUN_PLACEHOLDER %t.out
+// RUN: %ACC_RUN_PLACEHOLDER %t.out
+
+#include <CL/sycl.hpp>
+
+#include <iostream>
+#include <math.h>
+#include <type_traits>
+
+constexpr cl::sycl::access::mode sycl_write = cl::sycl::access::mode::write;
+
+template <typename To, typename From>
+class BitCastKernel;
+
+template <typename To, typename From>
+To doBitCast(const From &ValueToConvert) {
+  std::vector<To> Vec(1);
+  {
+    sycl::buffer<To, 1> Buf(Vec.data(), 1);
+    sycl::queue Queue;
+    Queue.submit([&](sycl::handler &cgh) {
+      auto acc = Buf.template get_access<sycl_write>(cgh);
+      cgh.single_task<class BitCastKernel<To, From>>([=]() {
+        // TODO: change to sycl::bit_cast in the future
+        acc[0] = sycl::detail::bit_cast<To>(ValueToConvert);
+      });
+    });
+  }
+  return Vec[0];
+}
+
+template <typename To, typename From>
+int test(const From &Value) {
+  auto ValueConvertedTwoTimes = doBitCast<From>(doBitCast<To>(Value));
+  bool isOriginalValueEqualsToConvertedTwoTimes = false;
+  if (std::is_integral<From>::value) {
+    isOriginalValueEqualsToConvertedTwoTimes = Value == ValueConvertedTwoTimes;
+  } else if ((std::is_floating_point<From>::value) || std::is_same<From, cl::sycl::half>::value) {
+    static const float Epsilon = 0.0000001f;
+    isOriginalValueEqualsToConvertedTwoTimes = fabs(Value - ValueConvertedTwoTimes) < Epsilon;
+  } else {
+    std::cerr << "Type " << typeid(From).name() << " neither integral nor floating point nor cl::sycl::half\n";
+    return 1;
+  }
+  if (!isOriginalValueEqualsToConvertedTwoTimes) {
+    std::cerr << "FAIL: Original value which is " << Value << " != value converted two times which is " << ValueConvertedTwoTimes << "\n";
+    return 1;
+  }
+  std::cout << "PASS\n";
+  return 0;
+}
+
+int main() {
+  int ReturnCode = 0;
+
+  std::cout << "cl::sycl::half to unsigned short ...\n";
+  ReturnCode += test<unsigned short>(cl::sycl::half(1.0f));
+
+  std::cout << "unsigned short to cl::sycl::half ...\n";
+  ReturnCode += test<cl::sycl::half>(static_cast<unsigned short>(16384));
+
+  std::cout << "cl::sycl::half to short ...\n";
+  ReturnCode += test<short>(cl::sycl::half(1.0f));
+
+  std::cout << "short to cl::sycl::half ...\n";
+  ReturnCode += test<cl::sycl::half>(static_cast<short>(16384));
+
+  std::cout << "int to float ...\n";
+  ReturnCode += test<float>(static_cast<int>(2));
+
+  std::cout << "float to int ...\n";
+  ReturnCode += test<int>(static_cast<float>(-2.4f));
+
+  std::cout << "unsigned int to float ...\n";
+  ReturnCode += test<float>(static_cast<unsigned int>(6));
+
+  std::cout << "float to unsigned int ...\n";
+  ReturnCode += test<unsigned int>(static_cast<float>(-2.4f));
+
+  return ReturnCode;
+}
diff --git a/sycl/tools/install.bat b/sycl/tools/install.bat
index a7abc57b495b..f770d47d3583 100755
--- a/sycl/tools/install.bat
+++ b/sycl/tools/install.bat
@@ -7,18 +7,20 @@ echo ### 1. Save and update OpenCL.dll available in the system
 echo ###
 set TMP_FILE=%TEMP%\install.bat.tmp
 
+
+set SYSTEM_OCL_ICD_LOADER=C:\Windows\System32\OpenCL.dll
+set NEW_OCL_ICD_LOADER=%OCL_RT_DIR%\OpenCL.dll
 set INSTALL_ERRORS=0
 
-PowerShell -Command "& {(Get-Command .\OpenCL.dll).FileVersionInfo.FileVersion}" > %TMP_FILE%1
+PowerShell -Command "& {(Get-Command %NEW_OCL_ICD_LOADER%).FileVersionInfo.FileVersion}" > %TMP_FILE%1
 set /p DOWNLOADED_OPENCL_VER= < %TMP_FILE%1
-echo Downloaded OpenCL.dll verison: %DOWNLOADED_OPENCL_VER%
 
-IF EXIST C:\Windows\System32\OpenCL.dll (
-  PowerShell -Command "& {(Get-Command C:\Windows\System32\OpenCL.dll).FileVersionInfo.FileVersion}" > %TMP_FILE%2
-  set /p SYSTEM_OPENCL_VER= < %TMP_FILE%2
-  echo System OpenCL.dll version: %SYSTEM_OPENCL_VER%
+IF EXIST %SYSTEM_OCL_ICD_LOADER% (
+  echo %SYSTEM_OCL_ICD_LOADER% is present. Checking version.
+  PowerShell -Command "& {(Get-Command %SYSTEM_OCL_ICD_LOADER%).FileVersionInfo.FileVersion}" > %TMP_FILE%2
+  set /p SYSTEM_OPENCL_VER=<%TMP_FILE%2
 
-  PowerShell -Command "& {[version]($Env:SYSTEM_OPENCL_VER) -lt ([version]$Env:DOWNLOADED_OPENCL_VER)}" > %TMP_FILE%3
+  PowerShell -Command "& {([version]$Env:SYSTEM_OPENCL_VER) -lt ([version]$Env:DOWNLOADED_OPENCL_VER)}" > %TMP_FILE%3
   set /p NEED_OPENCL_UPGRADE= < %TMP_FILE%3
   set /p NEED_OPENCL_BACKUP= < %TMP_FILE%3
 ) else (
@@ -27,17 +29,20 @@ IF EXIST C:\Windows\System32\OpenCL.dll (
   set NEED_OPENCL_BACKUP=False
 )
 
-echo Need to backup C:\Windows\System32\OpenCL.dll : %NEED_OPENCL_BACKUP%
-echo Need to update C:\Windows\System32\OpenCL.dll : %NEED_OPENCL_UPGRADE%
+echo Downloaded OpenCL.dll version: %DOWNLOADED_OPENCL_VER%
+echo System OpenCL.dll version: %SYSTEM_OPENCL_VER%
+
+echo Need to backup %SYSTEM_OCL_ICD_LOADER% : %NEED_OPENCL_BACKUP%
+echo Need to update %SYSTEM_OCL_ICD_LOADER% : %NEED_OPENCL_UPGRADE%
 echo.
 
 IF %NEED_OPENCL_BACKUP% == True (
-  echo Save system OpenCL.dll: C:\Windows\System32\OpenCL.dll to C:\Windows\System32\OpenCL.dll.%SYSTEM_OPENCL_VER%
-  copy /Y C:\Windows\System32\OpenCL.dll C:\Windows\System32\OpenCL.dll.%SYSTEM_OPENCL_VER%
+  echo Save system OpenCL.dll: %SYSTEM_OCL_ICD_LOADER% to %SYSTEM_OCL_ICD_LOADER%.%SYSTEM_OPENCL_VER%
+  copy /Y %SYSTEM_OCL_ICD_LOADER% %SYSTEM_OCL_ICD_LOADER%.%SYSTEM_OPENCL_VER%
   IF ERRORLEVEL 1 (
     echo !!! Cannot save the original file C:\Windows\System32\OpenCL.dll
     echo !!! Try saving the file manually using File Explorer:
-    echo !!!     C:\Windows\System32\OpenCL.dll to C:\Windows\System32\OpenCL.dll.%SYSTEM_OPENCL_VER%
+    echo !!!     %SYSTEM_OCL_ICD_LOADER% to %SYSTEM_OCL_ICD_LOADER%.%SYSTEM_OPENCL_VER%
     echo !!! Or run this script as Administrator.
     set INSTALL_ERRORS=1
   ) ELSE (
@@ -47,17 +52,17 @@ IF %NEED_OPENCL_BACKUP% == True (
 )
 
 IF %NEED_OPENCL_UPGRADE% == True (
-  echo Replace C:\Windows\System32\OpenCL.dll with the new downloaded OpenCL.dll
+  echo Replace %SYSTEM_OCL_ICD_LOADER% with the new downloaded %NEW_OCL_ICD_LOADER%
 
   rem CHANGE THE FILE ATTRIBUTES. OTHERWISE, IT CANNOT BE REPLACED by regular MOVE, DEL, COPY commands.
-  PowerShell -Command "& {$acl = Get-Acl C:\Windows\System32\OpenCL.dll; $AccessRule = New-Object System.Security.AccessControl.FileSystemAccessRule(\"Users\",\"FullControl\",\"Allow\"); $acl.SetAccessRule($AccessRule); $acl | Set-Acl c:\Windows\System32\OpenCL.dll; }"
+  PowerShell -Command "& {$acl = Get-Acl %SYSTEM_OCL_ICD_LOADER%; $AccessRule = New-Object System.Security.AccessControl.FileSystemAccessRule(\"Users\",\"FullControl\",\"Allow\"); $acl.SetAccessRule($AccessRule); $acl | Set-Acl %SYSTEM_OCL_ICD_LOADER%; }"
 
 
-  copy /Y %OCL_RT_DIR%OpenCL.dll C:\Windows\System32\
+  copy /Y %NEW_OCL_ICD_LOADER% %SYSTEM_OCL_ICD_LOADER%
   IF ERRORLEVEL 1 (
-    echo !!! Cannot copy new OpenCL.dll to C:\Windows\System32\OpenCL.dll
+    echo !!! Cannot copy %NEW_OCL_ICD_LOADER% to %SYSTEM_OCL_ICD_LOADER%
     echo !!! Try copying the file manually using File Explorer:
-    echo !!!     %OCL_RT_DIR%OpenCL.dll to C:\Windows\System32\
+    echo !!!     %NEW_OCL_ICD_LOADER% to %SYSTEM_OCL_ICD_LOADER%
     echo !!! Or run this script as Administrator.
     set INSTALL_ERRORS=1
   ) ELSE (
@@ -130,8 +135,8 @@ echo.
 IF %INSTALL_ERRORS% == 1 (
   echo Installation finished WITH ERRORS!
   echo See recommendations printed above and perform the following actions manually:
-  echo   1. Save C:\Windows\System32\OpenCL.dll to C:\Windows\System32\OpenCL.dll.%SYSTEM_OPENCL_VER%
-  echo   2. Copy %OCL_RT_DIR%OpenCL.dll to C:\Windows\System32\OpenCL.dll
+  echo   1. Save %SYSTEM_OCL_ICD_LOADER% to %SYSTEM_OCL_ICD_LOADER%.%SYSTEM_OPENCL_VER%
+  echo   2. Copy %NEW_OCL_ICD_LOADER% to %SYSTEM_OCL_ICD_LOADER%
   echo   3. Add/set the environment variable OCL_ICD_FILENAMES to %OCL_RT_DIR%intelocl64.dll
   echo   4. Copy TBB libraries or create symbolic links in %OCL_RT_DIR%tbb.
   echo   5. Add/set the environment variable PATH to %OCL_RT_DIR%tbb
diff --git a/sycl/unittests/CMakeLists.txt b/sycl/unittests/CMakeLists.txt
index 5538a6bd48d9..01ec50e5b76a 100644
--- a/sycl/unittests/CMakeLists.txt
+++ b/sycl/unittests/CMakeLists.txt
@@ -56,5 +56,6 @@ endfunction()
 
 add_subdirectory(misc)
 add_subdirectory(pi)
-add_subdirectory(thread_safety)
+add_subdirectory(program)
 add_subdirectory(scheduler)
+add_subdirectory(thread_safety)
diff --git a/sycl/unittests/pi/PiMock.cpp b/sycl/unittests/pi/PiMock.cpp
index a237071db29f..d3474f950a08 100644
--- a/sycl/unittests/pi/PiMock.cpp
+++ b/sycl/unittests/pi/PiMock.cpp
@@ -12,16 +12,13 @@
 
 using namespace cl::sycl;
 
-pi_result
-piProgramBuildRedefine(pi_program program, pi_uint32 num_devices,
-                       const pi_device *device_list, const char *options,
-                       void (*pfn_notify)(pi_program program, void *user_data),
-                       void *user_data) {
+pi_result piProgramBuildRedefine(pi_program, pi_uint32, const pi_device *,
+                                 const char *, void (*)(pi_program, void *),
+                                 void *) {
   return PI_INVALID_BINARY;
 }
 
-pi_result piKernelCreateRedefine(pi_program program, const char *kernel_name,
-                                 pi_kernel *ret_kernel) {
+pi_result piKernelCreateRedefine(pi_program, const char *, pi_kernel *) {
   return PI_INVALID_DEVICE;
 }
 
@@ -91,7 +88,7 @@ TEST(PiMockTest, RedefineAPI) {
   // Pass a captureless lambda
   auto *OldFuncPtr = Table.piProgramRetain;
   Mock.redefine<detail::PiApiKind::piProgramRetain>(
-      [](pi_program program) -> pi_result { return PI_SUCCESS; });
+      [](pi_program) -> pi_result { return PI_SUCCESS; });
   EXPECT_FALSE(Table.piProgramRetain == OldFuncPtr)
       << "Passing a lambda didn't change the function table entry";
   ASSERT_FALSE(Table.piProgramRetain == nullptr)
diff --git a/sycl/unittests/pi/PlatformTest.cpp b/sycl/unittests/pi/PlatformTest.cpp
index 0ac0dbb9da9e..c3d04721cc99 100644
--- a/sycl/unittests/pi/PlatformTest.cpp
+++ b/sycl/unittests/pi/PlatformTest.cpp
@@ -24,7 +24,7 @@ class PlatformTest : public testing::TestWithParam<detail::plugin> {
 
   ~PlatformTest() override = default;
 
-  void SetUp() {
+  void SetUp() override {
 
     detail::plugin plugin = GetParam();
 
diff --git a/sycl/unittests/program/CMakeLists.txt b/sycl/unittests/program/CMakeLists.txt
new file mode 100644
index 000000000000..043079836f6b
--- /dev/null
+++ b/sycl/unittests/program/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_sycl_unittest(ProgramTests OBJECT
+  KernelRelease.cpp
+)
diff --git a/sycl/unittests/program/KernelRelease.cpp b/sycl/unittests/program/KernelRelease.cpp
new file mode 100644
index 000000000000..a90ada3a686c
--- /dev/null
+++ b/sycl/unittests/program/KernelRelease.cpp
@@ -0,0 +1,99 @@
+//==----------- KernelRelease.cpp --- kernel release unit test -------------==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include <CL/sycl.hpp>
+#include <detail/context_impl.hpp>
+#include <gtest/gtest.h>
+#include <helpers/PiMock.hpp>
+
+#include <iostream>
+#include <memory>
+
+using namespace cl::sycl;
+
+struct TestCtx {
+  TestCtx(context &Ctx) : Ctx{Ctx} {};
+
+  context &Ctx;
+  int KernelReferenceCount = 0;
+};
+
+std::unique_ptr<TestCtx> TestContext;
+
+pi_result redefinedProgramCreateWithSource(pi_context context, pi_uint32 count,
+                                           const char **strings,
+                                           const size_t *lengths,
+                                           pi_program *ret_program) {
+  return PI_SUCCESS;
+}
+
+pi_result
+redefinedProgramBuild(pi_program program, pi_uint32 num_devices,
+                      const pi_device *device_list, const char *options,
+                      void (*pfn_notify)(pi_program program, void *user_data),
+                      void *user_data) {
+  return PI_SUCCESS;
+}
+
+pi_result redefinedKernelCreate(pi_program program, const char *kernel_name,
+                                pi_kernel *ret_kernel) {
+  TestContext->KernelReferenceCount = 1;
+  return PI_SUCCESS;
+}
+
+pi_result redefinedKernelRetain(pi_kernel kernel) {
+  ++TestContext->KernelReferenceCount;
+  return PI_SUCCESS;
+}
+
+pi_result redefinedKernelRelease(pi_kernel kernel) {
+  --TestContext->KernelReferenceCount;
+  return PI_SUCCESS;
+}
+
+pi_result redefinedKernelGetInfo(pi_kernel kernel, pi_kernel_info param_name,
+                                 size_t param_value_size, void *param_value,
+                                 size_t *param_value_size_ret) {
+  EXPECT_EQ(param_name, PI_KERNEL_INFO_CONTEXT)
+      << "Unexpected kernel info requested";
+  auto *Result = reinterpret_cast<RT::PiContext *>(param_value);
+  RT::PiContext PiCtx =
+      detail::getSyclObjImpl(TestContext->Ctx)->getHandleRef();
+  *Result = PiCtx;
+  return PI_SUCCESS;
+}
+
+TEST(KernelReleaseTest, GetKernelRelease) {
+  unittest::PiMock Mock;
+  platform Plt = Mock.getPlatform();
+  if (Plt.is_host()) {
+    std::cerr << "The program/kernel methods are mostly no-op on the host "
+                 "device, the test is not run."
+              << std::endl;
+    return;
+  }
+
+  Mock.redefine<detail::PiApiKind::piclProgramCreateWithSource>(
+      redefinedProgramCreateWithSource);
+  Mock.redefine<detail::PiApiKind::piProgramBuild>(redefinedProgramBuild);
+  Mock.redefine<detail::PiApiKind::piKernelCreate>(redefinedKernelCreate);
+  Mock.redefine<detail::PiApiKind::piKernelRetain>(redefinedKernelRetain);
+  Mock.redefine<detail::PiApiKind::piKernelRelease>(redefinedKernelRelease);
+  Mock.redefine<detail::PiApiKind::piKernelGetInfo>(redefinedKernelGetInfo);
+
+  context Ctx{Plt};
+  TestContext.reset(new TestCtx(Ctx));
+
+  program Prg{Ctx};
+  Prg.build_with_source("");
+
+  { kernel Krnl = Prg.get_kernel(""); }
+
+  ASSERT_EQ(TestContext->KernelReferenceCount, 0)
+      << "Reference count not equal to 0 after kernel destruction";
+}
diff --git a/sycl/unittests/scheduler/SchedulerTestUtils.hpp b/sycl/unittests/scheduler/SchedulerTestUtils.hpp
index 814def6b0581..594426b007ef 100644
--- a/sycl/unittests/scheduler/SchedulerTestUtils.hpp
+++ b/sycl/unittests/scheduler/SchedulerTestUtils.hpp
@@ -29,7 +29,7 @@ class MockCommand : public cl::sycl::detail::Command {
       : Command{cl::sycl::detail::Command::EMPTY_TASK, Queue},
         MRequirement{std::move(getMockRequirement())} {}
 
-  void printDot(std::ostream &Stream) const override {}
+  void printDot(std::ostream &) const override {}
   void emitInstrumentationData() override {}
 
   const cl::sycl::detail::Requirement *getRequirement() const final {