From f443035c078397640ef49f89a9a54e0dc332b8cd Mon Sep 17 00:00:00 2001 From: Evgeny Mankov Date: Mon, 23 Sep 2024 22:19:56 +0100 Subject: [PATCH] [HIPIFY][MIOpen] Versioning - Step 4 - `Appeared` + Formatting --- .../CUDNN_API_supported_by_HIP_and_MIOPEN.md | 66 +- docs/tables/CUDNN_API_supported_by_MIOPEN.md | 66 +- src/CUDA2HIP_DNN_API_types.cpp | 2509 +++++++++-------- 3 files changed, 1337 insertions(+), 1304 deletions(-) diff --git a/docs/tables/CUDNN_API_supported_by_HIP_and_MIOPEN.md b/docs/tables/CUDNN_API_supported_by_HIP_and_MIOPEN.md index b7a6c78b..3f36dc83 100644 --- a/docs/tables/CUDNN_API_supported_by_HIP_and_MIOPEN.md +++ b/docs/tables/CUDNN_API_supported_by_HIP_and_MIOPEN.md @@ -131,7 +131,7 @@ |`CUDNN_ATTR_OPERATION_MATMUL_GEMM_K_OVERRIDE_DESC`|8.7.0| | | | | | | | | |`MIOPEN_ATTR_OPERATION_MATMUL_GEMM_K_OVERRIDE_DESC`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_MATMUL_GEMM_M_OVERRIDE_DESC`|8.7.0| | | | | | | | | |`MIOPEN_ATTR_OPERATION_MATMUL_GEMM_M_OVERRIDE_DESC`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_MATMUL_GEMM_N_OVERRIDE_DESC`|8.7.0| | | | | | | | | |`MIOPEN_ATTR_OPERATION_MATMUL_GEMM_N_OVERRIDE_DESC`|6.2.0| | | | | -|`CUDNN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT`|8.1.0|9.0.0| | | | | | | | |`MIOPEN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT`| | | | | | +|`CUDNN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT`|8.1.0|9.0.0| | | | | | | | |`MIOPEN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_NORM_BWD_DBIAS_DESC`|8.5.0| | | | | | | | | |`MIOPEN_ATTR_OPERATION_NORM_BWD_DBIAS_DESC`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_NORM_BWD_DSCALE_DESC`|8.5.0| | | | | | | | | |`MIOPEN_ATTR_OPERATION_NORM_BWD_DSCALE_DESC`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_NORM_BWD_DXDESC`|8.5.0| | | | | | | | | |`MIOPEN_ATTR_OPERATION_NORM_BWD_DXDESC`|6.2.0| | | | | @@ -241,42 +241,42 @@ |`CUDNN_ATTR_VARIANT_PACK_INTERMEDIATES`|8.0.1| | | | | | | | | |`MIOPEN_ATTR_VARIANT_PACK_INTERMEDIATES`|6.2.0| | | | | |`CUDNN_ATTR_VARIANT_PACK_UNIQUE_IDS`|8.0.1| | | | | | | | | |`MIOPEN_ATTR_VARIANT_PACK_UNIQUE_IDS`|6.2.0| | | | | |`CUDNN_ATTR_VARIANT_PACK_WORKSPACE`|8.0.1| | | | | | | | | |`MIOPEN_ATTR_VARIANT_PACK_WORKSPACE`|6.2.0| | | | | -|`CUDNN_BACKEND_CONVOLUTION_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_CONVOLUTION_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_ENGINECFG_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_ENGINECFG_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_ENGINEHEUR_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_ENGINEHEUR_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_ENGINE_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_ENGINE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_EXECUTION_PLAN_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_EXECUTION_PLAN_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_CONVOLUTION_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_CONVOLUTION_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_ENGINECFG_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_ENGINECFG_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_ENGINEHEUR_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_ENGINEHEUR_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_ENGINE_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_ENGINE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_EXECUTION_PLAN_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_EXECUTION_PLAN_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BACKEND_KERNEL_CACHE_DESCRIPTOR`|9.4.0| | | | | | | | | | | | | | | | -|`CUDNN_BACKEND_KNOB_CHOICE_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_KNOB_CHOICE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_KNOB_INFO_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_KNOB_INFO_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_LAYOUT_INFO_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_LAYOUT_INFO_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_MATMUL_DESCRIPTOR`|8.1.0| | | | | | | | | |`MIOPEN_BACKEND_MATMUL_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATIONGRAPH_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATIONGRAPH_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_KNOB_CHOICE_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_KNOB_CHOICE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_KNOB_INFO_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_KNOB_INFO_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_LAYOUT_INFO_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_LAYOUT_INFO_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_MATMUL_DESCRIPTOR`|8.1.0| | | | | | | | | |`MIOPEN_BACKEND_MATMUL_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATIONGRAPH_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATIONGRAPH_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BACKEND_OPERATION_BN_BWD_WEIGHTS_DESCRIPTOR`|8.2.0| | | | | | | | | | | | | | | | |`CUDNN_BACKEND_OPERATION_BN_FINALIZE_STATISTICS_DESCRIPTOR`|8.1.0| | | | | | | | | | | | | | | | -|`CUDNN_BACKEND_OPERATION_CONCAT_DESCRIPTOR`|8.5.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_CONCAT_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_MATMUL_DESCRIPTOR`|8.1.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_MATMUL_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR`|8.5.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR`|8.5.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_OPERATION_CONCAT_DESCRIPTOR`|8.5.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_CONCAT_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_MATMUL_DESCRIPTOR`|8.1.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_MATMUL_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR`|8.5.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR`|8.5.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BACKEND_OPERATION_PAGED_CACHE_LOAD_DESCRIPTOR`|9.4.0| | | | | | | | | | | | | | | | -|`CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR`|8.1.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR`|8.3.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR`|8.3.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR`|8.1.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR`|8.3.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR`|8.3.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BACKEND_OPERATION_RESHAPE_DESCRIPTOR`|8.7.0| | | | | | | | | | | | | | | | -|`CUDNN_BACKEND_OPERATION_RNG_DESCRIPTOR`|8.7.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_RNG_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR`|8.5.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_POINTWISE_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_POINTWISE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_REDUCTION_DESCRIPTOR`|8.1.0| | | | | | | | | |`MIOPEN_BACKEND_REDUCTION_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_RESAMPLE_DESCRIPTOR`|8.3.0| | | | | | | | | |`MIOPEN_BACKEND_RESAMPLE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_RNG_DESCRIPTOR`|8.7.0| | | | | | | | | |`MIOPEN_BACKEND_RNG_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_TENSOR_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_TENSOR_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_VARIANT_PACK_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_VARIANT_PACK_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_OPERATION_RNG_DESCRIPTOR`|8.7.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_RNG_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR`|8.5.0| | | | | | | | | |`MIOPEN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_POINTWISE_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_POINTWISE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_REDUCTION_DESCRIPTOR`|8.1.0| | | | | | | | | |`MIOPEN_BACKEND_REDUCTION_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_RESAMPLE_DESCRIPTOR`|8.3.0| | | | | | | | | |`MIOPEN_BACKEND_RESAMPLE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_RNG_DESCRIPTOR`|8.7.0| | | | | | | | | |`MIOPEN_BACKEND_RNG_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_TENSOR_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_TENSOR_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_VARIANT_PACK_DESCRIPTOR`|8.0.1| | | | | | | | | |`MIOPEN_BACKEND_VARIANT_PACK_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BATCHNORM_OPS_BN`|7.4.1|9.0.0| | | | | | | | | | | | | | | |`CUDNN_BATCHNORM_OPS_BN_ACTIVATION`|7.4.1|9.0.0| | | | | | | | | | | | | | | |`CUDNN_BATCHNORM_OPS_BN_ADD_ACTIVATION`|7.4.1|9.0.0| | | | | | | | | | | | | | | @@ -763,7 +763,7 @@ |`cudnnBackendAttributeName_t`|8.0.1| | | | | | | | | |`miopenBackendAttributeName_t`|6.2.0| | | | | |`cudnnBackendAttributeType_t`|8.0.1| | | | | | | | | |`miopenBackendAttributeType_t`| | | | | | |`cudnnBackendBehaviorNote_t`|8.2.0| | | | | | | | | | | | | | | | -|`cudnnBackendDescriptorType_t`|8.0.1| | | | | | | | | |`miopenBackendDescriptorType_t`| | | | | | +|`cudnnBackendDescriptorType_t`|8.0.1| | | | | | | | | |`miopenBackendDescriptorType_t`|6.2.0| | | | | |`cudnnBackendDescriptor_t`|8.0.1| | | | | | | | | |`miopenBackendDescriptor_t`| | | | | | |`cudnnBackendHeurMode_t`|8.0.1| | | | | | | | | |`miopenBackendHeurMode_t`| | | | | | |`cudnnBackendKnobType_t`|8.0.1| | | | | | | | | | | | | | | | diff --git a/docs/tables/CUDNN_API_supported_by_MIOPEN.md b/docs/tables/CUDNN_API_supported_by_MIOPEN.md index fdc31ab1..65d09d76 100644 --- a/docs/tables/CUDNN_API_supported_by_MIOPEN.md +++ b/docs/tables/CUDNN_API_supported_by_MIOPEN.md @@ -131,7 +131,7 @@ |`CUDNN_ATTR_OPERATION_MATMUL_GEMM_K_OVERRIDE_DESC`|8.7.0| | | |`MIOPEN_ATTR_OPERATION_MATMUL_GEMM_K_OVERRIDE_DESC`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_MATMUL_GEMM_M_OVERRIDE_DESC`|8.7.0| | | |`MIOPEN_ATTR_OPERATION_MATMUL_GEMM_M_OVERRIDE_DESC`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_MATMUL_GEMM_N_OVERRIDE_DESC`|8.7.0| | | |`MIOPEN_ATTR_OPERATION_MATMUL_GEMM_N_OVERRIDE_DESC`|6.2.0| | | | | -|`CUDNN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT`|8.1.0|9.0.0| | |`MIOPEN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT`| | | | | | +|`CUDNN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT`|8.1.0|9.0.0| | |`MIOPEN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_NORM_BWD_DBIAS_DESC`|8.5.0| | | |`MIOPEN_ATTR_OPERATION_NORM_BWD_DBIAS_DESC`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_NORM_BWD_DSCALE_DESC`|8.5.0| | | |`MIOPEN_ATTR_OPERATION_NORM_BWD_DSCALE_DESC`|6.2.0| | | | | |`CUDNN_ATTR_OPERATION_NORM_BWD_DXDESC`|8.5.0| | | |`MIOPEN_ATTR_OPERATION_NORM_BWD_DXDESC`|6.2.0| | | | | @@ -241,42 +241,42 @@ |`CUDNN_ATTR_VARIANT_PACK_INTERMEDIATES`|8.0.1| | | |`MIOPEN_ATTR_VARIANT_PACK_INTERMEDIATES`|6.2.0| | | | | |`CUDNN_ATTR_VARIANT_PACK_UNIQUE_IDS`|8.0.1| | | |`MIOPEN_ATTR_VARIANT_PACK_UNIQUE_IDS`|6.2.0| | | | | |`CUDNN_ATTR_VARIANT_PACK_WORKSPACE`|8.0.1| | | |`MIOPEN_ATTR_VARIANT_PACK_WORKSPACE`|6.2.0| | | | | -|`CUDNN_BACKEND_CONVOLUTION_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_CONVOLUTION_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_ENGINECFG_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_ENGINECFG_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_ENGINEHEUR_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_ENGINEHEUR_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_ENGINE_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_ENGINE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_EXECUTION_PLAN_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_EXECUTION_PLAN_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_CONVOLUTION_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_CONVOLUTION_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_ENGINECFG_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_ENGINECFG_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_ENGINEHEUR_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_ENGINEHEUR_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_ENGINE_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_ENGINE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_EXECUTION_PLAN_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_EXECUTION_PLAN_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BACKEND_KERNEL_CACHE_DESCRIPTOR`|9.4.0| | | | | | | | | | -|`CUDNN_BACKEND_KNOB_CHOICE_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_KNOB_CHOICE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_KNOB_INFO_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_KNOB_INFO_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_LAYOUT_INFO_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_LAYOUT_INFO_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_MATMUL_DESCRIPTOR`|8.1.0| | | |`MIOPEN_BACKEND_MATMUL_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATIONGRAPH_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATIONGRAPH_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_KNOB_CHOICE_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_KNOB_CHOICE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_KNOB_INFO_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_KNOB_INFO_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_LAYOUT_INFO_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_LAYOUT_INFO_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_MATMUL_DESCRIPTOR`|8.1.0| | | |`MIOPEN_BACKEND_MATMUL_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATIONGRAPH_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATIONGRAPH_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BACKEND_OPERATION_BN_BWD_WEIGHTS_DESCRIPTOR`|8.2.0| | | | | | | | | | |`CUDNN_BACKEND_OPERATION_BN_FINALIZE_STATISTICS_DESCRIPTOR`|8.1.0| | | | | | | | | | -|`CUDNN_BACKEND_OPERATION_CONCAT_DESCRIPTOR`|8.5.0| | | |`MIOPEN_BACKEND_OPERATION_CONCAT_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_MATMUL_DESCRIPTOR`|8.1.0| | | |`MIOPEN_BACKEND_OPERATION_MATMUL_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR`|8.5.0| | | |`MIOPEN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR`|8.5.0| | | |`MIOPEN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_OPERATION_CONCAT_DESCRIPTOR`|8.5.0| | | |`MIOPEN_BACKEND_OPERATION_CONCAT_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_MATMUL_DESCRIPTOR`|8.1.0| | | |`MIOPEN_BACKEND_OPERATION_MATMUL_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR`|8.5.0| | | |`MIOPEN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR`|8.5.0| | | |`MIOPEN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BACKEND_OPERATION_PAGED_CACHE_LOAD_DESCRIPTOR`|9.4.0| | | | | | | | | | -|`CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR`|8.1.0| | | |`MIOPEN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR`|8.3.0| | | |`MIOPEN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR`|8.3.0| | | |`MIOPEN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR`|8.1.0| | | |`MIOPEN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR`|8.3.0| | | |`MIOPEN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR`|8.3.0| | | |`MIOPEN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BACKEND_OPERATION_RESHAPE_DESCRIPTOR`|8.7.0| | | | | | | | | | -|`CUDNN_BACKEND_OPERATION_RNG_DESCRIPTOR`|8.7.0| | | |`MIOPEN_BACKEND_OPERATION_RNG_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR`|8.5.0| | | |`MIOPEN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_POINTWISE_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_POINTWISE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_REDUCTION_DESCRIPTOR`|8.1.0| | | |`MIOPEN_BACKEND_REDUCTION_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_RESAMPLE_DESCRIPTOR`|8.3.0| | | |`MIOPEN_BACKEND_RESAMPLE_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_RNG_DESCRIPTOR`|8.7.0| | | |`MIOPEN_BACKEND_RNG_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_TENSOR_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_TENSOR_DESCRIPTOR`| | | | | | -|`CUDNN_BACKEND_VARIANT_PACK_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_VARIANT_PACK_DESCRIPTOR`| | | | | | +|`CUDNN_BACKEND_OPERATION_RNG_DESCRIPTOR`|8.7.0| | | |`MIOPEN_BACKEND_OPERATION_RNG_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR`|8.5.0| | | |`MIOPEN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_POINTWISE_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_POINTWISE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_REDUCTION_DESCRIPTOR`|8.1.0| | | |`MIOPEN_BACKEND_REDUCTION_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_RESAMPLE_DESCRIPTOR`|8.3.0| | | |`MIOPEN_BACKEND_RESAMPLE_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_RNG_DESCRIPTOR`|8.7.0| | | |`MIOPEN_BACKEND_RNG_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_TENSOR_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_TENSOR_DESCRIPTOR`|6.2.0| | | | | +|`CUDNN_BACKEND_VARIANT_PACK_DESCRIPTOR`|8.0.1| | | |`MIOPEN_BACKEND_VARIANT_PACK_DESCRIPTOR`|6.2.0| | | | | |`CUDNN_BATCHNORM_OPS_BN`|7.4.1|9.0.0| | | | | | | | | |`CUDNN_BATCHNORM_OPS_BN_ACTIVATION`|7.4.1|9.0.0| | | | | | | | | |`CUDNN_BATCHNORM_OPS_BN_ADD_ACTIVATION`|7.4.1|9.0.0| | | | | | | | | @@ -763,7 +763,7 @@ |`cudnnBackendAttributeName_t`|8.0.1| | | |`miopenBackendAttributeName_t`|6.2.0| | | | | |`cudnnBackendAttributeType_t`|8.0.1| | | |`miopenBackendAttributeType_t`| | | | | | |`cudnnBackendBehaviorNote_t`|8.2.0| | | | | | | | | | -|`cudnnBackendDescriptorType_t`|8.0.1| | | |`miopenBackendDescriptorType_t`| | | | | | +|`cudnnBackendDescriptorType_t`|8.0.1| | | |`miopenBackendDescriptorType_t`|6.2.0| | | | | |`cudnnBackendDescriptor_t`|8.0.1| | | |`miopenBackendDescriptor_t`| | | | | | |`cudnnBackendHeurMode_t`|8.0.1| | | |`miopenBackendHeurMode_t`| | | | | | |`cudnnBackendKnobType_t`|8.0.1| | | | | | | | | | diff --git a/src/CUDA2HIP_DNN_API_types.cpp b/src/CUDA2HIP_DNN_API_types.cpp index 2e74af4d..b29507f7 100644 --- a/src/CUDA2HIP_DNN_API_types.cpp +++ b/src/CUDA2HIP_DNN_API_types.cpp @@ -912,1245 +912,1278 @@ const std::map CUDA_DNN_TYPE_NAME_MAP { }; const std::map CUDA_DNN_TYPE_NAME_VER_MAP { - {"cudnnForwardMode_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_FWD_MODE_INFERENCE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_FWD_MODE_TRAINING", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"cudnnRNNMode_t", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_RELU", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_TANH", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_LSTM", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_GRU", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnRNNBiasMode_t", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_NO_BIAS", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_SINGLE_INP_BIAS", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_DOUBLE_BIAS", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_SINGLE_REC_BIAS", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"cudnnDirectionMode_t", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_UNIDIRECTIONAL", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_BIDIRECTIONAL", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnRNNInputMode_t", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_LINEAR_INPUT", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_SKIP_INPUT", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnRNNClipMode_t", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_CLIP_NONE", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_CLIP_MINMAX", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"cudnnRNNDataLayout_t", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_DATA_LAYOUT_SEQ_MAJOR_UNPACKED", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_DATA_LAYOUT_SEQ_MAJOR_PACKED", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_DATA_LAYOUT_BATCH_MAJOR_UNPACKED", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"cudnnRNNPaddingMode_t", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_PADDED_IO_DISABLED", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_PADDED_IO_ENABLED", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"cudnnRNNStruct", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnRNNDescriptor_t", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnPersistentRNNPlan", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"cudnnPersistentRNNPlan_t", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"cudnnRNNDataStruct", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"cudnnRNNDataDescriptor_t", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"cudnnWgradMode_t", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_WGRAD_MODE_ADD", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_WGRAD_MODE_SET", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"cudnnBackendDescriptor_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"cudnnPointwiseMode_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_ADD", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_MUL", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_MIN", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_MAX", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_SQRT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_RELU_FWD", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_TANH_FWD", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_SIGMOID_FWD", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_ELU_FWD", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_GELU_FWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_SOFTPLUS_FWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_SWISH_FWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_RELU_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_TANH_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_SIGMOID_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_ELU_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_GELU_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_SOFTPLUS_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_SWISH_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"cudnnGenStatsMode_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_GENSTATS_SUM_SQSUM", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"cudnnBackendAttributeName_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_MATH_PREC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_NAN_PROPAGATION", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_RELU_LOWER_CLIP", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_RELU_UPPER_CLIP", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_RELU_LOWER_CLIP_SLOPE", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_ELU_ALPHA", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_SOFTPLUS_BETA", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_SWISH_BETA", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_CONVOLUTION_COMP_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_CONVOLUTION_CONV_MODE", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_CONVOLUTION_DILATIONS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_CONVOLUTION_FILTER_STRIDES", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_CONVOLUTION_POST_PADDINGS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_CONVOLUTION_PRE_PADDINGS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_CONVOLUTION_SPATIAL_DIMS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINEHEUR_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINEHEUR_OPERATION_GRAPH", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINEHEUR_RESULTS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINECFG_ENGINE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINECFG_INTERMEDIATE_INFO", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINECFG_KNOB_CHOICES", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_EXECUTION_PLAN_HANDLE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_EXECUTION_PLAN_WORKSPACE_SIZE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_EXECUTION_PLAN_COMPUTED_INTERMEDIATE_UIDS", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_EXECUTION_PLAN_RUN_ONLY_INTERMEDIATE_UIDS", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_INTERMEDIATE_INFO_UNIQUE_ID", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_INTERMEDIATE_INFO_SIZE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_EXECUTION_PLAN_ENGINE_CONFIG", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_INTERMEDIATE_INFO_DEPENDENT_DATA_UIDS", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_INTERMEDIATE_INFO_DEPENDENT_ATTRIBUTES", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_KNOB_CHOICE_KNOB_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_KNOB_CHOICE_KNOB_VALUE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_ALPHA", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_BETA", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_CONV_DESC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_W", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_X", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_Y", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_ALPHA", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_BETA", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_CONV_DESC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_W", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_DX", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_DY", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_ALPHA", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_BETA", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_CONV_DESC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_DW", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_X", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_DY", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_POINTWISE_PW_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_POINTWISE_XDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_POINTWISE_BDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_POINTWISE_YDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_POINTWISE_ALPHA1", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_POINTWISE_ALPHA2", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_POINTWISE_DXDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_POINTWISE_DYDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_GENSTATS_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_GENSTATS_MATH_PREC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_GENSTATS_XDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_GENSTATS_SUMDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_GENSTATS_SQSUMDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_STATS_MODE", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_MATH_PREC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_Y_SUM_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_Y_SQ_SUM_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_SCALE_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_BIAS_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_PREV_RUNNING_MEAN_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_PREV_RUNNING_VAR_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_UPDATED_RUNNING_MEAN_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_UPDATED_RUNNING_VAR_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_SAVED_MEAN_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_SAVED_INV_STD_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_EQ_SCALE_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_EQ_BIAS_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_ACCUM_COUNT_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_EPSILON_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_FINALIZE_EXP_AVERATE_FACTOR_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATIONGRAPH_HANDLE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATIONGRAPH_OPS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATIONGRAPH_ENGINE_GLOBAL_COUNT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_BYTE_ALIGNMENT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_DATA_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_DIMENSIONS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_STRIDES", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_VECTOR_COUNT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_VECTORIZED_DIMENSION", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_UNIQUE_ID", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_IS_VIRTUAL", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_IS_BY_VALUE", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_VARIANT_PACK_UNIQUE_IDS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_VARIANT_PACK_WORKSPACE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_VARIANT_PACK_DATA_POINTERS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_VARIANT_PACK_INTERMEDIATES", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_LAYOUT_INFO_TENSOR_UID", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_LAYOUT_INFO_TYPES", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_KNOB_INFO_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_KNOB_INFO_MAXIMUM_VALUE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_KNOB_INFO_MINIMUM_VALUE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_KNOB_INFO_STRIDE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINE_OPERATION_GRAPH", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINE_GLOBAL_INDEX", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINE_KNOB_INFO", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINE_NUMERICAL_NOTE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINE_LAYOUT_INFO", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_MATMUL_COMP_TYPE", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_MATMUL_ADESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_MATMUL_BDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_MATMUL_CDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_MATMUL_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT", {CUDNN_810, CUDNN_900, CUDA_0 }}, - {"CUDNN_ATTR_REDUCTION_OPERATOR", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_REDUCTION_COMP_TYPE", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_REDUCTION_XDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_REDUCTION_YDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_REDUCTION_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"cudnnBackendAttributeType_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_HANDLE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_DATA_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_BOOLEAN", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_INT64", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_FLOAT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_DOUBLE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_VOID_PTR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_CONVOLUTION_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_HEUR_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_KNOB_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_NAN_PROPOGATION", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_TYPE_NUMERICAL_NOTE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_LAYOUT_TYPE", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_ATTRIB_NAME", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_POINTWISE_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_BACKEND_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_GENSTATS_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_BN_FINALIZE_STATS_MODE", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_REDUCTION_OPERATOR_TYPE", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"cudnnBackendDescriptorType_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_POINTWISE_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_CONVOLUTION_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_ENGINE_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_ENGINECFG_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_ENGINEHEUR_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_EXECUTION_PLAN_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_KNOB_CHOICE_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_KNOB_INFO_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_LAYOUT_INFO_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATIONGRAPH_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_VARIANT_PACK_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_TENSOR_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_MATMUL_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_MATMUL_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_BN_FINALIZE_STATISTICS_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_REDUCTION_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"cudnnBackendNumericalNote_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_TENSOR_CORE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_DOWN_CONVERT_INPUTS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_REDUCED_PRECISION_REDUCTION", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_FFT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_NONDETERMINISTIC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_WINOGRAD", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_TYPE_COUNT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"cudnnBackendLayoutType_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_LAYOUT_TYPE_PREFERRED_NCHW", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_LAYOUT_TYPE_PREFERRED_NHWC", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_LAYOUT_TYPE_PREFERRED_PAD4CK", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_LAYOUT_TYPE_PREFERRED_PAD8CK", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"CUDNN_LAYOUT_TYPE_COUNT", {CUDNN_802, CUDA_0, CUDA_0 }}, - {"cudnnBackendKnobType_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SPLIT_K", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SWIZZLE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_TILE_SIZE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_USE_TEX", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_EDGE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_KBLOCK", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_LDGA", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_LDGB", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_CHUNK_K", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SPLIT_H", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_WINO_TILE", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_MULTIPLY", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SPLIT_K_BUF", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_TILEK", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_STAGES", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_REDUCTION_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_CTA_SPLIT_K_MODE", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SPLIT_K_SLC", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_IDX_MODE", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SLICED", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SPLIT_RS", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SINGLEBUFFER", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_LDGC", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SPECFILT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_KERNEL_CFG", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_COUNTS", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"cudnnBackendHeurMode_t", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_HEUR_MODE_INSTANT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_HEUR_MODE_B", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"CUDNN_HEUR_MODES_COUNT", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionFwdAlgoPerf_t", {CUDNN_30, CUDNN_900, CUDA_0 }}, - {"cudnnReorderType_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"CUDNN_DEFAULT_REORDER", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"CUDNN_NO_REORDER", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"cudnnConvolutionMode_t", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_CROSS_CORRELATION", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"cudnnConvolutionStruct", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionDescriptor_t", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"cudnnConvolutionBwdFilterAlgoPerf_t", {CUDNN_30, CUDNN_900, CUDA_0 }}, - {"cudnnContext", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"cudnnHandle_t", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"cudnnStatus_t", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_SUCCESS", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_INITIALIZED", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_ALLOC_FAILED", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_INTERNAL_ERROR", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_INVALID_VALUE", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_STATUS_ARCH_MISMATCH", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_STATUS_MAPPING_ERROR", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_STATUS_EXECUTION_FAILED", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_LICENSE_ERROR", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_RUNTIME_PREREQUISITE_MISSING", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"CUDNN_STATUS_RUNTIME_IN_PROGRESS", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_RUNTIME_FP_OVERFLOW", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_VERSION_MISMATCH", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"cudnnRuntimeTag_t", {CUDNN_705, CUDNN_900, CUDA_0 }}, - {"cudnnErrQueryMode_t", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_ERRQUERY_RAWCODE", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_ERRQUERY_NONBLOCKING", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_ERRQUERY_BLOCKING", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"libraryPropertyType", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"libraryPropertyType_t", {CUDNN_60, CUDA_0, CUDNN_900}}, - {"cudnnTensorDescriptor_t", {CUDNN_20, CUDA_0, CUDA_0 }}, - {"cudnnTensorStruct", {CUDNN_20, CUDA_0, CUDA_0 }}, - {"cudnnPoolingDescriptor_t", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"cudnnPoolingStruct", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"cudnnFilterDescriptor_t", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"cudnnFilterStruct", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"cudnnLRNDescriptor_t", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"cudnnLRNStruct", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"cudnnActivationDescriptor_t", {CUDNN_40, CUDNN_900, CUDA_0 }}, - {"cudnnActivationStruct", {CUDNN_40, CUDNN_900, CUDA_0 }}, - {"cudnnSpatialTransformerDescriptor_t", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnSpatialTransformerStruct", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnOpTensorDescriptor_t", {CUDNN_50, CUDNN_900, CUDA_0 }}, - {"cudnnOpTensorStruct", {CUDNN_50, CUDNN_900, CUDA_0 }}, - {"cudnnReduceTensorDescriptor_t", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"cudnnReduceTensorStruct", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"cudnnCTCLossDescriptor_t", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"cudnnTensorTransformDescriptor_t", {CUDNN_750, CUDNN_900, CUDA_0 }}, - {"cudnnTensorTransformStruct", {CUDNN_750, CUDNN_900, CUDA_0 }}, - {"cudnnDataType_t", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_FLOAT", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_DOUBLE", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_HALF", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_INT8", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_INT32", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_INT8x4", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"CUDNN_DATA_UINT8", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_UINT8x4", {CUDNN_713, CUDNN_900, CUDA_0 }}, - {"CUDNN_DATA_INT8x32", {CUDNN_721, CUDNN_900, CUDA_0 }}, - {"CUDNN_DATA_BFLOAT16", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_INT64", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"cudnnMathType_t", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_DEFAULT_MATH", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_TENSOR_OP_MATH", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION", {CUDNN_721, CUDA_0, CUDA_0 }}, - {"CUDNN_FMA_MATH", {CUDNN_801, CUDA_0, CUDA_0 }}, - {"cudnnNanPropagation_t", {CUDNN_40, CUDA_0, CUDA_0 }}, - {"CUDNN_NOT_PROPAGATE_NAN", {CUDNN_40, CUDNN_900, CUDA_0 }}, - {"CUDNN_PROPAGATE_NAN", {CUDNN_40, CUDNN_900, CUDA_0 }}, - {"cudnnDeterminism_t", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_NON_DETERMINISTIC", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_DETERMINISTIC", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_DIM_MAX", {CUDNN_40, CUDA_0, CUDA_0 }}, - {"cudnnTensorFormat_t", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_TENSOR_NCHW", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_TENSOR_NHWC", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_TENSOR_NCHW_VECT_C", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"cudnnFoldingDirection_t", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_TRANSFORM_FOLD", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_TRANSFORM_UNFOLD", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"cudnnOpTensorOp_t", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_OP_TENSOR_ADD", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_OP_TENSOR_MUL", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_OP_TENSOR_MIN", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_OP_TENSOR_MAX", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_OP_TENSOR_SQRT", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_OP_TENSOR_NOT", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"cudnnReduceTensorOp_t", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_ADD", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_MUL", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_MIN", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_MAX", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_AMAX", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_AVG", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_NORM1", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_NORM2", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_MUL_NO_ZEROS", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"cudnnReduceTensorIndices_t", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_NO_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"CUDNN_REDUCE_TENSOR_FLATTENED_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"cudnnIndicesType_t", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"CUDNN_32BIT_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"CUDNN_64BIT_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"CUDNN_16BIT_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"CUDNN_8BIT_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"cudnnSoftmaxAlgorithm_t", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_SOFTMAX_FAST", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_SOFTMAX_ACCURATE", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_SOFTMAX_LOG", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"cudnnSoftmaxMode_t", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_SOFTMAX_MODE_INSTANCE", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"CUDNN_SOFTMAX_MODE_CHANNEL", {CUDNN_10, CUDA_0, CUDA_0 }}, - {"cudnnPoolingMode_t", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_POOLING_MAX", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_POOLING_AVERAGE_COUNT_INCLUDE_PADDING", {CUDNN_20, CUDNN_900, CUDA_0 }}, - {"CUDNN_POOLING_AVERAGE_COUNT_EXCLUDE_PADDING", {CUDNN_20, CUDNN_900, CUDA_0 }}, - {"CUDNN_POOLING_MAX_DETERMINISTIC", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"cudnnActivationMode_t", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_ACTIVATION_SIGMOID", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_ACTIVATION_RELU", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_ACTIVATION_TANH", {CUDNN_10, CUDNN_900, CUDA_0 }}, - {"CUDNN_ACTIVATION_CLIPPED_RELU", {CUDNN_40, CUDNN_900, CUDA_0 }}, - {"CUDNN_ACTIVATION_ELU", {CUDNN_60, CUDNN_900, CUDA_0 }}, - {"CUDNN_ACTIVATION_IDENTITY", {CUDNN_713, CUDNN_900, CUDA_0 }}, - {"CUDNN_ACTIVATION_SWISH", {CUDNN_820, CUDNN_900, CUDA_0 }}, - {"CUDNN_LRN_MIN_N", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_LRN_MAX_N", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_LRN_MIN_K", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_LRN_MIN_BETA", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"cudnnLRNMode_t", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_LRN_CROSS_CHANNEL_DIM1", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"cudnnDivNormMode_t", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_DIVNORM_PRECOMPUTED_MEANS", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"cudnnBatchNormMode_t", {CUDNN_40, CUDNN_900, CUDA_0 }}, - {"CUDNN_BATCHNORM_PER_ACTIVATION", {CUDNN_40, CUDNN_900, CUDA_0 }}, - {"CUDNN_BATCHNORM_SPATIAL", {CUDNN_40, CUDNN_900, CUDA_0 }}, - {"CUDNN_BATCHNORM_SPATIAL_PERSISTENT", {CUDNN_705, CUDNN_900, CUDA_0 }}, - {"CUDNN_BN_MIN_EPSILON", {CUDNN_40, CUDA_0, CUDA_0 }}, - {"cudnnBatchNormOps_t", {CUDNN_741, CUDNN_900, CUDA_0 }}, - {"CUDNN_BATCHNORM_OPS_BN", {CUDNN_741, CUDNN_900, CUDA_0 }}, - {"CUDNN_BATCHNORM_OPS_BN_ACTIVATION", {CUDNN_741, CUDNN_900, CUDA_0 }}, - {"CUDNN_BATCHNORM_OPS_BN_ADD_ACTIVATION", {CUDNN_741, CUDNN_900, CUDA_0 }}, - {"cudnnNormMode_t", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_NORM_PER_ACTIVATION", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_NORM_PER_CHANNEL", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"cudnnNormAlgo_t", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_NORM_ALGO_STANDARD", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_NORM_ALGO_PERSIST", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"cudnnNormOps_t", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_NORM_OPS_NORM", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_NORM_OPS_NORM_ACTIVATION", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"CUDNN_NORM_OPS_NORM_ADD_ACTIVATION", {CUDNN_801, CUDNN_900, CUDA_0 }}, - {"cudnnSamplerType_t", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_SAMPLER_BILINEAR", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnDropoutDescriptor_t", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnDropoutStruct", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"cudnnAlgorithmDescriptor_t", {CUDNN_713, CUDA_0, CUDNN_900}}, - {"cudnnAlgorithmStruct", {CUDNN_713, CUDA_0, CUDNN_900}}, - {"cudnnAlgorithmPerformance_t", {CUDNN_713, CUDA_0, CUDNN_900}}, - {"cudnnAlgorithmPerformanceStruct", {CUDNN_713, CUDA_0, CUDNN_900}}, - {"cudnnConvolutionFwdAlgo_t", {CUDNN_20, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_FWD_ALGO_IMPLICIT_GEMM", {CUDNN_20, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_FWD_ALGO_IMPLICIT_PRECOMP_GEMM", {CUDNN_20, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_FWD_ALGO_GEMM", {CUDNN_20, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_FWD_ALGO_DIRECT", {CUDNN_20, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_FWD_ALGO_FFT", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_FWD_ALGO_FFT_TILING", {CUDNN_40, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_FWD_ALGO_WINOGRAD", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_FWD_ALGO_WINOGRAD_NONFUSED", {CUDNN_51, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_FWD_ALGO_COUNT", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionBwdFilterAlgo_t", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_0", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_1", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_FFT", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_3", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_WINOGRAD", {CUDNN_51, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_WINOGRAD_NONFUSED", {CUDNN_51, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_FFT_TILING", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_COUNT", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionBwdDataAlgo_t", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_0", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_1", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_FFT", {CUDNN_30, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_FFT_TILING", {CUDNN_40, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_WINOGRAD", {CUDNN_50, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_WINOGRAD_NONFUSED", {CUDNN_51, CUDA_0, CUDA_0 }}, - {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_COUNT", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"cudnnRNNAlgo_t", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_ALGO_STANDARD", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_ALGO_PERSIST_STATIC", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_ALGO_PERSIST_DYNAMIC", {CUDNN_60, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_ALGO_PERSIST_STATIC_SMALL_H", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_RNN_ALGO_COUNT", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"cudnnCTCLossAlgo_t", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_CTC_LOSS_ALGO_DETERMINISTIC", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"CUDNN_CTC_LOSS_ALGO_NON_DETERMINISTIC", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"cudnnAlgorithm_t", {CUDNN_713, CUDA_0, CUDNN_900}}, - {"cudnnSeverity_t", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"CUDNN_SEV_FATAL", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"CUDNN_SEV_ERROR", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"CUDNN_SEV_WARNING", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"CUDNN_SEV_INFO", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"CUDNN_SEV_ERROR_EN", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"CUDNN_SEV_WARNING_EN", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"CUDNN_SEV_INFO_EN", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"cudnnDebug_t", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionFwdPreference_t", {CUDNN_20, CUDNN_765, CUDNN_801}}, - {"CUDNN_CONVOLUTION_FWD_NO_WORKSPACE", {CUDNN_20, CUDNN_765, CUDNN_801}}, - {"CUDNN_CONVOLUTION_FWD_PREFER_FASTEST", {CUDNN_20, CUDNN_765, CUDNN_801}}, - {"CUDNN_CONVOLUTION_FWD_SPECIFY_WORKSPACE_LIMIT", {CUDNN_20, CUDNN_765, CUDNN_801}}, - {"cudnnConvolutionBwdDataAlgoPerf_t", {CUDNN_30, CUDNN_900, CUDA_0 }}, - {"cudnnFusedOpsConstParamStruct", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"cudnnFusedOpsConstParamPack_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"cudnnFusedOpsVariantParamStruct", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"cudnnFusedOpsVariantParamPack_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"cudnnFusedOpsPlanStruct", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"cudnnFusedOpsPlan_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"cudnnFusedOps_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"CUDNN_FUSED_SCALE_BIAS_ACTIVATION_CONV_BNSTATS", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_FUSED_SCALE_BIAS_ACTIVATION_WGRAD", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_FUSED_BN_FINALIZE_STATISTICS_TRAINING", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_FUSED_BN_FINALIZE_STATISTICS_INFERENCE", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_FUSED_CONV_SCALE_BIAS_ADD_ACTIVATION", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_FUSED_SCALE_BIAS_ADD_ACTIVATION_GEN_BITMASK", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_FUSED_DACTIVATION_FORK_DBATCHNORM", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"cudnnFusedOpsConstParamLabel_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"CUDNN_PARAM_XDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_XDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_MODE", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_EQSCALEBIAS_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_EQSCALE_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_EQBIAS_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_ACTIVATION_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_CONV_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_WDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_WDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_DWDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_DWDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_YDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_YDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_DYDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_DYDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_YSTATS_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_YSUM_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_YSQSUM_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_SCALEBIAS_MEANVAR_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_SCALE_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_BIAS_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_SAVED_MEAN_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_SAVED_INVSTD_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_RUNNING_MEAN_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_RUNNING_VAR_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_ZDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_ZDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_Z_EQSCALEBIAS_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_Z_EQSCALE_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_Z_EQBIAS_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_ACTIVATION_BITMASK_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_ACTIVATION_BITMASK_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_DXDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_DXDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_DZDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_DZDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_DSCALE_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PARAM_BN_DBIAS_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"cudnnFusedOpsPointerPlaceHolder_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"CUDNN_PTR_NULL", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_ELEM_ALIGNED", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_16B_ALIGNED", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"cudnnFusedOpsVariantParamLabel_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, - {"CUDNN_PTR_XDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_EQSCALE", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_EQBIAS", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_WDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_DWDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_YDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_DYDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_YSUM", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_YSQSUM", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_WORKSPACE", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_SCALE", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_BIAS", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_SAVED_MEAN", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_SAVED_INVSTD", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_RUNNING_MEAN", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_RUNNING_VAR", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_ZDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_Z_EQSCALE", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_Z_EQBIAS", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_ACTIVATION_BITMASK", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_DXDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_DZDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_DSCALE", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_PTR_BN_DBIAS", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_SCALAR_SIZE_T_WORKSPACE_SIZE_IN_BYTES", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_SCALAR_INT64_T_BN_ACCUMULATION_COUNT", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_SCALAR_DOUBLE_BN_EXP_AVG_FACTOR", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_SCALAR_DOUBLE_BN_EPSILON", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"cudnnSeqDataAxis_t", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_SEQDATA_TIME_DIM", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_SEQDATA_BATCH_DIM", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_SEQDATA_BEAM_DIM", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_SEQDATA_VECT_DIM", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_SEQDATA_DIM_COUNT", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionBwdFilterPreference_t", {CUDNN_30, CUDNN_765, CUDNN_801}}, - {"CUDNN_CONVOLUTION_BWD_FILTER_NO_WORKSPACE", {CUDNN_30, CUDNN_765, CUDNN_801}}, - {"CUDNN_CONVOLUTION_BWD_FILTER_PREFER_FASTEST", {CUDNN_30, CUDNN_765, CUDNN_801}}, - {"CUDNN_CONVOLUTION_BWD_FILTER_SPECIFY_WORKSPACE_LIMIT", {CUDNN_30, CUDNN_765, CUDNN_801}}, - {"cudnnSeqDataStruct", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"cudnnSeqDataDescriptor_t", {CUDNN_750, CUDNN_900, CUDA_0 }}, - {"cudnnAttnQueryMap_t", {CUDNN_750, CUDA_0, CUDNN_900}}, - {"CUDNN_ATTN_QUERYMAP_ALL_TO_ONE", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTN_QUERYMAP_ONE_TO_ONE", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTN_DISABLE_PROJ_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTN_ENABLE_PROJ_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, - {"cudnnAttnStruct", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"cudnnAttnDescriptor_t", {CUDNN_750, CUDNN_900, CUDA_0 }}, - {"cudnnMultiHeadAttnWeightKind_t", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_MH_ATTN_Q_WEIGHTS", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_MH_ATTN_K_WEIGHTS", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_MH_ATTN_V_WEIGHTS", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_MH_ATTN_O_WEIGHTS", {CUDNN_750, CUDA_0, CUDA_0 }}, - {"CUDNN_MH_ATTN_Q_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, - {"CUDNN_MH_ATTN_K_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, - {"CUDNN_MH_ATTN_V_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, - {"CUDNN_MH_ATTN_O_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTN_WKIND_COUNT", {CUDNN_763, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionBwdDataPreference_t", {CUDNN_30, CUDNN_765, CUDNN_801}}, - {"CUDNN_CONVOLUTION_BWD_DATA_NO_WORKSPACE", {CUDNN_30, CUDNN_765, CUDNN_801}}, - {"CUDNN_CONVOLUTION_BWD_DATA_PREFER_FASTEST", {CUDNN_30, CUDNN_765, CUDNN_801}}, - {"CUDNN_CONVOLUTION_BWD_DATA_SPECIFY_WORKSPACE_LIMIT", {CUDNN_30, CUDNN_765, CUDNN_801}}, - {"cudnnLossNormalizationMode_t", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_LOSS_NORMALIZATION_NONE", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"CUDNN_LOSS_NORMALIZATION_SOFTMAX", {CUDNN_760, CUDA_0, CUDA_0 }}, - {"cudnnCTCLossStruct", {CUDNN_705, CUDA_0, CUDA_0 }}, - {"cudnnCallback_t", {CUDNN_713, CUDA_0, CUDA_0 }}, - {"cudnnBnFinalizeStatsMode_t", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_BN_FINALIZE_STATISTICS_TRAINING", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"CUDNN_BN_FINALIZE_STATISTICS_INFERENCE", {CUDNN_810, CUDA_0, CUDA_0 }}, - {"cudnnAlgorithmUnionStruct", {CUDNN_820, CUDA_0, CUDNN_900}}, - {"cudnnDebugStruct", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionBwdFilterAlgoPerfStruct", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionFwdAlgoPerfStruct", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"cudnnConvolutionBwdDataAlgoPerfStruct", {CUDNN_820, CUDNN_900, CUDA_0 }}, - {"CUDNN_ATTR_ENGINE_BEHAVIOR_NOTE", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_MATH_PREC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_MEAN_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_INVSTD_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_BN_SCALE_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_X_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_DY_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_DBN_SCALE_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_DBN_BIAS_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_DY_SCALE_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_X_SCALE_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_BIAS", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_BEHAVIOR_NOTE", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"cudnnBackendBehaviorNote_t", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_BEHAVIOR_NOTE_RUNTIME_COMPILATION", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_BEHAVIOR_NOTE_TYPE_COUNT", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_BN_BWD_WEIGHTS_DESCRIPTOR", {CUDNN_820, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_BOOLEAN", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_ADD_SQUARE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_DIV", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_MOD", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_POW", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_SUB", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_ABS", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_CEIL", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_COS", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_EXP", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_FLOOR", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_LOG", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_NEG", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_RSQRT", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_SIN", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_TAN", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_ERF", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_IDENTITY", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_GELU_APPROX_TANH_FWD", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_GELU_APPROX_TANH_BWD", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_CMP_EQ", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_CMP_NEQ", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_CMP_GT", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_CMP_GE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_CMP_LT", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_CMP_LE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_LOGICAL_AND", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_LOGICAL_OR", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_LOGICAL_NOT", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_GEN_INDEX", {CUDNN_840, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_BINARY_SELECT", {CUDNN_840, CUDA_0, CUDA_0 }}, - {"cudnnFractionStruct", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"cudnnFraction_t", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"cudnnResampleMode_t", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_RESAMPLE_NEAREST", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_RESAMPLE_BILINEAR", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_RESAMPLE_AVGPOOL", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_RESAMPLE_MAXPOOL", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"cudnnSignalMode_t", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_SIGNAL_SET", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_SIGNAL_WAIT", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_POINTWISE_AXIS", {CUDNN_840, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_EXECUTION_PLAN_JSON_REPRESENTATION", {CUDNN_840, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_POINTWISE_TDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_REORDERING_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RESAMPLE_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RESAMPLE_COMP_TYPE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RESAMPLE_SPATIAL_DIMS", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RESAMPLE_POST_PADDINGS", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RESAMPLE_PRE_PADDINGS", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RESAMPLE_STRIDES", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RESAMPLE_WINDOW_DIMS", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RESAMPLE_NAN_PROPAGATION", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RESAMPLE_PADDING_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_XDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_YDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_IDXDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_ALPHA", {CUDNN_830, CUDNN_900, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_BETA", {CUDNN_830, CUDNN_900, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_DESC", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_DXDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_DYDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_IDXDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_ALPHA", {CUDNN_830, CUDNN_900, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_BETA", {CUDNN_830, CUDNN_900, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_DESC", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONCAT_AXIS", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONCAT_INPUT_DESCS", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONCAT_INPLACE_INDEX", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_CONCAT_OUTPUT_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_SIGNAL_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_SIGNAL_FLAGDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_SIGNAL_VALUE", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_SIGNAL_XDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_SIGNAL_YDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_PHASE", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_XDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_MEAN_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_INV_VARIANCE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_SCALE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_BIAS_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_EPSILON_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_EXP_AVG_FACTOR_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_INPUT_RUNNING_MEAN_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_INPUT_RUNNING_VAR_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_OUTPUT_RUNNING_MEAN_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_OUTPUT_RUNNING_VAR_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_YDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_FWD_PEER_STAT_DESCS", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_XDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_MEAN_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_INV_VARIANCE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_DYDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_SCALE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_EPSILON_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_DSCALE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_DBIAS_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_DXDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_NORM_BWD_PEER_STAT_DESCS", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_TENSOR_REORDERING_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_RESAMPLE_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_PADDING_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_INT32", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_CHAR", {CUDNN_840, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_SIGNAL_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_FRACTION", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_NORM_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_NORM_FWD_PHASE", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_RESAMPLE_DESCRIPTOR", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_CONCAT_DESCRIPTOR", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_WINOGRAD_TILE_4x4", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_WINOGRAD_TILE_6x6", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_WINOGRAD_TILE_13x13", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_BEHAVIOR_NOTE_REQUIRES_FILTER_INT8x32_REORDER", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_BEHAVIOR_NOTE_REQUIRES_BIAS_INT8x32_REORDER", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_WORKSPACE", {CUDNN_840, CUDA_0, CUDA_0 }}, - {"CUDNN_HEUR_MODE_FALLBACK", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_HEUR_MODE_A", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"cudnnBackendTensorReordering_t", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_TENSOR_REORDERING_NONE", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_TENSOR_REORDERING_INT8x32", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"cudnnPaddingMode_t", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_ZERO_PAD", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_NEG_INF_PAD", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"CUDNN_EDGE_VAL_PAD", {CUDNN_830, CUDA_0, CUDA_0 }}, - {"cudnnBackendNormMode_t", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_LAYER_NORM", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_INSTANCE_NORM", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_BATCH_NORM", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_GROUP_NORM", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"cudnnBackendNormFwdPhase_t", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_NORM_FWD_INFERENCE", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_NORM_FWD_TRAINING", {CUDNN_850, CUDA_0, CUDA_0 }}, - {"CUDNN_RESAMPLE_AVGPOOL_INCLUDE_PADDING", {CUDNN_860, CUDA_0, CUDA_0 }}, - {"CUDNN_RESAMPLE_AVGPOOL_EXCLUDE_PADDING", {CUDNN_860, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_TILE_CGA", {CUDNN_860, CUDNN_900, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_TILE_CGA_M", {CUDNN_860, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_TILE_CGA_N", {CUDNN_860, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_FP8_E4M3", {CUDNN_860, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_FP8_E5M2", {CUDNN_860, CUDA_0, CUDA_0 }}, - {"CUDNN_DATA_FAST_FLOAT_FOR_FP8", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"cudnnRngDistribution_t", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_RNG_DISTRIBUTION_BERNOULLI", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_RNG_DISTRIBUTION_UNIFORM", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_RNG_DISTRIBUTION_NORMAL", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_MATMUL_GEMM_M_OVERRIDE_DESC", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_MATMUL_GEMM_N_OVERRIDE_DESC", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_MATMUL_GEMM_K_OVERRIDE_DESC", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_XDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_YDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESHAPE_XDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RESHAPE_YDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RNG_DISTRIBUTION", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RNG_NORMAL_DIST_MEAN", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RNG_NORMAL_DIST_STANDARD_DEVIATION", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RNG_UNIFORM_DIST_MAXIMUM", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RNG_UNIFORM_DIST_MINIMUM", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_RNG_BERNOULLI_DIST_PROBABILITY", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RNG_YDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RNG_SEED", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RNG_DESC", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_TYPE_RNG_DISTRIBUTION", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_RESHAPE_DESCRIPTOR", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_RNG_DESCRIPTOR", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_RNG_DESCRIPTOR", {CUDNN_870, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_RNG_OFFSET_DESC", {CUDNN_880, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_BLOCK_SIZE", {CUDNN_880, CUDA_0, CUDA_0 }}, - {"CUDNN_TENSOR_REORDERING_F16x16", {CUDNN_880, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_RECIPROCAL", {CUDNN_890, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_TENSOR_RAGGED_OFFSET_DESC", {CUDNN_890, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_MATMUL_PADDING_VALUE", {CUDNN_890, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_OCCUPANCY", {CUDNN_890, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_ARRAY_SIZE_PER_THREAD", {CUDNN_890, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_NUM_C_PER_BLOCK", {CUDNN_890, CUDNN_900, CUDA_0 }}, - {"CUDNN_ATTR_ENGINEHEUR_SM_COUNT_TARGET", {CUDNN_895, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINE_SM_COUNT_TARGET", {CUDNN_895, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_SPLIT_COLS", {CUDNN_895, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_TILE_ROWS", {CUDNN_895, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_TILE_COLS", {CUDNN_895, CUDA_0, CUDA_0 }}, - {"CUDNN_KNOB_TYPE_LOAD_SIZE", {CUDNN_895, CUDA_0, CUDA_0 }}, - {"CUDNN_RMS_NORM", {CUDNN_896, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_SUBLIBRARY_VERSION_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_SERIALIZATION_VERSION_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_DEPRECATED", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM_NULL_POINTER", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM_MISALIGNED_POINTER", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM_NOT_FINALIZED", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM_OUT_OF_BOUND", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM_SIZE_INSUFFICIENT", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM_STREAM_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM_SHAPE_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM_DUPLICATED_ENTRIES", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_BAD_PARAM_ATTRIBUTE_TYPE", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_GRAPH_PATTERN", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_SHAPE", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_DATA_TYPE", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_LAYOUT", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_INCOMPATIBLE_CUDA_DRIVER", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_INCOMPATIBLE_CUDART", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_ARCH_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_RUNTIME_PREREQUISITE_MISSING", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_SUBLIBRARY_UNAVAILABLE", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_SHARED_MEMORY_INSUFFICIENT", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_PADDING", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_NOT_SUPPORTED_BAD_LAUNCH_PARAM", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_INTERNAL_ERROR_COMPILATION_FAILED", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_INTERNAL_ERROR_UNEXPECTED_VALUE", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_INTERNAL_ERROR_HOST_ALLOCATION_FAILED", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_INTERNAL_ERROR_DEVICE_ALLOCATION_FAILED", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_INTERNAL_ERROR_BAD_LAUNCH_PARAM", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_INTERNAL_ERROR_TEXTURE_CREATION_FAILED", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_EXECUTION_FAILED_CUDA_DRIVER", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_EXECUTION_FAILED_CUBLAS", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_EXECUTION_FAILED_CUDART", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_EXECUTION_FAILED_CURAND", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_FULL_ERROR_CODE", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_CATEGORY", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_SPECIFIC_ERROR", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_POINTWISE_ATAN2", {CUDNN_910, CUDA_0, CUDA_0 }}, - {"CUDNN_NUMERICAL_NOTE_STRICT_NAN_PROP", {CUDNN_910, CUDA_0, CUDA_0 }}, - {"CUDNN_STATUS_SUBLIBRARY_LOADING_FAILED", {CUDNN_920, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINECFG_WORKSPACE_SIZE", {CUDNN_920, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_ENGINECFG_SHARED_MEMORY_USED", {CUDNN_920, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_EXECUTION_PLAN_KERNEL_CACHE", {CUDNN_940, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATIONGRAPH_IS_DYNAMIC_SHAPE_ENABLED", {CUDNN_940, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_PAGED_CACHE_LOAD_CONTAINER_DESC", {CUDNN_940, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_PAGED_CACHE_LOAD_YDESC", {CUDNN_940, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_PAGED_CACHE_LOAD_SEQUENCE_DESC", {CUDNN_940, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_OPERATION_PAGED_CACHE_LOAD_PAGE_TABLE_DESC", {CUDNN_940, CUDA_0, CUDA_0 }}, - {"CUDNN_ATTR_KERNEL_CACHE_IS_ENGINECFG_KERNEL_CACHED", {CUDNN_940, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_KERNEL_CACHE_DESCRIPTOR", {CUDNN_940, CUDA_0, CUDA_0 }}, - {"CUDNN_BACKEND_OPERATION_PAGED_CACHE_LOAD_DESCRIPTOR", {CUDNN_940, CUDA_0, CUDA_0 }}, - {"cudnnCTCGradMode_t", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_CTC_ZERO_OOB_GRADIENTS", {CUDNN_900, CUDA_0, CUDA_0 }}, - {"CUDNN_CTC_SKIP_OOB_GRADIENTS", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"cudnnForwardMode_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_FWD_MODE_INFERENCE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_FWD_MODE_TRAINING", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"cudnnRNNMode_t", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_RELU", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_TANH", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_LSTM", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_GRU", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnRNNBiasMode_t", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_NO_BIAS", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_SINGLE_INP_BIAS", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_DOUBLE_BIAS", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_SINGLE_REC_BIAS", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"cudnnDirectionMode_t", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_UNIDIRECTIONAL", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_BIDIRECTIONAL", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnRNNInputMode_t", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_LINEAR_INPUT", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_SKIP_INPUT", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnRNNClipMode_t", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_CLIP_NONE", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_CLIP_MINMAX", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"cudnnRNNDataLayout_t", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_DATA_LAYOUT_SEQ_MAJOR_UNPACKED", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_DATA_LAYOUT_SEQ_MAJOR_PACKED", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_DATA_LAYOUT_BATCH_MAJOR_UNPACKED", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"cudnnRNNPaddingMode_t", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_PADDED_IO_DISABLED", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_PADDED_IO_ENABLED", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"cudnnRNNStruct", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnRNNDescriptor_t", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnPersistentRNNPlan", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"cudnnPersistentRNNPlan_t", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"cudnnRNNDataStruct", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"cudnnRNNDataDescriptor_t", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"cudnnWgradMode_t", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_WGRAD_MODE_ADD", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_WGRAD_MODE_SET", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"cudnnBackendDescriptor_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"cudnnPointwiseMode_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_ADD", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_MUL", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_MIN", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_MAX", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_SQRT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_RELU_FWD", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_TANH_FWD", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_SIGMOID_FWD", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_ELU_FWD", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_GELU_FWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_SOFTPLUS_FWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_SWISH_FWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_RELU_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_TANH_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_SIGMOID_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_ELU_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_GELU_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_SOFTPLUS_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_SWISH_BWD", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"cudnnGenStatsMode_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_GENSTATS_SUM_SQSUM", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"cudnnBackendAttributeName_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_MATH_PREC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_NAN_PROPAGATION", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_RELU_LOWER_CLIP", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_RELU_UPPER_CLIP", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_RELU_LOWER_CLIP_SLOPE", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_ELU_ALPHA", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_SOFTPLUS_BETA", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_SWISH_BETA", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_CONVOLUTION_COMP_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_CONVOLUTION_CONV_MODE", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_CONVOLUTION_DILATIONS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_CONVOLUTION_FILTER_STRIDES", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_CONVOLUTION_POST_PADDINGS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_CONVOLUTION_PRE_PADDINGS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_CONVOLUTION_SPATIAL_DIMS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINEHEUR_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINEHEUR_OPERATION_GRAPH", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINEHEUR_RESULTS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINECFG_ENGINE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINECFG_INTERMEDIATE_INFO", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINECFG_KNOB_CHOICES", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_EXECUTION_PLAN_HANDLE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_EXECUTION_PLAN_WORKSPACE_SIZE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_EXECUTION_PLAN_COMPUTED_INTERMEDIATE_UIDS", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_EXECUTION_PLAN_RUN_ONLY_INTERMEDIATE_UIDS", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_INTERMEDIATE_INFO_UNIQUE_ID", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_INTERMEDIATE_INFO_SIZE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_EXECUTION_PLAN_ENGINE_CONFIG", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_INTERMEDIATE_INFO_DEPENDENT_DATA_UIDS", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_INTERMEDIATE_INFO_DEPENDENT_ATTRIBUTES", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_KNOB_CHOICE_KNOB_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_KNOB_CHOICE_KNOB_VALUE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_ALPHA", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_BETA", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_CONV_DESC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_W", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_X", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_Y", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_ALPHA", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_BETA", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_CONV_DESC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_W", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_DX", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_DY", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_ALPHA", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_BETA", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_CONV_DESC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_DW", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_X", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_DY", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_POINTWISE_PW_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_POINTWISE_XDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_POINTWISE_BDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_POINTWISE_YDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_POINTWISE_ALPHA1", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_POINTWISE_ALPHA2", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_POINTWISE_DXDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_POINTWISE_DYDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_GENSTATS_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_GENSTATS_MATH_PREC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_GENSTATS_XDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_GENSTATS_SUMDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_GENSTATS_SQSUMDESC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_STATS_MODE", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_MATH_PREC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_Y_SUM_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_Y_SQ_SUM_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_SCALE_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_BIAS_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_PREV_RUNNING_MEAN_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_PREV_RUNNING_VAR_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_UPDATED_RUNNING_MEAN_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_UPDATED_RUNNING_VAR_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_SAVED_MEAN_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_SAVED_INV_STD_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_EQ_SCALE_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_EQ_BIAS_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_ACCUM_COUNT_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_EPSILON_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_FINALIZE_EXP_AVERATE_FACTOR_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATIONGRAPH_HANDLE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATIONGRAPH_OPS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATIONGRAPH_ENGINE_GLOBAL_COUNT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_BYTE_ALIGNMENT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_DATA_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_DIMENSIONS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_STRIDES", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_VECTOR_COUNT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_VECTORIZED_DIMENSION", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_UNIQUE_ID", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_IS_VIRTUAL", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_IS_BY_VALUE", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_VARIANT_PACK_UNIQUE_IDS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_VARIANT_PACK_WORKSPACE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_VARIANT_PACK_DATA_POINTERS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_VARIANT_PACK_INTERMEDIATES", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_LAYOUT_INFO_TENSOR_UID", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_LAYOUT_INFO_TYPES", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_KNOB_INFO_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_KNOB_INFO_MAXIMUM_VALUE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_KNOB_INFO_MINIMUM_VALUE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_KNOB_INFO_STRIDE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINE_OPERATION_GRAPH", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINE_GLOBAL_INDEX", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINE_KNOB_INFO", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINE_NUMERICAL_NOTE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINE_LAYOUT_INFO", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_MATMUL_COMP_TYPE", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_MATMUL_ADESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_MATMUL_BDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_MATMUL_CDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_MATMUL_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT", {CUDNN_810, CUDNN_900, CUDA_0 }}, + {"CUDNN_ATTR_REDUCTION_OPERATOR", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_REDUCTION_COMP_TYPE", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_REDUCTION_XDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_REDUCTION_YDESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_REDUCTION_DESC", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"cudnnBackendAttributeType_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_HANDLE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_DATA_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_BOOLEAN", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_INT64", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_FLOAT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_DOUBLE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_VOID_PTR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_CONVOLUTION_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_HEUR_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_KNOB_TYPE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_NAN_PROPOGATION", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_TYPE_NUMERICAL_NOTE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_LAYOUT_TYPE", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_ATTRIB_NAME", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_POINTWISE_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_BACKEND_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_GENSTATS_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_BN_FINALIZE_STATS_MODE", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_REDUCTION_OPERATOR_TYPE", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"cudnnBackendDescriptorType_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_POINTWISE_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_CONVOLUTION_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_ENGINE_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_ENGINECFG_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_ENGINEHEUR_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_EXECUTION_PLAN_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_KNOB_CHOICE_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_KNOB_INFO_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_LAYOUT_INFO_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATIONGRAPH_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_VARIANT_PACK_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_TENSOR_DESCRIPTOR", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_MATMUL_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_MATMUL_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_BN_FINALIZE_STATISTICS_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_REDUCTION_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"cudnnBackendNumericalNote_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_TENSOR_CORE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_DOWN_CONVERT_INPUTS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_REDUCED_PRECISION_REDUCTION", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_FFT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_NONDETERMINISTIC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_WINOGRAD", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_TYPE_COUNT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"cudnnBackendLayoutType_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_LAYOUT_TYPE_PREFERRED_NCHW", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_LAYOUT_TYPE_PREFERRED_NHWC", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_LAYOUT_TYPE_PREFERRED_PAD4CK", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_LAYOUT_TYPE_PREFERRED_PAD8CK", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"CUDNN_LAYOUT_TYPE_COUNT", {CUDNN_802, CUDA_0, CUDA_0 }}, + {"cudnnBackendKnobType_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SPLIT_K", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SWIZZLE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_TILE_SIZE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_USE_TEX", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_EDGE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_KBLOCK", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_LDGA", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_LDGB", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_CHUNK_K", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SPLIT_H", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_WINO_TILE", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_MULTIPLY", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SPLIT_K_BUF", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_TILEK", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_STAGES", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_REDUCTION_MODE", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_CTA_SPLIT_K_MODE", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SPLIT_K_SLC", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_IDX_MODE", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SLICED", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SPLIT_RS", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SINGLEBUFFER", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_LDGC", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SPECFILT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_KERNEL_CFG", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_COUNTS", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"cudnnBackendHeurMode_t", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_HEUR_MODE_INSTANT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_HEUR_MODE_B", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"CUDNN_HEUR_MODES_COUNT", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionFwdAlgoPerf_t", {CUDNN_30, CUDNN_900, CUDA_0 }}, + {"cudnnReorderType_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"CUDNN_DEFAULT_REORDER", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"CUDNN_NO_REORDER", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"cudnnConvolutionMode_t", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_CROSS_CORRELATION", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"cudnnConvolutionStruct", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionDescriptor_t", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"cudnnConvolutionBwdFilterAlgoPerf_t", {CUDNN_30, CUDNN_900, CUDA_0 }}, + {"cudnnContext", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"cudnnHandle_t", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"cudnnStatus_t", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_SUCCESS", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_INITIALIZED", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_ALLOC_FAILED", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_INTERNAL_ERROR", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_INVALID_VALUE", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_STATUS_ARCH_MISMATCH", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_STATUS_MAPPING_ERROR", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_STATUS_EXECUTION_FAILED", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_LICENSE_ERROR", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_RUNTIME_PREREQUISITE_MISSING", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"CUDNN_STATUS_RUNTIME_IN_PROGRESS", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_RUNTIME_FP_OVERFLOW", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_VERSION_MISMATCH", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"cudnnRuntimeTag_t", {CUDNN_705, CUDNN_900, CUDA_0 }}, + {"cudnnErrQueryMode_t", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_ERRQUERY_RAWCODE", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_ERRQUERY_NONBLOCKING", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_ERRQUERY_BLOCKING", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"libraryPropertyType", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"libraryPropertyType_t", {CUDNN_60, CUDA_0, CUDNN_900}}, + {"cudnnTensorDescriptor_t", {CUDNN_20, CUDA_0, CUDA_0 }}, + {"cudnnTensorStruct", {CUDNN_20, CUDA_0, CUDA_0 }}, + {"cudnnPoolingDescriptor_t", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"cudnnPoolingStruct", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"cudnnFilterDescriptor_t", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"cudnnFilterStruct", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"cudnnLRNDescriptor_t", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"cudnnLRNStruct", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"cudnnActivationDescriptor_t", {CUDNN_40, CUDNN_900, CUDA_0 }}, + {"cudnnActivationStruct", {CUDNN_40, CUDNN_900, CUDA_0 }}, + {"cudnnSpatialTransformerDescriptor_t", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnSpatialTransformerStruct", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnOpTensorDescriptor_t", {CUDNN_50, CUDNN_900, CUDA_0 }}, + {"cudnnOpTensorStruct", {CUDNN_50, CUDNN_900, CUDA_0 }}, + {"cudnnReduceTensorDescriptor_t", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"cudnnReduceTensorStruct", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"cudnnCTCLossDescriptor_t", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"cudnnTensorTransformDescriptor_t", {CUDNN_750, CUDNN_900, CUDA_0 }}, + {"cudnnTensorTransformStruct", {CUDNN_750, CUDNN_900, CUDA_0 }}, + {"cudnnDataType_t", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_FLOAT", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_DOUBLE", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_HALF", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_INT8", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_INT32", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_INT8x4", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"CUDNN_DATA_UINT8", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_UINT8x4", {CUDNN_713, CUDNN_900, CUDA_0 }}, + {"CUDNN_DATA_INT8x32", {CUDNN_721, CUDNN_900, CUDA_0 }}, + {"CUDNN_DATA_BFLOAT16", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_INT64", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"cudnnMathType_t", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_DEFAULT_MATH", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_TENSOR_OP_MATH", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION", {CUDNN_721, CUDA_0, CUDA_0 }}, + {"CUDNN_FMA_MATH", {CUDNN_801, CUDA_0, CUDA_0 }}, + {"cudnnNanPropagation_t", {CUDNN_40, CUDA_0, CUDA_0 }}, + {"CUDNN_NOT_PROPAGATE_NAN", {CUDNN_40, CUDNN_900, CUDA_0 }}, + {"CUDNN_PROPAGATE_NAN", {CUDNN_40, CUDNN_900, CUDA_0 }}, + {"cudnnDeterminism_t", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_NON_DETERMINISTIC", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_DETERMINISTIC", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_DIM_MAX", {CUDNN_40, CUDA_0, CUDA_0 }}, + {"cudnnTensorFormat_t", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_TENSOR_NCHW", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_TENSOR_NHWC", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_TENSOR_NCHW_VECT_C", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"cudnnFoldingDirection_t", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_TRANSFORM_FOLD", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_TRANSFORM_UNFOLD", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"cudnnOpTensorOp_t", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_OP_TENSOR_ADD", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_OP_TENSOR_MUL", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_OP_TENSOR_MIN", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_OP_TENSOR_MAX", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_OP_TENSOR_SQRT", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_OP_TENSOR_NOT", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"cudnnReduceTensorOp_t", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_ADD", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_MUL", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_MIN", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_MAX", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_AMAX", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_AVG", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_NORM1", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_NORM2", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_MUL_NO_ZEROS", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"cudnnReduceTensorIndices_t", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_NO_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"CUDNN_REDUCE_TENSOR_FLATTENED_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"cudnnIndicesType_t", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"CUDNN_32BIT_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"CUDNN_64BIT_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"CUDNN_16BIT_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"CUDNN_8BIT_INDICES", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"cudnnSoftmaxAlgorithm_t", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_SOFTMAX_FAST", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_SOFTMAX_ACCURATE", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_SOFTMAX_LOG", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"cudnnSoftmaxMode_t", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_SOFTMAX_MODE_INSTANCE", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"CUDNN_SOFTMAX_MODE_CHANNEL", {CUDNN_10, CUDA_0, CUDA_0 }}, + {"cudnnPoolingMode_t", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_POOLING_MAX", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_POOLING_AVERAGE_COUNT_INCLUDE_PADDING", {CUDNN_20, CUDNN_900, CUDA_0 }}, + {"CUDNN_POOLING_AVERAGE_COUNT_EXCLUDE_PADDING", {CUDNN_20, CUDNN_900, CUDA_0 }}, + {"CUDNN_POOLING_MAX_DETERMINISTIC", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"cudnnActivationMode_t", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_ACTIVATION_SIGMOID", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_ACTIVATION_RELU", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_ACTIVATION_TANH", {CUDNN_10, CUDNN_900, CUDA_0 }}, + {"CUDNN_ACTIVATION_CLIPPED_RELU", {CUDNN_40, CUDNN_900, CUDA_0 }}, + {"CUDNN_ACTIVATION_ELU", {CUDNN_60, CUDNN_900, CUDA_0 }}, + {"CUDNN_ACTIVATION_IDENTITY", {CUDNN_713, CUDNN_900, CUDA_0 }}, + {"CUDNN_ACTIVATION_SWISH", {CUDNN_820, CUDNN_900, CUDA_0 }}, + {"CUDNN_LRN_MIN_N", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_LRN_MAX_N", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_LRN_MIN_K", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_LRN_MIN_BETA", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"cudnnLRNMode_t", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_LRN_CROSS_CHANNEL_DIM1", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"cudnnDivNormMode_t", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_DIVNORM_PRECOMPUTED_MEANS", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"cudnnBatchNormMode_t", {CUDNN_40, CUDNN_900, CUDA_0 }}, + {"CUDNN_BATCHNORM_PER_ACTIVATION", {CUDNN_40, CUDNN_900, CUDA_0 }}, + {"CUDNN_BATCHNORM_SPATIAL", {CUDNN_40, CUDNN_900, CUDA_0 }}, + {"CUDNN_BATCHNORM_SPATIAL_PERSISTENT", {CUDNN_705, CUDNN_900, CUDA_0 }}, + {"CUDNN_BN_MIN_EPSILON", {CUDNN_40, CUDA_0, CUDA_0 }}, + {"cudnnBatchNormOps_t", {CUDNN_741, CUDNN_900, CUDA_0 }}, + {"CUDNN_BATCHNORM_OPS_BN", {CUDNN_741, CUDNN_900, CUDA_0 }}, + {"CUDNN_BATCHNORM_OPS_BN_ACTIVATION", {CUDNN_741, CUDNN_900, CUDA_0 }}, + {"CUDNN_BATCHNORM_OPS_BN_ADD_ACTIVATION", {CUDNN_741, CUDNN_900, CUDA_0 }}, + {"cudnnNormMode_t", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_NORM_PER_ACTIVATION", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_NORM_PER_CHANNEL", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"cudnnNormAlgo_t", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_NORM_ALGO_STANDARD", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_NORM_ALGO_PERSIST", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"cudnnNormOps_t", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_NORM_OPS_NORM", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_NORM_OPS_NORM_ACTIVATION", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"CUDNN_NORM_OPS_NORM_ADD_ACTIVATION", {CUDNN_801, CUDNN_900, CUDA_0 }}, + {"cudnnSamplerType_t", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_SAMPLER_BILINEAR", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnDropoutDescriptor_t", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnDropoutStruct", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"cudnnAlgorithmDescriptor_t", {CUDNN_713, CUDA_0, CUDNN_900}}, + {"cudnnAlgorithmStruct", {CUDNN_713, CUDA_0, CUDNN_900}}, + {"cudnnAlgorithmPerformance_t", {CUDNN_713, CUDA_0, CUDNN_900}}, + {"cudnnAlgorithmPerformanceStruct", {CUDNN_713, CUDA_0, CUDNN_900}}, + {"cudnnConvolutionFwdAlgo_t", {CUDNN_20, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_FWD_ALGO_IMPLICIT_GEMM", {CUDNN_20, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_FWD_ALGO_IMPLICIT_PRECOMP_GEMM", {CUDNN_20, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_FWD_ALGO_GEMM", {CUDNN_20, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_FWD_ALGO_DIRECT", {CUDNN_20, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_FWD_ALGO_FFT", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_FWD_ALGO_FFT_TILING", {CUDNN_40, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_FWD_ALGO_WINOGRAD", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_FWD_ALGO_WINOGRAD_NONFUSED", {CUDNN_51, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_FWD_ALGO_COUNT", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionBwdFilterAlgo_t", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_0", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_1", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_FFT", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_3", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_WINOGRAD", {CUDNN_51, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_WINOGRAD_NONFUSED", {CUDNN_51, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_FFT_TILING", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_FILTER_ALGO_COUNT", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionBwdDataAlgo_t", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_0", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_1", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_FFT", {CUDNN_30, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_FFT_TILING", {CUDNN_40, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_WINOGRAD", {CUDNN_50, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_WINOGRAD_NONFUSED", {CUDNN_51, CUDA_0, CUDA_0 }}, + {"CUDNN_CONVOLUTION_BWD_DATA_ALGO_COUNT", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"cudnnRNNAlgo_t", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_ALGO_STANDARD", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_ALGO_PERSIST_STATIC", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_ALGO_PERSIST_DYNAMIC", {CUDNN_60, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_ALGO_PERSIST_STATIC_SMALL_H", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_RNN_ALGO_COUNT", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"cudnnCTCLossAlgo_t", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_CTC_LOSS_ALGO_DETERMINISTIC", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"CUDNN_CTC_LOSS_ALGO_NON_DETERMINISTIC", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"cudnnAlgorithm_t", {CUDNN_713, CUDA_0, CUDNN_900}}, + {"cudnnSeverity_t", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"CUDNN_SEV_FATAL", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"CUDNN_SEV_ERROR", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"CUDNN_SEV_WARNING", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"CUDNN_SEV_INFO", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"CUDNN_SEV_ERROR_EN", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"CUDNN_SEV_WARNING_EN", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"CUDNN_SEV_INFO_EN", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"cudnnDebug_t", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionFwdPreference_t", {CUDNN_20, CUDNN_765, CUDNN_801}}, + {"CUDNN_CONVOLUTION_FWD_NO_WORKSPACE", {CUDNN_20, CUDNN_765, CUDNN_801}}, + {"CUDNN_CONVOLUTION_FWD_PREFER_FASTEST", {CUDNN_20, CUDNN_765, CUDNN_801}}, + {"CUDNN_CONVOLUTION_FWD_SPECIFY_WORKSPACE_LIMIT", {CUDNN_20, CUDNN_765, CUDNN_801}}, + {"cudnnConvolutionBwdDataAlgoPerf_t", {CUDNN_30, CUDNN_900, CUDA_0 }}, + {"cudnnFusedOpsConstParamStruct", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"cudnnFusedOpsConstParamPack_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"cudnnFusedOpsVariantParamStruct", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"cudnnFusedOpsVariantParamPack_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"cudnnFusedOpsPlanStruct", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"cudnnFusedOpsPlan_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"cudnnFusedOps_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"CUDNN_FUSED_SCALE_BIAS_ACTIVATION_CONV_BNSTATS", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_FUSED_SCALE_BIAS_ACTIVATION_WGRAD", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_FUSED_BN_FINALIZE_STATISTICS_TRAINING", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_FUSED_BN_FINALIZE_STATISTICS_INFERENCE", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_FUSED_CONV_SCALE_BIAS_ADD_ACTIVATION", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_FUSED_SCALE_BIAS_ADD_ACTIVATION_GEN_BITMASK", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_FUSED_DACTIVATION_FORK_DBATCHNORM", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"cudnnFusedOpsConstParamLabel_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"CUDNN_PARAM_XDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_XDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_MODE", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_EQSCALEBIAS_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_EQSCALE_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_EQBIAS_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_ACTIVATION_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_CONV_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_WDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_WDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_DWDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_DWDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_YDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_YDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_DYDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_DYDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_YSTATS_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_YSUM_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_YSQSUM_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_SCALEBIAS_MEANVAR_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_SCALE_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_BIAS_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_SAVED_MEAN_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_SAVED_INVSTD_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_RUNNING_MEAN_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_RUNNING_VAR_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_ZDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_ZDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_Z_EQSCALEBIAS_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_Z_EQSCALE_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_Z_EQBIAS_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_ACTIVATION_BITMASK_DESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_ACTIVATION_BITMASK_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_DXDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_DXDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_DZDESC", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_DZDATA_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_DSCALE_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PARAM_BN_DBIAS_PLACEHOLDER", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"cudnnFusedOpsPointerPlaceHolder_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"CUDNN_PTR_NULL", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_ELEM_ALIGNED", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_16B_ALIGNED", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"cudnnFusedOpsVariantParamLabel_t", {CUDNN_760, CUDNN_900, CUDA_0 }}, + {"CUDNN_PTR_XDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_EQSCALE", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_EQBIAS", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_WDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_DWDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_YDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_DYDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_YSUM", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_YSQSUM", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_WORKSPACE", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_SCALE", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_BIAS", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_SAVED_MEAN", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_SAVED_INVSTD", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_RUNNING_MEAN", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_RUNNING_VAR", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_ZDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_Z_EQSCALE", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_Z_EQBIAS", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_ACTIVATION_BITMASK", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_DXDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_DZDATA", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_DSCALE", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_PTR_BN_DBIAS", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_SCALAR_SIZE_T_WORKSPACE_SIZE_IN_BYTES", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_SCALAR_INT64_T_BN_ACCUMULATION_COUNT", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_SCALAR_DOUBLE_BN_EXP_AVG_FACTOR", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_SCALAR_DOUBLE_BN_EPSILON", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"cudnnSeqDataAxis_t", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_SEQDATA_TIME_DIM", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_SEQDATA_BATCH_DIM", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_SEQDATA_BEAM_DIM", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_SEQDATA_VECT_DIM", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_SEQDATA_DIM_COUNT", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionBwdFilterPreference_t", {CUDNN_30, CUDNN_765, CUDNN_801}}, + {"CUDNN_CONVOLUTION_BWD_FILTER_NO_WORKSPACE", {CUDNN_30, CUDNN_765, CUDNN_801}}, + {"CUDNN_CONVOLUTION_BWD_FILTER_PREFER_FASTEST", {CUDNN_30, CUDNN_765, CUDNN_801}}, + {"CUDNN_CONVOLUTION_BWD_FILTER_SPECIFY_WORKSPACE_LIMIT", {CUDNN_30, CUDNN_765, CUDNN_801}}, + {"cudnnSeqDataStruct", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"cudnnSeqDataDescriptor_t", {CUDNN_750, CUDNN_900, CUDA_0 }}, + {"cudnnAttnQueryMap_t", {CUDNN_750, CUDA_0, CUDNN_900}}, + {"CUDNN_ATTN_QUERYMAP_ALL_TO_ONE", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTN_QUERYMAP_ONE_TO_ONE", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTN_DISABLE_PROJ_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTN_ENABLE_PROJ_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, + {"cudnnAttnStruct", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"cudnnAttnDescriptor_t", {CUDNN_750, CUDNN_900, CUDA_0 }}, + {"cudnnMultiHeadAttnWeightKind_t", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_MH_ATTN_Q_WEIGHTS", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_MH_ATTN_K_WEIGHTS", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_MH_ATTN_V_WEIGHTS", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_MH_ATTN_O_WEIGHTS", {CUDNN_750, CUDA_0, CUDA_0 }}, + {"CUDNN_MH_ATTN_Q_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, + {"CUDNN_MH_ATTN_K_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, + {"CUDNN_MH_ATTN_V_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, + {"CUDNN_MH_ATTN_O_BIASES", {CUDNN_763, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTN_WKIND_COUNT", {CUDNN_763, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionBwdDataPreference_t", {CUDNN_30, CUDNN_765, CUDNN_801}}, + {"CUDNN_CONVOLUTION_BWD_DATA_NO_WORKSPACE", {CUDNN_30, CUDNN_765, CUDNN_801}}, + {"CUDNN_CONVOLUTION_BWD_DATA_PREFER_FASTEST", {CUDNN_30, CUDNN_765, CUDNN_801}}, + {"CUDNN_CONVOLUTION_BWD_DATA_SPECIFY_WORKSPACE_LIMIT", {CUDNN_30, CUDNN_765, CUDNN_801}}, + {"cudnnLossNormalizationMode_t", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_LOSS_NORMALIZATION_NONE", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"CUDNN_LOSS_NORMALIZATION_SOFTMAX", {CUDNN_760, CUDA_0, CUDA_0 }}, + {"cudnnCTCLossStruct", {CUDNN_705, CUDA_0, CUDA_0 }}, + {"cudnnCallback_t", {CUDNN_713, CUDA_0, CUDA_0 }}, + {"cudnnBnFinalizeStatsMode_t", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_BN_FINALIZE_STATISTICS_TRAINING", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"CUDNN_BN_FINALIZE_STATISTICS_INFERENCE", {CUDNN_810, CUDA_0, CUDA_0 }}, + {"cudnnAlgorithmUnionStruct", {CUDNN_820, CUDA_0, CUDNN_900}}, + {"cudnnDebugStruct", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionBwdFilterAlgoPerfStruct", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionFwdAlgoPerfStruct", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"cudnnConvolutionBwdDataAlgoPerfStruct", {CUDNN_820, CUDNN_900, CUDA_0 }}, + {"CUDNN_ATTR_ENGINE_BEHAVIOR_NOTE", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_MATH_PREC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_MEAN_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_INVSTD_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_BN_SCALE_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_X_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_DY_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_DBN_SCALE_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_DBN_BIAS_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_DY_SCALE_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_X_SCALE_DESC", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_BIAS", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_BEHAVIOR_NOTE", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"cudnnBackendBehaviorNote_t", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_BEHAVIOR_NOTE_RUNTIME_COMPILATION", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_BEHAVIOR_NOTE_TYPE_COUNT", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_BN_BWD_WEIGHTS_DESCRIPTOR", {CUDNN_820, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_BOOLEAN", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_ADD_SQUARE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_DIV", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_MOD", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_POW", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_SUB", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_ABS", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_CEIL", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_COS", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_EXP", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_FLOOR", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_LOG", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_NEG", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_RSQRT", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_SIN", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_TAN", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_ERF", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_IDENTITY", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_GELU_APPROX_TANH_FWD", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_GELU_APPROX_TANH_BWD", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_CMP_EQ", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_CMP_NEQ", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_CMP_GT", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_CMP_GE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_CMP_LT", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_CMP_LE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_LOGICAL_AND", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_LOGICAL_OR", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_LOGICAL_NOT", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_GEN_INDEX", {CUDNN_840, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_BINARY_SELECT", {CUDNN_840, CUDA_0, CUDA_0 }}, + {"cudnnFractionStruct", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"cudnnFraction_t", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"cudnnResampleMode_t", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_RESAMPLE_NEAREST", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_RESAMPLE_BILINEAR", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_RESAMPLE_AVGPOOL", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_RESAMPLE_MAXPOOL", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"cudnnSignalMode_t", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_SIGNAL_SET", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_SIGNAL_WAIT", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_POINTWISE_AXIS", {CUDNN_840, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_EXECUTION_PLAN_JSON_REPRESENTATION", {CUDNN_840, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_POINTWISE_TDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_REORDERING_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RESAMPLE_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RESAMPLE_COMP_TYPE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RESAMPLE_SPATIAL_DIMS", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RESAMPLE_POST_PADDINGS", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RESAMPLE_PRE_PADDINGS", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RESAMPLE_STRIDES", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RESAMPLE_WINDOW_DIMS", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RESAMPLE_NAN_PROPAGATION", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RESAMPLE_PADDING_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_XDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_YDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_IDXDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_ALPHA", {CUDNN_830, CUDNN_900, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_BETA", {CUDNN_830, CUDNN_900, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_FWD_DESC", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_DXDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_DYDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_IDXDESC", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_ALPHA", {CUDNN_830, CUDNN_900, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_BETA", {CUDNN_830, CUDNN_900, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_DESC", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONCAT_AXIS", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONCAT_INPUT_DESCS", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONCAT_INPLACE_INDEX", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_CONCAT_OUTPUT_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_SIGNAL_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_SIGNAL_FLAGDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_SIGNAL_VALUE", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_SIGNAL_XDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_SIGNAL_YDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_PHASE", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_XDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_MEAN_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_INV_VARIANCE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_SCALE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_BIAS_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_EPSILON_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_EXP_AVG_FACTOR_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_INPUT_RUNNING_MEAN_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_INPUT_RUNNING_VAR_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_OUTPUT_RUNNING_MEAN_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_OUTPUT_RUNNING_VAR_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_YDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_FWD_PEER_STAT_DESCS", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_XDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_MEAN_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_INV_VARIANCE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_DYDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_SCALE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_EPSILON_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_DSCALE_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_DBIAS_DESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_DXDESC", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_NORM_BWD_PEER_STAT_DESCS", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_TENSOR_REORDERING_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_RESAMPLE_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_PADDING_MODE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_INT32", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_CHAR", {CUDNN_840, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_SIGNAL_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_FRACTION", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_NORM_MODE", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_NORM_FWD_PHASE", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_RESAMPLE_DESCRIPTOR", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_CONCAT_DESCRIPTOR", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_WINOGRAD_TILE_4x4", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_WINOGRAD_TILE_6x6", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_WINOGRAD_TILE_13x13", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_BEHAVIOR_NOTE_REQUIRES_FILTER_INT8x32_REORDER", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_BEHAVIOR_NOTE_REQUIRES_BIAS_INT8x32_REORDER", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_WORKSPACE", {CUDNN_840, CUDA_0, CUDA_0 }}, + {"CUDNN_HEUR_MODE_FALLBACK", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_HEUR_MODE_A", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"cudnnBackendTensorReordering_t", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_TENSOR_REORDERING_NONE", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_TENSOR_REORDERING_INT8x32", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"cudnnPaddingMode_t", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_ZERO_PAD", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_NEG_INF_PAD", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"CUDNN_EDGE_VAL_PAD", {CUDNN_830, CUDA_0, CUDA_0 }}, + {"cudnnBackendNormMode_t", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_LAYER_NORM", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_INSTANCE_NORM", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_BATCH_NORM", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_GROUP_NORM", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"cudnnBackendNormFwdPhase_t", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_NORM_FWD_INFERENCE", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_NORM_FWD_TRAINING", {CUDNN_850, CUDA_0, CUDA_0 }}, + {"CUDNN_RESAMPLE_AVGPOOL_INCLUDE_PADDING", {CUDNN_860, CUDA_0, CUDA_0 }}, + {"CUDNN_RESAMPLE_AVGPOOL_EXCLUDE_PADDING", {CUDNN_860, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_TILE_CGA", {CUDNN_860, CUDNN_900, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_TILE_CGA_M", {CUDNN_860, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_TILE_CGA_N", {CUDNN_860, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_FP8_E4M3", {CUDNN_860, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_FP8_E5M2", {CUDNN_860, CUDA_0, CUDA_0 }}, + {"CUDNN_DATA_FAST_FLOAT_FOR_FP8", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"cudnnRngDistribution_t", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_RNG_DISTRIBUTION_BERNOULLI", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_RNG_DISTRIBUTION_UNIFORM", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_RNG_DISTRIBUTION_NORMAL", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_MATMUL_GEMM_M_OVERRIDE_DESC", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_MATMUL_GEMM_N_OVERRIDE_DESC", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_MATMUL_GEMM_K_OVERRIDE_DESC", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_XDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESAMPLE_BWD_YDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESHAPE_XDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RESHAPE_YDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RNG_DISTRIBUTION", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RNG_NORMAL_DIST_MEAN", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RNG_NORMAL_DIST_STANDARD_DEVIATION", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RNG_UNIFORM_DIST_MAXIMUM", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RNG_UNIFORM_DIST_MINIMUM", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_RNG_BERNOULLI_DIST_PROBABILITY", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RNG_YDESC", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RNG_SEED", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RNG_DESC", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_TYPE_RNG_DISTRIBUTION", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_RESHAPE_DESCRIPTOR", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_RNG_DESCRIPTOR", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_RNG_DESCRIPTOR", {CUDNN_870, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_RNG_OFFSET_DESC", {CUDNN_880, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_BLOCK_SIZE", {CUDNN_880, CUDA_0, CUDA_0 }}, + {"CUDNN_TENSOR_REORDERING_F16x16", {CUDNN_880, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_RECIPROCAL", {CUDNN_890, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_TENSOR_RAGGED_OFFSET_DESC", {CUDNN_890, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_MATMUL_PADDING_VALUE", {CUDNN_890, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_OCCUPANCY", {CUDNN_890, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_ARRAY_SIZE_PER_THREAD", {CUDNN_890, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_NUM_C_PER_BLOCK", {CUDNN_890, CUDNN_900, CUDA_0 }}, + {"CUDNN_ATTR_ENGINEHEUR_SM_COUNT_TARGET", {CUDNN_895, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINE_SM_COUNT_TARGET", {CUDNN_895, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_SPLIT_COLS", {CUDNN_895, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_TILE_ROWS", {CUDNN_895, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_TILE_COLS", {CUDNN_895, CUDA_0, CUDA_0 }}, + {"CUDNN_KNOB_TYPE_LOAD_SIZE", {CUDNN_895, CUDA_0, CUDA_0 }}, + {"CUDNN_RMS_NORM", {CUDNN_896, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_SUBLIBRARY_VERSION_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_SERIALIZATION_VERSION_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_DEPRECATED", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM_NULL_POINTER", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM_MISALIGNED_POINTER", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM_NOT_FINALIZED", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM_OUT_OF_BOUND", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM_SIZE_INSUFFICIENT", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM_STREAM_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM_SHAPE_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM_DUPLICATED_ENTRIES", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_BAD_PARAM_ATTRIBUTE_TYPE", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_GRAPH_PATTERN", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_SHAPE", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_DATA_TYPE", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_LAYOUT", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_INCOMPATIBLE_CUDA_DRIVER", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_INCOMPATIBLE_CUDART", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_ARCH_MISMATCH", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_RUNTIME_PREREQUISITE_MISSING", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_SUBLIBRARY_UNAVAILABLE", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_SHARED_MEMORY_INSUFFICIENT", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_PADDING", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_NOT_SUPPORTED_BAD_LAUNCH_PARAM", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_INTERNAL_ERROR_COMPILATION_FAILED", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_INTERNAL_ERROR_UNEXPECTED_VALUE", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_INTERNAL_ERROR_HOST_ALLOCATION_FAILED", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_INTERNAL_ERROR_DEVICE_ALLOCATION_FAILED", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_INTERNAL_ERROR_BAD_LAUNCH_PARAM", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_INTERNAL_ERROR_TEXTURE_CREATION_FAILED", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_EXECUTION_FAILED_CUDA_DRIVER", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_EXECUTION_FAILED_CUBLAS", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_EXECUTION_FAILED_CUDART", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_EXECUTION_FAILED_CURAND", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_FULL_ERROR_CODE", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_CATEGORY", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_SPECIFIC_ERROR", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_POINTWISE_ATAN2", {CUDNN_910, CUDA_0, CUDA_0 }}, + {"CUDNN_NUMERICAL_NOTE_STRICT_NAN_PROP", {CUDNN_910, CUDA_0, CUDA_0 }}, + {"CUDNN_STATUS_SUBLIBRARY_LOADING_FAILED", {CUDNN_920, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINECFG_WORKSPACE_SIZE", {CUDNN_920, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_ENGINECFG_SHARED_MEMORY_USED", {CUDNN_920, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_EXECUTION_PLAN_KERNEL_CACHE", {CUDNN_940, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATIONGRAPH_IS_DYNAMIC_SHAPE_ENABLED", {CUDNN_940, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_PAGED_CACHE_LOAD_CONTAINER_DESC", {CUDNN_940, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_PAGED_CACHE_LOAD_YDESC", {CUDNN_940, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_PAGED_CACHE_LOAD_SEQUENCE_DESC", {CUDNN_940, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_OPERATION_PAGED_CACHE_LOAD_PAGE_TABLE_DESC", {CUDNN_940, CUDA_0, CUDA_0 }}, + {"CUDNN_ATTR_KERNEL_CACHE_IS_ENGINECFG_KERNEL_CACHED", {CUDNN_940, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_KERNEL_CACHE_DESCRIPTOR", {CUDNN_940, CUDA_0, CUDA_0 }}, + {"CUDNN_BACKEND_OPERATION_PAGED_CACHE_LOAD_DESCRIPTOR", {CUDNN_940, CUDA_0, CUDA_0 }}, + {"cudnnCTCGradMode_t", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_CTC_ZERO_OOB_GRADIENTS", {CUDNN_900, CUDA_0, CUDA_0 }}, + {"CUDNN_CTC_SKIP_OOB_GRADIENTS", {CUDNN_900, CUDA_0, CUDA_0 }}, }; const std::map HIP_DNN_TYPE_NAME_VER_MAP { - {"miopenStatus_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenStatusSuccess", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenStatusNotInitialized", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenStatusAllocFailed", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenStatusBadParm", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenStatusInternalError", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenStatusInvalidValue", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenStatusUnsupportedOp", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenStatusVersionMismatch", {HIP_5040, HIP_0, HIP_0 }}, - {"miopenConvolutionMode_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenConvolution", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenTensorLayout_t", {HIP_5030, HIP_0, HIP_0 }}, - {"miopenTensorNCHW", {HIP_5030, HIP_0, HIP_0 }}, - {"miopenTensorNHWC", {HIP_5030, HIP_0, HIP_0 }}, - {"miopenDataType_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenFloat", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenDouble", {HIP_4050, HIP_0, HIP_0 }}, - {"miopenHalf", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenInt8", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenInt32", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenInt8x4", {HIP_2030, HIP_0, HIP_0 }}, - {"miopenBFloat16", {HIP_2060, HIP_0, HIP_0 }}, - {"miopenInt64", {HIP_6020, HIP_0, HIP_0 }}, - {"miopenConvFwdAlgorithm_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenConvolutionFwdAlgoImplicitGEMM", {HIP_2060, HIP_0, HIP_0 }}, - {"miopenConvolutionFwdAlgoGEMM", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenConvolutionFwdAlgoDirect", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenConvolutionFwdAlgoFFT", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenConvolutionFwdAlgoWinograd", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenCTCLossAlgo_t", {HIP_2060, HIP_0, HIP_0 }}, - {"MIOPEN_CTC_LOSS_ALGO_DETERMINISTIC", {HIP_2060, HIP_0, HIP_0 }}, - {"miopenLRNMode_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenLRNCrossChannel", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNInputMode_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNlinear", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNskip", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNDirectionMode_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNunidirection", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNbidirection", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenNanPropagation_t", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_NOT_PROPAGATE_NAN", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_PROPAGATE_NAN", {HIP_3090, HIP_0, HIP_0 }}, - {"miopenConvBwdDataAlgorithm_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenConvolutionBwdDataAlgoGEMM", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenConvolutionBwdDataAlgoDirect", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenConvolutionBwdDataAlgoFFT", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenConvolutionBwdDataAlgoWinograd", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNAlgo_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNdefault", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNMode_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNRELU", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNTANH", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenLSTM", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenGRU", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNBiasMode_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNNoBias", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenRNNwithBias", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenTensorOp_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenTensorOpAdd", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenTensorOpMul", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenTensorOpMin", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenTensorOpMax", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenReduceTensorOp_t", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_ADD", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_MUL", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_MIN", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_MAX", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_AMAX", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_AVG", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_NORM1", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_NORM2", {HIP_3090, HIP_0, HIP_0 }}, - {"miopenReduceTensorIndices_t", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_NO_INDICES", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_REDUCE_TENSOR_FLATTENED_INDICES", {HIP_3090, HIP_0, HIP_0 }}, - {"miopenIndicesType_t", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_32BIT_INDICES", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_64BIT_INDICES", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_16BIT_INDICES", {HIP_3090, HIP_0, HIP_0 }}, - {"MIOPEN_8BIT_INDICES", {HIP_3090, HIP_0, HIP_0 }}, - {"miopenSoftmaxAlgorithm_t", {HIP_2060, HIP_0, HIP_0 }}, - {"MIOPEN_SOFTMAX_FAST", {HIP_2060, HIP_0, HIP_0 }}, - {"MIOPEN_SOFTMAX_ACCURATE", {HIP_2060, HIP_0, HIP_0 }}, - {"MIOPEN_SOFTMAX_LOG", {HIP_2060, HIP_0, HIP_0 }}, - {"miopenSoftmaxMode_t", {HIP_2060, HIP_0, HIP_0 }}, - {"MIOPEN_SOFTMAX_MODE_INSTANCE", {HIP_2060, HIP_0, HIP_0 }}, - {"MIOPEN_SOFTMAX_MODE_CHANNEL", {HIP_2060, HIP_0, HIP_0 }}, - {"miopenPoolingMode_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenPoolingMax", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenActivationMode_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenActivationRELU", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenActivationTANH", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenActivationCLIPPEDRELU", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenActivationELU", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenActivationPASTHRU", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenBatchNormMode_t", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenBNPerActivation", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenBNSpatial", {HIP_2010, HIP_0, HIP_0 }}, - {"miopenPointwiseMode_t", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_ADD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_MUL", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_MIN", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_MAX", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_SQRT", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_ADD_SQUARE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_DIV", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_MOD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_POW", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_SUB", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_ABS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_CEIL", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_COS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_EXP", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_FLOOR", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_LOG", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_NEG", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_RSQRT", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_SIN", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_TAN", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_ERF", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_IDENTITY", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_RECIPROCAL", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_RELU_FWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_TANH_FWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_SIGMOID_FWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_ELU_FWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_GELU_FWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_SOFTPLUS_FWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_SWISH_FWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_GELU_APPROX_TANH_FWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_RELU_BWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_TANH_BWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_SIGMOID_BWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_ELU_BWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_GELU_BWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_SOFTPLUS_BWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_SWISH_BWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_GELU_APPROX_TANH_BWD", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_CMP_EQ", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_CMP_NEQ", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_CMP_GT", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_CMP_GE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_CMP_LT", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_CMP_LE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_LOGICAL_AND", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_LOGICAL_OR", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_LOGICAL_NOT", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_GEN_INDEX", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_POINTWISE_BINARY_SELECT", {HIP_6020, HIP_0, HIP_0 }}, - {"miopenBackendAttributeName_t", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_MATH_PREC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_NAN_PROPAGATION", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_RELU_LOWER_CLIP", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_RELU_UPPER_CLIP", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_RELU_LOWER_CLIP_SLOPE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_ELU_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_SOFTPLUS_BETA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_SWISH_BETA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_POINTWISE_AXIS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_CONVOLUTION_COMP_TYPE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_CONVOLUTION_CONV_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_CONVOLUTION_DILATIONS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_CONVOLUTION_FILTER_STRIDES", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_CONVOLUTION_POST_PADDINGS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_CONVOLUTION_PRE_PADDINGS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_CONVOLUTION_SPATIAL_DIMS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINEHEUR_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINEHEUR_OPERATION_GRAPH", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINEHEUR_RESULTS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINEHEUR_SM_COUNT_TARGET", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINECFG_ENGINE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINECFG_INTERMEDIATE_INFO", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINECFG_KNOB_CHOICES", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_EXECUTION_PLAN_HANDLE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_EXECUTION_PLAN_ENGINE_CONFIG", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_EXECUTION_PLAN_WORKSPACE_SIZE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_EXECUTION_PLAN_COMPUTED_INTERMEDIATE_UIDS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_EXECUTION_PLAN_RUN_ONLY_INTERMEDIATE_UIDS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_EXECUTION_PLAN_JSON_REPRESENTATION", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_INTERMEDIATE_INFO_UNIQUE_ID", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_INTERMEDIATE_INFO_SIZE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_INTERMEDIATE_INFO_DEPENDENT_DATA_UIDS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_INTERMEDIATE_INFO_DEPENDENT_ATTRIBUTES", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_KNOB_CHOICE_KNOB_TYPE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_KNOB_CHOICE_KNOB_VALUE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_BETA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_CONV_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_W", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_X", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_Y", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_BETA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_CONV_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_W", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_DX", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_DY", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_BETA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_CONV_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_DW", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_X", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_DY", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_POINTWISE_PW_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_POINTWISE_XDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_POINTWISE_BDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_POINTWISE_YDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_POINTWISE_ALPHA1", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_POINTWISE_ALPHA2", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_POINTWISE_DXDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_POINTWISE_DYDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_POINTWISE_TDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_GENSTATS_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_GENSTATS_MATH_PREC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_GENSTATS_XDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_GENSTATS_SUMDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_GENSTATS_SQSUMDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_STATS_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_MATH_PREC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_Y_SUM_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_Y_SQ_SUM_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_BIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_PREV_RUNNING_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_PREV_RUNNING_VAR_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_UPDATED_RUNNING_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_UPDATED_RUNNING_VAR_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_SAVED_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_SAVED_INV_STD_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_EQ_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_EQ_BIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_ACCUM_COUNT_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_EPSILON_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_EXP_AVERATE_FACTOR_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATIONGRAPH_HANDLE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATIONGRAPH_OPS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATIONGRAPH_ENGINE_GLOBAL_COUNT", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_BYTE_ALIGNMENT", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_DATA_TYPE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_DIMENSIONS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_STRIDES", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_VECTOR_COUNT", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_VECTORIZED_DIMENSION", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_UNIQUE_ID", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_IS_VIRTUAL", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_IS_BY_VALUE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_REORDERING_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_TENSOR_RAGGED_OFFSET_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_VARIANT_PACK_UNIQUE_IDS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_VARIANT_PACK_DATA_POINTERS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_VARIANT_PACK_INTERMEDIATES", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_VARIANT_PACK_WORKSPACE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_LAYOUT_INFO_TENSOR_UID", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_LAYOUT_INFO_TYPES", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_KNOB_INFO_TYPE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_KNOB_INFO_MAXIMUM_VALUE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_KNOB_INFO_MINIMUM_VALUE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_KNOB_INFO_STRIDE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINE_OPERATION_GRAPH", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINE_GLOBAL_INDEX", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINE_KNOB_INFO", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINE_NUMERICAL_NOTE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINE_LAYOUT_INFO", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINE_BEHAVIOR_NOTE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_ENGINE_SM_COUNT_TARGET", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_MATMUL_COMP_TYPE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_MATMUL_PADDING_VALUE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_MATMUL_ADESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_MATMUL_BDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_MATMUL_CDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_MATMUL_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_MATMUL_GEMM_M_OVERRIDE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_MATMUL_GEMM_N_OVERRIDE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_MATMUL_GEMM_K_OVERRIDE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_REDUCTION_OPERATOR", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_REDUCTION_COMP_TYPE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_REDUCTION_XDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_REDUCTION_YDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_REDUCTION_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_MATH_PREC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_INVSTD_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_BN_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_X_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_DY_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_DBN_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_DBN_BIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_DY_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_X_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_BIAS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RESAMPLE_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RESAMPLE_COMP_TYPE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RESAMPLE_SPATIAL_DIMS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RESAMPLE_POST_PADDINGS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RESAMPLE_PRE_PADDINGS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RESAMPLE_STRIDES", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RESAMPLE_WINDOW_DIMS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RESAMPLE_NAN_PROPAGATION", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RESAMPLE_PADDING_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_XDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_YDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_IDXDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_BETA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_DXDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_DYDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_IDXDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_BETA", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_XDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_YDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONCAT_AXIS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONCAT_INPUT_DESCS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONCAT_INPLACE_INDEX", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_CONCAT_OUTPUT_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_SIGNAL_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_SIGNAL_FLAGDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_SIGNAL_VALUE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_SIGNAL_XDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_SIGNAL_YDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_PHASE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_XDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_INV_VARIANCE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_BIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_EPSILON_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_EXP_AVG_FACTOR_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_INPUT_RUNNING_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_INPUT_RUNNING_VAR_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_OUTPUT_RUNNING_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_OUTPUT_RUNNING_VAR_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_YDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_FWD_PEER_STAT_DESCS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_MODE", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_XDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_INV_VARIANCE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_DYDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_EPSILON_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_DSCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_DBIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_DXDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_NORM_BWD_PEER_STAT_DESCS", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESHAPE_XDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RESHAPE_YDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RNG_DISTRIBUTION", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RNG_NORMAL_DIST_MEAN", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RNG_NORMAL_DIST_STANDARD_DEVIATION", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RNG_UNIFORM_DIST_MAXIMUM", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RNG_UNIFORM_DIST_MINIMUM", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_RNG_BERNOULLI_DIST_PROBABILITY", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RNG_YDESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RNG_SEED", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RNG_DESC", {HIP_6020, HIP_0, HIP_0 }}, - {"MIOPEN_ATTR_OPERATION_RNG_OFFSET_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"miopenStatus_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenStatusSuccess", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenStatusNotInitialized", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenStatusAllocFailed", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenStatusBadParm", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenStatusInternalError", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenStatusInvalidValue", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenStatusUnsupportedOp", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenStatusVersionMismatch", {HIP_5040, HIP_0, HIP_0 }}, + {"miopenConvolutionMode_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenConvolution", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenTensorLayout_t", {HIP_5030, HIP_0, HIP_0 }}, + {"miopenTensorNCHW", {HIP_5030, HIP_0, HIP_0 }}, + {"miopenTensorNHWC", {HIP_5030, HIP_0, HIP_0 }}, + {"miopenDataType_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenFloat", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenDouble", {HIP_4050, HIP_0, HIP_0 }}, + {"miopenHalf", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenInt8", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenInt32", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenInt8x4", {HIP_2030, HIP_0, HIP_0 }}, + {"miopenBFloat16", {HIP_2060, HIP_0, HIP_0 }}, + {"miopenInt64", {HIP_6020, HIP_0, HIP_0 }}, + {"miopenConvFwdAlgorithm_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenConvolutionFwdAlgoImplicitGEMM", {HIP_2060, HIP_0, HIP_0 }}, + {"miopenConvolutionFwdAlgoGEMM", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenConvolutionFwdAlgoDirect", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenConvolutionFwdAlgoFFT", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenConvolutionFwdAlgoWinograd", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenCTCLossAlgo_t", {HIP_2060, HIP_0, HIP_0 }}, + {"MIOPEN_CTC_LOSS_ALGO_DETERMINISTIC", {HIP_2060, HIP_0, HIP_0 }}, + {"miopenLRNMode_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenLRNCrossChannel", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNInputMode_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNlinear", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNskip", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNDirectionMode_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNunidirection", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNbidirection", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenNanPropagation_t", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_NOT_PROPAGATE_NAN", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_PROPAGATE_NAN", {HIP_3090, HIP_0, HIP_0 }}, + {"miopenConvBwdDataAlgorithm_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenConvolutionBwdDataAlgoGEMM", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenConvolutionBwdDataAlgoDirect", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenConvolutionBwdDataAlgoFFT", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenConvolutionBwdDataAlgoWinograd", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNAlgo_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNdefault", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNMode_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNRELU", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNTANH", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenLSTM", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenGRU", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNBiasMode_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNNoBias", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenRNNwithBias", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenTensorOp_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenTensorOpAdd", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenTensorOpMul", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenTensorOpMin", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenTensorOpMax", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenReduceTensorOp_t", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_ADD", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_MUL", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_MIN", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_MAX", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_AMAX", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_AVG", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_NORM1", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_NORM2", {HIP_3090, HIP_0, HIP_0 }}, + {"miopenReduceTensorIndices_t", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_NO_INDICES", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_REDUCE_TENSOR_FLATTENED_INDICES", {HIP_3090, HIP_0, HIP_0 }}, + {"miopenIndicesType_t", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_32BIT_INDICES", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_64BIT_INDICES", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_16BIT_INDICES", {HIP_3090, HIP_0, HIP_0 }}, + {"MIOPEN_8BIT_INDICES", {HIP_3090, HIP_0, HIP_0 }}, + {"miopenSoftmaxAlgorithm_t", {HIP_2060, HIP_0, HIP_0 }}, + {"MIOPEN_SOFTMAX_FAST", {HIP_2060, HIP_0, HIP_0 }}, + {"MIOPEN_SOFTMAX_ACCURATE", {HIP_2060, HIP_0, HIP_0 }}, + {"MIOPEN_SOFTMAX_LOG", {HIP_2060, HIP_0, HIP_0 }}, + {"miopenSoftmaxMode_t", {HIP_2060, HIP_0, HIP_0 }}, + {"MIOPEN_SOFTMAX_MODE_INSTANCE", {HIP_2060, HIP_0, HIP_0 }}, + {"MIOPEN_SOFTMAX_MODE_CHANNEL", {HIP_2060, HIP_0, HIP_0 }}, + {"miopenPoolingMode_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenPoolingMax", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenActivationMode_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenActivationRELU", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenActivationTANH", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenActivationCLIPPEDRELU", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenActivationELU", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenActivationPASTHRU", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenBatchNormMode_t", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenBNPerActivation", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenBNSpatial", {HIP_2010, HIP_0, HIP_0 }}, + {"miopenPointwiseMode_t", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_ADD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_MUL", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_MIN", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_MAX", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_SQRT", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_ADD_SQUARE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_DIV", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_MOD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_POW", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_SUB", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_ABS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_CEIL", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_COS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_EXP", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_FLOOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_LOG", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_NEG", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_RSQRT", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_SIN", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_TAN", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_ERF", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_IDENTITY", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_RECIPROCAL", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_RELU_FWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_TANH_FWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_SIGMOID_FWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_ELU_FWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_GELU_FWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_SOFTPLUS_FWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_SWISH_FWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_GELU_APPROX_TANH_FWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_RELU_BWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_TANH_BWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_SIGMOID_BWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_ELU_BWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_GELU_BWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_SOFTPLUS_BWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_SWISH_BWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_GELU_APPROX_TANH_BWD", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_CMP_EQ", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_CMP_NEQ", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_CMP_GT", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_CMP_GE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_CMP_LT", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_CMP_LE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_LOGICAL_AND", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_LOGICAL_OR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_LOGICAL_NOT", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_GEN_INDEX", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_POINTWISE_BINARY_SELECT", {HIP_6020, HIP_0, HIP_0 }}, + {"miopenBackendAttributeName_t", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_MATH_PREC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_NAN_PROPAGATION", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_RELU_LOWER_CLIP", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_RELU_UPPER_CLIP", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_RELU_LOWER_CLIP_SLOPE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_ELU_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_SOFTPLUS_BETA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_SWISH_BETA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_POINTWISE_AXIS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_CONVOLUTION_COMP_TYPE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_CONVOLUTION_CONV_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_CONVOLUTION_DILATIONS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_CONVOLUTION_FILTER_STRIDES", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_CONVOLUTION_POST_PADDINGS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_CONVOLUTION_PRE_PADDINGS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_CONVOLUTION_SPATIAL_DIMS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINEHEUR_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINEHEUR_OPERATION_GRAPH", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINEHEUR_RESULTS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINEHEUR_SM_COUNT_TARGET", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINECFG_ENGINE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINECFG_INTERMEDIATE_INFO", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINECFG_KNOB_CHOICES", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_EXECUTION_PLAN_HANDLE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_EXECUTION_PLAN_ENGINE_CONFIG", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_EXECUTION_PLAN_WORKSPACE_SIZE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_EXECUTION_PLAN_COMPUTED_INTERMEDIATE_UIDS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_EXECUTION_PLAN_RUN_ONLY_INTERMEDIATE_UIDS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_EXECUTION_PLAN_JSON_REPRESENTATION", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_INTERMEDIATE_INFO_UNIQUE_ID", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_INTERMEDIATE_INFO_SIZE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_INTERMEDIATE_INFO_DEPENDENT_DATA_UIDS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_INTERMEDIATE_INFO_DEPENDENT_ATTRIBUTES", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_KNOB_CHOICE_KNOB_TYPE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_KNOB_CHOICE_KNOB_VALUE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_BETA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_CONV_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_W", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_X", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_FORWARD_Y", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_BETA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_CONV_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_W", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_DX", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_DY", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_BETA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_CONV_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_DW", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_X", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_DY", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_POINTWISE_PW_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_POINTWISE_XDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_POINTWISE_BDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_POINTWISE_YDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_POINTWISE_ALPHA1", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_POINTWISE_ALPHA2", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_POINTWISE_DXDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_POINTWISE_DYDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_POINTWISE_TDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_GENSTATS_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_GENSTATS_MATH_PREC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_GENSTATS_XDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_GENSTATS_SUMDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_GENSTATS_SQSUMDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_STATS_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_MATH_PREC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_Y_SUM_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_Y_SQ_SUM_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_BIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_PREV_RUNNING_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_PREV_RUNNING_VAR_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_UPDATED_RUNNING_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_UPDATED_RUNNING_VAR_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_SAVED_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_SAVED_INV_STD_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_EQ_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_EQ_BIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_ACCUM_COUNT_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_EPSILON_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_FINALIZE_EXP_AVERATE_FACTOR_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATIONGRAPH_HANDLE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATIONGRAPH_OPS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATIONGRAPH_ENGINE_GLOBAL_COUNT", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_BYTE_ALIGNMENT", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_DATA_TYPE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_DIMENSIONS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_STRIDES", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_VECTOR_COUNT", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_VECTORIZED_DIMENSION", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_UNIQUE_ID", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_IS_VIRTUAL", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_IS_BY_VALUE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_REORDERING_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_TENSOR_RAGGED_OFFSET_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_VARIANT_PACK_UNIQUE_IDS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_VARIANT_PACK_DATA_POINTERS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_VARIANT_PACK_INTERMEDIATES", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_VARIANT_PACK_WORKSPACE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_LAYOUT_INFO_TENSOR_UID", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_LAYOUT_INFO_TYPES", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_KNOB_INFO_TYPE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_KNOB_INFO_MAXIMUM_VALUE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_KNOB_INFO_MINIMUM_VALUE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_KNOB_INFO_STRIDE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINE_OPERATION_GRAPH", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINE_GLOBAL_INDEX", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINE_KNOB_INFO", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINE_NUMERICAL_NOTE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINE_LAYOUT_INFO", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINE_BEHAVIOR_NOTE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_ENGINE_SM_COUNT_TARGET", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_MATMUL_COMP_TYPE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_MATMUL_PADDING_VALUE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_MATMUL_ADESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_MATMUL_BDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_MATMUL_CDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_MATMUL_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_MATMUL_IRREGULARLY_STRIDED_BATCH_COUNT", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_MATMUL_GEMM_M_OVERRIDE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_MATMUL_GEMM_N_OVERRIDE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_MATMUL_GEMM_K_OVERRIDE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_REDUCTION_OPERATOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_REDUCTION_COMP_TYPE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_REDUCTION_XDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_REDUCTION_YDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_REDUCTION_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_MATH_PREC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_INVSTD_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_BN_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_X_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_DY_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_DBN_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_DBN_BIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_DY_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_X_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_BN_BWD_WEIGHTS_EQ_BIAS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RESAMPLE_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RESAMPLE_COMP_TYPE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RESAMPLE_SPATIAL_DIMS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RESAMPLE_POST_PADDINGS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RESAMPLE_PRE_PADDINGS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RESAMPLE_STRIDES", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RESAMPLE_WINDOW_DIMS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RESAMPLE_NAN_PROPAGATION", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RESAMPLE_PADDING_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_XDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_YDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_IDXDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_BETA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_FWD_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_DXDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_DYDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_IDXDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_ALPHA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_BETA", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_XDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESAMPLE_BWD_YDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONCAT_AXIS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONCAT_INPUT_DESCS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONCAT_INPLACE_INDEX", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_CONCAT_OUTPUT_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_SIGNAL_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_SIGNAL_FLAGDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_SIGNAL_VALUE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_SIGNAL_XDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_SIGNAL_YDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_PHASE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_XDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_INV_VARIANCE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_BIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_EPSILON_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_EXP_AVG_FACTOR_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_INPUT_RUNNING_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_INPUT_RUNNING_VAR_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_OUTPUT_RUNNING_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_OUTPUT_RUNNING_VAR_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_YDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_FWD_PEER_STAT_DESCS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_MODE", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_XDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_MEAN_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_INV_VARIANCE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_DYDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_SCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_EPSILON_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_DSCALE_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_DBIAS_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_DXDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_NORM_BWD_PEER_STAT_DESCS", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESHAPE_XDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RESHAPE_YDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RNG_DISTRIBUTION", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RNG_NORMAL_DIST_MEAN", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RNG_NORMAL_DIST_STANDARD_DEVIATION", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RNG_UNIFORM_DIST_MAXIMUM", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RNG_UNIFORM_DIST_MINIMUM", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_RNG_BERNOULLI_DIST_PROBABILITY", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RNG_YDESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RNG_SEED", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RNG_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_ATTR_OPERATION_RNG_OFFSET_DESC", {HIP_6020, HIP_0, HIP_0 }}, + {"miopenBackendDescriptorType_t", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_POINTWISE_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_CONVOLUTION_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_ENGINE_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_ENGINECFG_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_ENGINEHEUR_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_EXECUTION_PLAN_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_INTERMEDIATE_INFO_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_KNOB_CHOICE_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_KNOB_INFO_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_LAYOUT_INFO_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATIONGRAPH_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_VARIANT_PACK_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_TENSOR_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_MATMUL_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_MATMUL_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_REDUCTION_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_RESAMPLE_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_CONCAT_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_RNG_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, + {"MIOPEN_BACKEND_OPERATION_RNG_DESCRIPTOR", {HIP_6020, HIP_0, HIP_0 }}, };