From e9bc32cdbca180226082bd8558689962c1128b0b Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 2 Feb 2020 08:02:17 -0600 Subject: [PATCH 01/35] Improve tun (#198) * Remove the code duplication in tun_net_receive_tap and remove the unused filep field * Shouldn't return -EBUSY in tun_write. Let the caller wait until the write buffer free * Handle that write buffer is ready first correctly in tun_read * Remove the unused tun_ipv6multicast --- drivers/net/tun.c | 278 ++++++++++++++++++++-------------------------- 1 file changed, 123 insertions(+), 155 deletions(-) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 44f67bee01d..53869a59e7c 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -134,12 +134,13 @@ struct tun_device_s { bool bifup; /* true:ifup false:ifdown */ bool read_wait; + bool write_wait; WDOG_ID txpoll; /* TX poll timer */ struct work_s work; /* For deferring poll work to the work queue */ - FAR struct file *filep; FAR struct pollfd *poll_fds; sem_t waitsem; sem_t read_wait_sem; + sem_t write_wait_sem; size_t read_d_len; size_t write_d_len; @@ -170,7 +171,7 @@ static void tun_unlock(FAR struct tun_device_s *priv); /* Common TX logic */ -static int tun_fd_transmit(FAR struct tun_device_s *priv); +static void tun_fd_transmit(FAR struct tun_device_s *priv); static int tun_txpoll(FAR struct net_driver_s *dev); #ifdef CONFIG_NET_ETHERNET static int tun_txpoll_tap(FAR struct net_driver_s *dev); @@ -201,13 +202,11 @@ static int tun_txavail(FAR struct net_driver_s *dev); static int tun_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac); static int tun_rmmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac); #endif -#ifdef CONFIG_NET_ICMPv6 -static void tun_ipv6multicast(FAR struct tun_device_s *priv); -#endif -static int tun_dev_init(FAR struct tun_device_s *priv, FAR struct file *filep, +static int tun_dev_init(FAR struct tun_device_s *priv, + FAR struct file *filep, FAR const char *devfmt, bool tun); -static int tun_dev_uninit(FAR struct tun_device_s *priv); +static void tun_dev_uninit(FAR struct tun_device_s *priv); /* File interface */ @@ -291,6 +290,18 @@ static void tun_pollnotify(FAR struct tun_device_s *priv, { FAR struct pollfd *fds = priv->poll_fds; + if (priv->read_wait && (eventset & POLLIN)) + { + priv->read_wait = false; + nxsem_post(&priv->read_wait_sem); + } + + if (priv->write_wait && (eventset & POLLOUT)) + { + priv->write_wait = false; + nxsem_post(&priv->write_wait_sem); + } + if (fds == NULL) { return; @@ -316,7 +327,7 @@ static void tun_pollnotify(FAR struct tun_device_s *priv, * priv - Reference to the driver state structure * * Returned Value: - * OK on success; a negated errno on failure + * None * * Assumptions: * May or may not be called from an interrupt handler. In either case, @@ -325,23 +336,10 @@ static void tun_pollnotify(FAR struct tun_device_s *priv, * ****************************************************************************/ -static int tun_fd_transmit(FAR struct tun_device_s *priv) +static void tun_fd_transmit(FAR struct tun_device_s *priv) { NETDEV_TXPACKETS(&priv->dev); - - /* Verify that the hardware is ready to send another packet. If we get - * here, then we are committed to sending a packet; Higher level logic - * must have assured that there is no transmission in progress. - */ - - if (priv->read_wait) - { - priv->read_wait = false; - nxsem_post(&priv->read_wait_sem); - } - tun_pollnotify(priv, POLLIN); - return OK; } /**************************************************************************** @@ -452,8 +450,8 @@ static int tun_txpoll_tap(FAR struct net_driver_s *dev) } } - /* If zero is returned, the polling will continue until all connections have - * been examined. + /* If zero is returned, the polling will continue until all connections + * have been examined. */ return 0; @@ -589,33 +587,6 @@ static void tun_net_receive_tap(FAR struct tun_device_s *priv) arp_ipin(&priv->dev); ipv4_input(&priv->dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - /* Update the Ethernet header with the correct MAC address */ - -#ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(priv->dev.d_flags)) -#endif - { - arp_out(&priv->dev); - } -#ifdef CONFIG_NET_IPv6 - else - { - neighbor_out(&priv->dev); - } -#endif - - /* And send the packet */ - - priv->write_d_len = priv->dev.d_len; - tun_fd_transmit(priv); - } } else #endif @@ -628,31 +599,6 @@ static void tun_net_receive_tap(FAR struct tun_device_s *priv) /* Give the IPv6 packet to the network layer. */ ipv6_input(&priv->dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - /* Update the Ethernet header with the correct MAC address */ - -#ifdef CONFIG_NET_IPv4 - if (IFF_IS_IPv4(priv->dev.d_flags)) - { - arp_out(&priv->dev); - } - else -#endif -#ifdef CONFIG_NET_IPv6 - { - neighbor_out(&priv->dev); - } -#endif - - priv->write_d_len = priv->dev.d_len; - tun_fd_transmit(priv); - } } else #endif @@ -670,12 +616,41 @@ static void tun_net_receive_tap(FAR struct tun_device_s *priv) { priv->write_d_len = priv->dev.d_len; tun_fd_transmit(priv); + priv->dev.d_len = 0; } } else #endif { NETDEV_RXDROPPED(&priv->dev); + priv->dev.d_len = 0; + } + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + /* Update the Ethernet header with the correct MAC address */ + +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(priv->dev.d_flags)) +#endif + { + arp_out(&priv->dev); + } +#ifdef CONFIG_NET_IPv6 + else + { + neighbor_out(&priv->dev); + } +#endif + + /* And send the packet */ + + priv->write_d_len = priv->dev.d_len; + tun_fd_transmit(priv); } } #endif @@ -889,16 +864,6 @@ static int tun_ifup(FAR struct net_driver_s *dev) dev->d_ipv6addr[6], dev->d_ipv6addr[7]); #endif - /* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */ - - /* Instantiate the MAC address from priv->dev.d_mac.ether.ether_addr_octet */ - -#ifdef CONFIG_NET_ICMPv6 - /* Set up IPv6 multicast address filtering */ - - tun_ipv6multicast(priv); -#endif - /* Set and activate a timer process */ wd_start(priv->txpoll, TUN_WDDELAY, tun_poll_expiry, @@ -1113,7 +1078,8 @@ static void tun_ipv6multicast(FAR struct tun_device_s *priv) * ****************************************************************************/ -static int tun_dev_init(FAR struct tun_device_s *priv, FAR struct file *filep, +static int tun_dev_init(FAR struct tun_device_s *priv, + FAR struct file *filep, FAR const char *devfmt, bool tun) { int ret; @@ -1134,16 +1100,18 @@ static int tun_dev_init(FAR struct tun_device_s *priv, FAR struct file *filep, nxsem_init(&priv->waitsem, 0, 1); nxsem_init(&priv->read_wait_sem, 0, 0); + nxsem_init(&priv->write_wait_sem, 0, 0); /* The wait semaphore is used for signaling and, hence, should not have * priority inheritance enabled. */ nxsem_setprotocol(&priv->read_wait_sem, SEM_PRIO_NONE); + nxsem_setprotocol(&priv->write_wait_sem, SEM_PRIO_NONE); /* Create a watchdog for timing polling for and timing of transmissions */ - priv->txpoll = wd_create(); /* Create periodic poll timer */ + priv->txpoll = wd_create(); /* Create periodic poll timer */ /* Assign d_ifname if specified. */ @@ -1159,12 +1127,11 @@ static int tun_dev_init(FAR struct tun_device_s *priv, FAR struct file *filep, { nxsem_destroy(&priv->waitsem); nxsem_destroy(&priv->read_wait_sem); + nxsem_destroy(&priv->write_wait_sem); return ret; } - priv->filep = filep; /* Set link to file */ - filep->f_priv = priv; /* Set link to TUN device */ - + filep->f_priv = priv; /* Set link to TUN device */ return ret; } @@ -1172,7 +1139,7 @@ static int tun_dev_init(FAR struct tun_device_s *priv, FAR struct file *filep, * Name: tun_dev_uninit ****************************************************************************/ -static int tun_dev_uninit(FAR struct tun_device_s *priv) +static void tun_dev_uninit(FAR struct tun_device_s *priv) { /* Put the interface in the down state */ @@ -1184,8 +1151,7 @@ static int tun_dev_uninit(FAR struct tun_device_s *priv) nxsem_destroy(&priv->waitsem); nxsem_destroy(&priv->read_wait_sem); - - return OK; + nxsem_destroy(&priv->write_wait_sem); } /**************************************************************************** @@ -1195,7 +1161,6 @@ static int tun_dev_uninit(FAR struct tun_device_s *priv) static int tun_open(FAR struct file *filep) { filep->f_priv = 0; - return OK; } @@ -1222,7 +1187,6 @@ static int tun_close(FAR struct file *filep) tun_dev_uninit(priv); tundev_unlock(tun); - return OK; } @@ -1236,40 +1200,47 @@ static ssize_t tun_write(FAR struct file *filep, FAR const char *buffer, FAR struct tun_device_s *priv = filep->f_priv; ssize_t ret; - if (priv == NULL) + if (priv == NULL || buflen > CONFIG_NET_TUN_PKTSIZE) { return -EINVAL; } tun_lock(priv); - if (priv->write_d_len > 0) + for (; ; ) { - tun_unlock(priv); - return -EBUSY; - } + /* Check if there are free space to write */ - net_lock(); + if (priv->write_d_len == 0) + { + memcpy(priv->write_buf, buffer, buflen); - if (buflen > CONFIG_NET_TUN_PKTSIZE) - { - ret = -EINVAL; - } - else - { - memcpy(priv->write_buf, buffer, buflen); + net_lock(); + priv->dev.d_buf = priv->write_buf; + priv->dev.d_len = buflen; + + tun_net_receive(priv); + net_unlock(); + + ret = buflen; + break; + } - priv->dev.d_buf = priv->write_buf; - priv->dev.d_len = buflen; + /* Wait if there are no free space to write */ - tun_net_receive(priv); + if ((filep->f_oflags & O_NONBLOCK) != 0) + { + ret = -EAGAIN; + break; + } - ret = (ssize_t)buflen; + priv->write_wait = true; + tun_unlock(priv); + nxsem_wait(&priv->write_wait_sem); + tun_lock(priv); } - net_unlock(); tun_unlock(priv); - return ret; } @@ -1282,8 +1253,6 @@ static ssize_t tun_read(FAR struct file *filep, FAR char *buffer, { FAR struct tun_device_s *priv = filep->f_priv; ssize_t ret; - size_t write_d_len; - size_t read_d_len; if (priv == NULL) { @@ -1292,33 +1261,53 @@ static ssize_t tun_read(FAR struct file *filep, FAR char *buffer, tun_lock(priv); - /* Check if there are data to read in write buffer */ - - write_d_len = priv->write_d_len; - if (write_d_len > 0) + for (; ; ) { - if (buflen < write_d_len) + /* Check if there are data to read in write buffer */ + + if (priv->write_d_len > 0) { - ret = -EINVAL; - goto out; + if (buflen < priv->write_d_len) + { + ret = -EINVAL; + break; + } + + memcpy(buffer, priv->write_buf, priv->write_d_len); + ret = priv->write_d_len; + priv->write_d_len = 0; + + NETDEV_TXDONE(&priv->dev); + tun_pollnotify(priv, POLLOUT); + break; } - memcpy(buffer, priv->write_buf, write_d_len); - ret = (ssize_t)write_d_len; + /* Check if there are data to read in read buffer */ - priv->write_d_len = 0; - NETDEV_TXDONE(&priv->dev); - tun_pollnotify(priv, POLLOUT); + if (priv->read_d_len > 0) + { + if (buflen < priv->read_d_len) + { + ret = -EINVAL; + break; + } - goto out; - } + memcpy(buffer, priv->read_buf, priv->read_d_len); + ret = priv->read_d_len; + priv->read_d_len = 0; + + net_lock(); + tun_txdone(priv); + net_unlock(); + break; + } + + /* Wait if there are no data to read */ - if (priv->read_d_len == 0) - { if ((filep->f_oflags & O_NONBLOCK) != 0) { ret = -EAGAIN; - goto out; + break; } priv->read_wait = true; @@ -1327,27 +1316,7 @@ static ssize_t tun_read(FAR struct file *filep, FAR char *buffer, tun_lock(priv); } - net_lock(); - - read_d_len = priv->read_d_len; - if (buflen < read_d_len) - { - ret = -EINVAL; - } - else - { - memcpy(buffer, priv->read_buf, read_d_len); - ret = (ssize_t)read_d_len; - } - - priv->read_d_len = 0; - tun_txdone(priv); - - net_unlock(); - -out: tun_unlock(priv); - return ret; } @@ -1410,7 +1379,6 @@ int tun_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup) errout: tun_unlock(priv); - return ret; } From 57099fe4415a7c33279e0e60b6f9026c1649ccde Mon Sep 17 00:00:00 2001 From: liuhaitao Date: Sun, 2 Feb 2020 10:29:28 +0800 Subject: [PATCH 02/35] tools/testbuild.sh: update fail to return the error value instead --- tools/testbuild.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/testbuild.sh b/tools/testbuild.sh index 59b02186086..79561fa83a1 100755 --- a/tools/testbuild.sh +++ b/tools/testbuild.sh @@ -154,7 +154,7 @@ cd $nuttx || { echo "ERROR: failed to CD to $nuttx"; exit 1; } function distclean { if [ -f .config ]; then echo " Cleaning..." - ${MAKE} ${JOPTION} ${MAKE_FLAGS} distclean 1>/dev/null || fail=1 + ${MAKE} ${JOPTION} ${MAKE_FLAGS} distclean 1>/dev/null || fail=$? fi } @@ -183,7 +183,7 @@ function configure { echo "$toolchain=y" >> $nuttx/.config echo " Refreshing..." - ${MAKE} ${MAKE_FLAGS} olddefconfig 1>/dev/null || fail=1 + ${MAKE} ${MAKE_FLAGS} olddefconfig 1>/dev/null || fail=$? fi } @@ -192,7 +192,7 @@ function configure { function build { echo " Building NuttX..." echo "------------------------------------------------------------------------------------" - ${MAKE} ${JOPTION} ${MAKE_FLAGS} 1>/dev/null || fail=1 + ${MAKE} ${JOPTION} ${MAKE_FLAGS} 1>/dev/null || fail=$? } # Coordinate the steps for the next build test From 2d7c072723902aa763d3851f6399c39cbb1851fe Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 2 Feb 2020 14:20:43 +0800 Subject: [PATCH 03/35] Remove duplicated NET_SLIP option from drivers/net/Kconfig --- ChangeLog | 4 ++-- ReleaseNotes | 4 ++-- drivers/net/Kconfig | 33 --------------------------------- drivers/net/slip.c | 2 +- include/nuttx/net/slip.h | 2 +- net/Kconfig | 7 ++++++- 6 files changed, 12 insertions(+), 40 deletions(-) diff --git a/ChangeLog b/ChangeLog index 33cb6974a66..808be46ec12 100644 --- a/ChangeLog +++ b/ChangeLog @@ -15767,7 +15767,7 @@ Other TCP-specific issues also fixed. There remains a major outstanding issue with ACK handling. Handle case where the local address is zero (listen socket). Major re-architecting of TCP logic - to properly handle TCP stuf like ACKs and TPC windowing which were + to properly handle TCP stuf like ACKs and TCP windowing which were not properly covered in the initial design. Still does not work; hangs waiting of ACKs.Various fixes for a clean build if either TCP or UDP are disabled. Given the current state of TCP, it is @@ -17528,7 +17528,7 @@ use file-system in between. NOTE that this provides the opposite capability of FTL which will let you use an MTD interface directly as a block device. From Jussi Kivilinna (2017-10-19). - * There was a reference counting problem in the TPC logic of + * There was a reference counting problem in the TCP logic of net_clone(). net_clone() which is the common logic underlying dup() and dup2() for sockets. When net_clone() calls net_start_monitor() and net_start_monitor() returns a failure (because the underlying TCP diff --git a/ReleaseNotes b/ReleaseNotes index 4feea7fba79..59d4810e3af 100644 --- a/ReleaseNotes +++ b/ReleaseNotes @@ -16312,7 +16312,7 @@ detailed bugfix information): - sockgetname() files need to include udp/udp.h and tcp/tcp.h or otherwise NET_UDP_HAVE_STACK and NET_TCP_HAVE_STACK are undefined and the logic is never compiled. Noted by Anthony Merlino. - - dup()/dup2(): There was a reference counting problem in the TPC + - dup()/dup2(): There was a reference counting problem in the TCP logic of net_clone(). net_clone() which is the common logic underlying dup() and dup2() for sockets. When net_clone() calls net_start_monitor() and net_start_monitor() returns a failure @@ -20236,7 +20236,7 @@ detailed bugfix information): multicast address. Exiting logic only supported UDP multicast. But MLD and certain other ICMPv6 packets also require acceptance of multicast packets. From Gregory Nutt. - - TCP: In TPC recv window calculations, in order to receive data we + - TCP: In TCP recv window calculations, in order to receive data we must not only have IOBs available, but we must also have at least one IOB chain qentry available. Otherwise, we will advertise that we an buffer a lot of data when, in fact, we cannot. This is an diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index df323c25a9d..db0531890c2 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -94,10 +94,6 @@ config TELNET_DUMPBUFFER endif # NETDEV_TELNET -config ARCH_HAVE_NETDEV_STATISTICS - bool - default n - config NETDEV_STATISTICS bool "Network device driver statistics" depends on NET_STATISTICS && ARCH_HAVE_NETDEV_STATISTICS @@ -307,35 +303,6 @@ config ENCX24J600_REGDEBUG endif # ENCX24J600 -menuconfig NET_SLIP - bool "SLIP (serial line) support" - default n - select ARCH_HAVE_NETDEV_STATISTICS - ---help--- - Reference: RFC 1055 - -if NET_SLIP - -config NET_SLIP_STACKSIZE - int "Daemon stack size" - default 2048 - ---help--- - Provides the stack size for SLIP RX and TX. - -config NET_SLIP_DEFPRIO - int "Daemon priority" - default 128 - ---help--- - Provides the priority for SLIP RX and TX threads. - -config NET_SLIP_NINTERFACES - int "Number of SLIP interfaces" - default 1 - ---help--- - Determines the number of physical interfaces that will be supported. - -endif - menuconfig NET_FTMAC100 bool "Faraday 10/100 Ethernet" default n diff --git a/drivers/net/slip.c b/drivers/net/slip.c index 0972a9c9c25..d8307c05044 100644 --- a/drivers/net/slip.c +++ b/drivers/net/slip.c @@ -87,7 +87,7 @@ #endif /* The Linux slip module hard-codes its MTU size to 296 (40 bytes for the - * IP+TPC headers plus 256 bytes of data). So you might as well set + * IP+TCP headers plus 256 bytes of data). So you might as well set * CONFIG_NET_SLIP_PKTSIZE to 296 as well. * * There may be an issue with this setting, however. I see that Linux uses diff --git a/include/nuttx/net/slip.h b/include/nuttx/net/slip.h index 914f0ffd6bd..0efae08b6e8 100644 --- a/include/nuttx/net/slip.h +++ b/include/nuttx/net/slip.h @@ -62,7 +62,7 @@ * Default 296 * * The Linux slip module hard-codes its MTU size to 296 (40 bytes for the - * IP+TPC headers plus 256 bytes of data). So you might as well set + * IP+TCP headers plus 256 bytes of data). So you might as well set * CONFIG_NET_SLIP_PKTSIZE to 296 as well. * * There may be an issue with this setting, however. I see that Linux diff --git a/net/Kconfig b/net/Kconfig index 4c8d0dcec6d..306268a3c6b 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -11,6 +11,10 @@ config ARCH_HAVE_PHY bool default n +config ARCH_HAVE_NETDEV_STATISTICS + bool + default n + config NET_WRITE_BUFFERS bool default n @@ -84,7 +88,7 @@ config NET_SLIP_PKTSIZE 296 are not recommended. The Linux slip module hard-codes its MTU size to 296 (40 bytes for - the IP+TPC headers plus 256 bytes of data). So you might as well + the IP+TCP headers plus 256 bytes of data). So you might as well set CONFIG_NET_SLIP_PKTSIZE to 296 as well. There may be an issue with this setting, however. I see that Linux @@ -125,6 +129,7 @@ config NET_LOOPBACK menuconfig NET_SLIP bool "SLIP support" + select ARCH_HAVE_NETDEV_STATISTICS default n ---help--- Enables building of the SLIP driver. SLIP requires From c5b1554d84bc4990667fb91fdf6276e2b258f501 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 2 Feb 2020 14:15:24 +0800 Subject: [PATCH 04/35] Remove NETDEV_LOOPBACK option, NET_LOOPBACK is enough --- arch/arm/src/common/up_initialize.c | 2 +- arch/avr/src/common/up_initialize.c | 2 +- arch/hc/src/common/up_initialize.c | 2 +- arch/mips/src/common/up_initialize.c | 2 +- arch/or1k/src/common/up_initialize.c | 2 +- arch/renesas/src/common/up_initialize.c | 2 +- arch/sim/src/sim/up_initialize.c | 2 +- arch/x86/src/common/up_initialize.c | 2 +- arch/xtensa/src/common/xtensa_initialize.c | 2 +- arch/z16/src/common/up_initialize.c | 2 +- arch/z80/src/common/up_initialize.c | 2 +- drivers/net/Kconfig | 11 ----------- drivers/net/Make.defs | 2 +- drivers/net/loopback.c | 8 ++++---- fs/userfs/Kconfig | 2 +- include/nuttx/net/loopback.h | 2 -- net/Kconfig | 1 + 17 files changed, 18 insertions(+), 30 deletions(-) diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c index 14a287a5ed8..3ad5ff880f2 100644 --- a/arch/arm/src/common/up_initialize.c +++ b/arch/arm/src/common/up_initialize.c @@ -247,7 +247,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/avr/src/common/up_initialize.c b/arch/avr/src/common/up_initialize.c index 867d0eafc58..8378ac49f31 100644 --- a/arch/avr/src/common/up_initialize.c +++ b/arch/avr/src/common/up_initialize.c @@ -285,7 +285,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/hc/src/common/up_initialize.c b/arch/hc/src/common/up_initialize.c index 1b44f614445..3e588fd9b1b 100644 --- a/arch/hc/src/common/up_initialize.c +++ b/arch/hc/src/common/up_initialize.c @@ -207,7 +207,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c index b60662e824d..345657822a8 100644 --- a/arch/mips/src/common/up_initialize.c +++ b/arch/mips/src/common/up_initialize.c @@ -209,7 +209,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/or1k/src/common/up_initialize.c b/arch/or1k/src/common/up_initialize.c index 8c140e01d4b..5609a5f405d 100644 --- a/arch/or1k/src/common/up_initialize.c +++ b/arch/or1k/src/common/up_initialize.c @@ -305,7 +305,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/renesas/src/common/up_initialize.c b/arch/renesas/src/common/up_initialize.c index cf8e7617fe2..0993bcf67fe 100644 --- a/arch/renesas/src/common/up_initialize.c +++ b/arch/renesas/src/common/up_initialize.c @@ -193,7 +193,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/sim/src/sim/up_initialize.c b/arch/sim/src/sim/up_initialize.c index 124cc39ecb8..94a586ff998 100644 --- a/arch/sim/src/sim/up_initialize.c +++ b/arch/sim/src/sim/up_initialize.c @@ -274,7 +274,7 @@ void up_initialize(void) netdriver_init(); /* Our "real" network driver */ #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/x86/src/common/up_initialize.c b/arch/x86/src/common/up_initialize.c index 35498b64d5c..432672be3f7 100644 --- a/arch/x86/src/common/up_initialize.c +++ b/arch/x86/src/common/up_initialize.c @@ -209,7 +209,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index 75fd8b7ba64..922b4a528ba 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -217,7 +217,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/z16/src/common/up_initialize.c b/arch/z16/src/common/up_initialize.c index 0e4e0ba67d1..4da19789c23 100644 --- a/arch/z16/src/common/up_initialize.c +++ b/arch/z16/src/common/up_initialize.c @@ -209,7 +209,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/arch/z80/src/common/up_initialize.c b/arch/z80/src/common/up_initialize.c index 4d42fa221ac..c93c776bb38 100644 --- a/arch/z80/src/common/up_initialize.c +++ b/arch/z80/src/common/up_initialize.c @@ -214,7 +214,7 @@ void up_initialize(void) up_netinitialize(); #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /* Initialize the local loopback device */ localhost_initialize(); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index db0531890c2..68b5b843995 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -5,17 +5,6 @@ comment "General Ethernet MAC Driver Options" -config NETDEV_LOOPBACK - bool - default n if !NET_LOOPBACK - default y if NET_LOOPBACK - select ARCH_HAVE_NETDEV_STATISTICS - ---help--- - Add support for the local network loopback device, lo. - -if NETDEV_LOOPBACK -endif # NETDEV_LOOPBACK - config NET_RPMSG_DRV bool "RPMSG net driver" depends on NET && OPENAMP diff --git a/drivers/net/Make.defs b/drivers/net/Make.defs index bf8e314d683..c5078e00778 100644 --- a/drivers/net/Make.defs +++ b/drivers/net/Make.defs @@ -39,7 +39,7 @@ ifeq ($(CONFIG_NET),y) # Include network interface drivers -ifeq ($(CONFIG_NETDEV_LOOPBACK),y) +ifeq ($(CONFIG_NET_LOOPBACK),y) CSRCS += loopback.c endif diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index d990d6856bf..88a5d057c3a 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -62,13 +62,13 @@ # include #endif -#ifdef CONFIG_NETDEV_LOOPBACK +#ifdef CONFIG_NET_LOOPBACK /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* We need to have the work queue to handle SPI interrupts */ +/* We need to have the work queue to handle interrupts */ #if !defined(CONFIG_SCHED_WORKQUEUE) # error Worker thread support is required (CONFIG_SCHED_WORKQUEUE) @@ -78,7 +78,7 @@ #define LO_WDDELAY (1*CLK_TCK) -/* This is a helper pointer for accessing the contents of the Ethernet header */ +/* This is a helper pointer for accessing the contents of the IP header */ #define IPv4BUF ((FAR struct ipv4_hdr_s *)priv->lo_dev.d_buf) #define IPv6BUF ((FAR struct ipv6_hdr_s *)priv->lo_dev.d_buf) @@ -552,4 +552,4 @@ int localhost_initialize(void) return lo_ifup(&priv->lo_dev); } -#endif /* CONFIG_NETDEV_LOOPBACK */ +#endif /* CONFIG_NET_LOOPBACK */ diff --git a/fs/userfs/Kconfig b/fs/userfs/Kconfig index 4a13140b8b2..762e4c85e26 100644 --- a/fs/userfs/Kconfig +++ b/fs/userfs/Kconfig @@ -6,7 +6,7 @@ config FS_USERFS bool "User file system" default n - depends on NET_IPv4 && NET_UDP && NETDEV_LOOPBACK + depends on NET_IPv4 && NET_UDP && NET_LOOPBACK ---help--- Enable support for user file system. See include/nuttx/fs/userfs.h diff --git a/include/nuttx/net/loopback.h b/include/nuttx/net/loopback.h index 03bc0a3dc19..1dce9fc1d4f 100644 --- a/include/nuttx/net/loopback.h +++ b/include/nuttx/net/loopback.h @@ -99,9 +99,7 @@ EXTERN const net_ipv6addr_t g_lo_ipv6mask; * ****************************************************************************/ -#ifdef CONFIG_NETDEV_LOOPBACK int localhost_initialize(void); -#endif /* CONFIG_NETDEV_LOOPBACK */ #undef EXTERN #ifdef __cplusplus diff --git a/net/Kconfig b/net/Kconfig index 306268a3c6b..e7c697347e4 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -123,6 +123,7 @@ config NET_ETHERNET config NET_LOOPBACK bool "Local loopback" + select ARCH_HAVE_NETDEV_STATISTICS default n ---help--- Add support for the local network loopback device, lo. From ca8191ad41e78031f98bd6b542e8509e791e6fa4 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 2 Feb 2020 15:21:03 +0800 Subject: [PATCH 05/35] drivers/net/slip.c: Don't use fd related operation in SLIP kernel thread --- drivers/net/slip.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/net/slip.c b/drivers/net/slip.c index d8307c05044..646e2ad1923 100644 --- a/drivers/net/slip.c +++ b/drivers/net/slip.c @@ -59,6 +59,7 @@ #include #include #include +#include #include #include #include @@ -139,7 +140,7 @@ struct slip_driver_s { volatile bool bifup; /* true:ifup false:ifdown */ bool txnodelay; /* True: nxsig_usleep() not needed */ - int16_t fd; /* TTY file descriptor */ + struct file file; /* TTY file descriptor */ uint16_t rxlen; /* The number of bytes in rxbuf */ pid_t rxpid; /* Receiver thread ID */ pid_t txpid; /* Transmitter thread ID */ @@ -173,9 +174,9 @@ static void slip_semtake(FAR struct slip_driver_s *priv); static void slip_write(FAR struct slip_driver_s *priv, FAR const uint8_t *buffer, int len); static void slip_putc(FAR struct slip_driver_s *priv, int ch); -static int slip_transmit(FAR struct slip_driver_s *priv); +static void slip_transmit(FAR struct slip_driver_s *priv); static int slip_txpoll(FAR struct net_driver_s *dev); -static void slip_txtask(int argc, FAR char *argv[]); +static int slip_txtask(int argc, FAR char *argv[]); /* Packet receiver task */ @@ -226,9 +227,8 @@ static inline void slip_write(FAR struct slip_driver_s *priv, { /* Handle the case where the write is awakened by a signal */ - while (write(priv->fd, buffer, len) < 0) + while (file_write(&priv->file, buffer, len) < 0) { - DEBUGASSERT(errno == EINTR); } } @@ -265,7 +265,7 @@ static inline void slip_putc(FAR struct slip_driver_s *priv, int ch) * ****************************************************************************/ -static int slip_transmit(FAR struct slip_driver_s *priv) +static void slip_transmit(FAR struct slip_driver_s *priv) { uint8_t *src; uint8_t *start; @@ -359,7 +359,6 @@ static int slip_transmit(FAR struct slip_driver_s *priv) slip_putc(priv, SLIP_END); NETDEV_TXDONE(&priv->dev); priv->txnodelay = true; - return OK; } /**************************************************************************** @@ -420,7 +419,7 @@ static int slip_txpoll(FAR struct net_driver_s *dev) * ****************************************************************************/ -static void slip_txtask(int argc, FAR char *argv[]) +static int slip_txtask(int argc, FAR char *argv[]) { FAR struct slip_driver_s *priv; unsigned int index = *(argv[1]) - '0'; @@ -443,7 +442,7 @@ static void slip_txtask(int argc, FAR char *argv[]) start_ticks = clock_systimer(); for (; ; ) { - /* Wait for the timeout to expire (or until we are signaled by by */ + /* Wait for the timeout to expire (or until we are signaled by */ slip_semtake(priv); if (!priv->txnodelay) @@ -494,6 +493,8 @@ static void slip_txtask(int argc, FAR char *argv[]) slip_semgive(priv); } } + + return OK; } /**************************************************************************** @@ -514,12 +515,11 @@ static inline int slip_getc(FAR struct slip_driver_s *priv) { uint8_t ch; - while (read(priv->fd, &ch, 1) < 0) + while (file_read(&priv->file, &ch, 1) < 0) { - DEBUGASSERT(errno == EINTR); } - return (int)ch; + return ch; } /**************************************************************************** @@ -952,6 +952,7 @@ int slip_initialize(int intf, FAR const char *devname) FAR struct slip_driver_s *priv; char buffer[8]; FAR char *argv[2]; + int ret; /* Get the interface structure associated with this interface number. */ @@ -972,11 +973,11 @@ int slip_initialize(int intf, FAR const char *devname) /* Open the device */ - priv->fd = nx_open(devname, O_RDWR, 0666); - if (priv->fd < 0) + ret = file_open(&priv->file, devname, O_RDWR, 0666); + if (ret < 0) { - nerr("ERROR: Failed to open %s: %d\n", devname, priv->fd); - return priv->fd; + nerr("ERROR: Failed to open %s: %d\n", devname, ret); + return ret; } /* Initialize the wait semaphore */ @@ -991,7 +992,7 @@ int slip_initialize(int intf, FAR const char *devname) argv[1] = NULL; priv->rxpid = kthread_create("rxslip", CONFIG_NET_SLIP_DEFPRIO, - CONFIG_NET_SLIP_STACKSIZE, (main_t)slip_rxtask, + CONFIG_NET_SLIP_STACKSIZE, slip_rxtask, (FAR char * const *)argv); if (priv->rxpid < 0) { @@ -1006,7 +1007,7 @@ int slip_initialize(int intf, FAR const char *devname) /* Start the SLIP transmitter kernel thread */ priv->txpid = kthread_create("txslip", CONFIG_NET_SLIP_DEFPRIO, - CONFIG_NET_SLIP_STACKSIZE, (main_t)slip_txtask, + CONFIG_NET_SLIP_STACKSIZE, slip_txtask, (FAR char * const *)argv); if (priv->txpid < 0) { @@ -1025,13 +1026,6 @@ int slip_initialize(int intf, FAR const char *devname) /* Register the device with the OS so that socket IOCTLs can be performed */ netdev_register(&priv->dev, NET_LL_SLIP); - - /* When the RX and TX tasks were created, the TTY file descriptor was - * dup'ed for each task. This task no longer needs the file descriptor - * and we can safely close it. - */ - - close(priv->fd); return OK; } From 0159726da5794eecddc2a949ec46afccd6552fc3 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 2 Feb 2020 15:24:17 +0800 Subject: [PATCH 06/35] drivers/net/slip.c: It's enough to only hold the net lock in SLIP driver --- drivers/net/slip.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/net/slip.c b/drivers/net/slip.c index 646e2ad1923..bdd2481bbfa 100644 --- a/drivers/net/slip.c +++ b/drivers/net/slip.c @@ -460,12 +460,6 @@ static int slip_txtask(int argc, FAR char *argv[]) if (priv->bifup) { - /* Get exclusive access to the network (if it it is already being - * used slip_rxtask, then we have to wait). - */ - - slip_semtake(priv); - /* Poll the networking layer for new XMIT data. */ net_lock(); @@ -490,7 +484,6 @@ static int slip_txtask(int argc, FAR char *argv[]) } net_unlock(); - slip_semgive(priv); } } @@ -705,11 +698,10 @@ static int slip_rxtask(int argc, FAR char *argv[]) /* Handle the IP input. Get exclusive access to the network. */ - slip_semtake(priv); + net_lock(); priv->dev.d_buf = priv->rxbuf; priv->dev.d_len = priv->rxlen; - net_lock(); NETDEV_RXPACKETS(&priv->dev); /* All packets are assumed to be IP packets (we don't have a choice.. @@ -759,7 +751,6 @@ static int slip_rxtask(int argc, FAR char *argv[]) } net_unlock(); - slip_semgive(priv); } /* We won't get here */ From 7a5f92ec0c0b1a59e3923297a4fba2e9ef65b37c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 2 Feb 2020 08:48:48 -0600 Subject: [PATCH 07/35] sched/sched/sched_getcpu.c: All new files should have Apache 2.0 headers. --- sched/sched/sched_getcpu.c | 39 ++++++++++++-------------------------- 1 file changed, 12 insertions(+), 27 deletions(-) diff --git a/sched/sched/sched_getcpu.c b/sched/sched/sched_getcpu.c index 9e5ada23e1f..85a172f458f 100644 --- a/sched/sched/sched_getcpu.c +++ b/sched/sched/sched_getcpu.c @@ -1,35 +1,20 @@ /**************************************************************************** * sched/sched/sched_getcpu.c * - * Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ From 18325867bb72c81597776d3b0cdd257ea04329b0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 2 Feb 2020 08:49:14 -0600 Subject: [PATCH 08/35] Documentation/NuttXCCodingStandard.html: Update license information * Change required license for new files from BSD to Apache 2.0 * Update source file templates to use Apache 2.0 license vs. the BSD license. --- Documentation/NuttXCCodingStandard.html | 88 ++++++++----------------- 1 file changed, 29 insertions(+), 59 deletions(-) diff --git a/Documentation/NuttXCCodingStandard.html b/Documentation/NuttXCCodingStandard.html index 74522f2ed27..4af6a8a8303 100644 --- a/Documentation/NuttXCCodingStandard.html +++ b/Documentation/NuttXCCodingStandard.html @@ -87,7 +87,7 @@

Table of Contents

NuttX C Coding Standard

-

Last Updated: January 2, 2020

+

Last Updated: February 2, 2020

@@ -132,15 +132,15 @@

1.1 File Organization

  • A blank line
  • - Standard (modified) BSD licensing information. + NuttX standard Apache 2.0 licensing information as provided in the appendix.

    • Sample File Headers. Sample file headers are provided in an Appendix to this document. - No software may be included in the NuttX source tree that does not have licensing information included in the file. - No software may be included in the NuttX source tree that does not have a (modified) BSD license or compatible license (such as the MIT license). - If the file does not following BSD licensing, then the appropriate license information should be provided in the header rather than the (modified) BSD licensing information and a NOTE should be included in the top-level COPYING file to indicate any variations from (modified) BSD licensing. + No new software may be included in the NuttX source tree that does not have licensing information included in the file. + No new software may be included in the NuttX source tree that does not have a Apache 2.0 license or license (or, in the case of 3rd party file, a compatible license such as the BSD or MIT licenses). + If the file does not follow Apache 2.0 licensing, then the appropriate license information should be provided in the header rather than the Apache 2.0 licensing information and a NOTE should be included in the top-level COPYING file to indicate any variations from Apache 2.0 licensing.

    Grouping. @@ -2888,35 +2888,20 @@

    A.1 C Source File Structure

    * <Relative path to the file> * <Optional one line file description> * - * Copyright (C) <Year> <Copyright holder's name>. All rights reserved. - * Author: <Author's name> <Contact e-mail> + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -3014,35 +2999,20 @@

    A.2 C Header File Structure

    * <Relative path to the file> * <Optional one line file description> * - * Copyright (C) <Year> <Copyright holder's name>. All rights reserved. - * Author: <Author's name> <Contact e-mail> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * http://www.apache.org/licenses/LICENSE-2.0 * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ From 1321c34022d8e867ee3da1b664c4c7a95ee6a3e8 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 2 Feb 2020 15:42:28 +0800 Subject: [PATCH 09/35] drivers/net/phy_notify.c: Use IFNAMSIZ for interface name size Replace CONFIG_PHY_NOTIFICATION_MAXINTFLEN with IFNAMSIZ --- drivers/net/phy_notify.c | 13 +++++-------- include/nuttx/net/phy.h | 10 ---------- 2 files changed, 5 insertions(+), 18 deletions(-) diff --git a/drivers/net/phy_notify.c b/drivers/net/phy_notify.c index 3ceda17e910..7d6abb8cad0 100644 --- a/drivers/net/phy_notify.c +++ b/drivers/net/phy_notify.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include @@ -104,7 +105,7 @@ struct phy_notify_s { bool assigned; - char intf[CONFIG_PHY_NOTIFICATION_MAXINTFLEN + 1]; + char intf[IFNAMSIZ + 1]; pid_t pid; struct sigevent event; struct sigwork_s work; @@ -200,7 +201,7 @@ static FAR struct phy_notify_s *phy_find_assigned(FAR const char *intf, { client = &g_notify_clients[i]; if (client->assigned && client->pid == pid && - strncmp(client->intf, intf, CONFIG_PHY_NOTIFICATION_MAXINTFLEN) == 0) + strncmp(client->intf, intf, IFNAMSIZ) == 0) { /* Return the matching client entry to the caller */ @@ -262,8 +263,6 @@ static int phy_handler(int irq, FAR void *context, FAR void *arg) * * Input Parameters: * intf - Provides the name of the network interface, for example, "eth0". - * The length of intf must not exceed 4 bytes (excluding NULL - * terminator). Configurable with CONFIG_PHY_NOTIFICATION_MAXINTFLEN. * pid - Identifies the task to receive the signal. The special value * of zero means to use the pid of the current task. * event - Describes the way a task is to be notified @@ -315,8 +314,8 @@ int phy_notify_subscribe(FAR const char *intf, pid_t pid, client->pid = pid; client->event = *event; - strncpy(client->intf, intf, CONFIG_PHY_NOTIFICATION_MAXINTFLEN + 1); - client->intf[CONFIG_PHY_NOTIFICATION_MAXINTFLEN] = '\0'; + strncpy(client->intf, intf, IFNAMSIZ + 1); + client->intf[IFNAMSIZ] = '\0'; /* Attach/re-attach the PHY interrupt */ @@ -343,8 +342,6 @@ int phy_notify_subscribe(FAR const char *intf, pid_t pid, * * Input Parameters: * intf - Provides the name of the network interface, for example, "eth0". - * The length of 'intf' must not exceed 4 bytes (excluding NULL - * terminator). Configurable with CONFIG_PHY_NOTIFICATION_MAXINTFLEN. * pid - Identifies the task that was receiving notifications. * * Returned Value: diff --git a/include/nuttx/net/phy.h b/include/nuttx/net/phy.h index 553cbe369a6..ae7e294c29e 100644 --- a/include/nuttx/net/phy.h +++ b/include/nuttx/net/phy.h @@ -60,12 +60,6 @@ # define CONFIG_PHY_NOTIFICATION_NCLIENTS 1 #endif -/* Maximum length of on interface device name (excluding NULL termination) */ - -#ifndef CONFIG_PHY_NOTIFICATION_MAXINTFLEN -# define CONFIG_PHY_NOTIFICATION_MAXINTFLEN 4 -#endif - /**************************************************************************** * Public Data ****************************************************************************/ @@ -96,8 +90,6 @@ extern "C" * * Input Parameters: * intf - Provides the name of the network interface, for example, "eth0". - * The length of intf must not exceed 4 bytes (excluding NULL - * terminator). Configurable with CONFIG_PHY_NOTIFICATION_MAXINTFLEN. * pid - Identifies the task to receive the signal. The special value * of zero means to use the pid of the current task. * event - Describe the way a task is to be notified @@ -125,8 +117,6 @@ int phy_notify_subscribe(FAR const char *intf, pid_t pid, * * Input Parameters: * intf - Provides the name of the network interface, for example, "eth0". - * The length of 'intf' must not exceed 4 bytes (excluding NULL - * terminator). Configurable with CONFIG_PHY_NOTIFICATION_MAXINTFLEN. * pid - Identifies the task that was receiving notifications. * * Returned Value: From 5f7a797e89a48ad0f633f740970abd4259858d31 Mon Sep 17 00:00:00 2001 From: liuhaitao Date: Mon, 3 Feb 2020 10:07:32 +0800 Subject: [PATCH 10/35] net/igmp/igmp.h: include to fix build break Build nucleo-144/f767-netnsh fail with below error: In file included from igmp/igmp_initialize.c:54: ./igmp/igmp.h:130:3: error: unknown type name 'sem_t' 130 | sem_t sem; /* Used to wait for message transmission */ | ^~~~~ make[1]: *** [igmp_initialize.o] Error 1 Signed-off-by: liuhaitao --- net/igmp/igmp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/net/igmp/igmp.h b/net/igmp/igmp.h index e97352bb876..e2f94791beb 100644 --- a/net/igmp/igmp.h +++ b/net/igmp/igmp.h @@ -77,6 +77,7 @@ #include +#include #include #include From 2483b65bfba479ff44286152d7d85dd3ed731c7f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 3 Feb 2020 10:13:18 -0600 Subject: [PATCH 11/35] tools/nxstyle.c: Ignore inttypes.h constants. Eliminate warnings. Ignore mixed case identifies beginning with PRIx. These most likely come from inttypes.h and we nxstyle must tolerate those definitions even though they do not follow the coding style. --- tools/nxstyle.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/tools/nxstyle.c b/tools/nxstyle.c index b2bb33fe5a3..8ee609e2bbd 100644 --- a/tools/nxstyle.c +++ b/tools/nxstyle.c @@ -1265,27 +1265,38 @@ int main(int argc, char **argv, char **envp) if (have_upper && have_lower) { + /* REVISIT: Although pre-processor definitions are + * supposed to be all upper-case, there are exceptions + * such as using 'p' for a decimal point or 'MHz'. + * Those will be reported here, but probably should be + * considered false alarms. + */ + + /* Ignore inttype.h strings beginning with PRIx */ + + if (ident_index >= 4 && + (strncmp(&line[ident_index], "PRIx", 4) == 0)) + { + /* No error */ + } + /* Special case hex constants. These will look like * identifiers starting with 'x' or 'X' but preceded * with '0' */ - if (ident_index < 1 || - (line[ident_index] != 'x' && line[ident_index] != 'X') || - line[ident_index - 1] != '0') + else if (ident_index < 1 || + (line[ident_index] != 'x' && + line[ident_index] != 'X') || + line[ident_index - 1] != '0') { - /* REVISIT: Although pre-processor definitions are - * supposed to be all upper-case, there are exceptions - * such as using 'p' for a decimal point or 'MHz'. - * Those will be reported here, but probably should be - * considered false alarms. - */ - - ERROR("Mixed case identifier found", lineno, ident_index); + ERROR("Mixed case identifier found", + lineno, ident_index); } else if (have_upper) { - ERROR("Upper case hex constant found", lineno, ident_index); + ERROR("Upper case hex constant found", + lineno, ident_index); } } From adbff7de81944ef76fbdb9838fe5d7b29641a6b2 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 13 May 2018 17:22:25 +0800 Subject: [PATCH 12/35] tools/Config.mk: add DEFINE macro like INCDIR --- libs/libc/Makefile | 6 +----- libs/libnx/Makefile | 6 +----- mm/Makefile | 6 +----- tools/Config.mk | 2 ++ tools/Makefile.unix | 2 +- tools/Makefile.win | 2 +- 6 files changed, 7 insertions(+), 17 deletions(-) diff --git a/libs/libc/Makefile b/libs/libc/Makefile index f4b6cea3873..de648dc3751 100644 --- a/libs/libc/Makefile +++ b/libs/libc/Makefile @@ -38,11 +38,7 @@ # CFLAGS ifneq ($(CONFIG_BUILD_FLAT),y) -ifeq ($(CONFIG_WINDOWS_NATIVE),y) - KDEFINE = ${shell $(TOPDIR)\tools\define.bat "$(CC)" __KERNEL__} -else - KDEFINE = ${shell $(TOPDIR)/tools/define.sh "$(CC)" __KERNEL__} -endif + KDEFINE = ${shell $(DEFINE) "$(CC)" __KERNEL__} endif # Sources and paths diff --git a/libs/libnx/Makefile b/libs/libnx/Makefile index c0109dc07d5..cdf9b4fa148 100644 --- a/libs/libnx/Makefile +++ b/libs/libnx/Makefile @@ -38,11 +38,7 @@ # CFLAGS ifneq ($(CONFIG_BUILD_FLAT),y) -ifeq ($(CONFIG_WINDOWS_NATIVE),y) - KDEFINE = ${shell $(TOPDIR)\tools\define.bat "$(CC)" __KERNEL__} -else - KDEFINE = ${shell $(TOPDIR)/tools/define.sh "$(CC)" __KERNEL__} -endif + KDEFINE = ${shell $(DEFINE) "$(CC)" __KERNEL__} endif # Sources and paths diff --git a/mm/Makefile b/mm/Makefile index bc4ce9aff4c..7f1dbcfb6a8 100644 --- a/mm/Makefile +++ b/mm/Makefile @@ -41,11 +41,7 @@ DELIM := $(strip /) # CFLAGS ifneq ($(CONFIG_BUILD_FLAT),y) -ifeq ($(CONFIG_WINDOWS_NATIVE),y) - KDEFINE = ${shell $(TOPDIR)\tools\define.bat "$(CC)" __KERNEL__} -else - KDEFINE = ${shell $(TOPDIR)/tools/define.sh "$(CC)" __KERNEL__} -endif + KDEFINE = ${shell $(DEFINE) "$(CC)" __KERNEL__} endif # Sources and paths diff --git a/tools/Config.mk b/tools/Config.mk index 2a45f5b0e6b..0f6212890df 100644 --- a/tools/Config.mk +++ b/tools/Config.mk @@ -93,8 +93,10 @@ endif # CONFIG_WINDOWS_NATIVE - Defined for a Windows native build ifeq ($(CONFIG_WINDOWS_NATIVE),y) + DEFINE = "$(TOPDIR)\tools\define.bat" INCDIR = "$(TOPDIR)\tools\incdir.bat" else + DEFINE = "$(TOPDIR)/tools/define.sh" INCDIR = "$(TOPDIR)/tools/incdir.sh" endif diff --git a/tools/Makefile.unix b/tools/Makefile.unix index 917ea0dbdf8..cb4c0cc4c15 100644 --- a/tools/Makefile.unix +++ b/tools/Makefile.unix @@ -81,7 +81,7 @@ endif # This define is passed as EXTRADEFINES for kernel-mode builds. It is also passed # during PASS1 (but not PASS2) context and depend targets. -KDEFINE = ${shell $(TOPDIR)/tools/define.sh "$(CC)" __KERNEL__} +KDEFINE = ${shell $(DEFINE) "$(CC)" __KERNEL__} # Process architecture and board-specific directories diff --git a/tools/Makefile.win b/tools/Makefile.win index 6ef5bdc65f2..be4fd82a60c 100644 --- a/tools/Makefile.win +++ b/tools/Makefile.win @@ -66,7 +66,7 @@ endif # This define is passed as EXTRADEFINES for kernel-mode builds. It is also passed # during PASS1 (but not PASS2) context and depend targets. -KDEFINE = ${shell $(TOPDIR)\tools\define.bat "$(CC)" __KERNEL__} +KDEFINE = ${shell $(DEFINE) "$(CC)" __KERNEL__} # Process architecture and board-specific directories From dfcbc42679f5ee1c66185e829730c82b00473e8c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 3 Feb 2020 13:53:23 -0600 Subject: [PATCH 13/35] tools/nxstyle.c: Fix logic error in previous change. --- tools/nxstyle.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tools/nxstyle.c b/tools/nxstyle.c index 8ee609e2bbd..2167647a3d3 100644 --- a/tools/nxstyle.c +++ b/tools/nxstyle.c @@ -1274,8 +1274,7 @@ int main(int argc, char **argv, char **envp) /* Ignore inttype.h strings beginning with PRIx */ - if (ident_index >= 4 && - (strncmp(&line[ident_index], "PRIx", 4) == 0)) + if ((strncmp(&line[ident_index], "PRIx", 4) == 0)) { /* No error */ } From af68c22a2e29945169dbf83b806d98ec51536e54 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 4 Feb 2020 20:45:00 +0000 Subject: [PATCH 14/35] arch/arm/src/kinetis/kinetis_spi.c: Clear the MDIS bit before trying to disable TX or RX. --- arch/arm/src/kinetis/kinetis_spi.c | 96 ++++++++++++++++++------------ 1 file changed, 59 insertions(+), 37 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_spi.c b/arch/arm/src/kinetis/kinetis_spi.c index 82f2412d3e7..9ec568f5526 100644 --- a/arch/arm/src/kinetis/kinetis_spi.c +++ b/arch/arm/src/kinetis/kinetis_spi.c @@ -119,15 +119,18 @@ struct kinetis_spidev_s /* Helpers */ -static inline uint32_t spi_getreg(FAR struct kinetis_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(FAR struct kinetis_spidev_s *priv, uint8_t offset, - uint32_t value); -static inline uint16_t spi_getreg16(FAR struct kinetis_spidev_s *priv, uint8_t offset); -static inline void spi_putreg16(FAR struct kinetis_spidev_s *priv, uint8_t offset, - uint16_t value); -static inline uint8_t spi_getreg8(FAR struct kinetis_spidev_s *priv, uint8_t offset); -static inline void spi_putreg8(FAR struct kinetis_spidev_s *priv, uint8_t offset, - uint8_t value); +static inline uint32_t spi_getreg(FAR struct kinetis_spidev_s *priv, + uint8_t offset); +static inline void spi_putreg(FAR struct kinetis_spidev_s *priv, + uint8_t offset, uint32_t value); +static inline uint16_t spi_getreg16(FAR struct kinetis_spidev_s *priv, + uint8_t offset); +static inline void spi_putreg16(FAR struct kinetis_spidev_s *priv, + uint8_t offset, uint16_t value); +static inline uint8_t spi_getreg8(FAR struct kinetis_spidev_s *priv, + uint8_t offset); +static inline void spi_putreg8(FAR struct kinetis_spidev_s *priv, + uint8_t offset, uint8_t value); static inline uint16_t spi_readword(FAR struct kinetis_spidev_s *priv); static inline void spi_writeword(FAR struct kinetis_spidev_s *priv, uint16_t word); @@ -136,28 +139,31 @@ static inline void spi_run(FAR struct kinetis_spidev_s *priv, bool enable); static inline void spi_write_control(FAR struct kinetis_spidev_s *priv, uint32_t control); static inline void spi_write_status(FAR struct kinetis_spidev_s *priv, - uint32_t status); + uint32_t status); static inline void spi_wait_status(FAR struct kinetis_spidev_s *priv, - uint32_t status); -static uint16_t spi_send_data(FAR struct kinetis_spidev_s *priv, uint16_t wd, - bool last); + uint32_t status); +static uint16_t spi_send_data(FAR struct kinetis_spidev_s *priv, + uint16_t wd, bool last); /* SPI methods */ static int spi_lock(FAR struct spi_dev_s *dev, bool lock); -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); -static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); +static void spi_setmode(FAR struct spi_dev_s *dev, + enum spi_mode_e mode); static void spi_setbits(FAR struct spi_dev_s *dev, int nbits); #ifdef CONFIG_SPI_HWFEATURES static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features); #endif static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd); -static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, +static void spi_exchange(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, FAR void *rxbuffer, size_t nwords); #ifndef CONFIG_SPI_EXCHANGE -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, - size_t nwords); +static void spi_sndblock(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, size_t nwords); static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t nwords); #endif @@ -347,7 +353,8 @@ static inline void spi_putreg(FAR struct kinetis_spidev_s *priv, uint8_t offset, * ************************************************************************************/ -static inline uint16_t spi_getreg16(FAR struct kinetis_spidev_s *priv, uint8_t offset) +static inline uint16_t spi_getreg16(FAR struct kinetis_spidev_s *priv, + uint8_t offset) { return getreg16(priv->spibase + offset); } @@ -431,9 +438,9 @@ static inline void spi_putreg8(FAR struct kinetis_spidev_s *priv, uint8_t offset * ************************************************************************************/ -static inline void spi_write_status(FAR struct kinetis_spidev_s *priv, uint32_t status) +static inline void spi_write_status(FAR struct kinetis_spidev_s *priv, + uint32_t status) { - /* Write the SR Register */ spi_putreg(priv, KINETIS_SPI_SR_OFFSET, status); @@ -454,9 +461,9 @@ static inline void spi_write_status(FAR struct kinetis_spidev_s *priv, uint32_t * ************************************************************************************/ -static inline void spi_wait_status(FAR struct kinetis_spidev_s *priv, uint32_t status) +static inline void spi_wait_status(FAR struct kinetis_spidev_s *priv, + uint32_t status) { - while (status != (spi_getreg(priv, KINETIS_SPI_SR_OFFSET) & status)); } @@ -475,9 +482,9 @@ static inline void spi_wait_status(FAR struct kinetis_spidev_s *priv, uint32_t s * ************************************************************************************/ -static inline void spi_write_control(FAR struct kinetis_spidev_s *priv, uint32_t control) +static inline void spi_write_control(FAR struct kinetis_spidev_s *priv, + uint32_t control) { - /* Write the control word to the SPI Data Register */ spi_putreg16(priv, KINETIS_SPI_PUSHR_OFFSET + 2, (uint16_t) (control >> 16)); @@ -520,7 +527,7 @@ static inline void spi_writeword(FAR struct kinetis_spidev_s *priv, uint16_t wor * * Returned Value: * The 8-bit value from the FIFO - * + * ************************************************************************************/ static inline uint16_t spi_readword(FAR struct kinetis_spidev_s *priv) @@ -529,7 +536,7 @@ static inline uint16_t spi_readword(FAR struct kinetis_spidev_s *priv) spi_wait_status(priv, SPI_SR_RFDF | SPI_SR_TCF); - /* Return the data */ + /* Return the data */ return spi_getreg16(priv, KINETIS_SPI_POPR_OFFSET); } @@ -803,7 +810,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) regval = spi_getreg(priv, priv->ctarsel); regval &= ~(SPI_CTARM_FMSZ_MASK); - regval |= SPI_CTARM_FMSZ(nbits-1); + regval |= SPI_CTARM_FMSZ(nbits - 1); spi_putreg(priv, priv->ctarsel, regval); /* Save the selection so the subsequence re-configurations will be faster */ @@ -950,7 +957,8 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) * nwords - the length of data to be exchaned in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * packed into uint8_t's; if nbits > 8, the data is packed into + * uint16_t's * * Returned Value: * None @@ -1001,7 +1009,6 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, } else { - /* 8-bit mode */ while (nwords-- > 0) @@ -1019,7 +1026,8 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, /* Exchange one word */ - byte = (uint8_t) spi_send_data(priv, (uint16_t)byte, nwords ? false : true); + byte = (uint8_t) spi_send_data(priv, (uint16_t)byte, + nwords ? false : true); /* Is there a buffer to receive the return value? */ @@ -1030,6 +1038,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, } } } + /************************************************************************************ * Name: spi_sndblock * @@ -1042,7 +1051,8 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, * nwords - the length of data to send from the buffer in number of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's * * Returned Value: * None @@ -1070,7 +1080,8 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, * nwords - the length of data that can be received in the buffer in number * of words. The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's * * Returned Value: * None @@ -1078,7 +1089,8 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, ************************************************************************************/ #ifndef CONFIG_SPI_EXCHANGE -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t nwords) +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, + size_t nwords) { spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); return spi_exchange(dev, NULL, rxbuffer, nwords); @@ -1182,6 +1194,15 @@ FAR struct spi_dev_s *kinetis_spibus_initialize(int port) spi_run(priv, false); + /* Read MCR register and clear MDIS (to Enable module clock) + * It is necessary because to disable RX and TX FIFO the MDIS + * bit should be cleared first. + */ + + regval = spi_getreg(priv, KINETIS_SPI_MCR_OFFSET); + regval &= ~(SPI_MCR_MDIS); + spi_putreg(priv, KINETIS_SPI_MCR_OFFSET, regval); + /* Configure master mode: * Master Mode - Enabled * Continuous SCK - Disabled @@ -1201,9 +1222,10 @@ FAR struct spi_dev_s *kinetis_spibus_initialize(int port) * */ - spi_putreg(priv, KINETIS_SPI_MCR_OFFSET, SPI_MCR_MSTR | SPI_MCR_DCONF_SPI | - SPI_MCR_SMPL_PT_0CLKS | SPI_MCR_PCSIS_MASK | SPI_MCR_HALT| - SPI_MCR_DIS_RXF | SPI_MCR_DIS_TXF); + regval |= SPI_MCR_MSTR | SPI_MCR_DCONF_SPI | SPI_MCR_SMPL_PT_0CLKS | + SPI_MCR_PCSIS_MASK | SPI_MCR_HALT | SPI_MCR_DIS_RXF | + SPI_MCR_DIS_TXF; + spi_putreg(priv, KINETIS_SPI_MCR_OFFSET, regval); /* Set the initial SPI configuration */ From 99c6f96a9c09a69fa7d29c0aa4591780ece7d048 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Wed, 5 Feb 2020 10:58:19 +0900 Subject: [PATCH 15/35] boards: spresense: Add strip option to Make.defs This option is needed to retain symbol tables in elf files Signed-off-by: Masayuki Ishikawa --- boards/arm/cxd56xx/spresense/scripts/Make.defs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/arm/cxd56xx/spresense/scripts/Make.defs b/boards/arm/cxd56xx/spresense/scripts/Make.defs index 01f5b2cdc5b..b2a0fc235ef 100644 --- a/boards/arm/cxd56xx/spresense/scripts/Make.defs +++ b/boards/arm/cxd56xx/spresense/scripts/Make.defs @@ -65,7 +65,7 @@ AR = $(ARCROSSDEV)ar rcs NM = $(ARCROSSDEV)nm OBJCOPY = $(CROSSDEV)objcopy OBJDUMP = $(CROSSDEV)objdump -STRIP = $(CROSSDEV)strip +STRIP = $(CROSSDEV)strip --strip-unneeded MKNXFLAT = mknxflat LDNXFLAT = ldnxflat From d430be293f635746cf46ab1201eac513bfd3cc56 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Wed, 5 Feb 2020 11:03:24 +0900 Subject: [PATCH 16/35] boards: spresense: Add elf configuration NOTE: you need to apply another PR to apps to avoid crash in task test Signed-off-by: Masayuki Ishikawa --- .../cxd56xx/spresense/configs/elf/defconfig | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 boards/arm/cxd56xx/spresense/configs/elf/defconfig diff --git a/boards/arm/cxd56xx/spresense/configs/elf/defconfig b/boards/arm/cxd56xx/spresense/configs/elf/defconfig new file mode 100644 index 00000000000..66bb6f9c567 --- /dev/null +++ b/boards/arm/cxd56xx/spresense/configs/elf/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_CXD56_I2C0_SCUSEQ is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="spresense" +CONFIG_ARCH_BOARD_SPRESENSE=y +CONFIG_ARCH_CHIP="cxd56xx" +CONFIG_ARCH_CHIP_CXD56XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=5434 +CONFIG_BOOT_RUNFROMISRAM=y +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_CXD56_BINARY=y +CONFIG_CXD56_I2C0=y +CONFIG_CXD56_I2C=y +CONFIG_CXD56_SPI4=y +CONFIG_CXD56_SPI5=y +CONFIG_CXD56_SPI=y +CONFIG_ELF=y +CONFIG_EXAMPLES_ELF=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_I2C=y +CONFIG_LIB_BOARDCTL=y +CONFIG_LIB_ENVPATH=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_PATH_INITIAL="/mnt/romfs" +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=1572864 +CONFIG_RAM_START=0x0d000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=4 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2020 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="elf_main" From 3704f0f5cc0d6ca6ca4ae50bd3a15beb7dc25b4e Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Wed, 5 Feb 2020 16:09:02 +0900 Subject: [PATCH 17/35] boards: spresense: Update README.txt Signed-off-by: Masayuki Ishikawa --- boards/arm/cxd56xx/spresense/README.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/boards/arm/cxd56xx/spresense/README.txt b/boards/arm/cxd56xx/spresense/README.txt index 2138fba6325..3e6edae0ab1 100644 --- a/boards/arm/cxd56xx/spresense/README.txt +++ b/boards/arm/cxd56xx/spresense/README.txt @@ -22,6 +22,14 @@ about this board. Configuration sub-directories ----------------------------- + elf + + This is a configuration to test apps/examples/elf. + + posix_spawn + + This is a configuration to test apps/examples/posix_spawn. + smp This is a configuration to run Spresense in SMP mode. To use this From 85617c05fc5e097eb23c5f7d4ac90ca300f79846 Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Wed, 5 Feb 2020 16:22:24 +0900 Subject: [PATCH 18/35] gs2200m: Add a comment to mention the referred document Many of existing comments in this file refer to the document. Like "NOTE: See 3.2.2.3 Annexure - HI Frame Format (From Host)" --- drivers/wireless/gs2200m.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/wireless/gs2200m.c b/drivers/wireless/gs2200m.c index bea69b6385d..7c89ea21f3d 100644 --- a/drivers/wireless/gs2200m.c +++ b/drivers/wireless/gs2200m.c @@ -33,6 +33,14 @@ * ****************************************************************************/ +/**************************************************************************** + * gs2200m driver. + * + * See "GS2200MS2W Adapter Command Reference Guide" for the explanation + * of AT commands. You can find the document at: + * https://www.telit.com/m2m-iot-products/wifi-bluetooth-modules/wi-fi-gs2200m/ + ****************************************************************************/ + /**************************************************************************** * Included Files ****************************************************************************/ From 2984fb960223430111ad75acccdabe0380a23be7 Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Mon, 3 Feb 2020 15:25:43 +0900 Subject: [PATCH 19/35] sim: Add -fno-common to ARCHCPUFLAGS It seems that "ld -r" on macOS doesn't include objects from libraries for common symbols. Because of that, sim build ends up with undefined references to globals like g_binfmts and g_mmheap. --- boards/sim/sim/sim/configs/cxxtest/Make.defs | 5 +++++ boards/sim/sim/sim/configs/nsh2/Make.defs | 5 +++++ boards/sim/sim/sim/scripts/Make.defs | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/boards/sim/sim/sim/configs/cxxtest/Make.defs b/boards/sim/sim/sim/configs/cxxtest/Make.defs index 53fe2d56dc4..47f169a7493 100644 --- a/boards/sim/sim/sim/configs/cxxtest/Make.defs +++ b/boards/sim/sim/sim/configs/cxxtest/Make.defs @@ -60,6 +60,11 @@ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include ARCHINCLUDESXX = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx -isystem $(TOPDIR)/include/uClibc++ ARCHSCRIPT = +# Add -fno-common because macOS "ld -r" doesn't seem to pick objects +# for common symbols. +ARCHCPUFLAGS += -fno-common +ARCHCPUFLAGSXX += -fno-common + ifeq ($(CONFIG_SIM_M32),y) ARCHCPUFLAGS += -m32 ARCHCPUFLAGSXX += -m32 diff --git a/boards/sim/sim/sim/configs/nsh2/Make.defs b/boards/sim/sim/sim/configs/nsh2/Make.defs index b00ada0bfbc..680efd6df75 100644 --- a/boards/sim/sim/sim/configs/nsh2/Make.defs +++ b/boards/sim/sim/sim/configs/nsh2/Make.defs @@ -57,6 +57,11 @@ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include ARCHINCLUDESXX = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx ARCHSCRIPT = +# Add -fno-common because macOS "ld -r" doesn't seem to pick objects +# for common symbols. +ARCHCPUFLAGS += -fno-common +ARCHCPUFLAGSXX += -fno-common + ifeq ($(CONFIG_SIM_M32),y) ARCHCPUFLAGS += -m32 ARCHCPUFLAGSXX += -m32 diff --git a/boards/sim/sim/sim/scripts/Make.defs b/boards/sim/sim/sim/scripts/Make.defs index 9eb3d13c2ea..b1fca660d4d 100644 --- a/boards/sim/sim/sim/scripts/Make.defs +++ b/boards/sim/sim/sim/scripts/Make.defs @@ -63,6 +63,11 @@ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include ARCHINCLUDESXX = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx ARCHSCRIPT = +# Add -fno-common because macOS "ld -r" doesn't seem to pick objects +# for common symbols. +ARCHCPUFLAGS += -fno-common +ARCHCPUFLAGSXX += -fno-common + ifeq ($(CONFIG_SIM_M32),y) ARCHCPUFLAGS += -m32 ARCHCPUFLAGSXX += -m32 From 342b56ae8b1adc8dff69115d3d4937e7de2ce03d Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Mon, 3 Feb 2020 14:18:17 +0900 Subject: [PATCH 20/35] Revert "A workaround for macOS linker" Unnecessary after "sim: Add -fno-common to KERNEL ARCHCPUFLAGS" This reverts commit cc90d586c09770770d047c8d3a45ab1db35c58f4. --- binfmt/binfmt_globals.c | 2 +- mm/umm_heap/umm_globals.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/binfmt/binfmt_globals.c b/binfmt/binfmt_globals.c index 94f98f13d49..ea01ab025b2 100644 --- a/binfmt/binfmt_globals.c +++ b/binfmt/binfmt_globals.c @@ -56,7 +56,7 @@ * protection to simply disable pre-emption when accessing this list. */ -FAR struct binfmt_s *g_binfmts = NULL; +FAR struct binfmt_s *g_binfmts; /**************************************************************************** * Private Functions diff --git a/mm/umm_heap/umm_globals.c b/mm/umm_heap/umm_globals.c index a00ce3c4ec6..012aac76315 100644 --- a/mm/umm_heap/umm_globals.c +++ b/mm/umm_heap/umm_globals.c @@ -64,5 +64,5 @@ #else /* Otherwise, the user heap data structures are in common .bss */ -struct mm_heap_s g_mmheap = {}; +struct mm_heap_s g_mmheap; #endif From a5bb9f7660ef02f52d26cd932aabcd26d45f7aee Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Wed, 5 Feb 2020 20:00:29 +0900 Subject: [PATCH 21/35] boards: maix-bit: Adjust CONFIG_BOARD_LOOPSPERMSEC Also, remove CONFIG_NSH_FILEIOSIZE setting --- boards/risc-v/k210/maix-bit/configs/nsh/defconfig | 3 +-- boards/risc-v/k210/maix-bit/configs/smp/defconfig | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/boards/risc-v/k210/maix-bit/configs/nsh/defconfig b/boards/risc-v/k210/maix-bit/configs/nsh/defconfig index 41e912783a1..9c2d0747f93 100644 --- a/boards/risc-v/k210/maix-bit/configs/nsh/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BINFMT_DISABLE=y -CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BOARD_LOOPSPERMSEC=46000 CONFIG_BUILTIN=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y @@ -37,7 +37,6 @@ CONFIG_NSH_DISABLE_MKDIR=y CONFIG_NSH_DISABLE_RM=y CONFIG_NSH_DISABLE_RMDIR=y CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_FILEIOSIZE=64 CONFIG_NSH_READLINE=y CONFIG_NSH_STRERROR=y CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/risc-v/k210/maix-bit/configs/smp/defconfig b/boards/risc-v/k210/maix-bit/configs/smp/defconfig index ea3ecde537d..4d91102afe9 100644 --- a/boards/risc-v/k210/maix-bit/configs/smp/defconfig +++ b/boards/risc-v/k210/maix-bit/configs/smp/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BINFMT_DISABLE=y -CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BOARD_LOOPSPERMSEC=46000 CONFIG_BUILTIN=y CONFIG_BUILTIN_PROXY_STACKSIZE=2048 CONFIG_DEBUG_FULLOPT=y @@ -40,7 +40,6 @@ CONFIG_NSH_DISABLE_MKDIR=y CONFIG_NSH_DISABLE_RM=y CONFIG_NSH_DISABLE_RMDIR=y CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_FILEIOSIZE=64 CONFIG_NSH_READLINE=y CONFIG_NSH_STRERROR=y CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 From d4e5736712aa97db859798049af3b185d82adae4 Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Wed, 5 Feb 2020 18:32:33 -0300 Subject: [PATCH 22/35] Improvements to gs2200m gs2200m: Make CHECK_VERSION use Kconfig gs2200m: Add a config to set log level --- drivers/wireless/Kconfig | 11 +++++++++++ drivers/wireless/gs2200m.c | 26 ++++++++++++++++++++++++-- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/wireless/Kconfig b/drivers/wireless/Kconfig index 2490a40c4e7..299b6648e9f 100644 --- a/drivers/wireless/Kconfig +++ b/drivers/wireless/Kconfig @@ -40,6 +40,17 @@ config WL_GS2200M_DISABLE_DHCPC bool "Disable the internal dhcp client" default n +config WL_GS2200M_CHECK_VERSION + bool "Check the version of GS2200M" + default n + +config WL_GS2200M_LOGLEVEL + int "Log level" + default 0 + range 0 2 + ---help--- + The debug level of GS2200M. (AT+LOGLVL) + endif source drivers/wireless/spirit/Kconfig diff --git a/drivers/wireless/gs2200m.c b/drivers/wireless/gs2200m.c index 7c89ea21f3d..297d925deb1 100644 --- a/drivers/wireless/gs2200m.c +++ b/drivers/wireless/gs2200m.c @@ -1966,11 +1966,27 @@ static enum pkt_type_e gs2200m_set_gpio(FAR struct gs2200m_dev_s *dev, } #endif +/**************************************************************************** + * Name: gs2200m_set_loglevel + * NOTE: See 11.3.1 Log Level + ****************************************************************************/ + +#if CONFIG_WL_GS2200M_LOGLEVEL > 0 +static enum pkt_type_e gs2200m_set_loglevel(FAR struct gs2200m_dev_s *dev, + int level) +{ + char cmd[16]; + + snprintf(cmd, sizeof(cmd), "AT+LOGLVL=%d\r\n", level); + return gs2200m_send_cmd(dev, cmd, NULL); +} +#endif + /**************************************************************************** * Name: gs2200m_get_version ****************************************************************************/ -#ifdef CHECK_VERSION +#ifdef CONFIG_WL_GS2200M_CHECK_VERSION static enum pkt_type_e gs2200m_get_version(FAR struct gs2200m_dev_s *dev) { char cmd[16]; @@ -2875,7 +2891,13 @@ static int gs2200m_start(FAR struct gs2200m_dev_s *dev) t = gs2200m_enable_echo(dev, 0); ASSERT(TYPE_OK == t); -#ifdef CHECK_VERSION +#if CONFIG_WL_GS2200M_LOGLEVEL > 0 + /* Set log level */ + t = gs2200m_set_loglevel(dev, CONFIG_WL_GS2200M_LOGLEVEL); + ASSERT(TYPE_OK == t); +#endif + +#ifdef CONFIG_WL_GS2200M_CHECK_VERSION /* Version */ t = gs2200m_get_version(dev); From bc00f6e444e61aa3d85c7cd231728dca6301a3c3 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Wed, 5 Feb 2020 22:38:04 +0000 Subject: [PATCH 23/35] arch/arm/src/stm32f010g0: Add memorymap and pimmap support for the STM32F030RC --- arch/arm/include/stm32f0l0g0/chip.h | 21 +- .../stm32f0l0g0/hardware/stm32_memorymap.h | 7 +- .../src/stm32f0l0g0/hardware/stm32_pinmap.h | 4 +- .../hardware/stm32f03x_memorymap.h | 152 +++++++++++ .../stm32f0l0g0/hardware/stm32f03x_pinmap.h | 256 ++++++++++++++++++ 5 files changed, 436 insertions(+), 4 deletions(-) create mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h create mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h diff --git a/arch/arm/include/stm32f0l0g0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h index 72336a2916b..6c9b9799d0c 100644 --- a/arch/arm/include/stm32f0l0g0/chip.h +++ b/arch/arm/include/stm32f0l0g0/chip.h @@ -50,7 +50,26 @@ /* Get customizations for each supported chip */ -#if defined(CONFIG_ARCH_CHIP_STM32F051R8) +#if defined(CONFIG_ARCH_CHIP_STM32F030RC) + +# define STM32_FLASH_SIZE (256*1024) /* 256Kb */ +# define STM32_SRAM_SIZE (32*1024) /* 32Kb */ + +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 0 /* No I2S modules */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 6 /* Six USARTs modules */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NUSBDEV 0 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* One DAC channel */ +# define STM32_NCOMP 0 /* Two Analog Comparators */ +# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */ +# define STM32_NPORTS 5 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F051R8) # define STM32_FLASH_SIZE (64*1024) /* 64Kb */ # define STM32_SRAM_SIZE (8*1024) /* 8Kb */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h index ca15936ce27..a24b5b34927 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h @@ -44,8 +44,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_STM32F05X) || defined(CONFIG_STM32F0L0G0_STM32F07X) || \ - defined(CONFIG_STM32F0L0G0_STM32F09X) +#if defined(CONFIG_STM32F0L0G0_STM32F03X) +# include "hardware/stm32f03x_memorymap.h" +#elif defined(CONFIG_STM32F0L0G0_STM32F05X) || \ + defined(CONFIG_STM32F0L0G0_STM32F07X) || \ + defined(CONFIG_STM32F0L0G0_STM32F09X) # include "hardware/stm32f05xf07xf09x_memorymap.h" #elif defined(CONFIG_ARCH_CHIP_STM32L0) # include "hardware/stm32l0_memorymap.h" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h index 63270d7cbbe..86aaeecb600 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h @@ -43,7 +43,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_STM32F05X) +#if defined(CONFIG_STM32F0L0G0_STM32F03X) +# include "hardware/stm32f03x_pinmap.h" +#elif defined(CONFIG_STM32F0L0G0_STM32F05X) # include "hardware/stm32f05x_pinmap.h" #elif defined(CONFIG_STM32F0L0G0_STM32F07X) # include "hardware/stm32f07x_pinmap.h" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h new file mode 100644 index 00000000000..8a4ce2b0ae0 --- /dev/null +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h @@ -0,0 +1,152 @@ +/************************************************************************************ + * arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* ST32F05XF07X Address Blocks ******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ + /* 0x60000000-0xdfffffff: Reserved */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) + +/* Code Base Addresses **************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ + /* 0x00100000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ + /* 0x08100000-0x0fffffff: Reserved */ +#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */ + /* 0x10010000-0x1ffeffff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */ + /* 0x1fff7a10-0x1fff7fff: Reserved */ +#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */ + /* 0x1fffc008-0x1fffffff: Reserved */ + +/* System Memory Addresses **********************************************************/ + +#define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of + * the device Flash memory expressed in + * Kbytes. Example: 0x040 corresponds + * to 64 Kbytes + */ + +/* Peripheral Base Addresses ********************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */ + /* 0x4000a000-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */ + /* 0x40016c00-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x4007ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */ + /* 0x48001800-0x4fffFfff: Reserved */ +#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */ + +/* APB1 Base Addresses **************************************************************/ + + /* 0x40000000-0x400003ff Reserved */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ +#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ +#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */ +#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */ +#define STM32_USART5_BASE 0x40005000 /* 0x40005000-0x400053ff USART5 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */ +#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */ + /* 0x40005c00-0x40005fff Reserved */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ + /* 0x40007400-0x400077ff Reserved */ + +/* APB2 Base Addresses **************************************************************/ + +#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */ +#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */ +#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff USART6 */ +#define STM32_USART7_BASE 0x40011800 /* 0x40011800-0x40011bff USART7 */ +#define STM32_USART8_BASE 0x40011c00 /* 0x40011c00-0x40011fff USART8 */ +#define STM32_ADC12_BASE 0x40012400 /* 0x40012400-0x400127ff ADC 12 */ +#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ +#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ +#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ +#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */ +#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */ +#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */ + +/* AHB1 Base Addresses **************************************************************/ + +#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ + /* 0x40020400-0x400207ff: Reserved */ +#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ + /* 0x40024000-0x400243ff: Reserved */ + +/* AHB2 Base Addresses **************************************************************/ + +#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ +#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ +#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */ +#define STM32_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ + /* 0x48001000-0x480013ff: Reserved */ +#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ + +/* Cortex-M4 Base Addresses *********************************************************/ +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this + * address range + */ + +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 + +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h new file mode 100644 index 00000000000..598a2f850e6 --- /dev/null +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h @@ -0,0 +1,256 @@ +/************************************************************************************ + * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h + * + * Copyright (C) 2020 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "stm32_gpio.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * CAN1_RX connects vis PD0 on some board, then the following definition should + * appear inthe board.h header file for that board: + * + * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 + * + * The driver will then automatically configure PD0 as the CAN1 RX pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* ADC 1 */ + +#define GPIO_ADC1_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_ADC1_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_ADC1_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) +#define GPIO_ADC1_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_ADC1_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_ADC1_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_ADC1_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) +#define GPIO_ADC1_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) +#define GPIO_ADC1_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) +#define GPIO_ADC1_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) +#define GPIO_ADC1_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) +#define GPIO_ADC1_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) + +/* Events */ + +#define GPIO_EVENTOUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_EVENTOUT_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_EVENTOUT_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_EVENTOUT_4 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_EVENTOUT_5 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN11) +#define GPIO_EVENTOUT_6 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN0) +#define GPIO_EVENTOUT_7 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN1) +#define GPIO_EVENTOUT_8 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN2) +#define GPIO_EVENTOUT_9 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN3) +#define GPIO_EVENTOUT_10 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN4) +#define GPIO_EVENTOUT_11 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN4) +#define GPIO_EVENTOUT_12 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN5) +#define GPIO_EVENTOUT_13 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN12) +#define GPIO_EVENTOUT_14 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_EVENTOUT_15 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_EVENTOUT_16 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_EVENTOUT_17 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_EVENTOUT_18 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_EVENTOUT_19 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_EVENTOUT_20 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN7) + +/* I2C */ + +#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN6) +#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN8) +#define GPIO_I2C1_SCL_3 (GPIO_ALT | GPIO_AF0 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTF | GPIO_PIN6) +#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN7) +#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN9) +#define GPIO_I2C1_SDA_3 (GPIO_ALT | GPIO_AF0 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTF | GPIO_PIN7) +#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF3 | GPIO_FLOAT | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN5) + +#define GPIO_I2C2_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10) +#define GPIO_I2C2_SCL_2 (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN13) +#define GPIO_I2C2_SCL_3 (GPIO_ALT | GPIO_AF0 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTF | GPIO_PIN6) +#define GPIO_I2C2_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11) +#define GPIO_I2C2_SDA_2 (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN14) +#define GPIO_I2C2_SDA_3 (GPIO_ALT | GPIO_AF0 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTF | GPIO_PIN7) + +/* IR */ + +#define GPIO_IR_OUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_IR_OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN13) + +/* Clock output */ + +#define GPIO_MCO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN8) + +/* SPI */ + +#define GPIO_SPI1_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_SPI1_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_SPI1_MOSI_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_SPI1_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_SPI1_NSS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_SPI1_SCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN5) +#define GPIO_SPI1_SCK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3) + +#define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN14) +#define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN2) +#define GPIO_SPI2_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15) +#define GPIO_SPI2_MOSI_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3) +#define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN12) +#define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_SPI2_SCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_SPI2_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN10) + +/* SWD */ + +#define GPIO_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14) +#define GPIO_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13) + +/* Timers */ + +#define GPIO_TIM1_BKIN_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM1_BKIN_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN12) +#define GPIO_TIM1_CH1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_TIM1_CH1N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_TIM1_CH2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM1_CH2N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM1_CH2N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN14) +#define GPIO_TIM1_CH3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TIM1_CH3N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_TIM1_CH3N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN15) +#define GPIO_TIM1_CH4 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_TIM1_ETR (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN12) + +#define GPIO_TIM3_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN6) +#define GPIO_TIM3_CH1_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM3_CH1_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM3_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN7) +#define GPIO_TIM3_CH2_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM3_CH2_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM3_CH3_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN8) +#define GPIO_TIM3_CH3_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM3_CH4_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN9) +#define GPIO_TIM3_CH4_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_TIM3_ETR (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN2) + +#define GPIO_TIM14_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_TIM14_CH1_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_TIM14_CH1_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN7) + +#define GPIO_TIM15_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM15_BKIN_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12) +#define GPIO_TIM15_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN2) +#define GPIO_TIM15_CH1_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN14) +#define GPIO_TIM15_CH1N_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN15) +#define GPIO_TIM15_CH1N_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_TIM15_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN3) +#define GPIO_TIM15_CH2_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN15) + +#define GPIO_TIM16_BKIN (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM16_CH1_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_TIM16_CH1_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM16_CH1N (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN6) + +#define GPIO_TIM17_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TIM17_BKIN_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM17_CH1_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_TIM17_CH1_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM17_CH1N (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7) + +/* USARTs */ + +#define GPIO_USART1_CK (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_USART1_CTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_USART1_RTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN9) + +#define GPIO_USART2_CK (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_USART2_CTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN0) +#define GPIO_USART2_RTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN3) +#define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14) +#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN2) + +#define GPIO_USART3_CK_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN12) +#define GPIO_USART3_CK_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_USART3_CTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_USART3_CTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_USART3_RTS_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN2) +#define GPIO_USART3_RTS_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_USART3_RTS_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN12) +#define GPIO_USART3_RTS_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN14) +#define GPIO_USART3_RX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN5) +#define GPIO_USART3_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN11) +#define GPIO_USART3_RX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN11) +#define GPIO_USART3_TX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN4) +#define GPIO_USART3_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN10) +#define GPIO_USART3_TX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN10) + +#define GPIO_USART4_CK (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN12) +#define GPIO_USART4_CTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_USART4_RTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_USART4_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN11) +#define GPIO_USART4_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10) +#define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN0) + +#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H */ From 729af004c0754a75ebb49c1000530c5f1b7e6efe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beat=20K=C3=BCng?= Date: Wed, 5 Feb 2020 08:35:32 +0100 Subject: [PATCH 24/35] fix stm32_spibus_initialize: ensure leave_critical_section is called in case the requested SPI bus is invalid or not configured. --- arch/arm/src/stm32/stm32_spi.c | 1 - arch/arm/src/stm32f0l0g0/stm32_spi.c | 1 - arch/arm/src/stm32f7/stm32_spi.c | 1 - arch/arm/src/stm32h7/stm32_spi.c | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c index 8a636f4d2f9..c2cb1d81db6 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/stm32/stm32_spi.c @@ -2120,7 +2120,6 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus) #endif { spierr("ERROR: Unsupported SPI bus: %d\n", bus); - return NULL; } leave_critical_section(flags); diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c index fb782f19ab2..2e728e6ee2d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c @@ -1778,7 +1778,6 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus) #endif { spierr("ERROR: Unsupported SPI bus: %d\n", bus); - return NULL; } leave_critical_section(flags); diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index 8fbbaa23f97..bc8bb0875aa 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -2178,7 +2178,6 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus) #endif { spierr("ERROR: Unsupported SPI bus: %d\n", bus); - return NULL; } leave_critical_section(flags); diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c index c1b9026b09a..b84ed1c72df 100644 --- a/arch/arm/src/stm32h7/stm32_spi.c +++ b/arch/arm/src/stm32h7/stm32_spi.c @@ -2279,7 +2279,6 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus) #endif { spierr("ERROR: Unsupported SPI bus: %d\n", bus); - return NULL; } leave_critical_section(flags); From 542df2f80a1b07effa99d09dd6b46f8c6b3ba9a9 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 6 Feb 2020 11:35:42 +0900 Subject: [PATCH 25/35] boards: spresense: Fix LDMODULEFLAGS in Make.defs Signed-off-by: Masayuki Ishikawa --- boards/arm/cxd56xx/spresense/scripts/Make.defs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/arm/cxd56xx/spresense/scripts/Make.defs b/boards/arm/cxd56xx/spresense/scripts/Make.defs index b2a0fc235ef..92b2f92b218 100644 --- a/boards/arm/cxd56xx/spresense/scripts/Make.defs +++ b/boards/arm/cxd56xx/spresense/scripts/Make.defs @@ -105,9 +105,9 @@ CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs LDMODULEFLAGS = -r -e module_initialize ifeq ($(WINTOOL),y) - LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/sched/module/gnu-elf.ld}" + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" else - LDMODULEFLAGS += -T $(TOPDIR)/sched/module/gnu-elf.ld + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld endif # ELF module definitions From c19ac7da25f56ca52536482c0bd162dcd11d03c2 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 6 Feb 2020 11:37:49 +0900 Subject: [PATCH 26/35] boards: spresense: Add module configuration Signed-off-by: Masayuki Ishikawa --- .../spresense/configs/module/defconfig | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 boards/arm/cxd56xx/spresense/configs/module/defconfig diff --git a/boards/arm/cxd56xx/spresense/configs/module/defconfig b/boards/arm/cxd56xx/spresense/configs/module/defconfig new file mode 100644 index 00000000000..a03b4a85500 --- /dev/null +++ b/boards/arm/cxd56xx/spresense/configs/module/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_CXD56_I2C0_SCUSEQ is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="spresense" +CONFIG_ARCH_BOARD_SPRESENSE=y +CONFIG_ARCH_CHIP="cxd56xx" +CONFIG_ARCH_CHIP_CXD56XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=5434 +CONFIG_BOOT_RUNFROMISRAM=y +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_CXD56_BINARY=y +CONFIG_CXD56_I2C0=y +CONFIG_CXD56_I2C=y +CONFIG_CXD56_SPI4=y +CONFIG_CXD56_SPI5=y +CONFIG_CXD56_SPI=y +CONFIG_ELF=y +CONFIG_EXAMPLES_MODULE=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_I2C=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIB_BOARDCTL=y +CONFIG_LIB_ENVPATH=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MODULE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_PATH_INITIAL="/mnt/romfs" +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=1572864 +CONFIG_RAM_START=0x0d000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2020 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="module_main" From edb38ee53a2128df5259119b1081c4ce1a928fc9 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 6 Feb 2020 11:41:17 +0900 Subject: [PATCH 27/35] boards: spresense: Update README.txt Signed-off-by: Masayuki Ishikawa --- boards/arm/cxd56xx/spresense/README.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/boards/arm/cxd56xx/spresense/README.txt b/boards/arm/cxd56xx/spresense/README.txt index 3e6edae0ab1..74625e26f77 100644 --- a/boards/arm/cxd56xx/spresense/README.txt +++ b/boards/arm/cxd56xx/spresense/README.txt @@ -26,6 +26,10 @@ Configuration sub-directories This is a configuration to test apps/examples/elf. + module + + This is a configuration to test apps/examples/module. + posix_spawn This is a configuration to test apps/examples/posix_spawn. From afd03f5a7efbccb5115494ede005c6ae7f22353b Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Thu, 6 Feb 2020 16:16:53 +0900 Subject: [PATCH 28/35] sethost: If no host options are specified, try to guess --- tools/sethost.sh | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/tools/sethost.sh b/tools/sethost.sh index 2983095dd89..28baf587aaa 100755 --- a/tools/sethost.sh +++ b/tools/sethost.sh @@ -34,8 +34,8 @@ progname=$0 debug=n -host=linux -wenv=cygwin +host= +wenv= unset configfile function showusage { @@ -94,6 +94,32 @@ while [ ! -z "$1" ]; do shift done +# If the host was not explicitly given, try to guess. +# Examples of "uname -s" outputs: +# macOS: Darwin +# Cygwin: CYGWIN_NT-10.0-WOW +# Linux: Linux +# MSYS: MINGW32_NT-6.2 +if [ -z "$host" ]; then + case $(uname -s) in + Darwin) + host=macos + ;; + CYGWIN*) + host=windows + wenv=cygwin + ;; + MINGW32*) + host=windows + wenv=msys + ;; + *) + # Assume linux as a fallback + host=linux + ;; + esac +fi + if [ ! -z "$1" ]; then echo "ERROR: Garbage at the end of line" showusage From ac2aec96e066862192781de5054c7e227afa4567 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Thu, 6 Feb 2020 12:21:22 +0800 Subject: [PATCH 29/35] Refine Kconfig under drivers folder 1.Move subsystem config into sub folder 2.Remove the duplicated if/endif Change-Id: I0b96ac0570ee1ba62bbb95586381f5410b90bcf0 Signed-off-by: Xiang Xiao --- drivers/1wire/Kconfig | 4 --- drivers/Kconfig | 54 +++++++------------------------------ drivers/can/Kconfig | 3 --- drivers/contactless/Kconfig | 3 --- drivers/eeprom/Kconfig | 3 --- drivers/i2c/Kconfig | 6 ++--- drivers/mmcsd/Kconfig | 16 +++++++++++ drivers/rptun/Kconfig | 4 --- drivers/spi/Kconfig | 24 ++++++++--------- drivers/timers/Kconfig | 8 ++++++ drivers/usbmonitor/Kconfig | 1 - drivers/video/Kconfig | 16 +++++++++++ drivers/wireless/Kconfig | 4 --- 13 files changed, 64 insertions(+), 82 deletions(-) diff --git a/drivers/1wire/Kconfig b/drivers/1wire/Kconfig index c79af85d2e4..789ad09652e 100644 --- a/drivers/1wire/Kconfig +++ b/drivers/1wire/Kconfig @@ -3,13 +3,9 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if 1WIRE - config 1WIRE_DS28E17 bool "DS28E17 1-wire to I2C converter" default n depends on I2C ---help--- Enable support for the Maxim DS28E17 1-wire to I2C converter - -endif # 1WIRE diff --git a/drivers/Kconfig b/drivers/Kconfig index ab581fdf96e..66e6e2e4ff2 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -15,9 +15,6 @@ config DEV_ZERO bool "Enable /dev/zero" default n -source drivers/crypto/Kconfig -source drivers/loop/Kconfig - config DRVR_MKRD bool "RAM disk wrapper (mkrd)" default n @@ -77,6 +74,9 @@ endif # DRVR_WRITEBUFFER || DRVR_READAHEAD endmenu # Buffering +source drivers/crypto/Kconfig +source drivers/loop/Kconfig + menuconfig CAN bool "CAN Driver Support" default n @@ -88,18 +88,6 @@ if CAN source drivers/can/Kconfig endif -config ARCH_HAVE_PWM_PULSECOUNT - bool - default n - -config ARCH_HAVE_PWM_MULTICHAN - bool - default n - -config ARCH_HAVE_I2CRESET - bool - default n - menuconfig I2C bool "I2C Driver Support" default n @@ -155,20 +143,6 @@ if DRIVERS_AUDIO source drivers/audio/Kconfig endif # DRIVERS_AUDIO -config FB_CMAP - bool - default n - ---help--- - Set by driver-specific configuration to indicate support for color - mapping. Not directly user selectable. - -config FB_TRANSPARENCY - bool - default n - ---help--- - Set by driver-specific configuration to indicate support for color - transparency. Not directly user selectable. - menuconfig DRIVERS_VIDEO bool "Video Device Support" default n @@ -210,22 +184,6 @@ source drivers/leds/Kconfig # MMC/SD-related platform capabilities -config ARCH_HAVE_SDIO - bool - default n - -config ARCH_HAVE_SDIOWAIT_WRCOMPLETE - bool - default n - -config ARCH_HAVE_SDIO_PREFLIGHT - bool - default n - -config ARCH_HAVE_SDIO_DELAYED_INVLDT - bool - default n - menuconfig MMCSD bool "MMC/SD Driver Support" default n @@ -395,7 +353,9 @@ menuconfig DRIVERS_WIRELESS ---help--- Drivers for various wireless devices. +if DRIVERS_WIRELESS source drivers/wireless/Kconfig +endif # DRIVERS_WIRELESS menuconfig DRIVERS_CONTACTLESS bool "Contactless Device Support" @@ -403,7 +363,9 @@ menuconfig DRIVERS_CONTACTLESS ---help--- Drivers for various contactless devices. +if DRIVERS_CONTACTLESS source drivers/contactless/Kconfig +endif # DRIVERS_CONTACTLESS menuconfig 1WIRE bool "1wire Device Support" @@ -411,7 +373,9 @@ menuconfig 1WIRE ---help--- Drivers for various 1wire devices. +if 1WIRE source drivers/1wire/Kconfig +endif # 1WIRE source drivers/syslog/Kconfig diff --git a/drivers/can/Kconfig b/drivers/can/Kconfig index d539b29bb7e..ec3ba046c1c 100644 --- a/drivers/can/Kconfig +++ b/drivers/can/Kconfig @@ -3,8 +3,6 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if CAN - config CAN_EXTID bool "CAN extended IDs" default n @@ -179,4 +177,3 @@ config MCP2515_SPI_SCK_FREQUENCY range 100000 10000000 endif # CAN_MCP2515 -endif # CAN diff --git a/drivers/contactless/Kconfig b/drivers/contactless/Kconfig index 68af4b9d790..89ccbec0a4e 100644 --- a/drivers/contactless/Kconfig +++ b/drivers/contactless/Kconfig @@ -3,8 +3,6 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if DRIVERS_CONTACTLESS - config CL_MFRC522 bool "NXP MFRC522 ISO14443/Mifare Transceiver" default n @@ -56,4 +54,3 @@ config CL_PN532_DEBUG_RX depends on DEBUG_CONTACTLESS endif # CL_PN532 -endif # DRIVERS_CONTACTLESS diff --git a/drivers/eeprom/Kconfig b/drivers/eeprom/Kconfig index d7110d44b43..c7f1b90bc7f 100644 --- a/drivers/eeprom/Kconfig +++ b/drivers/eeprom/Kconfig @@ -3,7 +3,6 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if EEPROM config SPI_EE_25XX bool "Microchip 25xxNNN / Atmel AT25NNN / ST M95NNN SPI EEPROM devices" default n @@ -51,5 +50,3 @@ config AT24CS_UUID This option registers a char device driver with the ".uuid" suffix. endif # I2C_EE_24XX - -endif # EEPROM diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index cdfd124ce61..1fcb75c9769 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -3,7 +3,9 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if I2C +config ARCH_HAVE_I2CRESET + bool + default n config I2C_SLAVE bool "I2C Slave" @@ -48,5 +50,3 @@ config I2CMULTIPLEXER_PCA9540BDP # put more i2c mux devices here endmenu # I2C Multiplexer Support - -endif # I2C diff --git a/drivers/mmcsd/Kconfig b/drivers/mmcsd/Kconfig index 307b7a0208b..bf9d9374912 100644 --- a/drivers/mmcsd/Kconfig +++ b/drivers/mmcsd/Kconfig @@ -3,6 +3,22 @@ # see the file kconfig-language.txt in the NuttX tools repository. # +config ARCH_HAVE_SDIO + bool + default n + +config ARCH_HAVE_SDIOWAIT_WRCOMPLETE + bool + default n + +config ARCH_HAVE_SDIO_PREFLIGHT + bool + default n + +config ARCH_HAVE_SDIO_DELAYED_INVLDT + bool + default n + config MMCSD_NSLOTS int "Number of MMC/SD slots" default 1 diff --git a/drivers/rptun/Kconfig b/drivers/rptun/Kconfig index a640e73755b..31bd62bc514 100644 --- a/drivers/rptun/Kconfig +++ b/drivers/rptun/Kconfig @@ -3,8 +3,6 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if RPTUN - config RPTUN_PRIORITY int "rpturn thread priority" default 224 @@ -12,5 +10,3 @@ config RPTUN_PRIORITY config RPTUN_STACKSIZE int "rptun stack size" default 2048 - -endif diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 50210bf4406..8724e95ad28 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -3,18 +3,6 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -config ARCH_HAVE_SPI_CRCGENERATION - bool - default n - -config ARCH_HAVE_SPI_CS_CONTROL - bool - default n - -config ARCH_HAVE_SPI_BITORDER - bool - default n - menuconfig SPI bool "SPI Driver Support" default n @@ -25,6 +13,18 @@ menuconfig SPI if SPI +config ARCH_HAVE_SPI_CRCGENERATION +bool +default n + +config ARCH_HAVE_SPI_CS_CONTROL +bool +default n + +config ARCH_HAVE_SPI_BITORDER +bool +default n + config SPI_SLAVE bool "SPI slave" default n diff --git a/drivers/timers/Kconfig b/drivers/timers/Kconfig index 82ad5440975..c1ef786db65 100644 --- a/drivers/timers/Kconfig +++ b/drivers/timers/Kconfig @@ -14,6 +14,14 @@ config PWM if PWM +config ARCH_HAVE_PWM_PULSECOUNT + bool + default n + +config ARCH_HAVE_PWM_MULTICHAN + bool + default n + config PWM_PULSECOUNT bool "PWM Pulse Count Support" default n diff --git a/drivers/usbmonitor/Kconfig b/drivers/usbmonitor/Kconfig index 69862378e80..25ace5e7d82 100644 --- a/drivers/usbmonitor/Kconfig +++ b/drivers/usbmonitor/Kconfig @@ -3,7 +3,6 @@ # see the file kconfig-language.txt in the NuttX tools repository. # - config USBMONITOR_STACKSIZE int "USB Monitor daemon stack size" default 2048 diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index ce868ca6968..fe240b43747 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -7,6 +7,22 @@ config VIDEO_FB bool "Framebuffer character driver" default n +config FB_CMAP + bool + depends on VIDEO_FB + default n + ---help--- + Set by driver-specific configuration to indicate support for color + mapping. Not directly user selectable. + +config FB_TRANSPARENCY + bool + depends on VIDEO_FB + default n + ---help--- + Set by driver-specific configuration to indicate support for color + transparency. Not directly user selectable. + config FB_SYNC bool "Hardware signals vertical sync" depends on VIDEO_FB diff --git a/drivers/wireless/Kconfig b/drivers/wireless/Kconfig index 299b6648e9f..36c170462e3 100644 --- a/drivers/wireless/Kconfig +++ b/drivers/wireless/Kconfig @@ -3,8 +3,6 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if DRIVERS_WIRELESS - config WL_CC1101 bool "CC1101 RF transceiver support" default n @@ -134,5 +132,3 @@ config WL_NRF24L01_RXFIFO_LEN endif # WL_NRF24L01_RXSUPPORT endif # WL_NRF24L01 - -endif # DRIVERS_WIRELESS From 7f91a737ea57818df6f08f2758fcda018af844b7 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Thu, 6 Feb 2020 17:40:05 +0000 Subject: [PATCH 30/35] arch/arm/include/stm32f010g0/chip.h: Add support for STM32F030CC --- arch/arm/include/stm32f0l0g0/chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/stm32f0l0g0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h index 6c9b9799d0c..5682c9adc83 100644 --- a/arch/arm/include/stm32f0l0g0/chip.h +++ b/arch/arm/include/stm32f0l0g0/chip.h @@ -50,7 +50,7 @@ /* Get customizations for each supported chip */ -#if defined(CONFIG_ARCH_CHIP_STM32F030RC) +#if defined(CONFIG_ARCH_CHIP_STM32F030RC || CONFIG_ARCH_CHIP_STM32F030CC) # define STM32_FLASH_SIZE (256*1024) /* 256Kb */ # define STM32_SRAM_SIZE (32*1024) /* 32Kb */ From 486a05ed708dc0aaf8a68364d971328b0eb765e0 Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Fri, 7 Feb 2020 11:06:03 +0900 Subject: [PATCH 31/35] getopt: Fix a typo in a comment --- libs/libc/unistd/lib_getopt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libc/unistd/lib_getopt.c b/libs/libc/unistd/lib_getopt.c index 4c02284707e..e52bfd28d73 100644 --- a/libs/libc/unistd/lib_getopt.c +++ b/libs/libc/unistd/lib_getopt.c @@ -106,7 +106,7 @@ static bool g_binitialized = false; * * Returned Value: * If an option was successfully found, then getopt() returns the option - * haracter. If all command-line options have been parsed, then getopt() + * character. If all command-line options have been parsed, then getopt() * returns -1. If getopt() encounters an option character that was not * in optstring, then '?' is returned. If getopt() encounters an option * with a missing argument, then the return value depends on the first From 513475c11ca9d97e6e0bd4de11204d8b9a870b04 Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Fri, 7 Feb 2020 10:04:48 +0100 Subject: [PATCH 32/35] Kinetis renamed TJA1100 to TJA110X registers --- arch/arm/src/kinetis/kinetis_enet.c | 82 ++++++++++++++++------------- drivers/net/Kconfig | 16 +++++- include/nuttx/net/mii.h | 25 +++++---- 3 files changed, 73 insertions(+), 50 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index 7f7d722d2f2..24bc8942b3e 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -173,7 +173,7 @@ # define BOARD_PHY_NAME "TJA1100" # define BOARD_PHYID1 MII_PHYID1_TJA1100 # define BOARD_PHYID2 MII_PHYID2_TJA1100 -# define BOARD_PHY_STATUS MII_TJA1100_BSR +# define BOARD_PHY_STATUS MII_TJA110X_BSR # define BOARD_PHY_10BASET(s) 0 /* PHY only supports 100BASE-T1 */ # define BOARD_PHY_100BASET(s) 1 /* PHY only supports 100BASE-T1 */ # define BOARD_PHY_ISDUPLEX(s) 1 /* PHY only supports fullduplex */ @@ -223,8 +223,9 @@ /**************************************************************************** * Private Types ****************************************************************************/ -/* The kinetis_driver_s encapsulates all state information for a single hardware - * interface + +/* The kinetis_driver_s encapsulates all state information for a single + * hardware interface. */ struct kinetis_driver_s @@ -600,8 +601,8 @@ static int kinetis_txpoll(struct net_driver_s *dev) } } - /* If zero is returned, the polling will continue until all connections have - * been examined. + /* If zero is returned, the polling will continue until all connections + * have been examined. */ return 0; @@ -664,7 +665,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv) ipv4_input(&priv->dev); /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. + * sent out on the network, the field d_len will set to a value > 0 */ if (priv->dev.d_len > 0) @@ -702,7 +703,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv) ipv6_input(&priv->dev); /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. + * sent out on the network, the field d_len will set to a value > 0 */ if (priv->dev.d_len > 0) @@ -736,7 +737,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv) arp_arpin(&priv->dev); /* If the above function invocation resulted in data that should - * be sent out on the network, the field d_len will set to a + * be sent out on the network, the field d_len will set to a * value > 0. */ @@ -751,10 +752,11 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv) NETDEV_RXDROPPED(&priv->dev); } - /* Point the packet buffer back to the next TX buffer, which will be used - * during the next write. If the write queue is full, then this will - * point at an active buffer, which must not be written to. This is OK - * because devif_poll won't be called unless the queue is not full. + /* Point the packet buffer back to the next TX buffer, which will be + * used during the next write. If the write queue is full, then this + * will point at an active buffer, which must not be written to. + * This is OK because devif_poll won't be called unless the queue is + * not full. */ priv->dev.d_buf = @@ -1071,16 +1073,17 @@ static void kinetis_poll_work(FAR void *arg) { FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; - /* Check if there is there is a transmission in progress. We cannot perform - * the TX poll if he are unable to accept another packet for transmission. + /* Check if there is there is a transmission in progress. We cannot + * perform the TX poll if he are unable to accept another packet for + * transmission. */ net_lock(); if (!kinetis_txringfull(priv)) { /* If so, update TCP timing states and poll the network for new XMIT - * data. Hmmm..might be bug here. Does this mean if there is a transmit - * in progress, we will missing TCP time state updates? + * data. Hmmm..might be bug here. Does this mean if there is a + * transmit in progress, we will missing TCP time state updates? */ devif_timer(&priv->dev, KINETIS_WDDELAY, kinetis_txpoll); @@ -1343,8 +1346,8 @@ static void kinetis_txavail_work(FAR void *arg) if (!kinetis_txringfull(priv)) { - /* No, there is space for another transfer. Poll the network for new - * XMIT data. + /* No, there is space for another transfer. Poll the network for + * new XMIT data. */ devif_poll(&priv->dev, kinetis_txpoll); @@ -1473,7 +1476,8 @@ static int kinetis_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) ****************************************************************************/ #ifdef CONFIG_NETDEV_IOCTL -static int kinetis_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) +static int kinetis_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg) { #ifdef CONFIG_NETDEV_PHY_IOCTL FAR struct kinetis_driver_s *priv = @@ -1497,7 +1501,8 @@ static int kinetis_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - ret = kinetis_readmii(priv, req->phy_id, req->reg_num, &req->val_out); + ret = kinetis_readmii(priv, req->phy_id, req->reg_num, + &req->val_out); } break; @@ -1505,7 +1510,8 @@ static int kinetis_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - ret = kinetis_writemii(priv, req->phy_id, req->reg_num, req->val_in); + ret = kinetis_writemii(priv, req->phy_id, req->reg_num, + req->val_in); } break; #endif /* ifdef CONFIG_NETDEV_PHY_IOCTL */ @@ -1882,40 +1888,40 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv) } #if defined(CONFIG_ETH0_PHY_TJA1100) -/* The NXP TJA1100 PHY is an automotive 100BASE-T1 PHY +/* The NXP TJA110X PHY is an automotive 100BASE-T1 PHY * Which requires additional initialization */ - /* select mode TJA1100 */ + /* select mode TJA110X */ - kinetis_writemii(priv, phyaddr, MII_TJA1100_EXT_CNTRL, + kinetis_writemii(priv, phyaddr, MII_TJA110X_EXT_CNTRL, (MII_EXT_CNTRL_NORMAL | MII_EXT_CNTRL_CONFIG_EN | MII_EXT_CNTRL_CONFIG_INH)); # if defined(CONFIG_PHY_100BASE_T1_MASTER) - /* Set TJA1100 in master mode */ + /* Set TJA110X in master mode */ - kinetis_writemii(priv, phyaddr, MII_TJA1100_CONFIG1, + kinetis_writemii(priv, phyaddr, MII_TJA110X_CONFIG1, (MII_CONFIG1_MASTER | MII_CONFIG1_TX_1250MV | MII_CONFIG1_RMII_25MHZ | MII_CONFIG1_LED_EN)); # else - /* Set TJA1100 in slave mode */ + /* Set TJA110X in slave mode */ - kinetis_writemii(priv, phyaddr, MII_TJA1100_CONFIG1, + kinetis_writemii(priv, phyaddr, MII_TJA110X_CONFIG1, (MII_CONFIG1_TX_1250MV | MII_CONFIG1_RMII_25MHZ | MII_CONFIG1_LED_EN)); # endif - kinetis_writemii(priv, phyaddr, MII_TJA1100_CONFIG2, + kinetis_writemii(priv, phyaddr, MII_TJA110X_CONFIG2, (MII_CONFIG2_SNR_AV64 | MII_CONFIG2_WLIM_D | MII_CONFIG2_SNR_F_NL | MII_CONFIG2_SLP_T_1)); - /* Select normal mode TJA1100 */ + /* Select normal mode TJA110X */ - kinetis_writemii(priv, phyaddr, MII_TJA1100_EXT_CNTRL, + kinetis_writemii(priv, phyaddr, MII_TJA110X_EXT_CNTRL, (MII_EXT_CNTRL_NORMAL | MII_EXT_CNTRL_CONFIG_INH)); - kinetis_writemii(priv, phyaddr, MII_TJA1100_EXT_CNTRL, + kinetis_writemii(priv, phyaddr, MII_TJA110X_EXT_CNTRL, (MII_EXT_CNTRL_LINK_CNTRL | MII_EXT_CNTRL_NORMAL | MII_EXT_CNTRL_CONFIG_INH)); #endif @@ -2217,8 +2223,8 @@ int kinetis_netinitialize(int intf) #ifdef CONFIG_NET_ETHERNET /* Determine a semi-unique MAC address from MCU UID * We use UID Low and Mid Low registers to get 64 bits, from which we keep - * 48 bits. We then force unicast and locally administered bits (b0 and b1, - * 1st octet) + * 48 bits. We then force unicast and locally administered bits (b0 and + * b1, 1st octet) */ uidl = getreg32(KINETIS_SIM_UIDL); @@ -2230,10 +2236,10 @@ int kinetis_netinitialize(int intf) mac[0] = (uidml & 0x0000ff00) >> 8; mac[1] = (uidml & 0x000000ff); - mac[2] = (uidl & 0xff000000) >> 24; - mac[3] = (uidl & 0x00ff0000) >> 16; - mac[4] = (uidl & 0x0000ff00) >> 8; - mac[5] = (uidl & 0x000000ff); + mac[2] = (uidl & 0xff000000) >> 24; + mac[3] = (uidl & 0x00ff0000) >> 16; + mac[4] = (uidl & 0x0000ff00) >> 8; + mac[5] = (uidl & 0x000000ff); #endif /* Put the interface in the down state. This usually amounts to resetting diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 68b5b843995..9781d373258 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -377,6 +377,11 @@ config ETH0_PHY_DP83848C config ETH0_PHY_TJA1100 bool "NXP TJA1100 PHY" + select ARCH_PHY_100BASE_T1 + +config ETH0_PHY_TJA1101 + bool "NXP TJA1101 PHY" + select ARCH_PHY_100BASE_T1 config ETH0_PHY_LAN8720 bool "SMSC LAN8720 PHY" @@ -428,6 +433,11 @@ config ETH1_PHY_DP83848C config ETH1_PHY_TJA1100 bool "NXP TJA1100 PHY" + select ARCH_PHY_100BASE_T1 + +config ETH1_PHY_TJA1101 + bool "NXP TJA1101 PHY" + select ARCH_PHY_100BASE_T1 config ETH1_PHY_LAN8720 bool "SMSC LAN8720 PHY" @@ -437,7 +447,11 @@ config ETH1_PHY_DM9161 endchoice -if (ETH0_PHY_TJA1100 || ETH1_PHY_TJA1100) +config ARCH_PHY_100BASE_T1 + bool + default n + +if (ARCH_PHY_100BASE_T1) choice prompt "Automotive Ethernet 100BASE-T1 master/slave mode" diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h index 47aa6db5186..6125e44ea3d 100644 --- a/include/nuttx/net/mii.h +++ b/include/nuttx/net/mii.h @@ -634,20 +634,23 @@ # define MII_PHYCTRL1_MODE_10FDX (5 << MII_PHYCTRL1_MODE_SHIFT) /* 10Base-T full-duplex */ # define MII_PHYCTRL1_MODE_100FDX (6 << MII_PHYCTRL1_MODE_SHIFT) /* 100Base-T full-duplex */ -/* TJA1100 register bit settings *************************************************************/ +/* TJA110X register bit settings ********************************************/ -/* TJA1100 MII ID1/2 register bits */ +/* TJA110X MII ID1/2 register bits */ #define MII_PHYID1_TJA1100 0x0180 /* ID1 value for NXP TJA1100 */ #define MII_PHYID2_TJA1100 0xdc40 /* ID2 value for NXP TJA1100 */ -#define MII_TJA1100_BCR 0x0 /* Basic Control register */ -#define MII_TJA1100_BSR 0x1 /* Basic Status register */ -#define MII_TJA1100_EXT_CNTRL 0x11 /* Extra control register */ -#define MII_TJA1100_CONFIG1 0x12 /* CONFIG 1 register */ -#define MII_TJA1100_CONFIG2 0x13 /* CONFIG 2 register */ +#define MII_PHYID1_TJA1101 0x0180 /* ID1 value for NXP TJA1101 */ +#define MII_PHYID2_TJA1101 0xdd00 /* ID2 value for NXP TJA1101 */ -/* MII_TJA1100_EXT_CNTRL */ +#define MII_TJA110X_BCR 0x0 /* Basic Control register */ +#define MII_TJA110X_BSR 0x1 /* Basic Status register */ +#define MII_TJA110X_EXT_CNTRL 0x11 /* Extra control register */ +#define MII_TJA110X_CONFIG1 0x12 /* CONFIG 1 register */ +#define MII_TJA110X_CONFIG2 0x13 /* CONFIG 2 register */ + +/* MII_TJA110X_EXT_CNTRL */ #define MII_EXT_CNTRL_LINK_CNTRL (1 << 15) #define MII_EXT_CNTRL_POWER_MODE_SHIFT (11) @@ -680,7 +683,7 @@ #define MII_EXT_CNTRL_CONFIG_INH (1 << 1) #define MII_EXT_CNTRL_WAKE_REQ (1 << 0) /* transmit idle symbols as bus wake-up request */ -/* MII_TJA1100_CONFIG1 */ +/* MII_TJA110X_CONFIG1 */ #define MII_CONFIG1_MASTER (1 << 15) #define MII_CONFIG1_AUTO_OP (1 << 14) @@ -708,7 +711,7 @@ #define MII_CONFIG1_CNFG_WAKE (1 << 2) /* ratiometric input threshold, absolute if zero */ #define MII_CONFIG1_AUTO_PWD (1 << 1) /* autonomous power-down enabled */ -/* MII_TJA1100_CONFIG2 */ +/* MII_TJA110X_CONFIG2 */ #define MII_CONFIG2_PHYAD_SHIFT (11) /* readback of scrambler key */ #define MII_CONFIG2_PHYAD_MASK (0x1f << MII_CONFIG2_PHYAD_SHIFT) @@ -729,7 +732,7 @@ # define MII_CONFIG2_WLIM_F (6 << MII_CONFIG2_WLIM_SHIFT) /* Class F SNR warning limit */ # define MII_CONFIG2_WLIM_G (7 << MII_CONFIG2_WLIM_SHIFT) /* Class G SNR warning limit */ #define MII_CONFIG2_SNR_F_SHIFT (3) /* signal to noise ratio fail limit */ -#define MII_CONFIG2_SNR_F_MASK (7 << MII_CONFIG2_SNR_F_SHIFT)) +#define MII_CONFIG2_SNR_F_MASK (7 << MII_CONFIG2_SNR_F_SHIFT) # define MII_CONFIG2_SNR_F_NL (0 << MII_CONFIG2_SNR_F_SHIFT) /* no limit */ # define MII_CONFIG2_SNR_F_CLA (1 << MII_CONFIG2_SNR_F_SHIFT) /* Class A */ # define MII_CONFIG2_SNR_F_CLB (2 << MII_CONFIG2_SNR_F_SHIFT) /* Class B */ From d79e6734683743a47c535822637b2bc74c2f6846 Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Fri, 7 Feb 2020 10:09:43 +0100 Subject: [PATCH 33/35] imxrt added missing i2c prescale mask --- arch/arm/src/imxrt/imxrt_lpi2c.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.c b/arch/arm/src/imxrt/imxrt_lpi2c.c index c1a2e08e8f7..404119efdfa 100644 --- a/arch/arm/src/imxrt/imxrt_lpi2c.c +++ b/arch/arm/src/imxrt/imxrt_lpi2c.c @@ -1118,7 +1118,8 @@ static void imxrt_lpi2c_setclock(FAR struct imxrt_lpi2c_priv_s *priv, } } - imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCFGR1_OFFSET, 0, + imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCFGR1_OFFSET, + LPI2C_MCFGR1_PRESCALE_MASK, LPI2C_MCFGR1_PRESCALE(best_prescale)); /* Re-enable LPI2C if it was enabled previously */ @@ -1304,7 +1305,8 @@ static int imxrt_lpi2c_isr_process(struct imxrt_lpi2c_priv_s *priv) if ((priv->msgv->flags & I2C_M_NOSTART) == 0) { - imxrt_lpi2c_traceevent(priv, I2CEVENT_STARTRESTART, priv->msgc); + imxrt_lpi2c_traceevent(priv, I2CEVENT_STARTRESTART, + priv->msgc); imxrt_lpi2c_sendstart(priv, priv->msgv->addr); } else From 499607d68f609aa83e617d132cb36090c0fcca00 Mon Sep 17 00:00:00 2001 From: Peter van der Perk <57130844+PetervdPerk-NXP@users.noreply.github.com> Date: Fri, 7 Feb 2020 13:53:40 +0100 Subject: [PATCH 34/35] S32K add support for Nxp drone boards (#224) * S32K add support for Nxp drone boards * Update arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h codestyle Co-Authored-By: David Sidrane Co-authored-by: Jari van Ewijk Co-authored-by: David Sidrane --- arch/arm/include/s32k1xx/irq.h | 6 +- arch/arm/src/s32k1xx/Kconfig | 15 +- arch/arm/src/s32k1xx/Make.defs | 4 + arch/arm/src/s32k1xx/chip.h | 7 +- .../arm/src/s32k1xx/hardware/s32k148_pinmux.h | 16 +- arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h | 94 ++++++ arch/arm/src/s32k1xx/s32k14x/Make.defs | 1 + arch/arm/src/s32k1xx/s32k1xx_clockconfig.c | 85 +++--- arch/arm/src/s32k1xx/s32k1xx_clockconfig.h | 16 +- arch/arm/src/s32k1xx/s32k1xx_enet.c | 181 ++++++++---- arch/arm/src/s32k1xx/s32k1xx_lpi2c.c | 45 ++- arch/arm/src/s32k1xx/s32k1xx_lpspi.c | 45 +-- arch/arm/src/s32k1xx/s32k1xx_pin.h | 11 +- arch/arm/src/s32k1xx/s32k1xx_pinirq.c | 53 ++-- arch/arm/src/s32k1xx/s32k1xx_rtc.c | 267 ++++++++++++++++++ arch/arm/src/s32k1xx/s32k1xx_rtc.h | 121 ++++++++ arch/arm/src/s32k1xx/s32k1xx_start.c | 15 +- boards/Kconfig | 42 +++ boards/arm/s32k1xx/rddrone-uavcan144/Kconfig | 8 + .../arm/s32k1xx/rddrone-uavcan144/README.txt | 15 + .../rddrone-uavcan144/configs/nsh/defconfig | 71 +++++ .../configs/nshdebug/defconfig | 73 +++++ .../s32k1xx/rddrone-uavcan144/include/board.h | 153 ++++++++++ .../rddrone-uavcan144/scripts/Make.defs | 131 +++++++++ .../rddrone-uavcan144/scripts/flash.ld | 152 ++++++++++ .../rddrone-uavcan144/scripts/s32k144.cfg | 58 ++++ .../s32k1xx/rddrone-uavcan144/scripts/sram.ld | 129 +++++++++ .../s32k1xx/rddrone-uavcan144/src/.gitignore | 2 + .../s32k1xx/rddrone-uavcan144/src/Makefile | 60 ++++ .../rddrone-uavcan144/src/rddrone-uavcan144.h | 139 +++++++++ .../rddrone-uavcan144/src/s32k1xx_appinit.c | 94 ++++++ .../rddrone-uavcan144/src/s32k1xx_autoleds.c | 165 +++++++++++ .../rddrone-uavcan144/src/s32k1xx_boot.c | 93 ++++++ .../rddrone-uavcan144/src/s32k1xx_bringup.c | 147 ++++++++++ .../rddrone-uavcan144/src/s32k1xx_buttons.c | 165 +++++++++++ .../src/s32k1xx_clockconfig.c | 227 +++++++++++++++ .../src/s32k1xx_periphclocks.c | 187 ++++++++++++ .../rddrone-uavcan144/src/s32k1xx_spi.c | 199 +++++++++++++ .../rddrone-uavcan144/src/s32k1xx_userleds.c | 116 ++++++++ boards/arm/s32k1xx/rddrone-uavcan146/Kconfig | 8 + .../arm/s32k1xx/rddrone-uavcan146/README.txt | 15 + .../rddrone-uavcan146/configs/nsh/defconfig | 71 +++++ .../configs/nshdebug/defconfig | 73 +++++ .../s32k1xx/rddrone-uavcan146/include/board.h | 153 ++++++++++ .../rddrone-uavcan146/scripts/Make.defs | 131 +++++++++ .../rddrone-uavcan146/scripts/flash.ld | 152 ++++++++++ .../rddrone-uavcan146/scripts/s32k146.cfg | 58 ++++ .../s32k1xx/rddrone-uavcan146/scripts/sram.ld | 129 +++++++++ .../s32k1xx/rddrone-uavcan146/src/.gitignore | 2 + .../s32k1xx/rddrone-uavcan146/src/Makefile | 60 ++++ .../rddrone-uavcan146/src/rddrone-uavcan146.h | 139 +++++++++ .../rddrone-uavcan146/src/s32k1xx_appinit.c | 94 ++++++ .../rddrone-uavcan146/src/s32k1xx_autoleds.c | 165 +++++++++++ .../rddrone-uavcan146/src/s32k1xx_boot.c | 93 ++++++ .../rddrone-uavcan146/src/s32k1xx_bringup.c | 144 ++++++++++ .../rddrone-uavcan146/src/s32k1xx_buttons.c | 165 +++++++++++ .../src/s32k1xx_clockconfig.c | 227 +++++++++++++++ .../src/s32k1xx_periphclocks.c | 187 ++++++++++++ .../rddrone-uavcan146/src/s32k1xx_spi.c | 199 +++++++++++++ .../rddrone-uavcan146/src/s32k1xx_userleds.c | 116 ++++++++ boards/arm/s32k1xx/s32k118evb/README.txt | 4 +- boards/arm/s32k1xx/s32k118evb/include/board.h | 14 +- boards/arm/s32k1xx/s32k118evb/src/Makefile | 12 +- .../arm/s32k1xx/s32k118evb/src/s32k118evb.h | 15 +- .../s32k1xx/s32k118evb/src/s32k1xx_appinit.c | 94 ++++++ .../s32k1xx/s32k118evb/src/s32k1xx_autoleds.c | 165 +++++++++++ .../arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c | 101 +++++++ .../s32k1xx/s32k118evb/src/s32k1xx_bringup.c | 109 +++++++ .../s32k1xx/s32k118evb/src/s32k1xx_buttons.c | 165 +++++++++++ .../s32k118evb/src/s32k1xx_clockconfig.c | 208 ++++++++++++++ .../s32k118evb/src/s32k1xx_periphclocks.c | 152 ++++++++++ .../s32k1xx/s32k118evb/src/s32k1xx_userleds.c | 116 ++++++++ boards/arm/s32k1xx/s32k144evb/Kconfig | 8 + boards/arm/s32k1xx/s32k144evb/README.txt | 15 + .../s32k1xx/s32k144evb/configs/nsh/defconfig | 54 ++++ boards/arm/s32k1xx/s32k144evb/include/board.h | 164 +++++++++++ .../arm/s32k1xx/s32k144evb/scripts/Make.defs | 131 +++++++++ .../arm/s32k1xx/s32k144evb/scripts/flash.ld | 152 ++++++++++ .../s32k1xx/s32k144evb/scripts/s32k144.cfg | 58 ++++ boards/arm/s32k1xx/s32k144evb/scripts/sram.ld | 129 +++++++++ boards/arm/s32k1xx/s32k144evb/src/.gitignore | 2 + boards/arm/s32k1xx/s32k144evb/src/Makefile | 60 ++++ .../arm/s32k1xx/s32k144evb/src/s32k144evb.h | 135 +++++++++ .../s32k1xx/s32k144evb/src/s32k1xx_appinit.c | 94 ++++++ .../s32k1xx/s32k144evb/src/s32k1xx_autoleds.c | 165 +++++++++++ .../arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c | 93 ++++++ .../s32k1xx/s32k144evb/src/s32k1xx_bringup.c | 141 +++++++++ .../s32k1xx/s32k144evb/src/s32k1xx_buttons.c | 165 +++++++++++ .../s32k144evb/src/s32k1xx_clockconfig.c | 227 +++++++++++++++ .../s32k144evb/src/s32k1xx_periphclocks.c | 187 ++++++++++++ .../arm/s32k1xx/s32k144evb/src/s32k1xx_spi.c | 198 +++++++++++++ .../s32k1xx/s32k144evb/src/s32k1xx_userleds.c | 116 ++++++++ boards/arm/s32k1xx/s32k146evb/README.txt | 4 +- .../s32k1xx/s32k146evb/configs/nsh/defconfig | 6 +- boards/arm/s32k1xx/s32k146evb/include/board.h | 38 ++- boards/arm/s32k1xx/s32k146evb/src/Makefile | 16 +- .../arm/s32k1xx/s32k146evb/src/s32k146evb.h | 17 +- .../s32k1xx/s32k146evb/src/s32k1xx_appinit.c | 94 ++++++ .../s32k1xx/s32k146evb/src/s32k1xx_autoleds.c | 165 +++++++++++ .../arm/s32k1xx/s32k146evb/src/s32k1xx_boot.c | 93 ++++++ .../s32k1xx/s32k146evb/src/s32k1xx_bringup.c | 141 +++++++++ .../s32k1xx/s32k146evb/src/s32k1xx_buttons.c | 165 +++++++++++ .../s32k146evb/src/s32k1xx_clockconfig.c | 227 +++++++++++++++ .../s32k146evb/src/s32k1xx_periphclocks.c | 187 ++++++++++++ .../arm/s32k1xx/s32k146evb/src/s32k1xx_spi.c | 198 +++++++++++++ .../s32k1xx/s32k146evb/src/s32k1xx_userleds.c | 116 ++++++++ boards/arm/s32k1xx/s32k148evb/README.txt | 4 +- .../s32k1xx/s32k148evb/configs/nsh/defconfig | 4 +- boards/arm/s32k1xx/s32k148evb/include/board.h | 14 +- .../arm/s32k1xx/s32k148evb/scripts/flash.ld | 2 +- boards/arm/s32k1xx/s32k148evb/scripts/sram.ld | 2 +- boards/arm/s32k1xx/s32k148evb/src/Makefile | 12 +- .../arm/s32k1xx/s32k148evb/src/s32k148evb.h | 17 +- .../s32k1xx/s32k148evb/src/s32k1xx_appinit.c | 94 ++++++ .../s32k1xx/s32k148evb/src/s32k1xx_autoleds.c | 165 +++++++++++ .../arm/s32k1xx/s32k148evb/src/s32k1xx_boot.c | 101 +++++++ .../s32k1xx/s32k148evb/src/s32k1xx_bringup.c | 109 +++++++ .../s32k1xx/s32k148evb/src/s32k1xx_buttons.c | 165 +++++++++++ .../s32k148evb/src/s32k1xx_clockconfig.c | 227 +++++++++++++++ .../s32k148evb/src/s32k1xx_periphclocks.c | 178 ++++++++++++ .../s32k1xx/s32k148evb/src/s32k1xx_userleds.c | 116 ++++++++ drivers/spi/spi_bitbang.c | 38 ++- 122 files changed, 11681 insertions(+), 272 deletions(-) create mode 100644 arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h create mode 100644 arch/arm/src/s32k1xx/s32k1xx_rtc.c create mode 100644 arch/arm/src/s32k1xx/s32k1xx_rtc.h create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/Kconfig create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/README.txt create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/include/board.h create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/scripts/flash.ld create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/scripts/s32k144.cfg create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/scripts/sram.ld create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/.gitignore create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/Makefile create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/rddrone-uavcan144.h create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_appinit.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_autoleds.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_buttons.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_periphclocks.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_userleds.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/Kconfig create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/README.txt create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/include/board.h create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/scripts/flash.ld create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/scripts/s32k146.cfg create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/scripts/sram.ld create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/.gitignore create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/Makefile create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_appinit.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_autoleds.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c create mode 100644 boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_userleds.c create mode 100644 boards/arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c create mode 100644 boards/arm/s32k1xx/s32k118evb/src/s32k1xx_autoleds.c create mode 100644 boards/arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c create mode 100644 boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c create mode 100644 boards/arm/s32k1xx/s32k118evb/src/s32k1xx_buttons.c create mode 100644 boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c create mode 100644 boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclocks.c create mode 100644 boards/arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c create mode 100644 boards/arm/s32k1xx/s32k144evb/Kconfig create mode 100644 boards/arm/s32k1xx/s32k144evb/README.txt create mode 100644 boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig create mode 100644 boards/arm/s32k1xx/s32k144evb/include/board.h create mode 100644 boards/arm/s32k1xx/s32k144evb/scripts/Make.defs create mode 100644 boards/arm/s32k1xx/s32k144evb/scripts/flash.ld create mode 100644 boards/arm/s32k1xx/s32k144evb/scripts/s32k144.cfg create mode 100644 boards/arm/s32k1xx/s32k144evb/scripts/sram.ld create mode 100644 boards/arm/s32k1xx/s32k144evb/src/.gitignore create mode 100644 boards/arm/s32k1xx/s32k144evb/src/Makefile create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k144evb.h create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k1xx_autoleds.c create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k1xx_buttons.c create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k1xx_periphclocks.c create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k1xx_spi.c create mode 100644 boards/arm/s32k1xx/s32k144evb/src/s32k1xx_userleds.c create mode 100644 boards/arm/s32k1xx/s32k146evb/src/s32k1xx_appinit.c create mode 100644 boards/arm/s32k1xx/s32k146evb/src/s32k1xx_autoleds.c create mode 100644 boards/arm/s32k1xx/s32k146evb/src/s32k1xx_boot.c create mode 100644 boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c create mode 100644 boards/arm/s32k1xx/s32k146evb/src/s32k1xx_buttons.c create mode 100644 boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c create mode 100644 boards/arm/s32k1xx/s32k146evb/src/s32k1xx_periphclocks.c create mode 100644 boards/arm/s32k1xx/s32k146evb/src/s32k1xx_spi.c create mode 100644 boards/arm/s32k1xx/s32k146evb/src/s32k1xx_userleds.c create mode 100644 boards/arm/s32k1xx/s32k148evb/src/s32k1xx_appinit.c create mode 100644 boards/arm/s32k1xx/s32k148evb/src/s32k1xx_autoleds.c create mode 100644 boards/arm/s32k1xx/s32k148evb/src/s32k1xx_boot.c create mode 100644 boards/arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c create mode 100644 boards/arm/s32k1xx/s32k148evb/src/s32k1xx_buttons.c create mode 100644 boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c create mode 100644 boards/arm/s32k1xx/s32k148evb/src/s32k1xx_periphclocks.c create mode 100644 boards/arm/s32k1xx/s32k148evb/src/s32k1xx_userleds.c diff --git a/arch/arm/include/s32k1xx/irq.h b/arch/arm/include/s32k1xx/irq.h index b18bef7d8ec..ddef8ea5a10 100644 --- a/arch/arm/include/s32k1xx/irq.h +++ b/arch/arm/include/s32k1xx/irq.h @@ -46,10 +46,10 @@ #include -#if defined(CONFIG_ARCH_CHIP_S32K11X) -# include -#elif defined(CONFIG_ARCH_CHIP_S32K14X) +#if defined(CONFIG_ARCH_CHIP_S32K14X) # include +#elif defined(CONFIG_ARCH_CHIP_S32K11X) +# include #else # error Unrecognized S32K1XX part #endif diff --git a/arch/arm/src/s32k1xx/Kconfig b/arch/arm/src/s32k1xx/Kconfig index ff480fb959b..63e0cd95815 100644 --- a/arch/arm/src/s32k1xx/Kconfig +++ b/arch/arm/src/s32k1xx/Kconfig @@ -79,6 +79,9 @@ config ARCH_CHIP_S32K14X config S32K1XX_HAVE_ENET bool default n + select ARCH_HAVE_PHY + select ARCH_PHY_INTERRUPT + select ARCH_HAVE_NETDEV_STATISTICS config S32K1XX_HAVE_EWM bool @@ -183,18 +186,26 @@ config S32K1XX_LPUART0 default n select S32K1XX_LPUART select LPUART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config S32K1XX_LPUART1 bool "LPUART1" default n select S32K1XX_LPUART select LPUART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config S32K1XX_LPUART2 bool "LPUART2" default n select S32K1XX_LPUART select LPUART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config S32K1XX_RTC + bool "RTC" + default n + endmenu # S32K1XX Peripheral Selection @@ -267,14 +278,14 @@ config S32K1XX_FLASHCFG_FPROT config S32K1XX_FLASHCFG_FSEC hex "Flash security byte" - default 0xff + default 0xfe ---help--- Refer to the S32K1xx reference manual or to hardware/s32k1xx_flashcfg.h for a description of the FSEC bitfields. config S32K1XX_FLASHCFG_FOPT hex "Flash nonvolatile option byte" - default 0xff + default 0x7f ---help--- Refer to the S32K1xx reference manual or to hardware/s32k1xx_flashcfg.h for a description of the FOPT bitfields. diff --git a/arch/arm/src/s32k1xx/Make.defs b/arch/arm/src/s32k1xx/Make.defs index 880f575de22..3f69fb03639 100644 --- a/arch/arm/src/s32k1xx/Make.defs +++ b/arch/arm/src/s32k1xx/Make.defs @@ -90,6 +90,10 @@ ifeq ($(CONFIG_S32K1XX_ENET),y) CHIP_CSRCS += s32k1xx_enet.c endif +ifeq ($(CONFIG_S32K1XX_RTC),y) +CHIP_CSRCS += s32k1xx_rtc.c +endif + # Source files specific to the ARM CPU family and to the S32K1xx chip family ifeq ($(CONFIG_ARCH_CHIP_S32K11X),y) diff --git a/arch/arm/src/s32k1xx/chip.h b/arch/arm/src/s32k1xx/chip.h index f3f9b9c2293..73b58829a06 100644 --- a/arch/arm/src/s32k1xx/chip.h +++ b/arch/arm/src/s32k1xx/chip.h @@ -58,6 +58,11 @@ #define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT #define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT +/* Cache line sizes (in bytes)for the S32K14X */ + +#define ARMV7M_DCACHE_LINESIZE 16 /* 16 bytes (4 words) */ +#define ARMV7M_ICACHE_LINESIZE 16 /* 16 bytes (4 words) */ + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -71,7 +76,7 @@ ************************************************************************************/ /************************************************************************************ - * Public Functions + * Public Function Prototypes ************************************************************************************/ #endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h b/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h index 06afa605bac..bb6aaef6278 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h +++ b/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h @@ -642,14 +642,18 @@ #define PIN_RMII_MDIO (PIN_ALT5 | PIN_PORTB | PIN4) #define PIN_RMII_RX_DV (PIN_ALT5 | PIN_PORTC | PIN17) #define PIN_RMII_RX_ER (PIN_ALT5 | PIN_PORTC | PIN16) -#define PIN_RMII_RXD_1 (PIN_ALT5 | PIN_PORTC | PIN0) -#define PIN_RMII_RXD_2 (PIN_ALT5 | PIN_PORTC | PIN1) -#define PIN_RMII_RXD_3 (PIN_ALT4 | PIN_PORTC | PIN0) -#define PIN_RMII_RXD_4 (PIN_ALT4 | PIN_PORTC | PIN1) +#define PIN_RMII_RXD0_1 (PIN_ALT5 | PIN_PORTC | PIN1) +#define PIN_RMII_RXD1_1 (PIN_ALT4 | PIN_PORTC | PIN0) +#define PIN_RMII_RXD0_2 (PIN_ALT5 | PIN_PORTC | PIN0) +#define PIN_RMII_RXD1_2 (PIN_ALT4 | PIN_PORTC | PIN1) #define PIN_RMII_TX_CLK (PIN_ALT5 | PIN_PORTD | PIN11) #define PIN_RMII_TX_EN (PIN_ALT5 | PIN_PORTD | PIN12) -#define PIN_RMII_TXD_1 (PIN_ALT5 | PIN_PORTC | PIN2) -#define PIN_RMII_TXD_2 (PIN_ALT5 | PIN_PORTD | PIN7) +#define PIN_RMII_TXD0 (PIN_ALT5 | PIN_PORTC | PIN2) +#define PIN_RMII_TXD1 (PIN_ALT5 | PIN_PORTD | PIN7) + +#define PIN_RMII_MDC PIN_RMII_MDC_2 +#define PIN_RMII_RXD0 PIN_RMII_RXD0_1 +#define PIN_RMII_RXD1 PIN_RMII_RXD1_1 /* NMI */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h new file mode 100644 index 00000000000..b09914ec12d --- /dev/null +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h @@ -0,0 +1,94 @@ +/**************************************************************************************************** + * arch/arm/src/s32k1xx/chip/s32k1xx_rtc.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RTC_H +#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RTC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* RTC Register Offsets *****************************************************************************/ + +#define S32K1XX_RTC_TSR_OFFSET 0x0000 /* Time Seconds register */ +#define S32K1XX_RTC_TPR_OFFSET 0x0004 /* Time Prescaler Register */ +#define S32K1XX_RTC_TAR_OFFSET 0x0008 /* Time Alarm Register */ +#define S32K1XX_RTC_TCR_OFFSET 0x000C /* Time Compensation Register */ +#define S32K1XX_RTC_CR_OFFSET 0x0010 /* Control Register */ +#define S32K1XX_RTC_SR_OFFSET 0x0014 /* Status Register */ +#define S32K1XX_RTC_LR_OFFSET 0x0018 /* Lock Register */ +#define S32K1XX_RTC_IER_OFFSET 0x001C /* Interrupt Enable Register */ + +/* RTC Register Addresses ***************************************************************************/ + +#define S32K1XX_RTC_TSR (S32K1XX_RTC_BASE + S32K1XX_RTC_TSR_OFFSET) +#define S32K1XX_RTC_TPR (S32K1XX_RTC_BASE + S32K1XX_RTC_TPR_OFFSET) +#define S32K1XX_RTC_TAR (S32K1XX_RTC_BASE + S32K1XX_RTC_TAR_OFFSET) +#define S32K1XX_RTC_TCR (S32K1XX_RTC_BASE + S32K1XX_RTC_TCR_OFFSET) +#define S32K1XX_RTC_CR (S32K1XX_RTC_BASE + S32K1XX_RTC_CR_OFFSET) +#define S32K1XX_RTC_SR (S32K1XX_RTC_BASE + S32K1XX_RTC_SR_OFFSET) +#define S32K1XX_RTC_LR (S32K1XX_RTC_BASE + S32K1XX_RTC_LR_OFFSET) +#define S32K1XX_RTC_IER (S32K1XX_RTC_BASE + S32K1XX_RTC_IER_OFFSET) + +/* RTC Register Bitfield Definitions ****************************************************************/ + +/* TSR Bit Fields */ + +#define RTC_TSR_SHIFT (0) +#define RTC_TSR_MASK (0xffffffff << RTC_TSR_SHIFT) + +/* CR Bit Fields */ + +#define RTC_CR_SWR (1 << 0) +#define RTC_CR_SUP (1 << 2) +#define RTC_CR_UM (1 << 3) +#define RTC_CR_CPS (1 << 5) +#define RTC_CR_LPOS (1 << 7) +#define RTC_CR_CPE (1 << 24) + +/* SR Bit Fields */ + +#define RTC_SR_TIF (1 << 0) +#define RTC_SR_TOF (1 << 1) +#define RTC_SR_TAF (1 << 2) +#define RTC_SR_TCE (1 << 4) +#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RTC_H */ diff --git a/arch/arm/src/s32k1xx/s32k14x/Make.defs b/arch/arm/src/s32k1xx/s32k14x/Make.defs index 9fe8cd72ec7..a0c67d51154 100644 --- a/arch/arm/src/s32k1xx/s32k14x/Make.defs +++ b/arch/arm/src/s32k1xx/s32k14x/Make.defs @@ -48,6 +48,7 @@ CMN_CSRCS += up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c CMN_CSRCS += up_doirq.c up_hardfault.c up_initialstate.c up_memfault.c CMN_CSRCS += up_releasepending.c up_reprioritizertr.c up_schedulesigaction.c CMN_CSRCS += up_sigdeliver.c up_svcall.c up_trigger_irq.c up_unblocktask.c +CMN_CSRCS += up_systemreset.c ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) CMN_ASRCS += up_lazyexception.S diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c index 574446bd1da..492b32c014a 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c +++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c @@ -113,8 +113,8 @@ #define SOSC_STABILIZATION_TIMEOUT 3205000 #define SPLL_STABILIZATION_TIMEOUT 1000 -/* System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the range of - * SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX. +/* System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the + * range of SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX. */ #define SCG_SPLL_REF_MIN 8000000 @@ -221,7 +221,7 @@ static uint32_t g_tclkfreq[NUMBER_OF_TCLK_INPUTS]; /* TCLKx clocks */ * Returned Value: * The current system clock source. * - *****************************************************************************/ + ****************************************************************************/ static inline uint32_t s32k1xx_get_scgclk_source(void) { @@ -240,7 +240,7 @@ static inline uint32_t s32k1xx_get_scgclk_source(void) * Returned Value: * The current running mode. * - *****************************************************************************/ + ****************************************************************************/ static enum scg_system_clock_mode_e s32k1xx_get_runmode(void) { @@ -293,7 +293,7 @@ static enum scg_system_clock_mode_e s32k1xx_get_runmode(void) * Returned Value: * The SOSC frequency. Zero is returned if the SOSC is invalid. * - *****************************************************************************/ + ****************************************************************************/ static uint32_t s32k1xx_get_soscfreq(void) { @@ -321,7 +321,7 @@ static uint32_t s32k1xx_get_soscfreq(void) * Returned Value: * The SIRC frequency. Zero is returned if the SIRC is invalid. * - *****************************************************************************/ + ****************************************************************************/ static uint32_t s32k1xx_get_sircfreq(void) { @@ -333,7 +333,7 @@ static uint32_t s32k1xx_get_sircfreq(void) if ((getreg32(S32K1XX_SCG_SIRCCFG) & SCG_SIRCCFG_RANGE) != 0) { - return SCG_SIRQ_HIGHRANGE_FREQUENCY; + return SCG_SIRC_HIGHRANGE_FREQUENCY; } } @@ -352,7 +352,7 @@ static uint32_t s32k1xx_get_sircfreq(void) * Returned Value: * The FIRC frequency. Zero is returned if the FIRC is invalid. * - *****************************************************************************/ + ****************************************************************************/ static uint32_t s32k1xx_get_fircfreq(void) { @@ -360,7 +360,7 @@ static uint32_t s32k1xx_get_fircfreq(void) if ((getreg32(S32K1XX_SCG_FIRCCSR) & SCG_FIRCCSR_FIRCVLD) != 0) { - return SCG_FIRQ_FREQUENCY0; + return SCG_FIRC_FREQUENCY0; } else { @@ -380,7 +380,7 @@ static uint32_t s32k1xx_get_fircfreq(void) * Returned Value: * The SPLL frequency. Zero is returned if the SPLL is invalid. * - *****************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_HAVE_SPLL static uint32_t s32k1xx_get_spllfreq(void) @@ -429,7 +429,7 @@ static uint32_t s32k1xx_get_spllfreq(void) * Returned Values: * The requested clock source frequency. Zero is returned on any error. * - *****************************************************************************/ + ****************************************************************************/ static uint32_t s32k1xx_get_srcfreq(enum scg_system_clock_src_e src) { @@ -476,7 +476,7 @@ static uint32_t s32k1xx_get_srcfreq(enum scg_system_clock_src_e src) * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ static int s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, @@ -546,7 +546,7 @@ s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, break; #ifdef CONFIG_S32K1XX_HAVE_HSRUN - case SCG_SYSTEM_CLOCK_MODE_HSRUN: /*!< High Speed Run mode. */ + case SCG_SYSTEM_CLOCK_MODE_HSRUN: /* High Speed Run mode. */ DEBUGASSERT(SCG_SYSTEM_CLOCK_SRC_FIRC == config->src || SCG_SYSTEM_CLOCK_SRC_SYS_PLL == config->src); @@ -574,6 +574,7 @@ s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, break; #endif default: + /* Invalid mode */ DEBUGPANIC(); @@ -596,7 +597,7 @@ s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ static int s32k1xx_transition_systemclock(const struct scg_system_clock_config_s *cfg) @@ -621,7 +622,7 @@ s32k1xx_transition_systemclock(const struct scg_system_clock_config_s *cfg) if (ret == OK) { /* Wait for system clock to transition. - * + * * e10777: The SCG_RCCR[SCS] and SCG_HCCR[SCS] may have a corrupted * status during the interval when the system clock is switching. * Workaround: The SCS field should be read twice by the software to @@ -662,7 +663,7 @@ s32k1xx_transition_systemclock(const struct scg_system_clock_config_s *cfg) * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ static int s32k1xx_firc_config(bool enable, const struct scg_firc_config_s *firccfg) @@ -690,7 +691,7 @@ static int s32k1xx_firc_config(bool enable, regval &= ~SCG_FIRCCSR_LK; putreg32(regval, S32K1XX_SCG_FIRCCSR); - /* Disable monitor, disable clock and clear error. */ + /* Disable monitor, disable clock and clear error. */ putreg32(SCG_FIRCCSR_FIRCERR, S32K1XX_SCG_FIRCCSR); } @@ -766,7 +767,7 @@ static int s32k1xx_firc_config(bool enable, * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ static int s32k11_firc_clocksource(void) { @@ -817,7 +818,7 @@ static int s32k11_firc_clocksource(void) * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ static int s32k1xx_sirc_config(bool enable, const struct scg_sirc_config_s *sirccfg) @@ -928,7 +929,7 @@ static int s32k1xx_sirc_config(bool enable, * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ static int s32k1xx_sosc_config(bool enable, const struct scg_sosc_config_s *sosccfg) @@ -1058,7 +1059,7 @@ static int s32k1xx_sosc_config(bool enable, * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_HAVE_SPLL static int s32k1xx_spll_config(bool enable, @@ -1151,6 +1152,7 @@ static int s32k1xx_spll_config(bool enable, break; default: + /* Invalid monitor mode */ DEBUGPANIC(); @@ -1188,7 +1190,7 @@ static int s32k1xx_spll_config(bool enable, * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg) { @@ -1203,12 +1205,12 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg) ret = s32k1xx_sirc_config(scgcfg->sirc.initialize, &scgcfg->sirc); if (ret == OK) { - ret = s32k1xx_sosc_config(scgcfg->sosc.initialize, &scgcfg->sosc); + ret = s32k1xx_sosc_config(scgcfg->sosc.initialize, &scgcfg->sosc); #ifdef CONFIG_S32K1XX_HAVE_SPLL - if (ret == OK) - { - ret = s32k1xx_spll_config(scgcfg->spll.initialize, &scgcfg->spll); - } + if (ret == OK) + { + ret = s32k1xx_spll_config(scgcfg->spll.initialize, &scgcfg->spll); + } #endif } @@ -1298,7 +1300,8 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg) { /* Configure the remaining clock source (FIRC). */ - ret = s32k1xx_firc_config(scgcfg->firc.initialize, &scgcfg->firc); + ret = s32k1xx_firc_config(scgcfg->firc.initialize, + &scgcfg->firc); if (ret == OK) { /* Transition to the next system clock source. */ @@ -1325,7 +1328,8 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg) { /* Configure the remaining clock source (FIRC) */ - ret = s32k1xx_firc_config(scgcfg->firc.initialize, &scgcfg->firc); + ret = s32k1xx_firc_config(scgcfg->firc.initialize, + &scgcfg->firc); } } } @@ -1346,7 +1350,7 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg) * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ static int s32k1xx_scg_config(const struct scg_config_s *scgcfg) { @@ -1414,7 +1418,7 @@ static int s32k1xx_scg_config(const struct scg_config_s *scgcfg) } } - return ret; + return ret; } /**************************************************************************** @@ -1429,7 +1433,7 @@ static int s32k1xx_scg_config(const struct scg_config_s *scgcfg) * Returned Value: * None. * - *****************************************************************************/ + ****************************************************************************/ static void s32k1xx_sim_config(const struct sim_clock_config_s *simcfg) { @@ -1590,7 +1594,7 @@ static void s32k1xx_sim_config(const struct sim_clock_config_s *simcfg) * Returned Value: * None. * - *****************************************************************************/ + ****************************************************************************/ static void s32k1xx_pmc_config(const struct pmc_config_s *pmccfg) { @@ -1643,7 +1647,7 @@ static void s32k1xx_pmc_config(const struct pmc_config_s *pmccfg) * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ int s32k1xx_clockconfig(const struct clock_configuration_s *clkcfg) { @@ -1685,7 +1689,7 @@ int s32k1xx_clockconfig(const struct clock_configuration_s *clkcfg) * The current value of the CORE clock frequency. Zero is returned on any * failure. * - *****************************************************************************/ + ****************************************************************************/ uint32_t s32k1xx_get_coreclk(void) { @@ -1722,7 +1726,7 @@ uint32_t s32k1xx_get_coreclk(void) /* Slow IRC high range clock (8 MHz ) */ - coreclk = SCG_SIRQ_HIGHRANGE_FREQUENCY; + coreclk = SCG_SIRC_HIGHRANGE_FREQUENCY; break; case SCG_CSR_SCS_FIRC: /* Fast IRC */ @@ -1734,7 +1738,7 @@ uint32_t s32k1xx_get_coreclk(void) /* Fast IRC is trimmed to 48 MHz */ - coreclk = SCG_FIRQ_FREQUENCY0; + coreclk = SCG_FIRC_FREQUENCY0; break; #ifdef CONFIG_S32K1XX_HAVE_SPLL @@ -1767,10 +1771,10 @@ uint32_t s32k1xx_get_coreclk(void) * type - Identifies the system clock of interest * * Returned Values: - * The current value of the system clock frequency. Zero is returned on any - * failure. + * The current value of the system clock frequency. Zero is returned on + * any failure. * - *****************************************************************************/ + ****************************************************************************/ uint32_t s32k1xx_get_sysclk(enum scg_system_clock_type_e type) { @@ -1937,6 +1941,7 @@ uint32_t s32k1xx_get_asnchfreq(enum clock_names_e clksrc, break; default: + /* Invalid async clock source */ freq = 0; diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h index cfbbe26e68c..dc2c7c8b3a0 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h +++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h @@ -76,9 +76,9 @@ /* Nomial frequencies of internal clocks */ -#define SCG_SIRQ_LOWRANGE_FREQUENCY 2000000 /* 2MHz */ -#define SCG_SIRQ_HIGHRANGE_FREQUENCY 8000000 /* 8MHz */ -#define SCG_FIRQ_FREQUENCY0 48000000 /* 48MHz */ +#define SCG_SIRC_LOWRANGE_FREQUENCY 2000000 /* 2MHz */ +#define SCG_SIRC_HIGHRANGE_FREQUENCY 8000000 /* 8MHz */ +#define SCG_FIRC_FREQUENCY0 48000000 /* 48MHz */ #define NUMBER_OF_TCLK_INPUTS 3 @@ -479,7 +479,7 @@ extern "C" * Zero (OK) is returned a success; A negated errno value is returned on * any failure. * - *****************************************************************************/ + ****************************************************************************/ int s32k1xx_clockconfig(FAR const struct clock_configuration_s *clkcfg); @@ -496,7 +496,7 @@ int s32k1xx_clockconfig(FAR const struct clock_configuration_s *clkcfg); * The current value of the CORE clock frequency. Zero is returned on any * failure. * - *****************************************************************************/ + ****************************************************************************/ uint32_t s32k1xx_get_coreclk(void); @@ -511,10 +511,10 @@ uint32_t s32k1xx_get_coreclk(void); * type - Identifies the system clock of interest * * Returned Values: - * The current value of the system clock frequency. Zero is returned on any - * failure. + * The current value of the system clock frequency. Zero is returned on + * any failure. * - *****************************************************************************/ + ****************************************************************************/ uint32_t s32k1xx_get_sysclk(enum scg_system_clock_type_e type); diff --git a/arch/arm/src/s32k1xx/s32k1xx_enet.c b/arch/arm/src/s32k1xx/s32k1xx_enet.c index 2f5e719734d..682cd4f2654 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_enet.c +++ b/arch/arm/src/s32k1xx/s32k1xx_enet.c @@ -207,6 +207,15 @@ # define BOARD_PHY_10BASET(s) (((s)&MII_LAN8720_SPSCR_10MBPS) != 0) # define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0) # define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0) +#elif defined(CONFIG_ETH0_PHY_TJA1101) +# define BOARD_PHY_NAME "TJA1101" +# define BOARD_PHYID1 MII_PHYID1_TJA1101 +# define BOARD_PHYID2 MII_PHYID2_TJA1101 +# define BOARD_PHY_STATUS MII_TJA110X_BSR +# define BOARD_PHY_ADDR (0) +# define BOARD_PHY_10BASET(s) 0 /* PHY only supports 100BASE-T1 */ +# define BOARD_PHY_100BASET(s) 1 /* PHY only supports 100BASE-T1 */ +# define BOARD_PHY_ISDUPLEX(s) 1 /* PHY only supports fullduplex */ #else # error "Unrecognized or missing PHY selection" #endif @@ -222,7 +231,7 @@ * = 23 */ -#define S32K1XX_MII_SPEED 0x38 /* 100Mbs. Revisit and remove hardcoded value */ +#define S32K1XX_MII_SPEED 0x0f /* 100Mbs. Revisit and remove hardcoded value */ #if S32K1XX_MII_SPEED > 63 # error "S32K1XX_MII_SPEED is out-of-range" #endif @@ -251,8 +260,8 @@ * Private Types ****************************************************************************/ -/* The s32k1xx_driver_s encapsulates all state information for a single hardware - * interface +/* The s32k1xx_driver_s encapsulates all state information for a single + * hardware interface */ struct s32k1xx_driver_s @@ -328,7 +337,8 @@ static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv); static void s32k1xx_txdone(FAR struct s32k1xx_driver_s *priv); static void s32k1xx_enet_interrupt_work(FAR void *arg); -static int s32k1xx_enet_interrupt(int irq, FAR void *context, FAR void *arg); +static int s32k1xx_enet_interrupt(int irq, FAR void *context, + FAR void *arg); /* Watchdog timer expirations */ @@ -537,13 +547,13 @@ static int s32k1xx_transmit(FAR struct s32k1xx_driver_s *priv) buf = (uint8_t *)s32k1xx_swap32((uint32_t)priv->dev.d_buf); if (priv->rxdesc[priv->rxtail].data == buf) { - struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail]; + struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail]; - /* Data was written into the RX buffer, so swap the TX and RX buffers */ + /* Data was written into the RX buffer, so swap the TX and RX buffers */ - DEBUGASSERT((rxdesc->status1 & RXDESC_E) == 0); - rxdesc->data = txdesc->data; - txdesc->data = buf; + DEBUGASSERT((rxdesc->status1 & RXDESC_E) == 0); + rxdesc->data = txdesc->data; + txdesc->data = buf; } else { @@ -647,11 +657,11 @@ static int s32k1xx_txpoll(struct net_driver_s *dev) { return -EBUSY; } - } + } } - /* If zero is returned, the polling will continue until all connections have - * been examined. + /* If zero is returned, the polling will continue until all connections + * have been examined. */ return 0; @@ -684,7 +694,7 @@ static inline void s32k1xx_dispatch(FAR struct s32k1xx_driver_s *priv) #ifdef CONFIG_NET_PKT /* When packet sockets are enabled, feed the frame into the packet tap */ - pkt_input(&priv->dev); + pkt_input(&priv->dev); #endif #ifdef CONFIG_NET_IPv4 @@ -842,7 +852,8 @@ static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv) */ priv->dev.d_len = s32k1xx_swap16(rxdesc->length); - priv->dev.d_buf = (uint8_t *)s32k1xx_swap32((uint32_t)rxdesc->data); + priv->dev.d_buf = + (uint8_t *)s32k1xx_swap32((uint32_t)rxdesc->data); /* Invalidate the buffer so that the correct packet will be re-read * from memory when the packet content is accessed. @@ -1080,7 +1091,8 @@ static void s32k1xx_enet_interrupt_work(FAR void *arg) #if 0 up_enable_irq(S32K1XX_IRQ_EMACTMR); #endif - up_enable_irq(S32K1XX_IRQ_ENET); + up_enable_irq(S32K1XX_IRQ_ENET_TXDONE); + up_enable_irq(S32K1XX_IRQ_ENET_RXDONE); } /**************************************************************************** @@ -1112,7 +1124,8 @@ static int s32k1xx_enet_interrupt(int irq, FAR void *context, FAR void *arg) * condition here. */ - up_disable_irq(S32K1XX_IRQ_ENET); + up_disable_irq(S32K1XX_IRQ_ENET_TXDONE); + up_disable_irq(S32K1XX_IRQ_ENET_RXDONE); /* Schedule to perform the interrupt processing on the worker thread. */ @@ -1188,7 +1201,8 @@ static void s32k1xx_txtimeout_expiry(int argc, uint32_t arg, ...) * condition with interrupt work that is already queued and in progress. */ - up_disable_irq(S32K1XX_IRQ_ENET); + up_disable_irq(S32K1XX_IRQ_ENET_TXDONE); + up_disable_irq(S32K1XX_IRQ_ENET_RXDONE); /* Schedule to perform the TX timeout processing on the worker thread, * canceling any pending interrupt work. @@ -1218,8 +1232,9 @@ static void s32k1xx_poll_work(FAR void *arg) { FAR struct s32k1xx_driver_s *priv = (FAR struct s32k1xx_driver_s *)arg; - /* Check if there is there is a transmission in progress. We cannot perform - * the TX poll if he are unable to accept another packet for transmission. + /* Check if there is there is a transmission in progress. We cannot + * perform the TX poll if he are unable to accept another packet for + * transmission. */ net_lock(); @@ -1372,7 +1387,8 @@ static int s32k1xx_ifup_action(struct net_driver_s *dev, bool resetphy) /* Clear all pending ENET interrupt */ - putreg32(RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS, S32K1XX_ENET_EIR); + putreg32(RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS, + S32K1XX_ENET_EIR); /* Enable RX and error interrupts at the controller (TX interrupts are * still disabled). @@ -1388,7 +1404,8 @@ static int s32k1xx_ifup_action(struct net_driver_s *dev, bool resetphy) #if 0 up_enable_irq(S32K1XX_IRQ_EMACTMR); #endif - up_enable_irq(S32K1XX_IRQ_ENET); + up_enable_irq(S32K1XX_IRQ_ENET_TXDONE); + up_enable_irq(S32K1XX_IRQ_ENET_RXDONE); return OK; } @@ -1447,7 +1464,8 @@ static int s32k1xx_ifdown(struct net_driver_s *dev) flags = enter_critical_section(); - up_disable_irq(S32K1XX_IRQ_ENET); + up_disable_irq(S32K1XX_IRQ_ENET_TXDONE); + up_disable_irq(S32K1XX_IRQ_ENET_RXDONE); putreg32(0, S32K1XX_ENET_EIMR); /* Cancel the TX poll timer and TX timeout timers */ @@ -1550,6 +1568,7 @@ static int s32k1xx_txavail(struct net_driver_s *dev) return OK; } + /**************************************************************************** * Function: s32k1xx_calcethcrc * @@ -1597,7 +1616,7 @@ static uint32_t s32k1xx_calcethcrc(const uint8_t *data, size_t length) } return crc; - } +} #endif /**************************************************************************** @@ -1747,7 +1766,8 @@ static int s32k1xx_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) ****************************************************************************/ #ifdef CONFIG_NETDEV_IOCTL -static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) +static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg) { #ifdef CONFIG_NETDEV_PHY_IOCTL FAR struct s32k1xx_driver_s *priv = @@ -1788,7 +1808,8 @@ static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - ret = s32k1xx_readmii(priv, req->phy_id, req->reg_num, &req->val_out); + ret = + s32k1xx_readmii(priv, req->phy_id, req->reg_num, &req->val_out); } break; @@ -1796,7 +1817,8 @@ static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - ret = s32k1xx_writemii(priv, req->phy_id, req->reg_num, req->val_in); + ret = + s32k1xx_writemii(priv, req->phy_id, req->reg_num, req->val_in); } break; #endif /* CONFIG_NETDEV_PHY_IOCTL */ @@ -1880,8 +1902,7 @@ static void s32k1xx_initmii(struct s32k1xx_driver_s *priv) * clock. This hold time value may need to be increased on some platforms */ - putreg32(ENET_MSCR_HOLDTIME_2CYCLES | - S32K1XX_MII_SPEED << ENET_MSCR_MII_SPEED_SHIFT, + putreg32(S32K1XX_MII_SPEED << ENET_MSCR_MII_SPEED_SHIFT, S32K1XX_ENET_MSCR); } @@ -2025,7 +2046,8 @@ static int s32k1xx_readmii(struct s32k1xx_driver_s *priv, uint8_t phyaddr, * ****************************************************************************/ -static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy) +static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, + bool renogphy) { uint32_t rcr; uint32_t tcr; @@ -2037,9 +2059,10 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy) if (renogphy) { - /* Loop (potentially infinitely?) until we successfully communicate with - * the PHY. This is 'standard stuff' that should work for any PHY - we - * are not communicating with it's 'special' registers at this point. + /* Loop (potentially infinitely?) until we successfully communicate + * with the PHY. This is 'standard stuff' that should work for any PHY + * - we are not communicating with it's 'special' registers at this + * point. */ ninfo("%s: Try phyaddr: %u\n", BOARD_PHY_NAME, phyaddr); @@ -2061,7 +2084,8 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy) if (retries >= 3) { - nerr("ERROR: Failed to read %s PHYID1 at address %d\n", BOARD_PHY_NAME, phyaddr); + nerr("ERROR: Failed to read %s PHYID1 at address %d\n", + BOARD_PHY_NAME, phyaddr); return -ENOENT; } @@ -2145,15 +2169,15 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy) #elif defined (CONFIG_ETH0_PHY_LAN8720) - /* Make sure that PHY comes up in correct mode when it's reset */ + /* Make sure that PHY comes up in correct mode when it's reset */ - s32k1xx_writemii(priv, phyaddr, MII_LAN8720_MODES, - MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL | - MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR)); + s32k1xx_writemii(priv, phyaddr, MII_LAN8720_MODES, + MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL | + MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR)); - /* ...and reset PHY */ + /* ...and reset PHY */ - s32k1xx_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); + s32k1xx_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); #endif /* Start auto negotiation */ @@ -2227,17 +2251,17 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy) { if (renogphy == false) { - /* Give things one more chance with renegociation turned on */ + /* Give things one more chance with renegociation turned on */ return s32k1xx_initphy(priv, true); } else { - /* That didn't end well, just give up */ + /* That didn't end well, just give up */ - nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n", - BOARD_PHY_NAME, BOARD_PHY_STATUS, ret); - return ret; + nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n", + BOARD_PHY_NAME, BOARD_PHY_STATUS, ret); + return ret; } } @@ -2261,12 +2285,12 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy) putreg32(rcr, S32K1XX_ENET_RCR); putreg32(tcr, S32K1XX_ENET_TCR); - /* Enable Discard Of Frames With MAC Layer Errors. + /* Do not Discard Of Frames With MAC Layer Errors. * Enable Discard Of Frames With Wrong Protocol Checksum. * Bit 1: Enable discard of frames with wrong IPv4 header checksum. */ - racc = ENET_RACC_PRODIS | ENET_RACC_LINEDIS | ENET_RACC_IPDIS; + racc = ENET_RACC_PRODIS | ENET_RACC_IPDIS; putreg32(racc, S32K1XX_ENET_RACC); /* Setup half or full duplex */ @@ -2308,6 +2332,45 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy) return -EIO; } +#if defined(CONFIG_ETH0_PHY_TJA1101) +/* The NXP TJA110X PHY is an automotive 100BASE-T1 PHY + * Which requires additional initialization + */ + + /* select mode TJA110X */ + + s32k1xx_writemii(priv, phyaddr, MII_TJA110X_EXT_CNTRL, + (MII_EXT_CNTRL_NORMAL | MII_EXT_CNTRL_CONFIG_EN | + MII_EXT_CNTRL_CONFIG_INH)); + +# if defined(CONFIG_PHY_100BASE_T1_MASTER) + /* Set TJA110X in master mode */ + + s32k1xx_writemii(priv, phyaddr, MII_TJA110X_CONFIG1, + (MII_CONFIG1_MASTER | MII_CONFIG1_TX_1250MV | + MII_CONFIG1_RMII_25MHZ | MII_CONFIG1_LED_EN)); +# else + /* Set TJA110X in slave mode */ + + s32k1xx_writemii(priv, phyaddr, MII_TJA110X_CONFIG1, + (MII_CONFIG1_TX_1250MV | MII_CONFIG1_RMII_25MHZ | + MII_CONFIG1_LED_EN)); +# endif + + s32k1xx_writemii(priv, phyaddr, MII_TJA110X_CONFIG2, + (MII_CONFIG2_SNR_AV64 | MII_CONFIG2_WLIM_D | + MII_CONFIG2_SNR_F_NL | MII_CONFIG2_SLP_T_1)); + + /* Select normal mode TJA110X */ + + s32k1xx_writemii(priv, phyaddr, MII_TJA110X_EXT_CNTRL, + (MII_EXT_CNTRL_NORMAL | MII_EXT_CNTRL_CONFIG_INH)); + + s32k1xx_writemii(priv, phyaddr, MII_TJA110X_EXT_CNTRL, + (MII_EXT_CNTRL_LINK_CNTRL | MII_EXT_CNTRL_NORMAL | + MII_EXT_CNTRL_CONFIG_INH)); +#endif + putreg32(rcr, S32K1XX_ENET_RCR); putreg32(tcr, S32K1XX_ENET_TCR); return OK; @@ -2453,7 +2516,6 @@ int s32k1xx_netinitialize(int intf) uint32_t uidml; uint8_t *mac; #endif - uint32_t regval; int ret; /* Get the interface structure associated with this interface number. */ @@ -2471,11 +2533,12 @@ int s32k1xx_netinitialize(int intf) s32k1xx_pinconfig(PIN_RMII_MDIO); s32k1xx_pinconfig(PIN_RMII_RX_DV); s32k1xx_pinconfig(PIN_RMII_RX_ER); - s32k1xx_pinconfig(PIN_RMII_RX_EN); - s32k1xx_pinconfig(PIN_RMII_RXD); + s32k1xx_pinconfig(PIN_RMII_RXD0); + s32k1xx_pinconfig(PIN_RMII_RXD1); s32k1xx_pinconfig(PIN_RMII_TX_CLK); s32k1xx_pinconfig(PIN_RMII_TX_EN); - s32k1xx_pinconfig(PIN_RMII_TXD); + s32k1xx_pinconfig(PIN_RMII_TXD0); + s32k1xx_pinconfig(PIN_RMII_TXD1); #if 0 /* Configure all ENET/MII pins */ @@ -2512,7 +2575,7 @@ int s32k1xx_netinitialize(int intf) /* Attach the Ethernet interrupt handler */ - if (irq_attach(S32K1XX_IRQ_ENET, s32k1xx_enet_interrupt, NULL)) + if (irq_attach(S32K1XX_IRQ_ENET_TXDONE, s32k1xx_enet_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -2520,6 +2583,14 @@ int s32k1xx_netinitialize(int intf) return -EAGAIN; } + if (irq_attach(S32K1XX_IRQ_ENET_RXDONE, s32k1xx_enet_interrupt, NULL)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach EMACRX IRQ\n"); + return -EAGAIN; + } + /* Initialize the driver structure */ memset(priv, 0, sizeof(struct s32k1xx_driver_s)); @@ -2543,14 +2614,14 @@ int s32k1xx_netinitialize(int intf) #ifdef CONFIG_NET_ETHERNET /* Determine a semi-unique MAC address from MCU UID * We use UID Low and Mid Low registers to get 64 bits, from which we keep - * 48 bits. We then force unicast and locally administered bits (b0 and b1, - * 1st octet) + * 48 bits. We then force unicast and locally administered bits (b0 and + * b1, 1st octet) */ /* hardcoded offset: todo: need proper header file */ - uidl = getreg32(S32K1XX_OCOTP_BASE + 0x410); - uidml = getreg32(S32K1XX_OCOTP_BASE + 0x420); + uidl = getreg32(S32K1XX_SIM_BASE + 0x60); + uidml = getreg32(S32K1XX_SIM_BASE + 0x5c); mac = priv->dev.d_mac.ether.ether_addr_octet; uidml |= 0x00000200; diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c b/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c index 135697291fe..d7fca330963 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c @@ -893,7 +893,7 @@ static void s32k1xx_lpi2c_tracedump(FAR struct s32k1xx_lpi2c_priv_s *priv) } #endif /* CONFIG_I2C_TRACE */ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpi2c_pckfreq * * Description: @@ -903,9 +903,10 @@ static void s32k1xx_lpi2c_tracedump(FAR struct s32k1xx_lpi2c_priv_s *priv) * base - The base address of the LPI2C peripheral registers * * Returned Value: - * The frequency of the LPI2C functional input frequency (or zero on a failure) + * The frequency of the LPI2C functional input frequency (or zero on a + * failure) * - ************************************************************************************/ + ****************************************************************************/ static uint32_t s32k1xx_lpi2c_pckfreq(uintptr_t base) { @@ -1062,7 +1063,8 @@ static void s32k1xx_lpi2c_setclock(FAR struct s32k1xx_lpi2c_priv_s *priv, } } - s32k1xx_lpi2c_modifyreg(priv, S32K1XX_LPI2C_MCFGR1_OFFSET, 0, + s32k1xx_lpi2c_modifyreg(priv, S32K1XX_LPI2C_MCFGR1_OFFSET, + LPI2C_MCFGR1_PRESCALE_MASK, LPI2C_MCFGR1_PRESCALE(best_prescale)); /* Re-enable LPI2C if it was enabled previously */ @@ -1173,11 +1175,17 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv) s32k1xx_lpi2c_tracenew(priv, status); - /* Continue with either sending or reading data */ + /* After an error we can get an SDF */ + + if (priv->intstate == INTSTATE_DONE && (status & LPI2C_MSR_SDF) != 0) + { + s32k1xx_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + s32k1xx_lpi2c_putreg(priv, S32K1XX_LPI2C_MSR_OFFSET, LPI2C_MSR_SDF); + } /* Check if there is more bytes to send */ - if (((priv->flags & I2C_M_READ) == 0) && (status & LPI2C_MSR_TDF) != 0) + else if (((priv->flags & I2C_M_READ) == 0) && (status & LPI2C_MSR_TDF) != 0) { if (priv->dcnt > 0) { @@ -1242,7 +1250,8 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv) if ((priv->msgv->flags & I2C_M_NOSTART) == 0) { - s32k1xx_lpi2c_traceevent(priv, I2CEVENT_STARTRESTART, priv->msgc); + s32k1xx_lpi2c_traceevent(priv, I2CEVENT_STARTRESTART, + priv->msgc); s32k1xx_lpi2c_sendstart(priv, priv->msgv->addr); } else @@ -1285,13 +1294,18 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv) else if (priv->msgv && ((status & LPI2C_MSR_SDF) != 0)) { s32k1xx_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); - s32k1xx_lpi2c_putreg(priv, S32K1XX_LPI2C_MSR_OFFSET, LPI2C_MSR_SDF); + s32k1xx_lpi2c_putreg(priv, S32K1XX_LPI2C_MSR_OFFSET, + LPI2C_MSR_SDF); /* Check is there thread waiting for this event (there should be) */ #ifndef CONFIG_I2C_POLLED if (priv->intstate == INTSTATE_WAITING) { + /* Update Status once at the end */ + + priv->status = status; + /* inform the thread that transfer is complete * and wake it up */ @@ -1300,6 +1314,7 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv) priv->intstate = INTSTATE_DONE; } #else + priv->status = status; priv->intstate = INTSTATE_DONE; #endif /* Mark that this transaction stopped */ @@ -1340,6 +1355,10 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED if (priv->intstate == INTSTATE_WAITING) { + /* Update Status once at the end */ + + priv->status = status; + /* inform the thread that transfer is complete * and wake it up */ @@ -1348,11 +1367,11 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv) priv->intstate = INTSTATE_DONE; } #else + priv->status = status; priv->intstate = INTSTATE_DONE; #endif } - priv->status = status; return OK; } @@ -1386,8 +1405,8 @@ static int s32k1xx_lpi2c_init(FAR struct s32k1xx_lpi2c_priv_s *priv) { /* Power-up and configure GPIOs . * - * NOTE: Clocking to the LPSPI peripheral must be provided by board-specific logic - * as part of the clock configuration logic. + * NOTE: Clocking to the LPSPI peripheral must be provided by + * board-specific logic as part of the clock configuration logic. */ /* Configure pins */ @@ -1746,13 +1765,13 @@ FAR struct i2c_master_s *s32k1xx_i2cbus_initialize(int port) switch (port) { #ifdef CONFIG_S32K1XX_LPI2C0 - case 1: + case 0: priv = (struct s32k1xx_lpi2c_priv_s *)&s32k1xx_lpi2c0_priv; break; #endif #ifdef CONFIG_S32K1XX_LPI2C1 - case 2: + case 1: priv = (struct s32k1xx_lpi2c_priv_s *)&s32k1xx_lpi2c1_priv; break; #endif diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c index f9e7d1e3bfd..5fad2a6d551 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c @@ -35,23 +35,23 @@ ************************************************************************************/ /************************************************************************************ - * The external functions, s32k1xx_lpspi1/2/3/4select and s32k1xx_lpspi1/2/3/4status + * The external functions, s32k1xx_lpspi0/1/2select and s32k1xx_lpspi0/1/2status * must be provided by board-specific logic. They are implementations of the select * and status methods of the SPI interface defined by struct s32k1xx_lpspi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including s32k1xx_lpspibus_initialize()) - * are provided by common S32K1XX logic. To use this common SPI logic on your - * board: + * include/nuttx/spi/spi.h). All other methods (including + * s32k1xx_lpspibus_initialize()) are provided by common S32K1XX logic. To use this + * common SPI logic on your board: * * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip select * pins. - * 2. Provide s32k1xx_lpspi1/2/3/4select() and s32k1xx_lpspi1/2/3/4status() + * 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status() * functions in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. * 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level application * initialization logic - * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used to bind + * the SPI driver to higher level logic (e.g., calling * mmcsd_lpspislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * @@ -89,7 +89,8 @@ #include -#ifdef CONFIG_S32K1XX_LPSPI +#if defined(CONFIG_S32K1XX_LPSPI0) || defined(CONFIG_S32K1XX_LPSPI1) || \ + defined(CONFIG_S32K1XX_LPSPI2) /************************************************************************************ * Pre-processor Definitions @@ -952,8 +953,7 @@ static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev, s32k1xx_lpspi_putreg32(priv, S32K1XX_LPSPI_CCR_OFFSET, regval); s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, - LPSPI_TCR_PRESCALE_MASK, 0); - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, 0, + LPSPI_TCR_PRESCALE_MASK, LPSPI_TCR_PRESCALE(best_prescaler)); priv->frequency = frequency; @@ -970,7 +970,8 @@ static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev, if (men) { - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); + s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, 0, + LPSPI_CR_MEN); } } @@ -1090,7 +1091,6 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) if (nbits != priv->nbits) { - if (nbits < 2 || nbits > 4096) { return; @@ -1124,7 +1124,7 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) } } -/**************************************************************************** +/************************************************************************************ * Name: s32k1xx_lpspi_hwfeatures * * Description: @@ -1138,7 +1138,7 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) * Zero (OK) if the selected H/W features are enabled; A negated errno * value if any H/W feature is not supportable. * - ****************************************************************************/ + ************************************************************************************/ #ifdef CONFIG_SPI_HWFEATURES static int s32k1xx_lpspi_hwfeatures(FAR struct spi_dev_s *dev, @@ -1232,7 +1232,8 @@ static uint16_t s32k1xx_lpspi_send(FAR struct spi_dev_s *dev, uint16_t wd) * nwords - the length of data to be exchaned in units of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's * * Returned Value: * None @@ -1326,7 +1327,7 @@ static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, } #endif /* !CONFIG_S32K1XX_LPSPI_DMA || CONFIG_S32K1XX_DMACAPABLE */ -/**************************************************************************** +/************************************************************************************ * Name: s32k1xx_lpspi_sndblock * * Description: @@ -1338,7 +1339,8 @@ static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, * nwords - the length of data to send from the buffer in number of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's * * Returned Value: * None @@ -1366,7 +1368,8 @@ static void s32k1xx_lpspi_sndblock(FAR struct spi_dev_s *dev, * nwords - the length of data that can be received in the buffer in number * of words. The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's * * Returned Value: * None @@ -1386,7 +1389,8 @@ static void s32k1xx_lpspi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffe * Name: s32k1xx_lpspi_bus_initialize * * Description: - * Initialize the selected SPI bus in its default state (Master, 8-bit, mode 0, etc.) + * Initialize the selected SPI bus in its default state (Master, 8-bit, mode 0, + * etc.) * * Input Parameters: * priv - private SPI device structure @@ -1417,6 +1421,7 @@ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv) LPSPI_CFGR1_MASTER); /* Set specific PCS to active high or low */ + /* TODO: Not needed for now */ /* Set Configuration Register 1 related setting. */ @@ -1556,4 +1561,4 @@ FAR struct spi_dev_s *s32k1xx_lpspibus_initialize(int bus) return (FAR struct spi_dev_s *)priv; } -#endif /* CONFIG_S32K1XX_LPSPI */ +#endif /* CONFIG_S32K1XX_LPSPI0 || CONFIG_S32K1XX_LPSPI1 || CONFIG_S32K1XX_LPSPI2 */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_pin.h b/arch/arm/src/s32k1xx/s32k1xx_pin.h index 497136306b5..ac41b130ec3 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pin.h +++ b/arch/arm/src/s32k1xx/s32k1xx_pin.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/s32k1xx/s32k1xx.h + * arch/arm/src/s32k1xx/s32k1xx_pin.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt @@ -57,6 +57,7 @@ ************************************************************************************/ /* Bit-encoded input to s32k1xx_pinconfig() *****************************************/ + /* General form (32-bits, only 22 bits are unused in the encoding): * * oooo mmmv iiii ifd- ---- -ppp ---b bbbb @@ -75,7 +76,9 @@ #define _PIN_OPTIONS_MASK (15 << _PIN_OPTIONS_SHIFT) /* Port Modes */ - /* Unshifted versions: */ + +/* Unshifted versions: */ + #define PIN_MODE_ANALOG (0) /* 000 Pin Disabled (Analog) */ #define PIN_MODE_ALT1 (1) /* 001 Alternative 1 */ #define PIN_MODE_GPIO PIN_MODE_ALT1 /* 001 Alternative 1 (GPIO) */ @@ -85,7 +88,9 @@ #define PIN_MODE_ALT5 (5) /* 101 Alternative 5 */ #define PIN_MODE_ALT6 (6) /* 110 Alternative 6 */ #define PIN_MODE_ALT7 (7) /* 111 Alternative 7 */ - /* Shifted versions: */ + +/* Shifted versions: */ + #define _PIN_MODE_ANALOG (0 << _PIN_MODE_SHIFT) /* 000 Pin Disabled (Analog) */ #define _PIN_MODE_ALT1 (1 << _PIN_MODE_SHIFT) /* 001 Alternative 1 */ #define _PIN_MODE_GPIO (1 << _PIN_MODE_SHIFT) /* 001 Alternative 1 (GPIO) */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_pinirq.c b/arch/arm/src/s32k1xx/s32k1xx_pinirq.c index db990bd99f9..74b3ef754fd 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pinirq.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pinirq.c @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "s32k1xx.h" +#include "s32k1xx_pin.h" #include "hardware/s32k1xx_port.h" #ifdef CONFIG_S32K1XX_GPIOIRQ @@ -86,6 +86,7 @@ struct s32k1xx_pinirq_s /**************************************************************************** * Private Data ****************************************************************************/ + /* Per pin port interrupt vectors. NOTE: Not all pins in each port * correspond to externally available GPIOs. However, I believe that the * Kinesis will support interrupts even if the pin is not available as @@ -123,7 +124,8 @@ static struct s32k1xx_pinirq_s g_porteisrs[32]; #ifdef HAVE_PORTINTS static int s32k1xx_portinterrupt(int irq, FAR void *context, - uintptr_t addr, struct s32k1xx_pinirq_s *isrtab) + uintptr_t addr, + struct s32k1xx_pinirq_s *isrtab) { uint32_t isfr = getreg32(addr); int i; @@ -184,31 +186,40 @@ static int s32k1xx_portinterrupt(int irq, FAR void *context, #ifdef CONFIG_S32K1XX_PORTAINTS static int s32k1xx_portainterrupt(int irq, FAR void *context, FAR void *arg) { - return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTA_ISFR, g_portaisrs); + return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTA_ISFR, + g_portaisrs); } #endif + #ifdef CONFIG_S32K1XX_PORTBINTS static int s32k1xx_portbinterrupt(int irq, FAR void *context, FAR void *arg) { - return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTB_ISFR, g_portbisrs); + return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTB_ISFR, + g_portbisrs); } #endif + #ifdef CONFIG_S32K1XX_PORTCINTS static int s32k1xx_portcinterrupt(int irq, FAR void *context, FAR void *arg) { - return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTC_ISFR, g_portcisrs); + return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTC_ISFR, + g_portcisrs); } #endif + #ifdef CONFIG_S32K1XX_PORTDINTS static int s32k1xx_portdinterrupt(int irq, FAR void *context, FAR void *arg) { - return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTD_ISFR, g_portdisrs); + return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTD_ISFR, + g_portdisrs); } #endif + #ifdef CONFIG_S32K1XX_PORTEINTS static int s32k1xx_porteinterrupt(int irq, FAR void *context, FAR void *arg) { - return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTE_ISFR, g_porteisrs); + return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTE_ISFR, + g_porteisrs); } #endif @@ -276,7 +287,7 @@ void s32k1xx_pinirq_initialize(void) * Zero (OK) is returned on success; a negated errno value is returned on * any failure to indicate the nature of the failure. * - *******************************************************************************/ + ****************************************************************************/ int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg) { @@ -286,8 +297,8 @@ int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg) unsigned int port; unsigned int pin; - /* It only makes sense to call this function for input pins that are configured - * as interrupts. + /* It only makes sense to call this function for input pins that are + * configured as interrupts. */ DEBUGASSERT((pinset & _PIN_INTDMA_MASK) == _PIN_INTERRUPT); @@ -334,27 +345,27 @@ int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg) return -EINVAL; } - /* Get the old PIN ISR and set the new PIN ISR */ + /* Get the old PIN ISR and set the new PIN ISR */ - isrtab[pin].handler = pinisr; - isrtab[pin].arg = arg; + isrtab[pin].handler = pinisr; + isrtab[pin].arg = arg; - /* And return the old PIN isr address */ + /* And return the old PIN isr address */ - leave_critical_section(flags); - return OK; + leave_critical_section(flags); + return OK; #else - return -ENOSYS; + return -ENOSYS; #endif /* HAVE_PORTINTS */ } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pinirqenable * * Description: * Enable the interrupt for specified pin IRQ * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_pinirqenable(uint32_t pinset) { @@ -426,13 +437,13 @@ void s32k1xx_pinirqenable(uint32_t pinset) #endif /* HAVE_PORTINTS */ } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pinirqdisable * * Description: * Disable the interrupt for specified pin * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_pinirqdisable(uint32_t pinset) { diff --git a/arch/arm/src/s32k1xx/s32k1xx_rtc.c b/arch/arm/src/s32k1xx/s32k1xx_rtc.c new file mode 100644 index 00000000000..1bc1dc994b9 --- /dev/null +++ b/arch/arm/src/s32k1xx/s32k1xx_rtc.c @@ -0,0 +1,267 @@ +/**************************************************************************** + * arch/arm/src/s32k1xx/s32k1xx_rtc.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "up_arch.h" + +#include "hardware/s32k1xx_rtc.h" +#include "s32k1xx_periphclocks.h" +#include "s32k1xx_rtc.h" + +#ifdef CONFIG_S32K1XX_RTC + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Variable determines the state of the RTC module. + * + * After initialization value is set to 'true' if RTC starts successfully. + * The value can be changed to false also during operation if RTC for + * some reason fails. + */ + +volatile bool g_rtc_enabled = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_rtc_enable + * + * Description: + * Enable/start the LPRTC time counter. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void s32k1xx_rtc_enable(void) +{ + uint32_t regval; + + /* Enable the rtc */ + + regval = getreg32(S32K1XX_RTC_SR); + regval |= RTC_SR_TCE; + putreg32(regval, S32K1XX_RTC_SR); +} + +/**************************************************************************** + * Name: s32k1xx_rtc_disable + * + * Description: + * disable the LPRTC time counter. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void s32k1xx_rtc_disable(void) +{ + uint32_t regval; + + /* Enable the rtc */ + + regval = getreg32(S32K1XX_RTC_SR); + regval &= ~RTC_SR_TCE; + putreg32(regval, S32K1XX_RTC_SR); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the rtc per the selected configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + uint32_t regval; + + /* Disable the clock out pin */ + + regval = getreg32(S32K1XX_RTC_CR); + + regval &= ~RTC_CR_CPE; + + putreg32(regval, S32K1XX_RTC_CR); + + /* Set LPO_1KHZ clock source */ + + regval = getreg32(S32K1XX_RTC_CR); + + regval |= RTC_CR_LPOS; + + putreg32(regval, S32K1XX_RTC_CR); + + /* Set Update mode */ + + regval = getreg32(S32K1XX_RTC_CR); + + regval &= ~(RTC_CR_UM); + + putreg32(regval, S32K1XX_RTC_CR); + + /* Set Non-Supervisor access mode */ + + regval = getreg32(S32K1XX_RTC_CR); + + regval &= ~(RTC_CR_SUP); + + putreg32(regval, S32K1XX_RTC_CR); + + /* Enable the rtc */ + + s32k1xx_rtc_enable(); + + g_rtc_enabled = true; + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. This is similar to the standard time() + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. + * + * Input Parameters: + * None + * + * Returned Value: + * The current time in seconds + * + ****************************************************************************/ + +time_t up_rtc_time(void) +{ + uint32_t regval; + + regval = getreg32(S32K1XX_RTC_TSR); + regval &= RTC_TSR_MASK; + + return (uint32_t) (regval); +} + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(FAR const struct timespec *ts) +{ + DEBUGASSERT(ts != NULL); + + s32k1xx_rtc_disable(); + + putreg32((uint32_t)ts->tv_sec, S32K1XX_RTC_TSR); + + s32k1xx_rtc_enable(); + + return OK; +} + +/**************************************************************************** + * Name: s32k1xx_rtc_havesettime + * + * Description: + * Check if the rtc time has been set + * + * Input Parameters: + * None + * + * Returned Value: + * Returns true if RTC date-time have been previously set. + * + ****************************************************************************/ + +bool s32k1xx_rtc_havesettime(void) +{ + return 1; /* TODO */ +} +#endif /* CONFIG_s32k1xx_SNVS_rtc */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_rtc.h b/arch/arm/src/s32k1xx/s32k1xx_rtc.h new file mode 100644 index 00000000000..b00c3d38b94 --- /dev/null +++ b/arch/arm/src/s32k1xx/s32k1xx_rtc.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * arch/arm/src/s32k1xx/s32k1xx_rtc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_s32k1xx_s32k1xx_rtc_H +#define __ARCH_ARM_SRC_s32k1xx_s32k1xx_rtc_H + +#include + +#include "chip.h" + +#ifdef CONFIG_S32K1XX_RTC + +/**************************************************************************** + * Preprocessor Definitions + ****************************************************************************/ + +# ifdef CONFIG_RTC_DATETIME +# error CONFIG_RTC_DATETIME should not be selected with this driver +# endif + +# ifdef CONFIG_RTC_PERIODIC +# error CONFIG_RTC_PERIODIC should not be selected with this driver +# endif + +/* REVISIT: This is probably supportable. The 47 bit timer does have + * accuracy greater than 1 second. + */ + +# ifdef CONFIG_RTC_HIRES +# error CONFIG_RTC_PERIODIC should not be selected with this driver +# endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the rtc per the selected configuration. + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void); + +/**************************************************************************** + * Name: s32k1xx_rtc_havesettime + * + * Description: + * Check if the rtc time has been set + * + * Input Parameters: + * None + * + * Returned Value: + * Returns true if RTC date-time have been previously set. + * + ****************************************************************************/ + +bool s32k1xx_rtc_havesettime(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_S32K1XX_RTC */ +#endif /* __ARCH_ARM_SRC_s32k1xx_s32k1xx_rtc_H */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.c b/arch/arm/src/s32k1xx/s32k1xx_start.c index 709b7b3864f..4ac072037c2 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_start.c +++ b/arch/arm/src/s32k1xx/s32k1xx_start.c @@ -33,6 +33,10 @@ * ****************************************************************************/ +/**************************************************************************** + * Included Files + ****************************************************************************/ + #include #include @@ -57,6 +61,9 @@ #include "s32k1xx_serial.h" #include "s32k1xx_wdog.h" #include "s32k1xx_start.h" +#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET) +#include "hardware/s32k1xx_mpu.h" +#endif /**************************************************************************** * Pre-processor Definitions @@ -143,7 +150,8 @@ const uintptr_t g_idle_topstack = HEAP_BASE; * done, the processor reserves space on the stack for the FP state, * but does not save that state information to the stack. * - * Software must not change the value of the ASPEN bit or LSPEN bit while either: + * Software must not change the value of the ASPEN bit or LSPEN bit while + * either: * - the CPACR permits access to CP10 and CP11, that give access to the FP * extension, or * - the CONTROL.FPCA bit is set to 1 @@ -253,7 +261,8 @@ static inline void s32k1xx_mpu_config(void) */ regval = (MPU_RGDAAC_M3UM_XACCESS | MPU_RGDAAC_M3UM_WACCESS | - MPU_RGDAAC_M3UM_RACCESS | MPU_RGDAAC_M3SM_M3UM; + MPU_RGDAAC_M3UM_RACCESS | MPU_RGDAAC_M3SM_M3UM); + putreg32(regval, S32K1XX_MPU_RGDAAC(0)); } #endif @@ -330,11 +339,11 @@ void __start(void) showprogress('C'); #if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET) + /* Enable all MPU bus masters */ s32k1xx_mpu_config(); showprogress('D'); -} #endif /* Perform early serial initialization */ diff --git a/boards/Kconfig b/boards/Kconfig index 552641e408c..b622863cada 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1245,6 +1245,36 @@ config ARCH_BOARD_S32K118EVB This options selects support for NuttX on the NXP S32K118EVB board featuring the S32K118 Cortex-M0+. +config ARCH_BOARD_S32K144EVB + bool "NXP S32K144EVB" + depends on ARCH_CHIP_S32K144 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This options selects support for NuttX on the NXP S32K144EVB board + featuring the S32K144 Cortex-M4F. + +config ARCH_BOARD_RDDRONE_UAVCAN144 + bool "NXP RDDRONE-UAVCAN144" + depends on ARCH_CHIP_S32K144 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This options selects support for NuttX on the NXP RDDRONE-UAVCAN board + featuring the S32K144 Cortex-M4F. + +config ARCH_BOARD_RDDRONE_UAVCAN146 + bool "NXP RDDRONE-UAVCAN146" + depends on ARCH_CHIP_S32K146 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This options selects support for NuttX on the NXP RDDRONE-UAVCAN board + featuring the S32K146 Cortex-M4F. + config ARCH_BOARD_S32K146EVB bool "NXP S32K146EVB" depends on ARCH_CHIP_S32K146 @@ -2129,6 +2159,9 @@ config ARCH_BOARD default "rx65n-rsk2mb" if ARCH_BOARD_RX65N_RSK2MB default "rx65n-grrose" if ARCH_BOARD_RX65N_GRROSE default "s32k118evb" if ARCH_BOARD_S32K118EVB + default "s32k144evb" if ARCH_BOARD_S32K144EVB + default "rddrone-uavcan144" if ARCH_BOARD_RDDRONE_UAVCAN144 + default "rddrone-uavcan146" if ARCH_BOARD_RDDRONE_UAVCAN146 default "s32k146evb" if ARCH_BOARD_S32K146EVB default "s32k148evb" if ARCH_BOARD_S32K148EVB default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD @@ -2263,6 +2296,15 @@ endif if ARCH_BOARD_S32K118EVB source "boards/arm/s32k1xx/s32k118evb/Kconfig" endif +if ARCH_BOARD_S32K144EVB +source "boards/arm/s32k1xx/s32k144evb/Kconfig" +endif +if ARCH_BOARD_RDDRONE_UAVCAN144 +source "boards/arm/s32k1xx/rddrone-uavcan144/Kconfig" +endif +if ARCH_BOARD_RDDRONE_UAVCAN146 +source "boards/arm/s32k1xx/rddrone-uavcan146/Kconfig" +endif if ARCH_BOARD_S32K146EVB source "boards/arm/s32k1xx/s32k146evb/Kconfig" endif diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/Kconfig b/boards/arm/s32k1xx/rddrone-uavcan144/Kconfig new file mode 100644 index 00000000000..c61362c0a40 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_RDDRONE_UAVCAN144 + +endif # ARCH_BOARD_RDDRONE_UAVCAN144 diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/README.txt b/boards/arm/s32k1xx/rddrone-uavcan144/README.txt new file mode 100644 index 00000000000..d79bc82d82c --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/README.txt @@ -0,0 +1,15 @@ +README +====== + +This directory holds the port to the NXP RDDRONE-UAVCAN board with S32K144 MCU. + +Contents +======== + + o Status + +Status +====== + + 2020-01-23: Configuration created (copy-paste from S32K146EVB). + Tested: Serial console, I2C, SPI \ No newline at end of file diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig new file mode 100644 index 00000000000..a7abcbe5eb5 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="rddrone-uavcan144" +CONFIG_ARCH_BOARD_RDDRONE_UAVCAN144=y +CONFIG_ARCH_CHIP="s32k1xx" +CONFIG_ARCH_CHIP_S32K144=y +CONFIG_ARCH_CHIP_S32K14X=y +CONFIG_ARCH_CHIP_S32K1XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXADDR=0x7f +CONFIG_I2CTOOL_MAXBUS=0 +CONFIG_I2CTOOL_MINADDR=0x00 +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART0_RXBUFSIZE=64 +CONFIG_LPUART0_TXBUFSIZE=64 +CONFIG_LPUART1_RXBUFSIZE=64 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_LPUART1_TXBUFSIZE=64 +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MOTOROLA_SREC=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=61440 +CONFIG_RAM_START=0x1fff8000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_S32K1XX_LPI2C0=y +CONFIG_S32K1XX_LPSPI0=y +CONFIG_S32K1XX_LPUART0=y +CONFIG_S32K1XX_LPUART1=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPITOOL_DEFFREQ=400000 +CONFIG_SPITOOL_MAXBUS=0 +CONFIG_SPITOOL_PROGNAME="spi" +CONFIG_START_DAY=18 +CONFIG_START_MONTH=8 +CONFIG_START_YEAR=2019 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_CXXINITIALIZE=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_USER_ENTRYPOINT="nsh_main" \ No newline at end of file diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig new file mode 100644 index 00000000000..c48d50d84fd --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="rddrone-uavcan144" +CONFIG_ARCH_BOARD_RDDRONE_UAVCAN144=y +CONFIG_ARCH_CHIP="s32k1xx" +CONFIG_ARCH_CHIP_S32K144=y +CONFIG_ARCH_CHIP_S32K14X=y +CONFIG_ARCH_CHIP_S32K1XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXADDR=0x7f +CONFIG_I2CTOOL_MAXBUS=0 +CONFIG_I2CTOOL_MINADDR=0x00 +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART0_RXBUFSIZE=64 +CONFIG_LPUART0_TXBUFSIZE=64 +CONFIG_LPUART1_RXBUFSIZE=64 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_LPUART1_TXBUFSIZE=64 +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MOTOROLA_SREC=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=61440 +CONFIG_RAM_START=0x1fff8000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_S32K1XX_LPI2C0=y +CONFIG_S32K1XX_LPSPI0=y +CONFIG_S32K1XX_LPUART0=y +CONFIG_S32K1XX_LPUART1=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPITOOL_DEFFREQ=400000 +CONFIG_SPITOOL_MAXBUS=0 +CONFIG_SPITOOL_PROGNAME="spi" +CONFIG_START_DAY=18 +CONFIG_START_MONTH=8 +CONFIG_START_YEAR=2019 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_CXXINITIALIZE=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_USER_ENTRYPOINT="nsh_main" \ No newline at end of file diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/include/board.h b/boards/arm/s32k1xx/rddrone-uavcan144/include/board.h new file mode 100644 index 00000000000..6f5966eacd1 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/include/board.h @@ -0,0 +1,153 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/include/board.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RDDRONE_UAVCAN144_INCLUDE_BOARD_H +#define __BOARDS_ARM_RDDRONE_UAVCAN144_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The RDDRONE-UAVCAN144 is fitted with a 8MHz Crystal */ + +#define BOARD_XTAL_FREQUENCY 8000000 + +/* The S32K144 will run at 112MHz */ + +/* LED definitions **********************************************************/ + +/* The RDDRONE-UAVCAN144 has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual RGB + * components. + * + * The RGB components could, alternatively be controlled through PWM using + * the common RGB LED driver. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_R 0 +#define BOARD_LED_G 1 +#define BOARD_LED_B 2 +#define BOARD_NLEDS 3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_R_BIT (1 << BOARD_LED_R) +#define BOARD_LED_G_BIT (1 << BOARD_LED_G) +#define BOARD_LED_B_BIT (1 << BOARD_LED_B) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board + * the RDDRONE-UAVCAN144. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ---------------------------- ----------------- + */ + +#define LED_STARTED 1 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 2 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF ON */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON OFF */ +#define LED_INIRQ 0 /* In an interrupt (no change) */ +#define LED_SIGNAL 0 /* In a signal handler (no change) */ +#define LED_ASSERTION 0 /* An assertion failed (no change) */ +#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ +#undef LED_IDLE /* RDDRONE-UAVCAN144 in sleep mode (Not used) */ + +/* Button definitions *******************************************************/ + +/* The RDDRONE-UAVCAN144 supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +#define BUTTON_SW2 0 +#define BUTTON_SW3 1 +#define NUM_BUTTONS 2 + +#define BUTTON_SW2_BIT (1 << BUTTON_SW2) +#define BUTTON_SW3_BIT (1 << BUTTON_SW3) + +/* Alternate function pin selections ****************************************/ + +/* By default, the serial console will be provided on the OpenSDA VCOM port: + * + * OpenSDA UART TX PTC7 (LPUART1_TX) + * OpenSDA UART RX PTC6 (LPUART1_RX) + */ + +#define PIN_LPUART0_CTS PIN_LPUART0_CTS_2 /* PTC8 */ +#define PIN_LPUART0_RTS PIN_LPUART0_RTS_2 /* PTC9 */ +#define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTB0 */ +#define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTB1 */ + +#define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */ +#define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */ + +/* SPI selections ***********************************************************/ + +#define PIN_LPSPI0_SCK PIN_LPSPI0_SCK_2 /* PTB2 */ +#define PIN_LPSPI0_MISO PIN_LPSPI0_SIN_2 /* PTB3 */ +#define PIN_LPSPI0_MOSI PIN_LPSPI0_SOUT_3 /* PTB4 */ +#define PIN_LPSPI0_PCS PIN_LPSPI0_PCS0_2 /* PTB5 */ + +/* I2C selections ***********************************************************/ + +#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */ +#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */ + +#endif /* __BOARDS_ARM_RDDRONE_UAVCAN144_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs new file mode 100644 index 00000000000..e8cfa948118 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs @@ -0,0 +1,131 @@ +############################################################################ +# boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y) + LDSCRIPT = flash.ld +else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y) + LDSCRIPT = sram.ld +endif + +$(warning, LDSCRIPT is $(LDSCRIPT)) +ifeq ($(WINTOOL),y) + # Windows-native toolchains + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif +$(warning, LDSCRIPT is $(LDSCRIPT)) +$(warning, ARCHSCRIPT is $(ARCHSCRIPT)) + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = +ifeq ($(CONFIG_HOST_WINDOWS),y) + HOSTEXEEXT = .exe +else + HOSTEXEEXT = +endif + +ifeq ($(WINTOOL),y) + # Windows-native host tools + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh +else + # Linux/Cygwin-native host tools + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) +endif diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/scripts/flash.ld b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/flash.ld new file mode 100644 index 00000000000..ac751003661 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/flash.ld @@ -0,0 +1,152 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/scripts/flash.ld + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K144 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 60Kb of SRAM beginning at address 0x1fff:8000 (plus 4Kb of FlexRAM) + * + * The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is + * implemented such that the SRAM_L and SRAM_U ranges form a contiguous + * block in the memory map + * + * SRAM_L 1fff8000 - 1fffffff 32Kb + * SRAM_U 20000000 - 20006fff 28Kb + */ + +MEMORY +{ + vflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K + pflash (rx) : ORIGIN = 0x00000400, LENGTH = 16 + dflash (rx) : ORIGIN = 0x00000410, LENGTH = 511K-16 + sram (rwx) : ORIGIN = 0x1fff8000, LENGTH = 60K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +EXTERN(g_flashcfg) +ENTRY(_stext) + +SECTIONS +{ + .vectors : + { + _stext = ABSOLUTE(.); + *(.vectors) + } > vflash + + .flashcfg : + { + *(.flashcfg) + } > pflash + + .text : + { + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > dflash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > dflash + + .ARM.extab : + { + *(.ARM.extab*) + } >dflash + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } >dflash + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > dflash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > dflash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/scripts/s32k144.cfg b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/s32k144.cfg new file mode 100644 index 00000000000..7d30a9f05f0 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/s32k144.cfg @@ -0,0 +1,58 @@ +# +# NXP S32K144 - 1x ARM Cortex-M4 @ up to 112 MHz +# + +adapter_khz 4000 +transport select swd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s32k144 +} + +# +# M4 JTAG mode TAP +# +if { [info exists M4_JTAG_TAPID] } { + set _M4_JTAG_TAPID $M4_JTAG_TAPID +} else { + set _M4_JTAG_TAPID 0x4ba00477 +} + +# +# M4 SWD mode TAP +# +if { [info exists M4_SWD_TAPID] } { + set _M4_SWD_TAPID $M4_SWD_TAPID +} else { + set _M4_SWD_TAPID 0x2ba01477 +} + +source [find target/swj-dp.tcl] + +if { [using_jtag] } { + set _M4_TAPID $_M4_JTAG_TAPID +} else { + set _M4_TAPID $_M4_SWD_TAPID +} + +swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M4_TAPID + +target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 + +# S32K144 has 32+28 KB contiguous SRAM +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0xF000 +} +$_CHIPNAME.m4 configure -work-area-phys 0x1FFF8000 \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +$_CHIPNAME.m4 configure -rtos nuttx + +if { ![using_hla] } { + cortex_m reset_config vectreset +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/scripts/sram.ld b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/sram.ld new file mode 100644 index 00000000000..1b992ec3b36 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/sram.ld @@ -0,0 +1,129 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/scripts/sram.ld + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K144 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 60Kb of SRAM beginning at address 0x1fff:8000 (plus 4Kb of FlexRAM) + * + * The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is + * implemented such that the SRAM_L and SRAM_U ranges form a contiguous + * block in the memory map + * + * SRAM_L 1fff8000 - 1fffffff 32Kb + * SRAM_U 20000000 - 20006fff 28Kb + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x1fff8000, LENGTH = 60K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > sram + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > sram + + .ARM.extab : + { + *(.ARM.extab*) + } >sram + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } >sram + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/.gitignore b/boards/arm/s32k1xx/rddrone-uavcan144/src/.gitignore new file mode 100644 index 00000000000..726d936e1e3 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/Makefile b/boards/arm/s32k1xx/rddrone-uavcan144/src/Makefile new file mode 100644 index 00000000000..56fd2703ab3 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/Makefile @@ -0,0 +1,60 @@ +############################################################################ +# boards/arm/s32k1xx/rddrone-uavcan144/src/Makefile +# +# Copyright (C) 2019 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c +CSRCS += s32k1xx_periphclocks.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += s32k1xx_autoleds.c +else +CSRCS += s32k1xx_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += s32k1xx_buttons.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += s32k1xx_appinit.c +endif + +ifeq ($(CONFIG_S32K1XX_LPSPI),y) +CSRCS += s32k1xx_spi.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/rddrone-uavcan144.h b/boards/arm/s32k1xx/rddrone-uavcan144/src/rddrone-uavcan144.h new file mode 100644 index 00000000000..62697cd3b00 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/rddrone-uavcan144.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/rddrone-uavcan144.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN144_SRC_RDDRONE_UAVCAN144_H +#define __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN144_SRC_RDDRONE_UAVCAN144_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "hardware/s32k1xx_pinmux.h" +#include "s32k1xx_periphclocks.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* RDDRONE-UAVCAN144 GPIOs **************************************************/ + +/* LEDs. The RDDRONE-UAVCAN144 has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * An output of '1' illuminates the LED. + */ + +#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED_B (PIN_PTD0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) + +/* Buttons. The RDDRONE-UAVCAN144 supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH) +#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH) + +/* SPI chip selects */ + +/* A71CH Reset */ + +#define GPIO_A71CH_RST (PIN_PTA6 | GPIO_LOWDRIVE) + +/* Count of peripheral clock user configurations */ + +#define NUM_OF_PERIPHERAL_CLOCKS_0 15 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* User peripheral configuration structure 0 */ + +extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k1xx_bringup(void); + +/**************************************************************************** + * Name: s32k1xx_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the RDDRONE-UAVCAN144 + * board. + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_LPSPI +void s32k1xx_spidev_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN144_SRC_RDDRONE_UAVCAN144_H */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_appinit.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_appinit.c new file mode 100644 index 00000000000..5168f36f003 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_appinit.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "rddrone-uavcan144.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return s32k1xx_bringup(); +#endif +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_autoleds.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_autoleds.c new file mode 100644 index 00000000000..6a63a9b1678 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_autoleds.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_autoleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The RDDRONE-UAVCAN144 has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * An output of '1' illuminates the LED. + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Freedom K66F. The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ----------------------- ----------------- + * LED_STARTED NuttX has been started OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + * LED_IRQSENABLED Interrupts enabled OFF OFF ON + * LED_STACKCREATED Idle stack created OFF ON OFF + * LED_INIRQ In an interrupt (no change) + * LED_SIGNAL In a signal handler (no change) + * LED_ASSERTION An assertion failed (no change) + * LED_PANIC The system has crashed FLASH OFF OFF + * LED_IDLE K66 is in sleep mode (Optional, not used) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "rddrone-uavcan144.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Summary of all possible settings */ + +#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ +#define LED_OFF_OFF_OFF 1 /* LED_STARTED */ +#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */ +#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */ +#define LED_ON_OFF_OFF 4 /* LED_PANIC */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led != LED_NOCHANGE) + { + bool redon = false; + bool greenon = false; + bool blueon = false; + + switch (led) + { + default: + case LED_OFF_OFF_OFF: + break; + + case LED_OFF_OFF_ON: + blueon = true; + break; + + case LED_OFF_ON_OFF: + greenon = true; + break; + + case LED_ON_OFF_OFF: + redon = true; + break; + } + + s32k1xx_gpiowrite(GPIO_LED_R, redon); + s32k1xx_gpiowrite(GPIO_LED_G, greenon); + s32k1xx_gpiowrite(GPIO_LED_B, blueon); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_ON_OFF_OFF) + { + s32k1xx_gpiowrite(GPIO_LED_R, true); + s32k1xx_gpiowrite(GPIO_LED_G, false); + s32k1xx_gpiowrite(GPIO_LED_B, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c new file mode 100644 index 00000000000..3fcaa138bb5 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "rddrone-uavcan144.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_board_initialize + * + * Description: + * All S32K1XX architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void s32k1xx_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + s32k1xx_bringup(); +} +#endif diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c new file mode 100644 index 00000000000..bc0abbf10a1 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c @@ -0,0 +1,147 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_I2C_DRIVER +# include "s32k1xx_pin.h" +# include +# include "s32k1xx_lpi2c.h" +#endif + +#include "rddrone-uavcan144.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k1xx_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_S32K1XX_LPSPI + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function s32k1xx_spidev_initialize() has been brought into the link. + */ + + s32k1xx_spidev_initialize(); +#endif + +#if defined(CONFIG_S32K1XX_LPI2C0) + s32k1xx_pinconfig(GPIO_HIGHDRIVE | GPIO_OUTPUT_ONE | PIN_PORTA | PIN10); /* Set A71CH IF0 HIGH */ + s32k1xx_pinconfig(GPIO_HIGHDRIVE | GPIO_OUTPUT_ZERO | PIN_PORTA | PIN7); /* Set A71CH IF1 LOW */ + +#if defined(CONFIG_I2C_DRIVER) + FAR struct i2c_master_s *i2c; + i2c = s32k1xx_i2cbus_initialize(0); + + if (i2c == NULL) + { + serr("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, 0); + if (ret < 0) + { + serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + s32k1xx_i2cbus_uninitialize(i2c); + } + } +#endif +#endif + + return ret; +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_buttons.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_buttons.c new file mode 100644 index 00000000000..f5cf6e2a286 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_buttons.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_buttons.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The RDDRONE-UAVCAN144 supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "s32k1xx_pin.h" +#include "rddrone-uavcan144.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + /* Configure the GPIO pins as interrupting inputs. */ + + s32k1xx_pinconfig(GPIO_SW2); + s32k1xx_pinconfig(GPIO_SW3); +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + if (s32k1xx_gpioread(GPIO_SW2)) + { + ret |= BUTTON_SW2_BIT; + } + + if (s32k1xx_gpioread(GPIO_SW3)) + { + ret |= BUTTON_SW3_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + uint32_t pinset; + int ret; + + /* Map the button id to the GPIO bit set. */ + + if (id == BUTTON_SW2) + { + pinset = GPIO_SW2; + } + else if (id == BUTTON_SW3) + { + pinset = GPIO_SW3; + } + else + { + return -EINVAL; + } + + /* The button has already been configured as an interrupting input (by + * board_button_initialize() above). + * + * Attach the new button handler. + */ + + ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL); + if (ret >= 0) + { + /* Then make sure that interrupts are enabled on the pin */ + + s32k1xx_pinirqenable(pinset); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c new file mode 100644 index 00000000000..3ad5f31e0d7 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c @@ -0,0 +1,227 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "s32k1xx_clockconfig.h" +#include "s32k1xx_start.h" +#include "rddrone-uavcan144.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial board clocking. + */ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .scg = + { + .sirc = + { + .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = true, /* SIRCSTEN */ + .lowpower = true, /* SIRCLPEN */ + .locked = false, /* LK */ + }, + .firc = + { + .range = SCG_FIRC_RANGE_48M, /* RANGE */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .regulator = true, /* FIRCREGOFF */ + .locked = false, /* LK */ + }, + .sosc = + { + .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */ + .gain = SCG_SOSC_GAIN_LOW, /* HGO */ + .range = SCG_SOSC_RANGE_MID, /* RANGE */ + .extref = SCG_SOSC_REF_OSC, /* EREFS */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .locked = false, /* LK */ + }, + .spll = + { + .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */ + .prediv = 1, /* PREDIV */ + .mult = 40, /* MULT */ + .src = 0, /* SOURCE */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .locked = false, /* LK */ + }, + .rtc = + { + .initialize = true, /* Initialize */ + .clkin = 0 /* RTC_CLKIN */ + }, + .clockout = + { + .source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */ + .initialize = true, /* Initialize */ + }, + .clockmode = + { + .rccr = /* RCCR - Run Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .vccr = /* VCCR - VLPR Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */ + .divslow = 4, /* DIVSLOW, range 1..16 */ + .divbus = 1, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .hccr = + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + + /* .altclk */ + + .initialize = true, /* Initialize */ + }, + }, + .sim = + { + .clockout = /* Clock Out configuration. */ + { + .source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */ + .divider = 1, /* CLKOUTDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = false, /* CLKOUTEN */ + }, + .lpoclk = /* Low Power Clock configuration. */ + { + .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ + .initialize = true, /* Initialize */ + .lpo32k = true, /* LPO32KCLKEN */ + .lpo1k = true, /* LPO1KCLKEN */ + }, + .tclk = /* TCLK CLOCK configuration. */ + { + .tclkfreq[0] = 0, /* TCLK0 */ + .tclkfreq[1] = 0, /* TCLK1 */ + .tclkfreq[2] = 0, /* TCLK2 */ + .initialize = true, /* Initialize */ + }, + .platgate = /* Platform Gate Clock configuration. */ + { + .initialize = true, /* Initialize */ + .mscm = true, /* CGCMSCM */ + .mpu = true, /* CGCMPU */ + .dma = true, /* CGCDMA */ + .erm = true, /* CGCERM */ + .eim = true, /* CGCEIM */ + }, + .traceclk = /* Debug trace Clock Configuration. */ + { + .source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */ + .divider = 1, /* TRACEDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = true, /* TRACEDIVEN */ + .fraction = false, /* TRACEFRAC */ + }, +#ifdef CONFIG_S32K1XX_HAVE_QSPI + .qspirefclk = /* Quad Spi Internal Reference Clock Gating. */ + { + .refclk = false, /* Qspi reference clock gating */ + }, +#endif + }, + .pcc = + { + .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */ + .pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */ + }, + .pmc = + { + .lpoclk = /* Low Power Clock configuration. */ + { + .trim = 0, /* Trimming value for LPO */ + .initialize = true, /* Initialize */ + .enable = true, /* Enable/disable LPO */ + }, + } +}; diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_periphclocks.c new file mode 100644 index 00000000000..22be8927aa9 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_periphclocks.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_periphclks.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "s32k1xx_periphclocks.h" +#include "rddrone-uavcan144.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial peripheral clocking. + */ + +const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = +{ + { + .clkname = ADC0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = ADC1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPI2C0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI1_CLK, + .clkgate = false, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI2_CLK, + .clkgate = false, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPTMR0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART2_CLK, + .clkgate = false, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTA_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTB_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTC_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTD_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTE_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + } +}; diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c new file mode 100644 index 00000000000..1c0588c2209 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c @@ -0,0 +1,199 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" + +#include "s32k1xx_config.h" +#include "s32k1xx_lpspi.h" +#include "s32k1xx_pin.h" +#include "rddrone-uavcan144.h" + +#if defined(CONFIG_S32K1XX_LPSPI0) || defined(CONFIG_S32K1XX_LPSPI1) || \ + defined(CONFIG_S32K1XX_LPSPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the RDDRONE-UAVCAN144 + * board. + * + ****************************************************************************/ + +void weak_function s32k1xx_spidev_initialize(void) +{ +#ifdef CONFIG_S32K1XX_LPSPI0 + s32k1xx_pinconfig(PIN_LPSPI0_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi0; + g_lpspi0 = s32k1xx_lpspibus_initialize(0); + + if (!g_lpspi0) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI0\n"); + } + + spi_register(g_lpspi0, 0); +#endif +#endif + +#ifdef CONFIG_S32K1XX_LPSPI1 + s32k1xx_pinconfig(PIN_LPSPI1_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi1; + g_lpspi1 = s32k1xx_lpspibus_initialize(1); + + if (!g_lpspi1) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI1\n"); + } + + spi_register(g_lpspi1, 1); +#endif +#endif + +#ifdef CONFIG_S32K1XX_LPSPI2 + s32k1xx_pinconfig(PIN_LPSPI2_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi2; + g_lpspi2 = s32k1xx_lpspibus_initialize(2); + + if (!g_lpspi2) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI2\n"); + } + + spi_register(g_lpspi2, 2); +#endif +#endif +} + +/**************************************************************************** + * Name: s32k1xx_lpspi0/1/2select and s32k1xx_lpspi0/1/2status + * + * Description: + * The external functions, s32k1xx_lpspi0/1/2select and + * s32k1xx_lpspi0/1/2status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including s32k1xx_lpspibus_initialize()) are provided + * by common logic. To use this common SPI logic on your board: + * + * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_LPSPI0 +void s32k1xx_lpspi0select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI0_PCS, !selected); +} + +uint8_t s32k1xx_lpspi0status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_S32K1XX_LPSPI1 +void s32k1xx_lpspi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI1_PCS, !selected); +} + +uint8_t s32k1xx_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_S32K1XX_LPSPI2 +void s32k1xx_lpspi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI2_PCS, !selected); +} + +uint8_t s32k1xx_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_S32K1XX_LPSPI0 || CONFIG_S32K1XX_LPSPI01 || CONFIG_S32K1XX_LPSPI2 */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_userleds.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_userleds.c new file mode 100644 index 00000000000..de3e419b9b2 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_userleds.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_userleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "rddrone-uavcan144.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED_R) + { + ledcfg = GPIO_LED_R; + } + else if (led == BOARD_LED_G) + { + ledcfg = GPIO_LED_G; + } + else if (led == BOARD_LED_B) + { + ledcfg = GPIO_LED_B; + } + else + { + return; + } + + s32k1xx_gpiowrite(ledcfg, ledon); /* High illuminates */ +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + s32k1xx_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/Kconfig b/boards/arm/s32k1xx/rddrone-uavcan146/Kconfig new file mode 100644 index 00000000000..77a4ee5f7db --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_RDDRONE_UAVCAN146 + +endif # ARCH_BOARD_RDDRONE_UAVCAN146 diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/README.txt b/boards/arm/s32k1xx/rddrone-uavcan146/README.txt new file mode 100644 index 00000000000..86cb1a857ee --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/README.txt @@ -0,0 +1,15 @@ +README +====== + +This directory holds the port to the NXP RDDRONE-UAVCAN board with S32K146 MCU. + +Contents +======== + + o Status + +Status +====== + + 2020-01-23: Configuration created (copy-paste from S32K146EVB). + Tested: Serial console \ No newline at end of file diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig new file mode 100644 index 00000000000..80bed115388 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="rddrone-uavcan146" +CONFIG_ARCH_BOARD_RDDRONE_UAVCAN146=y +CONFIG_ARCH_CHIP="s32k1xx" +CONFIG_ARCH_CHIP_S32K146=y +CONFIG_ARCH_CHIP_S32K14X=y +CONFIG_ARCH_CHIP_S32K1XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXADDR=0x7f +CONFIG_I2CTOOL_MAXBUS=0 +CONFIG_I2CTOOL_MINADDR=0x00 +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART0_RXBUFSIZE=64 +CONFIG_LPUART0_TXBUFSIZE=64 +CONFIG_LPUART1_RXBUFSIZE=64 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_LPUART1_TXBUFSIZE=64 +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MOTOROLA_SREC=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=126976 +CONFIG_RAM_START=0x1fff0000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_S32K1XX_LPI2C0=y +CONFIG_S32K1XX_LPSPI0=y +CONFIG_S32K1XX_LPUART0=y +CONFIG_S32K1XX_LPUART1=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPITOOL_DEFFREQ=400000 +CONFIG_SPITOOL_MAXBUS=0 +CONFIG_SPITOOL_PROGNAME="spi" +CONFIG_START_DAY=18 +CONFIG_START_MONTH=8 +CONFIG_START_YEAR=2019 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_CXXINITIALIZE=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_USER_ENTRYPOINT="nsh_main" \ No newline at end of file diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig new file mode 100644 index 00000000000..a7a81e4c050 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="rddrone-uavcan146" +CONFIG_ARCH_BOARD_RDDRONE_UAVCAN146=y +CONFIG_ARCH_CHIP="s32k1xx" +CONFIG_ARCH_CHIP_S32K146=y +CONFIG_ARCH_CHIP_S32K14X=y +CONFIG_ARCH_CHIP_S32K1XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXADDR=0x7f +CONFIG_I2CTOOL_MAXBUS=0 +CONFIG_I2CTOOL_MINADDR=0x00 +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART0_RXBUFSIZE=64 +CONFIG_LPUART0_TXBUFSIZE=64 +CONFIG_LPUART1_RXBUFSIZE=64 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_LPUART1_TXBUFSIZE=64 +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MOTOROLA_SREC=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=126976 +CONFIG_RAM_START=0x1fff0000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_S32K1XX_LPI2C0=y +CONFIG_S32K1XX_LPSPI0=y +CONFIG_S32K1XX_LPUART0=y +CONFIG_S32K1XX_LPUART1=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPITOOL_DEFFREQ=400000 +CONFIG_SPITOOL_MAXBUS=0 +CONFIG_SPITOOL_PROGNAME="spi" +CONFIG_START_DAY=18 +CONFIG_START_MONTH=8 +CONFIG_START_YEAR=2019 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_CXXINITIALIZE=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_USER_ENTRYPOINT="nsh_main" \ No newline at end of file diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h b/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h new file mode 100644 index 00000000000..c0ab9d1d96a --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h @@ -0,0 +1,153 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/include/board.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RDDRONE_UAVCAN146_INCLUDE_BOARD_H +#define __BOARDS_ARM_RDDRONE_UAVCAN146_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The RDDRONE-UAVCAN146 is fitted with a 8MHz Crystal */ + +#define BOARD_XTAL_FREQUENCY 8000000 + +/* The S32K146 will run at 112MHz */ + +/* LED definitions **********************************************************/ + +/* The RDDRONE-UAVCAN146 has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual RGB + * components. + * + * The RGB components could, alternatively be controlled through PWM using + * the common RGB LED driver. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_R 0 +#define BOARD_LED_G 1 +#define BOARD_LED_B 2 +#define BOARD_NLEDS 3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_R_BIT (1 << BOARD_LED_R) +#define BOARD_LED_G_BIT (1 << BOARD_LED_G) +#define BOARD_LED_B_BIT (1 << BOARD_LED_B) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board + * the RDDRONE-UAVCAN146. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ---------------------------- ----------------- + */ + +#define LED_STARTED 1 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 2 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF ON */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON OFF */ +#define LED_INIRQ 0 /* In an interrupt (no change) */ +#define LED_SIGNAL 0 /* In a signal handler (no change) */ +#define LED_ASSERTION 0 /* An assertion failed (no change) */ +#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ +#undef LED_IDLE /* RDDRONE-UAVCAN146 in sleep mode (Not used) */ + +/* Button definitions *******************************************************/ + +/* The RDDRONE-UAVCAN146 supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +#define BUTTON_SW2 0 +#define BUTTON_SW3 1 +#define NUM_BUTTONS 2 + +#define BUTTON_SW2_BIT (1 << BUTTON_SW2) +#define BUTTON_SW3_BIT (1 << BUTTON_SW3) + +/* Alternate function pin selections ****************************************/ + +/* By default, the serial console will be provided on the OpenSDA VCOM port: + * + * OpenSDA UART TX PTC7 (LPUART1_TX) + * OpenSDA UART RX PTC6 (LPUART1_RX) + */ + +#define PIN_LPUART0_CTS PIN_LPUART0_CTS_2 /* PTC8 */ +#define PIN_LPUART0_RTS PIN_LPUART0_RTS_2 /* PTC9 */ +#define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTB0 */ +#define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTB1 */ + +#define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */ +#define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */ + +/* SPI selections ***********************************************************/ + +#define PIN_LPSPI0_SCK PIN_LPSPI0_SCK_2 /* PTB2 */ +#define PIN_LPSPI0_MISO PIN_LPSPI0_SIN_2 /* PTB3 */ +#define PIN_LPSPI0_MOSI PIN_LPSPI0_SOUT_3 /* PTB4 */ +#define PIN_LPSPI0_PCS PIN_LPSPI0_PCS0_2 /* PTB5 */ + +/* I2C selections ***********************************************************/ + +#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */ +#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */ + +#endif /* __BOARDS_ARM_RDDRONE_UAVCAN146_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs new file mode 100644 index 00000000000..6f0e0a6cd24 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs @@ -0,0 +1,131 @@ +############################################################################ +# boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y) + LDSCRIPT = flash.ld +else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y) + LDSCRIPT = sram.ld +endif + +$(warning, LDSCRIPT is $(LDSCRIPT)) +ifeq ($(WINTOOL),y) + # Windows-native toolchains + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif +$(warning, LDSCRIPT is $(LDSCRIPT)) +$(warning, ARCHSCRIPT is $(ARCHSCRIPT)) + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = +ifeq ($(CONFIG_HOST_WINDOWS),y) + HOSTEXEEXT = .exe +else + HOSTEXEEXT = +endif + +ifeq ($(WINTOOL),y) + # Windows-native host tools + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh +else + # Linux/Cygwin-native host tools + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) +endif diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/scripts/flash.ld b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/flash.ld new file mode 100644 index 00000000000..8d08125616f --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/flash.ld @@ -0,0 +1,152 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/scripts/flash.ld + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K146 has 1Mb of FLASH beginning at address 0x0000:0000 and + * 124Kb of SRAM beginning at address 0x1fff:0000 (plus 4Kb of FlexRAM) + * + * The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is + * implemented such that the SRAM_L and SRAM_U ranges form a contiguous + * block in the memory map + * + * SRAM_L 1fff0000 - 1fffffff 64Kb + * SRAM_U 20000000 - 2000efff 60Kb + */ + +MEMORY +{ + vflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K + pflash (rx) : ORIGIN = 0x00000400, LENGTH = 16 + dflash (rx) : ORIGIN = 0x00000410, LENGTH = 1023K-16 + sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 124K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +EXTERN(g_flashcfg) +ENTRY(_stext) + +SECTIONS +{ + .vectors : + { + _stext = ABSOLUTE(.); + *(.vectors) + } > vflash + + .flashcfg : + { + *(.flashcfg) + } > pflash + + .text : + { + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > dflash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > dflash + + .ARM.extab : + { + *(.ARM.extab*) + } >dflash + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } >dflash + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > dflash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > dflash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/scripts/s32k146.cfg b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/s32k146.cfg new file mode 100644 index 00000000000..749facc47c8 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/s32k146.cfg @@ -0,0 +1,58 @@ +# +# NXP S32K146 - 1x ARM Cortex-M4 @ up to 180 MHz +# + +adapter_khz 4000 +transport select swd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s32k146 +} + +# +# M4 JTAG mode TAP +# +if { [info exists M4_JTAG_TAPID] } { + set _M4_JTAG_TAPID $M4_JTAG_TAPID +} else { + set _M4_JTAG_TAPID 0x4ba00477 +} + +# +# M4 SWD mode TAP +# +if { [info exists M4_SWD_TAPID] } { + set _M4_SWD_TAPID $M4_SWD_TAPID +} else { + set _M4_SWD_TAPID 0x2ba01477 +} + +source [find target/swj-dp.tcl] + +if { [using_jtag] } { + set _M4_TAPID $_M4_JTAG_TAPID +} else { + set _M4_TAPID $_M4_SWD_TAPID +} + +swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M4_TAPID + +target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 + +# S32K146 has 64+60 KB contiguous SRAM +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1F000 +} +$_CHIPNAME.m4 configure -work-area-phys 0x1FFF0000 \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +$_CHIPNAME.m4 configure -rtos nuttx + +if { ![using_hla] } { + cortex_m reset_config vectreset +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/scripts/sram.ld b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/sram.ld new file mode 100644 index 00000000000..ff18d0ef33f --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/sram.ld @@ -0,0 +1,129 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/scripts/sram.ld + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K146 has 1Mb of FLASH beginning at address 0x0000:0000 and + * 124Kb of SRAM beginning at address 0x1fff:0000 (plus 4Kb of FlexRAM) + * + * The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is + * implemented such that the SRAM_L and SRAM_U ranges form a contiguous + * block in the memory map + * + * SRAM_L 1fff0000 - 1fffffff 64Kb + * SRAM_U 20000000 - 2000efff 60Kb + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 1M + sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 124K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > sram + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > sram + + .ARM.extab : + { + *(.ARM.extab*) + } >sram + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } >sram + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/.gitignore b/boards/arm/s32k1xx/rddrone-uavcan146/src/.gitignore new file mode 100644 index 00000000000..726d936e1e3 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/Makefile b/boards/arm/s32k1xx/rddrone-uavcan146/src/Makefile new file mode 100644 index 00000000000..bbae86505bf --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/Makefile @@ -0,0 +1,60 @@ +############################################################################ +# boards/arm/s32k1xx/rddrone-uavcan146/src/Makefile +# +# Copyright (C) 2019 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c +CSRCS += s32k1xx_periphclocks.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += s32k1xx_autoleds.c +else +CSRCS += s32k1xx_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += s32k1xx_buttons.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += s32k1xx_appinit.c +endif + +ifeq ($(CONFIG_S32K1XX_LPSPI),y) +CSRCS += s32k1xx_spi.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h b/boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h new file mode 100644 index 00000000000..a4f27649e96 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN146_SRC_RDDRONE_UAVCAN146_H +#define __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN146_SRC_RDDRONE_UAVCAN146_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "hardware/s32k1xx_pinmux.h" +#include "s32k1xx_periphclocks.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* RDDRONE-UAVCAN146 GPIOs **************************************************/ + +/* LEDs. The RDDRONE-UAVCAN146 has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * An output of '1' illuminates the LED. + */ + +#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED_B (PIN_PTD0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) + +/* Buttons. The RDDRONE-UAVCAN146 supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH) +#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH) + +/* SPI chip selects */ + +/* SE050 Enable */ + +#define GPIO_SE050_EN (PIN_PTA6 | GPIO_LOWDRIVE) + +/* Count of peripheral clock user configurations */ + +#define NUM_OF_PERIPHERAL_CLOCKS_0 15 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* User peripheral configuration structure 0 */ + +extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k1xx_bringup(void); + +/**************************************************************************** + * Name: s32k1xx_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the RDDRONE-UAVCAN146 + * board. + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_LPSPI +void s32k1xx_spidev_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN146_SRC_RDDRONE_UAVCAN146_H */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_appinit.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_appinit.c new file mode 100644 index 00000000000..54e98d554cc --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_appinit.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "rddrone-uavcan146.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return s32k1xx_bringup(); +#endif +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_autoleds.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_autoleds.c new file mode 100644 index 00000000000..a766850b3d0 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_autoleds.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_autoleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The RDDRONE-UAVCAN146 has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * An output of '1' illuminates the LED. + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Freedom K66F. The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ----------------------- ----------------- + * LED_STARTED NuttX has been started OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + * LED_IRQSENABLED Interrupts enabled OFF OFF ON + * LED_STACKCREATED Idle stack created OFF ON OFF + * LED_INIRQ In an interrupt (no change) + * LED_SIGNAL In a signal handler (no change) + * LED_ASSERTION An assertion failed (no change) + * LED_PANIC The system has crashed FLASH OFF OFF + * LED_IDLE K66 is in sleep mode (Optional, not used) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "rddrone-uavcan146.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Summary of all possible settings */ + +#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ +#define LED_OFF_OFF_OFF 1 /* LED_STARTED */ +#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */ +#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */ +#define LED_ON_OFF_OFF 4 /* LED_PANIC */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led != LED_NOCHANGE) + { + bool redon = false; + bool greenon = false; + bool blueon = false; + + switch (led) + { + default: + case LED_OFF_OFF_OFF: + break; + + case LED_OFF_OFF_ON: + blueon = true; + break; + + case LED_OFF_ON_OFF: + greenon = true; + break; + + case LED_ON_OFF_OFF: + redon = true; + break; + } + + s32k1xx_gpiowrite(GPIO_LED_R, redon); + s32k1xx_gpiowrite(GPIO_LED_G, greenon); + s32k1xx_gpiowrite(GPIO_LED_B, blueon); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_ON_OFF_OFF) + { + s32k1xx_gpiowrite(GPIO_LED_R, true); + s32k1xx_gpiowrite(GPIO_LED_G, false); + s32k1xx_gpiowrite(GPIO_LED_B, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c new file mode 100644 index 00000000000..59a6fdcd59c --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "rddrone-uavcan146.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_board_initialize + * + * Description: + * All S32K1XX architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void s32k1xx_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + s32k1xx_bringup(); +} +#endif diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c new file mode 100644 index 00000000000..300f08e9a4e --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_I2C_DRIVER +# include "s32k1xx_pin.h" +# include +# include "s32k1xx_lpi2c.h" +#endif + +#include "rddrone-uavcan146.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k1xx_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_S32K1XX_LPSPI + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function s32k1xx_spidev_initialize() has been brought into the link. + */ + + s32k1xx_spidev_initialize(); +#endif + +#if defined(CONFIG_S32K1XX_LPI2C0) +#if defined(CONFIG_I2C_DRIVER) + FAR struct i2c_master_s *i2c; + i2c = s32k1xx_i2cbus_initialize(0); + + if (i2c == NULL) + { + serr("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, 0); + if (ret < 0) + { + serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + s32k1xx_i2cbus_uninitialize(i2c); + } + } +#endif +#endif + + return ret; +} diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c new file mode 100644 index 00000000000..81fc9688f07 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The RDDRONE-UAVCAN146 supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "s32k1xx_pin.h" +#include "rddrone-uavcan146.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + /* Configure the GPIO pins as interrupting inputs. */ + + s32k1xx_pinconfig(GPIO_SW2); + s32k1xx_pinconfig(GPIO_SW3); +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + if (s32k1xx_gpioread(GPIO_SW2)) + { + ret |= BUTTON_SW2_BIT; + } + + if (s32k1xx_gpioread(GPIO_SW3)) + { + ret |= BUTTON_SW3_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + uint32_t pinset; + int ret; + + /* Map the button id to the GPIO bit set. */ + + if (id == BUTTON_SW2) + { + pinset = GPIO_SW2; + } + else if (id == BUTTON_SW3) + { + pinset = GPIO_SW3; + } + else + { + return -EINVAL; + } + + /* The button has already been configured as an interrupting input (by + * board_button_initialize() above). + * + * Attach the new button handler. + */ + + ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL); + if (ret >= 0) + { + /* Then make sure that interrupts are enabled on the pin */ + + s32k1xx_pinirqenable(pinset); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c new file mode 100644 index 00000000000..5f31c4c1e68 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c @@ -0,0 +1,227 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "s32k1xx_clockconfig.h" +#include "s32k1xx_start.h" +#include "rddrone-uavcan146.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial board clocking. + */ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .scg = + { + .sirc = + { + .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = true, /* SIRCSTEN */ + .lowpower = true, /* SIRCLPEN */ + .locked = false, /* LK */ + }, + .firc = + { + .range = SCG_FIRC_RANGE_48M, /* RANGE */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .regulator = true, /* FIRCREGOFF */ + .locked = false, /* LK */ + }, + .sosc = + { + .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */ + .gain = SCG_SOSC_GAIN_LOW, /* HGO */ + .range = SCG_SOSC_RANGE_MID, /* RANGE */ + .extref = SCG_SOSC_REF_OSC, /* EREFS */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .locked = false, /* LK */ + }, + .spll = + { + .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */ + .prediv = 1, /* PREDIV */ + .mult = 40, /* MULT */ + .src = 0, /* SOURCE */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .locked = false, /* LK */ + }, + .rtc = + { + .initialize = true, /* Initialize */ + .clkin = 0 /* RTC_CLKIN */ + }, + .clockout = + { + .source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */ + .initialize = true, /* Initialize */ + }, + .clockmode = + { + .rccr = /* RCCR - Run Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .vccr = /* VCCR - VLPR Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */ + .divslow = 4, /* DIVSLOW, range 1..16 */ + .divbus = 1, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .hccr = + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + + /* .altclk */ + + .initialize = true, /* Initialize */ + }, + }, + .sim = + { + .clockout = /* Clock Out configuration. */ + { + .source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */ + .divider = 1, /* CLKOUTDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = false, /* CLKOUTEN */ + }, + .lpoclk = /* Low Power Clock configuration. */ + { + .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ + .initialize = true, /* Initialize */ + .lpo32k = true, /* LPO32KCLKEN */ + .lpo1k = true, /* LPO1KCLKEN */ + }, + .tclk = /* TCLK CLOCK configuration. */ + { + .tclkfreq[0] = 0, /* TCLK0 */ + .tclkfreq[1] = 0, /* TCLK1 */ + .tclkfreq[2] = 0, /* TCLK2 */ + .initialize = true, /* Initialize */ + }, + .platgate = /* Platform Gate Clock configuration. */ + { + .initialize = true, /* Initialize */ + .mscm = true, /* CGCMSCM */ + .mpu = true, /* CGCMPU */ + .dma = true, /* CGCDMA */ + .erm = true, /* CGCERM */ + .eim = true, /* CGCEIM */ + }, + .traceclk = /* Debug trace Clock Configuration. */ + { + .source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */ + .divider = 1, /* TRACEDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = true, /* TRACEDIVEN */ + .fraction = false, /* TRACEFRAC */ + }, +#ifdef CONFIG_S32K1XX_HAVE_QSPI + .qspirefclk = /* Quad Spi Internal Reference Clock Gating. */ + { + .refclk = false, /* Qspi reference clock gating */ + }, +#endif + }, + .pcc = + { + .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */ + .pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */ + }, + .pmc = + { + .lpoclk = /* Low Power Clock configuration. */ + { + .trim = 0, /* Trimming value for LPO */ + .initialize = true, /* Initialize */ + .enable = true, /* Enable/disable LPO */ + }, + } +}; diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c new file mode 100644 index 00000000000..d2dc57f77a5 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclks.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "s32k1xx_periphclocks.h" +#include "rddrone-uavcan146.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial peripheral clocking. + */ + +const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = +{ + { + .clkname = ADC0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = ADC1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPI2C0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI1_CLK, + .clkgate = false, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI2_CLK, + .clkgate = false, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPTMR0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART2_CLK, + .clkgate = false, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTA_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTB_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTC_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTD_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTE_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + } +}; diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c new file mode 100644 index 00000000000..d9ca69a677e --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c @@ -0,0 +1,199 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" + +#include "s32k1xx_config.h" +#include "s32k1xx_lpspi.h" +#include "s32k1xx_pin.h" +#include "rddrone-uavcan146.h" + +#if defined(CONFIG_S32K1XX_LPSPI0) || defined(CONFIG_S32K1XX_LPSPI1) || \ + defined(CONFIG_S32K1XX_LPSPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the RDDRONE-UAVCAN146 + * board. + * + ****************************************************************************/ + +void weak_function s32k1xx_spidev_initialize(void) +{ +#ifdef CONFIG_S32K1XX_LPSPI0 + s32k1xx_pinconfig(PIN_LPSPI0_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi0; + g_lpspi0 = s32k1xx_lpspibus_initialize(0); + + if (!g_lpspi0) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI0\n"); + } + + spi_register(g_lpspi0, 0); +#endif +#endif + +#ifdef CONFIG_S32K1XX_LPSPI1 + s32k1xx_pinconfig(PIN_LPSPI1_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi1; + g_lpspi1 = s32k1xx_lpspibus_initialize(1); + + if (!g_lpspi1) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI1\n"); + } + + spi_register(g_lpspi1, 1); +#endif +#endif + +#ifdef CONFIG_S32K1XX_LPSPI2 + s32k1xx_pinconfig(PIN_LPSPI2_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi2; + g_lpspi2 = s32k1xx_lpspibus_initialize(2); + + if (!g_lpspi2) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI2\n"); + } + + spi_register(g_lpspi2, 2); +#endif +#endif +} + +/**************************************************************************** + * Name: s32k1xx_lpspi0/1/2select and s32k1xx_lpspi0/1/2status + * + * Description: + * The external functions, s32k1xx_lpspi0/1/2select and + * s32k1xx_lpspi0/1/2status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including s32k1xx_lpspibus_initialize()) are provided + * by common logic. To use this common SPI logic on your board: + * + * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_LPSPI0 +void s32k1xx_lpspi0select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI0_PCS, !selected); +} + +uint8_t s32k1xx_lpspi0status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_S32K1XX_LPSPI1 +void s32k1xx_lpspi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI1_PCS, !selected); +} + +uint8_t s32k1xx_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_S32K1XX_LPSPI2 +void s32k1xx_lpspi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI2_PCS, !selected); +} + +uint8_t s32k1xx_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_S32K1XX_LPSPI0 || CONFIG_S32K1XX_LPSPI01 || CONFIG_S32K1XX_LPSPI2 */ diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_userleds.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_userleds.c new file mode 100644 index 00000000000..3b66e0dd73d --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_userleds.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_userleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "rddrone-uavcan146.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED_R) + { + ledcfg = GPIO_LED_R; + } + else if (led == BOARD_LED_G) + { + ledcfg = GPIO_LED_G; + } + else if (led == BOARD_LED_B) + { + ledcfg = GPIO_LED_B; + } + else + { + return; + } + + s32k1xx_gpiowrite(ledcfg, ledon); /* High illuminates */ +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + s32k1xx_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/s32k118evb/README.txt b/boards/arm/s32k1xx/s32k118evb/README.txt index 1e9c468a160..37aa3278b56 100644 --- a/boards/arm/s32k1xx/s32k118evb/README.txt +++ b/boards/arm/s32k1xx/s32k118evb/README.txt @@ -65,7 +65,7 @@ LEDs and Buttons the common RGB LED driver. If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board - the s32k118evb. The following definitions describe how NuttX controls the + the S32K118EVB. The following definitions describe how NuttX controls the LEDs: ==========================================+========+========+========= @@ -80,7 +80,7 @@ LEDs and Buttons LED_SIGNAL In a signal handler (no change) LED_ASSERTION An assertion failed (no change) LED_PANIC The system has crashed FLASH OFF OFF - LED_IDLE S32K118EVN in sleep mode (no change) + LED_IDLE S32K118EVB in sleep mode (no change) ==========================================+========+========+========= Buttons diff --git a/boards/arm/s32k1xx/s32k118evb/include/board.h b/boards/arm/s32k1xx/s32k118evb/include/board.h index 065edbaf0e7..23f0cd0f2ab 100644 --- a/boards/arm/s32k1xx/s32k118evb/include/board.h +++ b/boards/arm/s32k1xx/s32k118evb/include/board.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_S32K118EVB_INCLUDE_BOARD_H +#define __BOARDS_ARM_S32K118EVB_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -89,10 +89,9 @@ #define BOARD_LED_B_BIT (1 << BOARD_LED_B) /* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board - * the s32k118evb. The following definitions describe how NuttX controls the + * the S32K118EVB. The following definitions describe how NuttX controls the * LEDs: * - * * SYMBOL Meaning LED state * RED GREEN BLUE * ------------------- ---------------------------- ----------------- @@ -106,7 +105,7 @@ #define LED_SIGNAL 0 /* In a signal handler (no change) */ #define LED_ASSERTION 0 /* An assertion failed (no change) */ #define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ -#undef LED_IDLE /* S32K118EVN in sleep mode (Not used) */ +#undef LED_IDLE /* S32K118EVB in sleep mode (Not used) */ /* Button definitions *******************************************************/ @@ -134,7 +133,4 @@ #define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTB0 */ #define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTB1 */ -/* DMA Channel/Stream Selections ********************************************/ - - -#endif /* __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_S32K118EVB_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k1xx/s32k118evb/src/Makefile b/boards/arm/s32k1xx/s32k118evb/src/Makefile index ef53d27691a..87cf7773b89 100644 --- a/boards/arm/s32k1xx/s32k118evb/src/Makefile +++ b/boards/arm/s32k1xx/s32k118evb/src/Makefile @@ -36,21 +36,21 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = s32k118_boot.c s32k118_bringup.c s32k118_clockconfig.c -CSRCS += s32k118_periphclocks.c +CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c +CSRCS += s32k1xx_periphclocks.c ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += s32k118_autoleds.c +CSRCS += s32k1xx_autoleds.c else -CSRCS += s32k118_userleds.c +CSRCS += s32k1xx_userleds.c endif ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += s32k118_buttons.c +CSRCS += s32k1xx_buttons.c endif ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += s32k118_appinit.c +CSRCS += s32k1xx_appinit.c endif include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h b/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h index 4a0c3fb6a72..76108fd80d7 100644 --- a/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h @@ -80,7 +80,6 @@ /* SPI chip selects */ - /* Count of peripheral clock user configurations */ #define NUM_OF_PERIPHERAL_CLOCKS_0 10 @@ -90,7 +89,7 @@ ****************************************************************************/ /**************************************************************************** - * Public data + * Public Data ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -100,11 +99,11 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; /**************************************************************************** - * Public Functions + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: s32k118_bringup + * Name: s32k1xx_bringup * * Description: * Perform architecture-specific initialization @@ -117,19 +116,19 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; * ****************************************************************************/ -int s32k118_bringup(void); +int s32k1xx_bringup(void); /**************************************************************************** - * Name: s32k118_spidev_initialize + * Name: s32k1xx_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the s32k118evb + * Called to configure SPI chip select GPIO pins for the S32K118EVB * board. * ****************************************************************************/ #ifdef CONFIG_S32K1XX_SPI -void s32k118_spidev_initialize(void); +void s32k1xx_spidev_initialize(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c new file mode 100644 index 00000000000..333806cfd3a --- /dev/null +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "s32k118evb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return s32k1xx_bringup(); +#endif +} diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_autoleds.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_autoleds.c new file mode 100644 index 00000000000..5c9cee4f0c2 --- /dev/null +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_autoleds.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_autoleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K118EVB has one RGB LED: + * + * RedLED PTD16 (FTM0CH1) + * GreenLED PTD15 (FTM0CH0) + * BlueLED PTE8 (FTM0CH6) + * + * An output of '1' illuminates the LED. + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Freedom K66F. The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ----------------------- ----------------- + * LED_STARTED NuttX has been started OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + * LED_IRQSENABLED Interrupts enabled OFF OFF ON + * LED_STACKCREATED Idle stack created OFF ON OFF + * LED_INIRQ In an interrupt (no change) + * LED_SIGNAL In a signal handler (no change) + * LED_ASSERTION An assertion failed (no change) + * LED_PANIC The system has crashed FLASH OFF OFF + * LED_IDLE K66 is in sleep mode (Optional, not used) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "s32k118evb.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Summary of all possible settings */ + +#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ +#define LED_OFF_OFF_OFF 1 /* LED_STARTED */ +#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */ +#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */ +#define LED_ON_OFF_OFF 4 /* LED_PANIC */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led != LED_NOCHANGE) + { + bool redon = false; + bool greenon = false; + bool blueon = false; + + switch (led) + { + default: + case LED_OFF_OFF_OFF: + break; + + case LED_OFF_OFF_ON: + blueon = true; + break; + + case LED_OFF_ON_OFF: + greenon = true; + break; + + case LED_ON_OFF_OFF: + redon = true; + break; + } + + s32k1xx_gpiowrite(GPIO_LED_R, redon); + s32k1xx_gpiowrite(GPIO_LED_G, greenon); + s32k1xx_gpiowrite(GPIO_LED_B, blueon); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_ON_OFF_OFF) + { + s32k1xx_gpiowrite(GPIO_LED_R, true); + s32k1xx_gpiowrite(GPIO_LED_G, false); + s32k1xx_gpiowrite(GPIO_LED_B, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c new file mode 100644 index 00000000000..d2faffc55dd --- /dev/null +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "s32k118evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_board_initialize + * + * Description: + * All S32K1XX architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void s32k1xx_board_initialize(void) +{ +#ifdef CONFIG_S32K1XX_SPI + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function s32k1xx_spidev_initialize() has been brought into the link. + */ + + s32k1xx_spidev_initialize(); +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + s32k1xx_bringup(); +} +#endif diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c new file mode 100644 index 00000000000..495468a7842 --- /dev/null +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "s32k118evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k1xx_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_buttons.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_buttons.c new file mode 100644 index 00000000000..b03eb8647c6 --- /dev/null +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_buttons.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_buttons.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K118EVB supports two buttons: + * + * SW2 PTD3 + * SW3 PTD5 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "s32k1xx_pin.h" +#include "s32k118evb.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + /* Configure the GPIO pins as interrupting inputs. */ + + s32k1xx_pinconfig(GPIO_SW2); + s32k1xx_pinconfig(GPIO_SW3); +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + if (s32k1xx_gpioread(GPIO_SW2)) + { + ret |= BUTTON_SW2_BIT; + } + + if (s32k1xx_gpioread(GPIO_SW3)) + { + ret |= BUTTON_SW3_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + uint32_t pinset; + int ret; + + /* Map the button id to the GPIO bit set. */ + + if (id == BUTTON_SW2) + { + pinset = GPIO_SW2; + } + else if (id == BUTTON_SW3) + { + pinset = GPIO_SW3; + } + else + { + return -EINVAL; + } + + /* The button has already been configured as an interrupting input (by + * board_button_initialize() above). + * + * Attach the new button handler. + */ + + ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL); + if (ret >= 0) + { + /* Then make sure that interrupts are enabled on the pin */ + + s32k1xx_pinirqenable(pinset); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c new file mode 100644 index 00000000000..cbec87dba58 --- /dev/null +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c @@ -0,0 +1,208 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "s32k1xx_clockconfig.h" +#include "s32k1xx_start.h" +#include "s32k118evb.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial board clocking. + */ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .scg = + { + .sirc = + { + .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* SIRCSTEN */ + .lowpower = true, /* SIRCLPEN */ + .locked = false, /* LK */ + }, + .firc = + { + .range = SCG_FIRC_RANGE_48M, /* RANGE */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .regulator = true, /* FIRCREGOFF */ + .locked = false, /* LK */ + }, + .sosc = + { + .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */ + .gain = SCG_SOSC_GAIN_LOW, /* HGO */ + .range = SCG_SOSC_RANGE_HIGH, /* RANGE */ + .extref = SCG_SOSC_REF_OSC, /* EREFS */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .locked = false, /* LK */ + }, + .rtc = + { + .initialize = true, /* Initialize */ + .clkin = 0 /* RTC_CLKIN */ + }, + .clockout = + { + .source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */ + .initialize = true, /* Initialize */ + }, + .clockmode = + { + .rccr = /* RCCR - Run Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_FIRC, /* SCS */ + .divslow = 2, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 1 /* DIVCORE, range 1..16 */ + }, + .vccr = /* VCCR - VLPR Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */ + .divslow = 4, /* DIVSLOW, range 1..16 */ + .divbus = 1, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + + /* .altclk */ + + .initialize = true, /* Initialize */ + }, + }, + .sim = + { + .clockout = /* Clock Out configuration. */ + { + .source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */ + .divider = 1, /* CLKOUTDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = false, /* CLKOUTEN */ + }, + .lpoclk = /* Low Power Clock configuration. */ + { + .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ + .initialize = true, /* Initialize */ + .lpo32k = true, /* LPO32KCLKEN */ + .lpo1k = true, /* LPO1KCLKEN */ + }, + .tclk = /* TCLK CLOCK configuration. */ + { + .tclkfreq[0] = 0, /* TCLK0 */ + .tclkfreq[1] = 0, /* TCLK1 */ + .tclkfreq[2] = 0, /* TCLK2 */ + .initialize = true, /* Initialize */ + }, + .platgate = /* Platform Gate Clock configuration. */ + { + .initialize = true, /* Initialize */ + .mscm = true, /* CGCMSCM */ + .mpu = true, /* CGCMPU */ + .dma = true, /* CGCDMA */ + .erm = true, /* CGCERM */ + .eim = true, /* CGCEIM */ + }, + .traceclk = /* Debug trace Clock Configuration. */ + { + .source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */ + .divider = 1, /* TRACEDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = true, /* TRACEDIVEN */ + .fraction = false, /* TRACEFRAC */ + }, +#ifdef CONFIG_S32K1XX_HAVE_QSPI + .qspirefclk = /* Quad Spi Internal Reference Clock Gating. */ + { + .refclk = false, /* Qspi reference clock gating */ + }, +#endif + }, + .pcc = + { + .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */ + .pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */ + }, + .pmc = + { + .lpoclk = /* Low Power Clock configuration. */ + { + .trim = 0, /* Trimming value for LPO */ + .initialize = true, /* Initialize */ + .enable = true, /* Enable/disable LPO */ + }, + } +}; diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclocks.c new file mode 100644 index 00000000000..370d7e419a8 --- /dev/null +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclocks.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclks.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "s32k1xx_periphclocks.h" +#include "s32k118evb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial peripheral clocking. + */ + +const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = +{ + { + .clkname = ADC0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC_DIV2, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = DMAMUX0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPTMR0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC_DIV2, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC_DIV2, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC_DIV2, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTA_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTB_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTC_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTD_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTE_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, +}; diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c new file mode 100644 index 00000000000..5091c46e688 --- /dev/null +++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "s32k118evb.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED_R) + { + ledcfg = GPIO_LED_R; + } + else if (led == BOARD_LED_G) + { + ledcfg = GPIO_LED_G; + } + else if (led == BOARD_LED_B) + { + ledcfg = GPIO_LED_B; + } + else + { + return; + } + + s32k1xx_gpiowrite(ledcfg, ledon); /* High illuminates */ +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + s32k1xx_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/s32k144evb/Kconfig b/boards/arm/s32k1xx/s32k144evb/Kconfig new file mode 100644 index 00000000000..cbc4ad6b192 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_S32K144EVB + +endif # ARCH_BOARD_S32K144EVB diff --git a/boards/arm/s32k1xx/s32k144evb/README.txt b/boards/arm/s32k1xx/s32k144evb/README.txt new file mode 100644 index 00000000000..eb55fb7d699 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/README.txt @@ -0,0 +1,15 @@ +README +====== + +This directory holds the port to the NXP S32K144EVB-Q100 development board. + +Contents +======== + + o Status + +Status +====== + + 2020-01-23: Configuration created (copy-paste from S32K146EVB). + Tested: Serial console, I2C, SPI. \ No newline at end of file diff --git a/boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig new file mode 100644 index 00000000000..8269069fd79 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="s32k144evb" +CONFIG_ARCH_BOARD_S32K144EVB=y +CONFIG_ARCH_CHIP="s32k1xx" +CONFIG_ARCH_CHIP_S32K144=y +CONFIG_ARCH_CHIP_S32K14X=y +CONFIG_ARCH_CHIP_S32K1XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_LPUART1_RXBUFSIZE=64 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_LPUART1_TXBUFSIZE=64 +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MOTOROLA_SREC=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=61440 +CONFIG_RAM_START=0x1fff8000 +CONFIG_RR_INTERVAL=200 +CONFIG_S32K1XX_LPUART1=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=18 +CONFIG_START_MONTH=8 +CONFIG_START_YEAR=2019 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_CXXINITIALIZE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/s32k1xx/s32k144evb/include/board.h b/boards/arm/s32k1xx/s32k144evb/include/board.h new file mode 100644 index 00000000000..de638025972 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/include/board.h @@ -0,0 +1,164 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/include/board.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_S32K144EVB_INCLUDE_BOARD_H +#define __BOARDS_ARM_S32K144EVB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The S32K144EVB is fitted with a 8MHz Crystal */ + +#define BOARD_XTAL_FREQUENCY 8000000 + +/* The S32K144 will run at 112MHz */ + +/* LED definitions **********************************************************/ + +/* The S32K144EVB has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual RGB + * components. + * + * The RGB components could, alternatively be controlled through PWM using + * the common RGB LED driver. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_R 0 +#define BOARD_LED_G 1 +#define BOARD_LED_B 2 +#define BOARD_NLEDS 3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_R_BIT (1 << BOARD_LED_R) +#define BOARD_LED_G_BIT (1 << BOARD_LED_G) +#define BOARD_LED_B_BIT (1 << BOARD_LED_B) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board + * the S32K144EVB. The following definitions describe how NuttX controls the + * LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ---------------------------- ----------------- + */ + +#define LED_STARTED 1 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 2 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF ON */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON OFF */ +#define LED_INIRQ 0 /* In an interrupt (no change) */ +#define LED_SIGNAL 0 /* In a signal handler (no change) */ +#define LED_ASSERTION 0 /* An assertion failed (no change) */ +#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ +#undef LED_IDLE /* S32K144EVB in sleep mode (Not used) */ + +/* Button definitions *******************************************************/ + +/* The S32K144EVB supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +#define BUTTON_SW2 0 +#define BUTTON_SW3 1 +#define NUM_BUTTONS 2 + +#define BUTTON_SW2_BIT (1 << BUTTON_SW2) +#define BUTTON_SW3_BIT (1 << BUTTON_SW3) + +/* Alternate function pin selections ****************************************/ + +/* By default, the serial console will be provided on the OpenSDA VCOM port: + * + * OpenSDA UART TX PTC7 (LPUART1_TX) + * OpenSDA UART RX PTC6 (LPUART1_RX) + */ + +#define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTB0 */ +#define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTB1 */ + +#define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */ +#define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */ + +#define PIN_LPUART2_RX PIN_LPUART2_RX_1 /* PTA8 */ +#define PIN_LPUART2_TX PIN_LPUART2_TX_1 /* PTA9 */ + +/* SPI selections ***********************************************************/ + +#define PIN_LPSPI0_SCK PIN_LPSPI0_SCK_2 /* PTB2 */ +#define PIN_LPSPI0_MISO PIN_LPSPI0_SIN_2 /* PTB3 */ +#define PIN_LPSPI0_MOSI PIN_LPSPI0_SOUT_3 /* PTB4 */ +#define PIN_LPSPI0_PCS PIN_LPSPI0_PCS0_1 /* PTB0 */ + +#define PIN_LPSPI1_SCK PIN_LPSPI1_SCK_1 /* PTB14 */ +#define PIN_LPSPI1_MISO PIN_LPSPI1_SIN_1 /* PTB15 */ +#define PIN_LPSPI1_MOSI PIN_LPSPI1_SOUT_1 /* PTB16 */ +#define PIN_LPSPI1_PCS PIN_LPSPI1_PCS3 /* PTB17 */ + +#define PIN_LPSPI2_SCK PIN_LPSPI2_SCK_2 /* PTE15 */ +#define PIN_LPSPI2_MISO PIN_LPSPI2_SIN_2 /* PTE16 */ +#define PIN_LPSPI2_MOSI PIN_LPSPI2_SOUT_1 /* PTA8 */ +#define PIN_LPSPI2_PCS PIN_LPSPI2_PCS0_2 /* PTA9 */ + +/* I2C selections ***********************************************************/ + +#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */ +#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */ + +#endif /* __BOARDS_ARM_S32K144EVB_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs b/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs new file mode 100644 index 00000000000..985e30c4a26 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs @@ -0,0 +1,131 @@ +############################################################################ +# boards/arm/s32k1xx/s32k144evb/scripts/Make.defs +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y) + LDSCRIPT = flash.ld +else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y) + LDSCRIPT = sram.ld +endif + +$(warning, LDSCRIPT is $(LDSCRIPT)) +ifeq ($(WINTOOL),y) + # Windows-native toolchains + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif +$(warning, LDSCRIPT is $(LDSCRIPT)) +$(warning, ARCHSCRIPT is $(ARCHSCRIPT)) + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = +ifeq ($(CONFIG_HOST_WINDOWS),y) + HOSTEXEEXT = .exe +else + HOSTEXEEXT = +endif + +ifeq ($(WINTOOL),y) + # Windows-native host tools + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh +else + # Linux/Cygwin-native host tools + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) +endif diff --git a/boards/arm/s32k1xx/s32k144evb/scripts/flash.ld b/boards/arm/s32k1xx/s32k144evb/scripts/flash.ld new file mode 100644 index 00000000000..8d153a622c9 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/scripts/flash.ld @@ -0,0 +1,152 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/scripts/flash.ld + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K144 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 60Kb of SRAM beginning at address 0x1fff:8000 (plus 4Kb of FlexRAM) + * + * The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is + * implemented such that the SRAM_L and SRAM_U ranges form a contiguous + * block in the memory map + * + * SRAM_L 1fff8000 - 1fffffff 32Kb + * SRAM_U 20000000 - 20006fff 28Kb + */ + +MEMORY +{ + vflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K + pflash (rx) : ORIGIN = 0x00000400, LENGTH = 16 + dflash (rx) : ORIGIN = 0x00000410, LENGTH = 511K-16 + sram (rwx) : ORIGIN = 0x1fff8000, LENGTH = 60K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +EXTERN(g_flashcfg) +ENTRY(_stext) + +SECTIONS +{ + .vectors : + { + _stext = ABSOLUTE(.); + *(.vectors) + } > vflash + + .flashcfg : + { + *(.flashcfg) + } > pflash + + .text : + { + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > dflash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > dflash + + .ARM.extab : + { + *(.ARM.extab*) + } >dflash + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } >dflash + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > dflash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > dflash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/s32k1xx/s32k144evb/scripts/s32k144.cfg b/boards/arm/s32k1xx/s32k144evb/scripts/s32k144.cfg new file mode 100644 index 00000000000..7d30a9f05f0 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/scripts/s32k144.cfg @@ -0,0 +1,58 @@ +# +# NXP S32K144 - 1x ARM Cortex-M4 @ up to 112 MHz +# + +adapter_khz 4000 +transport select swd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s32k144 +} + +# +# M4 JTAG mode TAP +# +if { [info exists M4_JTAG_TAPID] } { + set _M4_JTAG_TAPID $M4_JTAG_TAPID +} else { + set _M4_JTAG_TAPID 0x4ba00477 +} + +# +# M4 SWD mode TAP +# +if { [info exists M4_SWD_TAPID] } { + set _M4_SWD_TAPID $M4_SWD_TAPID +} else { + set _M4_SWD_TAPID 0x2ba01477 +} + +source [find target/swj-dp.tcl] + +if { [using_jtag] } { + set _M4_TAPID $_M4_JTAG_TAPID +} else { + set _M4_TAPID $_M4_SWD_TAPID +} + +swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M4_TAPID + +target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 + +# S32K144 has 32+28 KB contiguous SRAM +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0xF000 +} +$_CHIPNAME.m4 configure -work-area-phys 0x1FFF8000 \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +$_CHIPNAME.m4 configure -rtos nuttx + +if { ![using_hla] } { + cortex_m reset_config vectreset +} diff --git a/boards/arm/s32k1xx/s32k144evb/scripts/sram.ld b/boards/arm/s32k1xx/s32k144evb/scripts/sram.ld new file mode 100644 index 00000000000..210555e0e9a --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/scripts/sram.ld @@ -0,0 +1,129 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/scripts/sram.ld + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K144 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 60Kb of SRAM beginning at address 0x1fff:8000 (plus 4Kb of FlexRAM) + * + * The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is + * implemented such that the SRAM_L and SRAM_U ranges form a contiguous + * block in the memory map + * + * SRAM_L 1fff8000 - 1fffffff 32Kb + * SRAM_U 20000000 - 20006fff 28Kb + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x1fff8000, LENGTH = 60K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > sram + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > sram + + .ARM.extab : + { + *(.ARM.extab*) + } >sram + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } >sram + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/s32k1xx/s32k144evb/src/.gitignore b/boards/arm/s32k1xx/s32k144evb/src/.gitignore new file mode 100644 index 00000000000..726d936e1e3 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/boards/arm/s32k1xx/s32k144evb/src/Makefile b/boards/arm/s32k1xx/s32k144evb/src/Makefile new file mode 100644 index 00000000000..27d9e16cf9a --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/Makefile @@ -0,0 +1,60 @@ +############################################################################ +# boards/arm/s32k1xx/s32k144evb/src/Makefile +# +# Copyright (C) 2019 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c +CSRCS += s32k1xx_periphclocks.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += s32k1xx_autoleds.c +else +CSRCS += s32k1xx_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += s32k1xx_buttons.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += s32k1xx_appinit.c +endif + +ifeq ($(CONFIG_S32K1XX_LPSPI),y) +CSRCS += s32k1xx_spi.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k144evb.h b/boards/arm/s32k1xx/s32k144evb/src/s32k144evb.h new file mode 100644 index 00000000000..546b44b0e68 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k144evb.h @@ -0,0 +1,135 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k144evb.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_S32K1XX_S32K144EVB_SRC_S32K144EVB_H +#define __BOARDS_ARM_S32K1XX_S32K144EVB_SRC_S32K144EVB_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "hardware/s32k1xx_pinmux.h" +#include "s32k1xx_periphclocks.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* S32K144EVB GPIOs *********************************************************/ + +/* LEDs. The S32K144EVB has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * An output of '1' illuminates the LED. + */ + +#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED_B (PIN_PTD0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) + +/* Buttons. The S32K144EVB supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH) +#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH) + +/* SPI chip selects */ + +/* Count of peripheral clock user configurations */ + +#define NUM_OF_PERIPHERAL_CLOCKS_0 15 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* User peripheral configuration structure 0 */ + +extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k1xx_bringup(void); + +/**************************************************************************** + * Name: s32k1xx_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the S32K144EVB + * board. + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_LPSPI +void s32k1xx_spidev_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_S32K1XX_S32K144EVB_SRC_S32K144EVB_H */ diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c new file mode 100644 index 00000000000..3806a1684e9 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "s32k144evb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return s32k1xx_bringup(); +#endif +} diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_autoleds.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_autoleds.c new file mode 100644 index 00000000000..6d41b8ac40c --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_autoleds.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_autoleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K144EVB has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * An output of '1' illuminates the LED. + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Freedom K66F. The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ----------------------- ----------------- + * LED_STARTED NuttX has been started OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + * LED_IRQSENABLED Interrupts enabled OFF OFF ON + * LED_STACKCREATED Idle stack created OFF ON OFF + * LED_INIRQ In an interrupt (no change) + * LED_SIGNAL In a signal handler (no change) + * LED_ASSERTION An assertion failed (no change) + * LED_PANIC The system has crashed FLASH OFF OFF + * LED_IDLE K66 is in sleep mode (Optional, not used) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "s32k144evb.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Summary of all possible settings */ + +#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ +#define LED_OFF_OFF_OFF 1 /* LED_STARTED */ +#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */ +#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */ +#define LED_ON_OFF_OFF 4 /* LED_PANIC */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led != LED_NOCHANGE) + { + bool redon = false; + bool greenon = false; + bool blueon = false; + + switch (led) + { + default: + case LED_OFF_OFF_OFF: + break; + + case LED_OFF_OFF_ON: + blueon = true; + break; + + case LED_OFF_ON_OFF: + greenon = true; + break; + + case LED_ON_OFF_OFF: + redon = true; + break; + } + + s32k1xx_gpiowrite(GPIO_LED_R, redon); + s32k1xx_gpiowrite(GPIO_LED_G, greenon); + s32k1xx_gpiowrite(GPIO_LED_B, blueon); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_ON_OFF_OFF) + { + s32k1xx_gpiowrite(GPIO_LED_R, true); + s32k1xx_gpiowrite(GPIO_LED_G, false); + s32k1xx_gpiowrite(GPIO_LED_B, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c new file mode 100644 index 00000000000..9cfb0cf6abf --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "s32k144evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_board_initialize + * + * Description: + * All S32K1XX architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void s32k1xx_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + s32k1xx_bringup(); +} +#endif diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c new file mode 100644 index 00000000000..607b3d41d4b --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_I2C_DRIVER +# include +# include "s32k1xx_lpi2c.h" +#endif + +#include "s32k144evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k1xx_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_S32K1XX_LPSPI + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function s32k1xx_spidev_initialize() has been brought into the link. + */ + + s32k1xx_spidev_initialize(); +#endif + +#if defined(CONFIG_S32K1XX_LPI2C0) && defined(CONFIG_I2C_DRIVER) + FAR struct i2c_master_s *i2c; + + i2c = s32k1xx_i2cbus_initialize(0); + if (i2c == NULL) + { + serr("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, 0); + if (ret < 0) + { + serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + s32k1xx_i2cbus_uninitialize(i2c); + } + } +#endif + + return ret; +} diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_buttons.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_buttons.c new file mode 100644 index 00000000000..d6c84d486b8 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_buttons.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_buttons.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K144EVB supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "s32k1xx_pin.h" +#include "s32k144evb.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + /* Configure the GPIO pins as interrupting inputs. */ + + s32k1xx_pinconfig(GPIO_SW2); + s32k1xx_pinconfig(GPIO_SW3); +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + if (s32k1xx_gpioread(GPIO_SW2)) + { + ret |= BUTTON_SW2_BIT; + } + + if (s32k1xx_gpioread(GPIO_SW3)) + { + ret |= BUTTON_SW3_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + uint32_t pinset; + int ret; + + /* Map the button id to the GPIO bit set. */ + + if (id == BUTTON_SW2) + { + pinset = GPIO_SW2; + } + else if (id == BUTTON_SW3) + { + pinset = GPIO_SW3; + } + else + { + return -EINVAL; + } + + /* The button has already been configured as an interrupting input (by + * board_button_initialize() above). + * + * Attach the new button handler. + */ + + ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL); + if (ret >= 0) + { + /* Then make sure that interrupts are enabled on the pin */ + + s32k1xx_pinirqenable(pinset); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c new file mode 100644 index 00000000000..15857655346 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c @@ -0,0 +1,227 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "s32k1xx_clockconfig.h" +#include "s32k1xx_start.h" +#include "s32k144evb.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial board clocking. + */ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .scg = + { + .sirc = + { + .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = true, /* SIRCSTEN */ + .lowpower = true, /* SIRCLPEN */ + .locked = false, /* LK */ + }, + .firc = + { + .range = SCG_FIRC_RANGE_48M, /* RANGE */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .regulator = true, /* FIRCREGOFF */ + .locked = false, /* LK */ + }, + .sosc = + { + .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */ + .gain = SCG_SOSC_GAIN_LOW, /* HGO */ + .range = SCG_SOSC_RANGE_MID, /* RANGE */ + .extref = SCG_SOSC_REF_OSC, /* EREFS */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .locked = false, /* LK */ + }, + .spll = + { + .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */ + .prediv = 1, /* PREDIV */ + .mult = 40, /* MULT */ + .src = 0, /* SOURCE */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .locked = false, /* LK */ + }, + .rtc = + { + .initialize = true, /* Initialize */ + .clkin = 0 /* RTC_CLKIN */ + }, + .clockout = + { + .source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */ + .initialize = true, /* Initialize */ + }, + .clockmode = + { + .rccr = /* RCCR - Run Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .vccr = /* VCCR - VLPR Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */ + .divslow = 4, /* DIVSLOW, range 1..16 */ + .divbus = 1, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .hccr = + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + + /* .altclk */ + + .initialize = true, /* Initialize */ + }, + }, + .sim = + { + .clockout = /* Clock Out configuration. */ + { + .source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */ + .divider = 1, /* CLKOUTDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = false, /* CLKOUTEN */ + }, + .lpoclk = /* Low Power Clock configuration. */ + { + .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ + .initialize = true, /* Initialize */ + .lpo32k = true, /* LPO32KCLKEN */ + .lpo1k = true, /* LPO1KCLKEN */ + }, + .tclk = /* TCLK CLOCK configuration. */ + { + .tclkfreq[0] = 0, /* TCLK0 */ + .tclkfreq[1] = 0, /* TCLK1 */ + .tclkfreq[2] = 0, /* TCLK2 */ + .initialize = true, /* Initialize */ + }, + .platgate = /* Platform Gate Clock configuration. */ + { + .initialize = true, /* Initialize */ + .mscm = true, /* CGCMSCM */ + .mpu = true, /* CGCMPU */ + .dma = true, /* CGCDMA */ + .erm = true, /* CGCERM */ + .eim = true, /* CGCEIM */ + }, + .traceclk = /* Debug trace Clock Configuration. */ + { + .source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */ + .divider = 1, /* TRACEDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = true, /* TRACEDIVEN */ + .fraction = false, /* TRACEFRAC */ + }, +#ifdef CONFIG_S32K1XX_HAVE_QSPI + .qspirefclk = /* Quad Spi Internal Reference Clock Gating. */ + { + .refclk = false, /* Qspi reference clock gating */ + }, +#endif + }, + .pcc = + { + .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */ + .pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */ + }, + .pmc = + { + .lpoclk = /* Low Power Clock configuration. */ + { + .trim = 0, /* Trimming value for LPO */ + .initialize = true, /* Initialize */ + .enable = true, /* Enable/disable LPO */ + }, + } +}; diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_periphclocks.c new file mode 100644 index 00000000000..03d6ae1c39c --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_periphclocks.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_periphclks.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "s32k1xx_periphclocks.h" +#include "s32k144evb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial peripheral clocking. + */ + +const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = +{ + { + .clkname = ADC0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = ADC1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPI2C0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI2_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPTMR0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART2_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTA_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTB_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTC_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTD_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTE_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + } +}; diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_spi.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_spi.c new file mode 100644 index 00000000000..8e01e931b7b --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_spi.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_spi.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" + +#include "s32k1xx_config.h" +#include "s32k1xx_lpspi.h" +#include "s32k1xx_pin.h" +#include "s32k144evb.h" + +#if defined(CONFIG_S32K1XX_LPSPI0) || defined(CONFIG_S32K1XX_LPSPI1) || \ + defined(CONFIG_S32K1XX_LPSPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the S32K144EVB board. + * + ****************************************************************************/ + +void weak_function s32k1xx_spidev_initialize(void) +{ +#ifdef CONFIG_S32K1XX_LPSPI0 + s32k1xx_pinconfig(PIN_LPSPI0_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi0; + g_lpspi0 = s32k1xx_lpspibus_initialize(0); + + if (!g_lpspi0) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI0\n"); + } + + spi_register(g_lpspi0, 0); +#endif +#endif + +#ifdef CONFIG_S32K1XX_LPSPI1 + s32k1xx_pinconfig(PIN_LPSPI1_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi1; + g_lpspi1 = s32k1xx_lpspibus_initialize(1); + + if (!g_lpspi1) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI1\n"); + } + + spi_register(g_lpspi1, 1); +#endif +#endif + +#ifdef CONFIG_S32K1XX_LPSPI2 + s32k1xx_pinconfig(PIN_LPSPI2_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi2; + g_lpspi2 = s32k1xx_lpspibus_initialize(2); + + if (!g_lpspi2) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI2\n"); + } + + spi_register(g_lpspi2, 2); +#endif +#endif +} + +/**************************************************************************** + * Name: s32k1xx_lpspi0/1/2select and s32k1xx_lpspi0/1/2status + * + * Description: + * The external functions, s32k1xx_lpspi0/1/2select and + * s32k1xx_lpspi0/1/2status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including s32k1xx_lpspibus_initialize()) are provided + * by common logic. To use this common SPI logic on your board: + * + * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_LPSPI0 +void s32k1xx_lpspi0select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI0_PCS, !selected); +} + +uint8_t s32k1xx_lpspi0status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_S32K1XX_LPSPI1 +void s32k1xx_lpspi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI1_PCS, !selected); +} + +uint8_t s32k1xx_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_S32K1XX_LPSPI2 +void s32k1xx_lpspi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI2_PCS, !selected); +} + +uint8_t s32k1xx_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_S32K1XX_LPSPI0 || CONFIG_S32K1XX_LPSPI01 || CONFIG_S32K1XX_LPSPI2 */ diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_userleds.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_userleds.c new file mode 100644 index 00000000000..da6c1c43166 --- /dev/null +++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_userleds.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_userleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "s32k144evb.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED_R) + { + ledcfg = GPIO_LED_R; + } + else if (led == BOARD_LED_G) + { + ledcfg = GPIO_LED_G; + } + else if (led == BOARD_LED_B) + { + ledcfg = GPIO_LED_B; + } + else + { + return; + } + + s32k1xx_gpiowrite(ledcfg, ledon); /* High illuminates */ +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + s32k1xx_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/s32k146evb/README.txt b/boards/arm/s32k1xx/s32k146evb/README.txt index 05540082fce..da7558982fa 100644 --- a/boards/arm/s32k1xx/s32k146evb/README.txt +++ b/boards/arm/s32k1xx/s32k146evb/README.txt @@ -72,7 +72,7 @@ LEDs and Buttons the common RGB LED driver. If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board - the s32k146evb. The following definitions describe how NuttX controls the + the S32K146EVB. The following definitions describe how NuttX controls the LEDs: ==========================================+========+========+========= @@ -87,7 +87,7 @@ LEDs and Buttons LED_SIGNAL In a signal handler (no change) LED_ASSERTION An assertion failed (no change) LED_PANIC The system has crashed FLASH OFF OFF - LED_IDLE S32K146EVN in sleep mode (no change) + LED_IDLE S32K146EVB in sleep mode (no change) ==========================================+========+========+========= Buttons diff --git a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig index e409d5a9772..fd617f512be 100644 --- a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig +++ b/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_CHIP_S32K146=y CONFIG_ARCH_CHIP_S32K14X=y CONFIG_ARCH_CHIP_S32K1XX=y CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2988 +CONFIG_BOARD_LOOPSPERMSEC=3997 CONFIG_BUILTIN=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y @@ -38,8 +38,8 @@ CONFIG_NSH_READLINE=y CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_WDOGS=16 -CONFIG_RAM_SIZE=23552 -CONFIG_RAM_START=0x1ffffc00 +CONFIG_RAM_SIZE=126976 +CONFIG_RAM_START=0x1fff0000 CONFIG_RR_INTERVAL=200 CONFIG_S32K1XX_LPUART1=y CONFIG_SCHED_WAITPID=y diff --git a/boards/arm/s32k1xx/s32k146evb/include/board.h b/boards/arm/s32k1xx/s32k146evb/include/board.h index da991a11b61..23cbfb77f00 100644 --- a/boards/arm/s32k1xx/s32k146evb/include/board.h +++ b/boards/arm/s32k1xx/s32k146evb/include/board.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_S32K146EVB_INCLUDE_BOARD_H +#define __BOARDS_ARM_S32K146EVB_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -89,10 +89,9 @@ #define BOARD_LED_B_BIT (1 << BOARD_LED_B) /* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board - * the s32k146evb. The following definitions describe how NuttX controls the + * the S32K146EVB. The following definitions describe how NuttX controls the * LEDs: * - * * SYMBOL Meaning LED state * RED GREEN BLUE * ------------------- ---------------------------- ----------------- @@ -106,7 +105,7 @@ #define LED_SIGNAL 0 /* In a signal handler (no change) */ #define LED_ASSERTION 0 /* An assertion failed (no change) */ #define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ -#undef LED_IDLE /* S32K146EVN in sleep mode (Not used) */ +#undef LED_IDLE /* S32K146EVB in sleep mode (Not used) */ /* Button definitions *******************************************************/ @@ -131,10 +130,35 @@ * OpenSDA UART RX PTC6 (LPUART1_RX) */ +#define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTB0 */ +#define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTB1 */ + #define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */ #define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */ -/* DMA Channel/Stream Selections ********************************************/ +#define PIN_LPUART2_RX PIN_LPUART2_RX_1 /* PTA8 */ +#define PIN_LPUART2_TX PIN_LPUART2_TX_1 /* PTA9 */ + +/* SPI selections ***********************************************************/ + +#define PIN_LPSPI0_SCK PIN_LPSPI0_SCK_2 /* PTB2 */ +#define PIN_LPSPI0_MISO PIN_LPSPI0_SIN_2 /* PTB3 */ +#define PIN_LPSPI0_MOSI PIN_LPSPI0_SOUT_3 /* PTB4 */ +#define PIN_LPSPI0_PCS PIN_LPSPI0_PCS0_1 /* PTB0 */ + +#define PIN_LPSPI1_SCK PIN_LPSPI1_SCK_1 /* PTB14 */ +#define PIN_LPSPI1_MISO PIN_LPSPI1_SIN_1 /* PTB15 */ +#define PIN_LPSPI1_MOSI PIN_LPSPI1_SOUT_1 /* PTB16 */ +#define PIN_LPSPI1_PCS PIN_LPSPI1_PCS3 /* PTB17 */ + +#define PIN_LPSPI2_SCK PIN_LPSPI2_SCK_2 /* PTE15 */ +#define PIN_LPSPI2_MISO PIN_LPSPI2_SIN_2 /* PTE16 */ +#define PIN_LPSPI2_MOSI PIN_LPSPI2_SOUT_1 /* PTA8 */ +#define PIN_LPSPI2_PCS PIN_LPSPI2_PCS0_2 /* PTA9 */ + +/* I2C selections ***********************************************************/ +#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */ +#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */ -#endif /* __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_S32K146EVB_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k1xx/s32k146evb/src/Makefile b/boards/arm/s32k1xx/s32k146evb/src/Makefile index 5237a2677db..f1a55d1ff56 100644 --- a/boards/arm/s32k1xx/s32k146evb/src/Makefile +++ b/boards/arm/s32k1xx/s32k146evb/src/Makefile @@ -36,21 +36,25 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = s32k146_boot.c s32k146_bringup.c s32k146_clockconfig.c -CSRCS += s32k146_periphclocks.c +CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c +CSRCS += s32k1xx_periphclocks.c ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += s32k146_autoleds.c +CSRCS += s32k1xx_autoleds.c else -CSRCS += s32k146_userleds.c +CSRCS += s32k1xx_userleds.c endif ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += s32k146_buttons.c +CSRCS += s32k1xx_buttons.c endif ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += s32k146_appinit.c +CSRCS += s32k1xx_appinit.c +endif + +ifeq ($(CONFIG_S32K1XX_LPSPI),y) +CSRCS += s32k1xx_spi.c endif include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h index 13cfc0cafed..a0903649231 100644 --- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h @@ -80,17 +80,16 @@ /* SPI chip selects */ - /* Count of peripheral clock user configurations */ -#define NUM_OF_PERIPHERAL_CLOCKS_0 11 +#define NUM_OF_PERIPHERAL_CLOCKS_0 15 /**************************************************************************** * Public Types ****************************************************************************/ /**************************************************************************** - * Public data + * Public Data ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -100,11 +99,11 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; /**************************************************************************** - * Public Functions + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: s32k146_bringup + * Name: s32k1xx_bringup * * Description: * Perform architecture-specific initialization @@ -117,19 +116,19 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; * ****************************************************************************/ -int s32k146_bringup(void); +int s32k1xx_bringup(void); /**************************************************************************** - * Name: s32k146_spidev_initialize + * Name: s32k1xx_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the s32k146evb + * Called to configure SPI chip select GPIO pins for the S32K146EVB * board. * ****************************************************************************/ #ifdef CONFIG_S32K1XX_SPI -void s32k146_spidev_initialize(void); +void s32k1xx_spidev_initialize(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_appinit.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_appinit.c new file mode 100644 index 00000000000..c829e6cf4bf --- /dev/null +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k146evb/src/s32k1xx_appinit.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "s32k146evb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return s32k1xx_bringup(); +#endif +} diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_autoleds.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_autoleds.c new file mode 100644 index 00000000000..99e1aa5d5d7 --- /dev/null +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_autoleds.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k146evb/src/s32k1xx_autoleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K146EVB has one RGB LED: + * + * RedLED PTD15 (FTM0 CH0) + * GreenLED PTD16 (FTM0 CH1) + * BlueLED PTD0 (FTM0 CH2) + * + * An output of '1' illuminates the LED. + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Freedom K66F. The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ----------------------- ----------------- + * LED_STARTED NuttX has been started OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + * LED_IRQSENABLED Interrupts enabled OFF OFF ON + * LED_STACKCREATED Idle stack created OFF ON OFF + * LED_INIRQ In an interrupt (no change) + * LED_SIGNAL In a signal handler (no change) + * LED_ASSERTION An assertion failed (no change) + * LED_PANIC The system has crashed FLASH OFF OFF + * LED_IDLE K66 is in sleep mode (Optional, not used) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "s32k146evb.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Summary of all possible settings */ + +#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ +#define LED_OFF_OFF_OFF 1 /* LED_STARTED */ +#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */ +#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */ +#define LED_ON_OFF_OFF 4 /* LED_PANIC */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led != LED_NOCHANGE) + { + bool redon = false; + bool greenon = false; + bool blueon = false; + + switch (led) + { + default: + case LED_OFF_OFF_OFF: + break; + + case LED_OFF_OFF_ON: + blueon = true; + break; + + case LED_OFF_ON_OFF: + greenon = true; + break; + + case LED_ON_OFF_OFF: + redon = true; + break; + } + + s32k1xx_gpiowrite(GPIO_LED_R, redon); + s32k1xx_gpiowrite(GPIO_LED_G, greenon); + s32k1xx_gpiowrite(GPIO_LED_B, blueon); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_ON_OFF_OFF) + { + s32k1xx_gpiowrite(GPIO_LED_R, true); + s32k1xx_gpiowrite(GPIO_LED_G, false); + s32k1xx_gpiowrite(GPIO_LED_B, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_boot.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_boot.c new file mode 100644 index 00000000000..67e215f57fc --- /dev/null +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k146evb/src/s32k1xx_boot.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "s32k146evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_board_initialize + * + * Description: + * All S32K1XX architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void s32k1xx_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + s32k1xx_bringup(); +} +#endif diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c new file mode 100644 index 00000000000..830d574fab1 --- /dev/null +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k146evb/src/s32k1xx_bringup.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_I2C_DRIVER +# include +# include "s32k1xx_lpi2c.h" +#endif + +#include "s32k146evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k1xx_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_S32K1XX_LPSPI + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function s32k1xx_spidev_initialize() has been brought into the link. + */ + + s32k1xx_spidev_initialize(); +#endif + +#if defined(CONFIG_S32K1XX_LPI2C0) && defined(CONFIG_I2C_DRIVER) + FAR struct i2c_master_s *i2c; + + i2c = s32k1xx_i2cbus_initialize(0); + if (i2c == NULL) + { + serr("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, 0); + if (ret < 0) + { + serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + s32k1xx_i2cbus_uninitialize(i2c); + } + } +#endif + + return ret; +} diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_buttons.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_buttons.c new file mode 100644 index 00000000000..4eb3653372e --- /dev/null +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_buttons.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k146evb/src/s32k1xx_buttons.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K146EVB supports two buttons: + * + * SW2 PTC12 + * SW3 PTC13 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "s32k1xx_pin.h" +#include "s32k146evb.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + /* Configure the GPIO pins as interrupting inputs. */ + + s32k1xx_pinconfig(GPIO_SW2); + s32k1xx_pinconfig(GPIO_SW3); +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + if (s32k1xx_gpioread(GPIO_SW2)) + { + ret |= BUTTON_SW2_BIT; + } + + if (s32k1xx_gpioread(GPIO_SW3)) + { + ret |= BUTTON_SW3_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + uint32_t pinset; + int ret; + + /* Map the button id to the GPIO bit set. */ + + if (id == BUTTON_SW2) + { + pinset = GPIO_SW2; + } + else if (id == BUTTON_SW3) + { + pinset = GPIO_SW3; + } + else + { + return -EINVAL; + } + + /* The button has already been configured as an interrupting input (by + * board_button_initialize() above). + * + * Attach the new button handler. + */ + + ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL); + if (ret >= 0) + { + /* Then make sure that interrupts are enabled on the pin */ + + s32k1xx_pinirqenable(pinset); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c new file mode 100644 index 00000000000..fd6aca0f6cb --- /dev/null +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c @@ -0,0 +1,227 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "s32k1xx_clockconfig.h" +#include "s32k1xx_start.h" +#include "s32k146evb.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial board clocking. + */ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .scg = + { + .sirc = + { + .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = true, /* SIRCSTEN */ + .lowpower = true, /* SIRCLPEN */ + .locked = false, /* LK */ + }, + .firc = + { + .range = SCG_FIRC_RANGE_48M, /* RANGE */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .regulator = true, /* FIRCREGOFF */ + .locked = false, /* LK */ + }, + .sosc = + { + .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */ + .gain = SCG_SOSC_GAIN_LOW, /* HGO */ + .range = SCG_SOSC_RANGE_MID, /* RANGE */ + .extref = SCG_SOSC_REF_OSC, /* EREFS */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .locked = false, /* LK */ + }, + .spll = + { + .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */ + .prediv = 1, /* PREDIV */ + .mult = 40, /* MULT */ + .src = 0, /* SOURCE */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .locked = false, /* LK */ + }, + .rtc = + { + .initialize = true, /* Initialize */ + .clkin = 0 /* RTC_CLKIN */ + }, + .clockout = + { + .source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */ + .initialize = true, /* Initialize */ + }, + .clockmode = + { + .rccr = /* RCCR - Run Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .vccr = /* VCCR - VLPR Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */ + .divslow = 4, /* DIVSLOW, range 1..16 */ + .divbus = 1, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .hccr = + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + + /* .altclk */ + + .initialize = true, /* Initialize */ + }, + }, + .sim = + { + .clockout = /* Clock Out configuration. */ + { + .source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */ + .divider = 1, /* CLKOUTDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = false, /* CLKOUTEN */ + }, + .lpoclk = /* Low Power Clock configuration. */ + { + .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ + .initialize = true, /* Initialize */ + .lpo32k = true, /* LPO32KCLKEN */ + .lpo1k = true, /* LPO1KCLKEN */ + }, + .tclk = /* TCLK CLOCK configuration. */ + { + .tclkfreq[0] = 0, /* TCLK0 */ + .tclkfreq[1] = 0, /* TCLK1 */ + .tclkfreq[2] = 0, /* TCLK2 */ + .initialize = true, /* Initialize */ + }, + .platgate = /* Platform Gate Clock configuration. */ + { + .initialize = true, /* Initialize */ + .mscm = true, /* CGCMSCM */ + .mpu = true, /* CGCMPU */ + .dma = true, /* CGCDMA */ + .erm = true, /* CGCERM */ + .eim = true, /* CGCEIM */ + }, + .traceclk = /* Debug trace Clock Configuration. */ + { + .source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */ + .divider = 1, /* TRACEDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = true, /* TRACEDIVEN */ + .fraction = false, /* TRACEFRAC */ + }, +#ifdef CONFIG_S32K1XX_HAVE_QSPI + .qspirefclk = /* Quad Spi Internal Reference Clock Gating. */ + { + .refclk = false, /* Qspi reference clock gating */ + }, +#endif + }, + .pcc = + { + .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */ + .pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */ + }, + .pmc = + { + .lpoclk = /* Low Power Clock configuration. */ + { + .trim = 0, /* Trimming value for LPO */ + .initialize = true, /* Initialize */ + .enable = true, /* Enable/disable LPO */ + }, + } +}; diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_periphclocks.c new file mode 100644 index 00000000000..a32065bf43a --- /dev/null +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_periphclocks.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k146evb/src/s32k1xx_periphclks.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "s32k1xx_periphclocks.h" +#include "s32k146evb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial peripheral clocking. + */ + +const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = +{ + { + .clkname = ADC0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = ADC1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPI2C0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPSPI2_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPTMR0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART2_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTA_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTB_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTC_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTD_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTE_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + } +}; diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_spi.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_spi.c new file mode 100644 index 00000000000..424b44c0328 --- /dev/null +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_spi.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_spi.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Ivan Ucherdzhiev + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" + +#include "s32k1xx_config.h" +#include "s32k1xx_lpspi.h" +#include "s32k1xx_pin.h" +#include "s32k146evb.h" + +#if defined(CONFIG_S32K1XX_LPSPI0) || defined(CONFIG_S32K1XX_LPSPI1) || \ + defined(CONFIG_S32K1XX_LPSPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the S32K144EVB board. + * + ****************************************************************************/ + +void weak_function s32k1xx_spidev_initialize(void) +{ +#ifdef CONFIG_S32K1XX_LPSPI0 + s32k1xx_pinconfig(PIN_LPSPI0_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi0; + g_lpspi0 = s32k1xx_lpspibus_initialize(0); + + if (!g_lpspi0) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI0\n"); + } + + spi_register(g_lpspi0, 0); +#endif +#endif + +#ifdef CONFIG_S32K1XX_LPSPI1 + s32k1xx_pinconfig(PIN_LPSPI1_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi1; + g_lpspi1 = s32k1xx_lpspibus_initialize(1); + + if (!g_lpspi1) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI1\n"); + } + + spi_register(g_lpspi1, 1); +#endif +#endif + +#ifdef CONFIG_S32K1XX_LPSPI2 + s32k1xx_pinconfig(PIN_LPSPI2_PCS); + +#ifdef CONFIG_SPI_DRIVER + struct spi_dev_s *g_lpspi2; + g_lpspi2 = s32k1xx_lpspibus_initialize(2); + + if (!g_lpspi2) + { + spierr("ERROR: [boot] FAILED to initialize LPSPI2\n"); + } + + spi_register(g_lpspi2, 2); +#endif +#endif +} + +/**************************************************************************** + * Name: s32k1xx_lpspi0/1/2select and s32k1xx_lpspi0/1/2status + * + * Description: + * The external functions, s32k1xx_lpspi0/1/2select and + * s32k1xx_lpspi0/1/2status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including s32k1xx_lpspibus_initialize()) are provided + * by common logic. To use this common SPI logic on your board: + * + * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_LPSPI0 +void s32k1xx_lpspi0select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI0_PCS, !selected); +} + +uint8_t s32k1xx_lpspi0status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_S32K1XX_LPSPI1 +void s32k1xx_lpspi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI1_PCS, !selected); +} + +uint8_t s32k1xx_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_S32K1XX_LPSPI2 +void s32k1xx_lpspi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + s32k1xx_gpiowrite(PIN_LPSPI2_PCS, !selected); +} + +uint8_t s32k1xx_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_S32K1XX_LPSPI0 || CONFIG_S32K1XX_LPSPI01 || CONFIG_S32K1XX_LPSPI2 */ diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_userleds.c b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_userleds.c new file mode 100644 index 00000000000..0586a1d861f --- /dev/null +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k1xx_userleds.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k146evb/src/s32k1xx_userleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "s32k146evb.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED_R) + { + ledcfg = GPIO_LED_R; + } + else if (led == BOARD_LED_G) + { + ledcfg = GPIO_LED_G; + } + else if (led == BOARD_LED_B) + { + ledcfg = GPIO_LED_B; + } + else + { + return; + } + + s32k1xx_gpiowrite(ledcfg, ledon); /* High illuminates */ +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + s32k1xx_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/s32k148evb/README.txt b/boards/arm/s32k1xx/s32k148evb/README.txt index 685861140e8..3cb84c19171 100644 --- a/boards/arm/s32k1xx/s32k148evb/README.txt +++ b/boards/arm/s32k1xx/s32k148evb/README.txt @@ -54,7 +54,7 @@ LEDs and Buttons the common RGB LED driver. If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board - the s32k148evb. The following definitions describe how NuttX controls the + the S32K148EVB. The following definitions describe how NuttX controls the LEDs: ==========================================+========+========+========= @@ -69,7 +69,7 @@ LEDs and Buttons LED_SIGNAL In a signal handler (no change) LED_ASSERTION An assertion failed (no change) LED_PANIC The system has crashed FLASH OFF OFF - LED_IDLE S32K148EVN in sleep mode (no change) + LED_IDLE S32K148EVB in sleep mode (no change) ==========================================+========+========+========= Buttons diff --git a/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig index bdbf7d32465..5e79caadc7e 100644 --- a/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig +++ b/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig @@ -38,8 +38,8 @@ CONFIG_NSH_READLINE=y CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_WDOGS=16 -CONFIG_RAM_SIZE=23552 -CONFIG_RAM_START=0x1ffffc00 +CONFIG_RAM_SIZE=258048 +CONFIG_RAM_START=0x1ffe0000 CONFIG_RR_INTERVAL=200 CONFIG_S32K1XX_LPUART1=y CONFIG_SCHED_WAITPID=y diff --git a/boards/arm/s32k1xx/s32k148evb/include/board.h b/boards/arm/s32k1xx/s32k148evb/include/board.h index d8ae4d9a986..be8ccdf64db 100644 --- a/boards/arm/s32k1xx/s32k148evb/include/board.h +++ b/boards/arm/s32k1xx/s32k148evb/include/board.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_S32K148EVB_INCLUDE_BOARD_H +#define __BOARDS_ARM_S32K148EVB_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -89,10 +89,9 @@ #define BOARD_LED_B_BIT (1 << BOARD_LED_B) /* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board - * the s32k148evb. The following definitions describe how NuttX controls the + * the S32K148EVB. The following definitions describe how NuttX controls the * LEDs: * - * * SYMBOL Meaning LED state * RED GREEN BLUE * ------------------- ---------------------------- ----------------- @@ -106,7 +105,7 @@ #define LED_SIGNAL 0 /* In a signal handler (no change) */ #define LED_ASSERTION 0 /* An assertion failed (no change) */ #define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ -#undef LED_IDLE /* S32K148EVN in sleep mode (Not used) */ +#undef LED_IDLE /* S32K148EVB in sleep mode (Not used) */ /* Button definitions *******************************************************/ @@ -134,7 +133,4 @@ #define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */ #define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */ -/* DMA Channel/Stream Selections ********************************************/ - - -#endif /* __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_S32K148EVB_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld b/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld index b59ab9b42b8..13734e3be77 100644 --- a/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld +++ b/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld @@ -49,7 +49,7 @@ MEMORY vflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K pflash (rx) : ORIGIN = 0x00000400, LENGTH = 16 dflash (rx) : ORIGIN = 0x00000410, LENGTH = 2047K-16 - sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 252K + sram (rwx) : ORIGIN = 0x1ffe0000, LENGTH = 252K } OUTPUT_ARCH(arm) diff --git a/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld b/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld index c5819bf127c..42a9a2c130d 100644 --- a/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld +++ b/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld @@ -47,7 +47,7 @@ MEMORY { flash (rx) : ORIGIN = 0x00000000, LENGTH = 2M - sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 252K + sram (rwx) : ORIGIN = 0x1ffe0000, LENGTH = 252K } OUTPUT_ARCH(arm) diff --git a/boards/arm/s32k1xx/s32k148evb/src/Makefile b/boards/arm/s32k1xx/s32k148evb/src/Makefile index 706098e3e84..15a55fe9b05 100644 --- a/boards/arm/s32k1xx/s32k148evb/src/Makefile +++ b/boards/arm/s32k1xx/s32k148evb/src/Makefile @@ -36,21 +36,21 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = s32k148_boot.c s32k148_bringup.c s32k148_clockconfig.c -CSRCS += s32k148_periphclocks.c +CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c +CSRCS += s32k1xx_periphclocks.c ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += s32k148_autoleds.c +CSRCS += s32k1xx_autoleds.c else -CSRCS += s32k148_userleds.c +CSRCS += s32k1xx_userleds.c endif ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += s32k148_buttons.c +CSRCS += s32k1xx_buttons.c endif ifeq ($(CONFIG_LIB_BOARDCTL),y) -CSRCS += s32k148_appinit.c +CSRCS += s32k1xx_appinit.c endif include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h b/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h index ba85f505a57..068d74d63f6 100644 --- a/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h @@ -80,17 +80,16 @@ /* SPI chip selects */ - /* Count of peripheral clock user configurations */ -#define NUM_OF_PERIPHERAL_CLOCKS_0 11 +#define NUM_OF_PERIPHERAL_CLOCKS_0 14 /**************************************************************************** * Public Types ****************************************************************************/ /**************************************************************************** - * Public data + * Public Data ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -100,11 +99,11 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; /**************************************************************************** - * Public Functions + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: s32k148_bringup + * Name: s32k1xx_bringup * * Description: * Perform architecture-specific initialization @@ -117,19 +116,19 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; * ****************************************************************************/ -int s32k148_bringup(void); +int s32k1xx_bringup(void); /**************************************************************************** - * Name: s32k148_spidev_initialize + * Name: s32k1xx_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the s32k148evb + * Called to configure SPI chip select GPIO pins for the S32K148EVB * board. * ****************************************************************************/ #ifdef CONFIG_S32K1XX_SPI -void s32k148_spidev_initialize(void); +void s32k1xx_spidev_initialize(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_appinit.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_appinit.c new file mode 100644 index 00000000000..3ca3c884ab9 --- /dev/null +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k148evb/src/s32k1xx_appinit.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "s32k148evb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return s32k1xx_bringup(); +#endif +} diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_autoleds.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_autoleds.c new file mode 100644 index 00000000000..c2a6cbfb88c --- /dev/null +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_autoleds.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k148evb/src/s32k1xx_autoleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K148EVB has one RGB LED: + * + * RedLED PTE21 + * GreenLED PTE22 + * BlueLED PTE23 + * + * An output of '1' illuminates the LED. + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Freedom K66F. The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ----------------------- ----------------- + * LED_STARTED NuttX has been started OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + * LED_IRQSENABLED Interrupts enabled OFF OFF ON + * LED_STACKCREATED Idle stack created OFF ON OFF + * LED_INIRQ In an interrupt (no change) + * LED_SIGNAL In a signal handler (no change) + * LED_ASSERTION An assertion failed (no change) + * LED_PANIC The system has crashed FLASH OFF OFF + * LED_IDLE K66 is in sleep mode (Optional, not used) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "s32k148evb.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Summary of all possible settings */ + +#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ +#define LED_OFF_OFF_OFF 1 /* LED_STARTED */ +#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */ +#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */ +#define LED_ON_OFF_OFF 4 /* LED_PANIC */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led != LED_NOCHANGE) + { + bool redon = false; + bool greenon = false; + bool blueon = false; + + switch (led) + { + default: + case LED_OFF_OFF_OFF: + break; + + case LED_OFF_OFF_ON: + blueon = true; + break; + + case LED_OFF_ON_OFF: + greenon = true; + break; + + case LED_ON_OFF_OFF: + redon = true; + break; + } + + s32k1xx_gpiowrite(GPIO_LED_R, redon); + s32k1xx_gpiowrite(GPIO_LED_G, greenon); + s32k1xx_gpiowrite(GPIO_LED_B, blueon); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_ON_OFF_OFF) + { + s32k1xx_gpiowrite(GPIO_LED_R, true); + s32k1xx_gpiowrite(GPIO_LED_G, false); + s32k1xx_gpiowrite(GPIO_LED_B, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_boot.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_boot.c new file mode 100644 index 00000000000..246132e20f9 --- /dev/null +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k148evb/src/s32k1xx_boot.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "s32k148evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_board_initialize + * + * Description: + * All S32K1XX architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void s32k1xx_board_initialize(void) +{ +#ifdef CONFIG_S32K1XX_SPI + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function s32k1xx_spidev_initialize() has been brought into the link. + */ + + s32k1xx_spidev_initialize(); +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + s32k1xx_bringup(); +} +#endif diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c new file mode 100644 index 00000000000..790f16429d5 --- /dev/null +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "s32k148evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k1xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k1xx_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_buttons.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_buttons.c new file mode 100644 index 00000000000..5ecc5fd0e08 --- /dev/null +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_buttons.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k148evb/src/s32k1xx_buttons.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The S32K148EVB supports two buttons: + * + * SW3 PTC12 + * SW4 PTC13 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "s32k1xx_pin.h" +#include "s32k148evb.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + /* Configure the GPIO pins as interrupting inputs. */ + + s32k1xx_pinconfig(GPIO_SW3); + s32k1xx_pinconfig(GPIO_SW4); +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + if (s32k1xx_gpioread(GPIO_SW3)) + { + ret |= BUTTON_SW3_BIT; + } + + if (s32k1xx_gpioread(GPIO_SW4)) + { + ret |= BUTTON_SW4_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + uint32_t pinset; + int ret; + + /* Map the button id to the GPIO bit set. */ + + if (id == BUTTON_SW3) + { + pinset = GPIO_SW3; + } + else if (id == BUTTON_SW4) + { + pinset = GPIO_SW4; + } + else + { + return -EINVAL; + } + + /* The button has already been configured as an interrupting input (by + * board_button_initialize() above). + * + * Attach the new button handler. + */ + + ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL); + if (ret >= 0) + { + /* Then make sure that interrupts are enabled on the pin */ + + s32k1xx_pinirqenable(pinset); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c new file mode 100644 index 00000000000..1b5ccd9a118 --- /dev/null +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c @@ -0,0 +1,227 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "s32k1xx_clockconfig.h" +#include "s32k1xx_start.h" +#include "s32k148evb.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial board clocking. + */ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .scg = + { + .sirc = + { + .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* SIRCSTEN */ + .lowpower = true, /* SIRCLPEN */ + .locked = false, /* LK */ + }, + .firc = + { + .range = SCG_FIRC_RANGE_48M, /* RANGE */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .regulator = false, /* FIRCREGOFF */ + .locked = false, /* LK */ + }, + .sosc = + { + .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */ + .gain = SCG_SOSC_GAIN_LOW, /* HGO */ + .range = SCG_SOSC_RANGE_MID, /* RANGE */ + .extref = SCG_SOSC_REF_OSC, /* EREFS */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .lowpower = false, /* */ + .locked = false, /* LK */ + }, + .spll = + { + .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */ + .prediv = 1, /* PREDIV */ + .mult = 40, /* MULT */ + .src = 0, /* SOURCE */ + .initialize = true, /* Initialize */ + .stopmode = false, /* */ + .locked = false, /* LK */ + }, + .rtc = + { + .initialize = true, /* Initialize */ + .clkin = 0 /* RTC_CLKIN */ + }, + .clockout = + { + .source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */ + .initialize = true, /* Initialize */ + }, + .clockmode = + { + .rccr = /* RCCR - Run Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .vccr = /* VCCR - VLPR Clock Control Register */ + { + .src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */ + .divslow = 4, /* DIVSLOW, range 1..16 */ + .divbus = 1, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + .hccr = + { + .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */ + .divslow = 3, /* DIVSLOW, range 1..16 */ + .divbus = 2, /* DIVBUS, range 1..16 */ + .divcore = 2 /* DIVCORE, range 1..16 */ + }, + + /* .altclk */ + + .initialize = true, /* Initialize */ + }, + }, + .sim = + { + .clockout = /* Clock Out configuration. */ + { + .source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */ + .divider = 1, /* CLKOUTDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = false, /* CLKOUTEN */ + }, + .lpoclk = /* Low Power Clock configuration. */ + { + .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */ + .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */ + .initialize = true, /* Initialize */ + .lpo32k = true, /* LPO32KCLKEN */ + .lpo1k = true, /* LPO1KCLKEN */ + }, + .tclk = /* TCLK CLOCK configuration. */ + { + .tclkfreq[0] = 0, /* TCLK0 */ + .tclkfreq[1] = 0, /* TCLK1 */ + .tclkfreq[2] = 0, /* TCLK2 */ + .initialize = true, /* Initialize */ + }, + .platgate = /* Platform Gate Clock configuration. */ + { + .initialize = true, /* Initialize */ + .mscm = true, /* CGCMSCM */ + .mpu = true, /* CGCMPU */ + .dma = true, /* CGCDMA */ + .erm = true, /* CGCERM */ + .eim = true, /* CGCEIM */ + }, + .traceclk = /* Debug trace Clock Configuration. */ + { + .source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */ + .divider = 1, /* TRACEDIV, range 1..8 */ + .initialize = true, /* Initialize */ + .enable = true, /* TRACEDIVEN */ + .fraction = false, /* TRACEFRAC */ + }, +#ifdef CONFIG_S32K1XX_HAVE_QSPI + .qspirefclk = /* Quad Spi Internal Reference Clock Gating. */ + { + .refclk = false, /* Qspi reference clock gating */ + }, +#endif + }, + .pcc = + { + .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */ + .pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */ + }, + .pmc = + { + .lpoclk = /* Low Power Clock configuration. */ + { + .trim = 0, /* Trimming value for LPO */ + .initialize = true, /* Initialize */ + .enable = true, /* Enable/disable LPO */ + }, + } +}; diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_periphclocks.c new file mode 100644 index 00000000000..f0dbf9483c0 --- /dev/null +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_periphclocks.c @@ -0,0 +1,178 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k148evb/src/s32k1xx_periphclks.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Most of the settings within this file derives from NXP sample code for + * the S32K1XX MCUs. That sample code has this licensing information: + * + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "s32k1xx_periphclocks.h" +#include "s32k148evb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K1XX board must provide the following initialized structure. + * This is needed to establish the initial peripheral clocking. + */ + +const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = +{ + { + .clkname = ADC0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = ADC1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPTMR0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = LPUART2_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = ENET0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_FIRC, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = RTC0_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = FTM1_CLK, + .clkgate = true, + .clksrc = CLK_SRC_SIRC, + }, + { + .clkname = PORTA_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTB_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTC_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTD_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + }, + { + .clkname = PORTE_CLK, + .clkgate = true, + .clksrc = CLK_SRC_OFF, + .frac = MULTIPLY_BY_ONE, + .divider = 1, + } +}; diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_userleds.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_userleds.c new file mode 100644 index 00000000000..b0fdb3dabcc --- /dev/null +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_userleds.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/s32k1xx/s32k148evb/src/s32k1xx_userleds.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "s32k1xx_pin.h" +#include "s32k148evb.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k1xx_pinconfig(GPIO_LED_R); + s32k1xx_pinconfig(GPIO_LED_G); + s32k1xx_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED_R) + { + ledcfg = GPIO_LED_R; + } + else if (led == BOARD_LED_G) + { + ledcfg = GPIO_LED_G; + } + else if (led == BOARD_LED_B) + { + ledcfg = GPIO_LED_B; + } + else + { + return; + } + + s32k1xx_gpiowrite(ledcfg, ledon); /* High illuminates */ +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + s32k1xx_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) != 0); + s32k1xx_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/drivers/spi/spi_bitbang.c b/drivers/spi/spi_bitbang.c index e9314baa47a..646c6db4ce5 100644 --- a/drivers/spi/spi_bitbang.c +++ b/drivers/spi/spi_bitbang.c @@ -32,6 +32,7 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ + /**************************************************************************** * Included Files ****************************************************************************/ @@ -46,11 +47,14 @@ #include #include +#include + #ifdef CONFIG_SPI_BITBANG /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* This file holds the static, device-independ portion of the generica SPI- * bit-bang driver. The full driver consists of 5 files: * @@ -78,7 +82,6 @@ * information. */ - /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -136,7 +139,7 @@ static const struct spi_ops_s g_spiops = spi_sndblock, /* sndblock */ spi_recvblock, /* recvblock */ #endif - 0 /* registercallback */ + 0 /* registercallback */ }; /**************************************************************************** @@ -223,7 +226,8 @@ static void spi_select(FAR struct spi_dev_s *dev, uint32_t devid, * ****************************************************************************/ -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency) { FAR struct spi_bitbang_s *priv = (FAR struct spi_bitbang_s *)dev; uint32_t actual; @@ -365,14 +369,14 @@ static void spi_exchange(FAR struct spi_dev_s *dev, #ifdef CONFIG_SPI_BITBANG_VARWIDTH if (priv->nbits > 8) - { + { #ifdef CONFIG_ENDIAN_BIG - dataout <<= 8; - dataout |= *src++; + dataout <<= 8; + dataout |= *src++; #else - dataout |= (uint16_t)(*src++) << 8; + dataout |= (uint16_t)(*src++) << 8; #endif - } + } #endif } @@ -414,7 +418,8 @@ static void spi_exchange(FAR struct spi_dev_s *dev, * nwords - the length of data to send from the buffer in number of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's * * Returned Value: * None @@ -422,7 +427,8 @@ static void spi_exchange(FAR struct spi_dev_s *dev, ****************************************************************************/ #ifndef CONFIG_SPI_EXCHANGE -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, + size_t nwords) { /* spi_exchange can do this. */ @@ -440,9 +446,10 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size * dev - Device-specific state data * buffer - A pointer to the buffer in which to receive data * nwords - the length of data that can be received in the buffer in number - * of words. The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's * * Returned Value: * None @@ -450,7 +457,8 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size ****************************************************************************/ #ifndef CONFIG_SPI_EXCHANGE -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords) { /* spi_exchange can do this. */ @@ -502,7 +510,7 @@ static int spi_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) { FAR struct spi_bitbang_s *priv = (FAR struct spi_bitbang_s *)dev; - DEBUGASSERTcmddata(priv && priv->low && priv->low->status); + DEBUGASSERT(priv && priv->low && priv->low->status); return priv->low->cmddata(priv, devid, cmd); } From 3b311ab89562e1d33d5f45e5315bf54d23d5b427 Mon Sep 17 00:00:00 2001 From: liuhaitao Date: Fri, 7 Feb 2020 09:58:24 +0800 Subject: [PATCH 35/35] tools/testbuild.sh: use function to call make and fail handle in common Change-Id: I50cbc335254be0f2388b4bb6af8a874e74ba98c2 Signed-off-by: liuhaitao --- tools/testbuild.sh | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/tools/testbuild.sh b/tools/testbuild.sh index 79561fa83a1..16ccd703a61 100755 --- a/tools/testbuild.sh +++ b/tools/testbuild.sh @@ -149,12 +149,19 @@ blacklist=`grep "^-" $testfile` cd $nuttx || { echo "ERROR: failed to CD to $nuttx"; exit 1; } +function makefunc { + ${MAKE} $@ + if [ $? != 0 ]; then + fail=$? + fi +} + # Clean up after the last build function distclean { if [ -f .config ]; then echo " Cleaning..." - ${MAKE} ${JOPTION} ${MAKE_FLAGS} distclean 1>/dev/null || fail=$? + makefunc ${JOPTION} ${MAKE_FLAGS} distclean 1>/dev/null fi } @@ -183,7 +190,7 @@ function configure { echo "$toolchain=y" >> $nuttx/.config echo " Refreshing..." - ${MAKE} ${MAKE_FLAGS} olddefconfig 1>/dev/null || fail=$? + makefunc ${MAKE_FLAGS} olddefconfig 1>/dev/null fi } @@ -192,7 +199,7 @@ function configure { function build { echo " Building NuttX..." echo "------------------------------------------------------------------------------------" - ${MAKE} ${JOPTION} ${MAKE_FLAGS} 1>/dev/null || fail=$? + makefunc ${JOPTION} ${MAKE_FLAGS} 1>/dev/null } # Coordinate the steps for the next build test