From 1d97d643e08ef741f4b941f41af5525ea1d96918 Mon Sep 17 00:00:00 2001 From: ssszwic <114381825+ssszwic@users.noreply.github.com> Date: Wed, 3 Apr 2024 18:32:23 +0800 Subject: [PATCH] ICache: initializing p1_vaddr and p2_vaddr in prefetch pipeline (#2843) --- src/main/scala/xiangshan/frontend/icache/IPrefetch.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala b/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala index 33180ab978..180dc710dd 100644 --- a/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala +++ b/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala @@ -366,7 +366,7 @@ class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule */ val p1_valid = generatePipeControl(lastFire = p0_fire, thisFire = p1_fire || p1_discard, thisFlush = false.B, lastFlush = false.B) - val p1_vaddr = RegEnable(p0_vaddr, p0_fire) + val p1_vaddr = RegEnable(p0_vaddr, 0.U(VAddrBits.W), p0_fire) val p1_req_cancel = Wire(Bool()) /** 1. Receive resp from ITLB (no blocked) */ @@ -408,7 +408,7 @@ class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule val p2_valid = generatePipeControl(lastFire = p1_fire, thisFire = p2_fire || p2_discard, thisFlush = false.B, lastFlush = false.B) val p2_paddr = RegEnable(p1_paddr, p1_fire) - val p2_vaddr = RegEnable(p1_vaddr, p1_fire) + val p2_vaddr = RegEnable(p1_vaddr, 0.U(VAddrBits.W), p1_fire) val p2_req_cancel = Wire(Bool()) val p2_vidx = get_idx(p2_vaddr)