diff --git a/.shippable.yml b/.shippable.yml index 0bc41343977..1a57e03374b 100644 --- a/.shippable.yml +++ b/.shippable.yml @@ -56,6 +56,7 @@ build: - _make PLATFORM=mediatek-mt8173 CFG_ARM64_core=y - _make PLATFORM=imx-mx6ulevk ARCH=arm CFG_PAGEABLE_ADDR=0 CFG_NS_ENTRY_ADDR=0x80800000 CFG_DT_ADDR=0x83000000 CFG_DT=y DEBUG=y CFG_TEE_CORE_LOG_LEVEL=4 - _make PLATFORM=imx-mx6ullevk ARCH=arm CFG_PAGEABLE_ADDR=0 CFG_NS_ENTRY_ADDR=0x80800000 CFG_DT=y DEBUG=y CFG_TEE_CORE_LOG_LEVEL=4 + - _make PLATFORM=imx-mx6sxsabreauto - _make PLATFORM=imx-mx6qsabrelite - _make PLATFORM=imx-mx6qsabresd - _make PLATFORM=imx-mx6dlsabresd diff --git a/MAINTAINERS.md b/MAINTAINERS.md index 46865525612..017b224d4f8 100644 --- a/MAINTAINERS.md +++ b/MAINTAINERS.md @@ -18,6 +18,7 @@ for these platforms. | FSL i.MX6 Quad SABRE SD Board |`Yan Yan `,`Feng Yu `| | FSL i.MX6 UltraLite EVK Board |`Peng Fan `| | NXP i.MX6 ULL EVK Board |`Peng Fan `| +| NXP i.MX6 SX Sabreauto Board |`Peng Fan `| | NXP i.MX7 Dual SabreSD Board |`Peng Fan `| | ARM Foundation FVP |`Linaro `| | HiKey Board (HiSilicon Kirin 620) |`Linaro `| diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk index 40894f187df..312e7c8654e 100644 --- a/core/arch/arm/plat-imx/conf.mk +++ b/core/arch/arm/plat-imx/conf.mk @@ -4,6 +4,7 @@ PLATFORM_FLAVOR ?= mx6ulevk mx6ul-flavorlist = mx6ulevk mx6ull-flavorlist = mx6ullevk mx6q-flavorlist = mx6qsabrelite mx6qsabresd +mx6sx-flavorlist = mx6sxsabreauto mx6d-flavorlist = mx6dl-flavorlist = mx6dlsabresd mx6s-flavorlist = @@ -21,6 +22,10 @@ else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist))) $(call force,CFG_MX6DL,y) else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist))) $(call force,CFG_MX6S,y) +else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist))) +$(call force,CFG_MX6,y) +$(call force,CFG_MX6SX,y) +$(call force,CFG_IMX_UART,y) else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7-flavorlist))) $(call force,CFG_MX7,y) else @@ -56,7 +61,8 @@ endif # i.MX6 Solo/DualLite/Dual/Quad specific config -ifeq ($(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y) +ifeq ($(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \ + $(CFG_MX6SX)), y) include core/arch/arm/cpu/cortex-a9.mk $(call force,CFG_MX6,y) @@ -76,6 +82,17 @@ $(call force,CFG_SECURE_TIME_SOURCE_REE,y) CFG_BOOT_SECONDARY_REQUEST ?= y endif +ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto)) +CFG_PAGEABLE_ADDR ?= 0 +CFG_DDR_SIZE ?= 0x80000000 +CFG_DT ?= y +CFG_NS_ENTRY_ADDR ?= 0x80800000 +CFG_PSCI_ARM32 ?= y +CFG_BOOT_SYNC_CPU = n +CFG_BOOT_SECONDARY_REQUEST = n +CFG_TEE_CORE_NB_CORE ?= 1 +endif + ifeq ($(filter y, $(CFG_PSCI_ARM32)), y) CFG_HWSUPP_MEM_PERM_WXN = n CFG_IMX_WDOG ?= y diff --git a/core/arch/arm/plat-imx/config/config_imx6sx.h b/core/arch/arm/plat-imx/config/config_imx6sx.h new file mode 100644 index 00000000000..e10aa939ce1 --- /dev/null +++ b/core/arch/arm/plat-imx/config/config_imx6sx.h @@ -0,0 +1,154 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * Peng Fan + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CONFIG_IMX6SX_H +#define __CONFIG_IMX6SX_H + +#ifndef CFG_UART_BASE +#define CFG_UART_BASE (UART1_BASE) +#endif + +#ifndef CFG_DDR_SIZE +#error "CFG_DDR_SIZE not defined" +#endif + +#define DRAM0_SIZE CFG_DDR_SIZE + +/* Location of trusted dram */ +#define TZDRAM_BASE (DRAM0_BASE - 32 * 1024 * 1024 + CFG_DDR_SIZE) +#define TZDRAM_SIZE (30 * 1024 * 1024) + +/* Full GlobalPlatform test suite requires CFG_SHMEM_SIZE to be at least 2MB */ +#define CFG_SHMEM_START (TZDRAM_BASE + TZDRAM_SIZE) +#define CFG_SHMEM_SIZE 0x200000 + +#define CFG_TEE_RAM_VA_SIZE (1024 * 1024) + +/* + * Everything is in TZDRAM. + * +------------------+ + * | | TEE_RAM | + * + TZDRAM +---------+ + * | | TA_RAM | + * +--------+---------+ + */ +#define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE +#define CFG_TEE_RAM_START TZDRAM_BASE +#define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \ + CORE_MMU_DEVICE_SIZE) +#define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \ + CORE_MMU_DEVICE_SIZE) + +#ifndef CFG_TEE_LOAD_ADDR +#define CFG_TEE_LOAD_ADDR CFG_TEE_RAM_START +#endif + +#define CONSOLE_UART_BASE (CFG_UART_BASE) + +/* + * PL310 TAG RAM Control Register + * + * bit[10:8]:1 - 2 cycle of write accesses latency + * bit[6:4]:3 - 4 cycle of read accesses latency + * bit[2:0]:2 - 3 cycle of setup latency + */ +#ifndef PL310_TAG_RAM_CTRL_INIT +#define PL310_TAG_RAM_CTRL_INIT 0x00000132 +#endif + +/* + * PL310 DATA RAM Control Register + * + * bit[10:8]:1 - 2 cycle of write accesses latency + * bit[6:4]:3 - 4 cycle of read accesses latency + * bit[2:0]:2 - 3 cycle of setup latency + */ +#ifndef PL310_DATA_RAM_CTRL_INIT +#define PL310_DATA_RAM_CTRL_INIT 0x00000232 +#endif + +/* + * PL310 Auxiliary Control Register + * + * I/Dcache prefetch enabled (bit29:28=2b11) + * NS can access interrupts (bit27=1) + * NS can lockown cache lines (bit26=1) + * Pseudo-random replacement policy (bit25=0) + * Force write allocated (default) + * Shared attribute internally ignored (bit22=1, bit13=0) + * Parity disabled (bit21=0) + * Event monitor disabled (bit20=0) + * Platform fmavor specific way config (dual / quad): + * - 16kb way size (bit19:17=3b001) + * - 16-way associciativity (bit16=1) + * Store buffer device limitation enabled (bit11=1) + * Cacheable accesses have high prio (bit10=0) + * Full Line Zero (FLZ) disabled (bit0=0) + */ +#define PL310_AUX_CTRL_INIT 0x3C430800 + +/* + * PL310 Prefetch Control Register + * + * Double linefill disabled (bit30=0) + * I/D prefetch enabled (bit29:28=2b11) + * Prefetch drop enabled (bit24=1) + * Incr double linefill disable (bit23=0) + * Prefetch offset = 7 (bit4:0) + */ +#define PL310_PREFETCH_CTRL_INIT 0x31000007 + +/* + * PL310 Power Register + * + * Dynamic clock gating enabled + * Standby mode enabled + */ +#define PL310_POWER_CTRL_INIT 0x00000003 + +/* + * SCU Invalidate Register + * + * Invalidate all registers + */ +#define SCU_INV_CTRL_INIT 0xFFFFFFFF + +/* + * SCU Access Register + * - both secure CPU access SCU + */ +#define SCU_SAC_CTRL_INIT 0x0000000F + +/* + * SCU NonSecure Access Register + * - both nonsec cpu access SCU, private and global timer + */ +#define SCU_NSAC_CTRL_INIT 0x00000FFF + +#endif diff --git a/core/arch/arm/plat-imx/imx-regs.h b/core/arch/arm/plat-imx/imx-regs.h index ac88e9333f4..a935160a297 100644 --- a/core/arch/arm/plat-imx/imx-regs.h +++ b/core/arch/arm/plat-imx/imx-regs.h @@ -132,7 +132,7 @@ #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET_6UL (27) #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK_6UL GENMASK_32(31, 27) -#if defined(CFG_MX6UL) || defined(CFG_MX6ULL) +#if defined(CFG_MX6UL) || defined(CFG_MX6ULL) || defined(CFG_MX6SX) #define DRAM0_BASE 0x80000000 #else #define DRAM0_BASE 0x10000000 diff --git a/core/arch/arm/plat-imx/platform_config.h b/core/arch/arm/plat-imx/platform_config.h index 28c5ff8f475..e0fdf7cd036 100644 --- a/core/arch/arm/plat-imx/platform_config.h +++ b/core/arch/arm/plat-imx/platform_config.h @@ -38,6 +38,9 @@ #if defined(CFG_MX7) #include +#elif defined(CFG_MX6SX) +#include + /* For i.MX 6UltraLite and 6ULL EVK board */ #elif defined(CFG_MX6UL) || defined(CFG_MX6ULL) #include diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk index b0666a7d0e6..16465ae7ef0 100644 --- a/core/arch/arm/plat-imx/sub.mk +++ b/core/arch/arm/plat-imx/sub.mk @@ -12,7 +12,8 @@ endif cflags-pm/psci.c-y += -Wno-suggest-attribute=noreturn -ifneq (,$(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S))) +ifneq (,$(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \ + $(CFG_MX6SX))) srcs-y += a9_plat_init.S imx6.c endif