Is CAS / MemoryOrdering part of the sleigh design specification?

[Naville]

In Ghidra 11.2.1,
AArch64 atomic instruction ldar instruction gets lifted as just a load, as shown below:

ldar       x0,[sp]=>local_100
(register, 0x4000, 8) = LOAD (const, 0x1b1, 8), (register, 0x8, 8)

What am I doing wrong here?