Verilog Change Log

[0.0.6] 2021-03-16

Added Compile All.
Generated files are moved to ./build
Minor ts types improvements

[0.0.6] 2019-06-25

Remove redundant code.

[0.0.5] 2019-06-25

Fixed the Bug when Running Code in Windows.

[0.0.4] 2017-12-31

Add Verilog Snippets.

[0.0.3] 2017-12-27

Change the compile filename.

[0.0.2] 2017-12-27

Fixed the Description.

[0.0.1] 2017-12-27

Create the tmLanguage.