-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathGPIO.s
501 lines (501 loc) · 9.43 KB
/
GPIO.s
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
.cpu arm7tdmi
.arch armv4t
.fpu softvfp
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 1
.eabi_attribute 30, 6
.eabi_attribute 34, 0
.eabi_attribute 18, 4
.file "GPIO.c"
.text
.data
.align 2
.type Array, %object
.size Array, 32
Array:
.word 1073872896
.word 1073873920
.word 1073874944
.word 1073875968
.word 1073876992
.word 1073878016
.word 1073879040
.word 1073880064
.text
.align 2
.global GPIO_PinInit
.syntax unified
.arm
.type GPIO_PinInit, %function
GPIO_PinInit:
@ Function supports interworking.
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 1, uses_anonymous_args = 0
@ link register save eliminated.
str fp, [sp, #-4]!
add fp, sp, #0
sub sp, sp, #20
str r0, [fp, #-16]
mov r3, #1
strb r3, [fp, #-5]
ldr r3, [fp, #-16]
cmp r3, #0
beq .L2
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
cmp r3, #7
bhi .L3
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
cmp r3, #15
bhi .L3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [r3]
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
lsl r3, r3, #1
mov r1, #3
lsl r3, r1, r3
mvn r3, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r0, r3
ldr r3, .L10
ldr r3, [r3, r0, lsl #2]
and r2, r2, r1
str r2, [r3]
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [r3]
ldr r3, [fp, #-16]
ldrb r3, [r3, #2] @ zero_extendqisi2
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
lsl r3, r3, #1
lsl r3, r1, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r0, r3
ldr r3, .L10
ldr r3, [r3, r0, lsl #2]
orr r2, r2, r1
str r2, [r3]
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [r3, #12]
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
lsl r3, r3, #1
mov r1, #3
lsl r3, r1, r3
mvn r3, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r0, r3
ldr r3, .L10
ldr r3, [r3, r0, lsl #2]
and r2, r2, r1
str r2, [r3, #12]
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [r3, #12]
ldr r3, [fp, #-16]
ldrb r3, [r3, #5] @ zero_extendqisi2
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
lsl r3, r3, #1
lsl r3, r1, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r0, r3
ldr r3, .L10
ldr r3, [r3, r0, lsl #2]
orr r2, r2, r1
str r2, [r3, #12]
ldr r3, [fp, #-16]
ldrb r3, [r3, #2] @ zero_extendqisi2
cmp r3, #1
beq .L4
ldr r3, [fp, #-16]
ldrb r3, [r3, #2] @ zero_extendqisi2
cmp r3, #2
bne .L9
.L4:
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [r3, #4]
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
mov r1, r3
mov r3, #1
lsl r3, r3, r1
mvn r3, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r0, r3
ldr r3, .L10
ldr r3, [r3, r0, lsl #2]
and r2, r2, r1
str r2, [r3, #4]
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [r3, #4]
ldr r3, [fp, #-16]
ldrb r3, [r3, #3] @ zero_extendqisi2
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
lsl r3, r1, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r0, r3
ldr r3, .L10
ldr r3, [r3, r0, lsl #2]
orr r2, r2, r1
str r2, [r3, #4]
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [r3, #8]
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
lsl r3, r3, #1
mov r1, #3
lsl r3, r1, r3
mvn r3, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r0, r3
ldr r3, .L10
ldr r3, [r3, r0, lsl #2]
and r2, r2, r1
str r2, [r3, #8]
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [r3, #8]
ldr r3, [fp, #-16]
ldrb r3, [r3, #4] @ zero_extendqisi2
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
lsl r3, r3, #1
lsl r3, r1, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r0, r3
ldr r3, .L10
ldr r3, [r3, r0, lsl #2]
orr r2, r2, r1
str r2, [r3, #8]
ldr r3, [fp, #-16]
ldrb r3, [r3, #2] @ zero_extendqisi2
cmp r3, #2
bne .L9
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [fp, #-16]
ldrb r2, [r2, #1] @ zero_extendqisi2
lsr r2, r2, #3
and r0, r2, #255
mov r2, r0
add r2, r2, #8
ldr r2, [r3, r2, lsl #2]
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
and r3, r3, #7
lsl r3, r3, #2
mov r1, #15
lsl r3, r1, r3
mvn r3, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov ip, r3
ldr r3, .L10
ldr r3, [r3, ip, lsl #2]
and r1, r1, r2
add r2, r0, #8
str r1, [r3, r2, lsl #2]
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov r2, r3
ldr r3, .L10
ldr r3, [r3, r2, lsl #2]
ldr r2, [fp, #-16]
ldrb r2, [r2, #1] @ zero_extendqisi2
lsr r2, r2, #3
and r0, r2, #255
mov r2, r0
add r2, r2, #8
ldr r2, [r3, r2, lsl #2]
ldr r3, [fp, #-16]
ldrb r3, [r3, #1] @ zero_extendqisi2
and r3, r3, #7
lsl r3, r3, #2
mov r1, #15
lsl r3, r1, r3
mov r1, r3
ldr r3, [fp, #-16]
ldrb r3, [r3] @ zero_extendqisi2
mov ip, r3
ldr r3, .L10
ldr r3, [r3, ip, lsl #2]
orr r1, r2, r1
add r2, r0, #8
str r1, [r3, r2, lsl #2]
b .L9
.L3:
mov r3, #2
strb r3, [fp, #-5]
b .L7
.L2:
mov r3, #3
strb r3, [fp, #-5]
b .L7
.L9:
nop
.L7:
ldrb r3, [fp, #-5] @ zero_extendqisi2
mov r0, r3
add sp, fp, #0
@ sp needed
ldr fp, [sp], #4
bx lr
.L11:
.align 2
.L10:
.word Array
.size GPIO_PinInit, .-GPIO_PinInit
.align 2
.global GPIO_SetPinValue
.syntax unified
.arm
.type GPIO_SetPinValue, %function
GPIO_SetPinValue:
@ Function supports interworking.
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 1, uses_anonymous_args = 0
@ link register save eliminated.
str fp, [sp, #-4]!
add fp, sp, #0
sub sp, sp, #20
mov r3, r0
strb r3, [fp, #-13]
mov r3, r1
strb r3, [fp, #-14]
mov r3, r2
strb r3, [fp, #-15]
mov r3, #1
strb r3, [fp, #-5]
ldrb r3, [fp, #-13] @ zero_extendqisi2
cmp r3, #7
bhi .L13
ldrb r3, [fp, #-14] @ zero_extendqisi2
cmp r3, #15
bhi .L13
ldrb r3, [fp, #-15] @ zero_extendqisi2
cmp r3, #0
beq .L14
cmp r3, #1
beq .L15
b .L20
.L14:
ldrb r3, [fp, #-13] @ zero_extendqisi2
ldr r2, .L21
ldr r3, [r2, r3, lsl #2]
ldr r2, [r3, #20]
ldrb r3, [fp, #-14] @ zero_extendqisi2
mov r1, #1
lsl r3, r1, r3
mvn r3, r3
mov r0, r3
ldrb r3, [fp, #-13] @ zero_extendqisi2
ldr r1, .L21
ldr r3, [r1, r3, lsl #2]
and r2, r2, r0
str r2, [r3, #20]
b .L17
.L15:
ldrb r3, [fp, #-13] @ zero_extendqisi2
ldr r2, .L21
ldr r3, [r2, r3, lsl #2]
ldr r2, [r3, #20]
ldrb r3, [fp, #-14] @ zero_extendqisi2
mov r1, #1
lsl r3, r1, r3
mov r0, r3
ldrb r3, [fp, #-13] @ zero_extendqisi2
ldr r1, .L21
ldr r3, [r1, r3, lsl #2]
orr r2, r2, r0
str r2, [r3, #20]
b .L17
.L20:
mov r3, #2
strb r3, [fp, #-5]
b .L18
.L17:
b .L18
.L13:
mov r3, #2
strb r3, [fp, #-5]
.L18:
ldrb r3, [fp, #-5] @ zero_extendqisi2
mov r0, r3
add sp, fp, #0
@ sp needed
ldr fp, [sp], #4
bx lr
.L22:
.align 2
.L21:
.word Array
.size GPIO_SetPinValue, .-GPIO_SetPinValue
.align 2
.global GPIO_PinToggle
.syntax unified
.arm
.type GPIO_PinToggle, %function
GPIO_PinToggle:
@ Function supports interworking.
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 1, uses_anonymous_args = 0
@ link register save eliminated.
str fp, [sp, #-4]!
add fp, sp, #0
sub sp, sp, #20
mov r3, r0
mov r2, r1
strb r3, [fp, #-13]
mov r3, r2
strb r3, [fp, #-14]
mov r3, #1
strb r3, [fp, #-5]
ldrb r3, [fp, #-13] @ zero_extendqisi2
cmp r3, #7
bhi .L24
ldrb r3, [fp, #-14] @ zero_extendqisi2
cmp r3, #15
bhi .L24
ldrb r3, [fp, #-13] @ zero_extendqisi2
ldr r2, .L27
ldr r3, [r2, r3, lsl #2]
ldr r2, [r3, #20]
ldrb r3, [fp, #-14] @ zero_extendqisi2
mov r1, #1
lsl r3, r1, r3
mov r0, r3
ldrb r3, [fp, #-13] @ zero_extendqisi2
ldr r1, .L27
ldr r3, [r1, r3, lsl #2]
eor r2, r2, r0
str r2, [r3, #20]
b .L25
.L24:
mov r3, #2
strb r3, [fp, #-5]
.L25:
ldrb r3, [fp, #-5] @ zero_extendqisi2
mov r0, r3
add sp, fp, #0
@ sp needed
ldr fp, [sp], #4
bx lr
.L28:
.align 2
.L27:
.word Array
.size GPIO_PinToggle, .-GPIO_PinToggle
.align 2
.global GPIO_READ_PIN
.syntax unified
.arm
.type GPIO_READ_PIN, %function
GPIO_READ_PIN:
@ Function supports interworking.
@ args = 0, pretend = 0, frame = 16
@ frame_needed = 1, uses_anonymous_args = 0
@ link register save eliminated.
str fp, [sp, #-4]!
add fp, sp, #0
sub sp, sp, #20
mov r3, r0
str r2, [fp, #-20]
strb r3, [fp, #-13]
mov r3, r1
strb r3, [fp, #-14]
mov r3, #1
strb r3, [fp, #-5]
ldrb r3, [fp, #-13] @ zero_extendqisi2
cmp r3, #7
bhi .L30
ldrb r3, [fp, #-14] @ zero_extendqisi2
cmp r3, #15
bhi .L30
ldrb r3, [fp, #-13] @ zero_extendqisi2
ldr r2, .L33
ldr r3, [r2, r3, lsl #2]
ldr r2, [r3, #16]
ldrb r3, [fp, #-14] @ zero_extendqisi2
lsr r3, r2, r3
and r2, r3, #1
ldr r3, [fp, #-20]
str r2, [r3]
b .L31
.L30:
mov r3, #2
strb r3, [fp, #-5]
.L31:
ldrb r3, [fp, #-5] @ zero_extendqisi2
mov r0, r3
add sp, fp, #0
@ sp needed
ldr fp, [sp], #4
bx lr
.L34:
.align 2
.L33:
.word Array
.size GPIO_READ_PIN, .-GPIO_READ_PIN
.ident "GCC: (Arm GNU Toolchain 12.3.Rel1 (Build arm-12.35)) 12.3.1 20230626"