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iomap.txt
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iomap.txt
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C64 $0000000 6510/45GS10 CPU port DDR
C64 $0000000 CPU:PORTDDR 6510/45GS10 CPU port DDR
C64 $0000001 6510/45GS10 CPU port data
C64 $0000001 CPU:PORT 6510/45GS10 CPU port data
C64 $0000002-$000FFFF - 64KB RAM
C65 $0010000-$001FFFF - 64KB RAM
C65 $0020000-$003FFFF - 128KB ROM (can be used as RAM in M65 mode)
C65 $002A000-$002BFFF - 8KB C64 BASIC ROM
C65 $002D000-$002DFFF - 4KB C64 CHARACTER ROM
C65 $002E000-$002FFFF - 8KB C64 KERNAL ROM
C65 $0030000-$0031FFF - 16KB C65 DOS ROM
C65 $0032000-$0035FFF - 8KB C65 BASIC ROM
C65 $0038000-$003BFFF - 8KB C65 BASIC GRAPHICS ROM
C65 $003C000-$003CFFF - 4KB C65 KERNAL/INTERFACE ROM
C65 $003E000-$003FFFF - 8KB C65 KERNAL ROM
GS $00 ETHCOMMAND:STOPTX Immediately stop transmitting the current ethernet frame. Will cause a partially sent frame to be received, most likely resulting in the loss of that frame.
GS $01 ETHCOMMAND:STARTTX Transmit packet
GS $4000000 - $7FFFFFF Slow Device memory (64MB)
GS $4000000 - $7FFFFFF SUMMARY:SLOWDEV Slow Device memory (64MB)
GS $7010000.4-0 - Read /EXROM & /GAME signal probe count (MEGA65 R1 PCB only)
GS $7010000.5 - Force assertion of /RESET on cartridge port
GS $7010000.5 - Read cartridge force reset (1=reset)
GS $7010000.6 - Read cartridge /GAME flag
GS $7010000.7 - Read cartridge /EXROM flag
GS $7010001.0 - Invert joystick line polarity for joystick expander cartridge
GS $7010001.4 - Force disabling of joystick expander cartridge
GS $7010001.5 - Joystick read toggle flag DEBUG
GS $7010001.6 - 1=force joystick expansion mode.
GS $7010001.6 - Force enabling of joystick expander cartridge
GS $7010001.7 - Expansion port mode: 1=normal mode, 0=joystick expansion mode
GS $7010002 - Counter of /IRQ triggers from cartridge
GS $7010003 - Counter of /NMI triggers from cartridge
GS $7010004 - Counter of /DMA triggers from cartridge
GS $7010005 - Counter of /GAME triggers from cartridge
GS $7010006 - Counter of /EXROM triggers from cartridge
GS $7010007 - Directly read cartridge port data lines.
GS $7010008 - Directly read lower 8 cartridge address data lines.
GS $7010009 - Directly read upper 8 cartridge address data lines.
GS $7FEFFFF.0 Enable/disable SFX cartridge emulation
GS $8000000 - $FEFFFFF Slow Device memory (127MB)
GS $8000000 - $FEFFFFF SUMMARY:SLOWDEV Slow Device memory (127MB)
GS $BFFFFF0 - $BFFFFFF HYRAM!DEBUG Special HyperRAM setting registers used for debugging
C64 $D000 VIC-II:S0X@SNX sprite N horizontal position
C64 $D001 VIC-II:S0Y@SNY sprite N vertical position
C64 $D002 VIC-II:S1X @SNX
C64 $D003 VIC-II:S1Y @SNY
C64 $D004 VIC-II:S2X @SNX
C64 $D005 VIC-II:S2Y @SNY
C64 $D006 VIC-II:S3X @SNX
C64 $D007 VIC-II:S3Y @SNY
C64 $D008 VIC-II:S4X @SNX
C64 $D009 VIC-II:S4Y @SNY
C64 $D00A VIC-II:S5X @SNX
C64 $D00B VIC-II:S5Y @SNY
C64 $D00C VIC-II:S6X @SNX
C64 $D00D VIC-II:S6Y @SNY
C64 $D00E VIC-II:S7X @SNX
C64 $D00F VIC-II:S7Y @SNY
C64 $D010 VIC-II:SXMSB sprite horizontal position MSBs
C64 $D011.2-0 VIC-II:YSCL 24/25 vertical smooth scroll
C64 $D011.3 VIC-II:RSEL 24/25 row select
C64 $D011.4 VIC-II:BLNK Enable display: 0 = blank the display, 1 = show the display
C64 $D011.5 VIC-II:BMM bitmap mode
C64 $D011.6 VIC-II:ECM extended background mode
C64 $D011.7 VIC-II:RC8 raster compare bit 8
C64 $D011 VIC-II control register
C64 $D012 VIC-II:RC raster compare bits 0 to 7
C64 $D013 VIC-II:LPX Coarse horizontal beam position (was lightpen X)
C64 $D014 VIC-II:LPY Coarse vertical beam position (was lightpen Y)
C64 $D015 VIC-II:SE sprite enable bits
C64 $D016.2-0 VIC-II:XSCL horizontal smooth scroll
C64 $D016.3 VIC-II:CSEL 38/40 column select
C64 $D016.4 VIC-II:MCM Multi-colour mode
C64 $D016.5 VIC-II:RST Disables video output on MAX Machine(tm) VIC-II 6566. Ignored on normal C64s and the MEGA65
C64 $D016 VIC-II control register
C64 $D017 VIC-II:SEXY sprite vertical expansion enable bits
C64 $D018.3-1 VIC-II:CB character set address location ($\times$ 1KiB)
C64 $D018.7-4 VIC-II:VS screen address ($\times$ 1KiB)
C64 $D018 VIC-II RAM addresses
C64 $D019.0 VIC-II:RIRQ raster compare indicate or acknowledge
C64 $D019.1 VIC-II:ISBC sprite:bitmap collision indicate or acknowledge
C64 $D019.2 VIC-II:ISSC sprite:sprite collision indicate or acknowledge
C64 $D019.3 VIC-II:ILP light pen indicate or acknowledge
C64 $D019 VIC-II IRQ control
C64 $D01A.0 VIC-II:MRIRQ mask raster IRQ
C64 $D01A.1 VIC-II:MISBC mask sprite:bitmap collision IRQ
C64 $D01A.2 VIC-II:MISSC mask sprite:sprite collision IRQ
C64 $D01A compatibility IRQ mask bits
C64 $D01B VIC-II:BSP sprite background priority bits
C64 $D01C VIC-II:SCM sprite multicolour enable bits
C64 $D01D VIC-II:SEXX sprite horizontal expansion enable bits
C64 $D01E sprite/sprite collissions
C64 $D01E VIC-II:SSC sprite/sprite collision indicate bits
C64 $D01F sprite/foreground collissions
C64 $D01F VIC-II:SBC sprite/foreground collision indicate bits
C64 $D020.3-0 VIC-II:BORDERCOL display border colour (16 colour)
C65 $D020.7-0 VIC-III:BORDERCOL display border colour (256 colour)
GS $D020.7-0 VIC-IV:BORDERCOL display border colour (256 colour)
C64 $D020 Border colour
C64 $D021.3-0 VIC-II:SCREENCOL screen colour (16 colour)
C65 $D021.7-0 VIC-III:SCREENCOL screen colour (256 colour)
GS $D021.7-0 VIC-IV:SCREENCOL screen colour (256 colour)
C64 $D021 Screen colour
C64 $D022.3-0 VIC-II:MC1 multi-colour 1 (16 colour)
C65 $D022.7-0 VIC-III:MC1 multi-colour 1 (256 colour)
GS $D022.7-0 VIC-IV:MC1 multi-colour 1 (256 colour)
C64 $D022 VIC-II multi-colour 1
C64 $D023.3-0 VIC-II:MC2 multi-colour 2 (16 colour)
C65 $D023.7-0 VIC-III:MC2 multi-colour 2 (256 colour)
GS $D023.7-0 VIC-IV:MC2 multi-colour 2 (256 colour)
C64 $D023 VIC-II multi-colour 2
C64 $D024.3-0 VIC-II:MC3 multi-colour 3 (16 colour)
C65 $D024.7-0 VIC-III:MC3 multi-colour 3 (256 colour)
GS $D024.7-0 VIC-IV:MC3 multi-colour 3 (256 colour)
C64 $D024 VIC-II multi-colour 3
C65 $D025 VIC-III:SPRMC0 Sprite multi-colour 0 (8-bit for selection of any palette colour)
C64 $D025 VIC-II:SPRMC0 Sprite multi-colour 0
GS $D025 VIC-IV:SPRMC0 Sprite multi-colour 0 (8-bit for selection of any palette colour)
C65 $D026 VIC-III:SPRMC1 Sprite multi-colour 1 (8-bit for selection of any palette colour)
C64 $D026 VIC-II:SPRMC1 Sprite multi-colour 1
GS $D026 VIC-IV:SPRMC1 Sprite multi-colour 1 (8-bit for selection of any palette colour)
C64 $D027 VIC-II:SPR0COL@SPRNCOL sprite N colour / 16-colour sprite transparency colour (lower nybl)
C64 $D028 VIC-II:SPR1COL @SPRNCOL
C64 $D029 VIC-II:SPR2COL @SPRNCOL
C64 $D02A VIC-II:SPR3COL @SPRNCOL
C64 $D02B VIC-II:SPR4COL @SPRNCOL
C64 $D02C VIC-II:SPR5COL @SPRNCOL
C64 $D02D VIC-II:SPR6COL @SPRNCOL
C64 $D02E VIC-II:SPR7COL @SPRNCOL
C65 $D02F VIC-III KEY register for unlocking extended registers.
C65 $D02F VIC-III:KEY Write $A5 then $96 to enable C65/VIC-III IO registers
GS $D02F VIC-IV:KEY Write $45 then $54 to map 45E100 ethernet controller buffers to $D000-$DFFF
GS $D02F VIC-IV:KEY Write $47 then $53 to enable C65GS/VIC-IV IO registers
C65 $D02F Write anything else to return to C64/VIC-II IO map
C64 $D030.0 VIC-II:C128!FAST 2MHz select (for C128 2MHz emulation)
C65 $D030.0 VIC-III:CRAM2K Map 2nd KB of colour RAM @ $DC00-$DFFF
C65 $D030.1 VIC-III:EXTSYNC Enable external video sync (genlock input)
C65 $D030.2 VIC-III:PAL Use PALETTE ROM (0) or RAM (1) entries for colours 0 - 15
C65 $D030.3 VIC-III:ROM8 Map C65 ROM @ $8000
C65 $D030.4 VIC-III:ROMA Map C65 ROM @ $A000
C65 $D030.5 VIC-III:ROMC Map C65 ROM @ $C000
C65 $D030.6 VIC-III:CROM9 Select between C64 and C65 charset (not implemented)
C65 $D030.7 VIC-III:ROME Map C65 ROM @ $E000
C64 $D030 SUMMARY: C128 2MHz emulation
C65 $D030 SUMMARY:VIC-III Control Register A
C65 $D031.0 VIC-III:INT Enable VIC-III interlaced mode
C65 $D031.1 VIC-III:MONO Enable VIC-III MONO composite video output (colour if disabled)
C65 $D031.2 VIC-III:H1280 Enable 1280 horizontal pixels (not implemented)
C65 $D031.3 VIC-III:V400 Enable 400 vertical pixels
C65 $D031.4 VIC-III:BPM Bit-Plane Mode
C65 $D031.5 VIC-III:ATTR Enable extended attributes and 8 bit colour entries
C65 $D031.6 VIC-III:FAST Enable C65 FAST mode (~3.5MHz)
C65 $D031.7 VIC-III:H640 Enable C64 640 horizontal pixels / 80 column mode
C65 $D031 SUMMARY:VIC-III Control Register B
C65 $D032 - Bitplane enable bits
C65 $D033-$D03A - VIC-III Bitplane addresses
C65 $D033.1-3 VIC-III:B0ADEVN@BXADEVN Bitplane X address, even lines
C65 $D033.5-7 VIC-III:B0ADODD@BXADODD Bitplane X address, odd lines
C65 $D033 - Bitplane 0 address
C65 $D034.1-3 VIC-III:B1ADEVN @BXADEVN
C65 $D034.5-7 VIC-III:B1ADODD @BXADODD
C65 $D034 - Bitplane 1 address
C65 $D035.1-3 VIC-III:B2ADEVN @BXADEVN
C65 $D035.5-7 VIC-III:B2ADODD @BXADODD
C65 $D035 - Bitplane 2 address
C65 $D036.1-3 VIC-III:B3ADEVN @BXADEVN
C65 $D036.5-7 VIC-III:B3ADODD @BXADODD
C65 $D036 - Bitplane 3 address
C65 $D037.1-3 VIC-III:B4ADEVN @BXADEVN
C65 $D037.5-7 VIC-III:B4ADODD @BXADODD
C65 $D037 - Bitplane 4 address
C65 $D038.1-3 VIC-III:B5ADEVN @BXADEVN
C65 $D038.5-7 VIC-III:B5ADODD @BXADODD
C65 $D038 - Bitplane 5 address
C65 $D039.1-3 VIC-III:B6ADEVN @BXADEVN
C65 $D039.5-7 VIC-III:B6ADODD @BXADODD
C65 $D039 - Bitplane 6 address
C65 $D03A.1-3 VIC-III:B7ADEVN @BXADEVN
C65 $D03A.5-7 VIC-III:B7ADODD @BXADODD
C65 $D03A - Bitplane 7 address
C65 $D03B - Set bits to NOT bitplane contents
C65 $D03B VIC-III:BPCOMP Complement bitplane flags
C65 $D03C - Bitplane X
C65 $D03C VIC-III:BPX Bitplane X
C65 $D03D - Bitplane Y
C65 $D03D VIC-III:BPY Bitplane Y
C65 $D03E - Horizontal position (screen verniers?)
C65 $D03E VIC-III:HPOS Bitplane X Offset
C65 $D03F - Vertical position (screen verniers?)
C65 $D03F VIC-III:VPOS Bitplane Y Offset
C65 $D040 VIC-III:B0PIX@BNPIX Display Address Translater (DAT) Bitplane N port
C65 $D041 VIC-III:B1PIX @BNPIX
C65 $D042 VIC-III:B2PIX @BNPIX
C65 $D043 VIC-III:B3PIX @BNPIX
C65 $D044 VIC-III:B4PIX @BNPIX
C65 $D045 VIC-III:B5PIX @BNPIX
C65 $D046 VIC-III:B6PIX @BNPIX
C65 $D047 VIC-III:B7PIX @BNPIX
GS $D048 VIC-IV:TBDRPOS top border position
GS $D049.3-0 VIC-IV:TBDRPOS top border position MSB
GS $D049.7-4 VIC-IV:SPRBPMEN Sprite bitplane-modify-mode enables
GS $D04A VIC-IV:BBDRPOS bottom border position
GS $D04B.3-0 VIC-IV:BBDRPOS bottom border position
GS $D04B.7-4 VIC-IV:SPRBPMEN Sprite bitplane-modify-mode enables
GS $D04C VIC-IV:TEXTXPOS character generator horizontal position
GS $D04D.3-0 VIC-IV:TEXTXPOS character generator horizontal position
GS $D04D.7-4 VIC-IV:SPRTILEN Sprite horizontal tile enables.
GS $D04E VIC-IV:TEXTYPOS Character generator vertical position
GS $D04F.3-0 VIC-IV:TEXTYPOS Character generator vertical position
GS $D04F.7-4 VIC-IV:SPRTILEN Sprite 7-4 horizontal tile enables
GS $D050 VIC-IV:XPOSLSB Read horizontal raster scan position LSB
GS $D051.0-5 VIC-IV:XPOSMSB Read horizontal raster scan position MSB
GS $D051.6 VIC-IV:DBLRR When set, the Raster Rewrite Buffer is only updated every 2nd raster line, limiting resolution to V200, but allowing more cycles for Raster-Rewrite actions.
GS $D051.7 VIC-IV:NORRDEL When clear, raster rewrite double buffering is used
GS $D052 VIC-IV:FNRASTERLSB Read physical raster position
GS $D053.0-2 VIC-IV:FN!RASTER!MSB Read physical raster position
GS $D053.4 VIC-IV:RESERVED Reserved
GS $D053.5 VIC-IV:UPSCALE Enable integrated low-latency (130usec) 720p upscaler
GS $D053.6 VIC-IV:SHDEMU Enable simulated shadow-mask (PALEMU must also be enabled)
GS $D053.7 VIC-IV:FNRST Read raster compare source (0=VIC-IV fine raster, 1=VIC-II raster), provides same value as set in FNRSTCMP
GS $D054.0 VIC-IV:CHR16 enable 16-bit character numbers (two screen bytes per character)
GS $D054.1 VIC-IV:FCLRLO enable full-colour mode for character numbers <=$FF
GS $D054.2 VIC-IV:FCLRHI enable full-colour mode for character numbers >$FF
GS $D054.3 VIC-IV:SMTH video output horizontal smoothing enable
GS $D054.4 VIC-IV:SPR!H640 Sprite H640 enable
GS $D054.5 VIC-IV:PALEMU Enable PAL CRT-like scan-line emulation
GS $D054.6 VIC-IV:VFAST C65GS FAST mode (48MHz)
GS $D054.7 VIC-IV:ALPHEN Alpha compositor enable
GS $D054 SUMMARY:VIC-IV Control register C
GS $D055 VIC-IV:SPRHGTEN sprite extended height enable (one bit per sprite)
GS $D056 VIC-IV:SPRHGHT Sprite extended height size (sprite pixels high)
GS $D057 VIC-IV:SPRX64EN Sprite extended width enables (8 bytes per sprite row = 64 pixels wide for normal sprites or 16 pixels wide for 16-colour sprite mode)
GS $D058 VIC-IV:LINESTEPLSB number of bytes to advance between each text row (LSB)
GS $D059 VIC-IV:LINESTEPMSB number of bytes to advance between each text row (MSB)
GS $D05A VIC-IV:CHRXSCL Horizontal hardware scale of text mode (pixel 120ths per pixel)
GS $D05B VIC-IV:CHRYSCL Vertical scaling of text mode (number of physical rasters per char text row)
GS $D05C VIC-IV:SDBDRWD!LSB Width of single side border (LSB)
GS $D05D.0-5 VIC-IV:SDBDRWD!MSB side border width (MSB)
GS $D05D.6 VIC-IV:RST!DELEN Enable raster delay (delays raster counter and interrupts by one line to match output pipeline latency)
GS $D05D.7 VIC-IV:HOTREG Enable VIC-II hot registers. When enabled, touching many VIC-II registers causes the VIC-IV to recalculate display parameters, such as border positions and sizes. Touching registers while this is disabled will trigger a change when reenabling. Setting this to 0 will clear the recalc flag, canceling the recalculation.
GS $D05E VIC-IV:CHRCOUNT Number of characters to display per row (LSB)
GS $D05F VIC-IV:SPRXSMSBS Sprite H640 X Super-MSBs
GS $D060 VIC-IV:SCRNPTRLSB screen RAM precise base address (bits 0 - 7)
GS $D061 VIC-IV:SCRNPTRMSB screen RAM precise base address (bits 15 - 8)
GS $D062 VIC-IV:SCRNPTRBNK screen RAM precise base address (bits 23 - 16)
GS $D063.0-3 VIC-IV:SCRNPTRMB screen RAM precise base address (bits 27 - 24)
GS $D063.4-5 VIC-IV:CHRCOUNT Number of characters to display per
GS $D063.6 VIC-IV:FCOLMCM enable 256 colours in multicolour text mode
GS $D063.7 VIC-IV:EXGLYPH source full-colour character data from expansion RAM
GS $D064 VIC-IV:COLPTRLSB colour RAM base address (bits 0 - 7)
GS $D065 VIC-IV:COLPTRMSB colour RAM base address (bits 15 - 8)
GS $D066.0-4 VIC-IV xcounter pipeline delay DEBUG WILL BE REMOVED
GS $D066.6 VIC-IV render activity display enable DEBUG WILL BE REMOVED
GS $D066.7 VIC-IV test pattern display enable DEBUG WILL BE REMOVED
GS $D067 DEBUG:SBPDEBUG Sprite/bitplane first X DEBUG WILL BE REMOVED
GS $D068 VIC-IV:CHARPTRLSB Character set precise base address (bits 0 - 7)
GS $D069 VIC-IV:CHARPTRMSB Character set precise base address (bits 15 - 8)
GS $D06A VIC-IV:CHARPTRBNK Character set precise base address (bits 23 - 16)
GS $D06B VIC-IV:SPR16EN sprite 16-colour mode enables
GS $D06C VIC-IV:SPRPTRADRLSB sprite pointer address (bits 7 - 0)
GS $D06D VIC-IV:SPRPTRADRMSB sprite pointer address (bits 15 - 8)
GS $D06E.0-6 VIC-IV:SPRPTRBNK sprite pointer address (bits 23 - 16)
GS $D06E.7 VIC-IV:SPR!PTR16 16-bit sprite pointer mode (allows sprites to be located on any 64 byte boundary in chip RAM)
GS $D06F.5-0 VIC-IV:RASLINE0 first VIC-II raster line
GS $D06F.6 VIC-IV:VGAHDTV Select more VGA-compatible mode if set, instead of HDMI/HDTV VIC-II cycle-exact frame timing. May help to produce a functional display on older VGA monitors.
GS $D06F.7 VIC-IV:PALNTSC NTSC emulation mode (max raster = 262)
GS $D070.1-0 VIC-IV:ABTPALSEL VIC-IV bitmap/text palette bank (alternate palette)
GS $D070.3-2 VIC-IV:SPRPALSEL sprite palette bank
GS $D070.5-4 VIC-IV:BTPALSEL bitmap/text palette bank
GS $D070.7-6 VIC-IV:MAPEDPAL palette bank mapped at $D100-$D3FF
GS $D070 NONE:VIC-IV palette bank selection
GS $D071 VIC-IV:BP16ENS VIC-IV 16-colour bitplane enable flags
GS $D072 VIC-IV:SPRYADJ Sprite Y position adjustment
GS $D073.0-3 VIC-IV:ALPHADELAY Alpha delay for compositor
GS $D073.4-7 VIC-IV:RASTERHEIGHT physical rasters per VIC-II raster (1 to 16)
GS $D074 VIC-IV:SPRENALPHA Sprite alpha-blend enable
GS $D075 VIC-IV:SPRALPHAVAL Sprite alpha-blend value
GS $D076 VIC-IV:SPRENV400 Sprite V400 enables
GS $D077 VIC-IV:SPRYMSBS Sprite V400 Y position MSBs
GS $D078 VIC-IV:SPRYSMSBS Sprite V400 Y position super MSBs
GS $D079 VIC-IV:RASCMP Physical raster compare value to be used if FNRSTCMP is clear
GS $D07A.0-2 VIC-IV:RASCMP!MSB Raster compare value MSB
GS $D07A.3 VIC-IV:SPTR!CONT Continuously monitor sprite pointer, to allow changing sprite data source while a sprite is being drawn
GS $D07A.4 VIC-IV:CHARY16 Alternate char ROM bank on alternate raster lines in V200
GS $D07A.5 VIC-IV:NOBUGCOMPAT *DEPRECATED*, use HWERRATA - Disables VIC-III / C65 Bug Compatibility Mode if set
GS $D07A.6 VIC-IV:EXTIRQS Enable additional IRQ sources, e.g., raster X position.
GS $D07A.7 VIC-IV:FNRST!CMP Raster compare is in physical rasters if clear, or VIC-II rasters if set
GS $D07B VIC-IV:DISP!ROWS Number of text rows to display
GS $D07C.0-2 VIC-IV:BIT!PBANK Set which 128KB bank bitplanes
GS $D07C.3 VIC-IV:RESV @RESV
GS $D07C.4 VIC-IV:HSYNCP hsync polarity
GS $D07C.5 VIC-IV:VSYNCP vsync polarity
GS $D07C.6-7 VIC-IV:DEBUGC VIC-IV debug pixel select red(01), green(10) or blue(11) channel visible in $D07D
GS $D07D DEBUG:DEBUGOUT VIC-IV debug value read-back (read only)
GS $D07D DEBUG:DEBUGX VIC-IV debug X position (LSB) (write only)
GS $D07E DEBUG:DEBUGY VIC-IV debug Y position (LSB)
GS $D07F.0-3 DEBUG:DEBUGX VIC-IV debug X position (MSB)
GS $D07F.4-7 DEBUG:DEBUGY VIC-IV debug Y position (MSB)
GS $D07F.7 DEBUG:DEBUGOOF VIC-IV debug out-of-frame signal enable
C65 $D080.0-2 FDC:DS Drive select (0 to 7). Internal drive is 0. Second floppy drive on internal cable is 1. Other values reserved for C1565 external drive interface.
C65 $D080.3 FDC:SIDE Directly controls the SIDE signal to the floppy drive, i.e., selecting which side of the media is active.
C65 $D080.4 FDC:SWAP Swap upper and lower halves of data buffer (i.e. invert bit 8 of the sector buffer)
C65 $D080.5 FDC:MOTOR Activates drive motor and LED (unless LED signal is also set, causing the drive LED to blink)
C65 $D080.6 FDC:LED Drive LED blinks when set
C65 $D080.7 FDC:IRQ When set, enables interrupts to occur. Clearing clears any pending interrupt and disables interrupts until set again.
C65 $D080 - F011 FDC control
C65 $D081.0 FDC:NOBUF Reset the sector buffer read/write pointers
C65 $D081.1 FDC:ALT Selects alternate DPLL read recovery method (not implemented)
C65 $D081.2 FDC:ALGO Selects reading and writing algorithm (currently ignored).
C65 $D081.3 FDC:DIR Sets the stepping direction (inward vs
C65 $D081.4 FDC:STEP Writing 1 causes the head to step in the indicated direction
C65 $D081.5 FDC:FREE Command is a free-format (low level) operation
C65 $D081.6 FDC:RDCMD Command is a read operation if set
C65 $D081.7 FDC:WRCMD Command is a write operation if set
C65 $D081 FDC:COMMAND F011 FDC command register
C65 $D082.0 FDC:TK0 F011 Head is over track 0 flag (read only)
C65 $D082.1 FDC:PROT F011 Disk write protect flag (read only)
C65 $D082.2 FDC:LOST F011 LOST flag (data was lost during transfer, i.e., CPU did not read data fast enough) (read only)
C65 $D082.3 FDC:CRC F011 FDC CRC check failure flag (read only)
C65 $D082.4 FDC:RNF F011 FDC Request Not Found (RNF), i.e., a sector read or write operation did not find the requested sector (read only)
C65 $D082.5 FDC:EQ F011 FDC CPU and disk pointers to sector buffer are equal, indicating that the sector buffer is either full or empty. (read only)
C65 $D082.6 FDC:DRQ F011 FDC DRQ flag (one or more bytes of data are ready) (read only)
C65 $D082.7 FDC:BUSY F011 FDC busy flag (command is being executed) (read only)
C65 $D082 - F011 FDC Status A port (read only)
C65 $D083.0 FDC:DSKCHG F011 disk change sense (read only)
C65 $D083.1 FDC:IRQ The floppy controller has generated an interrupt (read only). Note that interrupts are not currently implemented on the 45GS27.
C65 $D083.2 FDC:INDEX F011 Index hole sense (read only)
C65 $D083.3 FDC:DISKIN F011 Disk sense (read only)
C65 $D083.4 FDC:WGATE F011 write gate flag. Indicates that the drive is currently writing to media. Bad things may happen if a write transaction is aborted (read only)
C65 $D083.5 FDC:RUN F011 Successive match. A synonym of RDREQ on the 45IO47 (read only)
C65 $D083.6 FDC:WTREQ F011 Write Request flag, i.e., the requested sector was found during a write operation (read only)
C65 $D083.7 FDC:RDREQ F011 Read Request flag, i.e., the requested sector was found during a read operation (read only)
C65 $D083 - F011 FDC Status B port (read only)
C65 $D084 FDC:TRACK F011 FDC track selection register
C65 $D085 FDC:SECTOR F011 FDC sector selection register
C65 $D086 FDC:SIDE F011 FDC side selection register
C65 $D087 FDC:DATA F011 FDC data register (read/write) for accessing the floppy controller's 512 byte sector buffer
C65 $D088 FDC:CLOCK Set or read the clock pattern to be used when writing address and data marks. Should normally be left $FF
C65 $D089 FDC:STEP Set or read the track stepping rate in 62.5 microsecond steps (normally 128, i.e., 8 milliseconds).
C65 $D08A FDC:PCODE (Read only) returns the protection code of the most recently read sector. Was intended for rudimentary copy protection. Not implemented.
GS $D08F MISCIO:HWERRATA Set/get MEGA65 hardware errata level
GS $D09B - FSM state of low-level SD controller (DEBUG)
GS $D09C - Last byte low-level SD controller read from card (DEBUG)
GS $D09D - FDC-side buffer pointer high bit (DEBUG)
GS $D09E - CPU-side buffer pointer low bits (DEBUG)
GS $D09F.0 - CPU-side buffer pointer high bit (DEBUG)
GS $D09F.1 - EQ flag (DEBUG)
GS $D09F.2 - EQ flag inhibit state (DEBUG)
C65 $D0A0-$D0FF - Reserved for C65 RAM Expansion Controller.
C65 $D0A0-$D0FF SUMMARY:REC Reserved for C65 RAM Expansion Controller.
C65 $D0A0 C65 RAM Expansion controller
GS $D0E0.0-3 Select active UART for other registers
GS $D0E0.4 Enable loopback mode
GS $D0E0.5 Buffered UART master RX buffer high-water IRQ enable
GS $D0E0.6 Buffered UART master TX queue low-water IRQ enable
GS $D0E0.7 Buffered UART master IRQ enable
GS $D0E1.0 Buffered UART enable interrupt on TX buffer low-water mark
GS $D0E1.1 Buffered UART enable interrupt on RX high-water mark
GS $D0E1.2 Buffered UART enable interrupt on RX byte
GS $D0E1.3 Buffered UART TX buffer full
GS $D0E1.4 Buffered UART RX buffer full
GS $D0E1.5 Buffered UART TX buffer empty
GS $D0E1.6 Buffered UART RX buffer empty
GS $D0E1.7 Buffered UART interrupt status
GS $D0E1 Buffered UART Status register / interrupt select register
GS $D0E2 Buffered UART Read register (write to ACK receipt of byte)
GS $D0E3 Buffered UART Write register (write to send byte)
GS $D0E4 Buffered UART bit rate divisor LSB
GS $D0E5 Buffered UART bit rate divisor middle byte
GS $D0E6 Buffered UART bit rate divisor MSB
GS $D0 ETHCOMMAND:RXNORMAL Disable the effects of RXONLYONE
C65 $D100-$D1FF VIC-III:PALRED red palette values (reversed nybl order)
C65 $D200-$D2FF VIC-III:PALGREEN green palette values (reversed nybl order)
C65 $D300-$D3FF VIC-III:PALBLUE blue palette values (reversed nybl order)
C64 $D400-$D40F = SID#1 (internally known as 'right SID #1' or as 'rightsid')
GS $D400 SID:VOICE1!FRQLO@VOICEX!FRQLO Voice X Frequency Low
GS $D401 SID:VOICE1!FRQHI@VOICEX!FRQHI Voice X Frequency High
GS $D402 SID:VOICE1!PWLO@VOICEX!PWLO Voice X Pulse Waveform Width Low
GS $D403.0-3 SID:VOICE1!PWHI@VOICEX!PWHI Voice X Pulse Waveform Width High
GS $D403.4-7 SID:VOICE1!UNSD@VOICEX!UNSD Unused
GS $D404.0 SID:VOICE1!CTRLGATE@VOICEX!CTRLGATE Voice X Gate Bit (1 = Start, 0 = Release)
GS $D404.1 SID:VOICE1!CTRLRMF Voice 1 Synchronize Osc. 1 with Osc. 3 Frequency
GS $D404.2 SID:VOICE1!CTRLRMO Voice 1 Ring Modulate Osc. 1 with Osc. 3 Output
GS $D404.3 SID:VOICE1!CTRLTST@VOICEX!CTRLTST Voice X Test Bit - Disable Oscillator
GS $D404.4 SID:VOICE1!CTRLTRI@VOICEX!CTRLTRI Voice X Triangle Waveform
GS $D404.5 SID:VOICE1!CTRLSAW@VOICEX!CTRLSAW Voice X Sawtooth Waveform
GS $D404.6 SID:VOICE1!CTRLPUL@VOICEX!CTRLPUL Voice X Pulse Waveform
GS $D404.7 SID:VOICE1!CTRLRNW@VOICEX!CTRLRNW Voice X Control Random Noise Waveform
GS $D405.3-0 SID:ENV1!DECDUR@ENVX!DECDUR Envelope Generator X Decay Cycle Duration
GS $D405.7-4 SID:ENV1!ATTDUR@ENVX!ATTDUR Envelope Generator X Attack Cycle Duration
GS $D406.3-0 SID:ENV1!RELDUR@ENVX!RELDUR Envelope Generator X Release Cycle Duration
GS $D406.7-4 SID:ENV1!SUSLEV@ENVX!SUSLEV Envelope Generator X Sustain Level
GS $D407 SID:VOICE2!FRQLO @VOICEX!FRQLO
GS $D408 SID:VOICE2!FRQHI @VOICEX!FRQHI
GS $D409 SID:VOICE2!PWLO @VOICEX!PWLO
GS $D40A.0-3 SID:VOICE2!PWHI @VOICEX!PWHI
GS $D40A.4-7 SID:VOICE2!UNSD @VOICEX!UNSD
GS $D40B.0 SID:VOICE2!CTRLGATE @VOICEX!CTRLGATE
GS $D40B.1 SID:VOICE2!CTRLRMF Voice 2 Synchronize Osc. 2 with Osc. 1 Frequency
GS $D40B.2 SID:VOICE2!CTRLRMO Voice 2 Ring Modulate Osc. 2 with Osc. 1 Output
GS $D40B.3 SID:VOICE2!CTRLTST @VOICEX!CTRLTST
GS $D40B.4 SID:VOICE2!CTRLTRI @VOICEX!CTRLTRI
GS $D40B.5 SID:VOICE2!CTRLSAW @VOICEX!CTRLSAW
GS $D40B.6 SID:VOICE2!CTRLPUL @VOICEX!CTRLPUL
GS $D40B.7 SID:VOICE2!CTRLRNW @VOICEX!CTRLRNW
GS $D40C.3-0 SID:ENV2!DECDUR @ENVX!DECDUR
GS $D40C.7-4 SID:ENV2!ATTDUR @ENVX!ATTDUR
GS $D40D.3-0 SID:ENV2!RELDUR @ENVX!RELDUR
GS $D40D.7-4 SID:ENV2!LEVDUR @ENVX!LEVDUR
GS $D40E SID:VOICE3!FRQLO @VOICEX!FRQLO
GS $D40F SID:VOICE3!FRQHI @VOICEX!FRQHI
GS $D410 SID:VOICE3!PWLO @VOICEX!PWLO
GS $D411.0-3 SID:VOICE3!PWHI @VOICEX!PWHI
GS $D411.4-7 SID:VOICE3!UNSD @VOICEX!UNSD
GS $D412.0 SID:VOICE3!CTRLGATE @VOICEX!CTRLGATE
GS $D412.1 SID:VOICE3!CTRLRMF Voice 3 Synchronize Osc. 3 with Osc. 2 Frequency
GS $D412.2 SID:VOICE3!CTRLRMO Voice 3 Ring Modulate Osc. 3 with Osc. 2 Output
GS $D412.3 SID:VOICE3!CTRLTST @VOICEX!CTRLTST
GS $D412.4 SID:VOICE3!CTRLTRI @VOICEX!CTRLTRI
GS $D412.5 SID:VOICE3!CTRLSAW @VOICEX!CTRLSAW
GS $D412.6 SID:VOICE3!CTRLPUL @VOICEX!CTRLPUL
GS $D412.7 SID:VOICE3!CTRLRNW @VOICEX!CTRLRNW
GS $D413.3-0 SID:ENV3!DECDUR @ENVX!DECDUR
GS $D413.7-4 SID:ENV3!ATTDUR @ENVX!ATTDUR
GS $D414.3-0 SID:ENV3!RELDUR @ENVX!RELDUR
GS $D414.7-4 SID:ENV3!LEVDUR @ENVX!SUSLEV
GS $D415 SID:FLTR!CUTFRQLO@FLTR!CUTFRQLO Filter Cutoff Frequency Low
GS $D416 SID:FLTR!CUTFRQHI@FLTR!CUTFRQHI Filter Cutoff Frequency High
GS $D417.0 SID:FLTR!V3OUT @FLTR!VXOUT
GS $D417.1 SID:FLTR!V2OUT @FLTR!VXOUT
GS $D417.2 SID:FLTR!V1OUT@FLTR!VXOUT Filter Voice X Output
GS $D417.3 SID:FLTR!EXTINP@FLTR!EXTINP Filter External Input
GS $D417.7-4 SID:FLTR!RESON@FLTR!RESON Filter Resonance
GS $D418.0-3 SID:FLTR!VOL Filter Output Volume
GS $D418.4 SID:FLTR!LOPASS Filter Low-Pass Mode
GS $D418.5 SID:FLTR!BDPASS Filter Band-Pass Mode
GS $D418.6 SID:FLTR!HIPASS Filter High-Pass Mode
GS $D418.7 SID:FLTR!CUTV3 Filter Cut-Off Voice 3 Output (1 = off)
GS $D419 SID:PADDLE1 Analog/Digital Converter: Game Paddle 1 (0-255)
GS $D41A SID:PADDLE2 Analog/Digital Converter Game Paddle 2 (0-255)
GS $D41B SID:OSC3RNG Oscillator 3 Random Number Generator
GS $D41C SID:ENV3OUT Envelope Generator 3 Output
C64 $D420-$D43F = SID#2 (internally known as 'right SID #2' or as 'backsid')
C64 $D440-$D45F = SID#3 (internally known as 'left SID #1' or as 'leftsid')
C64 $D460-$D47F = SID#4 (internally known as 'left SID #2' or as 'backsid')
C64 $D480-$D4FF = repeated images of SIDs
GS $D4 ETHCOMMAND:DEBUGVIC Select VIC-IV debug stream via ethernet when \$D6E1.3 is set
C65 $D600 UART:DATA UART data register (read or write)
C65 $D601.0 UART:RXRDY UART RX byte ready flag (clear by reading \$D600)
C65 $D601.1 UART:RXOVRRUN UART RX overrun flag (clear by reading \$D600)
C65 $D601.2 UART:PTYERR UART RX parity error flag (clear by reading \$D600)
C65 $D601.3 UART:FRMERR UART RX framing error flag (clear by reading \$D600)
C65 $D601 C65 UART status register
C65 $D602.0 UART:PTYEVEN UART Parity: 1=even, 0=odd
C65 $D602.1 UART:PTYEN UART Parity enable: 1=enabled
C65 $D602.2-3 UART:CHARSZ UART character size: 00=8, 01=7, 10=6, 11=5 bits per byte
C65 $D602.4-5 UART:SYNCMOD UART synchronisation mode flags (00=RX \& TX both async, 01=RX sync, TX async, 1x=TX sync, RX async (unused on the MEGA65)
C65 $D602.6 UART:RXEN UART enable receive
C65 $D602.7 UART:TXEN UART enable transmit
C65 $D602 C65 UART control register
C65 $D603 UART:DIVISOR UART baud rate divisor (16 bit). Baud rate = 7.09375MHz / DIVISOR, unless MEGA65 fast UART mode is enabled, in which case baud rate = 80MHz / DIVISOR
C65 $D604 UART:DIVISOR UART baud rate divisor (16 bit). Baud rate = 7.09375MHz / DIVISOR, unless MEGA65 fast UART mode is enabled, in which case baud rate = 80MHz / DIVISOR
C65 $D605.4 UART:IMRXNMI UART interrupt mask: NMI on RX (not yet implemented on the MEGA65)
C65 $D605.5 UART:IMTXNMI UART interrupt mask: NMI on TX (not yet implemented on the MEGA65)
C65 $D605.6 UART:IMRXIRQ UART interrupt mask: IRQ on RX (not yet implemented on the MEGA65)
C65 $D605.7 UART:IMTXIRQ UART interrupt mask: IRQ on TX (not yet implemented on the MEGA65)
C65 $D606.4 UART:IFRXNMI UART interrupt flag: NMI on RX (not yet implemented on the MEGA65)
C65 $D606.5 UART:IFTXNMI UART interrupt flag: NMI on TX (not yet implemented on the MEGA65)
C65 $D606.6 UART:IFRXIRQ UART interrupt flag: IRQ on RX (not yet implemented on the MEGA65)
C65 $D606.7 UART:IFTXIRQ UART interrupt flag: IRQ on TX (not yet implemented on the MEGA65)
C65 $D606 C65 UART interrupt flag register
GS $D607.0 UART:CAPLOCK C65 capslock key sense
GS $D607.1 UART:KEYCOL8 C65 keyboard column 8 select
C65 $D607 C65 UART 2-bit port data register (used for C65 keyboard)
GS $D608.0-1 UART:PORTEDDR C65 keyboard extra lines Data Direction Register (DDR)
C65 $D608 C65 UART data direction register (used for C65 keyboard)
GS $D609.0 UARTMISC:UFAST C65 UART BAUD clock source: 1 = 7.09375MHz, 0 = 80MHz (VIC-IV pixel clock)
GS $D609.6 FSERIAL:FSDIR Direction register for DMODE (not yet implemented)
GS $D609.7 FSERIAL:DMODE Fast IEC serial (not yet implemented)
GS $D609 MEGA65 extended UART control register
GS $D60A.0 UARTMISC:MODKEYLSHFT Left shift key state at top of typing event queue. 1 = held during event.
GS $D60A.1 UARTMISC:MODKEYRSHFT Right shift key state at top of typing event queue. 1 = held during event.
GS $D60A.2 UARTMISC:MODKEYCTRL CTRL key state at top of typing event queue. 1 = held during event.
GS $D60A.3 UARTMISC:MODKEYMEGA MEGA/C= key state at top of typing event queue. 1 = held during event.
GS $D60A.4 UARTMISC:MODKEYALT ALT key state at top of typing event queue. 1 = held during event.
GS $D60A.5 UARTMISC:MODKEYSCRL NOSCRL key state at top of typing event queue. 1 = held during event.
GS $D60A.6 UARTMISC:MODKEYCAPS CAPS LOCK key state at top of typing event queue. 1 = held during event.
GS $D60A.7 UARTMISC:KEYQUEUE 1 = Typing event queue is non-empty. Write 0 to this bit to flush queue.
GS $D60B.5-0 UARTMISC:PORTF PMOD port A on FPGA board (data) (Nexys4 boards only)
GS $D60B.6 UARTMISC:OSKZON Display hardware zoom of region under first touch point always
GS $D60B.7 UARTMISC:OSKZEN Display hardware zoom of region under first touch point for on-screen keyboard
GS $D60C.0-5 UARTMISC:PORTFDDR PMOD port A on FPGA board (DDR)
GS $D60C.6-7 UARTMISC:PORTFDDR On Screen Keyboard (OSK) Zoom Control Data Direction Register (DDR). Must be set to output to control these features.
GS $D60D.0 - Internal 1541 drive connect (1= use internal 1541 instead of IEC drive connector)
GS $D60D.0 UARTMISC:CONN41 Internal 1541 drive connect (1=connect internal 1541 drive to IEC bus)
GS $D60D.1 - Internal 1541 drive reset
GS $D60D.1 UARTMISC:RST41 Internal 1541 drive reset (1=reset, 0=operate)
GS $D60D.2 UARTMISC:SDDATA SD card MOSI/MISO
GS $D60D.3 UARTMISC:SDCLK SD card SCLK
GS $D60D.4 UARTMISC:SDCS SD card CS_BO
GS $D60D.5 UARTMISC:SDBSH Enable SD card bitbash mode
GS $D60D.6 UARTMISC:HDSDA HDMI I2C control interface SDA data line
GS $D60D.7 UARTMISC:HDSCL HDMI I2C control interface SCL clock
GS $D60D Bit bashing port
GS $D60E UARTMISC:BASHDDR Data Direction Register (DDR) for \$D60D bit bashing port.
GS $D60F.0 UARTMISC:KEYLEFT Directly read C65 Cursor left key
GS $D60F.1 UARTMISC:KEYUP Directly read C65 Cursor up key
GS $D60F.5 UARTMISC:REALHW Set to 1 if the MEGA65 is running on real hardware, set to 0 if emulated (Xemu) or simulated (ghdl)
GS $D60F.6 UARTMISC:OSKDIM Light or heavy dimming of background material behind on-screen keyboard
GS $D60F.7 UARTMISC:ACCESSKEY Enable accessible keyboard input via joystick port 2 fire button
GS $D610 UARTMISC:ASCIIKEY Top of typing event queue as ASCII. Write to clear event ready for next.
GS $D611.0 UARTMISC:MLSHFT Left shift key state (immediate; read only).
GS $D611.0 WRITE ONLY Connect POT lines to IEC port (for r1 PCB only)
GS $D611.1 UARTMISC:MRSHFT Right shift key state (immediate; read only).
GS $D611.1 WRITE ONLY enable real joystick ports (for r2 PCB only)
GS $D611.2 UARTMISC:MCTRL CTRL key state (immediate; read only).
GS $D611.3 UARTMISC:MMEGA MEGA/C= key state (immediate; read only).
GS $D611.4 UARTMISC:MALT ALT key state (immediate; read only).
GS $D611.5 UARTMISC:MSCRL NOSCRL key state (immediate; read only).
GS $D611.6 UARTMISC:MCAPS CAPS LOCK key state (immediate; read only).
GS $D611.7 UARTMISC:MDISABLE Disable modifiers.
GS $D611 Modifier key state.
GS $D612.0 UARTMISC:WGTKEY Enable widget board keyboard/joystick input
GS $D612.1 UARTMISC:PS2KEY Enable ps2 keyboard/joystick input
GS $D612.2 UARTMISC:PHYKEY Enable physical keyboard input
GS $D612.3 UARTMISC:VRTKEY Enable virtual/snythetic keyboard input
GS $D612.4 UARTMISC:OSKDEBUG Debug OSK overlay (WRITE ONLY)
GS $D612.4 UARTMISC:PS2JOY Enable PS/2 / USB keyboard simulated joystick input
GS $D612.5 UARTMISC:JOYSWAP Exchange joystick ports 1 \& 2
GS $D612.6 UARTMISC:LJOYA Rotate inputs of joystick A by 180 degrees (for left handed use)
GS $D612.7 UARTMISC:LJOYB Rotate inputs of joystick B by 180 degrees (for left handed use)
GS $D613 UARTMISC:KEYMATRIXPEEK 8-bit segment of combined keyboard matrix (READ)
GS $D614 UARTMISC:KEYMATRIXSEL Select which 8-bit segment of combined keyboard matrix to read.
GS $D615.0-6 UARTMISC:VIRTKEY1 Set to \$7F for no key down, else specify virtual key press.
GS $D615.7 UARTMISC:OSKEN Enable display of on-screen keyboard composited overlay
GS $D616.0-6 UARTMISC:VIRTKEY2 Set to \$7F for no key down, else specify 2nd virtual key press.
GS $D616.7 UARTMISC:OSKALT Display alternate on-screen keyboard layout (typically dial pad for MEGA65 telephone)
GS $D617.0-6 UARTMISC:VIRTKEY3 Set to \$7F for no key down, else specify 3nd virtual key press.
GS $D617.7 UARTMISC:OSKTOP 1=Display on-screen keyboard at top, 0=Disply on-screen keyboard at bottom of screen.
GS $D618 UARTMISC:KSCNRATE Physical keyboard scan rate (\$00=50MHz, \$FF=~200KHz)
GS $D619 UARTMISC:PETSCIIKEY Top of typing event queue as PETSCII. Write to clear event ready for next.
GS $D61A.0 SYSCTL:AUDMUTE Mute digital video audio (MEGA65 R2 only)
GS $D61A.1 SYSCTL:DVI Control digital video as DVI (disables audio)
GS $D61A.2 SYSCTL:AUDDBG Visualise audio samples (DEBUG)
GS $D61A.3 SYSCTL:AUD48K Select 48KHz or 44.1KHz digital video audio sample rate
GS $D61A.4 SYSCTL:LED Control LED next to U1 on mother board
GS $D61A.7 SYSCTL:AUDINV Invert digital video audio sample values
GS $D61A UARTMISC:SYSCTL System control flags (target specific)
GS $D61B.0 WRITEONLY enable/disable Amiga mouse support (1351 emulation) on jostick 1
GS $D61B.1 WRITEONLY enable/disable Amiga mouse support (1351 emulation) on jostick 2
GS $D61B.2 WRITEONLY assume amiga mouse on jostick 1 if enabled.
GS $D61B.3 WRITEONLY assume amiga mouse on jostick 2 if enabled.
GS $D61B.6 WRITEONLY DEBUG disable ASCII key retrigger suppression
GS $D61B.7 WRITEONLY DEBUG disable ASCII key glitch suppression
GS $D61B DEBUG:AMIMOUSDETECT READ 1351/amiga mouse auto detection DEBUG
GS $D61C DEBUG:1541PCLSB internal 1541 PC LSB
GS $D61D.0-6 UARTMISC:KEYLED!REG Keyboard LED register select (R,G,B channels x 4 = 0 to 11)
GS $D61D.7 UARTMISC:KEYLED!ENA Keyboard LED control enable
GS $D61E UARTMISC:KEYLED!VAL Keyboard LED register value (write only)
GS $D61F DEBUG:BUCKYCOPY DUPLICATE Modifier key state (hardware accelerated keyboard scanner).
GS $D620 UARTMISC:POTAX Read Port A paddle X, without having to fiddle with SID/CIA settings.
GS $D621 UARTMISC:POTAY Read Port A paddle Y, without having to fiddle with SID/CIA settings.
GS $D622 UARTMISC:POTBX Read Port B paddle X, without having to fiddle with SID/CIA settings.
GS $D623 UARTMISC:POTBY Read Port B paddle Y, without having to fiddle with SID/CIA settings.
GS $D624.0 Paddles connected via IEC port (rev1 PCB debug)
GS $D624.1 pot_drain signal
GS $D624.3-2 CIA porta bits 7-6 for POT multiplexor
GS $D624.4 fa_potx line
GS $D624.5 fa_poty line
GS $D624.6 fb_potx line
GS $D624.7 fb_poty line
GS $D624 DEBUG:POTDEBUG READ ONLY flags for paddles. See c65uart.vhdl for more information.
GS $D625 UARTMISC:J21L J21 pins 1 -- 6, 9 -- 10 input/output values
GS $D626 UARTMISC:J21H J21 pins 11 -- 14 input/output values
GS $D627 UARTMISC:J21LDDR J21 pins 1 -- 6, 9 -- 10 data direction register
GS $D628.0-3 UARTMISC:J21HDDR J21 pins 11 -- 14 data direction register
GS $D628.4-7 UARTMISC:BOARDMINOR Read PCB minor revision (R5+ only, else reads zeroes)
GS $D629 UARTMISC:M65MODEL MEGA65 model ID. Can be used to determine the model of MEGA65 a programme is running on, e.g., to enable touch controls on MEGAphone.
GS $D62A KBD:FWDATEL LSB of keyboard firmware date stamp (days since 1 Jan 2020)
GS $D62B KBD:FWDATEH MSB of keyboard firmware date stamp (days since 1 Jan 2020)
GS $D62C KBD:FWGIT0 LSB of keyboard firmware git commit
GS $D62D KBD:FWGIT0 2nd byte of keyboard firmware git commit
GS $D62E KBD:FWGIT0 3rd byte of keyboard firmware git commit
GS $D62F KBD:FWGIT0 MSB of keyboard firmware git commit
GS $D630 FPGA:FWDATEL LSB of MEGA65 FPGA design date stamp (days since 1 Jan 2020)
GS $D631 FPGA:FWDATEH MSB of MEGA65 FPGA design date stamp (days since 1 Jan 2020)
GS $D632 FPGA:FWGIT0 LSB of MEGA65 FPGA design git commit
GS $D633 FPGA:FWGIT0 2nd byte of MEGA65 FPGA design git commit
GS $D634 FPGA:FWGIT0 3rd byte of MEGA65 FPGA design git commit
GS $D635 FPGA:FWGIT0 MSB of MEGA65 FPGA design git commit
GS $D636 AUXFPGA:FWDATEL LSB of Auxilliary (MAX10) FPGA design date stamp (days since 1 Jan 2020)
GS $D637 AUXFPGA:MFWDATEH MSB of Auxilliary (MAX10) FPGA design date stamp (days since 1 Jan 2020)
GS $D638 AUXFPGA:FWGIT0 LSB of Auxilliary (MAX10) FPGA design git commit
GS $D639 AUXFPGA:FWGIT0 2nd byte of Auxilliary (MAX10) FPGA design git commit
GS $D63A AUXFPGA:FWGIT0 3rd byte of Auxilliary (MAX10) FPGA design git commit
GS $D63B AUXFPGA:FWGIT0 MSB of Auxilliary (MAX10) FPGA design git commit
GS $D63C.0-3 SID:SIDMODE Select SID mode: 0=6581, 1=8580
GS $D63C.4 AUDIOMIX:DCTRKEN Enable DC offset subtraction in audio mixer
GS $D63C.5-7 DEBUG:RESETSRC Source of last CPU reset
GS $D63D AUDIOMIX:DCTIME Audio mixer DC-estimation time step. Lower values = faster updating of DC estimation, at the cost of making low-frequencies quieter.
GS $D640 CPU:HTRAP00@HTRAPXX Writing triggers hypervisor trap \$XX
GS $D640 HCPU:REGA Hypervisor A register storage
GS $D641 CPU:HTRAP01 @HTRAPXX
GS $D641 HCPU:REGX Hypervisor X register storage
GS $D642 CPU:HTRAP02 @HTRAPXX
GS $D642 HCPU_REGY Hypervisor Y register storage
GS $D643 CPU:HTRAP03 @HTRAPXX
GS $D643 HCPU:REGZ Hypervisor Z register storage
GS $D644 CPU:HTRAP04 @HTRAPXX
GS $D644 HCPU:REGB Hypervisor B register storage
GS $D645 CPU:HTRAP05 @HTRAPXX
GS $D645 HCPU:SPL Hypervisor SPL register storage
GS $D646 CPU:HTRAP06 @HTRAPXX
GS $D646 HCPU:SPH Hypervisor SPH register storage
GS $D647 CPU:HTRAP07 @HTRAPXX
GS $D647 HCPU:PFLAGS Hypervisor P register storage
GS $D648 CPU:HTRAP08 @HTRAPXX
GS $D648 HCPU:PCL Hypervisor PC-low register storage
GS $D649 CPU:HTRAP09 @HTRAPXX
GS $D649 HCPU:PCH Hypervisor PC-high register storage
GS $D64A CPU:HTRAP0A @HTRAPXX
GS $D64A HCPU:MAPLO0 Hypervisor MAPLO register storage (high bits)
GS $D64B CPU:HTRAP0B @HTRAPXX
GS $D64B HCPU:MAPLO1 Hypervisor MAPLO register storage (low bits)
GS $D64C CPU:HTRAP0C @HTRAPXX
GS $D64C HCPU:MAPHI0 Hypervisor MAPHI register storage (high bits)
GS $D64D CPU:HTRAP0D @HTRAPXX
GS $D64D HCPU:MAPHI1 Hypervisor MAPHI register storage (low bits)
GS $D64E CPU:HTRAP0E @HTRAPXX
GS $D64E HCPU:MAPLOMB Hypervisor MAPLO mega-byte number register storage
GS $D64F CPU:HTRAP0F @HTRAPXX
GS $D64F HCPU:MAPHIMB Hypervisor MAPHI mega-byte number register storage
GS $D650 CPU:HTRAP10 @HTRAPXX
GS $D650 HCPU:PORT00 Hypervisor CPU port \$00 value
GS $D651 CPU:HTRAP11 @HTRAPXX
GS $D651 HCPU:PORT01 Hypervisor CPU port \$01 value
GS $D652.0-1 HCPU:VICMODE VIC-II/VIC-III/VIC-IV mode select
GS $D652.2 HCPU:EXSID 0=Use internal SIDs, 1=Use external(1) SIDs
GS $D652 CPU:HTRAP12 @HTRAPXX
GS $D652 - Hypervisor VIC-IV IO mode
GS $D653 CPU:HTRAP13 @HTRAPXX
GS $D653 HCPU:DMASRCMB Hypervisor DMAgic source MB
GS $D654 CPU:HTRAP14 @HTRAPXX
GS $D654 HCPU:DMADSTMB Hypervisor DMAgic destination MB
GS $D655 CPU:HTRAP15 @HTRAPXX
GS $D655 HCPU:DMALADDR0 Hypervisor DMAGic list address bits 0-7
GS $D656 CPU:HTRAP16 @HTRAPXX
GS $D656 HCPU:DMALADDR1 Hypervisor DMAGic list address bits 15-8
GS $D657 CPU:HTRAP17 @HTRAPXX
GS $D657 HCPU:DMALADDR2 Hypervisor DMAGic list address bits 23-16
GS $D658 CPU:HTRAP18 @HTRAPXX
GS $D658 HCPU:DMALADDR3 Hypervisor DMAGic list address bits 27-24
GS $D659.0 HCPU:VFLOP0 1=Virtualise SD/Floppy0 access (usually for access via serial debugger interface)
GS $D659.1 HCPU:VFLOP1 1=Virtualise SD/Floppy1 access (usually for access via serial debugger interface)
GS $D659 CPU:HTRAP19 @HTRAPXX
GS $D659 - Hypervisor virtualise hardware flags
GS $D65A CPU:HTRAP1A @HTRAPXX
GS $D65B CPU:HTRAP1B @HTRAPXX
GS $D65C CPU:HTRAP1C @HTRAPXX
GS $D65D.0-3 HCPU:VPG!DIRTY Hypervisor page dirty
GS $D65D.4 HCPU:VPG!ACTIVE Hypervisor page active
GS $D65D.6-7 HCPU:VIRT!PAGE0 Hypervisor current virtual page number (bits 0 - 1)
GS $D65D CPU:HTRAP1D @HTRAPXX
GS $D65E CPU:HTRAP1E @HTRAPXX
GS $D65E HCPU:VIRTPAGE1 Hypervisor current virtual page number (bits 2 - 9)
GS $D65F CPU:HTRAP1F @HTRAPXX
GS $D65F HCPU:VIRTPAGE2 Hypervisor current virtual page number (bits 10 - 17)
GS $D660 CPU:HTRAP20 @HTRAPXX
GS $D660 HCPU:VPG0LOG0@VPGXLOG0 Hypervisor virtual memory page X logical page (bits 0 - 7)
GS $D661 CPU:HTRAP21 @HTRAPXX
GS $D661 HCPU:VPG0LOG1@VPGXLOG1 Hypervisor virtual memory page X logical page (bits 8 - 15)
GS $D662 CPU:HTRAP22 @HTRAPXX
GS $D662 HCPU:VPG0PHY0@VPGXPHY0 Hypervisor virtual memory page X physical page (bits 0 - 7)
GS $D663 CPU:HTRAP23 @HTRAPXX
GS $D663 HCPU:VPG0PHY1@VPGXPHY1 Hypervisor virtual memory page X physical page (bits 8 - 15)
GS $D664 CPU:HTRAP24 @HTRAPXX
GS $D664 HCPU:VPG1LOG0 @VPGXLOG0
GS $D665 CPU:HTRAP25 @HTRAPXX
GS $D665 HCPU:VPG1LOG1 @VPGXLOG1
GS $D666 CPU:HTRAP26 @HTRAPXX
GS $D666 HCPU:VPG1PHY0 @VPGXPHY0
GS $D667 CPU:HTRAP27 @HTRAPXX
GS $D667 HCPU:VPG1PHY0 @VPGXPHY1
GS $D668 CPU:HTRAP28 @HTRAPXX
GS $D668 HCPU:VPG2LOG0 @VPGXLOG0
GS $D669 CPU:HTRAP29 @HTRAPXX
GS $D669 HCPU:VPG2LOG1 @VPGXLOG1
GS $D66A CPU:HTRAP2A @HTRAPXX
GS $D66A HCPU:VPG2PHY0 @VPGXPHY0
GS $D66B CPU:HTRAP2B @HTRAPXX
GS $D66B HCPU:VPG2PHY0 @VPGXPHY1
GS $D66C CPU:HTRAP2C @HTRAPXX
GS $D66C HCPU:VPG3LOG0 @VPGXLOG0
GS $D66D CPU:HTRAP2D @HTRAPXX
GS $D66D HCPU:VPG3LOG1 @VPGXLOG1
GS $D66E CPU:HTRAP2E @HTRAPXX
GS $D66E HCPU:VPG3PHY0 @VPGXPHY0
GS $D66F CPU:HTRAP2F @HTRAPXX
GS $D66F HCPU:VPG3PHY0 @VPGXPHY1
GS $D670 CPU:HTRAP30 @HTRAPXX
GS $D670 HCPU:GEORAMBASE Hypervisor GeoRAM base address (x MB)
GS $D671 CPU:HTRAP31 @HTRAPXX
GS $D671 HCPU:GEORAMMASK Hypervisor GeoRAM address mask (applied to GeoRAM block register)
GS $D672.6 HCPU:MATRIXEN Enable composited Matrix Mode, and disable UART access to serial monitor.
GS $D672 CPU:HTRAP32 @HTRAPXX
GS $D672 - Protected Hardware configuration
GS $D673 CPU:HTRAP33 @HTRAPXX
GS $D674 CPU:HTRAP34 @HTRAPXX
GS $D675 CPU:HTRAP35 @HTRAPXX
GS $D676 CPU:HTRAP36 @HTRAPXX
GS $D677 CPU:HTRAP37 @HTRAPXX
GS $D678 CPU:HTRAP38 @HTRAPXX
GS $D679 CPU:HTRAP39 @HTRAPXX
GS $D67A CPU:HTRAP3A @HTRAPXX
GS $D67B CPU:HTRAP3B @HTRAPXX
GS $D67C.0-7 HCPU:UARTDATA (write) Hypervisor write serial output to UART monitor
GS $D67C.6 (read) Hypervisor internal immediate UART monitor busy flag (can write when 0)
GS $D67C.7 (read) Hypervisor serial output from UART monitor busy flag (can write when 0)
GS $D67C CPU:HTRAP3C @HTRAPXX
GS $D67D.0 HCPU:RSVD RESERVED
GS $D67D.1 HCPU:JMP32EN Hypervisor enable 32-bit JMP/JSR etc
GS $D67D.2 HCPU:ROMPROT Hypervisor write protect C65 ROM \$20000-\$3FFFF
GS $D67D.3 HCPU:ASCFAST Hypervisor enable ASC/DIN CAPS LOCK key to enable/disable CPU slow-down in C64/C128/C65 modes
GS $D67D.4 HCPU:CPUFAST Hypervisor force CPU to 48MHz for userland (userland can override via POKE0)
GS $D67D.5 HCPU:F4502 Hypervisor force CPU to 4502 personality, even in C64 IO mode.
GS $D67D.6 HCPU:PIRQ Hypervisor flag to indicate if an IRQ is pending on exit from the hypervisor / set 1 to force IRQ/NMI deferal for 1,024 cycles on exit from hypervisor.
GS $D67D.7 HCPU:PNMI Hypervisor flag to indicate if an NMI is pending on exit from the hypervisor.
GS $D67D CPU:HTRAP3D @HTRAPXX
GS $D67D HCPU:WATCHDOG Hypervisor watchdog register: writing any value clears the watch dog
GS $D67E.5 (read) Hypervisor read /GAME signal from cartridge.
GS $D67E.6 (read) Hypervisor read /EXROM signal from cartridge.
GS $D67E.7 (read) Hypervisor upgraded flag. Writing any value here sets this bit until next power on (i.e., it surives reset).
GS $D67E CPU:HTRAP3E @HTRAPXX
GS $D67E HCPU:HICKED Hypervisor already-upgraded bit (writing sets permanently)
GS $D67F CPU:HTRAP3F @HTRAPXX
GS $D67F HCPU:ENTEREXIT Writing trigger return from hypervisor
GS $D680.0 - SD controller SDIO BUSY flag
GS $D680.1 - SD controller SDCARD BUSY flag
GS $D680.2 - SD controller RESET flag
GS $D680.3 - SD controller sector buffer mapped flag
GS $D680.4 - SD controller SDHC mode flag
GS $D680.5 - SD controller SDIO FSM ERROR flag
GS $D680.6 - SD controller SDIO error flag
GS $D680.7 - SD controller primary / secondary SD card
GS $D680 SD:CMDANDSTAT SD controller status/command
GS $D681-$D684 - SD controller SD sector address
GS $D681 SD:SECTOR0 SD controller SD sector address (LSB)
GS $D682 SD:SECTOR1 SD controller SD sector address (2nd byte)
GS $D683 SD:SECTOR2 SD controller SD sector address (3rd byte)
GS $D684 SD:SECTOR3 SD controller SD sector address (MSB)
GS $D685 - DEBUG Show current state ID of SD card interface
GS $D686 - DEBUG SD card data token
GS $D686 SD:FILLVAL WRITE ONLY set fill byte for use in fill mode, instead of SD buffer data
GS $D687 - DEBUG SD card most recent byte read
GS $D688 - Low-byte of F011 buffer pointer (disk side) (read only)
GS $D689.0 - High bit of F011 buffer pointer (disk side) (read only)
GS $D689.0 SD:BUFBIT8 (read only) reads bit 8 of the sector buffer pointer
GS $D689.1 SD:BUFFFULL (read only) if set, indicates that the sector buffer is full and has not yet been read
GS $D689.1 - Sector read from SD/F011/FDC, but not yet read by CPU (i.e., EQ and DRQ)
GS $D689.2 - (read only, debug) sd_handshake signal.
GS $D689.2 SD:HNDSHK Set/read SD card sd_handshake signal
GS $D689.3 - (read only, debug) sd_data_ready signal.
GS $D689.3 SD:DRDY SD Card Data Ready indication
GS $D689.4 - RESERVED
GS $D689.4 SD:RESERVED Reserved
GS $D689.5 - F011 swap drive 0 / 1
GS $D689.5 SD:FDCSWAP Set to swap floppy drive 0 (the internal drive) and drive 1 (the drive on the 2nd position on the internal floppy cable).
GS $D689.6 - QSPI bytes not all identical during last read
GS $D689.7 - Memory mapped sector buffer select: 1=SD-Card, 0=F011/FDC
GS $D689.7 SD:BUFFSEL Set to switch sector buffer to view SD card direct access, clear for access to the F011 FDC sector buffer.
GS $D68A.0 SD:CDC00 (read only) Set if colour RAM at $DC00
GS $D68A.1 SD:VICIII (read only) Set if VIC-IV or ethernet IO bank visible
GS $D68A.2 SD:VFDC0 (read only) Set if drive 0 is virtualised (sectors delivered via serial monitor interface)
GS $D68A.3 SD:VFDC1 (read only) Set if drive 1 is virtualised (sectors delivered via serial monitor interface)
GS $D68A.6 SDFDC:D0D64 F011 drive 0 disk image is D64 if set, otherwise D81 (also see SDFDC:D0MD)
GS $D68A.7 SDFDC:D1D64 F011 drive 1 disk image is D64 if set, otherwise D81 (also see SDFDC:D1MD)
GS $D68A - DEBUG check signals that can inhibit sector buffer mapping
GS $D68B.0 - F011 drive 0 disk image enable
GS $D68B.0 SDFDC:D0IMG F011 drive 0 use disk image if set, otherwise use real floppy drive.
GS $D68B.1 - F011 drive 0 present
GS $D68B.1 SDFDC:D0P F011 drive 0 media present
GS $D68B.2 - F011 drive 0 write protect
GS $D68B.2 SDFDC:D0WP Write enable F011 drive 0
GS $D68B.3 SDFDC:D1IMG F011 drive 1 use disk image if set, otherwise use real floppy drive.
GS $D68B.4 SDFDC:D1P F011 drive 1 media present
GS $D68B.5 SDFDC:D1WP Write enable F011 drive 1
GS $D68B.6 F011:MDISK0 Enable D65 ``MEGA Disk'' for F011 emulated drive 0
GS $D68B.6 SDFDC:D0MD F011 drive 0 disk image is D65 if set, otherwise D81 (also see SDFDC:D0D64)
GS $D68B.7 F011:MDISK0 Enable D65 ``MEGA Disk'' for F011 emulated drive 1
GS $D68B.7 SDFDC:D1MD F011 drive 1 disk image is D65 if set, otherwise D81 (also see SDFDC:D1D64)
GS $D68B - Diskimage control flags
GS $D68B - F011 emulation control register
GS $D68C-$D68F - F011 drive 0 disk image address on SD card
GS $D68C F011:DISKADDR0 Diskimage sector number (bits 0-7)
GS $D68C SDFDC:D0STARTSEC0 F011 drive 0 disk image address on SD card (LSB)
GS $D68D F011:DISKADDR1 Diskimage sector number (bits 8-15)
GS $D68D SDFDC:D0STARTSEC1 F011 drive 0 disk image address on SD card (2nd byte)
GS $D68E F011:DISKADDR2 Diskimage sector number (bits 16-23)
GS $D68E SDFDC:D0STARTSEC2 F011 drive 0 disk image address on SD card (3rd byte)
GS $D68F F011:DISKADDR3 Diskimage sector number (bits 24-31)
GS $D68F SDFDC:D0STARTSEC3 F011 drive 0 disk image address on SD card (MSB)
GS $D690-$D693 - F011 drive 1 disk image address on SD card
GS $D690 F011:DISK2ADDR0 Diskimage 2 sector number (bits 0-7)
GS $D690 SDFDC:D1STARTSEC0 F011 drive 1 disk image address on SD card (LSB)
GS $D691 F011:DISK2ADDR1 Diskimage 2 sector number (bits 8-15)
GS $D691 SDFDC:D1STARTSEC1 F011 drive 1 disk image address on SD card (2nd byte)
GS $D692 F011:DISK2ADDR2 Diskimage 2 sector number (bits 16-23)
GS $D692 SDFDC:D1STARTSEC2 F011 drive 1 disk image address on SD card (3rd byte)
GS $D693 F011:DISK2ADDR3 Diskimage 2 sector number (bits 24-31)
GS $D693 SDFDC:D1STARTSEC3 F011 drive 1 disk image address on SD card (MSB)
GS $D696 F011:AUTOTUNE Enable automatic track seeking for sector reads and writes
GS $D697.0 AUTOIEC:IRQTOEN Enable timeout interrupt source if set
GS $D697.1 AUTOIEC:IRQREADYEN Enable TX interrupt source if set
GS $D697.2 AUTOIEC:IRQRXEN Enable RX interrupt source if set
GS $D697.3 AUTOIEC:IRQEN Enable interrupts if set
GS $D697.4 AUTOIEC:IRQTO Set if a protocol timeout has occurred, e.g., device not found.
GS $D697.5 AUTOIEC:IRQREADY Set if ready to process a command
GS $D697.6 AUTOIEC:IRQRX Set if a byte has been received from a listener.
GS $D697.7 AUTOIEC:IRQFLAG Interrupt flag. Set if any IRQ event is triggered.
GS $D698.0 AUTOIEC:STDDIR Data direction when timeout occurred.
GS $D698.1 AUTOIEC:STTO Timeout occurred
GS $D698.2 AUTOIEC:STD State of DATA line
GS $D698.3 AUTOIEC:STC State of CLK line
GS $D698.4 AUTOIEC:STVERIFY Verify error occurred
GS $D698.5 AUTOIEC:STSRQ State of SRQ line
GS $D698.6 AUTOIEC:STNOEOI End of Indicate (EOI/EOF)
GS $D698.7 AUTOIEC:STNODEV Device not present
GS $D699 AUTOIEC:DATA Data byte read from IEC bus
GS $D69A.0-3 AUTOIEC:DIDEVNUM Lower 4 bits of currently selected device number
GS $D69A.4 AUTOIEC:DIATN Device is currently held under attention
GS $D69A.5-6 AUTOIEC:DIPROT Device protocol support (5=C128/C65 FAST, bit 6 = JiffyDOS(tm))
GS $D69A.7 AUTOIEC:DIPRESENT Device is present
GS $D69B DEBUG:J21INL Status of M65 R3 J21 pins
GS $D69C DEBUG:J21INH Status of M65 R3 J21 pins
GS $D69D.0-4 DEBUG:DIPSW Status of M65 R3/R3A/R4 DIP switches
GS $D69D.5-7 DEBUG:DIPSWHI Status of M65 R5 DIP switches
GS $D69E DEBUG:SWSTATUS Status of switches 0 to 7
GS $D69F DEBUG:SWSTATUS Status of switches 8 to 15
GS $D6A0.0 FDC:DBGWGATE Control floppy drive SIDE1 line
GS $D6A0.1 FDC:DBGWGATE Control floppy drive WGATE line
GS $D6A0.2 FDC:DBGWDATA Control floppy drive WDATA line
GS $D6A0 - 3.5" FDC control line debug access
GS $D6A0.3 FDC:DBGDIR Control floppy drive STEP line
GS $D6A0.4 FDC:DBGDIR Control floppy drive STEPDIR line
GS $D6A0.5 FDC:DBGMOTORA Control floppy drive SELECT line
GS $D6A0.6 FDC:DBGMOTORA Control floppy drive MOTOR line
GS $D6A0.7 FDC:DENSITY Control floppy drive density select line
GS $D6A0 - DEBUG FDC read status lines
GS $D6A1.0 F011:DRV0EN Use real floppy drive instead of SD card for 1st floppy drive
GS $D6A1.0 SDFDC:USEREAL0 Use real floppy drive for drive 0 if set (read-only, except for from hypervisor)
GS $D6A1.1 - Match any sector on a real floppy read/write
GS $D6A1.1 SDFDC:TARGANY Read next sector under head if set, ignoring the requested side, track and sector number.
GS $D6A1.2 F011:DRV2EN Use real floppy drive instead of SD card for 2nd floppy drive
GS $D6A1.2 SDFDC:USEREAL1 Use real floppy drive for drive 1 if set (read-only, except for from hypervisor)
GS $D6A1.3 SDFDC:SILENT Disable floppy spinning and tracking for SD card operations.
GS $D6A1.4-7 F011:STATUS FDC debug status flags
GS $D6A2 - FDC clock cycles per MFM data bit
GS $D6A2 FDC:DATARATE Set number of bus cycles per floppy magnetic interval (decrease to increase data rate)
GS $D6A3 - FDC track number of last matching sector header
GS $D6A4 - FDC sector number of last matching sector header
GS $D6A5 - FDC side number of last matching sector header
GS $D6A6 - SD:TITRACK Track number from track info block (or $FF if not yet received)
GS $D6A7 - SD:TIRATE Track data rate from track info block
GS $D6A8 - SD:TIENCODING Track encoding from track info block ($x1 = RLL2,7, $x0 = MFM, $4x = track-at-once, $0x = individually writable sectors)
GS $D6A9 - SD:TISECTORS Number of sectors from track info block
GS $D6AA - DEBUG FDC last gap interval (LSB)
GS $D6AB - DEBUG FDC last gap interval (MSB)
GS $D6AC.0-3 MISCIO:WHEEL3TARGET Select audio channel volume to be set by thumb wheel #3
GS $D6AC.4-6 - PHONE:RESERVED
GS $D6AC.7 MISCIO:WHEELBRIGHTEN Enable control of LCD panel brightness via thumb wheel
GS $D6AD.0-3 MISCIO:WHEEL1TARGET Select audio channel volume to be set by thumb wheel #1
GS $D6AD.0-3 - PHONE:Volume knob 1 audio target
GS $D6AD.4-7 MISCIO:WHEEL2TARGET Select audio channel volume to be set by thumb wheel #2
GS $D6AD.4-7 - PHONE:Volume knob 2 audio target
GS $D6AE.0-3 SD:FDC!ENC Select floppy encoding (0=MFM, 1=RLL2,7, F=Raw encoding)
GS $D6AE.4 SD:AUTO!2XSEL Automatically select DD or HD decoder for last sector display
GS $D6AE.5 SD:FDC!VARSPD Enable automatic variable speed selection for floppy controller using Track Information Blocks on MEGA65 HD floppies
GS $D6AE.6 SD:FDC!2XSEL Select HD decoder for last sector display
GS $D6AE.7 SD:FDC!TIBEN Enable use of Track Info Block settings
GS $D6AF.0 SD:VR!FOUND Manually set f011_rsector_found signal (indented for virtual F011 mode only)
GS $D6AF.1 SD:VW!FOUND Manually set f011_wsector_found signal (indented for virtual F011 mode only)
GS $D6AF.2 SD:VEQ!INH Manually set f011_eq_inhibit signal (indented for virtual F011 mode only)
GS $D6AF.3 SD:VRNF Manually set f011_rnf signal (indented for virtual F011 mode only)
GS $D6AF.4 SD:VDRQ Manually set f011_drq signal (indented for virtual F011 mode only)
GS $D6AF.5 SD:VLOST Manually set f011_lost signal (indented for virtual F011 mode only)
GS $D6AF - DEBUG FDC last quantised gap READ ONLY
GS $D6AF - Directly set F011 flags (intended for virtual F011 mode) WRITE ONLY
GS $D6B0.0 TOUCH:EV1 Touch event 1 is valid
GS $D6B0.1 TOUCH:EV2 Touch event 2 is valid
GS $D6B0.2-3 TOUCH:UPDN1 Touch event 1 up/down state
GS $D6B0.5-4 TOUCH:UPDN2 Touch event 2 up/down state
GS $D6B0.6 MISCIO:TCHFLX Flip X axis of touch interface if set
GS $D6B0.6 TOUCH:XINV Invert horizontal axis
GS $D6B0.7 MISCIO:TCHFLX Flip Y axis of touch interface if set
GS $D6B0.7 TOUCH:YINV Invert vertical axis
GS $D6B0 - Touch pad control / status
GS $D6B1 MISCIO:TCHXSCALE Set X scale value for touch interface (LSB)
GS $D6B1 TOUCH:CALXSCALELSB Touch pad X scaling LSB
GS $D6B2 MISCIO:TCHXSCALE Set X scale value for touch interface (MSB)
GS $D6B2 TOUCH:CALXSCALEMSB Touch pad X scaling MSB
GS $D6B3 MISCIO:TCHYSCALE Set Y scale value for touch interface (LSB)
GS $D6B3 TOUCH:CALYSCALELSB Touch pad Y scaling LSB
GS $D6B4 MISCIO:TCHYSCALE Set Y scale value for touch interface (MSB)
GS $D6B4 TOUCH:CALYSCALEMSB Touch pad Y scaling MSB
GS $D6B5 MISCIO:TCHXDELTA Set X delta value for touch interface (LSB)
GS $D6B5 TOUCH:CALXDELTALSB Touch pad X delta LSB
GS $D6B6 TOUGH:CALXDELTAMSB Touch pad X delta MSB
GS $D6B7 MISCIO:TCHYDELTA Set Y delta value for touch interface (LSB)
GS $D6B7 TOUCH:CALYDELTALSB Touch pad Y delta LSB
GS $D6B8 MISCIO:TCHYDELTA Set Y delta value for touch interface (MSB)
GS $D6B8 TOUCH:CALYDELTAMSB Touch pad Y delta MSB
GS $D6B9 TOUCH:TOUCH1XLSB Touch pad touch #1 X LSB
GS $D6BA TOUCH:TOUCH1YLSB Touch pad touch #1 Y LSB
GS $D6BB.0-1 TOUCH:TOUCH1XMSB Touch pad touch \#1 X MSBs
GS $D6BB.5-4 TOUCH:TOUCH1YMSB Touch pad touch \#1 Y MSBs
GS $D6BB MISCIO:TCHXDELTA Set X delta value for touch interface (MSB)
GS $D6BC TOUCH:TOUCH2XLSB Touch pad touch \#2 X LSB
GS $D6BD TOUCH:TOUCH2YLSB Touch pad touch \#2 Y LSB
GS $D6BE.0-1 TOUCH:TOUCH2XMSB Touch pad touch \#2 X MSBs
GS $D6BE.5-4 TOUCH:TOUCH2YMSB Touch pad touch \#2 Y MSBs
GS $D6BF.0-6 MISCIO:TCHBYTENUM Select byte number for touch panel communications instrumentation
GS $D6BF.7 MISCIO:TCHI2CEN Enable/disable touch panel I2C communications
GS $D6C0.0-3 TOUCH:GESTUREDIR Touch pad gesture directions (left,right,up,down)
GS $D6C0.7-4 TOUCH:GESTUREID Touch pad gesture ID
GS $D6C4 FPGA:REGNUM Select ICAPE2 FPGA configuration register for reading WRITE ONLY
GS $D6C4 FPGA:REGVAL Value of selected ICAPE2 register (least significant byte)
GS $D6C5 FPGA:REGVAL Value of selected ICAPE2 register
GS $D6C6 FPGA:REGVAL Value of selected ICAPE2 register
GS $D6C7 FPGA:REGVAL Value of selected ICAPE2 register (most significant byte)
GS $D6C8-B - Address currently loaded bitstream was fetched from flash memory.
GS $D6C8 FPGA:BOOTADDR0 Address of bitstream in boot flash for reconfiguration (least significant byte)
GS $D6C9 FPGA:BOOTADDR1 Address of bitstream in boot flash for reconfiguration
GS $D6CA FPGA:BOOTADDR2 Address of bitstream in boot flash for reconfiguration
GS $D6CB FPGA:BOOTADDR3 Address of bitstream in boot flash for reconfiguration (most significant byte)
GS $D6CC.0-3 QSPI:DB Data bits for QSPI flash interface (read/write)
GS $D6CC.4 QSPI:RESERVED (set to 0)
GS $D6CC.5 QSPI:CLOCK Clock output line for QSPI flash
GS $D6CC.6 QSPI:CSN Active-low chip-select for QSPI flash
GS $D6CC.7 QSPI:TRI Tristate DB0-3
GS $D6CD.0 QSPI:CLOCKRUN Set to cause QSPI clock to free run at CPU clock frequency.
GS $D6CD.1 QSPI:CLOCK Alternate address for direct manipulation of QSPI CLOCK
GS $D6CF FPGA:RECONFTRIG Write $42 to Trigger FPGA reconfiguration to switch to alternate bitstream.
GS $D6D0 MISC:I2CBUSSELECT I2C bus select (bus 0 = temp sensor on Nexys4 boardS)
GS $D6D0 MISCIO:I2CBUSSEL Select I2C bus number (I2C busses vary between MEGA65 and MEGAphone variants)
GS $D6D1.0 MISCIO:I2CRST I2C reset
GS $D6D1.1 MISCIO:I2CL I2C command latch write strobe (write 1 to trigger command)
GS $D6D1.2 MISCIO:I2CRW I2C Select read (1) or write (0)
GS $D6D1.5 MISCIO:I2CSW I2C bus 1 swap SDA/SCL pins
GS $D6D1.6 MISCIO:I2CBSY I2C busy flag
GS $D6D1.7 MISCIO:I2CERR I2C ack error
GS $D6D1 - I2C control/status
GS $D6D2.7-1 MISCIO:I2CADDR I2C address
GS $D6D3 MISCIO:I2CWDATA I2C data write register
GS $D6D4 MISCIO:I2CRDATA I2C data read register
GS $D6DA MISC:SDDEBUGERRLSB DEBUG SD card last error code LSB
GS $D6DB MISC:SDDEBUGERRMSB DEBUG SD card last error code MSB
GS $D6DE FPGA:FPGATEMPLSB FPGA die temperature sensor (lower nybl)
GS $D6DF FPGA:FPGATEMPMSB FPGA die temperature sensor (upper byte)
GS $D6E0.0 Clear to reset ethernet PHY and state machine
GS $D6E0.0 ETH:RST Write 0 to hold ethernet controller under reset
GS $D6E0.1 Clear to reset ethernet state machine only, but not the phy
GS $D6E0.1 ETH:TXRST Write 0 to hold ethernet controller transmit sub-system under reset
GS $D6E0.2 ETH:DRXD Read ethernet RX bits currently on the wire
GS $D6E0.3 ETH:DRXDV Read ethernet RX data valid (debug)
GS $D6E0.4 ETH:RCENABLED (read only) Ethernet remote control enable status
GS $D6E0.6 ETH:RXBLKD Indicate if ethernet RX is blocked until RX buffers freed
GS $D6E0.7 ETH:TXIDLE Ethernet transmit side is idle, i.e., a packet can be sent.
GS $D6E1.0 RESERVED
GS $D6E1.1-2 ETH:RXBF Number of free receive buffers
GS $D6E1.1 WRITE ONLY Access next received ethernet frame
GS $D6E1.2 WRITE ONLY Enable real-time CPU/BUS monitoring via ethernet
GS $D6E1.3 Enable real-time video streaming via ethernet (or fast IO bus if CPU/bus monitoring enabled)
GS $D6E1.3 ETH:STRM Enable streaming of CPU instruction stream or VIC-IV display on ethernet
GS $D6E1.4 ETH:TXQ Ethernet TX IRQ status
GS $D6E1.5 ETH:RXQ Ethernet RX IRQ status
GS $D6E1.6 ETH:TXQEN Enable ethernet TX IRQ
GS $D6E1.7 ETH:RXQEN Enable ethernet RX IRQ
GS $D6E1 - Ethernet interrupt and control register
GS $D6E2 ETH:TXSZLSB TX Packet size (low byte)
GS $D6E2 Set low-order size of frame to TX
GS $D6E3 ETH:TXSZMSB TX Packet size (high byte)
GS $D6E3 Set high-order size of frame to TX
GS $D6E4 ETH:COMMAND Ethernet command register (write only)
GS $D6E5.0 Enable of filtering unicast frames if MAC address does not match.
GS $D6E5.0 ETH:NOPROM Ethernet disable promiscuous mode
GS $D6E5.1 Disable CRC checking of broadcast ethernet frames
GS $D6E5.1 ETH:NOCRC Disable CRC check for received packets
GS $D6E5.2-3 Ethernet TX clock phase adjust
GS $D6E5.2-3 ETH:TXPH Ethernet TX clock phase adjust
GS $D6E5.4 Enable accepting of broadcast ethernet frames
GS $D6E5.4 ETH:BCST Accept broadcast frames
GS $D6E5.5 Enable accepting of unicast ethernet frames
GS $D6E5.5 ETH:MCST Accept multicast frames
GS $D6E5.6-7 Ethernet RX clock phase adjust
GS $D6E5.6-7 ETH:RXPH Ethernet RX clock phase adjust
GS $D6E6.0-4 ETH:MIIMREG Ethernet MIIM register number
GS $D6E6.7-5 ETH:MIIMPHY Ethernet MIIM PHY number (use 0 for Nexys4, 1 for MEGA65 r1 PCBs)
GS $D6E7 ETH:MIIMVLSB Ethernet MIIM register value (LSB)
GS $D6E8 ETH:MIIMVMSB Ethernet MIIM register value (MSB)
GS $D6E9 ETH:MACADDR1@MACADDRX Ethernet MAC address