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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
<title>MC6809-MC6809E Microprocessor Programming Manual [M6809PM] - Table Of Contents - Maddes.net</title>
<link rel="stylesheet" type="text/css" media="all" href="css/m6809pm.css">
</head>
<body><div class="text">
<a name="top"></a>
<table border="0"><tr>
<td><a href="https://github.com/M6809-Docs/m6809pm" target="_top">Contact</a></td>
</tr></table>
<hr>
<h1>MC6809-MC6809E 8-Bit Microprocessor Programming Manual [M6809PM/AD]<br>© Motorola Inc., 1981</h1>
<p>Original Issue: March 1, 1981<br>
Reprinted: May 1983</p>
<p>Last update: <a href="#changelog">2024-10-07</a></p>
<ul>
<li><a href="#foreword">Foreword</a></li>
<li><a href="#errata">Errata & Corrections</a></li>
<li><a href="#toc">Table Of Contents</a> (PDF pages 5-10)</li>
<li><a href="#loi">List Of Illustrations</a> (PDF page 10)</li>
<li><a href="#lot">List Of Tables</a> (PDF pages 11-12)</li>
<li><a href="#legal">Legal Stuff</a> (PDF page 220)</li>
<li><a href="#links">Links</a></li>
<li><a href="#changelog">Change log</a></li>
</ul>
<h1><a name="foreword">Foreword</a></h1>
<p>This is the Programming Manual for the 6809 microprocessor from Motorola Inc. (now <a href="http://www.freescale.com/" target="_top">Freescale</a> as of 2006).<br>
It is © Motorola Inc., 1981.<br>
<s>It can be freely obtained as a scanned PDF at <a href="http://www.freescale.com/" target="_top">Freescale's homepage</a> under [Support → ] Documentation → Order Literature (=Literature Distribution Center) → Search for description "6809" and with item status "Active and Archive".</s>
<s>Another download location for M6809PM is the <a href="http://www.bitsavers.org/pdf/motorola/" target="_top">BitSavers.org PDF Document Archive</a>, which also has a copy of the original data sheet.</s>
PDFs are available at the <a href="https://github.com/M6809-Docs/m6809pm" target="_top">M6809PM repo</a> of the M6809 Docs team (M6809PM.rev0_May83.pdf, m6809pm.fsl.ad.rev0.pdf) or at <a href="https://www.maddes.net/files/m6809pm/" target="_top">Maddes.net</a>.<br>
<a href="sections.htm">Sections 1-4</a> plus appendices <a href="appendix_a.htm">A</a>, <a href="appendix_c.htm">C</a>, <a href="appendix_d.htm">D</a>, <a href="appendix_e.htm">E</a> and <a href="appendix_f.htm">F</a> got htmlized, so you can easily search inside the text.
The original layout of the print was kept wherever possible.<br>
Also some additional errata and corrections were made to the text.<br>
If you think there are any legal concerns to this please contact us via the contact link.<br>
And remember: Use all information at your own risk.</p>
<p>Get all html pages as a zip file from the <a href="https://github.com/M6809-Docs/m6809pm" target="_top">M6809PM repo</a> of the M6809 Docs team.</p>
<h1><a name="errata">Errata & Corrections</a></h1>
<p>Errata (fixing incorrect information) are formatted like <span class="errata">this</span>.<br>
Corrections (typos, unambiguousness, readability, etc.) are formatted like <span class="correction">this</span>.<br>
HTMLization errors will just be fixed and listed in the change log at the end of this page.</p>
<h2><a name="errata">Errata</a></h2>
<ul>
<li>Table 4-4:<ul>
<li><a href="sections.htm#tab4-4">PSHU</a> (PDF page 46) - duplicate X, instead of correct S</li>
</ul></li>
<li>Appendix A:<ul>
<li><a href="appendix_a.htm#BGT">BGT</a> (PDF page 63) - formula from description was incompletely negated into easier readable version for operation paragraph (Thanks to <a href="https://github.com/cmarrin" target="_top">Chris Marrin</a>)</li>
<li><a href="appendix_a.htm#BIT">BIT</a> (PDF page 66) - incorrect source form (Thanks to <a href="https://github.com/cmarrin" target="_top">Chris Marrin</a>)</li>
<li><a href="appendix_a.htm#BLE">BLE</a> (PDF page 67) - missing outer parenthesis</li>
<li><a href="appendix_a.htm#DAA">DAA</a> (PDF page 84) - LSN correction checks for H bit (half carry) instead of C bit (Thanks to <a href="https://github.com/cmarrin" target="_top">Chris Marrin</a>)</li>
<li><a href="appendix_a.htm#PSHU">PSHU</a>, <a href="appendix_a.htm#PULU">PULU</a> (PDF pages 102 & 104) - b6 is S instead of U</li>
</ul></li>
<li>Appendix D:<ul>
<li><a href="appendix_d.htm#tabD-1f">ASRA, ASRB</a> (PDF page 205) - instruction forms incorrectly listed (Thanks to <a href="https://alex.kazik.de/" target="_top">Alex</a>)</li>
<li><a href="appendix_d.htm#tabD-1f">LSR, ORB</a> (PDF page 206) - some numbers of MPU Cycles missing (Thanks to <a href="https://alex.kazik.de/" target="_top">Alex</a>)</li>
<li><a href="appendix_d.htm#tabD-1f">SWI3</a> (PDF page 206) - some numbers of Program Bytes missing (Thanks to <a href="https://alex.kazik.de/" target="_top">Alex</a>)</li>
</ul></li>
</ul>
<h2><a name="errata">Corrections</a></h2>
<ul>
<li>Added radix (base) to numbers to show if they are binary "<sub>2</sub>" or hexadecimal "<sub>16</sub>" (may not be 100% yet)</li>
<li>Appendix A:<ul>
<li><a href="appendix_a.htm#BLS">BLS</a> (PDF page 69) - use square parenthesis as in the other operation conditions</li>
</ul></li>
<li>Appendix D:<ul>
<li><a href="appendix_d.htm#noteD-1a">Branch Notes</a> (PDF pages 204 & 206) - moved "5(6)" note up to Branch Instructions (Thanks to <a href="https://alex.kazik.de/" target="_top">Alex</a>)</li>
</ul></li>
</ul>
<h1><a name="toc">Table Of Contents</a></h1>
<p>PDF pages 5-10</p>
<table>
<tr>
<th colspan="5"><a href="sections.htm#sec1">SECTION 1<br>GENERAL DESCRIPTION</a><br>PDF pages 13-24</th>
</tr>
<tr>
<td class="top left">1.1</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_1">Introduction</a></td>
</tr>
<tr>
<td class="top left">1.2</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_2">Features</a></td>
</tr>
<tr>
<td class="top left">1.3</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_3">Software Features</a></td>
</tr>
<tr>
<td class="top left">1.4</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_4">Programming Model</a></td>
</tr>
<tr>
<td class="top left">1.5</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_5">Index Registers (X, Y)</a></td>
</tr>
<tr>
<td class="top left">1.6</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_6">Stack Pointer Registers (U, S)</a></td>
</tr>
<tr>
<td class="top left">1.7</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_7">Program Counter (PC)</a></td>
</tr>
<tr>
<td class="top left">1.8</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_8">Accumulator Registers (A, B, D)</a></td>
</tr>
<tr>
<td class="top left">1.9</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_9">Direct Page Register (DP)</a></td>
</tr>
<tr>
<td class="top left">1.10</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_10">Condition Code Register (CC)</a></td>
</tr>
<tr>
<td class="top left">1.10.1</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_10_1">Condition Code Bits</a></td>
</tr>
<tr>
<td class="top left">1.10.1.1</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_10_1_1">Half Carry (H), Bit 5</a></td>
</tr>
<tr>
<td class="top left">1.10.1.2</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_10_1_2">Negative (N), Bit 3</a></td>
</tr>
<tr>
<td class="top left">1.10.1.3</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_10_1_3">Zero (Z), Bit 2</a></td>
</tr>
<tr>
<td class="top left">1.10.1.4</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_10_1_4">Overflow (V), Bit 1</a></td>
</tr>
<tr>
<td class="top left">1.10.1.5</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_10_1_5">Carry (C), Bit 0</a></td>
</tr>
<tr>
<td class="top left">1.10.2</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_10_2">Interrupt Mask Bits and Stacking Indicator</a></td>
</tr>
<tr>
<td class="top left">1.10.2.1</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_10_2_1">Fast Interrupt Request Mask (F), Bit 6</a></td>
</tr>
<tr>
<td class="top left">1.10.2.2</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_10_2_2">Interrupt Request Mask (I), Bit 4</a></td>
</tr>
<tr>
<td class="top left">1.10.2.3</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_10_2_3">Entire Flag (E), Bit 7</a></td>
</tr>
<tr>
<td class="top left">1.11</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec1_11">Pin Assignments and Signal Description</a></td>
</tr>
<tr>
<td class="top left">1.11.1</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_1">MC6809 Clocks</a></td>
</tr>
<tr>
<td class="top left">1.11.1.1</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_1_1">Oscillator (EXTAL, XTAL)</a></td>
</tr>
<tr>
<td class="top left">1.11.1.2</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_1_2">Enable (E)</a></td>
</tr>
<tr>
<td class="top left">1.11.1.3</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_1_3">Quadrature (Q)</a></td>
</tr>
<tr>
<td class="top left">1.11.2</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_2">MC6809E Clocks (E and Q)</a></td>
</tr>
<tr>
<td class="top left">1.11.3</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_3">Three State Controls (TSC) (MC6809E)</a></td>
</tr>
<tr>
<td class="top left">1.11.4</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_4">Last Instruction Cycle (LIC) (MC6809E)</a></td>
</tr>
<tr>
<td class="top left">1.11.5</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_5">Address Bus (A0-A15)</a></td>
</tr>
<tr>
<td class="top left">1.11.6</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_6">Data Bus (D0-D7)</a></td>
</tr>
<tr>
<td class="top left">1.11.7</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_7">Read/Write (R/<span class="lowsignal">W</span>)</a></td>
</tr>
<tr>
<td class="top left">1.11.8</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_8">Processor State Indicators (BA, BS)</a></td>
</tr>
<tr>
<td class="top left">1.11.8.1</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_8_1">Normal</a></td>
</tr>
<tr>
<td class="top left">1.11.8.2</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_8_2">Interrupt or Reset Acknowledge</a></td>
</tr>
<tr>
<td class="top left">1.11.8.3</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_8_3">Sync Acknowledge</a></td>
</tr>
<tr>
<td class="top left">1.11.8.4</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_8_4">Halt/Bus Grant</a></td>
</tr>
<tr>
<td class="top left">1.11.9</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_9">Reset (<span class="lowsignal">RESET</span>)</a></td>
</tr>
<tr>
<td class="top left">1.11.10</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_10">Interrupts</a></td>
</tr>
<tr>
<td class="top left">1.11.10.1</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_10_1">Non-Maskable Interrupt (<span class="lowsignal">NMI</span>)</a></td>
</tr>
<tr>
<td class="top left">1.11.10.2</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_10_2">Fast Interrupt Request (<span class="lowsignal">FIRQ</span>)</a></td>
</tr>
<tr>
<td class="top left">1.11.10.3</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec1_11_10_3">Interrupt Request (<span class="lowsignal">IRQ</span>)</a></td>
</tr>
<tr>
<td class="top left">1.11.11</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_11">Memory Read (MRDY) (MC6809)</a></td>
</tr>
<tr>
<td class="top left">1.11.12</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_12">Advanced Valid Memory Address (AVMA) (MC6809E)</a></td>
</tr>
<tr>
<td class="top left">1.11.13</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_13">Halt (HALT)</a></td>
</tr>
<tr>
<td class="top left">1.11.14</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_14">Direct Memory Access/Bus Request (<span class="lowsignal">DMA</span>/<span class="lowsignal">BREQ</span>) (MC6809)</a></td>
</tr>
<tr>
<td class="top left">1.11.15</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_15">Busy (MC6809E)</a></td>
</tr>
<tr>
<td class="top left">1.11.16</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec1_11_16">Power</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5"><a href="sections.htm#sec2">SECTION 2<br>ADDRESSING MODES</a><br>PDF pages 25-30</th>
</tr>
<tr>
<td class="top left">2.1</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec2_1">Introduction</a></td>
</tr>
<tr>
<td class="top left">2.2</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec2_2">Addressing Modes</a></td>
</tr>
<tr>
<td class="top left">2.2.1</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec2_2_1">Inherent</a></td>
</tr>
<tr>
<td class="top left">2.2.2</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec2_2_2">Immediate</a></td>
</tr>
<tr>
<td class="top left">2.2.3</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec2_2_3">Extended</a></td>
</tr>
<tr>
<td class="top left">2.2.4</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec2_2_4">Direct</a></td>
</tr>
<tr>
<td class="top left">2.2.5</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec2_2_5">Indexed</a></td>
</tr>
<tr>
<td class="top left">2.2.5.1</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec2_2_5_1">Constant Offset from Register</a></td>
</tr>
<tr>
<td class="top left">2.2.5.2</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec2_2_5_2">Accumulator Offset from Register</a></td>
</tr>
<tr>
<td class="top left">2.2.5.3</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec2_2_5_3">Autoincrement/Decrement from Register</a></td>
</tr>
<tr>
<td class="top left">2.2.5.4</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec2_2_5_4">Indirection</a></td>
</tr>
<tr>
<td class="top left">2.2.5.5</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec2_2_5_5">Extended Indirect</a></td>
</tr>
<tr>
<td class="top left">2.2.5.6</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec2_2_5_6">Program Counter Relative</a></td>
</tr>
<tr>
<td class="top left">2.2.6</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec2_2_6">Branch Relative</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5"><a href="sections.htm#sec3">SECTION 3<br>INTERRUPT CAPABILITIES</a><br>PDF pages 31-34</th>
</tr>
<tr>
<td class="top left">3.1</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec3_1">Introduction</a></td>
</tr>
<tr>
<td class="top left">3.2</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec3_2">Non-Maskable Interrupt (<span class="lowsignal">NMI</span>)</a></td>
</tr>
<tr>
<td class="top left">3.3</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec3_3">Fast Maskable Interrupt Request (<span class="lowsignal">FIRQ</span>)</a></td>
</tr>
<tr>
<td class="top left">3.4</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec3_4">Normal Maskable Interrupt Request (<span class="lowsignal">IRQ</span>)</a></td>
</tr>
<tr>
<td class="top left">3.5</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec3_5">Software Interrupts (SWI, SWI2, SWI3)</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5"><a href="sections.htm#sec4">SECTION 4<br>PROGRAMMING</a><br>PDF pages 35-48</th>
</tr>
<tr>
<td class="top left">4.1</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec4_1">Introduction</a></td>
</tr>
<tr>
<td class="top left">4.1.1</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_1_1">Position Independence</a></td>
</tr>
<tr>
<td class="top left">4.1.2</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_1_2">Modular Programming</a></td>
</tr>
<tr>
<td class="top left">4.1.2.1</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec4_1_2_1">Local Storage</a></td>
</tr>
<tr>
<td class="top left">4.1.2.2</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec4_1_2_2">Global Storage</a></td>
</tr>
<tr>
<td class="top left">4.1.3</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_1_3">Reentrancy/Recursion</a></td>
</tr>
<tr>
<td class="top left">4.2</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec4_2">M6809 Capabilities</a></td>
</tr>
<tr>
<td class="top left">4.2.1</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_2_1">Module Construction</a></td>
</tr>
<tr>
<td class="top left">4.2.1.1</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec4_2_1_1">Parameters</a></td>
</tr>
<tr>
<td class="top left">4.2.1.2</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec4_2_1_2">Local Storage</a></td>
</tr>
<tr>
<td class="top left">4.2.1.3</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec4_2_1_3">Global Storage</a></td>
</tr>
<tr>
<td class="top left">4.2.2</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_2_2">Position-Independent Code</a></td>
</tr>
<tr>
<td class="top left">4.2.3</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_2_3">Reentrant Programs</a></td>
</tr>
<tr>
<td class="top left">4.2.4</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_2_4">Recursive Programs</a></td>
</tr>
<tr>
<td class="top left">4.2.5</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_2_5">Loops</a></td>
</tr>
<tr>
<td class="top left">4.2.6</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_2_6">Stack Programming</a></td>
</tr>
<tr>
<td class="top left">4.2.6.1</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec4_2_6_1">M6809 Stacking Operations</a></td>
</tr>
<tr>
<td class="top left">4.2.6.2</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec4_2_6_2">Subroutine Linkage</a></td>
</tr>
<tr>
<td class="top left">4.2.6.3</td><td colspan="3"></td><td colspan="1"><a href="sections.htm#sec4_2_6_3">Software Stacks</a></td>
</tr>
<tr>
<td class="top left">4.2.7</td><td colspan="2"></td><td colspan="2"><a href="sections.htm#sec4_2_7">Real Time Programming</a></td>
</tr>
<tr>
<td class="top left">4.3</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec4_3">Program Documentation</a></td>
</tr>
<tr>
<td class="top left">4.4</td><td colspan="1"></td><td colspan="3"><a href="sections.htm#sec4_4">Instruction Set</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5"><a href="appendix_a.htm#appA">APPENDIX A<br>INSTRUCTION SET DETAILS</a><br>PDF pages 49-124</th>
</tr>
<tr>
<td class="top left">A.1</td><td colspan="1"></td><td colspan="3"><a href="appendix_a.htm#appA_1">Introduction</a></td>
</tr>
<tr>
<td class="top left">A.2</td><td colspan="1"></td><td colspan="3"><a href="appendix_a.htm#appA_2">Notation</a><br>
Instructions (listed in alphabetical order)<br>
<table><tr><td width="400">
<a href="appendix_a.htm#ABX">ABX</a>,
<a href="appendix_a.htm#ADC">ADC</a>,
<a href="appendix_a.htm#ADD (8-Bit)">ADD (8-Bit)</a>,
<a href="appendix_a.htm#ADD (16-Bit)">ADD (16-Bit)</a>,
<a href="appendix_a.htm#AND">AND</a>,
<a href="appendix_a.htm#AND">AND (into CCR)</a>,
<a href="appendix_a.htm#ASL">ASL</a>,
<a href="appendix_a.htm#ASR">ASR</a>,
<a href="appendix_a.htm#BCC">BCC</a>,
<a href="appendix_a.htm#BCS">BCS</a>,
<a href="appendix_a.htm#BEQ">BEQ</a>,
<a href="appendix_a.htm#BGE">BGE</a>,
<a href="appendix_a.htm#BGT">BGT</a>,
<a href="appendix_a.htm#BHI">BHI</a>,
<a href="appendix_a.htm#BHS">BHS</a>,
<a href="appendix_a.htm#BIT">BIT</a>,
<a href="appendix_a.htm#BLE">BLE</a>,
<a href="appendix_a.htm#BLO">BLO</a>,
<a href="appendix_a.htm#BLS">BLS</a>,
<a href="appendix_a.htm#BLT">BLT</a>,
<a href="appendix_a.htm#BMI">BMI</a>,
<a href="appendix_a.htm#BNE">BNE</a>,
<a href="appendix_a.htm#BPL">BPL</a>,
<a href="appendix_a.htm#BRA">BRA</a>,
<a href="appendix_a.htm#BRN">BRN</a>,
<a href="appendix_a.htm#BSR">BSR</a>,
<a href="appendix_a.htm#BVC">BVC</a>,
<a href="appendix_a.htm#BVS">BVS</a>,
<a href="appendix_a.htm#CLR">CLR</a>,
<a href="appendix_a.htm#CMP (8-Bit)">CMP (8-Bit)</a>,
<a href="appendix_a.htm#CMP (16-Bit)">CMP (16-Bit)</a>,
<a href="appendix_a.htm#COM">COM</a>,
<a href="appendix_a.htm#CWAI">CWAI</a>,
<a href="appendix_a.htm#DAA">DAA</a>,
<a href="appendix_a.htm#DEC">DEC</a>,
<a href="appendix_a.htm#EOR">EOR</a>,
<a href="appendix_a.htm#EXG">EXG</a>,
<a href="appendix_a.htm#INC">INC</a>,
<a href="appendix_a.htm#JMP">JMP</a>,
<a href="appendix_a.htm#JSR">JSR</a>,
<a href="appendix_a.htm#LD (8-Bit)">LD (8-Bit)</a>,
<a href="appendix_a.htm#LD (16-Bit)">LD (16-Bit)</a>,
<a href="appendix_a.htm#LEA">LEA</a>,
<a href="appendix_a.htm#LSL">LSL</a>,
<a href="appendix_a.htm#LSR">LSR</a>,
<a href="appendix_a.htm#MUL">MUL</a>,
<a href="appendix_a.htm#NEG">NEG</a>,
<a href="appendix_a.htm#NOP">NOP</a>,
<a href="appendix_a.htm#OR">OR</a>,
<a href="appendix_a.htm#OR">OR (into CCR)</a>,
<a href="appendix_a.htm#PSHS">PSHS</a>,
<a href="appendix_a.htm#PSHU">PSHU</a>,
<a href="appendix_a.htm#PULS">PULS</a>,
<a href="appendix_a.htm#PULU">PULU</a>,
<a href="appendix_a.htm#ROL">ROL</a>,
<a href="appendix_a.htm#ROR">ROR</a>,
<a href="appendix_a.htm#RTI">RTI</a>,
<a href="appendix_a.htm#RTS">RTS</a>,
<a href="appendix_a.htm#SBC">SBC</a>,
<a href="appendix_a.htm#SEX">SEX</a>,
<a href="appendix_a.htm#ST (8-Bit)">ST (8-Bit)</a>,
<a href="appendix_a.htm#ST (16-Bit)">ST (16-Bit)</a>,
<a href="appendix_a.htm#SUB (8-Bit)">SUB (8-Bit)</a>,
<a href="appendix_a.htm#SUB (16-Bit)">SUB (16-Bit)</a>,
<a href="appendix_a.htm#SWI">SWI</a>,
<a href="appendix_a.htm#SWI2">SWI2</a>,
<a href="appendix_a.htm#SWI3">SWI3</a>,
<a href="appendix_a.htm#SYNC">SYNC</a>,
<a href="appendix_a.htm#TFR">TFR</a>,
<a href="appendix_a.htm#TST">TST</a>,
<a href="appendix_a.htm#FIRQ"><span class="lowsignal">FIRQ</span></a>,
<a href="appendix_a.htm#IRQ"><span class="lowsignal">IRQ</span></a>,
<a href="appendix_a.htm#NMI"><span class="lowsignal">NMI</span></a>,
<a href="appendix_a.htm#RESTART">RESTART</a>
</td></tr></table>
</td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5">APPENDIX B<br>ASSIST09 MONITOR PROGRAM<br>PDF pages 125-198</th>
</tr>
<tr>
<td colspan="5" class="top left">Appendix B will not be htmlized.</td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5"><a href="appendix_c.htm#appC">APPENDIX C<br>MACHINE CODE TO INSTRUCTION CROSS REFERENCE</a><br>PDF pages 199-202</th>
</tr>
<tr>
<td class="top left">C.1</td><td colspan="1"></td><td colspan="3"><a href="appendix_c.htm#appC_1">Introduction</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5"><a href="appendix_d.htm#appD">APPENDIX D<br>PROGRAMMING AID</a><br>PDF pages 203-206</th>
</tr>
<tr>
<td class="top left">D.1</td><td colspan="1"></td><td colspan="3"><a href="appendix_d.htm#appD_1">Introduction</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5"><a href="appendix_e.htm#appE">APPENDIX E<br>ASCII CHARACTER SET</a><br>PDF pages 207-210</th>
</tr>
<tr>
<td class="top left">E.1</td><td colspan="1"></td><td colspan="3"><a href="appendix_e.htm#appE_1">Introduction</a></td>
</tr>
<tr>
<td class="top left">E.2</td><td colspan="1"></td><td colspan="3"><a href="appendix_e.htm#appE_2">Character Representation and Code Identification</a></td>
</tr>
<tr>
<td class="top left">E.3</td><td colspan="1"></td><td colspan="3"><a href="appendix_e.htm#appE_3">Control Characters</a></td>
</tr>
<tr>
<td class="top left">E.4</td><td colspan="1"></td><td colspan="3"><a href="appendix_e.htm#appE_4">Graphic Characters</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5"><a href="appendix_f.htm#appF">APPENDIX F<br>OPCODE MAP</a><br>PDF pages 211-214</th>
</tr>
<tr>
<td class="top left">F.1</td><td colspan="1"></td><td colspan="3"><a href="appendix_f.htm#appF_1">Introduction</a></td>
</tr>
<tr>
<td class="top left">F.2</td><td colspan="1"></td><td colspan="3"><a href="appendix_f.htm#appF_2">Opcode Map</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5">APPENDIX G<br>PIN ASSIGNMENTS<br>PDF pages 215-216</th>
</tr>
<tr>
<td colspan="5" class="top left">Appendix G will not be htmlized. Same figure as in <a href="sections.htm#sec1_11">section 1.11</a>.</td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<th colspan="5">APPENDIX H<br>CONVERSION TABLE<br>PDF pages 217-219</th>
</tr>
<tr>
<td colspan="5" class="top left">Appendix H will not be htmlized.</td>
</tr>
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<tr>
<td class="top left"></td><td></td><td></td><td></td><td></td>
</tr>
</table>
<h1><a name="loi">List Of Illustrations</a></h1>
<p>PDF page 10</p>
<table>
<tr>
<td class="top left">1-1</td><td></td><td><a href="sections.htm#fig1-1">Programming Model</a></td>
</tr>
<tr>
<td class="top left">1-2</td><td></td><td><a href="sections.htm#fig1-2">Condition Code Register</a></td>
</tr>
<tr>
<td class="top left">1-3</td><td></td><td><a href="sections.htm#fig1-3">Processor Pin Assignments</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">2-1</td><td></td><td><a href="sections.htm#fig2-1">Postbyte Usage for EXG/TFR, PSH/PUL Instructions</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">3-1</td><td></td><td><a href="sections.htm#fig3-1">Interrupt Processing Flowchart</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">4-1</td><td></td><td><a href="sections.htm#fig4-1">Stacking Order</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">B-1</td><td></td><td>Appendix B will not be htmlized.</td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">E-1</td><td></td><td><a href="appendix_e.htm#figE-1">ASCII Character Set</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">G-1</td><td></td><td>Appendix G will not be htmlized. Same figure as in <a href="sections.htm#sec1_11">section 1.11</a>.</td>
</tr>
</table>
<h1><a name="lot">List Of Tables</a></h1>
<p>PDF pages 11-12</p>
<table>
<tr>
<td class="top left">1-1</td><td></td><td><a href="sections.htm#tab1-1">BA/BS Signal Encoding</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">2-1</td><td></td><td><a href="sections.htm#tab2-1">Postbyte Usage for Indexed Addressing Modes</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">3-1</td><td></td><td><a href="sections.htm#tab3-1">Interrupt Vector Locations</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">4-1</td><td></td><td><a href="sections.htm#tab4-1">Instruction Set</a></td>
</tr>
<tr>
<td class="top left">4-2</td><td></td><td><a href="sections.htm#tab4-2">8-Bit Accumulator and Memory Instructions</a></td>
</tr>
<tr>
<td class="top left">4-3</td><td></td><td><a href="sections.htm#tab4-3">16-Bit Accumulator and Memory Instructions</a></td>
</tr>
<tr>
<td class="top left">4-4</td><td></td><td><a href="sections.htm#tab4-4">Index/Stack Pointer Instructions</a></td>
</tr>
<tr>
<td class="top left">4-5</td><td></td><td><a href="sections.htm#tab4-5">Branch Instructions</a></td>
</tr>
<tr>
<td class="top left">4-6</td><td></td><td><a href="sections.htm#tab4-6">Miscellaneous Instructions</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">A-1</td><td></td><td><a href="appendix_a.htm#tabA-1">Operation Notation</a></td>
</tr>
<tr>
<td class="top left">A-2</td><td></td><td><a href="appendix_a.htm#tabA-2">Register Notation</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">B-1<br>B-2<br>B-3</td><td></td><td>Appendix B will not be htmlized.</td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">C-1</td><td></td><td><a href="appendix_c.htm#tabC-1">Machine Code to Instruction Cross Reference</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">D-1</td><td></td><td><a href="appendix_d.htm#tabD-1">Programming Aid</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">E-1</td><td></td><td><a href="appendix_e.htm#tabE-1">Control Characters</a></td>
</tr>
<tr>
<td class="top left">E-2</td><td></td><td><a href="appendix_e.htm#tabE-2">Graphic Characters</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">F-1</td><td></td><td><a href="appendix_f.htm#tabF-1">Opcode Map</a></td>
</tr>
<tr>
<td class="top left">F-2</td><td></td><td><a href="appendix_f.htm#tabF-2">Indexed Addressing Mode Data</a></td>
</tr>
<tr>
<td colspan="5"> </td>
</tr>
<tr>
<td class="top left">H-1<br>H-2</td><td></td><td>Appendix H will not be htmlized.</td>
</tr>
</table>
<h1><a name="legal">Legal Stuff</a></h1>
<p>PDF page 220</p>
<p>Motorola reserves the right to make changes without further notice to any products herein.
Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
"Typical" parameters can and do vary in different applications.
All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.
Motorola does not convey any license under its patent rights nor the rights of others.
Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and <img src="gfx/motorola_tm.jpg" width="20" alt="Motorola Logo"> are registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.</p>
<table>
<tr>
<th colspan="2" class="left">Literature Distribution Centers: (as of 1993 = print of manual)</th>
</tr>
<tr>
<td class="top left">USA:</td><td>Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.</td>
</tr>
<tr>
<td class="top left">EUROPE:</td><td>Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.</td>
</tr>
<tr>
<td class="top left">JAPAN:</td><td>Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan.</td>
</tr>
<tr>
<td class="top left">ASIA PACIFIC:</td><td>Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.</td>
</tr>
</table>
<h1><a name="links">Links</a></h1>
<ul>
<li><a href="http://en.wikipedia.org/wiki/Motorola_6809" target="_top">M6809 Wikipedia Article</a></li>
<li><a href="http://www.classiccmp.org/dunfield/d6809/docs.htm" target="_top">Dave's Old Computers</a></li>
<li><a href="http://koti.mbnet.fi/~atjs/mc6809/" target="_top">6809 Emulation Page</a></li>
<li><a href="http://retro.co.za/6809/" target="_top">Wouter's Page</a></li>
<li><a href="http://www.howell1964.freeserve.co.uk/parts/" target="_top">Keith's Home Page</a></li>
</ul>
<h1><a name="changelog">Change log</a></h1>
<ul>
<li>2024-10-07:<br>
Added errata for Appendix A: instruction BIT</li>
<li>2024-05-09:<br>
Updated pages with M6809 Docs team information.<br>
Separated between errata and corrections.<br>
Added PDF page numbers for easier review and/or reference.<br>
Added errata for Appendix A: instruction BGT, BLE</li>
<li>2024-05-04:<br>
Added errata for Appendix A: instruction DAA</li>
<li>2023-08-15:<br>
Appendix C, opcode 21: BRN was wrongly HTMLized as BAN (Thanks to Eric Hood)</li>
<li>2012-09-25:<br>
Appendix D, instruction ORB: byte count 2+ for indexed mode was wrongly HTMLized as 1+<br>
Added errata for Appendix D: instructions ASRA, ASRB, LSR, ORB, SWI3</li>
<li>2008-12-25:<br>
Appendix C, opcode 27: BEQ was wrongly HTMLized as BEG</li>
</ul>
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Maintained by <a href="https://github.com/M6809-Docs/m6809pm" target="_top">the M6809 Docs team</a> in 2024.<br>
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