From 6ef15110d332f4db1085f719294676f1f406dcd7 Mon Sep 17 00:00:00 2001 From: fewtarius Date: Sat, 30 Dec 2023 21:02:14 +0000 Subject: [PATCH 01/35] Add a guard to set_epp so it isn't executed on devices that don't have it available. --- packages/jelos/sources/scripts/runemu.sh | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/packages/jelos/sources/scripts/runemu.sh b/packages/jelos/sources/scripts/runemu.sh index 103a7580b5..c9536ef5aa 100755 --- a/packages/jelos/sources/scripts/runemu.sh +++ b/packages/jelos/sources/scripts/runemu.sh @@ -336,11 +336,14 @@ case ${CPU_VENDOR} in esac ### Apply energy performance preference -EPP=$(get_setting "power.epp" "${PLATFORM}" "${ROMNAME##*/}") -if [ ! -z ${EPP} ] +if [ -e "/usr/bin/set_epp" ] then - ${VERBOSE} && log $0 "Set EPP to (${EPP})" - /usr/bin/set_epp ${EPP} + EPP=$(get_setting "power.epp" "${PLATFORM}" "${ROMNAME##*/}") + if [ ! -z ${EPP} ] + then + ${VERBOSE} && log $0 "Set EPP to (${EPP})" + /usr/bin/set_epp ${EPP} + fi fi ### Configure GPU performance mode From 10c7c11c34a07abf41ef475cf72daf779ae536a3 Mon Sep 17 00:00:00 2001 From: fewtarius Date: Mon, 1 Jan 2024 15:34:14 +0000 Subject: [PATCH 02/35] Update several emulators and cores. --- packages/apps/moonlight/package.mk | 2 +- packages/emulators/libretro/beetle-pce-fast-lr/package.mk | 2 +- packages/emulators/libretro/beetle-pce-lr/package.mk | 2 +- packages/emulators/libretro/beetle-supergrafx-lr/package.mk | 2 +- packages/emulators/libretro/bsnes-lr/package.mk | 2 +- packages/emulators/libretro/cap32-lr/package.mk | 2 +- packages/emulators/libretro/dosbox-pure-lr/package.mk | 2 +- packages/emulators/libretro/fbneo-lr/package.mk | 2 +- packages/emulators/libretro/fceumm-lr/package.mk | 2 +- packages/emulators/libretro/gambatte-lr/package.mk | 2 +- packages/emulators/libretro/gearboy-lr/package.mk | 2 +- packages/emulators/libretro/gearcoleco-lr/package.mk | 2 +- packages/emulators/libretro/gearsystem-lr/package.mk | 2 +- packages/emulators/libretro/genesis-plus-gx-lr/package.mk | 2 +- packages/emulators/libretro/handy-lr/package.mk | 2 +- packages/emulators/libretro/libretro-database/package.mk | 2 +- packages/emulators/libretro/mojozork-lr/package.mk | 2 +- packages/emulators/libretro/mupen64plus-nx-lr/package.mk | 2 +- packages/emulators/libretro/opera-lr/package.mk | 2 +- packages/emulators/libretro/pcsx_rearmed-lr/package.mk | 2 +- packages/emulators/libretro/scummvm-lr/package.mk | 2 +- packages/emulators/libretro/slang-shaders/package.mk | 2 +- packages/emulators/libretro/stella-lr/package.mk | 2 +- packages/emulators/standalone/flycast-sa/package.mk | 2 +- packages/emulators/standalone/gzdoom-sa/package.mk | 2 +- packages/emulators/standalone/hatarisa/package.mk | 2 +- packages/emulators/standalone/openbor/package.mk | 3 ++- packages/emulators/tools/control-gen/package.mk | 2 +- packages/emulators/tools/gamecontrollerdb/package.mk | 2 +- packages/emulators/tools/retroarch-assets/package.mk | 2 +- packages/emulators/tools/retroarch-joypads/package.mk | 2 +- 31 files changed, 32 insertions(+), 31 deletions(-) diff --git a/packages/apps/moonlight/package.mk b/packages/apps/moonlight/package.mk index 99b3ae5150..ed0f64f105 100644 --- a/packages/apps/moonlight/package.mk +++ b/packages/apps/moonlight/package.mk @@ -14,7 +14,7 @@ if [ "${TARGET_ARCH}" = "x86_64" ] then PKG_SITE+="qt" PKG_URL="${PKG_SITE}.git" - PKG_VERSION="8f2db994068757bead7598a8308c9e839be85e8c" + PKG_VERSION="e20d56041ea73a543511385583c580f4c09b21f3" PKG_DEPENDS_TARGET+=" qt5" PKG_TOOLCHAIN="manual" make_target() { diff --git a/packages/emulators/libretro/beetle-pce-fast-lr/package.mk b/packages/emulators/libretro/beetle-pce-fast-lr/package.mk index 6d9e1a57e2..2bf13aa9d3 100644 --- a/packages/emulators/libretro/beetle-pce-fast-lr/package.mk +++ b/packages/emulators/libretro/beetle-pce-fast-lr/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="beetle-pce-fast-lr" -PKG_VERSION="fe662eb161f73749a372657192c7fe234bc8e3ad" +PKG_VERSION="ac1c49539a4b18449b3118835c52d606545bb87a" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPLv2" diff --git a/packages/emulators/libretro/beetle-pce-lr/package.mk b/packages/emulators/libretro/beetle-pce-lr/package.mk index 45fcb75139..da808c870f 100644 --- a/packages/emulators/libretro/beetle-pce-lr/package.mk +++ b/packages/emulators/libretro/beetle-pce-lr/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="beetle-pce-lr" -PKG_VERSION="65977d85040622d15e96b6aa6581e30e6c6829e8" +PKG_VERSION="ae3159b15e303cb7156ca1274353fdf665b31a6d" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPLv2" diff --git a/packages/emulators/libretro/beetle-supergrafx-lr/package.mk b/packages/emulators/libretro/beetle-supergrafx-lr/package.mk index ab96c8d5bd..ac31f2c141 100644 --- a/packages/emulators/libretro/beetle-supergrafx-lr/package.mk +++ b/packages/emulators/libretro/beetle-supergrafx-lr/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="beetle-supergrafx-lr" -PKG_VERSION="47c977c169cd60f1518d64ccf1fc83481bf6e869" +PKG_VERSION="bcf492267f7f112705a82901de0a3e58e8151aa2" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPLv2" diff --git a/packages/emulators/libretro/bsnes-lr/package.mk b/packages/emulators/libretro/bsnes-lr/package.mk index 84e4162e53..2b6fa286e8 100644 --- a/packages/emulators/libretro/bsnes-lr/package.mk +++ b/packages/emulators/libretro/bsnes-lr/package.mk @@ -2,7 +2,7 @@ # Copyright (C) 2022-present JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="bsnes-lr" -PKG_VERSION="370a8642b1ec06d60d65467f4db1b098e4cb49f1" +PKG_VERSION="1ed1dea381af35a865846af2ce38dfde10ab6834" PKG_LICENSE="GPLv2" PKG_SITE="https://github.com/libretro/bsnes-libretro" PKG_URL="${PKG_SITE}/archive/${PKG_VERSION}.tar.gz" diff --git a/packages/emulators/libretro/cap32-lr/package.mk b/packages/emulators/libretro/cap32-lr/package.mk index 4a79e957a7..85a69fc449 100644 --- a/packages/emulators/libretro/cap32-lr/package.mk +++ b/packages/emulators/libretro/cap32-lr/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="cap32-lr" -PKG_VERSION="4a071f2c004273abf0f9fa0640b36f6664d8381a" +PKG_VERSION="488c29894c3c82d441abbccad903e27aac5d06cc" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPLv2" diff --git a/packages/emulators/libretro/dosbox-pure-lr/package.mk b/packages/emulators/libretro/dosbox-pure-lr/package.mk index 752152d761..e1661a1e33 100644 --- a/packages/emulators/libretro/dosbox-pure-lr/package.mk +++ b/packages/emulators/libretro/dosbox-pure-lr/package.mk @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="dosbox-pure-lr" -PKG_VERSION="696503df41c52376cc4de8774c4c46107a846a8f" +PKG_VERSION="87bf6365158325b76ff238c1ad8daf16a859bbe8" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPLv2" diff --git a/packages/emulators/libretro/fbneo-lr/package.mk b/packages/emulators/libretro/fbneo-lr/package.mk index 75a74773b3..83faa3fdb0 100644 --- a/packages/emulators/libretro/fbneo-lr/package.mk +++ b/packages/emulators/libretro/fbneo-lr/package.mk @@ -4,7 +4,7 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="fbneo-lr" -PKG_VERSION="c6cb6e43497f45a7d39e1194447f318eb0b27b16" +PKG_VERSION="0f0e76c4a4762f29cdc3e88b0ed82ae6ae638dbe" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="Non-commercial" diff --git a/packages/emulators/libretro/fceumm-lr/package.mk b/packages/emulators/libretro/fceumm-lr/package.mk index 47b82be940..63ba946446 100644 --- a/packages/emulators/libretro/fceumm-lr/package.mk +++ b/packages/emulators/libretro/fceumm-lr/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="fceumm-lr" -PKG_VERSION="76bde1c45707db6c5947c35b9c3e46dea4eb6258" +PKG_VERSION="a3af9f1ae34f82c4f30b572a92678500a18424ed" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPLv2" diff --git a/packages/emulators/libretro/gambatte-lr/package.mk b/packages/emulators/libretro/gambatte-lr/package.mk index afebf510ac..0b20a5f27c 100644 --- a/packages/emulators/libretro/gambatte-lr/package.mk +++ b/packages/emulators/libretro/gambatte-lr/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="gambatte-lr" -PKG_VERSION="035dbe127a38ce55501a0dfc3913d85f6446fe9a" +PKG_VERSION="ee002a8f529a5b542b0151784156f5002a6541f5" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPLv2" diff --git a/packages/emulators/libretro/gearboy-lr/package.mk b/packages/emulators/libretro/gearboy-lr/package.mk index d76bcb4dc8..c43d017b4b 100644 --- a/packages/emulators/libretro/gearboy-lr/package.mk +++ b/packages/emulators/libretro/gearboy-lr/package.mk @@ -15,7 +15,7 @@ ################################################################################ PKG_NAME="gearboy-lr" -PKG_VERSION="7e2b48051875ea5fe9a61d68b821bab763646c85" +PKG_VERSION="3e1d40edcd22c3ebd8a5337f83a11234bbd57845" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/emulators/libretro/gearcoleco-lr/package.mk b/packages/emulators/libretro/gearcoleco-lr/package.mk index e07490302a..f817aa5398 100644 --- a/packages/emulators/libretro/gearcoleco-lr/package.mk +++ b/packages/emulators/libretro/gearcoleco-lr/package.mk @@ -15,7 +15,7 @@ ################################################################################ PKG_NAME="gearcoleco-lr" -PKG_VERSION="09f8d89f1c35bbd5d6eaf5fb47c090a3fdad28ba" +PKG_VERSION="ef00ff5de9149f2bcb51c590df52fa578bba4ec4" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/emulators/libretro/gearsystem-lr/package.mk b/packages/emulators/libretro/gearsystem-lr/package.mk index 7c88c66f6b..07b98a52a9 100644 --- a/packages/emulators/libretro/gearsystem-lr/package.mk +++ b/packages/emulators/libretro/gearsystem-lr/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="gearsystem-lr" -PKG_VERSION="302fc34fc36e33d017bbc6dbe3ca101e6e3fafae" +PKG_VERSION="a2e8af25e732dcc499c7f348c156ad78f6ac0645" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPLv3" diff --git a/packages/emulators/libretro/genesis-plus-gx-lr/package.mk b/packages/emulators/libretro/genesis-plus-gx-lr/package.mk index 966c5a0553..08a2859014 100644 --- a/packages/emulators/libretro/genesis-plus-gx-lr/package.mk +++ b/packages/emulators/libretro/genesis-plus-gx-lr/package.mk @@ -21,7 +21,7 @@ ################################################################################ PKG_NAME="genesis-plus-gx-lr" -PKG_VERSION="5ca4135eed69e8ce153c76e403491eae560eae69" +PKG_VERSION="0d26f0f15f7efdf8159898308c40e778304b3f63" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="Non-commercial" diff --git a/packages/emulators/libretro/handy-lr/package.mk b/packages/emulators/libretro/handy-lr/package.mk index 0b1186e1b8..8a644b85f4 100644 --- a/packages/emulators/libretro/handy-lr/package.mk +++ b/packages/emulators/libretro/handy-lr/package.mk @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="handy-lr" -PKG_VERSION="0559d3397f689ea453b986311aeac8dbd33afb0b" +PKG_VERSION="65d6b865544cd441ef2bd18cde7bd834c23d0e48" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="Zlib" diff --git a/packages/emulators/libretro/libretro-database/package.mk b/packages/emulators/libretro/libretro-database/package.mk index 9882005be3..0c8d7ac80c 100644 --- a/packages/emulators/libretro/libretro-database/package.mk +++ b/packages/emulators/libretro/libretro-database/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="libretro-database" -PKG_VERSION="02dac2c8a7b779b495d5ce93d8fedd01738fc566" +PKG_VERSION="155fe1aefee4169e5b5f1a116445ad442e533094" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/emulators/libretro/mojozork-lr/package.mk b/packages/emulators/libretro/mojozork-lr/package.mk index 7e6e3b7a39..8631f9aac7 100644 --- a/packages/emulators/libretro/mojozork-lr/package.mk +++ b/packages/emulators/libretro/mojozork-lr/package.mk @@ -2,7 +2,7 @@ # Copyright (C) 2022-present AmberELEC (https://github.com/AmberELEC) PKG_NAME="mojozork-lr" -PKG_VERSION="89832e31d9d05c4e81908286b99db21924f3ba1a" +PKG_VERSION="5c8d81f8db53c206ace6952472e7a7e68bd8e752" PKG_SITE="https://github.com/icculus/mojozork" PKG_URL="${PKG_SITE}/archive/${PKG_VERSION}.tar.gz" PKG_DEPENDS_TARGET="toolchain" diff --git a/packages/emulators/libretro/mupen64plus-nx-lr/package.mk b/packages/emulators/libretro/mupen64plus-nx-lr/package.mk index 76b4da63eb..1f2e10dfb6 100755 --- a/packages/emulators/libretro/mupen64plus-nx-lr/package.mk +++ b/packages/emulators/libretro/mupen64plus-nx-lr/package.mk @@ -2,7 +2,7 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="mupen64plus-nx-lr" -PKG_VERSION="f1ad37c3a9be64b499d9a36f57e41d59fb677c73" +PKG_VERSION="9dd74591ac1010fbb2d9bf5c31ad4dda49be1dd0" PKG_LICENSE="GPLv2" PKG_SITE="https://github.com/libretro/mupen64plus-libretro-nx" PKG_URL="${PKG_SITE}/archive/${PKG_VERSION}.tar.gz" diff --git a/packages/emulators/libretro/opera-lr/package.mk b/packages/emulators/libretro/opera-lr/package.mk index 9f3e6ae613..dcc0142e7f 100644 --- a/packages/emulators/libretro/opera-lr/package.mk +++ b/packages/emulators/libretro/opera-lr/package.mk @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="opera-lr" -PKG_VERSION="100ae1e7decefe1f17d98cfcb9f2af4ff8452691" +PKG_VERSION="9d18f6cdab4d5c94e2db6448294d1caa11411425" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="LGPL with additional notes" diff --git a/packages/emulators/libretro/pcsx_rearmed-lr/package.mk b/packages/emulators/libretro/pcsx_rearmed-lr/package.mk index 3c46d528d9..f5b241a2b8 100644 --- a/packages/emulators/libretro/pcsx_rearmed-lr/package.mk +++ b/packages/emulators/libretro/pcsx_rearmed-lr/package.mk @@ -3,7 +3,7 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="pcsx_rearmed-lr" -PKG_VERSION="963f41620dce6ddb2527b7e3dced09564031f783" +PKG_VERSION="cf6f7cacc502169c0931320a08b0e6027e1ac908" PKG_ARCH="arm aarch64" PKG_LICENSE="GPLv2" PKG_SITE="https://github.com/libretro/pcsx_rearmed" diff --git a/packages/emulators/libretro/scummvm-lr/package.mk b/packages/emulators/libretro/scummvm-lr/package.mk index 204f463d71..3d8b959900 100644 --- a/packages/emulators/libretro/scummvm-lr/package.mk +++ b/packages/emulators/libretro/scummvm-lr/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="scummvm-lr" -PKG_VERSION="0db091d15ac2a1a6058c8f0d69df36d23bc3638f" +PKG_VERSION="18c3591548d0665b4b92a1810f3a57f9f2797ba4" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPLv2" diff --git a/packages/emulators/libretro/slang-shaders/package.mk b/packages/emulators/libretro/slang-shaders/package.mk index d5e29a7708..9c7750d96b 100644 --- a/packages/emulators/libretro/slang-shaders/package.mk +++ b/packages/emulators/libretro/slang-shaders/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="slang-shaders" -PKG_VERSION="8595c3cbea2120bc9b82e4ff756f61100543ec83" +PKG_VERSION="995f32763875303d400d140deade0399505947b1" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/emulators/libretro/stella-lr/package.mk b/packages/emulators/libretro/stella-lr/package.mk index 89c69bc125..1678c9d265 100644 --- a/packages/emulators/libretro/stella-lr/package.mk +++ b/packages/emulators/libretro/stella-lr/package.mk @@ -20,7 +20,7 @@ ################################################################################ PKG_NAME="stella-lr" -PKG_VERSION="8fe2adf28affc0477ee91689edef3b90168cd3ce" +PKG_VERSION="0bc9c5667a38d01ad931f26f0b7579bd6597f2c3" PKG_REV="1" PKG_LICENSE="GPL2" PKG_SITE="https://github.com/stella-emu/stella" diff --git a/packages/emulators/standalone/flycast-sa/package.mk b/packages/emulators/standalone/flycast-sa/package.mk index 9f9433dcad..08626eb127 100644 --- a/packages/emulators/standalone/flycast-sa/package.mk +++ b/packages/emulators/standalone/flycast-sa/package.mk @@ -3,7 +3,7 @@ # Copyright (C) 2022-present JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="flycast-sa" -PKG_VERSION="f4f087a6ea83a5483dedf23ad2b38763988eccc5" +PKG_VERSION="4a0ace5de2fd07fcf6c8e7d3c7d8f3c48d4d4581" PKG_LICENSE="GPLv2" PKG_SITE="https://github.com/flyinghead/flycast" PKG_URL="${PKG_SITE}.git" diff --git a/packages/emulators/standalone/gzdoom-sa/package.mk b/packages/emulators/standalone/gzdoom-sa/package.mk index 17a1faedb1..ee13468357 100644 --- a/packages/emulators/standalone/gzdoom-sa/package.mk +++ b/packages/emulators/standalone/gzdoom-sa/package.mk @@ -3,7 +3,7 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="gzdoom-sa" -PKG_VERSION="a368588db6f8485072429f264aca2d9c411fe9b2" +PKG_VERSION="5b90b2d80c6b976138472e8e389d76cb89282e37" PKG_LICENSE="GPLv3" PKG_SITE="https://github.com/ZDoom/gzdoom" PKG_URL="${PKG_SITE}.git" diff --git a/packages/emulators/standalone/hatarisa/package.mk b/packages/emulators/standalone/hatarisa/package.mk index bf218d8947..736256d8fe 100644 --- a/packages/emulators/standalone/hatarisa/package.mk +++ b/packages/emulators/standalone/hatarisa/package.mk @@ -2,7 +2,7 @@ # Copyright (C) 2018-present 5schatten (https://github.com/5schatten) PKG_NAME="hatarisa" -PKG_VERSION="4017c93ee54a99d6c28284d02eb62b981c742e8a" +PKG_VERSION="14bcf9b0426be229b081447e65bc567d8f8a62b3" PKG_LICENSE="GPL" PKG_SITE="https://github.com/hatari/hatari" PKG_URL="https://github.com/hatari/hatari/archive/${PKG_VERSION}.tar.gz" diff --git a/packages/emulators/standalone/openbor/package.mk b/packages/emulators/standalone/openbor/package.mk index 34527afff2..c7b54a3c61 100644 --- a/packages/emulators/standalone/openbor/package.mk +++ b/packages/emulators/standalone/openbor/package.mk @@ -4,7 +4,7 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="openbor" -PKG_VERSION="b8303cce992a0db93c3a465df3c943942fe322f8" +PKG_VERSION="5c8261444de6b61f8e2ce6e79e3d86a2949e55bd" PKG_ARCH="any" PKG_SITE="https://github.com/DCurrent/openbor" PKG_URL="${PKG_SITE}.git" @@ -24,6 +24,7 @@ pre_configure_target() { pre_make_target() { cd ${PKG_BUILD}/engine + chmod 0755 version.sh ./version.sh } diff --git a/packages/emulators/tools/control-gen/package.mk b/packages/emulators/tools/control-gen/package.mk index c0d614aeaf..fb7d32fb73 100644 --- a/packages/emulators/tools/control-gen/package.mk +++ b/packages/emulators/tools/control-gen/package.mk @@ -2,7 +2,7 @@ # Copyright (C) 2022-present JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="control-gen" -PKG_VERSION="16179c655447007c2580243659fc36a34e6a749d" +PKG_VERSION="3dd24b72a72316d3049dcf98dd2894ff91d971f6" PKG_ARCH="any" PKG_LICENSE="GPLv2" PKG_DEPENDS_TARGET="toolchain" diff --git a/packages/emulators/tools/gamecontrollerdb/package.mk b/packages/emulators/tools/gamecontrollerdb/package.mk index 137b362f08..828a0438a4 100644 --- a/packages/emulators/tools/gamecontrollerdb/package.mk +++ b/packages/emulators/tools/gamecontrollerdb/package.mk @@ -2,7 +2,7 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="gamecontrollerdb" -PKG_VERSION="a2ae8f6968dfb27a57a15c8f62ea9f20b05362c4" +PKG_VERSION="25915d3aacf38e42da899b569dfdd0631cc73dbe" PKG_ARCH="any" PKG_LICENSE="GPL" PKG_DEPENDS_TARGET="toolchain SDL2" diff --git a/packages/emulators/tools/retroarch-assets/package.mk b/packages/emulators/tools/retroarch-assets/package.mk index 81cfd3a29b..424d22677c 100644 --- a/packages/emulators/tools/retroarch-assets/package.mk +++ b/packages/emulators/tools/retroarch-assets/package.mk @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="retroarch-assets" -PKG_VERSION="1440f6737840f010f3b12a6b68b7a3871506e207" +PKG_VERSION="6c1674c502dce3045cf799b2b0f1d716a96c2806" PKG_LICENSE="GPL" PKG_SITE="https://github.com/libretro/retroarch-assets" PKG_URL="https://github.com/libretro/retroarch-assets/archive/${PKG_VERSION}.tar.gz" diff --git a/packages/emulators/tools/retroarch-joypads/package.mk b/packages/emulators/tools/retroarch-joypads/package.mk index 83eff86c6f..24c3b1b913 100644 --- a/packages/emulators/tools/retroarch-joypads/package.mk +++ b/packages/emulators/tools/retroarch-joypads/package.mk @@ -2,7 +2,7 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="retroarch-joypads" -PKG_VERSION="a57f1489ac289415d7fbdae4d56d55ed01c45714" +PKG_VERSION="d0bcfef45de186df8be9037cd4b8db1b21cf683b" PKG_LICENSE="GPL" PKG_SITE="https://github.com/libretro/retroarch-joypad-autoconfig" PKG_URL="${PKG_SITE}.git" From 3728c1ea3c0719785b7471bc0745ee9f4b189d60 Mon Sep 17 00:00:00 2001 From: brooksytech <1673861+brooksytech@users.noreply.github.com> Date: Mon, 1 Jan 2024 15:42:32 +0000 Subject: [PATCH 03/35] Bump kernel to 6.1.70 on supported devices --- projects/Amlogic/packages/linux/package.mk | 2 +- projects/Rockchip/packages/linux/package.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/Amlogic/packages/linux/package.mk b/projects/Amlogic/packages/linux/package.mk index 29ff5a02a6..3860010f8c 100644 --- a/projects/Amlogic/packages/linux/package.mk +++ b/projects/Amlogic/packages/linux/package.mk @@ -18,7 +18,7 @@ PKG_PATCH_DIRS+="${DEVICE}" case ${DEVICE} in S922X*) - PKG_VERSION="6.1.69" + PKG_VERSION="6.1.70" PKG_URL="https://www.kernel.org/pub/linux/kernel/v6.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" ;; esac diff --git a/projects/Rockchip/packages/linux/package.mk b/projects/Rockchip/packages/linux/package.mk index 3236c8df88..babc723231 100644 --- a/projects/Rockchip/packages/linux/package.mk +++ b/projects/Rockchip/packages/linux/package.mk @@ -36,7 +36,7 @@ case ${DEVICE} in PKG_GIT_CLONE_BRANCH="main" ;; RK33*) - PKG_VERSION="6.1.69" + PKG_VERSION="6.1.70" PKG_URL="https://www.kernel.org/pub/linux/kernel/v6.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" ;; esac From 40d2508866aeb5dcee267990e8d6e019c0750e8c Mon Sep 17 00:00:00 2001 From: fewtarius Date: Mon, 1 Jan 2024 16:54:59 +0000 Subject: [PATCH 04/35] Bump AMD64 Linux to 6.6.9. --- packages/kernel/linux/package.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/packages/kernel/linux/package.mk b/packages/kernel/linux/package.mk index e0968313e7..33169c422b 100644 --- a/packages/kernel/linux/package.mk +++ b/packages/kernel/linux/package.mk @@ -4,7 +4,7 @@ PKG_NAME="linux" PKG_LICENSE="GPL" -PKG_VERSION="6.6.8" +PKG_VERSION="6.6.9" PKG_URL="https://www.kernel.org/pub/linux/kernel/v6.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" PKG_SITE="http://www.kernel.org" PKG_DEPENDS_HOST="ccache:host rsync:host openssl:host rdfind:host" From 92801d1c57cec68d03669bd9fc920768b99cc115 Mon Sep 17 00:00:00 2001 From: fewtarius Date: Tue, 2 Jan 2024 13:57:37 +0000 Subject: [PATCH 05/35] Fix gzdoom. --- packages/emulators/standalone/gzdoom-sa/package.mk | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/packages/emulators/standalone/gzdoom-sa/package.mk b/packages/emulators/standalone/gzdoom-sa/package.mk index ee13468357..8c19ad4dfa 100644 --- a/packages/emulators/standalone/gzdoom-sa/package.mk +++ b/packages/emulators/standalone/gzdoom-sa/package.mk @@ -3,10 +3,11 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="gzdoom-sa" -PKG_VERSION="5b90b2d80c6b976138472e8e389d76cb89282e37" +PKG_VERSION="6ce809e" PKG_LICENSE="GPLv3" PKG_SITE="https://github.com/ZDoom/gzdoom" PKG_URL="${PKG_SITE}.git" +PKG_GIT_CLONE_BRANCH="4.11" PKG_DEPENDS_HOST="toolchain SDL2:host zmusic:host libvpx:host libwebp:host" PKG_DEPENDS_TARGET="toolchain SDL2 gzdoom-sa:host zmusic libvpx libwebp" PKG_LONGDESC="GZDoom is a modder-friendly OpenGL and Vulkan source port based on the DOOM engine" @@ -36,15 +37,15 @@ pre_configure_target() { ### Enable GLES on devices that don't support OpenGL. if [ ! "${OPENGL_SUPPORT}" = "yes" ] then - sed -i 's~#define USE_GLAD_LOADER 0~#define USE_GLAD_LOADER 1~g' ${PKG_BUILD}/src/common/rendering/gles/gles_system.h - PKG_CMAKE_OPTS_TARGET+=" -DHAVE_GLES2=ON \ - -DHAVE_VULKAN=OFF" + PKG_CMAKE_OPTS_TARGET+=" -DHAVE_GLES2=ON" fi ### Enable vulkan support on devices that have it available. if [ "${VULKAN_SUPPORT}" = "yes" ] then PKG_CMAKE_OPTS_TARGET+=" -DHAVE_VULKAN=ON" + else + PKG_CMAKE_OPTS_TARGET+=" -DHAVE_VULKAN=OFF" fi } From 61ddbd69de36a4a77fb8c94e467e1636ce89fff3 Mon Sep 17 00:00:00 2001 From: fewtarius Date: Tue, 2 Jan 2024 14:58:14 +0000 Subject: [PATCH 06/35] Drop dev build schedule, move to manual dev builds. --- .github/workflows/release-dev.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/.github/workflows/release-dev.yaml b/.github/workflows/release-dev.yaml index 425f200f9e..761ce4df5a 100644 --- a/.github/workflows/release-dev.yaml +++ b/.github/workflows/release-dev.yaml @@ -6,8 +6,6 @@ name: release-dev on: - schedule: - - cron: '0 12 * * *' workflow_dispatch: env: BRANCH: dev From 1404c6ce086329378f3d2c1c33dc9615f06d6706 Mon Sep 17 00:00:00 2001 From: brooksytech <1673861+brooksytech@users.noreply.github.com> Date: Tue, 2 Jan 2024 15:00:19 +0000 Subject: [PATCH 07/35] Bump citra-sa and yuzu-sa --- packages/emulators/standalone/citra-sa/package.mk | 2 +- packages/emulators/standalone/yuzu-sa/package.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/packages/emulators/standalone/citra-sa/package.mk b/packages/emulators/standalone/citra-sa/package.mk index 18739fcbc6..5da3e1ecdb 100644 --- a/packages/emulators/standalone/citra-sa/package.mk +++ b/packages/emulators/standalone/citra-sa/package.mk @@ -17,7 +17,7 @@ case ${DEVICE} in ;; *) PKG_URL="${PKG_SITE}.git" - PKG_VERSION="b6b98af105c7bcc958b5888f8a3b85fec71989ed" + PKG_VERSION="9b147d3f9c31bc6af1ce1281c52b02b338925e5a" ;; esac diff --git a/packages/emulators/standalone/yuzu-sa/package.mk b/packages/emulators/standalone/yuzu-sa/package.mk index 60a1bf0ce6..56e5dfae60 100644 --- a/packages/emulators/standalone/yuzu-sa/package.mk +++ b/packages/emulators/standalone/yuzu-sa/package.mk @@ -2,7 +2,7 @@ # Copyright (C) 2022-present JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="yuzu-sa" -PKG_VERSION="05e3db3ac9edbff0e4885ef8b42d3a2427c9f027" +PKG_VERSION="29b983398cadb90820210318ae7200ede3a582f9" PKG_ARCH="x86_64" PKG_LICENSE="GPLv3" PKG_SITE="https://github.com/yuzu-emu/yuzu" From 22ec9a79b92ce5a796756e184c199cfb4b63a78a Mon Sep 17 00:00:00 2001 From: fewtarius Date: Wed, 3 Jan 2024 01:04:33 +0000 Subject: [PATCH 08/35] Fix incorrect syncthing path. --- .../patches/003-fix-default-path.patch | 102 ++++++++++++++++++ .../syncthing/sources/start_syncthing.sh | 2 +- 2 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 packages/network/syncthing/patches/003-fix-default-path.patch diff --git a/packages/network/syncthing/patches/003-fix-default-path.patch b/packages/network/syncthing/patches/003-fix-default-path.patch new file mode 100644 index 0000000000..cef26ecc62 --- /dev/null +++ b/packages/network/syncthing/patches/003-fix-default-path.patch @@ -0,0 +1,102 @@ +diff -rupN syncthing.orig/lib/locations/locations.go syncthing/lib/locations/locations.go +--- syncthing.orig/lib/locations/locations.go 2023-12-11 06:46:46.000000000 +0000 ++++ syncthing/lib/locations/locations.go 2024-01-03 01:01:17.529930502 +0000 +@@ -49,7 +49,7 @@ const ( + + LevelDBDir = "index-v0.14.0.db" + configFileName = "config.xml" +- defaultStateDir = ".local/state/syncthing" ++ defaultStateDir = ".config/syncthing" + oldDefaultConfigDir = ".config/syncthing" + ) + +@@ -244,7 +244,7 @@ func unixConfigDir(userHome, xdgConfigHo + func unixDataDir(userHome, configDir, xdgDataHome, xdgStateHome string, fileExists func(string) bool) string { + // If a database exists at the config location, use that. This is the + // most common case for both legacy (~/.config/syncthing) and current +- // (~/.local/state/syncthing) setups. ++ // (~/.config/syncthing) setups. + if fileExists(filepath.Join(configDir, LevelDBDir)) { + return configDir + } +diff -rupN syncthing.orig/lib/locations/locations_test.go syncthing/lib/locations/locations_test.go +--- syncthing.orig/lib/locations/locations_test.go 2023-12-11 06:46:46.000000000 +0000 ++++ syncthing/lib/locations/locations_test.go 2024-01-03 01:01:17.529930502 +0000 +@@ -29,9 +29,9 @@ func TestUnixConfigDir(t *testing.T) { + // First some "new installations", no files exist previously. + + // No variables set, use our current default +- {"/home/user", "", "", nil, "/home/user/.local/state/syncthing"}, ++ {"/home/user", "", "", nil, "/home/user/.config/syncthing"}, + // Config home set, doesn't matter +- {"/home/user", "/somewhere/else", "", nil, "/home/user/.local/state/syncthing"}, ++ {"/home/user", "/somewhere/else", "", nil, "/home/user/.config/syncthing"}, + // State home set, use that + {"/home/user", "", "/var/state", nil, "/var/state/syncthing"}, + // State home set, again config home doesn't matter +@@ -75,9 +75,9 @@ func TestUnixDataDir(t *testing.T) { + // First some "new installations", no files exist previously. + + // No variables set, use our current default +- {"/home/user", "", "", "", nil, "/home/user/.local/state/syncthing"}, ++ {"/home/user", "", "", "", nil, "/home/user/.config/syncthing"}, + // Data home set, doesn't matter +- {"/home/user", "", "/somewhere/else", "", nil, "/home/user/.local/state/syncthing"}, ++ {"/home/user", "", "/somewhere/else", "", nil, "/home/user/.config/syncthing"}, + // State home set, use that + {"/home/user", "", "", "/var/state", nil, "/var/state/syncthing"}, + +diff -rupN syncthing.orig/man/syncthing.1 syncthing/man/syncthing.1 +--- syncthing.orig/man/syncthing.1 2023-12-11 06:46:46.000000000 +0000 ++++ syncthing/man/syncthing.1 2024-01-03 01:01:17.529930502 +0000 +@@ -157,7 +157,7 @@ given subcommand. + .B \-\-home= + Set common configuration and data directory. The default configuration + directory is \fB$XDG_STATE_HOME/syncthing\fP or +-\fB$HOME/.local/state/syncthing\fP (Unix\-like), ++\fB$HOME/.config/syncthing\fP (Unix\-like), + \fB$HOME/Library/Application Support/Syncthing\fP (Mac) and + \fB%LOCALAPPDATA%\eSyncthing\fP (Windows). + .UNINDENT +diff -rupN syncthing.orig/man/syncthing-config.5 syncthing/man/syncthing-config.5 +--- syncthing.orig/man/syncthing-config.5 2023-12-11 06:46:46.000000000 +0000 ++++ syncthing/man/syncthing-config.5 2024-01-03 01:01:17.529930502 +0000 +@@ -37,7 +37,7 @@ syncthing-config \- Syncthing Configurat + .nf + .ft C + $XDG_STATE_HOME/syncthing +-$HOME/.local/state/syncthing ++$HOME/.config/syncthing + $HOME/Library/Application Support/Syncthing + %LOCALAPPDATA%\eSyncthing + .ft P +@@ -48,7 +48,7 @@ $HOME/Library/Application Support/Syncth + .sp + Changed in version 1.27.0: The default location of the configuration and database directory on + Unix\-like systems was changed to \fB$XDG_STATE_HOME/syncthing\fP or +-\fB$HOME/.local/state/syncthing\fP\&. Previously the default config location ++\fB$HOME/.config/syncthing\fP\&. Previously the default config location + was \fB$XDG_CONFIG_HOME/syncthing\fP or \fB$HOME/.config/syncthing\fP\&. The + database directory was previously \fB$HOME/.config/syncthing\fP or, if the + environment variable was set, \fB$XDG_DATA_HOME/syncthing\fP\&. Existing +@@ -65,7 +65,7 @@ Syncthing also keeps an index database w + default stored in the same directory, though this can be overridden. + .sp + The location defaults to \fB$XDG_STATE_HOME/syncthing\fP or +-\fB$HOME/.local/state/syncthing\fP (Unix\-like), \fB$HOME/Library/Application ++\fB$HOME/.config/syncthing\fP (Unix\-like), \fB$HOME/Library/Application + Support/Syncthing\fP (Mac), or \fB%LOCALAPPDATA%\eSyncthing\fP (Windows). It can + be changed at runtime using the \fB\-\-config\fP or \fB\-\-home\fP flags or the + corresponding environment varibles (\fB$STCONFDIR\fP or \fBSTHOMEDIR\fP). The +diff -rupN syncthing.orig/man/syncthing-faq.7 syncthing/man/syncthing-faq.7 +--- syncthing.orig/man/syncthing-faq.7 2023-12-11 06:46:46.000000000 +0000 ++++ syncthing/man/syncthing-faq.7 2024-01-03 01:01:17.529930502 +0000 +@@ -355,7 +355,7 @@ The web GUI contains a \fBRecent Changes + displays changes since the last (re)start of Syncthing. With the \fB\-\-audit\fP + option you can enable a persistent, detailed log of changes and most + activities, which contains a JSON\-formatted sequence of events in the +-\fB~/.local/state/syncthing/audit\-_date_\-_time_.log\fP file. ++\fB~/.config/syncthing/audit\-_date_\-_time_.log\fP file. + .SS Does the audit log contain every change? + .sp + The audit log (and the \fBRecent Changes\fP window) sees the changes that your diff --git a/packages/network/syncthing/sources/start_syncthing.sh b/packages/network/syncthing/sources/start_syncthing.sh index e1f3175da1..ecb4451f51 100755 --- a/packages/network/syncthing/sources/start_syncthing.sh +++ b/packages/network/syncthing/sources/start_syncthing.sh @@ -7,6 +7,6 @@ ROOTPASS=$(get_setting root.password) # Set the root user and password for SyncThing syncthing generate --gui-user root --gui-password ${ROOTPASS} -xmlstarlet ed --inplace -u "//configuration/gui/address" -v ":8384" /storage/.config/syncthing/config.xml +xmlstarlet ed --inplace -u "//configuration/gui/address" -v "0.0.0.0:8384" /storage/.config/syncthing/config.xml syncthing -no-browser -no-restart From 6800f8ddeb9ac3d5f155a3e035eaaee08b29e6b4 Mon Sep 17 00:00:00 2001 From: fewtarius Date: Wed, 3 Jan 2024 19:06:44 +0000 Subject: [PATCH 09/35] Revert gcc to 12.3 as at least one emulator segfaults with gcc 13.2(.0 & .1) (Dolphin). --- .../standalone/dolphin-sa/package.mk | 10 +- packages/lang/gcc/package.mk | 6 +- .../patches/gcc-sync-to-12.3.1-01032024.patch | 180005 +++++++++++++++ 3 files changed, 180011 insertions(+), 10 deletions(-) create mode 100644 packages/lang/gcc/patches/gcc-sync-to-12.3.1-01032024.patch diff --git a/packages/emulators/standalone/dolphin-sa/package.mk b/packages/emulators/standalone/dolphin-sa/package.mk index e5b7468269..cc365f7e9b 100644 --- a/packages/emulators/standalone/dolphin-sa/package.mk +++ b/packages/emulators/standalone/dolphin-sa/package.mk @@ -48,15 +48,10 @@ then fi pre_configure_target() { - sed -i 's~#include ~#include \n#include ~g' ${PKG_BUILD}/Externals/VulkanMemoryAllocator/include/vk_mem_alloc.h - sed -i 's~#include ~#include \n#include ~g' ${PKG_BUILD}/Externals/VulkanMemoryAllocator/include/vk_mem_alloc.h -} - -PKG_CMAKE_OPTS_TARGET+=" -DENABLE_HEADLESS=ON \ + PKG_CMAKE_OPTS_TARGET+=" -DENABLE_HEADLESS=ON \ -DENABLE_EVDEV=ON \ -DUSE_DISCORD_PRESENCE=OFF \ -DBUILD_SHARED_LIBS=OFF \ - -DUSE_MGBA=OFF \ -DLINUX_LOCAL_DEV=ON \ -DENABLE_PULSEAUDIO=ON \ -DENABLE_ALSA=ON \ @@ -67,7 +62,10 @@ PKG_CMAKE_OPTS_TARGET+=" -DENABLE_HEADLESS=ON \ -DENABLE_QT=OFF \ -DENCODE_FRAMEDUMPS=OFF \ -DENABLE_CLI_TOOL=OFF" + sed -i 's~#include ~#include \n#include ~g' ${PKG_BUILD}/Externals/VulkanMemoryAllocator/include/vk_mem_alloc.h + sed -i 's~#include ~#include \n#include ~g' ${PKG_BUILD}/Externals/VulkanMemoryAllocator/include/vk_mem_alloc.h +} makeinstall_target() { mkdir -p ${INSTALL}/usr/bin diff --git a/packages/lang/gcc/package.mk b/packages/lang/gcc/package.mk index 1c54751471..de9c60d9ce 100644 --- a/packages/lang/gcc/package.mk +++ b/packages/lang/gcc/package.mk @@ -4,7 +4,7 @@ # Copyright (C) 2023 JELOS (https://github.com/JustEnoughLinuxOS) PKG_NAME="gcc" -PKG_VERSION="13.2.0" +PKG_VERSION="12.3.0" PKG_LICENSE="GPL-2.0-or-later" PKG_SITE="https://gcc.gnu.org/" PKG_URL="https://ftp.gnu.org/gnu/gcc/${PKG_NAME}-${PKG_VERSION}/${PKG_NAME}-${PKG_VERSION}.tar.xz" @@ -54,6 +54,7 @@ GCC_COMMON_CONFIGURE_OPTS="--target=${TARGET_NAME} \ --disable-libssp \ --disable-static \ --enable-shared \ + --disable-werror \ --enable-__cxa_atexit" PKG_CONFIGURE_OPTS_BOOTSTRAP="${GCC_COMMON_CONFIGURE_OPTS} \ @@ -68,7 +69,6 @@ PKG_CONFIGURE_OPTS_BOOTSTRAP="${GCC_COMMON_CONFIGURE_OPTS} \ --disable-threads \ --without-headers \ --with-newlib \ - --disable-werror \ ${GCC_OPTS}" PKG_CONFIGURE_OPTS_HOST="${GCC_COMMON_CONFIGURE_OPTS} \ @@ -85,8 +85,6 @@ PKG_CONFIGURE_OPTS_HOST="${GCC_COMMON_CONFIGURE_OPTS} \ --enable-clocale=gnu \ ${GCC_OPTS}" -PKG_CONFIGURE_OPTS_TARGET="${PKG_CONFIGURE_OPTS_HOST}" - post_makeinstall_bootstrap() { GCC_VERSION=$(${TOOLCHAIN}/bin/${TARGET_NAME}-gcc -dumpversion) DATE="0401$(echo ${GCC_VERSION} | sed 's/\./0/g')" diff --git a/packages/lang/gcc/patches/gcc-sync-to-12.3.1-01032024.patch b/packages/lang/gcc/patches/gcc-sync-to-12.3.1-01032024.patch new file mode 100644 index 0000000000..91ff0a9788 --- /dev/null +++ b/packages/lang/gcc/patches/gcc-sync-to-12.3.1-01032024.patch @@ -0,0 +1,180005 @@ +diff --git a/fixincludes/ChangeLog b/fixincludes/ChangeLog +index d02624f669f..e7afc3fa00e 100644 +--- a/fixincludes/ChangeLog ++++ b/fixincludes/ChangeLog +@@ -1,3 +1,10 @@ ++2023-12-11 Rainer Orth ++ ++ * inclhack.def (darwin_flt_eval_method): Handle macOS 14 guard ++ variant. ++ * fixincl.x: Regenerate. ++ * tests/base/math.h [DARWIN_FLT_EVAL_METHOD_CHECK]: Update test. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/fixincludes/fixincl.x b/fixincludes/fixincl.x +index bad490453b7..b314506f00d 100644 +--- a/fixincludes/fixincl.x ++++ b/fixincludes/fixincl.x +@@ -2,11 +2,11 @@ + * + * DO NOT EDIT THIS FILE (fixincl.x) + * +- * It has been AutoGen-ed February 27, 2022 at 07:47:03 PM by AutoGen 5.18.16 ++ * It has been AutoGen-ed December 11, 2023 at 06:14:06 PM by AutoGen 5.18.16 + * From the definitions inclhack.def + * and the template file fixincl + */ +-/* DO NOT SVN-MERGE THIS FILE, EITHER Sun Feb 27 19:47:03 UTC 2022 ++/* DO NOT SVN-MERGE THIS FILE, EITHER Mon Dec 11 18:14:06 CET 2023 + * + * You must regenerate it. Use the ./genfixes script. + * +@@ -3587,7 +3587,7 @@ tSCC* apzDarwin_Flt_Eval_MethodMachs[] = { + * content selection pattern - do fix if pattern found + */ + tSCC zDarwin_Flt_Eval_MethodSelect0[] = +- "^#if __FLT_EVAL_METHOD__ == 0$"; ++ "^#if __FLT_EVAL_METHOD__ == 0( \\|\\| __FLT_EVAL_METHOD__ == -1)?$"; + + #define DARWIN_FLT_EVAL_METHOD_TEST_CT 1 + static tTestDesc aDarwin_Flt_Eval_MethodTests[] = { +@@ -3598,7 +3598,7 @@ static tTestDesc aDarwin_Flt_Eval_MethodTests[] = { + */ + static const char* apzDarwin_Flt_Eval_MethodPatch[] = { + "format", +- "#if __FLT_EVAL_METHOD__ == 0 || __FLT_EVAL_METHOD__ == 16", ++ "%0 || __FLT_EVAL_METHOD__ == 16", + (char*)NULL }; + + /* * * * * * * * * * * * * * * * * * * * * * * * * * +diff --git a/fixincludes/inclhack.def b/fixincludes/inclhack.def +index 7605ac89aa2..5cdd52a8de8 100644 +--- a/fixincludes/inclhack.def ++++ b/fixincludes/inclhack.def +@@ -1772,10 +1772,11 @@ fix = { + hackname = darwin_flt_eval_method; + mach = "*-*-darwin*"; + files = math.h; +- select = "^#if __FLT_EVAL_METHOD__ == 0$"; ++ select = "^#if __FLT_EVAL_METHOD__ == 0( \\|\\| __FLT_EVAL_METHOD__ == -1)?$"; + c_fix = format; +- c_fix_arg = "#if __FLT_EVAL_METHOD__ == 0 || __FLT_EVAL_METHOD__ == 16"; +- test_text = "#if __FLT_EVAL_METHOD__ == 0"; ++ c_fix_arg = "%0 || __FLT_EVAL_METHOD__ == 16"; ++ test_text = "#if __FLT_EVAL_METHOD__ == 0\n" ++ "#if __FLT_EVAL_METHOD__ == 0 || __FLT_EVAL_METHOD__ == -1"; + }; + + /* +diff --git a/fixincludes/tests/base/math.h b/fixincludes/tests/base/math.h +index 29b67579748..7b92f29a409 100644 +--- a/fixincludes/tests/base/math.h ++++ b/fixincludes/tests/base/math.h +@@ -32,6 +32,7 @@ + + #if defined( DARWIN_FLT_EVAL_METHOD_CHECK ) + #if __FLT_EVAL_METHOD__ == 0 || __FLT_EVAL_METHOD__ == 16 ++#if __FLT_EVAL_METHOD__ == 0 || __FLT_EVAL_METHOD__ == -1 || __FLT_EVAL_METHOD__ == 16 + #endif /* DARWIN_FLT_EVAL_METHOD_CHECK */ + + +diff --git a/gcc/BASE-VER b/gcc/BASE-VER +index 4d23cb8e0bd..9c028e25d40 100644 +--- a/gcc/BASE-VER ++++ b/gcc/BASE-VER +@@ -1 +1 @@ +-12.3.0 ++12.3.1 +diff --git a/gcc/ChangeLog b/gcc/ChangeLog +index 07376405660..54316b78f1a 100644 +--- a/gcc/ChangeLog ++++ b/gcc/ChangeLog +@@ -1,3 +1,1696 @@ ++2023-12-19 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-19 Jakub Jelinek ++ ++ PR target/112816 ++ * config/i386/mmx.md (signbitv2sf2): Force operands[1] into a REG. ++ ++2023-12-18 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-18 Jakub Jelinek ++ ++ PR tree-optimization/113013 ++ * tree-object-size.cc (alloc_object_size): Return size_unknown if ++ corresponding argument(s) don't have integral type or have integral ++ type with higher precision than sizetype. Don't check arg1 >= 0 ++ uselessly. Compare argument indexes against gimple_call_num_args ++ in unsigned type rather than int. Formatting fixes. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-11-29 Jakub Jelinek ++ ++ PR middle-end/112733 ++ * fold-const.cc (multiple_of_p): Pass SIGNED rather than ++ UNSIGNED for wi::multiple_of_p on widest_int arguments. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-05 Jakub Jelinek ++ ++ PR target/112845 ++ * config/i386/i386.md (movabsq $(i32 << shift), r64 peephole2): FAIL ++ if the new immediate is ix86_endbr_immediate_operand. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-04 Jakub Jelinek ++ ++ PR target/112837 ++ * config/i386/i386.cc (ix86_elim_entry_set_got): Before checking ++ for UNSPEC_SET_GOT check that SET_SRC is UNSPEC. Use SET_SRC and ++ SET_DEST macros instead of XEXP, rename vec variable to set. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-04 Jakub Jelinek ++ ++ PR target/112816 ++ * config/i386/sse.md (signbit2): Force operands[1] into a REG. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-11-25 Jakub Jelinek ++ ++ PR target/111408 ++ * config/i386/i386.md (*jcc_bt_mask): Add (const_int 0) as ++ expected second operand of bt_comparison_operator. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-11-13 Jakub Jelinek ++ ++ PR tree-optimization/111967 ++ * gimple-range-cache.cc (block_range_cache::set_bb_range): Grow ++ m_ssa_ranges to num_ssa_names rather than num_ssa_names + 1. ++ (block_range_cache::dump): Iterate from 1 rather than 0. Don't use ++ ssa_name (x) unless m_ssa_ranges[x] is non-NULL. Iterate to ++ m_ssa_ranges.length () rather than num_ssa_names. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-11-09 Jakub Jelinek ++ ++ PR c/112339 ++ * attribs.cc (attribute_ignored_p): Only return true for ++ attr_namespace_ignored_p if as is NULL. ++ (decl_attributes): Never add ignored attributes. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-07-19 Jakub Jelinek ++ ++ PR tree-optimization/110731 ++ * wide-int.cc (wi::divmod_internal): Always unpack dividend and ++ divisor as UNSIGNED regardless of sgn. ++ ++2023-12-15 Richard Biener ++ ++ Backported from master: ++ 2023-08-24 Richard Biener ++ ++ PR debug/111080 ++ * dwarf2out.cc (prune_unused_types_walk): Handle ++ DW_TAG_restrict_type, DW_TAG_shared_type, DW_TAG_atomic_type, ++ DW_TAG_immutable_type, DW_TAG_coarray_type, DW_TAG_unspecified_type ++ and DW_TAG_dynamic_type as to only output them when referenced. ++ ++2023-12-15 Richard Biener ++ ++ Backported from master: ++ 2023-08-25 Richard Biener ++ ++ PR tree-optimization/111137 ++ * tree-vect-data-refs.cc (vect_slp_analyze_load_dependences): ++ Properly handle grouped stores from other SLP instances. ++ ++2023-12-15 Richard Biener ++ ++ Backported from master: ++ 2023-08-25 Richard Biener ++ ++ * tree-vect-data-refs.cc (vect_slp_analyze_store_dependences): ++ Split out from vect_slp_analyze_node_dependences, remove ++ dead code. ++ (vect_slp_analyze_load_dependences): Split out from ++ vect_slp_analyze_node_dependences, adjust comments. Process ++ queued stores before any disambiguation. ++ (vect_slp_analyze_node_dependences): Remove. ++ (vect_slp_analyze_instance_dependence): Adjust. ++ ++2023-12-12 liuhongt ++ ++ Backported from master: ++ 2023-12-12 liuhongt ++ ++ PR target/112891 ++ * config/i386/i386.cc (ix86_avx_u128_mode_after): Return ++ AVX_U128_ANY if callee_abi doesn't clobber all_sse_regs to ++ align with ix86_avx_u128_mode_needed. ++ (ix86_avx_u128_mode_needed): Return AVX_U128_ClEAN for ++ sibling_call. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-10-23 Richard Biener ++ ++ PR tree-optimization/111917 ++ * tree-ssa-loop-unswitch.cc (hoist_guard): Always insert ++ new conditional after last stmt. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-10-17 Richard Biener ++ ++ PR middle-end/111818 ++ * tree-ssa.cc (maybe_optimize_var): When clearing ++ DECL_NOT_GIMPLE_REG_P always rewrite into SSA. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-09-28 Richard Biener ++ ++ PR tree-optimization/111614 ++ * tree-ssa-reassoc.cc (undistribute_bitref_for_vector): Properly ++ convert the first vector when required. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-10-12 Richard Biener ++ ++ PR tree-optimization/111764 ++ * tree-vect-loop.cc (check_reduction_path): Remove the attempt ++ to allow x + x via special-casing of assigns. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-10-20 Richard Biener ++ ++ PR tree-optimization/111445 ++ * tree-scalar-evolution.cc (simple_iv_with_niters): ++ Add missing check for a sign-conversion. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-08-18 Richard Biener ++ ++ PR tree-optimization/111019 ++ * tree-ssa-loop-im.cc (gather_mem_refs_stmt): When canonicalizing ++ also scrap base and offset in case the ref is indirect. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-08-03 Richard Biener ++ ++ PR tree-optimization/110702 ++ * tree-ssa-loop-ivopts.cc (rewrite_use_address): When ++ we created a NULL pointer based access rewrite that to ++ a LEA. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-07-06 Richard Biener ++ ++ PR tree-optimization/110556 ++ * tree-ssa-tail-merge.cc (gimple_equal_p): Check ++ assign code and all operands of non-stores. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-07-06 Richard Biener ++ ++ PR tree-optimization/110515 ++ * tree-ssa-pre.cc (compute_avail): Make code dealing ++ with hoisting loads with different alias-sets more ++ robust. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-06-20 Richard Biener ++ ++ PR debug/110295 ++ * dwarf2out.cc (process_scope_var): Continue processing ++ the decl after setting a parent in case the existing DIE ++ was in limbo. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-05-31 Richard Biener ++ ++ PR ipa/109983 ++ PR tree-optimization/109143 ++ * tree-ssa-structalias.cc (struct topo_info): Remove. ++ (init_topo_info): Likewise. ++ (free_topo_info): Likewise. ++ (compute_topo_order): Simplify API, put the component ++ with ESCAPED last so it's processed first. ++ (topo_visit): Adjust. ++ (solve_graph): Likewise. ++ ++2023-11-24 Uros Bizjak ++ ++ Backported from master: ++ 2023-11-23 Uros Bizjak ++ ++ PR target/112672 ++ * config/i386/i386.md (parityhi2): ++ Use temporary register in the call to gen_parityhi2_cmp. ++ ++2023-11-22 Maciej W. Rozycki ++ ++ Backported from master: ++ 2023-11-22 Maciej W. Rozycki ++ ++ PR target/111815 ++ * config/vax/vax.cc (index_term_p): Only accept the index scaler ++ as the RHS operand to ASHIFT. ++ ++2023-11-20 Lulu Cheng ++ ++ Backported from master: ++ 2023-11-20 Lulu Cheng ++ ++ * config/loongarch/gnu-user.h (MUSL_ABI_SPEC): Modify suffix. ++ ++2023-11-20 Peng Fan ++ ++ Backported from master: ++ 2023-04-21 Peng Fan ++ ++ * config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER): Redefine. ++ ++2023-11-16 Xi Ruoyao ++ ++ Backported from master: ++ 2023-11-15 Xi Ruoyao ++ ++ * config/loongarch/loongarch.cc ++ (loongarch_memmodel_needs_release_fence): Remove. ++ (loongarch_cas_failure_memorder_needs_acquire): New static ++ function. ++ (loongarch_print_operand): Redefine 'G' for the barrier on CAS ++ failure. ++ * config/loongarch/sync.md (atomic_cas_value_strong): ++ Remove the redundant barrier before the LL instruction, and ++ emit an acquire barrier on failure if needed by ++ failure_memorder. ++ (atomic_cas_value_cmp_and_7_): Likewise. ++ (atomic_cas_value_add_7_): Remove the unnecessary barrier ++ before the LL instruction. ++ (atomic_cas_value_sub_7_): Likewise. ++ (atomic_cas_value_and_7_): Likewise. ++ (atomic_cas_value_xor_7_): Likewise. ++ (atomic_cas_value_or_7_): Likewise. ++ (atomic_cas_value_nand_7_): Likewise. ++ (atomic_cas_value_exchange_7_): Likewise. ++ ++2023-11-15 Kewen Lin ++ ++ Backported from master: ++ 2023-11-06 Kewen Lin ++ ++ PR target/111828 ++ * config.in: Regenerate. ++ * config/rs6000/rs6000.cc (rs6000_update_ipa_fn_target_info): Guard ++ inline asm handling under !HAVE_AS_POWER10_HTM. ++ * configure: Regenerate. ++ * configure.ac: Detect assembler support for HTM insns at power10. ++ ++2023-11-10 liuhongt ++ ++ Backported from master: ++ 2023-11-10 liuhongt ++ ++ PR target/112443 ++ * config/i386/sse.md (*avx2_pcmp3_4): Fix swap condition ++ from LT to GT since there's not in the pattern. ++ (*avx2_pcmp3_5): Ditto. ++ ++2023-11-06 John David Anglin ++ ++ * config/pa/pa.cc (pa_asm_trampoline_template): Fix typo. ++ ++2023-10-26 Lulu Cheng ++ ++ Backported from master: ++ 2023-10-23 Lulu Cheng ++ ++ * config/loongarch/loongarch.h (CLEAR_INSN_CACHE): New definition. ++ ++2023-10-26 chenxiaolong ++ ++ Backported from master: ++ 2023-10-25 chenxiaolong ++ ++ * config/loongarch/loongarch.md (get_thread_pointer):Adds the ++ instruction template corresponding to the __builtin_thread_pointer ++ function. ++ * doc/extend.texi:Add the __builtin_thread_pointer function support ++ description to the documentation. ++ ++2023-10-26 liuhongt ++ ++ Backported from master: ++ 2023-07-06 liuhongt ++ ++ PR target/110170 ++ * config/i386/i386.md (movdf_internal): Disparage slightly for ++ 2 alternatives (r,v) and (v,r) by adding constraint modifier ++ '?'. ++ ++2023-10-23 Oleg Endo ++ ++ PR target/111001 ++ * config/sh/sh_treg_combine.cc (sh_treg_combine::record_set_of_reg): ++ Skip over nop move insns. ++ ++2023-10-23 Kewen Lin ++ ++ Backported from master: ++ 2023-10-12 Kewen Lin ++ ++ PR target/111367 ++ * config/rs6000/rs6000.md (stack_protect_setsi): Support prefixed ++ instruction emission and incorporate to stack_protect_set. ++ (stack_protect_setdi): Rename to ... ++ (stack_protect_set): ... this, adjust constraint. ++ (stack_protect_testsi): Support prefixed instruction emission and ++ incorporate to stack_protect_test. ++ (stack_protect_testdi): Rename to ... ++ (stack_protect_test): ... this, adjust constraint. ++ ++2023-10-20 Oleg Endo ++ ++ PR target/101177 ++ * config/sh/sh.md (unnamed split pattern): Fix comparison of ++ find_regno_note result. ++ ++2023-10-19 Richard Sandiford ++ ++ Backported from master: ++ 2023-09-07 Richard Sandiford ++ ++ PR target/111528 ++ * lra-eliminations.cc (lra_eliminate_regs_1): Use simplify_gen_binary ++ rather than gen_rtx_PLUS. ++ ++2023-10-16 Kewen Lin ++ ++ Backported from master: ++ 2023-09-25 Kewen Lin ++ ++ PR target/111380 ++ * config/rs6000/rs6000.cc (rs6000_can_inline_p): Adopt ++ target_option_default_node when the callee has no option ++ attributes, also simplify the existing code accordingly. ++ ++2023-10-16 Kewen Lin ++ ++ Backported from master: ++ 2023-09-25 Kewen Lin ++ ++ PR target/111366 ++ * config/rs6000/rs6000.cc (rs6000_update_ipa_fn_target_info): Skip ++ empty inline asm. ++ ++2023-10-07 Andrew Pinski ++ ++ Backported from master: ++ 2023-10-06 Andrew Pinski ++ ++ PR middle-end/111699 ++ * match.pd ((c ? a : b) op d, (c ? a : b) op (c ? d : e), ++ (v ? w : 0) ? a : b, c1 ? c2 ? a : b : b): Enable only for GIMPLE. ++ ++2023-10-02 Pat Haugen ++ ++ Backported from master: ++ 2023-09-19 Pat Haugen ++ ++ * config/rs6000/rs6000.cc (rs6000_rtx_costs): Check whether the ++ modulo instruction is disabled. ++ * config/rs6000/rs6000.h (RS6000_DISABLE_SCALAR_MODULO): New. ++ * config/rs6000/rs6000.md (mod3, *mod3): Check it. ++ (define_expand umod3): New. ++ (define_insn umod3): Rename to *umod3 and check if the modulo ++ instruction is disabled. ++ (umodti3, modti3): Check if the modulo instruction is disabled. ++ ++2023-09-29 Wilco Dijkstra ++ ++ Backported from master: ++ 2023-09-28 Wilco Dijkstra ++ ++ PR target/111121 ++ * config/aarch64/aarch64.md (aarch64_movmemdi): Add new expander. ++ (movmemdi): Call aarch64_expand_cpymem_mops for correct expansion. ++ * config/aarch64/aarch64.cc (aarch64_expand_cpymem_mops): Add support ++ for memmove. ++ * config/aarch64/aarch64-protos.h (aarch64_expand_cpymem_mops): Add new ++ function. ++ ++2023-09-26 Eric Botcazou ++ ++ * gimple-range-gori.cc (gori_compute::logical_combine): Add missing ++ return statement in the varying case. ++ ++2023-09-20 Richard Sandiford ++ ++ Backported from master: ++ 2023-09-15 Richard Sandiford ++ ++ PR target/111411 ++ * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp): Require ++ the lower memory access to a mem-pair operand. ++ ++2023-09-20 Richard Sandiford ++ ++ Backported from master: ++ 2023-08-31 Richard Sandiford ++ ++ * config/aarch64/aarch64.md (untyped_call): Emit a call_value ++ rather than a call. List each possible destination register ++ in the call pattern. ++ ++2023-09-12 Uros Bizjak ++ ++ PR target/111340 ++ * config/i386/i386.cc (output_pic_addr_const): Handle CONST_WIDE_INT. ++ Call output_addr_const for CASE_CONST_SCALAR_INT. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_save_regs_above_locals_p): ++ New function. ++ (aarch64_layout_frame): Use it to decide whether locals should ++ go above or below the saved registers. ++ (aarch64_expand_prologue): Update stack layout comment. ++ Emit a stack tie after the final adjustment. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.h (aarch64_frame::saved_regs_size) ++ (aarch64_frame::below_hard_fp_saved_regs_size): Delete. ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Update accordingly. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.h (aarch64_frame::sve_save_and_probe) ++ (aarch64_frame::hard_fp_save_and_probe): New fields. ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Initialize them. ++ Rather than asserting that a leaf function saves LR, instead assert ++ that a leaf function saves something. ++ (aarch64_get_separate_components): Prevent the chosen probe ++ registers from being individually shrink-wrapped. ++ (aarch64_allocate_and_probe_stack_space): Remove workaround for ++ probe registers that aren't at the bottom of the previous allocation. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_allocate_and_probe_stack_space): ++ Always probe the residual allocation at offset 1024, asserting ++ that that is in range. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Ensure that ++ the LR save slot is in the first 16 bytes of the register save area. ++ Only form STP/LDP push/pop candidates if both registers are valid. ++ (aarch64_allocate_and_probe_stack_space): Remove workaround for ++ when LR was not in the first 16 bytes. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_allocate_and_probe_stack_space): ++ Don't probe final allocations that are exactly 1KiB in size (after ++ unprobed space above the final allocation has been deducted). ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Tweak ++ calculation of initial_adjust for frames in which all saves ++ are SVE saves. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Simplify ++ the allocation of the top of the frame. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.h (aarch64_frame): Add comment above ++ reg_offset. ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Walk offsets ++ from the bottom of the frame, rather than the bottom of the saved ++ register area. Measure reg_offset from the bottom of the frame ++ rather than the bottom of the saved register area. ++ (aarch64_save_callee_saves): Update accordingly. ++ (aarch64_restore_callee_saves): Likewise. ++ (aarch64_get_separate_components): Likewise. ++ (aarch64_process_components): Likewise. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.h (aarch64_frame::frame_size): Tweak comment. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.h (aarch64_frame::hard_fp_offset): Rename ++ to... ++ (aarch64_frame::bytes_above_hard_fp): ...this. ++ * config/aarch64/aarch64.cc (aarch64_layout_frame) ++ (aarch64_expand_prologue): Update accordingly. ++ (aarch64_initial_elimination_offset): Likewise. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.h (aarch64_frame::locals_offset): Rename to... ++ (aarch64_frame::bytes_above_locals): ...this. ++ * config/aarch64/aarch64.cc (aarch64_layout_frame) ++ (aarch64_initial_elimination_offset): Update accordingly. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_expand_prologue): Move the ++ calculation of chain_offset into the emit_frame_chain block. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.h (aarch64_frame::callee_offset): Delete. ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Remove ++ callee_offset handling. ++ (aarch64_save_callee_saves): Replace the start_offset parameter ++ with a bytes_below_sp parameter. ++ (aarch64_restore_callee_saves): Likewise. ++ (aarch64_expand_prologue): Update accordingly. ++ (aarch64_expand_epilogue): Likewise. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.h (aarch64_frame::bytes_below_hard_fp): New ++ field. ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Initialize it. ++ (aarch64_expand_epilogue): Use it instead of ++ below_hard_fp_saved_regs_size. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.h (aarch64_frame::bytes_below_saved_regs): New ++ field. ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Initialize it, ++ and use it instead of crtl->outgoing_args_size. ++ (aarch64_get_separate_components): Use bytes_below_saved_regs instead ++ of outgoing_args_size. ++ (aarch64_process_components): Likewise. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_layout_frame): Explicitly ++ allocate the frame in one go if there are no saved registers. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_expand_prologue): Use ++ chain_offset rather than callee_offset. ++ ++2023-09-12 Richard Sandiford ++ ++ * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use ++ a local shorthand for cfun->machine->frame. ++ (aarch64_restore_callee_saves, aarch64_get_separate_components): ++ (aarch64_process_components): Likewise. ++ (aarch64_allocate_and_probe_stack_space): Likewise. ++ (aarch64_expand_prologue, aarch64_expand_epilogue): Likewise. ++ (aarch64_layout_frame): Use existing shorthand for one more case. ++ ++2023-09-12 Haochen Gui ++ ++ Backported from master: ++ 2023-08-31 Haochen Gui ++ ++ PR target/96762 ++ * config/rs6000/rs6000-string.cc (expand_block_move): Call vector ++ load/store with length only on 64-bit Power10. ++ ++2023-09-11 liuhongt ++ ++ Backported from master: ++ 2023-09-11 liuhongt ++ ++ PR target/111306 ++ PR target/111335 ++ * config/i386/sse.md (int_comm): New int_attr. ++ (fma__): ++ Remove % for Complex conjugate operations since they're not ++ commutative. ++ (fma___pair): Ditto. ++ (___mask): Ditto. ++ (cmul3): Ditto. ++ ++2023-09-01 Tobias Burnus ++ ++ Backported from master: ++ 2023-08-19 Tobias Burnus ++ ++ PR middle-end/111017 ++ * omp-expand.cc (expand_omp_for_init_vars): Pass after=true ++ to expand_omp_build_cond for 'factor != 0' condition, resulting ++ in pre-r12-5295-g47de0b56ee455e code for the gimple insert. ++ ++2023-09-01 Lulu Cheng ++ ++ Backported from master: ++ 2023-09-01 Lulu Cheng ++ Guo Jie ++ ++ PR target/110484 ++ * config/loongarch/loongarch.cc (loongarch_emit_stack_tie): Use the ++ frame_pointer_needed to determine whether to use the $fp register. ++ ++2023-08-30 Jakub Jelinek ++ ++ Backported from master: ++ 2023-08-30 Jakub Jelinek ++ ++ PR tree-optimization/110914 ++ * tree-ssa-strlen.cc (strlen_pass::handle_builtin_memcpy): Don't call ++ adjust_last_stmt unless len is known constant. ++ ++2023-08-30 Jakub Jelinek ++ ++ Backported from master: ++ 2023-08-30 Jakub Jelinek ++ ++ PR tree-optimization/111015 ++ * gimple-ssa-store-merging.cc ++ (imm_store_chain_info::output_merged_store): Use wi::mask and ++ wide_int_to_tree instead of unsigned HOST_WIDE_INT shift and ++ build_int_cst to build BIT_AND_EXPR mask. ++ ++2023-08-19 Guo Jie ++ ++ Backported from master: ++ 2023-08-19 Guo Jie ++ Lulu Cheng ++ ++ * config/loongarch/t-loongarch: Add loongarch-driver.h into ++ TM_H. Add loongarch-def.h and loongarch-tune.h into ++ OPTIONS_H_EXTRA. ++ ++2023-08-16 liuhongt ++ ++ Backported from master: ++ 2023-08-16 liuhongt ++ ++ * config/i386/i386-builtins.cc ++ (ix86_vectorize_builtin_gather): Adjust for use_gather_8parts. ++ * config/i386/i386-options.cc (parse_mtune_ctrl_str): ++ Set/Clear tune features use_{gather,scatter}_{2parts, 4parts, ++ 8parts} for -mtune-crtl={,^}{use_gather,use_scatter}. ++ * config/i386/i386.cc (ix86_vectorize_builtin_scatter): Adjust ++ for use_scatter_8parts ++ * config/i386/i386.h (TARGET_USE_GATHER): Rename to .. ++ (TARGET_USE_GATHER_8PARTS): .. this. ++ (TARGET_USE_SCATTER): Rename to .. ++ (TARGET_USE_SCATTER_8PARTS): .. this. ++ * config/i386/x86-tune.def (X86_TUNE_USE_GATHER): Rename to ++ (X86_TUNE_USE_GATHER_8PARTS): .. this. ++ (X86_TUNE_USE_SCATTER): Rename to ++ (X86_TUNE_USE_SCATTER_8PARTS): .. this. ++ * config/i386/i386.opt: Add new options mgather, mscatter. ++ ++2023-08-16 liuhongt ++ ++ Backported from master: ++ 2023-08-16 liuhongt ++ ++ * config/i386/i386-options.cc (m_GDS): New macro. ++ * config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Don't ++ enable for m_GDS. ++ (X86_TUNE_USE_GATHER_4PARTS): Ditto. ++ (X86_TUNE_USE_GATHER): Ditto. ++ ++2023-08-09 liuhongt ++ ++ * common/config/i386/cpuinfo.h (get_available_features): Check ++ max_subleaf_level for valid subleaf before use CPUID. ++ ++2023-08-01 Kewen Lin ++ ++ Backported from master: ++ 2023-07-26 Kewen Lin ++ ++ PR target/110741 ++ * config/rs6000/vsx.md (define_insn xxeval): Correct vsx ++ operands output with "x". ++ ++2023-07-14 Uros Bizjak ++ ++ Backported from master: ++ 2023-07-14 Uros Bizjak ++ ++ PR target/110206 ++ * fwprop.cc (contains_paradoxical_subreg_p): Move to ... ++ * rtlanal.cc (contains_paradoxical_subreg_p): ... here. ++ * rtlanal.h (contains_paradoxical_subreg_p): Add prototype. ++ * cprop.cc (try_replace_reg): Do not set REG_EQUAL note ++ when the original source contains a paradoxical subreg. ++ ++2023-07-14 Oleg Endo ++ ++ PR target/101469 ++ * config/sh/sh.md (peephole2): Handle case where eliminated reg ++ is also used by the address of the following memory operand. ++ ++2023-07-13 Uros Bizjak ++ ++ Backported from master: ++ 2023-07-13 Uros Bizjak ++ ++ PR target/106966 ++ * config/alpha/alpha.cc (alpha_emit_set_long_const): ++ Always use DImode when constructing long const. ++ ++2023-07-08 Jonathan Wakely ++ ++ Backported from master: ++ 2023-07-08 Jonathan Wakely ++ ++ PR c++/110595 ++ * doc/invoke.texi (Warning Options): Fix typo. ++ ++2023-07-05 Michael Meissner ++ ++ Backported from master: ++ 2023-06-23 Michael Meissner ++ Aaron Sawdey ++ ++ PR target/105325 ++ * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that ++ allowed prefixed lwa to be generated. ++ * config/rs6000/fusion.md: Regenerate. ++ * config/rs6000/predicates.md (ds_form_mem_operand): Delete. ++ * config/rs6000/rs6000.md (prefixed attribute): Add support for load ++ plus compare immediate fused insns. ++ (maybe_prefixed): Likewise. ++ ++2023-07-05 Segher Boessenkool ++ ++ Backported from master: ++ 2023-06-06 Segher Boessenkool ++ ++ * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): New, rewritten and ++ split out from... ++ (gen_ld_cmpi_p10): ... this. ++ ++2023-07-04 Cui, Lili ++ ++ * common/config/i386/cpuinfo.h (get_intel_cpu): Remove model value 0xa8 ++ from Rocketlake, remove model value 0xbf from Alderlake. ++ ++2023-06-30 Eric Botcazou ++ ++ * gimple-fold.cc (fold_array_ctor_reference): Fix head comment. ++ (fold_nonarray_ctor_reference): Likewise. Specifically deal ++ with integral bit-fields. ++ (fold_ctor_reference): Make sure that the constructor uses the ++ native storage order. ++ ++2023-06-29 liuhongt ++ ++ PR rtl-optimization/110237 ++ * config/i386/sse.md (_store_mask): Refine with ++ UNSPEC_MASKMOV. ++ (maskstore_store_mask): New define_insn, it's renamed ++ from original _store_mask. ++ ++2023-06-29 liuhongt ++ ++ PR target/110309 ++ * config/i386/sse.md (maskload): ++ Refine pattern with UNSPEC_MASKLOAD. ++ (maskload): Ditto. ++ (*_load_mask): Extend mode iterator to ++ VI12HF_AVX512VL. ++ (*_load): Ditto. ++ ++2023-06-29 Hongyu Wang ++ ++ Backported from master: ++ 2023-06-26 Hongyu Wang ++ ++ * config/i386/i386-options.cc (ix86_valid_target_attribute_tree): ++ Override tune_string with arch_string if tune_string is not ++ explicitly specified. ++ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-06-02 Thomas Schwinge ++ ++ PR testsuite/66005 ++ * doc/install.texi: Document (optional) Perl usage for parallel ++ testing of libgomp. ++ ++2023-06-28 liuhongt ++ ++ * config/i386/i386-features.cc (pass_insert_vzeroupper:gate): ++ Move flag_expensive_optimizations && !optimize_size to .. ++ * config/i386/i386-options.cc (ix86_option_override_internal): ++ .. this, it makes -mvzeroupper independent of optimization ++ level, but still keeps the behavior of architecture ++ tuning(emit_vzeroupper) unchanged. ++ ++2023-06-27 Andrew Pinski ++ ++ Backported from master: ++ 2023-06-27 Andrew Pinski ++ ++ PR middle-end/110420 ++ PR middle-end/103979 ++ PR middle-end/98619 ++ * gimplify.cc (gimplify_asm_expr): Mark asm with labels as volatile. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-06-19 Richard Biener ++ ++ PR tree-optimization/110298 ++ * tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely): ++ Clear number of iterations info before cleaning up the CFG. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-06-09 Richard Biener ++ ++ PR middle-end/110182 ++ * match.pd (two conversions in a row): Use element_precision ++ to DTRT for VECTOR_TYPE. ++ ++2023-06-22 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110132 ++ * config/aarch64/aarch64-builtins.cc (aarch64_general_simulate_builtin): ++ New. Use it ... ++ (aarch64_init_ls64_builtins): ... here. Switch to declaring public ACLE ++ names for builtins. ++ (aarch64_general_init_builtins): Ensure we invoke the arm_acle.h ++ setup if in_lto_p, just like we do for SVE. ++ * config/aarch64/arm_acle.h: (__arm_ld64b): Delete. ++ (__arm_st64b): Delete. ++ (__arm_st64bv): Delete. ++ (__arm_st64bv0): Delete. ++ ++2023-06-22 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110100 ++ * config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64): ++ Use input operand for the destination address. ++ * config/aarch64/aarch64.md (st64b): Fix constraint on address ++ operand. ++ ++2023-06-22 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110100 ++ * config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types): ++ Replace eight consecutive spaces with tabs. ++ (aarch64_init_ls64_builtins): Likewise. ++ (aarch64_expand_builtin_ls64): Likewise. ++ * config/aarch64/aarch64.md (ld64b): Likewise. ++ (st64b): Likewise. ++ (st64bv): Likewise ++ (st64bv0): Likewise. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-12 Kewen Lin ++ ++ PR target/109932 ++ * config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128, ++ __builtin_unpack_vector_int128): Move from stanza power7 to vsx. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-12 Kewen Lin ++ ++ PR target/110011 ++ * config/rs6000/rs6000.cc (output_toc): Use the mode of the 128-bit ++ floating constant itself for real_to_target call. ++ ++2023-06-15 Lulu Cheng ++ ++ Backported from master: ++ 2023-06-15 Lulu Cheng ++ Andrew Pinski ++ ++ PR target/110136 ++ * config/loongarch/loongarch.md: Modify the register constraints for template ++ "jumptable" and "indirect_jump" from "r" to "e". ++ ++2023-06-12 Richard Biener ++ ++ Backported from master: ++ 2023-06-12 Richard Biener ++ ++ PR middle-end/110200 ++ * genmatch.cc (expr::gen_transform): Put braces around ++ the if arm for the (convert ...) short-cut. ++ ++2023-06-10 Georg-Johann Lay ++ ++ PR target/109650 ++ PR target/92729 ++ Backport from 2023-05-10 master r14-1688. ++ * config/avr/avr-passes.def (avr_pass_ifelse): Insert new pass. ++ * config/avr/avr.cc (avr_pass_ifelse): New RTL pass. ++ (avr_pass_data_ifelse): New pass_data for it. ++ (make_avr_pass_ifelse, avr_redundant_compare, avr_cbranch_cost) ++ (avr_canonicalize_comparison, avr_out_plus_set_ZN) ++ (avr_out_cmp_ext): New functions. ++ (compare_condtition): Make sure REG_CC dies in the branch insn. ++ (avr_rtx_costs_1): Add computation of cbranch costs. ++ (avr_adjust_insn_length) [ADJUST_LEN_ADD_SET_ZN, ADJUST_LEN_CMP_ZEXT]: ++ [ADJUST_LEN_CMP_SEXT]Handle them. ++ (TARGET_CANONICALIZE_COMPARISON): New define. ++ (avr_simplify_comparison_p, compare_diff_p, avr_compare_pattern) ++ (avr_reorg_remove_redundant_compare, avr_reorg): Remove functions. ++ (TARGET_MACHINE_DEPENDENT_REORG): Remove define. ++ * config/avr/avr-protos.h (avr_simplify_comparison_p): Remove proto. ++ (make_avr_pass_ifelse, avr_out_plus_set_ZN, cc_reg_rtx) ++ (avr_out_cmp_zext): New Protos ++ * config/avr/avr.md (branch, difficult_branch): Don't split insns. ++ (*cbranchhi.zero-extend.0", *cbranchhi.zero-extend.1") ++ (*swapped_tst, *add.for.eqne.): New insns. ++ (*cbranch4): Rename to cbranch4_insn. ++ (define_peephole): Add dead_or_set_regno_p(insn,REG_CC) as needed. ++ (define_deephole2): Add peep2_regno_dead_p(*,REG_CC) as needed. ++ Add new RTL peepholes for decrement-and-branch and *swapped_tst. ++ Rework signtest-and-branch peepholes for *sbrx_branch. ++ (adjust_len) [add_set_ZN, cmp_zext]: New. ++ (QIPSI): New mode iterator. ++ (ALLs1, ALLs2, ALLs4, ALLs234): New mode iterators. ++ (gelt): New code iterator. ++ (gelt_eqne): New code attribute. ++ (rvbranch, *rvbranch, difficult_rvbranch, *difficult_rvbranch) ++ (branch_unspec, *negated_tst, *reversed_tst) ++ (*cmpqi_sign_extend): Remove insns. ++ (define_c_enum "unspec") [UNSPEC_IDENTITY]: Remove. ++ * config/avr/avr-dimode.md (cbranch4): Canonicalize comparisons. ++ * config/avr/predicates.md (scratch_or_d_register_operand): New. ++ * config/avr/constraints.md (Yxx): New constraint. ++ ++2023-06-09 Jeevitha Palanisamy ++ ++ Backported from master: ++ 2023-06-06 Jeevitha Palanisamy ++ ++ PR target/106907 ++ * config/rs6000/rs6000.cc (vec_const_128bit_to_bytes): Remove ++ duplicate expression. ++ ++2023-06-09 Iain Sandoe ++ ++ Backported from master: ++ 2023-06-02 Iain Sandoe ++ ++ PR target/110044 ++ * config/rs6000/rs6000.cc (darwin_rs6000_special_round_type_align): ++ Make sure that we do not have a cap on field alignment before altering ++ the struct layout based on the type alignment of the first entry. ++ ++2023-06-09 liuhongt ++ ++ PR target/110108 ++ * config/i386/i386.cc (ix86_gimple_fold_builtin): Explicitly ++ view_convert_expr mask to signed type when folding pblendvb ++ builtins. ++ ++2023-06-08 Alex Coplan ++ ++ Backported from master: ++ 2023-05-25 Alex Coplan ++ ++ PR target/109800 ++ * config/arm/arm.md (movdf): Generate temporary pseudo in DImode ++ instead of DFmode. ++ * config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an ++ lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into ++ DFmode as an rvalue. ++ ++2023-06-08 Kyrylo Tkachov ++ ++ Backported from master: ++ 2023-05-24 Kyrylo Tkachov ++ ++ PR target/109939 ++ * config/arm/arm-builtins.cc (SAT_BINOP_UNSIGNED_IMM_QUALIFIERS): Use ++ qualifier_none for the return operand. ++ ++2023-06-02 Georg-Johann Lay ++ ++ PR target/110088 ++ * config/avr/avr.md: Add an RTL peephole to optimize operations on ++ non-LD_REGS after a move from LD_REGS. ++ (piaop): New code iterator. ++ ++2023-06-01 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-01 Jonathan Wakely ++ ++ PR target/109954 ++ * doc/invoke.texi (x86 Options): Fix description of -m32 option. ++ ++2023-05-30 Andreas Schwab ++ ++ PR target/110036 ++ * config/riscv/riscv.cc (riscv_asan_shadow_offset): Update to ++ match libsanitizer. ++ ++2023-05-25 Georg-Johann Lay ++ ++ PR target/104327 ++ * config/avr/avr.cc (avr_can_inline_p): New static function. ++ (TARGET_CAN_INLINE_P): Define to that function. ++ ++2023-05-25 Georg-Johann Lay ++ ++ PR target/82931 ++ * config/avr/avr.md (*movbitqi.0): Rename to *movbit.0-6. ++ Handle any bit position and use mode QISI. ++ * config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost ++ of 2 insns for bit-transfer of respective style. ++ ++2023-05-23 Georg-Johann Lay ++ ++ * config/avr/avr.cc (avr_insn_cost): New static function. ++ (TARGET_INSN_COST): Define to that function. ++ ++2023-05-22 Michael Meissner ++ ++ PR target/70243 ++ * config/rs6000/vsx.md (vsx_fmav4sf4): Do not generate vmaddfp. ++ (vsx_nfmsv4sf4): Do not generate vnmsubfp. Back port from master ++ 04/10/2023 change. ++ ++2023-05-22 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-21 Jakub Jelinek ++ ++ PR tree-optimization/109505 ++ * match.pd ((x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2), ++ Combine successive equal operations with constants, ++ (A +- CST1) +- CST2 -> A + CST3, (CST1 - A) +- CST2 -> CST3 - A, ++ CST1 - (CST2 - A) -> CST3 + A): Use ! on ops with 2 CONSTANT_CLASS_P ++ operands. ++ ++2023-05-22 Kewen Lin ++ ++ Backported from master: ++ 2023-05-17 Kewen Lin ++ ++ * tree-vect-loop.cc (vect_analyze_loop_1): Don't retry analysis with ++ suggested unroll factor once the previous analysis fails. ++ ++2023-05-20 Triffid Hunter ++ ++ PR target/105753 ++ Backport from 2023-05-20 https://gcc.gnu.org/r14-1016 ++ * config/avr/avr.md (divmodpsi, udivmodpsi, divmodsi, udivmodsi): ++ Remove superfluous "parallel" in insn pattern. ++ ([u]divmod4): Tidy code. Use gcc_unreachable() instead of ++ printing error text to assembly. ++ ++2023-05-18 Alexandre Oliva ++ ++ * config/arm/vfp.md (*thumb2_movsi_vfp): Drop blank after tab ++ after vmsr and vmrs, and lower the case of P0. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer types. ++ (__ARM_mve_coerce1): Remove. ++ (__ARM_mve_coerce2): Remove. ++ (__ARM_mve_coerce3): Remove. ++ (__ARM_mve_coerce_i_scalar): New. ++ (__ARM_mve_coerce_s8_ptr): New. ++ (__ARM_mve_coerce_u8_ptr): New. ++ (__ARM_mve_coerce_s16_ptr): New. ++ (__ARM_mve_coerce_u16_ptr): New. ++ (__ARM_mve_coerce_s32_ptr): New. ++ (__ARM_mve_coerce_u32_ptr): New. ++ (__ARM_mve_coerce_s64_ptr): New. ++ (__ARM_mve_coerce_u64_ptr): New. ++ (__ARM_mve_coerce_f_scalar): New. ++ (__ARM_mve_coerce_f16_ptr): New. ++ (__ARM_mve_coerce_f32_ptr): New. ++ (__arm_vst4q): Change _coerce_ overloads. ++ (__arm_vbicq): Change _coerce_ overloads. ++ (__arm_vmulq): Change _coerce_ overloads. ++ (__arm_vcmpeqq): Change _coerce_ overloads. ++ (__arm_vcmpneq): Change _coerce_ overloads. ++ (__arm_vmaxnmavq): Change _coerce_ overloads. ++ (__arm_vmaxnmvq): Change _coerce_ overloads. ++ (__arm_vminnmavq): Change _coerce_ overloads. ++ (__arm_vsubq): Change _coerce_ overloads. ++ (__arm_vminnmvq): Change _coerce_ overloads. ++ (__arm_vrshlq): Change _coerce_ overloads. ++ (__arm_vqsubq): Change _coerce_ overloads. ++ (__arm_vqdmulltq): Change _coerce_ overloads. ++ (__arm_vqdmullbq): Change _coerce_ overloads. ++ (__arm_vqdmulhq): Change _coerce_ overloads. ++ (__arm_vqaddq): Change _coerce_ overloads. ++ (__arm_vhaddq): Change _coerce_ overloads. ++ (__arm_vhsubq): Change _coerce_ overloads. ++ (__arm_vqdmlashq): Change _coerce_ overloads. ++ (__arm_vqrdmlahq): Change _coerce_ overloads. ++ (__arm_vmlasq): Change _coerce_ overloads. ++ (__arm_vqdmlahq): Change _coerce_ overloads. ++ (__arm_vmaxnmavq_p): Change _coerce_ overloads. ++ (__arm_vmaxnmvq_p): Change _coerce_ overloads. ++ (__arm_vminnmavq_p): Change _coerce_ overloads. ++ (__arm_vminnmvq_p): Change _coerce_ overloads. ++ (__arm_vfmasq_m): Change _coerce_ overloads. ++ (__arm_vld1q): Change _coerce_ overloads. ++ (__arm_vld1q_z): Change _coerce_ overloads. ++ (__arm_vld2q): Change _coerce_ overloads. ++ (__arm_vld4q): Change _coerce_ overloads. ++ (__arm_vldrhq_gather_offset): Change _coerce_ overloads. ++ (__arm_vldrhq_gather_offset_z): Change _coerce_ overloads. ++ (__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads. ++ (__arm_vldrhq_gather_shifted_offset_z): Change _coerce_ overloads. ++ (__arm_vldrwq_gather_offset): Change _coerce_ overloads. ++ (__arm_vldrwq_gather_offset_z): Change _coerce_ overloads. ++ (__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads. ++ (__arm_vldrwq_gather_shifted_offset_z): Change _coerce_ overloads. ++ (__arm_vst1q_p): Change _coerce_ overloads. ++ (__arm_vst2q): Change _coerce_ overloads. ++ (__arm_vst1q): Change _coerce_ overloads. ++ (__arm_vstrhq): Change _coerce_ overloads. ++ (__arm_vstrhq_p): Change _coerce_ overloads. ++ (__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads. ++ (__arm_vstrhq_scatter_offset): Change _coerce_ overloads. ++ (__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_ overloads. ++ (__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads. ++ (__arm_vstrwq_p): Change _coerce_ overloads. ++ (__arm_vstrwq): Change _coerce_ overloads. ++ (__arm_vstrwq_scatter_offset): Change _coerce_ overloads. ++ (__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads. ++ (__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads. ++ (__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_ overloads. ++ (__arm_vsetq_lane): Change _coerce_ overloads. ++ (__arm_vcmpneq_m): Change _coerce_ overloads. ++ (__arm_vldrbq_gather_offset): Change _coerce_ overloads. ++ (__arm_vdwdupq_x_u8): Change _coerce_ overloads. ++ (__arm_vdwdupq_x_u16): Change _coerce_ overloads. ++ (__arm_vdwdupq_x_u32): Change _coerce_ overloads. ++ (__arm_viwdupq_x_u8): Change _coerce_ overloads. ++ (__arm_viwdupq_x_u16): Change _coerce_ overloads. ++ (__arm_viwdupq_x_u32): Change _coerce_ overloads. ++ (__arm_vidupq_x_u8): Change _coerce_ overloads. ++ (__arm_vddupq_x_u8): Change _coerce_ overloads. ++ (__arm_vidupq_x_u16): Change _coerce_ overloads. ++ (__arm_vddupq_x_u16): Change _coerce_ overloads. ++ (__arm_vidupq_x_u32): Change _coerce_ overloads. ++ (__arm_vddupq_x_u32): Change _coerce_ overloads. ++ (__arm_vhaddq_x): Change _coerce_ overloads. ++ (__arm_vhsubq_x): Change _coerce_ overloads. ++ (__arm_vldrdq_gather_offset): Change _coerce_ overloads. ++ (__arm_vldrdq_gather_offset_z): Change _coerce_ overloads. ++ (__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads. ++ (__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads. ++ (__arm_vldrbq_gather_offset_z): Change _coerce_ overloads. ++ (__arm_vqrdmlahq_m): Change _coerce_ overloads. ++ (__arm_vqrdmlashq_m): Change _coerce_ overloads. ++ (__arm_vqdmlashq_m): Change _coerce_ overloads. ++ (__arm_vmlaldavaxq_p): Change _coerce_ overloads. ++ (__arm_vmlasq_m): Change _coerce_ overloads. ++ (__arm_vqdmulhq_m): Change _coerce_ overloads. ++ (__arm_vqdmulltq_m): Change _coerce_ overloads. ++ (__arm_vidupq_u16): Change _coerce_ overloads. ++ (__arm_vidupq_u32): Change _coerce_ overloads. ++ (__arm_vidupq_u8): Change _coerce_ overloads. ++ (__arm_vddupq_u16): Change _coerce_ overloads. ++ (__arm_vddupq_u32): Change _coerce_ overloads. ++ (__arm_vddupq_u8): Change _coerce_ overloads. ++ (__arm_viwdupq_m): Change _coerce_ overloads. ++ (__arm_viwdupq_u16): Change _coerce_ overloads. ++ (__arm_viwdupq_u32): Change _coerce_ overloads. ++ (__arm_viwdupq_u8): Change _coerce_ overloads. ++ (__arm_vdwdupq_m): Change _coerce_ overloads. ++ (__arm_vdwdupq_u16): Change _coerce_ overloads. ++ (__arm_vdwdupq_u32): Change _coerce_ overloads. ++ (__arm_vdwdupq_u8): Change _coerce_ overloads. ++ (__arm_vaddlvaq): Change _coerce_ overloads. ++ (__arm_vaddlvaq_p): Change _coerce_ overloads. ++ (__arm_vaddvaq): Change _coerce_ overloads. ++ (__arm_vaddvaq_p): Change _coerce_ overloads. ++ (__arm_vcmphiq_m): Change _coerce_ overloads. ++ (__arm_vmladavaq_p): Change _coerce_ overloads. ++ (__arm_vmladavaxq): Change _coerce_ overloads. ++ (__arm_vmlaldavaxq): Change _coerce_ overloads. ++ (__arm_vstrbq): Change _coerce_ overloads. ++ (__arm_vstrbq_p): Change _coerce_ overloads. ++ (__arm_vrmlaldavhaq_p): Change _coerce_ overloads. ++ (__arm_vstrbq_scatter_offset): Change _coerce_ overloads. ++ (__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads. ++ (__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads. ++ (__arm_vstrdq_scatter_offset): Change _coerce_ overloads. ++ (__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_ overloads. ++ (__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * config/arm/arm_mve.h (__arm_vbicq): Change coerce on ++ scalar constant. ++ (__arm_vmvnq_m): Likewise. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * config/arm/arm_mve.h (__arm_vorrq): Add _n variant. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2023-05-18 Stam Markianos-Wright ++ ++ * config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic. ++ (__arm_vadcq_u32): Likewise. ++ (__arm_vadcq_m_s32): Likewise. ++ (__arm_vadcq_m_u32): Likewise. ++ (__arm_vsbcq_s32): Likewise. ++ (__arm_vsbcq_u32): Likewise. ++ (__arm_vsbcq_m_s32): Likewise. ++ (__arm_vsbcq_m_u32): Likewise. ++ * config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile. ++ ++2023-05-18 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vrndq_m_f, mve_vrev64q_f) ++ (mve_vrev32q_fv8hf, mve_vcvttq_f32_f16v4sf) ++ (mve_vcvtbq_f32_f16v4sf, mve_vcvtq_to_f_) ++ (mve_vrev64q_, mve_vcvtq_from_f_) ++ (mve_vmovltq_, mve_vmovlbq_) ++ (mve_vcvtpq_, mve_vcvtnq_) ++ (mve_vcvtmq_, mve_vcvtaq_) ++ (mve_vmvnq_n_, mve_vrev16q_v16qi) ++ (mve_vctpqhi, mve_vbrsrq_n_f) ++ (mve_vbrsrq_n_, mve_vandq_f, mve_vbicq_f) ++ (mve_vbicq_n_, mve_vctpq_mhi) ++ (mve_vcvtbq_f16_f32v8hf, mve_vcvttq_f16_f32v8hf) ++ (mve_veorq_f, mve_vmlaldavxq_s, mve_vmlsldavq_s) ++ (mve_vmlsldavxq_s, mve_vornq_f, mve_vorrq_f) ++ (mve_vrmlaldavhxq_sv4si, mve_vbicq_m_n_) ++ (mve_vcvtq_m_to_f_, mve_vshlcq_) ++ (mve_vmvnq_m_, mve_vpselq_) ++ (mve_vcvtbq_m_f16_f32v8hf, mve_vcvtbq_m_f32_f16v4sf) ++ (mve_vcvttq_m_f16_f32v8hf, mve_vcvttq_m_f32_f16v4sf) ++ (mve_vmlaldavq_p_, mve_vmlsldavaq_s) ++ (mve_vmlsldavaxq_s, mve_vmlsldavq_p_s) ++ (mve_vmlsldavxq_p_s, mve_vmvnq_m_n_) ++ (mve_vorrq_m_n_, mve_vpselq_f) ++ (mve_vrev32q_m_fv8hf, mve_vrev32q_m_) ++ (mve_vrev64q_m_f, mve_vrmlaldavhaxq_sv4si) ++ (mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhaxq_sv4si) ++ (mve_vrmlsldavhq_p_sv4si, mve_vrmlsldavhxq_p_sv4si) ++ (mve_vrev16q_m_v16qi, mve_vrmlaldavhq_p_v4si) ++ (mve_vrmlsldavhaq_sv4si, mve_vandq_m_) ++ (mve_vbicq_m_, mve_veorq_m_) ++ (mve_vornq_m_, mve_vorrq_m_) ++ (mve_vandq_m_f, mve_vbicq_m_f, mve_veorq_m_f) ++ (mve_vornq_m_f, mve_vorrq_m_f) ++ (mve_vstrdq_scatter_shifted_offset_p_v2di_insn) ++ (mve_vstrdq_scatter_shifted_offset_v2di_insn) ++ (mve_vstrdq_scatter_base_wb_p_v2di) : Fix spacing and ++ capitalization in the emitted asm. ++ ++2023-05-18 Andrea Corallo ++ ++ * config/arm/constraints.md (mve_vldrd_immediate): Move it to ++ predicates.md. ++ (Ri): Move constraint definition from predicates.md. ++ (Rl): Define new constraint. ++ * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_v4si): Add ++ missing constraint. ++ (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint ++ for op 1, use mve_vstrw_immediate predicate and Rl constraint for ++ op 2. Fix asm output spacing. ++ (mve_vstrdq_scatter_base_wb_p_v2di): Add missing constraint. ++ * config/arm/predicates.md (Ri) Move constraint to constraints.md ++ (mve_vldrd_immediate): Move it from ++ constraints.md. ++ (mve_vstrw_immediate): New predicate. ++ ++2023-05-18 Murray Steele ++ ++ Backported from master: ++ 2023-01-18 Murray Steele ++ ++ PR target/108442 ++ * config/arm/arm_mve.h (__arm_vst1q_p_u8): Use prefixed intrinsic ++ function. ++ (__arm_vst1q_p_s8): Likewise. ++ (__arm_vld1q_z_u8): Likewise. ++ (__arm_vld1q_z_s8): Likewise. ++ (__arm_vst1q_p_u16): Likewise. ++ (__arm_vst1q_p_s16): Likewise. ++ (__arm_vld1q_z_u16): Likewise. ++ (__arm_vld1q_z_s16): Likewise. ++ (__arm_vst1q_p_u32): Likewise. ++ (__arm_vst1q_p_s32): Likewise. ++ (__arm_vld1q_z_u32): Likewise. ++ (__arm_vld1q_z_s32): Likewise. ++ (__arm_vld1q_z_f16): Likewise. ++ (__arm_vst1q_p_f16): Likewise. ++ (__arm_vld1q_z_f32): Likewise. ++ (__arm_vst1q_p_f32): Likewise. ++ ++2023-05-18 Andre Vieira ++ ++ Backported from master: ++ 2023-01-24 Andre Vieira ++ ++ PR target/108177 ++ * config/arm/mve.md (mve_vstrbq_p_, mve_vstrhq_p_fv8hf, ++ mve_vstrhq_p_, mve_vstrwq_p_v4si): Add memory operand ++ as input operand. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2023-04-04 Stam Markianos-Wright ++ ++ * config/arm/mve.md (mve_vcvtq_n_to_f_): Swap operands. ++ (mve_vcreateq_f): Swap operands. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2023-01-16 Stam Markianos-Wright ++ ++ PR target/96795 ++ PR target/107515 ++ * config/arm/arm_mve.h (__ARM_mve_coerce2): Split types. ++ (__ARM_mve_coerce3): Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vqnegq_s): Fix spacing. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vqabsq_s): Fix spacing. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vnegq_f, mve_vnegq_s): ++ Fix spacing. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * config/arm/mve.md (@mve_vclzq_s): Fix spacing. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vclsq_s): Fix spacing. ++ ++2023-05-18 Christophe Lyon ++ ++ Backported from master: ++ 2023-02-03 Christophe Lyon ++ ++ * config/arm/mve.md (mve_vabavq_p_): Add length ++ attribute. ++ (mve_vqshluq_m_n_s): Likewise. ++ (mve_vshlq_m_): Likewise. ++ (mve_vsriq_m_n_): Likewise. ++ (mve_vsubq_m_): Likewise. ++ ++2023-05-18 Christophe Lyon ++ ++ Backported from master: ++ 2022-10-03 Christophe Lyon ++ ++ * config/arm/mve.md (mve_vrev64q_m_): Add early ++ clobber. ++ (mve_vrev64q_m_f): Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vrmlaldavhq_v4si, ++ mve_vrmlaldavhaq_v4si): Fix spacing vs tabs. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vmlaldavaq_) ++ (mve_vmlaldavaxq_s, mve_vmlaldavaxq_p_): Fix ++ spacing vs tabs. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vsubq_n_f): Fix spacing. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vaddlvq_p_v4si) ++ (mve_vaddq_n_, mve_vaddvaq_) ++ (mve_vaddlvaq_v4si, mve_vaddq_n_f) ++ (mve_vaddlvaq_p_v4si, mve_vaddq, mve_vaddq_f): ++ Fix spacing. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2022-11-28 Stam Markianos-Wright ++ ++ * config/arm/arm_mve.h (__arm_vsubq_x FP): New overloads. ++ (__arm_vsubq_x Integer): New. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2022-11-28 Stam Markianos-Wright ++ ++ PR target/107515 ++ * config/arm/arm_mve.h (__ARM_mve_typeid): Add float types. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2022-11-28 Stam Markianos-Wright ++ ++ PR target/96795 ++ * config/arm/arm_mve.h (__arm_vaddq): Fix Overloading. ++ (__arm_vmulq): Likewise. ++ (__arm_vcmpeqq): Likewise. ++ (__arm_vcmpneq): Likewise. ++ (__arm_vmaxnmavq): Likewise. ++ (__arm_vmaxnmvq): Likewise. ++ (__arm_vminnmavq): Likewise. ++ (__arm_vsubq): Likewise. ++ (__arm_vminnmvq): Likewise. ++ (__arm_vrshlq): Likewise. ++ (__arm_vqsubq): Likewise. ++ (__arm_vqdmulltq): Likewise. ++ (__arm_vqdmullbq): Likewise. ++ (__arm_vqdmulhq): Likewise. ++ (__arm_vqaddq): Likewise. ++ (__arm_vhaddq): Likewise. ++ (__arm_vhsubq): Likewise. ++ (__arm_vqdmlashq): Likewise. ++ (__arm_vqrdmlahq): Likewise. ++ (__arm_vmlasq): Likewise. ++ (__arm_vqdmlahq): Likewise. ++ (__arm_vmaxnmavq_p): Likewise. ++ (__arm_vmaxnmvq_p): Likewise. ++ (__arm_vminnmavq_p): Likewise. ++ (__arm_vminnmvq_p): Likewise. ++ (__arm_vfmasq_m): Likewise. ++ (__arm_vsetq_lane): Likewise. ++ (__arm_vcmpneq_m): Likewise. ++ (__arm_vhaddq_x): Likewise. ++ (__arm_vhsubq_x): Likewise. ++ (__arm_vqrdmlashq_m): Likewise. ++ (__arm_vqdmlashq_m): Likewise. ++ (__arm_vmlaldavaxq_p): Likewise. ++ (__arm_vmlasq_m): Likewise. ++ (__arm_vqdmulhq_m): Likewise. ++ (__arm_vqdmulltq_m): Likewise. ++ (__arm_viwdupq_m): Likewise. ++ (__arm_viwdupq_u16): Likewise. ++ (__arm_viwdupq_u32): Likewise. ++ (__arm_viwdupq_u8): Likewise. ++ (__arm_vdwdupq_m): Likewise. ++ (__arm_vdwdupq_u16): Likewise. ++ (__arm_vdwdupq_u32): Likewise. ++ (__arm_vdwdupq_u8): Likewise. ++ (__arm_vaddlvaq): Likewise. ++ (__arm_vaddlvaq_p): Likewise. ++ (__arm_vaddvaq): Likewise. ++ (__arm_vaddvaq_p): Likewise. ++ (__arm_vcmphiq_m): Likewise. ++ (__arm_vmladavaq_p): Likewise. ++ (__arm_vmladavaxq): Likewise. ++ (__arm_vmlaldavaxq): Likewise. ++ (__arm_vrmlaldavhaq_p): Likewise. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2022-11-28 Stam Markianos-Wright ++ ++ PR target/96795 ++ * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Change types. ++ (__arm_vaddq_m_n_s32): Likewise. ++ (__arm_vaddq_m_n_s16): Likewise. ++ (__arm_vaddq_m_n_u8): Likewise. ++ (__arm_vaddq_m_n_u32): Likewise. ++ (__arm_vaddq_m_n_u16): Likewise. ++ (__arm_vaddq_m): Fix Overloading. ++ (__ARM_mve_coerce3): New. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vabsq_f): Fix spacing. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/mve.md (@mve_vcmpq_): Fix ++ spacing. ++ * config/arm/arm_mve.h (__arm_vcmpgtq_m, __arm_vcmpleq_m) ++ (__arm_vcmpltq_m, __arm_vcmpneq_m): Add missing defines. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vdupq_n_f) ++ (mve_vdupq_n_, mve_vdupq_m_n_) ++ (mve_vdupq_m_n_f): Fix spacing. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vdwdupq_m_wb_u_insn): Fix spacing. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/mve.md (mve_vddupq_u_insn): Fix 'vddup.u' ++ spacing. ++ (mve_vddupq_m_wb_u_insn): Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix ++ 'vmsr' spacing and reg capitalization. ++ ++2023-05-15 liuhongt ++ ++ * config/i386/cygwin.h (ENDFILE_SPEC): Link crtfastmath.o ++ whenever -mdaz-ftz is specified. Don't link crtfastmath.o ++ when -mno-daz-ftz is specified. ++ * config/i386/darwin.h (ENDFILE_SPEC): Ditto. ++ * config/i386/gnu-user-common.h ++ (GNU_USER_TARGET_MATHFILE_SPEC): Ditto. ++ * config/i386/mingw32.h (ENDFILE_SPEC): Ditto. ++ * config/i386/i386.opt (mdaz-ftz): New option. ++ * doc/invoke.texi (x86 options): Document mftz-daz. ++ ++2023-05-09 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-09 Jakub Jelinek ++ ++ PR tree-optimization/109778 ++ * wide-int.h (wi::lrotate, wi::rrotate): Call wi::lrshift on ++ wi::zext (x, width) rather than x if width != precision, rather ++ than using wi::zext (right, width) after the shift. ++ * tree-ssa-ccp.cc (bit_value_binop): Call wi::ext on the results ++ of wi::lrotate or wi::rrotate. ++ ++2023-05-09 Kewen Lin ++ ++ Backported from master: ++ 2023-04-26 Kewen Lin ++ ++ PR target/108758 ++ * config/rs6000/rs6000-builtins.def ++ (__builtin_vsx_scalar_cmp_exp_qp_eq, __builtin_vsx_scalar_cmp_exp_qp_gt ++ __builtin_vsx_scalar_cmp_exp_qp_lt, ++ __builtin_vsx_scalar_cmp_exp_qp_unordered): Move from stanza ieee128-hw ++ to power9-vector. ++ ++2023-05-09 Kewen Lin ++ ++ Backported from master: ++ 2023-04-26 Kewen Lin ++ ++ PR target/109069 ++ * config/rs6000/altivec.md (sldoi_to_mov): Replace predicate ++ easy_vector_constant with const_vector_each_byte_same, add ++ handlings in preparation for !easy_vector_constant, and update ++ VECTOR_UNIT_ALTIVEC_OR_VSX_P with VECTOR_MEM_ALTIVEC_OR_VSX_P. ++ * config/rs6000/predicates.md (const_vector_each_byte_same): New ++ predicate. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP +index e50dc5212d2..53df0019683 100644 +--- a/gcc/DATESTAMP ++++ b/gcc/DATESTAMP +@@ -1 +1 @@ +-20230508 ++20240103 +diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog +index 442fec8c8c8..fa3ef826d32 100644 +--- a/gcc/ada/ChangeLog ++++ b/gcc/ada/ChangeLog +@@ -1,3 +1,8 @@ ++2023-11-16 Eric Botcazou ++ ++ * gcc-interface/decl.cc (gnat_to_gnu_subprog_type): Also create a ++ TYPE_DECL for the return type built for the CI/CO mechanism. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/gcc/ada/gcc-interface/decl.cc b/gcc/ada/gcc-interface/decl.cc +index 1c7a716840e..606c2fd0a76 100644 +--- a/gcc/ada/gcc-interface/decl.cc ++++ b/gcc/ada/gcc-interface/decl.cc +@@ -6207,6 +6207,12 @@ gnat_to_gnu_subprog_type (Entity_Id gnat_subprog, bool definition, + + if (debug_info_p) + rest_of_record_type_compilation (gnu_cico_return_type); ++ ++ /* Declare it now since it will never be declared otherwise. This ++ is necessary to ensure that its subtrees are properly marked. */ ++ create_type_decl (TYPE_NAME (gnu_cico_return_type), ++ gnu_cico_return_type, ++ true, debug_info_p, gnat_subprog); + } + + gnu_return_type = gnu_cico_return_type; +diff --git a/gcc/attribs.cc b/gcc/attribs.cc +index b219f878042..876277dd5b3 100644 +--- a/gcc/attribs.cc ++++ b/gcc/attribs.cc +@@ -578,9 +578,9 @@ attribute_ignored_p (tree attr) + return false; + if (tree ns = get_attribute_namespace (attr)) + { +- if (attr_namespace_ignored_p (ns)) +- return true; + const attribute_spec *as = lookup_attribute_spec (TREE_PURPOSE (attr)); ++ if (as == NULL && attr_namespace_ignored_p (ns)) ++ return true; + if (as && as->max_length == -2) + return true; + } +@@ -851,7 +851,10 @@ decl_attributes (tree *node, tree attributes, int flags, + } + } + +- if (no_add_attrs) ++ if (no_add_attrs ++ /* Don't add attributes registered just for -Wno-attributes=foo::bar ++ purposes. */ ++ || attribute_ignored_p (attr)) + continue; + + if (spec->handler != NULL) +diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog +index 054a5330ac6..c95461dc065 100644 +--- a/gcc/c-family/ChangeLog ++++ b/gcc/c-family/ChangeLog +@@ -1,3 +1,31 @@ ++2023-12-15 Richard Biener ++ ++ Backported from master: ++ 2023-08-31 Richard Biener ++ ++ PR middle-end/111253 ++ * c-pretty-print.cc (c_pretty_printer::primary_expression): ++ Only dump gimple_assign_single_p SSA def RHS. ++ ++2023-05-19 Patrick Palka ++ ++ Backported from master: ++ 2023-05-15 Patrick Palka ++ ++ * c-cppbuiltin.cc (c_cpp_builtins): Predefine __cpp_auto_cast ++ for C++23. ++ ++2023-05-09 Martin Uecker ++ ++ Backported from master: ++ 2023-02-18 Martin Uecker ++ ++ PR c/105660 ++ * c-attribs.cc (append_access_attr): Use order of arguments when ++ construction string. ++ (append_access_attr_idxs): Rename and make static. ++ * c-warn.cc (warn_parm_array_mismatch): Add assertion. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/gcc/c-family/c-attribs.cc b/gcc/c-family/c-attribs.cc +index 111a33f405a..8221733613e 100644 +--- a/gcc/c-family/c-attribs.cc ++++ b/gcc/c-family/c-attribs.cc +@@ -4624,22 +4624,27 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr, + rdwr_map cur_idxs; + init_attr_rdwr_indices (&cur_idxs, attrs); + ++ tree args = TYPE_ARG_TYPES (node[0]); ++ int argpos = 0; + std::string spec; +- for (auto it = new_idxs.begin (); it != new_idxs.end (); ++it) ++ for (tree arg = args; arg; arg = TREE_CHAIN (arg), argpos++) + { +- const auto &newaxsref = *it; ++ const attr_access* const newa = new_idxs.get (argpos); ++ ++ if (!newa) ++ continue; + + /* The map has two equal entries for each pointer argument that + has an associated size argument. Process just the entry for + the former. */ +- if ((unsigned)newaxsref.first != newaxsref.second.ptrarg) ++ if ((unsigned)argpos != newa->ptrarg) + continue; + +- const attr_access* const cura = cur_idxs.get (newaxsref.first); ++ const attr_access* const cura = cur_idxs.get (argpos); + if (!cura) + { + /* The new attribute needs to be added. */ +- tree str = newaxsref.second.to_internal_string (); ++ tree str = newa->to_internal_string (); + spec += TREE_STRING_POINTER (str); + continue; + } +@@ -4647,7 +4652,6 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr, + /* The new access spec refers to an array/pointer argument for + which an access spec already exists. Check and diagnose any + conflicts. If no conflicts are found, merge the two. */ +- const attr_access* const newa = &newaxsref.second; + + if (!attrstr) + { +@@ -4782,7 +4786,7 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr, + continue; + + /* Merge the CURA and NEWA. */ +- attr_access merged = newaxsref.second; ++ attr_access merged = *newa; + + /* VLA seen in a declaration takes precedence. */ + if (cura->minsize == HOST_WIDE_INT_M1U) +@@ -4808,9 +4812,9 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr, + + /* Convenience wrapper for the above. */ + +-tree +-append_access_attr (tree node[3], tree attrs, const char *attrstr, +- char code, HOST_WIDE_INT idxs[2]) ++static tree ++append_access_attr_idxs (tree node[3], tree attrs, const char *attrstr, ++ char code, HOST_WIDE_INT idxs[2]) + { + char attrspec[80]; + int n = sprintf (attrspec, "%c%u", code, (unsigned) idxs[0] - 1); +@@ -5101,7 +5105,7 @@ handle_access_attribute (tree node[3], tree name, tree args, int flags, + attributes specified on previous declarations of the same type + and if not, concatenate the two. */ + const char code = attr_access::mode_chars[mode]; +- tree new_attrs = append_access_attr (node, attrs, attrstr, code, idxs); ++ tree new_attrs = append_access_attr_idxs (node, attrs, attrstr, code, idxs); + if (!new_attrs) + return NULL_TREE; + +@@ -5114,7 +5118,7 @@ handle_access_attribute (tree node[3], tree name, tree args, int flags, + { + /* Repeat for the previously declared type. */ + attrs = TYPE_ATTRIBUTES (TREE_TYPE (node[1])); +- new_attrs = append_access_attr (node, attrs, attrstr, code, idxs); ++ new_attrs = append_access_attr_idxs (node, attrs, attrstr, code, idxs); + if (!new_attrs) + return NULL_TREE; + +diff --git a/gcc/c-family/c-cppbuiltin.cc b/gcc/c-family/c-cppbuiltin.cc +index 4672ae8486a..c1b86c1fac0 100644 +--- a/gcc/c-family/c-cppbuiltin.cc ++++ b/gcc/c-family/c-cppbuiltin.cc +@@ -1080,6 +1080,7 @@ c_cpp_builtins (cpp_reader *pfile) + cpp_define (pfile, "__cpp_if_consteval=202106L"); + cpp_define (pfile, "__cpp_constexpr=202110L"); + cpp_define (pfile, "__cpp_multidimensional_subscript=202110L"); ++ cpp_define (pfile, "__cpp_auto_cast=202110L"); + } + if (flag_concepts) + { +diff --git a/gcc/c-family/c-pretty-print.cc b/gcc/c-family/c-pretty-print.cc +index 71a0cb51093..0c679c12d83 100644 +--- a/gcc/c-family/c-pretty-print.cc ++++ b/gcc/c-family/c-pretty-print.cc +@@ -33,6 +33,9 @@ along with GCC; see the file COPYING3. If not see + #include "langhooks.h" + #include "options.h" + #include "internal-fn.h" ++#include "function.h" ++#include "basic-block.h" ++#include "gimple.h" + + /* The pretty-printer code is primarily designed to closely follow + (GNU) C and C++ grammars. That is to be contrasted with spaghetti +@@ -1363,12 +1366,14 @@ c_pretty_printer::primary_expression (tree e) + else + primary_expression (var); + } +- else ++ else if (gimple_assign_single_p (SSA_NAME_DEF_STMT (e))) + { + /* Print only the right side of the GIMPLE assignment. */ + gimple *def_stmt = SSA_NAME_DEF_STMT (e); + pp_gimple_stmt_1 (this, def_stmt, 0, TDF_RHS_ONLY); + } ++ else ++ expression (e); + break; + + default: +diff --git a/gcc/c-family/c-warn.cc b/gcc/c-family/c-warn.cc +index 1e5a64260a3..9634351a4d3 100644 +--- a/gcc/c-family/c-warn.cc ++++ b/gcc/c-family/c-warn.cc +@@ -3628,6 +3628,8 @@ warn_parm_array_mismatch (location_t origloc, tree fndecl, tree newparms) + for (tree newvbl = newa->size, curvbl = cura->size; newvbl; + newvbl = TREE_CHAIN (newvbl), curvbl = TREE_CHAIN (curvbl)) + { ++ gcc_assert (curvbl); ++ + tree newpos = TREE_PURPOSE (newvbl); + tree curpos = TREE_PURPOSE (curvbl); + +diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h +index 0333da56ba5..316ad3cb3e9 100644 +--- a/gcc/common/config/i386/cpuinfo.h ++++ b/gcc/common/config/i386/cpuinfo.h +@@ -435,7 +435,6 @@ get_intel_cpu (struct __processor_model *cpu_model, + cpu_model->__cpu_subtype = INTEL_COREI7_SKYLAKE; + break; + case 0xa7: +- case 0xa8: + /* Rocket Lake. */ + cpu = "rocketlake"; + CHECK___builtin_cpu_is ("corei7"); +@@ -508,7 +507,6 @@ get_intel_cpu (struct __processor_model *cpu_model, + break; + case 0x97: + case 0x9a: +- case 0xbf: + /* Alder Lake. */ + cpu = "alderlake"; + CHECK___builtin_cpu_is ("corei7"); +@@ -649,7 +647,9 @@ get_available_features (struct __processor_model *cpu_model, + /* Get Advanced Features at level 7 (eax = 7, ecx = 0/1). */ + if (max_cpuid_level >= 7) + { +- __cpuid_count (7, 0, eax, ebx, ecx, edx); ++ unsigned int max_subleaf_level; ++ ++ __cpuid_count (7, 0, max_subleaf_level, ebx, ecx, edx); + if (ebx & bit_BMI) + set_feature (FEATURE_BMI); + if (ebx & bit_SGX) +@@ -761,18 +761,21 @@ get_available_features (struct __processor_model *cpu_model, + set_feature (FEATURE_AVX512FP16); + } + +- __cpuid_count (7, 1, eax, ebx, ecx, edx); +- if (eax & bit_HRESET) +- set_feature (FEATURE_HRESET); +- if (avx_usable) +- { +- if (eax & bit_AVXVNNI) +- set_feature (FEATURE_AVXVNNI); +- } +- if (avx512_usable) ++ if (max_subleaf_level >= 1) + { +- if (eax & bit_AVX512BF16) +- set_feature (FEATURE_AVX512BF16); ++ __cpuid_count (7, 1, eax, ebx, ecx, edx); ++ if (eax & bit_HRESET) ++ set_feature (FEATURE_HRESET); ++ if (avx_usable) ++ { ++ if (eax & bit_AVXVNNI) ++ set_feature (FEATURE_AVXVNNI); ++ } ++ if (avx512_usable) ++ { ++ if (eax & bit_AVX512BF16) ++ set_feature (FEATURE_AVX512BF16); ++ } + } + } + +diff --git a/gcc/config.in b/gcc/config.in +index 64c27c9cfac..cc638759a40 100644 +--- a/gcc/config.in ++++ b/gcc/config.in +@@ -672,6 +672,12 @@ + #endif + + ++/* Define if your assembler supports htm insns on power10. */ ++#ifndef USED_FOR_TARGET ++#undef HAVE_AS_POWER10_HTM ++#endif ++ ++ + /* Define if your assembler supports .ref */ + #ifndef USED_FOR_TARGET + #undef HAVE_AS_REF +diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc +index 42276e7caf7..197b763658c 100644 +--- a/gcc/config/aarch64/aarch64-builtins.cc ++++ b/gcc/config/aarch64/aarch64-builtins.cc +@@ -751,6 +751,16 @@ aarch64_general_add_builtin (const char *name, tree type, unsigned int code, + NULL, attrs); + } + ++static tree ++aarch64_general_simulate_builtin (const char *name, tree fntype, ++ unsigned int code, ++ tree attrs = NULL_TREE) ++{ ++ code = (code << AARCH64_BUILTIN_SHIFT) | AARCH64_BUILTIN_GENERAL; ++ return simulate_builtin_function_decl (input_location, name, fntype, ++ code, NULL, attrs); ++} ++ + static const char * + aarch64_mangle_builtin_scalar_type (const_tree type) + { +@@ -1634,11 +1644,11 @@ aarch64_init_ls64_builtins_types (void) + gcc_assert (TYPE_ALIGN (array_type) == 64); + + tree field = build_decl (input_location, FIELD_DECL, +- get_identifier ("val"), array_type); ++ get_identifier ("val"), array_type); + + ls64_arm_data_t = lang_hooks.types.simulate_record_decl (input_location, +- tuple_type_name, +- make_array_slice (&field, 1)); ++ tuple_type_name, ++ make_array_slice (&field, 1)); + + gcc_assert (TYPE_MODE (ls64_arm_data_t) == V8DImode); + gcc_assert (TYPE_MODE_RAW (ls64_arm_data_t) == TYPE_MODE (ls64_arm_data_t)); +@@ -1651,23 +1661,24 @@ aarch64_init_ls64_builtins (void) + aarch64_init_ls64_builtins_types (); + + ls64_builtins_data data[4] = { +- {"__builtin_aarch64_ld64b", AARCH64_LS64_BUILTIN_LD64B, ++ {"__arm_ld64b", AARCH64_LS64_BUILTIN_LD64B, + build_function_type_list (ls64_arm_data_t, +- const_ptr_type_node, NULL_TREE)}, +- {"__builtin_aarch64_st64b", AARCH64_LS64_BUILTIN_ST64B, ++ const_ptr_type_node, NULL_TREE)}, ++ {"__arm_st64b", AARCH64_LS64_BUILTIN_ST64B, + build_function_type_list (void_type_node, ptr_type_node, +- ls64_arm_data_t, NULL_TREE)}, +- {"__builtin_aarch64_st64bv", AARCH64_LS64_BUILTIN_ST64BV, ++ ls64_arm_data_t, NULL_TREE)}, ++ {"__arm_st64bv", AARCH64_LS64_BUILTIN_ST64BV, + build_function_type_list (uint64_type_node, ptr_type_node, +- ls64_arm_data_t, NULL_TREE)}, +- {"__builtin_aarch64_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0, ++ ls64_arm_data_t, NULL_TREE)}, ++ {"__arm_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0, + build_function_type_list (uint64_type_node, ptr_type_node, +- ls64_arm_data_t, NULL_TREE)}, ++ ls64_arm_data_t, NULL_TREE)}, + }; + + for (size_t i = 0; i < ARRAY_SIZE (data); ++i) + aarch64_builtin_decls[data[i].code] +- = aarch64_general_add_builtin (data[i].name, data[i].type, data[i].code); ++ = aarch64_general_simulate_builtin (data[i].name, data[i].type, ++ data[i].code); + } + + static void +@@ -1800,6 +1811,9 @@ aarch64_general_init_builtins (void) + + if (TARGET_MEMTAG) + aarch64_init_memtag_builtins (); ++ ++ if (in_lto_p) ++ handle_arm_acle_h (); + } + + /* Implement TARGET_BUILTIN_DECL for the AARCH64_BUILTIN_GENERAL group. */ +@@ -2281,40 +2295,40 @@ aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target) + { + case AARCH64_LS64_BUILTIN_LD64B: + { +- rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); +- create_output_operand (&ops[0], target, V8DImode); +- create_input_operand (&ops[1], op0, DImode); +- expand_insn (CODE_FOR_ld64b, 2, ops); +- return ops[0].value; ++ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); ++ create_output_operand (&ops[0], target, V8DImode); ++ create_input_operand (&ops[1], op0, DImode); ++ expand_insn (CODE_FOR_ld64b, 2, ops); ++ return ops[0].value; + } + case AARCH64_LS64_BUILTIN_ST64B: + { +- rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); +- rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); +- create_output_operand (&ops[0], op0, DImode); +- create_input_operand (&ops[1], op1, V8DImode); +- expand_insn (CODE_FOR_st64b, 2, ops); +- return const0_rtx; ++ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); ++ rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); ++ create_input_operand (&ops[0], op0, DImode); ++ create_input_operand (&ops[1], op1, V8DImode); ++ expand_insn (CODE_FOR_st64b, 2, ops); ++ return const0_rtx; + } + case AARCH64_LS64_BUILTIN_ST64BV: + { +- rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); +- rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); +- create_output_operand (&ops[0], target, DImode); +- create_input_operand (&ops[1], op0, DImode); +- create_input_operand (&ops[2], op1, V8DImode); +- expand_insn (CODE_FOR_st64bv, 3, ops); +- return ops[0].value; ++ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); ++ rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); ++ create_output_operand (&ops[0], target, DImode); ++ create_input_operand (&ops[1], op0, DImode); ++ create_input_operand (&ops[2], op1, V8DImode); ++ expand_insn (CODE_FOR_st64bv, 3, ops); ++ return ops[0].value; + } + case AARCH64_LS64_BUILTIN_ST64BV0: + { +- rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); +- rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); +- create_output_operand (&ops[0], target, DImode); +- create_input_operand (&ops[1], op0, DImode); +- create_input_operand (&ops[2], op1, V8DImode); +- expand_insn (CODE_FOR_st64bv0, 3, ops); +- return ops[0].value; ++ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); ++ rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); ++ create_output_operand (&ops[0], target, DImode); ++ create_input_operand (&ops[1], op0, DImode); ++ create_input_operand (&ops[2], op1, V8DImode); ++ expand_insn (CODE_FOR_st64bv0, 3, ops); ++ return ops[0].value; + } + } + +diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h +index 475d174dd39..9d99a021379 100644 +--- a/gcc/config/aarch64/aarch64-protos.h ++++ b/gcc/config/aarch64/aarch64-protos.h +@@ -781,6 +781,7 @@ bool aarch64_emit_approx_div (rtx, rtx, rtx); + bool aarch64_emit_approx_sqrt (rtx, rtx, bool); + tree aarch64_vector_load_decl (tree); + void aarch64_expand_call (rtx, rtx, rtx, bool); ++bool aarch64_expand_cpymem_mops (rtx *, bool); + bool aarch64_expand_cpymem (rtx *); + bool aarch64_expand_setmem (rtx *); + bool aarch64_float_const_zero_rtx_p (rtx); +diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc +index 226dc9dffd4..3bccd96a23d 100644 +--- a/gcc/config/aarch64/aarch64.cc ++++ b/gcc/config/aarch64/aarch64.cc +@@ -8133,18 +8133,32 @@ aarch64_needs_frame_chain (void) + return aarch64_use_frame_pointer; + } + ++/* Return true if the current function should save registers above ++ the locals area, rather than below it. */ ++ ++static bool ++aarch64_save_regs_above_locals_p () ++{ ++ /* When using stack smash protection, make sure that the canary slot ++ comes between the locals and the saved registers. Otherwise, ++ it would be possible for a carefully sized smash attack to change ++ the saved registers (particularly LR and FP) without reaching the ++ canary. */ ++ return crtl->stack_protect_guard; ++} ++ + /* Mark the registers that need to be saved by the callee and calculate + the size of the callee-saved registers area and frame record (both FP + and LR may be omitted). */ + static void + aarch64_layout_frame (void) + { +- poly_int64 offset = 0; + int regno, last_fp_reg = INVALID_REGNUM; + machine_mode vector_save_mode = aarch64_reg_save_mode (V8_REGNUM); + poly_int64 vector_save_size = GET_MODE_SIZE (vector_save_mode); + bool frame_related_fp_reg_p = false; + aarch64_frame &frame = cfun->machine->frame; ++ poly_int64 top_of_locals = -1; + + frame.emit_frame_chain = aarch64_needs_frame_chain (); + +@@ -8211,11 +8225,18 @@ aarch64_layout_frame (void) + && !crtl->abi->clobbers_full_reg_p (regno)) + frame.reg_offset[regno] = SLOT_REQUIRED; + +- /* With stack-clash, LR must be saved in non-leaf functions. The saving of +- LR counts as an implicit probe which allows us to maintain the invariant +- described in the comment at expand_prologue. */ +- gcc_assert (crtl->is_leaf +- || maybe_ne (frame.reg_offset[R30_REGNUM], SLOT_NOT_REQUIRED)); ++ bool regs_at_top_p = aarch64_save_regs_above_locals_p (); ++ ++ poly_int64 offset = crtl->outgoing_args_size; ++ gcc_assert (multiple_p (offset, STACK_BOUNDARY / BITS_PER_UNIT)); ++ if (regs_at_top_p) ++ { ++ offset += get_frame_size (); ++ offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT); ++ top_of_locals = offset; ++ } ++ frame.bytes_below_saved_regs = offset; ++ frame.sve_save_and_probe = INVALID_REGNUM; + + /* Now assign stack slots for the registers. Start with the predicate + registers, since predicate LDR and STR have a relatively small +@@ -8223,11 +8244,14 @@ aarch64_layout_frame (void) + for (regno = P0_REGNUM; regno <= P15_REGNUM; regno++) + if (known_eq (frame.reg_offset[regno], SLOT_REQUIRED)) + { ++ if (frame.sve_save_and_probe == INVALID_REGNUM) ++ frame.sve_save_and_probe = regno; + frame.reg_offset[regno] = offset; + offset += BYTES_PER_SVE_PRED; + } + +- if (maybe_ne (offset, 0)) ++ poly_int64 saved_prs_size = offset - frame.bytes_below_saved_regs; ++ if (maybe_ne (saved_prs_size, 0)) + { + /* If we have any vector registers to save above the predicate registers, + the offset of the vector register save slots need to be a multiple +@@ -8245,10 +8269,10 @@ aarch64_layout_frame (void) + offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT); + else + { +- if (known_le (offset, vector_save_size)) +- offset = vector_save_size; +- else if (known_le (offset, vector_save_size * 2)) +- offset = vector_save_size * 2; ++ if (known_le (saved_prs_size, vector_save_size)) ++ offset = frame.bytes_below_saved_regs + vector_save_size; ++ else if (known_le (saved_prs_size, vector_save_size * 2)) ++ offset = frame.bytes_below_saved_regs + vector_save_size * 2; + else + gcc_unreachable (); + } +@@ -8259,34 +8283,53 @@ aarch64_layout_frame (void) + for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++) + if (known_eq (frame.reg_offset[regno], SLOT_REQUIRED)) + { ++ if (frame.sve_save_and_probe == INVALID_REGNUM) ++ frame.sve_save_and_probe = regno; + frame.reg_offset[regno] = offset; + offset += vector_save_size; + } + + /* OFFSET is now the offset of the hard frame pointer from the bottom + of the callee save area. */ +- bool saves_below_hard_fp_p = maybe_ne (offset, 0); +- frame.below_hard_fp_saved_regs_size = offset; ++ auto below_hard_fp_saved_regs_size = offset - frame.bytes_below_saved_regs; ++ bool saves_below_hard_fp_p = maybe_ne (below_hard_fp_saved_regs_size, 0); ++ gcc_assert (!saves_below_hard_fp_p ++ || (frame.sve_save_and_probe != INVALID_REGNUM ++ && known_eq (frame.reg_offset[frame.sve_save_and_probe], ++ frame.bytes_below_saved_regs))); ++ ++ frame.bytes_below_hard_fp = offset; ++ frame.hard_fp_save_and_probe = INVALID_REGNUM; ++ ++ auto allocate_gpr_slot = [&](unsigned int regno) ++ { ++ if (frame.hard_fp_save_and_probe == INVALID_REGNUM) ++ frame.hard_fp_save_and_probe = regno; ++ frame.reg_offset[regno] = offset; ++ if (frame.wb_push_candidate1 == INVALID_REGNUM) ++ frame.wb_push_candidate1 = regno; ++ else if (frame.wb_push_candidate2 == INVALID_REGNUM) ++ frame.wb_push_candidate2 = regno; ++ offset += UNITS_PER_WORD; ++ }; ++ + if (frame.emit_frame_chain) + { + /* FP and LR are placed in the linkage record. */ +- frame.reg_offset[R29_REGNUM] = offset; +- frame.wb_push_candidate1 = R29_REGNUM; +- frame.reg_offset[R30_REGNUM] = offset + UNITS_PER_WORD; +- frame.wb_push_candidate2 = R30_REGNUM; +- offset += 2 * UNITS_PER_WORD; ++ allocate_gpr_slot (R29_REGNUM); ++ allocate_gpr_slot (R30_REGNUM); + } ++ else if (flag_stack_clash_protection ++ && known_eq (frame.reg_offset[R30_REGNUM], SLOT_REQUIRED)) ++ /* Put the LR save slot first, since it makes a good choice of probe ++ for stack clash purposes. The idea is that the link register usually ++ has to be saved before a call anyway, and so we lose little by ++ stopping it from being individually shrink-wrapped. */ ++ allocate_gpr_slot (R30_REGNUM); + + for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++) + if (known_eq (frame.reg_offset[regno], SLOT_REQUIRED)) +- { +- frame.reg_offset[regno] = offset; +- if (frame.wb_push_candidate1 == INVALID_REGNUM) +- frame.wb_push_candidate1 = regno; +- else if (frame.wb_push_candidate2 == INVALID_REGNUM) +- frame.wb_push_candidate2 = regno; +- offset += UNITS_PER_WORD; +- } ++ allocate_gpr_slot (regno); + + poly_int64 max_int_offset = offset; + offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT); +@@ -8295,6 +8338,8 @@ aarch64_layout_frame (void) + for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++) + if (known_eq (frame.reg_offset[regno], SLOT_REQUIRED)) + { ++ if (frame.hard_fp_save_and_probe == INVALID_REGNUM) ++ frame.hard_fp_save_and_probe = regno; + /* If there is an alignment gap between integer and fp callee-saves, + allocate the last fp register to it if possible. */ + if (regno == last_fp_reg +@@ -8317,30 +8362,36 @@ aarch64_layout_frame (void) + + offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT); + +- frame.saved_regs_size = offset; +- +- poly_int64 varargs_and_saved_regs_size = offset + frame.saved_varargs_size; ++ auto saved_regs_size = offset - frame.bytes_below_saved_regs; ++ gcc_assert (known_eq (saved_regs_size, below_hard_fp_saved_regs_size) ++ || (frame.hard_fp_save_and_probe != INVALID_REGNUM ++ && known_eq (frame.reg_offset[frame.hard_fp_save_and_probe], ++ frame.bytes_below_hard_fp))); + +- poly_int64 above_outgoing_args +- = aligned_upper_bound (varargs_and_saved_regs_size +- + get_frame_size (), +- STACK_BOUNDARY / BITS_PER_UNIT); +- +- frame.hard_fp_offset +- = above_outgoing_args - frame.below_hard_fp_saved_regs_size; ++ /* With stack-clash, a register must be saved in non-leaf functions. ++ The saving of the bottommost register counts as an implicit probe, ++ which allows us to maintain the invariant described in the comment ++ at expand_prologue. */ ++ gcc_assert (crtl->is_leaf || maybe_ne (saved_regs_size, 0)); + +- /* Both these values are already aligned. */ +- gcc_assert (multiple_p (crtl->outgoing_args_size, +- STACK_BOUNDARY / BITS_PER_UNIT)); +- frame.frame_size = above_outgoing_args + crtl->outgoing_args_size; ++ if (!regs_at_top_p) ++ { ++ offset += get_frame_size (); ++ offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT); ++ top_of_locals = offset; ++ } ++ offset += frame.saved_varargs_size; ++ gcc_assert (multiple_p (offset, STACK_BOUNDARY / BITS_PER_UNIT)); ++ frame.frame_size = offset; + +- frame.locals_offset = frame.saved_varargs_size; ++ frame.bytes_above_hard_fp = frame.frame_size - frame.bytes_below_hard_fp; ++ gcc_assert (known_ge (top_of_locals, 0)); ++ frame.bytes_above_locals = frame.frame_size - top_of_locals; + + frame.initial_adjust = 0; + frame.final_adjust = 0; + frame.callee_adjust = 0; + frame.sve_callee_adjust = 0; +- frame.callee_offset = 0; + + frame.wb_pop_candidate1 = frame.wb_push_candidate1; + frame.wb_pop_candidate2 = frame.wb_push_candidate2; +@@ -8351,7 +8402,7 @@ aarch64_layout_frame (void) + frame.is_scs_enabled + = (!crtl->calls_eh_return + && sanitize_flags_p (SANITIZE_SHADOW_CALL_STACK) +- && known_ge (cfun->machine->frame.reg_offset[LR_REGNUM], 0)); ++ && known_ge (frame.reg_offset[LR_REGNUM], 0)); + + /* When shadow call stack is enabled, the scs_pop in the epilogue will + restore x30, and we don't need to pop x30 again in the traditional +@@ -8371,75 +8422,76 @@ aarch64_layout_frame (void) + max_push_offset to 0, because no registers are popped at this time, + so callee_adjust cannot be adjusted. */ + HOST_WIDE_INT max_push_offset = 0; +- if (frame.wb_pop_candidate2 != INVALID_REGNUM) +- max_push_offset = 512; +- else if (frame.wb_pop_candidate1 != INVALID_REGNUM) +- max_push_offset = 256; ++ if (frame.wb_pop_candidate1 != INVALID_REGNUM) ++ { ++ if (frame.wb_pop_candidate2 != INVALID_REGNUM) ++ max_push_offset = 512; ++ else ++ max_push_offset = 256; ++ } + +- HOST_WIDE_INT const_size, const_outgoing_args_size, const_fp_offset; ++ HOST_WIDE_INT const_size, const_below_saved_regs, const_above_fp; + HOST_WIDE_INT const_saved_regs_size; +- if (frame.frame_size.is_constant (&const_size) +- && const_size < max_push_offset +- && known_eq (frame.hard_fp_offset, const_size)) ++ if (known_eq (saved_regs_size, 0)) ++ frame.initial_adjust = frame.frame_size; ++ else if (frame.frame_size.is_constant (&const_size) ++ && const_size < max_push_offset ++ && known_eq (frame.bytes_above_hard_fp, const_size)) + { +- /* Simple, small frame with no outgoing arguments: ++ /* Simple, small frame with no data below the saved registers. + + stp reg1, reg2, [sp, -frame_size]! + stp reg3, reg4, [sp, 16] */ + frame.callee_adjust = const_size; + } +- else if (crtl->outgoing_args_size.is_constant (&const_outgoing_args_size) +- && frame.saved_regs_size.is_constant (&const_saved_regs_size) +- && const_outgoing_args_size + const_saved_regs_size < 512 +- /* We could handle this case even with outgoing args, provided +- that the number of args left us with valid offsets for all +- predicate and vector save slots. It's such a rare case that +- it hardly seems worth the effort though. */ +- && (!saves_below_hard_fp_p || const_outgoing_args_size == 0) ++ else if (frame.bytes_below_saved_regs.is_constant (&const_below_saved_regs) ++ && saved_regs_size.is_constant (&const_saved_regs_size) ++ && const_below_saved_regs + const_saved_regs_size < 512 ++ /* We could handle this case even with data below the saved ++ registers, provided that that data left us with valid offsets ++ for all predicate and vector save slots. It's such a rare ++ case that it hardly seems worth the effort though. */ ++ && (!saves_below_hard_fp_p || const_below_saved_regs == 0) + && !(cfun->calls_alloca +- && frame.hard_fp_offset.is_constant (&const_fp_offset) +- && const_fp_offset < max_push_offset)) ++ && frame.bytes_above_hard_fp.is_constant (&const_above_fp) ++ && const_above_fp < max_push_offset)) + { +- /* Frame with small outgoing arguments: ++ /* Frame with small area below the saved registers: + + sub sp, sp, frame_size +- stp reg1, reg2, [sp, outgoing_args_size] +- stp reg3, reg4, [sp, outgoing_args_size + 16] */ ++ stp reg1, reg2, [sp, bytes_below_saved_regs] ++ stp reg3, reg4, [sp, bytes_below_saved_regs + 16] */ + frame.initial_adjust = frame.frame_size; +- frame.callee_offset = const_outgoing_args_size; + } + else if (saves_below_hard_fp_p +- && known_eq (frame.saved_regs_size, +- frame.below_hard_fp_saved_regs_size)) ++ && known_eq (saved_regs_size, below_hard_fp_saved_regs_size)) + { + /* Frame in which all saves are SVE saves: + +- sub sp, sp, hard_fp_offset + below_hard_fp_saved_regs_size ++ sub sp, sp, frame_size - bytes_below_saved_regs + save SVE registers relative to SP +- sub sp, sp, outgoing_args_size */ +- frame.initial_adjust = (frame.hard_fp_offset +- + frame.below_hard_fp_saved_regs_size); +- frame.final_adjust = crtl->outgoing_args_size; ++ sub sp, sp, bytes_below_saved_regs */ ++ frame.initial_adjust = frame.frame_size - frame.bytes_below_saved_regs; ++ frame.final_adjust = frame.bytes_below_saved_regs; + } +- else if (frame.hard_fp_offset.is_constant (&const_fp_offset) +- && const_fp_offset < max_push_offset) ++ else if (frame.bytes_above_hard_fp.is_constant (&const_above_fp) ++ && const_above_fp < max_push_offset) + { +- /* Frame with large outgoing arguments or SVE saves, but with +- a small local area: ++ /* Frame with large area below the saved registers, or with SVE saves, ++ but with a small area above: + + stp reg1, reg2, [sp, -hard_fp_offset]! + stp reg3, reg4, [sp, 16] + [sub sp, sp, below_hard_fp_saved_regs_size] + [save SVE registers relative to SP] +- sub sp, sp, outgoing_args_size */ +- frame.callee_adjust = const_fp_offset; +- frame.sve_callee_adjust = frame.below_hard_fp_saved_regs_size; +- frame.final_adjust = crtl->outgoing_args_size; ++ sub sp, sp, bytes_below_saved_regs */ ++ frame.callee_adjust = const_above_fp; ++ frame.sve_callee_adjust = below_hard_fp_saved_regs_size; ++ frame.final_adjust = frame.bytes_below_saved_regs; + } + else + { +- /* Frame with large local area and outgoing arguments or SVE saves, +- using frame pointer: ++ /* General case: + + sub sp, sp, hard_fp_offset + stp x29, x30, [sp, 0] +@@ -8447,10 +8499,29 @@ aarch64_layout_frame (void) + stp reg3, reg4, [sp, 16] + [sub sp, sp, below_hard_fp_saved_regs_size] + [save SVE registers relative to SP] +- sub sp, sp, outgoing_args_size */ +- frame.initial_adjust = frame.hard_fp_offset; +- frame.sve_callee_adjust = frame.below_hard_fp_saved_regs_size; +- frame.final_adjust = crtl->outgoing_args_size; ++ sub sp, sp, bytes_below_saved_regs */ ++ frame.initial_adjust = frame.bytes_above_hard_fp; ++ frame.sve_callee_adjust = below_hard_fp_saved_regs_size; ++ frame.final_adjust = frame.bytes_below_saved_regs; ++ } ++ ++ /* The frame is allocated in pieces, with each non-final piece ++ including a register save at offset 0 that acts as a probe for ++ the following piece. In addition, the save of the bottommost register ++ acts as a probe for callees and allocas. Roll back any probes that ++ aren't needed. ++ ++ A probe isn't needed if it is associated with the final allocation ++ (including callees and allocas) that happens before the epilogue is ++ executed. */ ++ if (crtl->is_leaf ++ && !cfun->calls_alloca ++ && known_eq (frame.final_adjust, 0)) ++ { ++ if (maybe_ne (frame.sve_callee_adjust, 0)) ++ frame.sve_save_and_probe = INVALID_REGNUM; ++ else ++ frame.hard_fp_save_and_probe = INVALID_REGNUM; + } + + /* Make sure the individual adjustments add up to the full frame size. */ +@@ -8754,15 +8825,17 @@ aarch64_add_cfa_expression (rtx_insn *insn, rtx reg, + } + + /* Emit code to save the callee-saved registers from register number START +- to LIMIT to the stack at the location starting at offset START_OFFSET, +- skipping any write-back candidates if SKIP_WB is true. HARD_FP_VALID_P +- is true if the hard frame pointer has been set up. */ ++ to LIMIT to the stack. The stack pointer is currently BYTES_BELOW_SP ++ bytes above the bottom of the static frame. Skip any write-back ++ candidates if SKIP_WB is true. HARD_FP_VALID_P is true if the hard ++ frame pointer has been set up. */ + + static void +-aarch64_save_callee_saves (poly_int64 start_offset, ++aarch64_save_callee_saves (poly_int64 bytes_below_sp, + unsigned start, unsigned limit, bool skip_wb, + bool hard_fp_valid_p) + { ++ aarch64_frame &frame = cfun->machine->frame; + rtx_insn *insn; + unsigned regno; + unsigned regno2; +@@ -8777,8 +8850,8 @@ aarch64_save_callee_saves (poly_int64 start_offset, + bool frame_related_p = aarch64_emit_cfi_for_reg_p (regno); + + if (skip_wb +- && (regno == cfun->machine->frame.wb_push_candidate1 +- || regno == cfun->machine->frame.wb_push_candidate2)) ++ && (regno == frame.wb_push_candidate1 ++ || regno == frame.wb_push_candidate2)) + continue; + + if (cfun->machine->reg_is_wrapped_separately[regno]) +@@ -8786,7 +8859,7 @@ aarch64_save_callee_saves (poly_int64 start_offset, + + machine_mode mode = aarch64_reg_save_mode (regno); + reg = gen_rtx_REG (mode, regno); +- offset = start_offset + cfun->machine->frame.reg_offset[regno]; ++ offset = frame.reg_offset[regno] - bytes_below_sp; + rtx base_rtx = stack_pointer_rtx; + poly_int64 sp_offset = offset; + +@@ -8797,9 +8870,7 @@ aarch64_save_callee_saves (poly_int64 start_offset, + else if (GP_REGNUM_P (regno) + && (!offset.is_constant (&const_offset) || const_offset >= 512)) + { +- gcc_assert (known_eq (start_offset, 0)); +- poly_int64 fp_offset +- = cfun->machine->frame.below_hard_fp_saved_regs_size; ++ poly_int64 fp_offset = frame.bytes_below_hard_fp - bytes_below_sp; + if (hard_fp_valid_p) + base_rtx = hard_frame_pointer_rtx; + else +@@ -8821,8 +8892,7 @@ aarch64_save_callee_saves (poly_int64 start_offset, + && (regno2 = aarch64_next_callee_save (regno + 1, limit)) <= limit + && !cfun->machine->reg_is_wrapped_separately[regno2] + && known_eq (GET_MODE_SIZE (mode), +- cfun->machine->frame.reg_offset[regno2] +- - cfun->machine->frame.reg_offset[regno])) ++ frame.reg_offset[regno2] - frame.reg_offset[regno])) + { + rtx reg2 = gen_rtx_REG (mode, regno2); + rtx mem2; +@@ -8864,14 +8934,16 @@ aarch64_save_callee_saves (poly_int64 start_offset, + } + + /* Emit code to restore the callee registers from register number START +- up to and including LIMIT. Restore from the stack offset START_OFFSET, +- skipping any write-back candidates if SKIP_WB is true. Write the +- appropriate REG_CFA_RESTORE notes into CFI_OPS. */ ++ up to and including LIMIT. The stack pointer is currently BYTES_BELOW_SP ++ bytes above the bottom of the static frame. Skip any write-back ++ candidates if SKIP_WB is true. Write the appropriate REG_CFA_RESTORE ++ notes into CFI_OPS. */ + + static void +-aarch64_restore_callee_saves (poly_int64 start_offset, unsigned start, ++aarch64_restore_callee_saves (poly_int64 bytes_below_sp, unsigned start, + unsigned limit, bool skip_wb, rtx *cfi_ops) + { ++ aarch64_frame &frame = cfun->machine->frame; + unsigned regno; + unsigned regno2; + poly_int64 offset; +@@ -8888,13 +8960,13 @@ aarch64_restore_callee_saves (poly_int64 start_offset, unsigned start, + rtx reg, mem; + + if (skip_wb +- && (regno == cfun->machine->frame.wb_pop_candidate1 +- || regno == cfun->machine->frame.wb_pop_candidate2)) ++ && (regno == frame.wb_pop_candidate1 ++ || regno == frame.wb_pop_candidate2)) + continue; + + machine_mode mode = aarch64_reg_save_mode (regno); + reg = gen_rtx_REG (mode, regno); +- offset = start_offset + cfun->machine->frame.reg_offset[regno]; ++ offset = frame.reg_offset[regno] - bytes_below_sp; + rtx base_rtx = stack_pointer_rtx; + if (mode == VNx2DImode && BYTES_BIG_ENDIAN) + aarch64_adjust_sve_callee_save_base (mode, base_rtx, anchor_reg, +@@ -8905,8 +8977,7 @@ aarch64_restore_callee_saves (poly_int64 start_offset, unsigned start, + && (regno2 = aarch64_next_callee_save (regno + 1, limit)) <= limit + && !cfun->machine->reg_is_wrapped_separately[regno2] + && known_eq (GET_MODE_SIZE (mode), +- cfun->machine->frame.reg_offset[regno2] +- - cfun->machine->frame.reg_offset[regno])) ++ frame.reg_offset[regno2] - frame.reg_offset[regno])) + { + rtx reg2 = gen_rtx_REG (mode, regno2); + rtx mem2; +@@ -9011,6 +9082,7 @@ offset_12bit_unsigned_scaled_p (machine_mode mode, poly_int64 offset) + static sbitmap + aarch64_get_separate_components (void) + { ++ aarch64_frame &frame = cfun->machine->frame; + sbitmap components = sbitmap_alloc (LAST_SAVED_REGNUM + 1); + bitmap_clear (components); + +@@ -9027,20 +9099,11 @@ aarch64_get_separate_components (void) + if (mode == VNx2DImode && BYTES_BIG_ENDIAN) + continue; + +- poly_int64 offset = cfun->machine->frame.reg_offset[regno]; +- +- /* If the register is saved in the first SVE save slot, we use +- it as a stack probe for -fstack-clash-protection. */ +- if (flag_stack_clash_protection +- && maybe_ne (cfun->machine->frame.below_hard_fp_saved_regs_size, 0) +- && known_eq (offset, 0)) +- continue; ++ poly_int64 offset = frame.reg_offset[regno]; + + /* Get the offset relative to the register we'll use. */ + if (frame_pointer_needed) +- offset -= cfun->machine->frame.below_hard_fp_saved_regs_size; +- else +- offset += crtl->outgoing_args_size; ++ offset -= frame.bytes_below_hard_fp; + + /* Check that we can access the stack slot of the register with one + direct load with no adjustments needed. */ +@@ -9057,11 +9120,11 @@ aarch64_get_separate_components (void) + /* If the spare predicate register used by big-endian SVE code + is call-preserved, it must be saved in the main prologue + before any saves that use it. */ +- if (cfun->machine->frame.spare_pred_reg != INVALID_REGNUM) +- bitmap_clear_bit (components, cfun->machine->frame.spare_pred_reg); ++ if (frame.spare_pred_reg != INVALID_REGNUM) ++ bitmap_clear_bit (components, frame.spare_pred_reg); + +- unsigned reg1 = cfun->machine->frame.wb_push_candidate1; +- unsigned reg2 = cfun->machine->frame.wb_push_candidate2; ++ unsigned reg1 = frame.wb_push_candidate1; ++ unsigned reg2 = frame.wb_push_candidate2; + /* If registers have been chosen to be stored/restored with + writeback don't interfere with them to avoid having to output explicit + stack adjustment instructions. */ +@@ -9072,6 +9135,13 @@ aarch64_get_separate_components (void) + + bitmap_clear_bit (components, LR_REGNUM); + bitmap_clear_bit (components, SP_REGNUM); ++ if (flag_stack_clash_protection) ++ { ++ if (frame.sve_save_and_probe != INVALID_REGNUM) ++ bitmap_clear_bit (components, frame.sve_save_and_probe); ++ if (frame.hard_fp_save_and_probe != INVALID_REGNUM) ++ bitmap_clear_bit (components, frame.hard_fp_save_and_probe); ++ } + + return components; + } +@@ -9170,6 +9240,7 @@ aarch64_get_next_set_bit (sbitmap bmp, unsigned int start) + static void + aarch64_process_components (sbitmap components, bool prologue_p) + { ++ aarch64_frame &frame = cfun->machine->frame; + rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed + ? HARD_FRAME_POINTER_REGNUM + : STACK_POINTER_REGNUM); +@@ -9184,11 +9255,9 @@ aarch64_process_components (sbitmap components, bool prologue_p) + machine_mode mode = aarch64_reg_save_mode (regno); + + rtx reg = gen_rtx_REG (mode, regno); +- poly_int64 offset = cfun->machine->frame.reg_offset[regno]; ++ poly_int64 offset = frame.reg_offset[regno]; + if (frame_pointer_needed) +- offset -= cfun->machine->frame.below_hard_fp_saved_regs_size; +- else +- offset += crtl->outgoing_args_size; ++ offset -= frame.bytes_below_hard_fp; + + rtx addr = plus_constant (Pmode, ptr_reg, offset); + rtx mem = gen_frame_mem (mode, addr); +@@ -9211,14 +9280,14 @@ aarch64_process_components (sbitmap components, bool prologue_p) + break; + } + +- poly_int64 offset2 = cfun->machine->frame.reg_offset[regno2]; ++ poly_int64 offset2 = frame.reg_offset[regno2]; + /* The next register is not of the same class or its offset is not + mergeable with the current one into a pair. */ + if (aarch64_sve_mode_p (mode) + || !satisfies_constraint_Ump (mem) + || GP_REGNUM_P (regno) != GP_REGNUM_P (regno2) + || (crtl->abi->id () == ARM_PCS_SIMD && FP_REGNUM_P (regno)) +- || maybe_ne ((offset2 - cfun->machine->frame.reg_offset[regno]), ++ || maybe_ne ((offset2 - frame.reg_offset[regno]), + GET_MODE_SIZE (mode))) + { + insn = emit_insn (set); +@@ -9240,9 +9309,7 @@ aarch64_process_components (sbitmap components, bool prologue_p) + /* REGNO2 can be saved/restored in a pair with REGNO. */ + rtx reg2 = gen_rtx_REG (mode, regno2); + if (frame_pointer_needed) +- offset2 -= cfun->machine->frame.below_hard_fp_saved_regs_size; +- else +- offset2 += crtl->outgoing_args_size; ++ offset2 -= frame.bytes_below_hard_fp; + rtx addr2 = plus_constant (Pmode, ptr_reg, offset2); + rtx mem2 = gen_frame_mem (mode, addr2); + rtx set2 = prologue_p ? gen_rtx_SET (mem2, reg2) +@@ -9316,10 +9383,10 @@ aarch64_stack_clash_protection_alloca_probe_range (void) + registers. If POLY_SIZE is not large enough to require a probe this function + will only adjust the stack. When allocating the stack space + FRAME_RELATED_P is then used to indicate if the allocation is frame related. +- FINAL_ADJUSTMENT_P indicates whether we are allocating the outgoing +- arguments. If we are then we ensure that any allocation larger than the ABI +- defined buffer needs a probe so that the invariant of having a 1KB buffer is +- maintained. ++ FINAL_ADJUSTMENT_P indicates whether we are allocating the area below ++ the saved registers. If we are then we ensure that any allocation ++ larger than the ABI defined buffer needs a probe so that the ++ invariant of having a 1KB buffer is maintained. + + We emit barriers after each stack adjustment to prevent optimizations from + breaking the invariant that we never drop the stack more than a page. This +@@ -9335,45 +9402,26 @@ aarch64_allocate_and_probe_stack_space (rtx temp1, rtx temp2, + bool frame_related_p, + bool final_adjustment_p) + { ++ aarch64_frame &frame = cfun->machine->frame; + HOST_WIDE_INT guard_size + = 1 << param_stack_clash_protection_guard_size; + HOST_WIDE_INT guard_used_by_caller = STACK_CLASH_CALLER_GUARD; ++ HOST_WIDE_INT byte_sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; ++ gcc_assert (multiple_p (poly_size, byte_sp_alignment)); + HOST_WIDE_INT min_probe_threshold + = (final_adjustment_p +- ? guard_used_by_caller ++ ? guard_used_by_caller + byte_sp_alignment + : guard_size - guard_used_by_caller); +- /* When doing the final adjustment for the outgoing arguments, take into +- account any unprobed space there is above the current SP. There are +- two cases: +- +- - When saving SVE registers below the hard frame pointer, we force +- the lowest save to take place in the prologue before doing the final +- adjustment (i.e. we don't allow the save to be shrink-wrapped). +- This acts as a probe at SP, so there is no unprobed space. +- +- - When there are no SVE register saves, we use the store of the link +- register as a probe. We can't assume that LR was saved at position 0 +- though, so treat any space below it as unprobed. */ +- if (final_adjustment_p +- && known_eq (cfun->machine->frame.below_hard_fp_saved_regs_size, 0)) +- { +- poly_int64 lr_offset = cfun->machine->frame.reg_offset[LR_REGNUM]; +- if (known_ge (lr_offset, 0)) +- min_probe_threshold -= lr_offset.to_constant (); +- else +- gcc_assert (!flag_stack_clash_protection || known_eq (poly_size, 0)); +- } +- +- poly_int64 frame_size = cfun->machine->frame.frame_size; ++ poly_int64 frame_size = frame.frame_size; + + /* We should always have a positive probe threshold. */ + gcc_assert (min_probe_threshold > 0); + + if (flag_stack_clash_protection && !final_adjustment_p) + { +- poly_int64 initial_adjust = cfun->machine->frame.initial_adjust; +- poly_int64 sve_callee_adjust = cfun->machine->frame.sve_callee_adjust; +- poly_int64 final_adjust = cfun->machine->frame.final_adjust; ++ poly_int64 initial_adjust = frame.initial_adjust; ++ poly_int64 sve_callee_adjust = frame.sve_callee_adjust; ++ poly_int64 final_adjust = frame.final_adjust; + + if (known_eq (frame_size, 0)) + { +@@ -9527,7 +9575,7 @@ aarch64_allocate_and_probe_stack_space (rtx temp1, rtx temp2, + /* Handle any residuals. Residuals of at least MIN_PROBE_THRESHOLD have to + be probed. This maintains the requirement that each page is probed at + least once. For initial probing we probe only if the allocation is +- more than GUARD_SIZE - buffer, and for the outgoing arguments we probe ++ more than GUARD_SIZE - buffer, and below the saved registers we probe + if the amount is larger than buffer. GUARD_SIZE - buffer + buffer == + GUARD_SIZE. This works that for any allocation that is large enough to + trigger a probe here, we'll have at least one, and if they're not large +@@ -9537,16 +9585,12 @@ aarch64_allocate_and_probe_stack_space (rtx temp1, rtx temp2, + are still safe. */ + if (residual) + { +- HOST_WIDE_INT residual_probe_offset = guard_used_by_caller; ++ gcc_assert (guard_used_by_caller + byte_sp_alignment <= size); ++ + /* If we're doing final adjustments, and we've done any full page + allocations then any residual needs to be probed. */ + if (final_adjustment_p && rounded_size != 0) + min_probe_threshold = 0; +- /* If doing a small final adjustment, we always probe at offset 0. +- This is done to avoid issues when LR is not at position 0 or when +- the final adjustment is smaller than the probing offset. */ +- else if (final_adjustment_p && rounded_size == 0) +- residual_probe_offset = 0; + + aarch64_sub_sp (temp1, temp2, residual, frame_related_p); + if (residual >= min_probe_threshold) +@@ -9557,8 +9601,8 @@ aarch64_allocate_and_probe_stack_space (rtx temp1, rtx temp2, + HOST_WIDE_INT_PRINT_DEC " bytes, probing will be required." + "\n", residual); + +- emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, +- residual_probe_offset)); ++ emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, ++ guard_used_by_caller)); + emit_insn (gen_blockage ()); + } + } +@@ -9596,20 +9640,24 @@ aarch64_epilogue_uses (int regno) + | for register varargs | + | | + +-------------------------------+ +- | local variables | <-- frame_pointer_rtx ++ | local variables (1) | <-- frame_pointer_rtx + | | + +-------------------------------+ +- | padding | \ +- +-------------------------------+ | +- | callee-saved registers | | frame.saved_regs_size +- +-------------------------------+ | +- | LR' | | +- +-------------------------------+ | +- | FP' | | +- +-------------------------------+ |<- hard_frame_pointer_rtx (aligned) +- | SVE vector registers | | \ +- +-------------------------------+ | | below_hard_fp_saved_regs_size +- | SVE predicate registers | / / ++ | padding (1) | ++ +-------------------------------+ ++ | callee-saved registers | ++ +-------------------------------+ ++ | LR' | ++ +-------------------------------+ ++ | FP' | ++ +-------------------------------+ <-- hard_frame_pointer_rtx (aligned) ++ | SVE vector registers | ++ +-------------------------------+ ++ | SVE predicate registers | ++ +-------------------------------+ ++ | local variables (2) | ++ +-------------------------------+ ++ | padding (2) | + +-------------------------------+ + | dynamic allocation | + +-------------------------------+ +@@ -9620,6 +9668,9 @@ aarch64_epilogue_uses (int regno) + +-------------------------------+ + | | <-- stack_pointer_rtx (aligned) + ++ The regions marked (1) and (2) are mutually exclusive. (2) is used ++ when aarch64_save_regs_above_locals_p is true. ++ + Dynamic stack allocations via alloca() decrease stack_pointer_rtx + but leave frame_pointer_rtx and hard_frame_pointer_rtx + unchanged. +@@ -9634,8 +9685,8 @@ aarch64_epilogue_uses (int regno) + When probing is needed, we emit a probe at the start of the prologue + and every PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE bytes thereafter. + +- We have to track how much space has been allocated and the only stores +- to the stack we track as implicit probes are the FP/LR stores. ++ We can also use register saves as probes. These are stored in ++ sve_save_and_probe and hard_fp_save_and_probe. + + For outgoing arguments we probe if the size is larger than 1KB, such that + the ABI specified buffer is maintained for the next callee. +@@ -9662,17 +9713,15 @@ aarch64_epilogue_uses (int regno) + void + aarch64_expand_prologue (void) + { +- poly_int64 frame_size = cfun->machine->frame.frame_size; +- poly_int64 initial_adjust = cfun->machine->frame.initial_adjust; +- HOST_WIDE_INT callee_adjust = cfun->machine->frame.callee_adjust; +- poly_int64 final_adjust = cfun->machine->frame.final_adjust; +- poly_int64 callee_offset = cfun->machine->frame.callee_offset; +- poly_int64 sve_callee_adjust = cfun->machine->frame.sve_callee_adjust; +- poly_int64 below_hard_fp_saved_regs_size +- = cfun->machine->frame.below_hard_fp_saved_regs_size; +- unsigned reg1 = cfun->machine->frame.wb_push_candidate1; +- unsigned reg2 = cfun->machine->frame.wb_push_candidate2; +- bool emit_frame_chain = cfun->machine->frame.emit_frame_chain; ++ aarch64_frame &frame = cfun->machine->frame; ++ poly_int64 frame_size = frame.frame_size; ++ poly_int64 initial_adjust = frame.initial_adjust; ++ HOST_WIDE_INT callee_adjust = frame.callee_adjust; ++ poly_int64 final_adjust = frame.final_adjust; ++ poly_int64 sve_callee_adjust = frame.sve_callee_adjust; ++ unsigned reg1 = frame.wb_push_candidate1; ++ unsigned reg2 = frame.wb_push_candidate2; ++ bool emit_frame_chain = frame.emit_frame_chain; + rtx_insn *insn; + + if (flag_stack_clash_protection && known_eq (callee_adjust, 0)) +@@ -9703,7 +9752,7 @@ aarch64_expand_prologue (void) + } + + /* Push return address to shadow call stack. */ +- if (cfun->machine->frame.is_scs_enabled) ++ if (frame.is_scs_enabled) + emit_insn (gen_scs_push ()); + + if (flag_stack_usage_info) +@@ -9740,21 +9789,21 @@ aarch64_expand_prologue (void) + if (callee_adjust != 0) + aarch64_push_regs (reg1, reg2, callee_adjust); + +- /* The offset of the frame chain record (if any) from the current SP. */ +- poly_int64 chain_offset = (initial_adjust + callee_adjust +- - cfun->machine->frame.hard_fp_offset); +- gcc_assert (known_ge (chain_offset, 0)); +- +- /* The offset of the bottom of the save area from the current SP. */ +- poly_int64 saved_regs_offset = chain_offset - below_hard_fp_saved_regs_size; ++ /* The offset of the current SP from the bottom of the static frame. */ ++ poly_int64 bytes_below_sp = frame_size - initial_adjust - callee_adjust; + + if (emit_frame_chain) + { ++ /* The offset of the frame chain record (if any) from the current SP. */ ++ poly_int64 chain_offset = (initial_adjust + callee_adjust ++ - frame.bytes_above_hard_fp); ++ gcc_assert (known_ge (chain_offset, 0)); ++ + if (callee_adjust == 0) + { + reg1 = R29_REGNUM; + reg2 = R30_REGNUM; +- aarch64_save_callee_saves (saved_regs_offset, reg1, reg2, ++ aarch64_save_callee_saves (bytes_below_sp, reg1, reg2, + false, false); + } + else +@@ -9779,8 +9828,7 @@ aarch64_expand_prologue (void) + implicit. */ + if (!find_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX)) + { +- rtx src = plus_constant (Pmode, stack_pointer_rtx, +- callee_offset); ++ rtx src = plus_constant (Pmode, stack_pointer_rtx, chain_offset); + add_reg_note (insn, REG_CFA_ADJUST_CFA, + gen_rtx_SET (hard_frame_pointer_rtx, src)); + } +@@ -9795,7 +9843,7 @@ aarch64_expand_prologue (void) + emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx)); + } + +- aarch64_save_callee_saves (saved_regs_offset, R0_REGNUM, R30_REGNUM, ++ aarch64_save_callee_saves (bytes_below_sp, R0_REGNUM, R30_REGNUM, + callee_adjust != 0 || emit_frame_chain, + emit_frame_chain); + if (maybe_ne (sve_callee_adjust, 0)) +@@ -9805,18 +9853,21 @@ aarch64_expand_prologue (void) + aarch64_allocate_and_probe_stack_space (tmp1_rtx, tmp0_rtx, + sve_callee_adjust, + !frame_pointer_needed, false); +- saved_regs_offset += sve_callee_adjust; ++ bytes_below_sp -= sve_callee_adjust; + } +- aarch64_save_callee_saves (saved_regs_offset, P0_REGNUM, P15_REGNUM, ++ aarch64_save_callee_saves (bytes_below_sp, P0_REGNUM, P15_REGNUM, + false, emit_frame_chain); +- aarch64_save_callee_saves (saved_regs_offset, V0_REGNUM, V31_REGNUM, ++ aarch64_save_callee_saves (bytes_below_sp, V0_REGNUM, V31_REGNUM, + callee_adjust != 0 || emit_frame_chain, + emit_frame_chain); + + /* We may need to probe the final adjustment if it is larger than the guard + that is assumed by the called. */ ++ gcc_assert (known_eq (bytes_below_sp, final_adjust)); + aarch64_allocate_and_probe_stack_space (tmp1_rtx, tmp0_rtx, final_adjust, + !frame_pointer_needed, true); ++ if (emit_frame_chain && maybe_ne (final_adjust, 0)) ++ emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx)); + } + + /* Return TRUE if we can use a simple_return insn. +@@ -9845,16 +9896,15 @@ aarch64_use_return_insn_p (void) + void + aarch64_expand_epilogue (bool for_sibcall) + { +- poly_int64 initial_adjust = cfun->machine->frame.initial_adjust; +- HOST_WIDE_INT callee_adjust = cfun->machine->frame.callee_adjust; +- poly_int64 final_adjust = cfun->machine->frame.final_adjust; +- poly_int64 callee_offset = cfun->machine->frame.callee_offset; +- poly_int64 sve_callee_adjust = cfun->machine->frame.sve_callee_adjust; +- poly_int64 below_hard_fp_saved_regs_size +- = cfun->machine->frame.below_hard_fp_saved_regs_size; +- unsigned reg1 = cfun->machine->frame.wb_pop_candidate1; +- unsigned reg2 = cfun->machine->frame.wb_pop_candidate2; +- unsigned int last_gpr = (cfun->machine->frame.is_scs_enabled ++ aarch64_frame &frame = cfun->machine->frame; ++ poly_int64 initial_adjust = frame.initial_adjust; ++ HOST_WIDE_INT callee_adjust = frame.callee_adjust; ++ poly_int64 final_adjust = frame.final_adjust; ++ poly_int64 sve_callee_adjust = frame.sve_callee_adjust; ++ poly_int64 bytes_below_hard_fp = frame.bytes_below_hard_fp; ++ unsigned reg1 = frame.wb_pop_candidate1; ++ unsigned reg2 = frame.wb_pop_candidate2; ++ unsigned int last_gpr = (frame.is_scs_enabled + ? R29_REGNUM : R30_REGNUM); + rtx cfi_ops = NULL; + rtx_insn *insn; +@@ -9888,7 +9938,7 @@ aarch64_expand_epilogue (bool for_sibcall) + /* We need to add memory barrier to prevent read from deallocated stack. */ + bool need_barrier_p + = maybe_ne (get_frame_size () +- + cfun->machine->frame.saved_varargs_size, 0); ++ + frame.saved_varargs_size, 0); + + /* Emit a barrier to prevent loads from a deallocated stack. */ + if (maybe_gt (final_adjust, crtl->outgoing_args_size) +@@ -9909,7 +9959,7 @@ aarch64_expand_epilogue (bool for_sibcall) + is restored on the instruction doing the writeback. */ + aarch64_add_offset (Pmode, stack_pointer_rtx, + hard_frame_pointer_rtx, +- -callee_offset - below_hard_fp_saved_regs_size, ++ -bytes_below_hard_fp + final_adjust, + tmp1_rtx, tmp0_rtx, callee_adjust == 0); + else + /* The case where we need to re-use the register here is very rare, so +@@ -9919,9 +9969,9 @@ aarch64_expand_epilogue (bool for_sibcall) + + /* Restore the vector registers before the predicate registers, + so that we can use P4 as a temporary for big-endian SVE frames. */ +- aarch64_restore_callee_saves (callee_offset, V0_REGNUM, V31_REGNUM, ++ aarch64_restore_callee_saves (final_adjust, V0_REGNUM, V31_REGNUM, + callee_adjust != 0, &cfi_ops); +- aarch64_restore_callee_saves (callee_offset, P0_REGNUM, P15_REGNUM, ++ aarch64_restore_callee_saves (final_adjust, P0_REGNUM, P15_REGNUM, + false, &cfi_ops); + if (maybe_ne (sve_callee_adjust, 0)) + aarch64_add_sp (NULL_RTX, NULL_RTX, sve_callee_adjust, true); +@@ -9929,7 +9979,7 @@ aarch64_expand_epilogue (bool for_sibcall) + /* When shadow call stack is enabled, the scs_pop in the epilogue will + restore x30, we don't need to restore x30 again in the traditional + way. */ +- aarch64_restore_callee_saves (callee_offset - sve_callee_adjust, ++ aarch64_restore_callee_saves (final_adjust + sve_callee_adjust, + R0_REGNUM, last_gpr, + callee_adjust != 0, &cfi_ops); + +@@ -9969,7 +10019,7 @@ aarch64_expand_epilogue (bool for_sibcall) + } + + /* Pop return address from shadow call stack. */ +- if (cfun->machine->frame.is_scs_enabled) ++ if (frame.is_scs_enabled) + { + machine_mode mode = aarch64_reg_save_mode (R30_REGNUM); + rtx reg = gen_rtx_REG (mode, R30_REGNUM); +@@ -12564,24 +12614,24 @@ aarch64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) + poly_int64 + aarch64_initial_elimination_offset (unsigned from, unsigned to) + { ++ aarch64_frame &frame = cfun->machine->frame; ++ + if (to == HARD_FRAME_POINTER_REGNUM) + { + if (from == ARG_POINTER_REGNUM) +- return cfun->machine->frame.hard_fp_offset; ++ return frame.bytes_above_hard_fp; + + if (from == FRAME_POINTER_REGNUM) +- return cfun->machine->frame.hard_fp_offset +- - cfun->machine->frame.locals_offset; ++ return frame.bytes_above_hard_fp - frame.bytes_above_locals; + } + + if (to == STACK_POINTER_REGNUM) + { + if (from == FRAME_POINTER_REGNUM) +- return cfun->machine->frame.frame_size +- - cfun->machine->frame.locals_offset; ++ return frame.frame_size - frame.bytes_above_locals; + } + +- return cfun->machine->frame.frame_size; ++ return frame.frame_size; + } + + +@@ -24686,10 +24736,11 @@ aarch64_copy_one_block_and_progress_pointers (rtx *src, rtx *dst, + *dst = aarch64_progress_pointer (*dst); + } + +-/* Expand a cpymem using the MOPS extension. OPERANDS are taken +- from the cpymem pattern. Return true iff we succeeded. */ +-static bool +-aarch64_expand_cpymem_mops (rtx *operands) ++/* Expand a cpymem/movmem using the MOPS extension. OPERANDS are taken ++ from the cpymem/movmem pattern. IS_MEMMOVE is true if this is a memmove ++ rather than memcpy. Return true iff we succeeded. */ ++bool ++aarch64_expand_cpymem_mops (rtx *operands, bool is_memmove = false) + { + if (!TARGET_MOPS) + return false; +@@ -24701,8 +24752,10 @@ aarch64_expand_cpymem_mops (rtx *operands) + rtx dst_mem = replace_equiv_address (operands[0], dst_addr); + rtx src_mem = replace_equiv_address (operands[1], src_addr); + rtx sz_reg = copy_to_mode_reg (DImode, operands[2]); +- emit_insn (gen_aarch64_cpymemdi (dst_mem, src_mem, sz_reg)); +- ++ if (is_memmove) ++ emit_insn (gen_aarch64_movmemdi (dst_mem, src_mem, sz_reg)); ++ else ++ emit_insn (gen_aarch64_cpymemdi (dst_mem, src_mem, sz_reg)); + return true; + } + +@@ -25981,11 +26034,9 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, + gcc_assert (known_eq (GET_MODE_SIZE (GET_MODE (mem_1)), + GET_MODE_SIZE (GET_MODE (mem_2)))); + +- /* One of the memory accesses must be a mempair operand. +- If it is not the first one, they need to be swapped by the +- peephole. */ +- if (!aarch64_mem_pair_operand (mem_1, GET_MODE (mem_1)) +- && !aarch64_mem_pair_operand (mem_2, GET_MODE (mem_2))) ++ /* The lower memory access must be a mem-pair operand. */ ++ rtx lower_mem = reversed ? mem_2 : mem_1; ++ if (!aarch64_mem_pair_operand (lower_mem, GET_MODE (lower_mem))) + return false; + + if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1))) +diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h +index 6834c3e9922..01f7751bc78 100644 +--- a/gcc/config/aarch64/aarch64.h ++++ b/gcc/config/aarch64/aarch64.h +@@ -860,6 +860,9 @@ extern enum aarch64_processor aarch64_tune; + #ifdef HAVE_POLY_INT_H + struct GTY (()) aarch64_frame + { ++ /* The offset from the bottom of the static frame (the bottom of the ++ outgoing arguments) of each register save slot, or -2 if no save is ++ needed. */ + poly_int64 reg_offset[LAST_SAVED_REGNUM + 1]; + + /* The number of extra stack bytes taken up by register varargs. +@@ -868,25 +871,28 @@ struct GTY (()) aarch64_frame + STACK_BOUNDARY. */ + HOST_WIDE_INT saved_varargs_size; + +- /* The size of the callee-save registers with a slot in REG_OFFSET. */ +- poly_int64 saved_regs_size; ++ /* The number of bytes between the bottom of the static frame (the bottom ++ of the outgoing arguments) and the bottom of the register save area. ++ This value is always a multiple of STACK_BOUNDARY. */ ++ poly_int64 bytes_below_saved_regs; + +- /* The size of the callee-save registers with a slot in REG_OFFSET that +- are saved below the hard frame pointer. */ +- poly_int64 below_hard_fp_saved_regs_size; ++ /* The number of bytes between the bottom of the static frame (the bottom ++ of the outgoing arguments) and the hard frame pointer. This value is ++ always a multiple of STACK_BOUNDARY. */ ++ poly_int64 bytes_below_hard_fp; + +- /* Offset from the base of the frame (incomming SP) to the +- top of the locals area. This value is always a multiple of ++ /* The number of bytes between the top of the locals area and the top ++ of the frame (the incomming SP). This value is always a multiple of + STACK_BOUNDARY. */ +- poly_int64 locals_offset; ++ poly_int64 bytes_above_locals; + +- /* Offset from the base of the frame (incomming SP) to the +- hard_frame_pointer. This value is always a multiple of ++ /* The number of bytes between the hard_frame_pointer and the top of ++ the frame (the incomming SP). This value is always a multiple of + STACK_BOUNDARY. */ +- poly_int64 hard_fp_offset; ++ poly_int64 bytes_above_hard_fp; + +- /* The size of the frame. This value is the offset from base of the +- frame (incomming SP) to the stack_pointer. This value is always ++ /* The size of the frame, i.e. the number of bytes between the bottom ++ of the outgoing arguments and the incoming SP. This value is always + a multiple of STACK_BOUNDARY. */ + poly_int64 frame_size; + +@@ -897,10 +903,6 @@ struct GTY (()) aarch64_frame + It is zero when no push is used. */ + HOST_WIDE_INT callee_adjust; + +- /* The offset from SP to the callee-save registers after initial_adjust. +- It may be non-zero if no push is used (ie. callee_adjust == 0). */ +- poly_int64 callee_offset; +- + /* The size of the stack adjustment before saving or after restoring + SVE registers. */ + poly_int64 sve_callee_adjust; +@@ -948,6 +950,14 @@ struct GTY (()) aarch64_frame + This is the register they should use. */ + unsigned spare_pred_reg; + ++ /* An SVE register that is saved below the hard frame pointer and that acts ++ as a probe for later allocations, or INVALID_REGNUM if none. */ ++ unsigned sve_save_and_probe; ++ ++ /* A register that is saved at the hard frame pointer and that acts ++ as a probe for later allocations, or INVALID_REGNUM if none. */ ++ unsigned hard_fp_save_and_probe; ++ + bool laid_out; + + /* True if shadow call stack should be enabled for the current function. */ +diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md +index d24c8afcfa6..fb100bdf6b3 100644 +--- a/gcc/config/aarch64/aarch64.md ++++ b/gcc/config/aarch64/aarch64.md +@@ -1159,9 +1159,27 @@ + { + int i; + ++ /* Generate a PARALLEL that contains all of the register results. ++ The offsets are somewhat arbitrary, since we don't know the ++ actual return type. The main thing we need to avoid is having ++ overlapping byte ranges, since those might give the impression ++ that two registers are known to have data in common. */ ++ rtvec rets = rtvec_alloc (XVECLEN (operands[2], 0)); ++ poly_int64 offset = 0; ++ for (i = 0; i < XVECLEN (operands[2], 0); i++) ++ { ++ rtx reg = SET_SRC (XVECEXP (operands[2], 0, i)); ++ gcc_assert (REG_P (reg)); ++ rtx offset_rtx = gen_int_mode (offset, Pmode); ++ rtx piece = gen_rtx_EXPR_LIST (VOIDmode, reg, offset_rtx); ++ RTVEC_ELT (rets, i) = piece; ++ offset += GET_MODE_SIZE (GET_MODE (reg)); ++ } ++ rtx ret = gen_rtx_PARALLEL (VOIDmode, rets); ++ + /* Untyped calls always use the default ABI. It's only possible to use + ABI variants if we know the type of the target function. */ +- emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); ++ emit_call_insn (gen_call_value (ret, operands[0], const0_rtx, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { +@@ -1627,7 +1645,22 @@ + } + ) + +-(define_insn "aarch64_movmemdi" ++(define_expand "aarch64_movmemdi" ++ [(parallel ++ [(set (match_operand 2) (const_int 0)) ++ (clobber (match_dup 3)) ++ (clobber (match_dup 4)) ++ (clobber (reg:CC CC_REGNUM)) ++ (set (match_operand 0) ++ (unspec:BLK [(match_operand 1) (match_dup 2)] UNSPEC_MOVMEM))])] ++ "TARGET_MOPS" ++ { ++ operands[3] = XEXP (operands[0], 0); ++ operands[4] = XEXP (operands[1], 0); ++ } ++) ++ ++(define_insn "*aarch64_movmemdi" + [(parallel [ + (set (match_operand:DI 2 "register_operand" "+&r") (const_int 0)) + (clobber (match_operand:DI 0 "register_operand" "+&r")) +@@ -1660,17 +1693,9 @@ + && INTVAL (sz_reg) < aarch64_mops_memmove_size_threshold) + FAIL; + +- rtx addr_dst = XEXP (operands[0], 0); +- rtx addr_src = XEXP (operands[1], 0); +- +- if (!REG_P (sz_reg)) +- sz_reg = force_reg (DImode, sz_reg); +- if (!REG_P (addr_dst)) +- addr_dst = force_reg (DImode, addr_dst); +- if (!REG_P (addr_src)) +- addr_src = force_reg (DImode, addr_src); +- emit_insn (gen_aarch64_movmemdi (addr_dst, addr_src, sz_reg)); +- DONE; ++ if (aarch64_expand_cpymem_mops (operands, true)) ++ DONE; ++ FAIL; + } + ) + +@@ -7668,9 +7693,9 @@ + ;; Load/Store 64-bit (LS64) instructions. + (define_insn "ld64b" + [(set (match_operand:V8DI 0 "register_operand" "=r") +- (unspec_volatile:V8DI +- [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))] +- UNSPEC_LD64B) ++ (unspec_volatile:V8DI ++ [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))] ++ UNSPEC_LD64B) + )] + "TARGET_LS64" + "ld64b\\t%0, [%1]" +@@ -7678,9 +7703,9 @@ + ) + + (define_insn "st64b" +- [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r")) +- (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] +- UNSPEC_ST64B) ++ [(set (mem:V8DI (match_operand:DI 0 "register_operand" "r")) ++ (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] ++ UNSPEC_ST64B) + )] + "TARGET_LS64" + "st64b\\t%1, [%0]" +@@ -7689,10 +7714,10 @@ + + (define_insn "st64bv" + [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET)) ++ (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET)) + (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) +- (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] +- UNSPEC_ST64BV) ++ (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] ++ UNSPEC_ST64BV) + )] + "TARGET_LS64" + "st64bv\\t%0, %2, [%1]" +@@ -7701,10 +7726,10 @@ + + (define_insn "st64bv0" + [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET)) ++ (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET)) + (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) +- (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] +- UNSPEC_ST64BV0) ++ (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] ++ UNSPEC_ST64BV0) + )] + "TARGET_LS64" + "st64bv0\\t%0, %2, [%1]" +diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h +index d26e269cb84..24c02d4fdf3 100644 +--- a/gcc/config/aarch64/arm_acle.h ++++ b/gcc/config/aarch64/arm_acle.h +@@ -270,40 +270,7 @@ __ttest (void) + #endif + + #ifdef __ARM_FEATURE_LS64 +-#pragma GCC push_options +-#pragma GCC target ("+nothing+ls64") +- + typedef __arm_data512_t data512_t; +- +-__extension__ extern __inline data512_t +-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_ld64b (const void *__addr) +-{ +- return __builtin_aarch64_ld64b (__addr); +-} +- +-__extension__ extern __inline void +-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_st64b (void *__addr, data512_t __value) +-{ +- __builtin_aarch64_st64b (__addr, __value); +-} +- +-__extension__ extern __inline uint64_t +-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_st64bv (void *__addr, data512_t __value) +-{ +- return __builtin_aarch64_st64bv (__addr, __value); +-} +- +-__extension__ extern __inline uint64_t +-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_st64bv0 (void *__addr, data512_t __value) +-{ +- return __builtin_aarch64_st64bv0 (__addr, __value); +-} +- +-#pragma GCC pop_options + #endif + + #pragma GCC push_options +diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc +index 0a85e66fa89..06c8356fc4e 100644 +--- a/gcc/config/alpha/alpha.cc ++++ b/gcc/config/alpha/alpha.cc +@@ -2070,6 +2070,8 @@ static rtx + alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1) + { + HOST_WIDE_INT d1, d2, d3, d4; ++ machine_mode mode = GET_MODE (target); ++ rtx orig_target = target; + + /* Decompose the entire word */ + +@@ -2082,6 +2084,9 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1) + d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; + gcc_assert (c1 == d4); + ++ if (mode != DImode) ++ target = gen_lowpart (DImode, target); ++ + /* Construct the high word */ + if (d4) + { +@@ -2101,7 +2106,7 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1) + if (d1) + emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1))); + +- return target; ++ return orig_target; + } + + /* Given an integral CONST_INT or CONST_VECTOR, return the low 64 bits. */ +diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc +index 36a40a1dc80..557d6f68fd1 100644 +--- a/gcc/config/arm/arm-builtins.cc ++++ b/gcc/config/arm/arm-builtins.cc +@@ -97,7 +97,7 @@ arm_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] + /* T (T, unsigned immediate). */ + static enum arm_type_qualifiers + arm_sat_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] +- = { qualifier_unsigned, qualifier_none, qualifier_unsigned_immediate }; ++ = { qualifier_none, qualifier_none, qualifier_unsigned_immediate }; + #define SAT_BINOP_UNSIGNED_IMM_QUALIFIERS \ + (arm_sat_binop_imm_qualifiers) + +diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md +index 60468f6182c..912b939f886 100644 +--- a/gcc/config/arm/arm.md ++++ b/gcc/config/arm/arm.md +@@ -7466,7 +7466,7 @@ + && !arm_const_double_rtx (operands[1]) + && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1]))) + { +- rtx clobreg = gen_reg_rtx (DFmode); ++ rtx clobreg = gen_reg_rtx (DImode); + emit_insn (gen_no_literal_pool_df_immediate (operands[0], operands[1], + clobreg)); + DONE; +diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h +index 073e3711623..c359e9c6336 100644 +--- a/gcc/config/arm/arm_mve.h ++++ b/gcc/config/arm/arm_mve.h +@@ -9675,42 +9675,42 @@ __arm_vabdq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pr + + __extension__ extern __inline int8x16_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) + { + return __builtin_mve_vaddq_m_n_sv16qi (__inactive, __a, __b, __p); + } + + __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) + { + return __builtin_mve_vaddq_m_n_sv4si (__inactive, __a, __b, __p); + } + + __extension__ extern __inline int16x8_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) + { + return __builtin_mve_vaddq_m_n_sv8hi (__inactive, __a, __b, __p); + } + + __extension__ extern __inline uint8x16_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) + { + return __builtin_mve_vaddq_m_n_uv16qi (__inactive, __a, __b, __p); + } + + __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) + { + return __builtin_mve_vaddq_m_n_uv4si (__inactive, __a, __b, __p); + } + + __extension__ extern __inline uint16x8_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) + { + return __builtin_mve_vaddq_m_n_uv8hi (__inactive, __a, __b, __p); + } +@@ -16055,7 +16055,7 @@ __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16065,7 +16065,7 @@ __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16075,7 +16075,7 @@ __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16085,7 +16085,7 @@ __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16131,7 +16131,7 @@ __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16141,7 +16141,7 @@ __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + uint32x4_t __res = __builtin_mve_vsbcq_uv4si (__a, __b); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16151,7 +16151,7 @@ __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16161,7 +16161,7 @@ __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p) + { +- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29)); ++ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29)); + uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b, __p); + *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u; + return __res; +@@ -16171,14 +16171,14 @@ __extension__ extern __inline void + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vst1q_p_u8 (uint8_t * __addr, uint8x16_t __value, mve_pred16_t __p) + { +- return vstrbq_p_u8 (__addr, __value, __p); ++ return __arm_vstrbq_p_u8 (__addr, __value, __p); + } + + __extension__ extern __inline void + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vst1q_p_s8 (int8_t * __addr, int8x16_t __value, mve_pred16_t __p) + { +- return vstrbq_p_s8 (__addr, __value, __p); ++ return __arm_vstrbq_p_s8 (__addr, __value, __p); + } + + __extension__ extern __inline void +@@ -16203,14 +16203,14 @@ __extension__ extern __inline uint8x16_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vld1q_z_u8 (uint8_t const *__base, mve_pred16_t __p) + { +- return vldrbq_z_u8 ( __base, __p); ++ return __arm_vldrbq_z_u8 ( __base, __p); + } + + __extension__ extern __inline int8x16_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vld1q_z_s8 (int8_t const *__base, mve_pred16_t __p) + { +- return vldrbq_z_s8 ( __base, __p); ++ return __arm_vldrbq_z_s8 ( __base, __p); + } + + __extension__ extern __inline int8x16x2_t +@@ -16253,14 +16253,14 @@ __extension__ extern __inline void + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vst1q_p_u16 (uint16_t * __addr, uint16x8_t __value, mve_pred16_t __p) + { +- return vstrhq_p_u16 (__addr, __value, __p); ++ return __arm_vstrhq_p_u16 (__addr, __value, __p); + } + + __extension__ extern __inline void + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vst1q_p_s16 (int16_t * __addr, int16x8_t __value, mve_pred16_t __p) + { +- return vstrhq_p_s16 (__addr, __value, __p); ++ return __arm_vstrhq_p_s16 (__addr, __value, __p); + } + + __extension__ extern __inline void +@@ -16285,14 +16285,14 @@ __extension__ extern __inline uint16x8_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vld1q_z_u16 (uint16_t const *__base, mve_pred16_t __p) + { +- return vldrhq_z_u16 ( __base, __p); ++ return __arm_vldrhq_z_u16 ( __base, __p); + } + + __extension__ extern __inline int16x8_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vld1q_z_s16 (int16_t const *__base, mve_pred16_t __p) + { +- return vldrhq_z_s16 ( __base, __p); ++ return __arm_vldrhq_z_s16 ( __base, __p); + } + + __extension__ extern __inline int16x8x2_t +@@ -16335,14 +16335,14 @@ __extension__ extern __inline void + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vst1q_p_u32 (uint32_t * __addr, uint32x4_t __value, mve_pred16_t __p) + { +- return vstrwq_p_u32 (__addr, __value, __p); ++ return __arm_vstrwq_p_u32 (__addr, __value, __p); + } + + __extension__ extern __inline void + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vst1q_p_s32 (int32_t * __addr, int32x4_t __value, mve_pred16_t __p) + { +- return vstrwq_p_s32 (__addr, __value, __p); ++ return __arm_vstrwq_p_s32 (__addr, __value, __p); + } + + __extension__ extern __inline void +@@ -16367,14 +16367,14 @@ __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vld1q_z_u32 (uint32_t const *__base, mve_pred16_t __p) + { +- return vldrwq_z_u32 ( __base, __p); ++ return __arm_vldrwq_z_u32 ( __base, __p); + } + + __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vld1q_z_s32 (int32_t const *__base, mve_pred16_t __p) + { +- return vldrwq_z_s32 ( __base, __p); ++ return __arm_vldrwq_z_s32 ( __base, __p); + } + + __extension__ extern __inline int32x4x2_t +@@ -19837,7 +19837,7 @@ __extension__ extern __inline float16x8_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vld1q_z_f16 (float16_t const *__base, mve_pred16_t __p) + { +- return vldrhq_z_f16 (__base, __p); ++ return __arm_vldrhq_z_f16 (__base, __p); + } + + __extension__ extern __inline void +@@ -19853,7 +19853,7 @@ __extension__ extern __inline void + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vst1q_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p) + { +- return vstrhq_p_f16 (__addr, __value, __p); ++ return __arm_vstrhq_p_f16 (__addr, __value, __p); + } + + __extension__ extern __inline float32x4x4_t +@@ -19878,7 +19878,7 @@ __extension__ extern __inline float32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vld1q_z_f32 (float32_t const *__base, mve_pred16_t __p) + { +- return vldrwq_z_f32 (__base, __p); ++ return __arm_vldrwq_z_f32 (__base, __p); + } + + __extension__ extern __inline void +@@ -19894,7 +19894,7 @@ __extension__ extern __inline void + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) + __arm_vst1q_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t __p) + { +- return vstrwq_p_f32 (__addr, __value, __p); ++ return __arm_vstrwq_p_f32 (__addr, __value, __p); + } + + __extension__ extern __inline float16x8_t +@@ -26417,42 +26417,42 @@ __arm_vabdq_m (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16 + + __extension__ extern __inline int8x16_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) + { + return __arm_vaddq_m_n_s8 (__inactive, __a, __b, __p); + } + + __extension__ extern __inline int32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) + { + return __arm_vaddq_m_n_s32 (__inactive, __a, __b, __p); + } + + __extension__ extern __inline int16x8_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) + { + return __arm_vaddq_m_n_s16 (__inactive, __a, __b, __p); + } + + __extension__ extern __inline uint8x16_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) + { + return __arm_vaddq_m_n_u8 (__inactive, __a, __b, __p); + } + + __extension__ extern __inline uint32x4_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) + { + return __arm_vaddq_m_n_u32 (__inactive, __a, __b, __p); + } + + __extension__ extern __inline uint16x8_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +-__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, int __b, mve_pred16_t __p) ++__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) + { + return __arm_vaddq_m_n_u16 (__inactive, __a, __b, __p); + } +@@ -35582,13 +35582,29 @@ enum { + short: __ARM_mve_type_int_n, \ + int: __ARM_mve_type_int_n, \ + long: __ARM_mve_type_int_n, \ +- double: __ARM_mve_type_fp_n, \ + long long: __ARM_mve_type_int_n, \ ++ _Float16: __ARM_mve_type_fp_n, \ ++ __fp16: __ARM_mve_type_fp_n, \ ++ float: __ARM_mve_type_fp_n, \ ++ double: __ARM_mve_type_fp_n, \ + unsigned char: __ARM_mve_type_int_n, \ + unsigned short: __ARM_mve_type_int_n, \ + unsigned int: __ARM_mve_type_int_n, \ + unsigned long: __ARM_mve_type_int_n, \ + unsigned long long: __ARM_mve_type_int_n, \ ++ signed char*: __ARM_mve_type_int8_t_ptr, \ ++ short*: __ARM_mve_type_int16_t_ptr, \ ++ int*: __ARM_mve_type_int32_t_ptr, \ ++ long*: __ARM_mve_type_int32_t_ptr, \ ++ long long*: __ARM_mve_type_int64_t_ptr, \ ++ _Float16*: __ARM_mve_type_float16_t_ptr, \ ++ __fp16*: __ARM_mve_type_float16_t_ptr, \ ++ float*: __ARM_mve_type_float32_t_ptr, \ ++ unsigned char*: __ARM_mve_type_uint8_t_ptr, \ ++ unsigned short*: __ARM_mve_type_uint16_t_ptr, \ ++ unsigned int*: __ARM_mve_type_uint32_t_ptr, \ ++ unsigned long*: __ARM_mve_type_uint32_t_ptr, \ ++ unsigned long long*: __ARM_mve_type_uint64_t_ptr, \ + default: __ARM_mve_unsupported_type)) + #else + #define __ARM_mve_typeid(x) _Generic(x, \ +@@ -35647,30 +35663,67 @@ enum { + unsigned int: __ARM_mve_type_int_n, \ + unsigned long: __ARM_mve_type_int_n, \ + unsigned long long: __ARM_mve_type_int_n, \ ++ signed char*: __ARM_mve_type_int8_t_ptr, \ ++ short*: __ARM_mve_type_int16_t_ptr, \ ++ int*: __ARM_mve_type_int32_t_ptr, \ ++ long*: __ARM_mve_type_int32_t_ptr, \ ++ long long*: __ARM_mve_type_int64_t_ptr, \ ++ unsigned char*: __ARM_mve_type_uint8_t_ptr, \ ++ unsigned short*: __ARM_mve_type_uint16_t_ptr, \ ++ unsigned int*: __ARM_mve_type_uint32_t_ptr, \ ++ unsigned long*: __ARM_mve_type_uint32_t_ptr, \ ++ unsigned long long*: __ARM_mve_type_uint64_t_ptr, \ + default: __ARM_mve_unsupported_type)) + #endif /* MVE Floating point. */ + + extern void *__ARM_undef; + #define __ARM_mve_coerce(param, type) \ + _Generic(param, type: param, default: *(type *)__ARM_undef) +-#define __ARM_mve_coerce1(param, type) \ +- _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef) +-#define __ARM_mve_coerce2(param, type) \ +- _Generic(param, type: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef) ++#define __ARM_mve_coerce_i_scalar(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef)) ++ ++#define __ARM_mve_coerce_s8_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, signed char*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_u8_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned char*: param, default: *(type *)__ARM_undef)) ++ ++#define __ARM_mve_coerce_s16_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, short*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_u16_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned short*: param, default: *(type *)__ARM_undef)) ++ ++#define __ARM_mve_coerce_s32_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, int*: param, long*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_u32_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned int*: param, unsigned long*: param, default: *(type *)__ARM_undef)) ++ ++#define __ARM_mve_coerce_s64_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, long long*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_u64_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned long long*: param, default: *(type *)__ARM_undef)) ++ ++#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ ++#define __ARM_mve_coerce_f_scalar(param, type) \ ++ _Generic(param, type: param, const type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_f16_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, __fp16*: param, _Float16*: param, default: *(type *)__ARM_undef)) ++#define __ARM_mve_coerce_f32_ptr(param, type) \ ++ _Generic(param, type: param, const type: param, default: _Generic (param, float*: param, default: *(type *)__ARM_undef)) ++#endif + + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + + #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce_f16_ptr(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) + + #define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -35847,6 +35900,10 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));}) + +@@ -35871,16 +35928,16 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(p0, float16x8_t), __ARM_mve_coerce(p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(p0, float32x4_t), __ARM_mve_coerce(p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -35897,10 +35954,10 @@ extern void *__ARM_undef; + #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -35925,14 +35982,14 @@ extern void *__ARM_undef; + #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -35957,14 +36014,14 @@ extern void *__ARM_undef; + #define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -35995,16 +36052,16 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));}) + + #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36012,13 +36069,13 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36028,11 +36085,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36040,25 +36097,25 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36113,8 +36170,8 @@ extern void *__ARM_undef; + #define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36125,14 +36182,14 @@ extern void *__ARM_undef; + #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36143,8 +36200,8 @@ extern void *__ARM_undef; + #define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -36166,14 +36223,14 @@ extern void *__ARM_undef; + #define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36186,8 +36243,8 @@ extern void *__ARM_undef; + #define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -36242,12 +36299,12 @@ extern void *__ARM_undef; + #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36278,12 +36335,12 @@ extern void *__ARM_undef; + #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36334,12 +36391,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36347,9 +36404,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36382,8 +36439,8 @@ extern void *__ARM_undef; + #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +@@ -36396,17 +36453,17 @@ extern void *__ARM_undef; + #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + + #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) +@@ -36414,12 +36471,12 @@ extern void *__ARM_undef; + #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36452,12 +36509,12 @@ extern void *__ARM_undef; + #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36482,12 +36539,12 @@ extern void *__ARM_undef; + #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -36630,12 +36687,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36714,44 +36771,44 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36941,11 +36998,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +@@ -36957,11 +37014,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));}) + + #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36971,11 +37028,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));}) + + #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -36988,14 +37045,14 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));}) + + #define __arm_vcvtbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37049,8 +37106,8 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double)), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) + +@@ -37065,8 +37122,8 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double)));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)));}) + + #define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37089,14 +37146,14 @@ extern void *__ARM_undef; + #define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37107,14 +37164,14 @@ extern void *__ARM_undef; + #define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vrndnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37176,13 +37233,13 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));}) + + #define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37283,11 +37340,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + +@@ -37316,14 +37373,14 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37464,15 +37521,15 @@ extern void *__ARM_undef; + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vfmasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vfmsq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37507,14 +37564,14 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37541,14 +37598,14 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -37565,236 +37622,236 @@ extern void *__ARM_undef; + + #define __arm_vld1q(p0) (\ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ +- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce1(p0, float32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *)))) + + #define __arm_vld1q_z(p0,p1) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ +- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce1(p0, float16_t *), p1), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \ ++ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), p1), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1))) + + #define __arm_vld2q(p0) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ +- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce1(p0, float32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *)))) + + #define __arm_vld4q(p0) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ +- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce1(p0, float32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *)))) + + #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) + + #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + + #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));}) + + #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) + + #define __arm_vldrwq_gather_offset(p0,p1) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1))) + + #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2))) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2))) + + #define __arm_vldrwq_gather_shifted_offset(p0,p1) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1))) + + #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ( \ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2))) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2))) + + #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));}) + + #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));}) + + #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));}) + + #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + + #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + + #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + + #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + + #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));}) + + #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + + #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + + #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));}) + + #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));}) + + #define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ +@@ -37811,44 +37868,44 @@ extern void *__ARM_undef; + #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + + #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + + #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + + #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + + #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));}) + + #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ +- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));}) + + #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -38021,19 +38078,19 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ +@@ -38156,19 +38213,19 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ +@@ -38254,10 +38311,22 @@ extern void *__ARM_undef; + #define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ +- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ +- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) ++ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \ ++ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));}) + + #define __arm_vcmulq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ +@@ -38281,16 +38350,16 @@ extern void *__ARM_undef; + #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint64x2_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ +- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ ++ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + + #else /* MVE Integer. */ + +@@ -38306,12 +38375,12 @@ extern void *__ARM_undef; + + #define __arm_vst4q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) + + #define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -38408,12 +38477,12 @@ extern void *__ARM_undef; + #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38440,12 +38509,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -38459,12 +38528,12 @@ extern void *__ARM_undef; + #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38495,12 +38564,12 @@ extern void *__ARM_undef; + #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38569,12 +38638,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38582,16 +38651,16 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) +@@ -38599,12 +38668,12 @@ extern void *__ARM_undef; + #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38620,7 +38689,11 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38635,12 +38708,12 @@ extern void *__ARM_undef; + #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38715,12 +38788,12 @@ extern void *__ARM_undef; + #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38745,12 +38818,12 @@ extern void *__ARM_undef; + #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38800,10 +38873,10 @@ extern void *__ARM_undef; + #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +@@ -38820,12 +38893,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38856,12 +38929,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38942,16 +39015,16 @@ extern void *__ARM_undef; + #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + + #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) + +@@ -38961,9 +39034,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38971,9 +39044,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38981,9 +39054,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -38991,20 +39064,20 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +@@ -39029,12 +39102,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + #define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -39144,25 +39217,25 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39225,9 +39298,56 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) ++ ++ ++#define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ ++ __typeof(p1) __p1 = (p1); \ ++ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) ++ ++#define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ ++ __typeof(p1) __p1 = (p1); \ ++ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) ++ ++#define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ ++ __typeof(p1) __p1 = (p1); \ ++ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) ++ ++#define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ ++ __typeof(p1) __p1 = (p1); \ ++ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + #define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39250,23 +39370,23 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39291,9 +39411,9 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));}) + + #define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39456,12 +39576,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -39561,12 +39681,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -39594,12 +39714,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -39611,12 +39731,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -39631,12 +39751,12 @@ extern void *__ARM_undef; + + #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ +@@ -39645,144 +39765,144 @@ extern void *__ARM_undef; + + #define __arm_vld1q(p0) (\ + _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)))) + + #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vldrwq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vldrwq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));}) + + #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + + #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vstrdq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ +@@ -39797,58 +39917,58 @@ extern void *__ARM_undef; + #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -39953,15 +40073,15 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ +@@ -40055,15 +40175,15 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ +@@ -40147,29 +40267,45 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + + #define __arm_vld1q_z(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1))) + + #define __arm_vld2q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)))) + + + #define __arm_vld4q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ +- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ +- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ +- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *)))) ++ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \ ++ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \ ++ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \ ++ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)))) ++ ++#define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ ++ __typeof(p2) __p2 = (p2); \ ++ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -40185,14 +40321,14 @@ extern void *__ARM_undef; + #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint64x2_t), p2));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));}) + + #endif /* MVE Integer. */ + +@@ -40303,62 +40439,62 @@ extern void *__ARM_undef; + #define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_vdwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_vdwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_viwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_viwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_viwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_vidupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u8 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vddupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u8 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vidupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u16 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vddupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u16 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vidupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u32 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vddupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u32 ((uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ +@@ -40372,12 +40508,12 @@ extern void *__ARM_undef; + #define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -40402,12 +40538,12 @@ extern void *__ARM_undef; + #define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -40447,20 +40583,20 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_wb_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + + #define __arm_vldrdq_gather_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \ +- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1))) ++ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1))) + + #define __arm_vldrdq_gather_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2))) ++ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2))) + + #define __arm_vldrdq_gather_shifted_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \ +- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1))) ++ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1))) + + #define __arm_vldrdq_gather_shifted_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \ +- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2))) ++ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2))) + + #define __arm_vadciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -40516,36 +40652,36 @@ extern void *__ARM_undef; + + #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -40646,12 +40782,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -40666,9 +40802,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -40794,17 +40930,17 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + + #define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -40874,10 +41010,10 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int) , p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));}) ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2));}) + + #define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -40943,12 +41079,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -40982,12 +41118,12 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41015,23 +41151,23 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41077,12 +41213,12 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +@@ -41094,17 +41230,17 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ +- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ ++ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) +@@ -41115,15 +41251,15 @@ extern void *__ARM_undef; + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));}) + + #define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ +- int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ ++ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ ++ int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +@@ -41189,9 +41325,9 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + + #define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41202,12 +41338,12 @@ extern void *__ARM_undef; + + #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vidupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41215,9 +41351,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vddupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41225,89 +41361,89 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));}) + + #define __arm_vidupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u16 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vidupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u32 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vidupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u8 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vddupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u16 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vddupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u32 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_vddupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u8 ((uint32_t) __p0, p1), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));}) ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));}) + + #define __arm_viwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_viwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1, (const int) p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, (const int) p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, (const int) p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, (const int) p2));}) + + #define __arm_viwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_viwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vdwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));}) + + #define __arm_vdwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vdwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vdwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +- int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \ +- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));}) ++ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \ ++ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));}) + + #define __arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -41343,14 +41479,14 @@ extern void *__ARM_undef; + #define __arm_vaddlvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vaddlvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vaddlvq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -41365,22 +41501,22 @@ extern void *__ARM_undef; + #define __arm_vaddvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vaddvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vaddvq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ +@@ -41406,9 +41542,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmpcsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41416,9 +41552,9 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));}) + + #define __arm_vcmphiq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41426,16 +41562,16 @@ extern void *__ARM_undef; + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));}) + + #define __arm_vcmphiq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ +- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ +- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ ++ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ ++ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) +@@ -41532,34 +41668,34 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vmladavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vmladavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41602,17 +41738,17 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vmlaldavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));}) + + #define __arm_vmlaldavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ +@@ -41776,22 +41912,22 @@ extern void *__ARM_undef; + + #define __arm_vstrbq(p0,p1) ({ __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + + #define __arm_vstrbq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + + #define __arm_vstrdq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ +@@ -41807,61 +41943,61 @@ extern void *__ARM_undef; + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + + #define __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ +- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ +- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ ++ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ ++ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + + #define __arm_vstrdq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ +- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) ++ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + + #define __arm_vstrdq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ +- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) ++ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + + #define __arm_vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ +- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) ++ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));}) + + #define __arm_vstrdq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \ +- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ +- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) ++ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \ ++ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));}) + + #endif /* __cplusplus */ + #endif /* __ARM_FEATURE_MVE */ +diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md +index db316d81dcc..10e7c9b9c32 100644 +--- a/gcc/config/arm/constraints.md ++++ b/gcc/config/arm/constraints.md +@@ -102,10 +102,6 @@ + (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2) + || (ival == 4) || (ival == 8))"))) + +-;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. +-(define_predicate "mve_vldrd_immediate" +- (match_test "satisfies_constraint_Ri (op)")) +- + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" + "The VFP registers @code{s0}-@code{s31}.") + +@@ -566,6 +562,22 @@ + (match_code "symbol_ref") + ) + ++;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. ++(define_constraint "Ri" ++ "@internal In Thumb-2 state a constant is multiple of 8 and in range ++ of -/+ 1016 for MVE" ++ (and (match_code "const_int") ++ (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) ++ && ((ival % 8) == 0)"))) ++ ++;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE. ++(define_constraint "Rl" ++ "@internal In Thumb-2 state a constant is multiple of 2 and in range ++ of -/+ 252 for MVE" ++ (and (match_code "const_int") ++ (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252) ++ && ((ival % 2) == 0)"))) ++ + (define_memory_constraint "Uz" + "@internal + A memory access that is accessible as an LDC/STC operand" +diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md +index 1d957dd2539..860d734b9a1 100644 +--- a/gcc/config/arm/mve.md ++++ b/gcc/config/arm/mve.md +@@ -134,7 +134,7 @@ + VRNDQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vrintzt.f%# %q0, %q2" ++ "vpst\;vrintzt.f%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -232,7 +232,7 @@ + VREV64Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vrev64.%# %q0, %q1" ++ "vrev64.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -245,7 +245,7 @@ + (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vneg.f%# %q0, %q1" ++ "vneg.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -259,7 +259,7 @@ + VDUPQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vdup.%# %q0, %1" ++ "vdup.%#\t%q0, %1" + [(set_attr "type" "mve_move") + ]) + +@@ -272,7 +272,7 @@ + (abs:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vabs.f%# %q0, %q1" ++ "vabs.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -286,7 +286,7 @@ + VREV32Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vrev32.16 %q0, %q1" ++ "vrev32.16\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + ;; +@@ -299,7 +299,7 @@ + VCVTTQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtt.f32.f16 %q0, %q1" ++ "vcvtt.f32.f16\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -313,7 +313,7 @@ + VCVTBQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtb.f32.f16 %q0, %q1" ++ "vcvtb.f32.f16\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -327,7 +327,7 @@ + VCVTQ_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvt.f%#.%# %q0, %q1" ++ "vcvt.f%#.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -341,7 +341,7 @@ + VREV64Q)) + ] + "TARGET_HAVE_MVE" +- "vrev64.%# %q0, %q1" ++ "vrev64.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -355,7 +355,7 @@ + VCVTQ_FROM_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvt.%#.f%# %q0, %q1" ++ "vcvt.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + ;; [vqnegq_s]) +@@ -367,7 +367,7 @@ + VQNEGQ_S)) + ] + "TARGET_HAVE_MVE" +- "vqneg.s%# %q0, %q1" ++ "vqneg.s%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -381,7 +381,7 @@ + VQABSQ_S)) + ] + "TARGET_HAVE_MVE" +- "vqabs.s%# %q0, %q1" ++ "vqabs.s%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -394,7 +394,7 @@ + (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE" +- "vneg.s%# %q0, %q1" ++ "vneg.s%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -428,7 +428,7 @@ + VDUPQ_N)) + ] + "TARGET_HAVE_MVE" +- "vdup.%# %q0, %1" ++ "vdup.%#\t%q0, %1" + [(set_attr "type" "mve_move") + ]) + +@@ -441,7 +441,7 @@ + (clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE" +- "vclz.i%# %q0, %q1" ++ "vclz.i%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + (define_expand "mve_vclzq_u" +@@ -462,7 +462,7 @@ + VCLSQ_S)) + ] + "TARGET_HAVE_MVE" +- "vcls.s%# %q0, %q1" ++ "vcls.s%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -517,7 +517,7 @@ + VMOVLTQ)) + ] + "TARGET_HAVE_MVE" +- "vmovlt.%# %q0, %q1" ++ "vmovlt.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -531,7 +531,7 @@ + VMOVLBQ)) + ] + "TARGET_HAVE_MVE" +- "vmovlb.%# %q0, %q1" ++ "vmovlb.%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -545,7 +545,7 @@ + VCVTPQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtp.%#.f%# %q0, %q1" ++ "vcvtp.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -559,7 +559,7 @@ + VCVTNQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtn.%#.f%# %q0, %q1" ++ "vcvtn.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -573,7 +573,7 @@ + VCVTMQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtm.%#.f%# %q0, %q1" ++ "vcvtm.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -587,7 +587,7 @@ + VCVTAQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvta.%#.f%# %q0, %q1" ++ "vcvta.%#.f%#\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -601,7 +601,7 @@ + VMVNQ_N)) + ] + "TARGET_HAVE_MVE" +- "vmvn.i%# %q0, %1" ++ "vmvn.i%#\t%q0, %1" + [(set_attr "type" "mve_move") + ]) + +@@ -615,7 +615,7 @@ + VREV16Q)) + ] + "TARGET_HAVE_MVE" +- "vrev16.8 %q0, %q1" ++ "vrev16.8\t%q0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -629,7 +629,7 @@ + VADDLVQ)) + ] + "TARGET_HAVE_MVE" +- "vaddlv.32 %Q0, %R0, %q1" ++ "vaddlv.32\t%Q0, %R0, %q1" + [(set_attr "type" "mve_move") + ]) + +@@ -643,7 +643,7 @@ + VCTPQ)) + ] + "TARGET_HAVE_MVE" +- "vctp. %1" ++ "vctp.\t%1" + [(set_attr "type" "mve_move") + ]) + +@@ -672,7 +672,7 @@ + VSUBQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vsub.f %q0, %q1, %2" ++ "vsub.f\t%q0, %q1, %2" + [(set_attr "type" "mve_move") + ]) + +@@ -687,7 +687,7 @@ + VBRSRQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vbrsr. %q0, %q1, %2" ++ "vbrsr.\t%q0, %q1, %2" + [(set_attr "type" "mve_move") + ]) + +@@ -716,7 +716,7 @@ + VCREATEQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" ++ "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -731,7 +731,7 @@ + VCREATEQ)) + ] + "TARGET_HAVE_MVE" +- "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1" ++ "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -810,7 +810,7 @@ + VADDLVQ_P)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vaddlvt.32 %Q0, %R0, %q1" ++ "vpst\;vaddlvt.32\t%Q0, %R0, %q1" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -824,7 +824,7 @@ + (match_operand:MVE_2 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE" +- "vcmp.%# , %q1, %q2" ++ "vcmp.%#\t, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -873,7 +873,7 @@ + VADDQ_N)) + ] + "TARGET_HAVE_MVE" +- "vadd.i%# %q0, %q1, %2" ++ "vadd.i%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") + ]) + +@@ -888,7 +888,7 @@ + VADDVAQ)) + ] + "TARGET_HAVE_MVE" +- "vaddva.%# %0, %q2" ++ "vaddva.%#\t%0, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -969,7 +969,7 @@ + VBRSRQ_N)) + ] + "TARGET_HAVE_MVE" +- "vbrsr.%# %q0, %q1, %2" ++ "vbrsr.%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") + ]) + +@@ -1828,7 +1828,7 @@ + VADDLVAQ)) + ] + "TARGET_HAVE_MVE" +- "vaddlva.32 %Q0, %R0, %q2" ++ "vaddlva.32\t%Q0, %R0, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -1843,7 +1843,7 @@ + VADDQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vadd.f%# %q0, %q1, %2" ++ "vadd.f%#\t%q0, %q1, %2" + [(set_attr "type" "mve_move") + ]) + +@@ -1857,7 +1857,7 @@ + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vand %q0, %q1, %q2" ++ "vand\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -1871,7 +1871,7 @@ + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vbic %q0, %q1, %q2" ++ "vbic\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -1886,7 +1886,7 @@ + VBICQ_N)) + ] + "TARGET_HAVE_MVE" +- "vbic.i%# %q0, %2" ++ "vbic.i%#\t%q0, %2" + [(set_attr "type" "mve_move") + ]) + +@@ -1960,7 +1960,7 @@ + VCTPQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vctpt. %1" ++ "vpst\;vctpt.\t%1" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -1975,7 +1975,7 @@ + VCVTBQ_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtb.f16.f32 %q0, %q2" ++ "vcvtb.f16.f32\t%q0, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -1990,7 +1990,7 @@ + VCVTTQ_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vcvtt.f16.f32 %q0, %q2" ++ "vcvtt.f16.f32\t%q0, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2004,7 +2004,7 @@ + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "veor %q0, %q1, %q2" ++ "veor\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2152,7 +2152,7 @@ + VMLALDAVXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlaldavx.s%# %Q0, %R0, %q1, %q2" ++ "vmlaldavx.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2167,7 +2167,7 @@ + VMLSLDAVQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlsldav.s%# %Q0, %R0, %q1, %q2" ++ "vmlsldav.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2182,7 +2182,7 @@ + VMLSLDAVXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlsldavx.s%# %Q0, %R0, %q1, %q2" ++ "vmlsldavx.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2255,7 +2255,7 @@ + (match_operand:MVE_0 1 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vorn %q0, %q1, %q2" ++ "vorn\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2269,7 +2269,7 @@ + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vorr %q0, %q1, %q2" ++ "vorr\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2419,7 +2419,7 @@ + VRMLALDAVHXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2" ++ "vrmlaldavhx.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2538,7 +2538,7 @@ + VRMLALDAVHQ)) + ] + "TARGET_HAVE_MVE" +- "vrmlaldavh.32 %Q0, %R0, %q1, %q2" ++ "vrmlaldavh.32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -2554,7 +2554,7 @@ + VBICQ_M_N)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vbict.i%# %q0, %2" ++ "vpst\;vbict.i%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -2599,7 +2599,7 @@ + VCVTQ_M_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvtt.f%#.%# %q0, %q2" ++ "vpst\;vcvtt.f%#.%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -2644,7 +2644,7 @@ + VRMLALDAVHAQ)) + ] + "TARGET_HAVE_MVE" +- "vrmlaldavha.32 %Q0, %R0, %q2, %q3" ++ "vrmlaldavha.32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -2707,7 +2707,7 @@ + (match_dup 4)] + VSHLCQ))] + "TARGET_HAVE_MVE" +- "vshlc %q0, %1, %4") ++ "vshlc\t%q0, %1, %4") + + ;; + ;; [vabsq_m_s]) +@@ -3041,7 +3041,7 @@ + VDUPQ_M_N)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vdupt.%# %q0, %2" ++ "vpst\;vdupt.%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3265,7 +3265,7 @@ + VMVNQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmvnt %q0, %q2" ++ "vpst\;vmvnt\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3297,7 +3297,7 @@ + VPSELQ)) + ] + "TARGET_HAVE_MVE" +- "vpsel %q0, %q1, %q2" ++ "vpsel\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -3498,7 +3498,7 @@ + ;; + (define_insn "mve_vrev64q_m_" + [ +- (set (match_operand:MVE_2 0 "s_register_operand" "=w") ++ (set (match_operand:MVE_2 0 "s_register_operand" "=&w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand: 3 "vpr_register_operand" "Up")] +@@ -3712,7 +3712,7 @@ + VADDLVAQ_P)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vaddlvat.32 %Q0, %R0, %q2" ++ "vpst\;vaddlvat.32\t%Q0, %R0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -3922,7 +3922,7 @@ + VCVTBQ_M_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvtbt.f16.f32 %q0, %q2" ++ "vpst\;vcvtbt.f16.f32\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3938,7 +3938,7 @@ + VCVTBQ_M_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvtbt.f32.f16 %q0, %q2" ++ "vpst\;vcvtbt.f32.f16\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3954,7 +3954,7 @@ + VCVTTQ_M_F16_F32)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvttt.f16.f32 %q0, %q2" ++ "vpst\;vcvttt.f16.f32\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3970,7 +3970,7 @@ + VCVTTQ_M_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vcvttt.f32.f16 %q0, %q2" ++ "vpst\;vcvttt.f32.f16\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -3986,7 +3986,7 @@ + VDUPQ_M_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vdupt.%# %q0, %2" ++ "vpst\;vdupt.%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4158,7 +4158,7 @@ + VMLALDAVAQ)) + ] + "TARGET_HAVE_MVE" +- "vmlaldava.%# %Q0, %R0, %q2, %q3" ++ "vmlaldava.%#\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4174,7 +4174,7 @@ + VMLALDAVAXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlaldavax.s%# %Q0, %R0, %q2, %q3" ++ "vmlaldavax.s%#\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4190,7 +4190,7 @@ + VMLALDAVQ_P)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmlaldavt.%# %Q0, %R0, %q1, %q2" ++ "vpst\;vmlaldavt.%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4221,7 +4221,7 @@ + VMLSLDAVAQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlsldava.s%# %Q0, %R0, %q2, %q3" ++ "vmlsldava.s%#\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4237,7 +4237,7 @@ + VMLSLDAVAXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vmlsldavax.s%# %Q0, %R0, %q2, %q3" ++ "vmlsldavax.s%#\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4253,7 +4253,7 @@ + VMLSLDAVQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmlsldavt.s%# %Q0, %R0, %q1, %q2" ++ "vpst\;vmlsldavt.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4269,7 +4269,7 @@ + VMLSLDAVXQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmlsldavxt.s%# %Q0, %R0, %q1, %q2" ++ "vpst\;vmlsldavxt.s%#\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -4346,7 +4346,7 @@ + VMVNQ_M_N)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmvnt.i%# %q0, %2" ++ "vpst\;vmvnt.i%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -4377,7 +4377,7 @@ + VORRQ_M_N)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vorrt.i%# %q0, %2" ++ "vpst\;vorrt.i%#\t%q0, %2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; +@@ -4392,7 +4392,7 @@ + VPSELQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpsel %q0, %q1, %q2" ++ "vpsel\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -4568,7 +4568,7 @@ + VREV32Q_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vrev32t.16 %q0, %q2" ++ "vpst\;vrev32t.16\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4584,7 +4584,7 @@ + VREV32Q_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrev32t.%# %q0, %q2" ++ "vpst\;vrev32t.%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4593,14 +4593,14 @@ + ;; + (define_insn "mve_vrev64q_m_f" + [ +- (set (match_operand:MVE_0 0 "s_register_operand" "=w") ++ (set (match_operand:MVE_0 0 "s_register_operand" "=&w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand:MVE_0 2 "s_register_operand" "w") + (match_operand: 3 "vpr_register_operand" "Up")] + VREV64Q_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vrev64t.%# %q0, %q2" ++ "vpst\;vrev64t.%#\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4616,7 +4616,7 @@ + VRMLALDAVHAXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3" ++ "vrmlaldavhax.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4632,7 +4632,7 @@ + VRMLALDAVHXQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2" ++ "vpst\;vrmlaldavhxt.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4648,7 +4648,7 @@ + VRMLSLDAVHAXQ_S)) + ] + "TARGET_HAVE_MVE" +- "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3" ++ "vrmlsldavhax.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4664,7 +4664,7 @@ + VRMLSLDAVHQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2" ++ "vpst\;vrmlsldavht.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4680,7 +4680,7 @@ + VRMLSLDAVHXQ_P_S)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2" ++ "vpst\;vrmlsldavhxt.s32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4905,7 +4905,7 @@ + VREV16Q_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrev16t.8 %q0, %q2" ++ "vpst\;vrev16t.8\t%q0, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4937,7 +4937,7 @@ + VRMLALDAVHQ_P)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vrmlaldavht.32 %Q0, %R0, %q1, %q2" ++ "vpst\;vrmlaldavht.32\t%Q0, %R0, %q1, %q2" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -4953,7 +4953,7 @@ + VRMLSLDAVHAQ_S)) + ] + "TARGET_HAVE_MVE" +- "vrmlsldavha.s32 %Q0, %R0, %q2, %q3" ++ "vrmlsldavha.s32\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + ]) + +@@ -4972,7 +4972,7 @@ + "TARGET_HAVE_MVE" + "vpst\;vabavt.%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") +-]) ++ (set_attr "length" "8")]) + + ;; + ;; [vqshluq_m_n_s]) +@@ -4988,7 +4988,8 @@ + ] + "TARGET_HAVE_MVE" + "vpst\n\tvqshlut.s%#\t%q0, %q2, %3" +- [(set_attr "type" "mve_move")]) ++ [(set_attr "type" "mve_move") ++ (set_attr "length" "8")]) + + ;; + ;; [vshlq_m_s, vshlq_m_u]) +@@ -5004,7 +5005,8 @@ + ] + "TARGET_HAVE_MVE" + "vpst\;vshlt.%#\t%q0, %q2, %q3" +- [(set_attr "type" "mve_move")]) ++ [(set_attr "type" "mve_move") ++ (set_attr "length" "8")]) + + ;; + ;; [vsriq_m_n_s, vsriq_m_n_u]) +@@ -5020,7 +5022,8 @@ + ] + "TARGET_HAVE_MVE" + "vpst\;vsrit.%#\t%q0, %q2, %3" +- [(set_attr "type" "mve_move")]) ++ [(set_attr "type" "mve_move") ++ (set_attr "length" "8")]) + + ;; + ;; [vsubq_m_u, vsubq_m_s]) +@@ -5036,7 +5039,8 @@ + ] + "TARGET_HAVE_MVE" + "vpst\;vsubt.i%#\t%q0, %q2, %q3" +- [(set_attr "type" "mve_move")]) ++ [(set_attr "type" "mve_move") ++ (set_attr "length" "8")]) + + ;; + ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]) +@@ -5118,7 +5122,7 @@ + VANDQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vandt %q0, %q2, %q3" ++ "vpst\;vandt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -5135,7 +5139,7 @@ + VBICQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vbict %q0, %q2, %q3" ++ "vpst\;vbict\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -5203,7 +5207,7 @@ + VEORQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;veort %q0, %q2, %q3" ++ "vpst\;veort\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -5458,7 +5462,7 @@ + VORNQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vornt %q0, %q2, %q3" ++ "vpst\;vornt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -5475,7 +5479,7 @@ + VORRQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vorrt %q0, %q2, %q3" ++ "vpst\;vorrt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -6121,7 +6125,7 @@ + VMLALDAVAXQ_P)) + ] + "TARGET_HAVE_MVE" +- "vpst\;vmlaldavaxt.%# %Q0, %R0, %q2, %q3" ++ "vpst\;vmlaldavaxt.%#\t%Q0, %R0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -6647,7 +6651,7 @@ + VANDQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vandt %q0, %q2, %q3" ++ "vpst\;vandt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -6664,7 +6668,7 @@ + VBICQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vbict %q0, %q2, %q3" ++ "vpst\;vbict\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -6868,7 +6872,7 @@ + VEORQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;veort %q0, %q2, %q3" ++ "vpst\;veort\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -7021,7 +7025,7 @@ + VORNQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vornt %q0, %q2, %q3" ++ "vpst\;vornt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -7038,7 +7042,7 @@ + VORRQ_M_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vpst\;vorrt %q0, %q2, %q3" ++ "vpst\;vorrt\t%q0, %q2, %q3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -7265,15 +7269,13 @@ + } + [(set_attr "length" "8")]) + +-;; +-;; [vstrbq_p_s vstrbq_p_u] +-;; + (define_insn "mve_vstrbq_p_" + [(set (match_operand: 0 "mve_memory_operand" "=Ux") +- (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") +- (match_operand: 2 "vpr_register_operand" "Up")] +- VSTRBQ)) +- ] ++ (unspec: ++ [(match_operand:MVE_2 1 "s_register_operand" "w") ++ (match_operand: 2 "vpr_register_operand" "Up") ++ (match_dup 0)] ++ VSTRBQ))] + "TARGET_HAVE_MVE" + { + rtx ops[2]; +@@ -8072,10 +8074,11 @@ + ;; + (define_insn "mve_vstrhq_p_fv8hf" + [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") +- (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w") +- (match_operand:V8BI 2 "vpr_register_operand" "Up")] +- VSTRHQ_F)) +- ] ++ (unspec:V8HI ++ [(match_operand:V8HF 1 "s_register_operand" "w") ++ (match_operand:V8BI 2 "vpr_register_operand" "Up") ++ (match_dup 0)] ++ VSTRHQ_F))] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + { + rtx ops[2]; +@@ -8092,8 +8095,10 @@ + ;; + (define_insn "mve_vstrhq_p_" + [(set (match_operand: 0 "mve_memory_operand" "=Ux") +- (unspec: [(match_operand:MVE_6 1 "s_register_operand" "w") +- (match_operand: 2 "vpr_register_operand" "Up")] ++ (unspec: ++ [(match_operand:MVE_6 1 "s_register_operand" "w") ++ (match_operand: 2 "vpr_register_operand" "Up") ++ (match_dup 0)] + VSTRHQ)) + ] + "TARGET_HAVE_MVE" +@@ -8271,10 +8276,11 @@ + ;; + (define_insn "mve_vstrwq_p_fv4sf" + [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") +- (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w") +- (match_operand: 2 "vpr_register_operand" "Up")] +- VSTRWQ_F)) +- ] ++ (unspec:V4SI ++ [(match_operand:V4SF 1 "s_register_operand" "w") ++ (match_operand: 2 "vpr_register_operand" "Up") ++ (match_dup 0)] ++ VSTRWQ_F))] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + { + rtx ops[2]; +@@ -8291,10 +8297,11 @@ + ;; + (define_insn "mve_vstrwq_p_v4si" + [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") +- (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") +- (match_operand:V4BI 2 "vpr_register_operand" "Up")] +- VSTRWQ)) +- ] ++ (unspec:V4SI ++ [(match_operand:V4SI 1 "s_register_operand" "w") ++ (match_operand:V4BI 2 "vpr_register_operand" "Up") ++ (match_dup 0)] ++ VSTRWQ))] + "TARGET_HAVE_MVE" + { + rtx ops[2]; +@@ -8478,7 +8485,7 @@ + (match_operand:HI 3 "vpr_register_operand" "Up")] + VSTRDSSOQ))] + "TARGET_HAVE_MVE" +- "vpst\;vstrdt.64\t%q2, [%0, %q1, UXTW #3]" ++ "vpst\;vstrdt.64\t%q2, [%0, %q1, uxtw #3]" + [(set_attr "length" "8")]) + + ;; +@@ -8507,7 +8514,7 @@ + (match_operand:V2DI 2 "s_register_operand" "w")] + VSTRDSSOQ))] + "TARGET_HAVE_MVE" +- "vstrd.64\t%q2, [%0, %q1, UXTW #3]" ++ "vstrd.64\t%q2, [%0, %q1, uxtw #3]" + [(set_attr "length" "4")]) + + ;; +@@ -8923,7 +8930,7 @@ + (match_operand:MVE_2 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE" +- "vadd.i%# %q0, %q1, %q2" ++ "vadd.i%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -8937,7 +8944,7 @@ + (match_operand:MVE_0 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +- "vadd.f%# %q0, %q1, %q2" ++ "vadd.f%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") + ]) + +@@ -9038,7 +9045,7 @@ + (minus:SI (match_dup 2) + (match_operand:SI 4 "immediate_operand" "i")))] + "TARGET_HAVE_MVE" +- "vddup.u%# %q0, %1, %3") ++ "vddup.u%#\t%q0, %1, %3") + + ;; + ;; [vddupq_m_n_u]) +@@ -9074,7 +9081,7 @@ + (minus:SI (match_dup 3) + (match_operand:SI 6 "immediate_operand" "i")))] + "TARGET_HAVE_MVE" +- "vpst\;\tvddupt.u%#\t%q0, %2, %4" ++ "vpst\;vddupt.u%#\t%q0, %2, %4" + [(set_attr "length""8")]) + + ;; +@@ -9190,7 +9197,7 @@ + VDWDUPQ_M)) + ] + "TARGET_HAVE_MVE" +- "vpst\;\tvdwdupt.u%#\t%q2, %3, %R4, %5" ++ "vpst\;vdwdupt.u%#\t%q2, %3, %R4, %5" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) + +@@ -9345,7 +9352,7 @@ + [(match_operand:V4SI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V4SI 3 "s_register_operand" "w") +- (match_operand:V4BI 4 "vpr_register_operand")] ++ (match_operand:V4BI 4 "vpr_register_operand" "Up")] + VSTRWSBWBQ)) + (set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_dup 1) (match_dup 2)] +@@ -9394,9 +9401,9 @@ + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 1 "s_register_operand" "0") +- (match_operand:SI 2 "mve_vldrd_immediate" "Ri") ++ (match_operand:SI 2 "mve_vstrw_immediate" "Rl") + (match_operand:V4SF 3 "s_register_operand" "w") +- (match_operand:V4BI 4 "vpr_register_operand")] ++ (match_operand:V4BI 4 "vpr_register_operand" "Up")] + VSTRWQSBWB_F)) + (set (match_operand:V4SI 0 "s_register_operand" "=w") + (unspec:V4SI [(match_dup 1) (match_dup 2)] +@@ -9408,7 +9415,7 @@ + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; +- output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); ++ output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops); + return ""; + } + [(set_attr "length" "8")]) +@@ -9447,7 +9454,7 @@ + [(match_operand:V2DI 1 "s_register_operand" "0") + (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:V2DI 3 "s_register_operand" "w") +- (match_operand:HI 4 "vpr_register_operand")] ++ (match_operand:HI 4 "vpr_register_operand" "Up")] + VSTRDSBWBQ)) + (set (match_operand:V2DI 0 "s_register_operand" "=w") + (unspec:V2DI [(match_dup 1) (match_dup 2)] +@@ -9459,7 +9466,7 @@ + ops[0] = operands[1]; + ops[1] = operands[2]; + ops[2] = operands[3]; +- output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops); ++ output_asm_insn ("vpst\;vstrdt.u64\t%q2, [%q0, %1]!",ops); + return ""; + } + [(set_attr "length" "8")]) +@@ -9768,7 +9775,7 @@ + + (define_insn "get_fpscr_nzcvqc" + [(set (match_operand:SI 0 "register_operand" "=r") +- (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] ++ (unspec_volatile:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] + "TARGET_HAVE_MVE" + "vmrs\\t%0, FPSCR_nzcvqc" + [(set_attr "type" "mve_move")]) +diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md +index 67f2fdb4f8f..b6eb12632d4 100644 +--- a/gcc/config/arm/predicates.md ++++ b/gcc/config/arm/predicates.md +@@ -73,13 +73,13 @@ + (define_predicate "mve_imm_selective_upto_8" + (match_test "satisfies_constraint_Rg (op)")) + +-;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. +-(define_constraint "Ri" +- "@internal In Thumb-2 state a constant is multiple of 8 and in range +- of -/+ 1016 for MVE" +- (and (match_code "const_int") +- (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) +- && ((ival % 8) == 0)"))) ++;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. ++(define_predicate "mve_vldrd_immediate" ++ (match_test "satisfies_constraint_Ri (op)")) ++ ++;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE. ++(define_predicate "mve_vstrw_immediate" ++ (match_test "satisfies_constraint_Rl (op)")) + + ; Predicate for stack protector guard's address in + ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns +diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md +index d0f423cc3c5..31e5818d4e3 100644 +--- a/gcc/config/arm/vfp.md ++++ b/gcc/config/arm/vfp.md +@@ -105,9 +105,9 @@ + case 8: + return "vmov%?.f32\t%0, %1\t%@ int"; + case 9: +- return "vmsr%?\t P0, %1\t@ movhi"; ++ return "vmsr%?\tp0, %1\t@ movhi"; + case 10: +- return "vmrs%?\t %0, P0\t@ movhi"; ++ return "vmrs%?\t%0, p0\t@ movhi"; + default: + gcc_unreachable (); + } +@@ -209,9 +209,9 @@ + case 8: + return "vmov%?.f32\t%0, %1\t%@ int"; + case 9: +- return "vmsr%?\t P0, %1\t%@ movhi"; ++ return "vmsr%?\tp0, %1\t%@ movhi"; + case 10: +- return "vmrs%?\t%0, P0\t%@ movhi"; ++ return "vmrs%?\t%0, p0\t%@ movhi"; + default: + gcc_unreachable (); + } +@@ -312,9 +312,9 @@ + case 12: case 13: + return output_move_vfp (operands); + case 14: +- return \"vmsr\\t P0, %1\"; ++ return \"vmsr\\tp0, %1\"; + case 15: +- return \"vmrs\\t %0, P0\"; ++ return \"vmrs\\t%0, p0\"; + case 16: + return \"mcr\\tp10, 7, %1, cr1, cr0, 0\\t @SET_FPSCR\"; + case 17: +@@ -2138,7 +2138,7 @@ + (define_insn_and_split "no_literal_pool_df_immediate" + [(set (match_operand:DF 0 "s_register_operand" "=w") + (match_operand:DF 1 "const_double_operand" "F")) +- (clobber (match_operand:DF 2 "s_register_operand" "=r"))] ++ (clobber (match_operand:DI 2 "s_register_operand" "=r"))] + "arm_disable_literal_pool + && TARGET_VFP_BASE + && !arm_const_double_rtx (operands[1]) +@@ -2153,8 +2153,9 @@ + unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32); + ival |= (zext_hwi (buf[1 - order], 32) << 32); + rtx cst = gen_int_mode (ival, DImode); +- emit_move_insn (simplify_gen_subreg (DImode, operands[2], DFmode, 0), cst); +- emit_move_insn (operands[0], operands[2]); ++ emit_move_insn (operands[2], cst); ++ emit_move_insn (operands[0], ++ simplify_gen_subreg (DFmode, operands[2], DImode, 0)); + DONE; + } + ) +diff --git a/gcc/config/avr/avr-dimode.md b/gcc/config/avr/avr-dimode.md +index 6e491336915..28e97da0516 100644 +--- a/gcc/config/avr/avr-dimode.md ++++ b/gcc/config/avr/avr-dimode.md +@@ -455,12 +455,18 @@ + (define_expand "cbranch4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL8 1 "register_operand" "") +- (match_operand:ALL8 2 "nonmemory_operand" "")]) +- (label_ref (match_operand 3 "" "")) +- (pc)))] ++ [(match_operand:ALL8 1 "register_operand") ++ (match_operand:ALL8 2 "nonmemory_operand")]) ++ (label_ref (match_operand 3)) ++ (pc)))] + "avr_have_dimode" + { ++ int icode = (int) GET_CODE (operands[0]); ++ ++ targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false); ++ operands[0] = gen_rtx_fmt_ee ((enum rtx_code) icode, ++ VOIDmode, operands[1], operands[2]); ++ + rtx acc_a = gen_rtx_REG (mode, ACC_A); + + avr_fix_inputs (operands, 1 << 2, regmask (mode, ACC_A)); +@@ -490,8 +496,8 @@ + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(reg:ALL8 ACC_A) + (reg:ALL8 ACC_B)]) +- (label_ref (match_operand 1 "" "")) +- (pc)))] ++ (label_ref (match_operand 1)) ++ (pc)))] + "avr_have_dimode" + "#" + "&& reload_completed" +@@ -544,8 +550,8 @@ + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(reg:ALL8 ACC_A) + (match_operand:ALL8 1 "const_operand" "n Ynn")]) +- (label_ref (match_operand 2 "" "")) +- (pc))) ++ (label_ref (match_operand 2 "" "")) ++ (pc))) + (clobber (match_scratch:QI 3 "=&d"))] + "avr_have_dimode + && !s8_operand (operands[1], VOIDmode)" +diff --git a/gcc/config/avr/avr-passes.def b/gcc/config/avr/avr-passes.def +index d8630151090..ba0c3f10972 100644 +--- a/gcc/config/avr/avr-passes.def ++++ b/gcc/config/avr/avr-passes.def +@@ -43,3 +43,23 @@ INSERT_PASS_BEFORE (pass_free_cfg, 1, avr_pass_recompute_notes); + insns withaout any insns in between. */ + + INSERT_PASS_AFTER (pass_expand, 1, avr_pass_casesi); ++ ++/* If-else decision trees generated for switch / case may produce sequences ++ like ++ ++ SREG = compare (reg, val); ++ if (SREG == 0) goto label1; ++ SREG = compare (reg, 1 + val); ++ if (SREG >= 0) goto label2; ++ ++ which can be optimized to ++ ++ SREG = compare (reg, val); ++ if (SREG == 0) goto label1; ++ if (SREG >= 0) goto label2; ++ ++ The optimal place for such a pass would be directly after expand, but ++ it's not possible for a jump insn to target more than one code label. ++ Hence, run a mini pass right before split2 which introduces REG_CC. */ ++ ++INSERT_PASS_BEFORE (pass_split_after_reload, 1, avr_pass_ifelse); +diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h +index 6023b33bcfe..e164967038f 100644 +--- a/gcc/config/avr/avr-protos.h ++++ b/gcc/config/avr/avr-protos.h +@@ -58,6 +58,8 @@ extern const char *ret_cond_branch (rtx x, int len, int reverse); + extern const char *avr_out_movpsi (rtx_insn *, rtx*, int*); + extern const char *avr_out_sign_extend (rtx_insn *, rtx*, int*); + extern const char *avr_out_insert_notbit (rtx_insn *, rtx*, rtx, int*); ++extern const char *avr_out_plus_set_ZN (rtx*, int*); ++extern const char *avr_out_cmp_ext (rtx*, enum rtx_code, int*); + + extern const char *ashlqi3_out (rtx_insn *insn, rtx operands[], int *len); + extern const char *ashlhi3_out (rtx_insn *insn, rtx operands[], int *len); +@@ -112,8 +114,6 @@ extern int jump_over_one_insn_p (rtx_insn *insn, rtx dest); + + extern void avr_final_prescan_insn (rtx_insn *insn, rtx *operand, + int num_operands); +-extern int avr_simplify_comparison_p (machine_mode mode, +- RTX_CODE op, rtx x); + extern RTX_CODE avr_normalize_condition (RTX_CODE condition); + extern void out_shift_with_cnt (const char *templ, rtx_insn *insn, + rtx operands[], int *len, int t_len); +@@ -145,6 +145,7 @@ extern rtx tmp_reg_rtx; + extern rtx zero_reg_rtx; + extern rtx all_regs_rtx[32]; + extern rtx rampz_rtx; ++extern rtx cc_reg_rtx; + + #endif /* RTX_CODE */ + +@@ -160,6 +161,7 @@ class rtl_opt_pass; + extern rtl_opt_pass *make_avr_pass_pre_proep (gcc::context *); + extern rtl_opt_pass *make_avr_pass_recompute_notes (gcc::context *); + extern rtl_opt_pass *make_avr_pass_casesi (gcc::context *); ++extern rtl_opt_pass *make_avr_pass_ifelse (gcc::context *); + + /* From avr-log.cc */ + +diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc +index 4ed390e4cf9..c286acabf2c 100644 +--- a/gcc/config/avr/avr.cc ++++ b/gcc/config/avr/avr.cc +@@ -359,6 +359,41 @@ public: + } + }; // avr_pass_casesi + ++ ++static const pass_data avr_pass_data_ifelse = ++{ ++ RTL_PASS, // type ++ "", // name (will be patched) ++ OPTGROUP_NONE, // optinfo_flags ++ TV_DF_SCAN, // tv_id ++ 0, // properties_required ++ 0, // properties_provided ++ 0, // properties_destroyed ++ 0, // todo_flags_start ++ TODO_df_finish | TODO_df_verify // todo_flags_finish ++}; ++ ++class avr_pass_ifelse : public rtl_opt_pass ++{ ++public: ++ avr_pass_ifelse (gcc::context *ctxt, const char *name) ++ : rtl_opt_pass (avr_pass_data_ifelse, ctxt) ++ { ++ this->name = name; ++ } ++ ++ void avr_rest_of_handle_ifelse (function*); ++ ++ virtual bool gate (function*) { return optimize > 0; } ++ ++ virtual unsigned int execute (function *func) ++ { ++ avr_rest_of_handle_ifelse (func); ++ ++ return 0; ++ } ++}; // avr_pass_ifelse ++ + } // anon namespace + + rtl_opt_pass* +@@ -373,6 +408,12 @@ make_avr_pass_casesi (gcc::context *ctxt) + return new avr_pass_casesi (ctxt, "avr-casesi"); + } + ++rtl_opt_pass* ++make_avr_pass_ifelse (gcc::context *ctxt) ++{ ++ return new avr_pass_ifelse (ctxt, "avr-ifelse"); ++} ++ + + /* Make one parallel insn with all the patterns from insns i[0]..i[5]. */ + +@@ -686,6 +727,304 @@ avr_pass_casesi::avr_rest_of_handle_casesi (function *func) + } + + ++/* A helper for the next method. Suppose we have two conditional branches ++ ++ if (reg xval1) goto label1; ++ if (reg xval2) goto label2; ++ ++ If the second comparison is redundant and there is a code such ++ that the sequence can be performed as ++ ++ REG_CC = compare (reg, xval1); ++ if (REG_CC 0) goto label1; ++ if (REG_CC 0) goto label2; ++ ++ then return . Otherwise, return UNKNOWN. ++ xval1 and xval2 are CONST_INT, and mode is the scalar int mode in which ++ the comparison will be carried out. reverse_cond1 can be set to reverse ++ condition cond1. This is useful if the second comparison does not follow ++ the first one, but is located after label1 like in: ++ ++ if (reg xval1) goto label1; ++ ... ++ label1: ++ if (reg xval2) goto label2; */ ++ ++static enum rtx_code ++avr_redundant_compare (enum rtx_code cond1, rtx xval1, ++ enum rtx_code cond2, rtx xval2, ++ machine_mode mode, bool reverse_cond1) ++{ ++ HOST_WIDE_INT ival1 = INTVAL (xval1); ++ HOST_WIDE_INT ival2 = INTVAL (xval2); ++ ++ unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); ++ unsigned HOST_WIDE_INT uval1 = mask & UINTVAL (xval1); ++ unsigned HOST_WIDE_INT uval2 = mask & UINTVAL (xval2); ++ ++ if (reverse_cond1) ++ cond1 = reverse_condition (cond1); ++ ++ if (cond1 == EQ) ++ { ++ //////////////////////////////////////////////// ++ // A sequence like ++ // if (reg == val) goto label1; ++ // if (reg > val) goto label2; ++ // can be re-written using the same, simple comparison like in: ++ // REG_CC = compare (reg, val) ++ // if (REG_CC == 0) goto label1; ++ // if (REG_CC >= 0) goto label2; ++ if (ival1 == ival2 ++ && (cond2 == GT || cond2 == GTU)) ++ return avr_normalize_condition (cond2); ++ ++ // Similar, but the input sequence is like ++ // if (reg == val) goto label1; ++ // if (reg >= val) goto label2; ++ if (ival1 == ival2 ++ && (cond2 == GE || cond2 == GEU)) ++ return cond2; ++ ++ // Similar, but the input sequence is like ++ // if (reg == val) goto label1; ++ // if (reg >= val + 1) goto label2; ++ if ((cond2 == GE && ival2 == 1 + ival1) ++ || (cond2 == GEU && uval2 == 1 + uval1)) ++ return cond2; ++ ++ // Similar, but the input sequence is like ++ // if (reg == val) goto label1; ++ // if (reg > val - 1) goto label2; ++ if ((cond2 == GT && ival2 == ival1 - 1) ++ || (cond2 == GTU && uval2 == uval1 - 1)) ++ return avr_normalize_condition (cond2); ++ ++ ///////////////////////////////////////////////////////// ++ // A sequence like ++ // if (reg == val) goto label1; ++ // if (reg < 1 + val) goto label2; ++ // can be re-written as ++ // REG_CC = compare (reg, val) ++ // if (REG_CC == 0) goto label1; ++ // if (REG_CC < 0) goto label2; ++ if ((cond2 == LT && ival2 == 1 + ival1) ++ || (cond2 == LTU && uval2 == 1 + uval1)) ++ return cond2; ++ ++ // Similar, but with an input sequence like ++ // if (reg == val) goto label1; ++ // if (reg <= val) goto label2; ++ if (ival1 == ival2 ++ && (cond2 == LE || cond2 == LEU)) ++ return avr_normalize_condition (cond2); ++ ++ // Similar, but with an input sequence like ++ // if (reg == val) goto label1; ++ // if (reg < val) goto label2; ++ if (ival1 == ival2 ++ && (cond2 == LT || cond2 == LTU)) ++ return cond2; ++ ++ // Similar, but with an input sequence like ++ // if (reg == val) goto label1; ++ // if (reg <= val - 1) goto label2; ++ if ((cond2 == LE && ival2 == ival1 - 1) ++ || (cond2 == LEU && uval2 == uval1 - 1)) ++ return avr_normalize_condition (cond2); ++ ++ } // cond1 == EQ ++ ++ return UNKNOWN; ++} ++ ++ ++/* If-else decision trees generated for switch / case may produce sequences ++ like ++ ++ SREG = compare (reg, val); ++ if (SREG == 0) goto label1; ++ SREG = compare (reg, 1 + val); ++ if (SREG >= 0) goto label2; ++ ++ which can be optimized to ++ ++ SREG = compare (reg, val); ++ if (SREG == 0) goto label1; ++ if (SREG >= 0) goto label2; ++ ++ The optimal place for such a pass would be directly after expand, but ++ it's not possible for a jump insn to target more than one code label. ++ Hence, run a mini pass right before split2 which introduces REG_CC. */ ++ ++void ++avr_pass_ifelse::avr_rest_of_handle_ifelse (function*) ++{ ++ rtx_insn *next_insn; ++ ++ for (rtx_insn *insn = get_insns(); insn; insn = next_insn) ++ { ++ next_insn = next_nonnote_nondebug_insn (insn); ++ ++ if (! next_insn) ++ break; ++ ++ // Search for two cbranch insns. The first one is a cbranch. ++ // Filter for "cbranch4_insn" with mode in QI, HI, PSI, SI. ++ ++ if (! JUMP_P (insn)) ++ continue; ++ ++ int icode1 = recog_memoized (insn); ++ ++ if (icode1 != CODE_FOR_cbranchqi4_insn ++ && icode1 != CODE_FOR_cbranchhi4_insn ++ && icode1 != CODE_FOR_cbranchpsi4_insn ++ && icode1 != CODE_FOR_cbranchsi4_insn) ++ continue; ++ ++ rtx_jump_insn *insn1 = as_a (insn); ++ rtx_jump_insn *insn2 = nullptr; ++ bool follow_label1 = false; ++ ++ // Extract the operands of the first insn: ++ // $0 = comparison operator ($1, $2) ++ // $1 = reg ++ // $2 = reg or const_int ++ // $3 = code_label ++ // $4 = optional SCRATCH for HI, PSI, SI cases. ++ ++ const auto &op = recog_data.operand; ++ ++ extract_insn (insn1); ++ rtx xop1[5] = { op[0], op[1], op[2], op[3], op[4] }; ++ int n_operands = recog_data.n_operands; ++ ++ // For now, we can optimize cbranches that follow an EQ cbranch, ++ // and cbranches that follow the label of a NE cbranch. ++ ++ if (GET_CODE (xop1[0]) == EQ ++ && JUMP_P (next_insn) ++ && recog_memoized (next_insn) == icode1) ++ { ++ // The 2nd cbranch insn follows insn1, i.e. is located in the ++ // fallthrough path of insn1. ++ ++ insn2 = as_a (next_insn); ++ } ++ else if (GET_CODE (xop1[0]) == NE) ++ { ++ // insn1 might branch to a label followed by a cbranch. ++ ++ rtx target1 = JUMP_LABEL (insn1); ++ rtx_insn *code_label1 = JUMP_LABEL_AS_INSN (insn1); ++ rtx_insn *next = next_nonnote_nondebug_insn (code_label1); ++ rtx_insn *barrier = prev_nonnote_nondebug_insn (code_label1); ++ ++ if (// Target label of insn1 is used exactly once and ++ // is not a fallthru, i.e. is preceded by a barrier. ++ LABEL_NUSES (target1) == 1 ++ && barrier ++ && BARRIER_P (barrier) ++ // Following the target label is a cbranch of the same kind. ++ && next ++ && JUMP_P (next) ++ && recog_memoized (next) == icode1) ++ { ++ follow_label1 = true; ++ insn2 = as_a (next); ++ } ++ } ++ ++ if (! insn2) ++ continue; ++ ++ // Also extract operands of insn2, and filter for REG + CONST_INT ++ // comparsons against the same register. ++ ++ extract_insn (insn2); ++ rtx xop2[5] = { op[0], op[1], op[2], op[3], op[4] }; ++ ++ if (! rtx_equal_p (xop1[1], xop2[1]) ++ || ! CONST_INT_P (xop1[2]) ++ || ! CONST_INT_P (xop2[2])) ++ continue; ++ ++ machine_mode mode = GET_MODE (xop1[1]); ++ enum rtx_code code1 = GET_CODE (xop1[0]); ++ enum rtx_code code2 = GET_CODE (xop2[0]); ++ ++ code2 = avr_redundant_compare (code1, xop1[2], code2, xop2[2], ++ mode, follow_label1); ++ if (code2 == UNKNOWN) ++ continue; ++ ++ ////////////////////////////////////////////////////// ++ // Found a replacement. ++ ++ if (dump_file) ++ { ++ fprintf (dump_file, "\n;; Found chain of jump_insn %d and" ++ " jump_insn %d, follow_label1=%d:\n", ++ INSN_UID (insn1), INSN_UID (insn2), follow_label1); ++ print_rtl_single (dump_file, PATTERN (insn1)); ++ print_rtl_single (dump_file, PATTERN (insn2)); ++ } ++ ++ if (! follow_label1) ++ next_insn = next_nonnote_nondebug_insn (insn2); ++ ++ // Pop the new branch conditions and the new comparison. ++ // Prematurely split into compare + branch so that we can drop ++ // the 2nd comparison. The following pass, split2, splits all ++ // insns for REG_CC, and it should still work as usual even when ++ // there are already some REG_CC insns around. ++ ++ rtx xcond1 = gen_rtx_fmt_ee (code1, VOIDmode, cc_reg_rtx, const0_rtx); ++ rtx xcond2 = gen_rtx_fmt_ee (code2, VOIDmode, cc_reg_rtx, const0_rtx); ++ rtx xpat1 = gen_branch (xop1[3], xcond1); ++ rtx xpat2 = gen_branch (xop2[3], xcond2); ++ rtx xcompare = NULL_RTX; ++ ++ if (mode == QImode) ++ { ++ gcc_assert (n_operands == 4); ++ xcompare = gen_cmpqi3 (xop1[1], xop1[2]); ++ } ++ else ++ { ++ gcc_assert (n_operands == 5); ++ rtx (*gen_cmp)(rtx,rtx,rtx) ++ = mode == HImode ? gen_gen_comparehi ++ : mode == PSImode ? gen_gen_comparepsi ++ : gen_gen_comparesi; // SImode ++ xcompare = gen_cmp (xop1[1], xop1[2], xop1[4]); ++ } ++ ++ // Emit that stuff. ++ ++ rtx_insn *cmp = emit_insn_before (xcompare, insn1); ++ rtx_jump_insn *branch1 = emit_jump_insn_before (xpat1, insn1); ++ rtx_jump_insn *branch2 = emit_jump_insn_before (xpat2, insn2); ++ ++ JUMP_LABEL (branch1) = xop1[3]; ++ JUMP_LABEL (branch2) = xop2[3]; ++ // delete_insn() decrements LABEL_NUSES when deleting a JUMP_INSN, but ++ // when we pop a new JUMP_INSN, do it by hand. ++ ++LABEL_NUSES (xop1[3]); ++ ++LABEL_NUSES (xop2[3]); ++ ++ delete_insn (insn1); ++ delete_insn (insn2); ++ ++ // As a side effect, also recog the new insns. ++ gcc_assert (valid_insn_p (cmp)); ++ gcc_assert (valid_insn_p (branch1)); ++ gcc_assert (valid_insn_p (branch2)); ++ } // loop insns ++} ++ ++ + /* Set `avr_arch' as specified by `-mmcu='. + Return true on success. */ + +@@ -1019,6 +1358,19 @@ avr_no_gccisr_function_p (tree func) + return avr_lookup_function_attribute1 (func, "no_gccisr"); + } + ++ ++/* Implement `TARGET_CAN_INLINE_P'. */ ++/* Some options like -mgas_isr_prologues depend on optimization level, ++ and the inliner might think that due to different options, inlining ++ is not permitted; see PR104327. */ ++ ++static bool ++avr_can_inline_p (tree /* caller */, tree /* callee */) ++{ ++ // No restrictions whatsoever. ++ return true; ++} ++ + /* Implement `TARGET_SET_CURRENT_FUNCTION'. */ + /* Sanity cheching for above function attributes. */ + +@@ -3173,28 +3525,6 @@ avr_asm_final_postscan_insn (FILE *stream, rtx_insn *insn, rtx*, int) + } + + +-/* Return 0 if undefined, 1 if always true or always false. */ +- +-int +-avr_simplify_comparison_p (machine_mode mode, RTX_CODE op, rtx x) +-{ +- unsigned int max = (mode == QImode ? 0xff : +- mode == HImode ? 0xffff : +- mode == PSImode ? 0xffffff : +- mode == SImode ? 0xffffffff : 0); +- if (max && op && CONST_INT_P (x)) +- { +- if (unsigned_condition (op) != op) +- max >>= 1; +- +- if (max != (INTVAL (x) & max) +- && INTVAL (x) != 0xff) +- return 1; +- } +- return 0; +-} +- +- + /* Worker function for `FUNCTION_ARG_REGNO_P'. */ + /* Returns nonzero if REGNO is the number of a hard + register in which function arguments are sometimes passed. */ +@@ -5677,29 +6007,36 @@ avr_frame_pointer_required_p (void) + || get_frame_size () > 0); + } + +-/* Returns the condition of compare insn INSN, or UNKNOWN. */ ++ ++/* Returns the condition of the branch following INSN, where INSN is some ++ comparison. If the next insn is not a branch or the condition code set ++ by INSN might be used by more insns than the next one, return UNKNOWN. ++ For now, just look at the next insn, which misses some opportunities like ++ following jumps. */ + + static RTX_CODE + compare_condition (rtx_insn *insn) + { +- rtx_insn *next = next_real_insn (insn); ++ rtx set; ++ rtx_insn *next = next_real_nondebug_insn (insn); + +- if (next && JUMP_P (next)) ++ if (next ++ && JUMP_P (next) ++ // If SREG does not die in the next insn, it is used in more than one ++ // branch. This can happen due to pass .avr-ifelse optimizations. ++ && dead_or_set_regno_p (next, REG_CC) ++ // Branches are (set (pc) (if_then_else (COND (...)))). ++ && (set = single_set (next)) ++ && GET_CODE (SET_SRC (set)) == IF_THEN_ELSE) + { +- rtx pat = PATTERN (next); +- if (GET_CODE (pat) == PARALLEL) +- pat = XVECEXP (pat, 0, 0); +- rtx src = SET_SRC (pat); +- +- if (IF_THEN_ELSE == GET_CODE (src)) +- return GET_CODE (XEXP (src, 0)); ++ return GET_CODE (XEXP (SET_SRC (set), 0)); + } + + return UNKNOWN; + } + + +-/* Returns true iff INSN is a tst insn that only tests the sign. */ ++/* Returns true if INSN is a tst insn that only tests the sign. */ + + static bool + compare_sign_p (rtx_insn *insn) +@@ -5709,23 +6046,95 @@ compare_sign_p (rtx_insn *insn) + } + + +-/* Returns true iff the next insn is a JUMP_INSN with a condition +- that needs to be swapped (GT, GTU, LE, LEU). */ ++/* Returns true if INSN is a compare insn with the EQ or NE condition. */ + + static bool +-compare_diff_p (rtx_insn *insn) ++compare_eq_p (rtx_insn *insn) + { + RTX_CODE cond = compare_condition (insn); +- return (cond == GT || cond == GTU || cond == LE || cond == LEU) ? cond : 0; ++ return (cond == EQ || cond == NE); + } + +-/* Returns true iff INSN is a compare insn with the EQ or NE condition. */ + +-static bool +-compare_eq_p (rtx_insn *insn) ++/* Implement `TARGET_CANONICALIZE_COMPARISON'. */ ++/* Basically tries to convert "difficult" comparisons like GT[U] ++ and LE[U] to simple ones. Some asymmetric comparisons can be ++ transformed to EQ or NE against zero. */ ++ ++static void ++avr_canonicalize_comparison (int *icode, rtx *op0, rtx *op1, bool op0_fixed) + { +- RTX_CODE cond = compare_condition (insn); +- return (cond == EQ || cond == NE); ++ enum rtx_code code = (enum rtx_code) *icode; ++ machine_mode mode = GET_MODE (*op0); ++ ++ bool signed_p = code == GT || code == LE; ++ bool unsigned_p = code == GTU || code == LEU; ++ bool difficult_p = signed_p || unsigned_p; ++ ++ if (// Only do integers and fixed-points. ++ (! SCALAR_INT_MODE_P (mode) ++ && ! ALL_SCALAR_FIXED_POINT_MODE_P (mode)) ++ // Only do comparisons against a register. ++ || ! register_operand (*op0, mode)) ++ return; ++ ++ // Canonicalize "difficult" reg-reg comparisons. ++ ++ if (! op0_fixed ++ && difficult_p ++ && register_operand (*op1, mode)) ++ { ++ std::swap (*op0, *op1); ++ *icode = (int) swap_condition (code); ++ return; ++ } ++ ++ // Canonicalize comparisons against compile-time constants. ++ ++ if (CONST_INT_P (*op1) ++ || CONST_FIXED_P (*op1)) ++ { ++ // INT_MODE of the same size. ++ scalar_int_mode imode = int_mode_for_mode (mode).require (); ++ ++ unsigned HOST_WIDE_INT mask = GET_MODE_MASK (imode); ++ unsigned HOST_WIDE_INT maxval = signed_p ? mask >> 1 : mask; ++ ++ // Convert value *op1 to imode. ++ rtx xval = simplify_gen_subreg (imode, *op1, mode, 0); ++ ++ // Canonicalize difficult comparisons against const. ++ if (difficult_p ++ && (UINTVAL (xval) & mask) != maxval) ++ { ++ // Convert *op0 > *op1 to *op0 >= 1 + *op1. ++ // Convert *op0 <= *op1 to *op0 < 1 + *op1. ++ xval = simplify_binary_operation (PLUS, imode, xval, const1_rtx); ++ ++ // Convert value back to its original mode. ++ *op1 = simplify_gen_subreg (mode, xval, imode, 0); ++ ++ // Map > to >= and <= to <. ++ *icode = (int) avr_normalize_condition (code); ++ ++ return; ++ } ++ ++ // Some asymmetric comparisons can be turned into EQ or NE. ++ if (code == LTU && xval == const1_rtx) ++ { ++ *icode = (int) EQ; ++ *op1 = CONST0_RTX (mode); ++ return; ++ } ++ ++ if (code == GEU && xval == const1_rtx) ++ { ++ *icode = (int) NE; ++ *op1 = CONST0_RTX (mode); ++ return; ++ } ++ } + } + + +@@ -6018,6 +6427,68 @@ avr_out_tstsi (rtx_insn *insn, rtx *op, int *plen) + } + + ++/* Output a comparison of a zero- or sign-extended register against a ++ plain register. CODE is SIGN_EXTEND or ZERO_EXTEND. Return "". ++ ++ PLEN != 0: Set *PLEN to the code length in words. Don't output anything. ++ PLEN == 0: Print instructions. */ ++ ++const char* ++avr_out_cmp_ext (rtx xop[], enum rtx_code code, int *plen) ++{ ++ // The smaller reg is the one that's to be extended. Get its index as z. ++ int z = GET_MODE_SIZE (GET_MODE (xop[1])) < GET_MODE_SIZE (GET_MODE (xop[0])); ++ rtx zreg = xop[z]; ++ rtx reg = xop[1 - z]; ++ machine_mode mode = GET_MODE (reg); ++ machine_mode zmode = GET_MODE (zreg); ++ rtx zex; ++ ++ if (plen) ++ *plen = 0; ++ ++ // zex holds the extended bytes above zreg. This is 0 for ZERO_EXTEND, ++ // and 0 or -1 for SIGN_EXTEND. ++ ++ if (code == SIGN_EXTEND) ++ { ++ // Sign-extend the high-byte of zreg to tmp_reg. ++ int zmsb = GET_MODE_SIZE (zmode) - 1; ++ rtx xzmsb = simplify_gen_subreg (QImode, zreg, zmode, zmsb); ++ ++ avr_asm_len ("mov __tmp_reg__,%0" CR_TAB ++ "rol __tmp_reg__" CR_TAB ++ "sbc __tmp_reg__,__tmp_reg__", &xzmsb, plen, 3); ++ zex = tmp_reg_rtx; ++ } ++ else if (code == ZERO_EXTEND) ++ { ++ zex = zero_reg_rtx; ++ } ++ else ++ gcc_unreachable(); ++ ++ // Now output n_bytes bytes of the very comparison. ++ ++ int n_bytes = GET_MODE_SIZE (mode); ++ ++ avr_asm_len ("cp %0,%1", xop, plen, 1); ++ ++ for (int b = 1; b < n_bytes; ++b) ++ { ++ rtx regs[2]; ++ regs[1 - z] = simplify_gen_subreg (QImode, reg, mode, b); ++ regs[z] = (b < GET_MODE_SIZE (zmode) ++ ? simplify_gen_subreg (QImode, zreg, zmode, b) ++ : zex); ++ ++ avr_asm_len ("cpc %0,%1", regs, plen, 1); ++ } ++ ++ return ""; ++} ++ ++ + /* Generate asm equivalent for various shifts. This only handles cases + that are not already carefully hand-optimized in ?sh??i3_out. + +@@ -8160,6 +8631,122 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label) + } + + ++/* Output an instruction sequence for addition of REG in XOP[0] and CONST_INT ++ in XOP[1] in such a way that SREG.Z and SREG.N are set according to the ++ result. XOP[2] might be a d-regs clobber register. If XOP[2] is SCRATCH, ++ then the addition can be performed without a clobber reg. Return "". ++ ++ If PLEN == NULL, then output the instructions. ++ If PLEN != NULL, then set *PLEN to the length of the sequence in words. */ ++ ++const char* ++avr_out_plus_set_ZN (rtx *xop, int *plen) ++{ ++ if (plen) ++ *plen = 0; ++ ++ // Register to compare and value to compare against. ++ rtx xreg = xop[0]; ++ rtx xval = xop[1]; ++ ++ machine_mode mode = GET_MODE (xreg); ++ ++ // Number of bytes to operate on. ++ int n_bytes = GET_MODE_SIZE (mode); ++ ++ if (n_bytes == 1) ++ { ++ if (INTVAL (xval) == 1) ++ return avr_asm_len ("inc %0", xop, plen, 1); ++ ++ if (INTVAL (xval) == -1) ++ return avr_asm_len ("dec %0", xop, plen, 1); ++ } ++ ++ if (n_bytes == 2 ++ && test_hard_reg_class (ADDW_REGS, xreg) ++ && IN_RANGE (INTVAL (xval), 1, 63)) ++ { ++ // Add 16-bit value in [1..63] to a w register. ++ return avr_asm_len ("adiw %0, %1", xop, plen, 1); ++ } ++ ++ // Addition won't work; subtract the negative of XVAL instead. ++ xval = simplify_unary_operation (NEG, mode, xval, mode); ++ ++ // Value (0..0xff) held in clobber register xop[2] or -1 if unknown. ++ int clobber_val = -1; ++ ++ // [0] = Current sub-register. ++ // [1] = Current partial xval. ++ // [2] = 8-bit clobber d-register or SCRATCH. ++ rtx op[3]; ++ op[2] = xop[2]; ++ ++ // Work byte-wise from LSB to MSB. The lower two bytes might be ++ // SBIW'ed in one go. ++ for (int i = 0; i < n_bytes; ++i) ++ { ++ op[0] = simplify_gen_subreg (QImode, xreg, mode, i); ++ ++ if (i == 0 ++ && n_bytes >= 2 ++ && test_hard_reg_class (ADDW_REGS, op[0])) ++ { ++ op[1] = simplify_gen_subreg (HImode, xval, mode, 0); ++ if (IN_RANGE (INTVAL (op[1]), 0, 63)) ++ { ++ // SBIW can handle the lower 16 bits. ++ avr_asm_len ("sbiw %0, %1", op, plen, 1); ++ ++ // Next byte has already been handled: Skip it. ++ ++i; ++ continue; ++ } ++ } ++ ++ op[1] = simplify_gen_subreg (QImode, xval, mode, i); ++ ++ if (test_hard_reg_class (LD_REGS, op[0])) ++ { ++ // d-regs can subtract immediates. ++ avr_asm_len (i == 0 ++ ? "subi %0, %1" ++ : "sbci %0, %1", op, plen, 1); ++ } ++ else ++ { ++ int val8 = 0xff & INTVAL (op[1]); ++ if (val8 == 0) ++ { ++ // Any register can subtract 0. ++ avr_asm_len (i == 0 ++ ? "sub %0, __zero_reg__" ++ : "sbc %0, __zero_reg__", op, plen, 1); ++ } ++ else ++ { ++ // Use d-register to hold partial xval. ++ ++ if (val8 != clobber_val) ++ { ++ // Load partial xval to QI clobber reg and memoize for later. ++ gcc_assert (REG_P (op[2])); ++ avr_asm_len ("ldi %2, %1", op, plen, 1); ++ clobber_val = val8; ++ } ++ ++ avr_asm_len (i == 0 ++ ? "sub %0, %2" ++ : "sbc %0, %2", op, plen, 1); ++ } ++ } ++ } // Loop bytes. ++ ++ return ""; ++} ++ ++ + /* Output bit operation (IOR, AND, XOR) with register XOP[0] and compile + time constant XOP[2]: + +@@ -9291,6 +9878,8 @@ avr_adjust_insn_length (rtx_insn *insn, int len) + case ADJUST_LEN_TSTSI: avr_out_tstsi (insn, op, &len); break; + case ADJUST_LEN_COMPARE: avr_out_compare (insn, op, &len); break; + case ADJUST_LEN_COMPARE64: avr_out_compare64 (insn, op, &len); break; ++ case ADJUST_LEN_CMP_UEXT: avr_out_cmp_ext (op, ZERO_EXTEND, &len); break; ++ case ADJUST_LEN_CMP_SEXT: avr_out_cmp_ext (op, SIGN_EXTEND, &len); break; + + case ADJUST_LEN_LSHRQI: lshrqi3_out (insn, op, &len); break; + case ADJUST_LEN_LSHRHI: lshrhi3_out (insn, op, &len); break; +@@ -9311,6 +9900,7 @@ avr_adjust_insn_length (rtx_insn *insn, int len) + case ADJUST_LEN_CALL: len = AVR_HAVE_JMP_CALL ? 2 : 1; break; + + case ADJUST_LEN_INSERT_BITS: avr_out_insert_bits (op, &len); break; ++ case ADJUST_LEN_ADD_SET_ZN: avr_out_plus_set_ZN (op, &len); break; + + case ADJUST_LEN_INSV_NOTBIT: + avr_out_insert_notbit (insn, op, NULL_RTX, &len); +@@ -10607,6 +11197,58 @@ avr_mul_highpart_cost (rtx x, int) + } + + ++/* Return the expected cost of a conditional branch like ++ (set (pc) ++ (if_then_else (X) ++ (label_ref *) ++ (pc))) ++ where X is some comparison operator. */ ++ ++static int ++avr_cbranch_cost (rtx x) ++{ ++ bool difficult_p = difficult_comparison_operator (x, VOIDmode); ++ ++ if (reload_completed) ++ { ++ // After reload, we basically just have plain branches. ++ return COSTS_N_INSNS (1 + difficult_p); ++ } ++ ++ rtx xreg = XEXP (x, 0); ++ rtx xval = XEXP (x, 1); ++ machine_mode mode = GET_MODE (xreg); ++ if (mode == VOIDmode) ++ mode = GET_MODE (xval); ++ int size = GET_MODE_SIZE (mode); ++ ++ if (GET_CODE (xreg) == ZERO_EXTEND ++ || GET_CODE (xval) == ZERO_EXTEND) ++ { ++ // *cbranch..0/1, code = zero_extend. ++ return COSTS_N_INSNS (size + 1); ++ } ++ ++ if (GET_CODE (xreg) == SIGN_EXTEND ++ || GET_CODE (xval) == SIGN_EXTEND) ++ { ++ // *cbranch..0/1, code = sign_extend. ++ // Make it a bit cheaper than it actually is (less reg pressure). ++ return COSTS_N_INSNS (size + 1 + 1); ++ } ++ ++ bool reg_p = register_operand (xreg, mode); ++ bool reg_or_0_p = reg_or_0_operand (xval, mode); ++ ++ return COSTS_N_INSNS (size ++ // For the branch ++ + 1 + difficult_p ++ // Combine might propagate constants other than zero ++ // into the 2nd operand. Make that more expensive. ++ + 1 * (!reg_p || !reg_or_0_p)); ++} ++ ++ + /* Mutually recursive subroutine of avr_rtx_cost for calculating the + cost of an RTX operand given its context. X is the rtx of the + operand, MODE is its mode, and OUTER is the rtx_code of this +@@ -10844,6 +11486,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code, + *total += COSTS_N_INSNS (1); + return true; + } ++ if (IOR == code ++ && AND == GET_CODE (XEXP (x, 0)) ++ && AND == GET_CODE (XEXP (x, 1)) ++ && single_zero_operand (XEXP (XEXP (x, 0), 1), mode)) ++ { ++ // Open-coded bit transfer. ++ *total = COSTS_N_INSNS (2); ++ return true; ++ } + *total = COSTS_N_INSNS (GET_MODE_SIZE (mode)); + *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, 0, speed); + if (!CONST_INT_P (XEXP (x, 1))) +@@ -11490,6 +12141,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code, + } + break; + ++ case IF_THEN_ELSE: ++ if (outer_code == SET ++ && XEXP (x, 2) == pc_rtx ++ && ordered_comparison_operator (XEXP (x, 0), VOIDmode)) ++ { ++ *total = avr_cbranch_cost (XEXP (x, 0)); ++ return true; ++ } ++ + default: + break; + } +@@ -11515,6 +12175,52 @@ avr_rtx_costs (rtx x, machine_mode mode, int outer_code, + } + + ++/* Implement `TARGET_INSN_COST'. */ ++/* For some insns, it is not enough to look at the cost of the SET_SRC. ++ In that case, have a look at the entire insn, e.g. during insn combine. */ ++ ++static int ++avr_insn_cost (rtx_insn *insn, bool speed) ++{ ++ const int unknown_cost = -1; ++ int cost = unknown_cost; ++ ++ rtx set = single_set (insn); ++ ++ if (set ++ && ZERO_EXTRACT == GET_CODE (SET_DEST (set))) ++ { ++ // Try find anything that would flip the extracted bit. ++ bool not_bit_p = false; ++ ++ subrtx_iterator::array_type array; ++ FOR_EACH_SUBRTX (iter, array, SET_SRC (set), NONCONST) ++ { ++ enum rtx_code code = GET_CODE (*iter); ++ not_bit_p |= code == NOT || code == XOR || code == GE; ++ } ++ ++ // Don't go too deep into the analysis. In almost all cases, ++ // using BLD/BST is the best we can do for single-bit moves, ++ // even considering CSE. ++ cost = COSTS_N_INSNS (2 + not_bit_p); ++ } ++ ++ if (cost != unknown_cost) ++ { ++ if (avr_log.rtx_costs) ++ avr_edump ("\n%? (%s) insn_cost=%d\n%r\n", ++ speed ? "speed" : "size", cost, insn); ++ return cost; ++ } ++ ++ // Resort to what rtlanal.cc::insn_cost() implements as a default ++ // when targetm.insn_cost() is not implemented. ++ ++ return pattern_cost (PATTERN (insn), speed); ++} ++ ++ + /* Implement `TARGET_ADDRESS_COST'. */ + + static int +@@ -11602,281 +12308,6 @@ avr_normalize_condition (RTX_CODE condition) + } + } + +-/* Helper function for `avr_reorg'. */ +- +-static rtx +-avr_compare_pattern (rtx_insn *insn) +-{ +- rtx pattern = single_set (insn); +- +- if (pattern +- && NONJUMP_INSN_P (insn) +- && REG_P (SET_DEST (pattern)) +- && REGNO (SET_DEST (pattern)) == REG_CC +- && GET_CODE (SET_SRC (pattern)) == COMPARE) +- { +- machine_mode mode0 = GET_MODE (XEXP (SET_SRC (pattern), 0)); +- machine_mode mode1 = GET_MODE (XEXP (SET_SRC (pattern), 1)); +- +- /* The 64-bit comparisons have fixed operands ACC_A and ACC_B. +- They must not be swapped, thus skip them. */ +- +- if ((mode0 == VOIDmode || GET_MODE_SIZE (mode0) <= 4) +- && (mode1 == VOIDmode || GET_MODE_SIZE (mode1) <= 4)) +- return pattern; +- } +- +- return NULL_RTX; +-} +- +-/* Helper function for `avr_reorg'. */ +- +-/* Expansion of switch/case decision trees leads to code like +- +- REG_CC = compare (Reg, Num) +- if (REG_CC == 0) +- goto L1 +- +- REG_CC = compare (Reg, Num) +- if (REG_CC > 0) +- goto L2 +- +- The second comparison is superfluous and can be deleted. +- The second jump condition can be transformed from a +- "difficult" one to a "simple" one because "REG_CC > 0" and +- "REG_CC >= 0" will have the same effect here. +- +- This function relies on the way switch/case is being expaned +- as binary decision tree. For example code see PR 49903. +- +- Return TRUE if optimization performed. +- Return FALSE if nothing changed. +- +- INSN1 is a comparison, i.e. avr_compare_pattern != 0. +- +- We don't want to do this in text peephole because it is +- tedious to work out jump offsets there and the second comparison +- might have been transormed by `avr_reorg'. +- +- RTL peephole won't do because peephole2 does not scan across +- basic blocks. */ +- +-static bool +-avr_reorg_remove_redundant_compare (rtx_insn *insn1) +-{ +- rtx comp1, ifelse1, xcond1; +- rtx_insn *branch1; +- rtx comp2, ifelse2, xcond2; +- rtx_insn *branch2, *insn2; +- enum rtx_code code; +- rtx_insn *jump; +- rtx target, cond; +- +- /* Look out for: compare1 - branch1 - compare2 - branch2 */ +- +- branch1 = next_nonnote_nondebug_insn (insn1); +- if (!branch1 || !JUMP_P (branch1)) +- return false; +- +- insn2 = next_nonnote_nondebug_insn (branch1); +- if (!insn2 || !avr_compare_pattern (insn2)) +- return false; +- +- branch2 = next_nonnote_nondebug_insn (insn2); +- if (!branch2 || !JUMP_P (branch2)) +- return false; +- +- comp1 = avr_compare_pattern (insn1); +- comp2 = avr_compare_pattern (insn2); +- xcond1 = single_set (branch1); +- xcond2 = single_set (branch2); +- +- if (!comp1 || !comp2 +- || !rtx_equal_p (comp1, comp2) +- || !xcond1 || SET_DEST (xcond1) != pc_rtx +- || !xcond2 || SET_DEST (xcond2) != pc_rtx +- || IF_THEN_ELSE != GET_CODE (SET_SRC (xcond1)) +- || IF_THEN_ELSE != GET_CODE (SET_SRC (xcond2))) +- { +- return false; +- } +- +- comp1 = SET_SRC (comp1); +- ifelse1 = SET_SRC (xcond1); +- ifelse2 = SET_SRC (xcond2); +- +- /* comp is COMPARE now and ifelse is IF_THEN_ELSE. */ +- +- if (EQ != GET_CODE (XEXP (ifelse1, 0)) +- || !REG_P (XEXP (comp1, 0)) +- || !CONST_INT_P (XEXP (comp1, 1)) +- || XEXP (ifelse1, 2) != pc_rtx +- || XEXP (ifelse2, 2) != pc_rtx +- || LABEL_REF != GET_CODE (XEXP (ifelse1, 1)) +- || LABEL_REF != GET_CODE (XEXP (ifelse2, 1)) +- || !COMPARISON_P (XEXP (ifelse2, 0)) +- || REG_CC != REGNO (XEXP (XEXP (ifelse1, 0), 0)) +- || REG_CC != REGNO (XEXP (XEXP (ifelse2, 0), 0)) +- || const0_rtx != XEXP (XEXP (ifelse1, 0), 1) +- || const0_rtx != XEXP (XEXP (ifelse2, 0), 1)) +- { +- return false; +- } +- +- /* We filtered the insn sequence to look like +- +- (set (reg:CC cc) +- (compare (reg:M N) +- (const_int VAL))) +- (set (pc) +- (if_then_else (eq (reg:CC cc) +- (const_int 0)) +- (label_ref L1) +- (pc))) +- +- (set (reg:CC cc) +- (compare (reg:M N) +- (const_int VAL))) +- (set (pc) +- (if_then_else (CODE (reg:CC cc) +- (const_int 0)) +- (label_ref L2) +- (pc))) +- */ +- +- code = GET_CODE (XEXP (ifelse2, 0)); +- +- /* Map GT/GTU to GE/GEU which is easier for AVR. +- The first two instructions compare/branch on EQ +- so we may replace the difficult +- +- if (x == VAL) goto L1; +- if (x > VAL) goto L2; +- +- with easy +- +- if (x == VAL) goto L1; +- if (x >= VAL) goto L2; +- +- Similarly, replace LE/LEU by LT/LTU. */ +- +- switch (code) +- { +- case EQ: +- case LT: case LTU: +- case GE: case GEU: +- break; +- +- case LE: case LEU: +- case GT: case GTU: +- code = avr_normalize_condition (code); +- break; +- +- default: +- return false; +- } +- +- /* Wrap the branches into UNSPECs so they won't be changed or +- optimized in the remainder. */ +- +- target = XEXP (XEXP (ifelse1, 1), 0); +- cond = XEXP (ifelse1, 0); +- jump = emit_jump_insn_after (gen_branch_unspec (target, cond), insn1); +- +- JUMP_LABEL (jump) = JUMP_LABEL (branch1); +- +- target = XEXP (XEXP (ifelse2, 1), 0); +- cond = gen_rtx_fmt_ee (code, VOIDmode, cc_reg_rtx, const0_rtx); +- jump = emit_jump_insn_after (gen_branch_unspec (target, cond), insn2); +- +- JUMP_LABEL (jump) = JUMP_LABEL (branch2); +- +- /* The comparisons in insn1 and insn2 are exactly the same; +- insn2 is superfluous so delete it. */ +- +- delete_insn (insn2); +- delete_insn (branch1); +- delete_insn (branch2); +- +- return true; +-} +- +- +-/* Implement `TARGET_MACHINE_DEPENDENT_REORG'. */ +-/* Optimize conditional jumps. */ +- +-static void +-avr_reorg (void) +-{ +- rtx_insn *insn = get_insns(); +- +- for (insn = next_real_insn (insn); insn; insn = next_real_insn (insn)) +- { +- rtx pattern = avr_compare_pattern (insn); +- +- if (!pattern) +- continue; +- +- if (optimize +- && avr_reorg_remove_redundant_compare (insn)) +- { +- continue; +- } +- +- if (compare_diff_p (insn)) +- { +- /* Now we work under compare insn with difficult branch. */ +- +- rtx_insn *next = next_real_insn (insn); +- rtx pat = PATTERN (next); +- if (GET_CODE (pat) == PARALLEL) +- pat = XVECEXP (pat, 0, 0); +- +- pattern = SET_SRC (pattern); +- +- if (true_regnum (XEXP (pattern, 0)) >= 0 +- && true_regnum (XEXP (pattern, 1)) >= 0) +- { +- rtx x = XEXP (pattern, 0); +- rtx src = SET_SRC (pat); +- rtx t = XEXP (src, 0); +- PUT_CODE (t, swap_condition (GET_CODE (t))); +- XEXP (pattern, 0) = XEXP (pattern, 1); +- XEXP (pattern, 1) = x; +- INSN_CODE (next) = -1; +- } +- else if (true_regnum (XEXP (pattern, 0)) >= 0 +- && XEXP (pattern, 1) == const0_rtx) +- { +- /* This is a tst insn, we can reverse it. */ +- rtx src = SET_SRC (pat); +- rtx t = XEXP (src, 0); +- +- PUT_CODE (t, swap_condition (GET_CODE (t))); +- XEXP (pattern, 1) = XEXP (pattern, 0); +- XEXP (pattern, 0) = const0_rtx; +- INSN_CODE (next) = -1; +- INSN_CODE (insn) = -1; +- } +- else if (true_regnum (XEXP (pattern, 0)) >= 0 +- && CONST_INT_P (XEXP (pattern, 1))) +- { +- rtx x = XEXP (pattern, 1); +- rtx src = SET_SRC (pat); +- rtx t = XEXP (src, 0); +- machine_mode mode = GET_MODE (XEXP (pattern, 0)); +- +- if (avr_simplify_comparison_p (mode, GET_CODE (t), x)) +- { +- XEXP (pattern, 1) = gen_int_mode (INTVAL (x) + 1, mode); +- PUT_CODE (t, avr_normalize_condition (GET_CODE (t))); +- INSN_CODE (next) = -1; +- INSN_CODE (insn) = -1; +- } +- } +- } +- } +-} + + /* Returns register number for function return value.*/ + +@@ -14572,6 +15003,8 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code) + #undef TARGET_ASM_FINAL_POSTSCAN_INSN + #define TARGET_ASM_FINAL_POSTSCAN_INSN avr_asm_final_postscan_insn + ++#undef TARGET_INSN_COST ++#define TARGET_INSN_COST avr_insn_cost + #undef TARGET_REGISTER_MOVE_COST + #define TARGET_REGISTER_MOVE_COST avr_register_move_cost + #undef TARGET_MEMORY_MOVE_COST +@@ -14580,8 +15013,6 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code) + #define TARGET_RTX_COSTS avr_rtx_costs + #undef TARGET_ADDRESS_COST + #define TARGET_ADDRESS_COST avr_address_cost +-#undef TARGET_MACHINE_DEPENDENT_REORG +-#define TARGET_MACHINE_DEPENDENT_REORG avr_reorg + #undef TARGET_FUNCTION_ARG + #define TARGET_FUNCTION_ARG avr_function_arg + #undef TARGET_FUNCTION_ARG_ADVANCE +@@ -14711,6 +15142,12 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code) + #undef TARGET_MD_ASM_ADJUST + #define TARGET_MD_ASM_ADJUST avr_md_asm_adjust + ++#undef TARGET_CAN_INLINE_P ++#define TARGET_CAN_INLINE_P avr_can_inline_p ++ ++#undef TARGET_CANONICALIZE_COMPARISON ++#define TARGET_CANONICALIZE_COMPARISON avr_canonicalize_comparison ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + +diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md +index efae7efb69b..de029476908 100644 +--- a/gcc/config/avr/avr.md ++++ b/gcc/config/avr/avr.md +@@ -77,7 +77,6 @@ + UNSPEC_FMULS + UNSPEC_FMULSU + UNSPEC_COPYSIGN +- UNSPEC_IDENTITY + UNSPEC_INSERT_BITS + UNSPEC_ROUND + ]) +@@ -165,6 +164,7 @@ + ashlsi, ashrsi, lshrsi, + ashlpsi, ashrpsi, lshrpsi, + insert_bits, insv_notbit, insv_notbit_0, insv_notbit_7, ++ add_set_ZN, cmp_uext, cmp_sext, + no" + (const_string "no")) + +@@ -251,11 +251,23 @@ + (define_mode_iterator QIHI2 [QI HI]) + (define_mode_iterator QISI [QI HI PSI SI]) + (define_mode_iterator QIDI [QI HI PSI SI DI]) ++(define_mode_iterator QIPSI [QI HI PSI]) + (define_mode_iterator HISI [HI PSI SI]) + ++;; Ordered integral and fixed-point modes of specific sizes. + (define_mode_iterator ALL1 [QI QQ UQQ]) + (define_mode_iterator ALL2 [HI HQ UHQ HA UHA]) + (define_mode_iterator ALL4 [SI SQ USQ SA USA]) ++(define_mode_iterator ALL234 [HI SI PSI ++ HQ UHQ HA UHA ++ SQ USQ SA USA]) ++ ++;; Ordered signed integral and signed fixed-point modes of specific sizes. ++(define_mode_iterator ALLs1 [QI QQ]) ++(define_mode_iterator ALLs2 [HI HQ HA]) ++(define_mode_iterator ALLs4 [SI SQ SA]) ++(define_mode_iterator ALLs234 [HI SI PSI ++ HQ HA SQ SA]) + + ;; All supported move-modes + (define_mode_iterator MOVMODE [QI QQ UQQ +@@ -273,15 +285,17 @@ + SQ USQ SA USA]) + + ;; Define code iterators +-;; Define two incarnations so that we can build the cross product. ++;; Define two incarnations so that we can build the cartesian product. + (define_code_iterator any_extend [sign_extend zero_extend]) + (define_code_iterator any_extend2 [sign_extend zero_extend]) + (define_code_iterator any_extract [sign_extract zero_extract]) + (define_code_iterator any_shiftrt [lshiftrt ashiftrt]) + ++(define_code_iterator piaop [plus ior and]) + (define_code_iterator bitop [xor ior and]) + (define_code_iterator xior [xor ior]) + (define_code_iterator eqne [eq ne]) ++(define_code_iterator gelt [ge lt]) + + (define_code_iterator ss_addsub [ss_plus ss_minus]) + (define_code_iterator us_addsub [us_plus us_minus]) +@@ -309,6 +323,10 @@ + [(ss_minus "") (us_minus "") + (ss_plus "%") (us_plus "%")]) + ++(define_code_attr gelt_eqne ++ [(ge "eq") ++ (lt "ne")]) ++ + ;; Map RTX code to its standard insn name + (define_code_attr code_stdname + [(ashift "ashl") +@@ -1529,9 +1547,8 @@ + "#" + "&& reload_completed" + [(parallel [(set (match_dup 0) +- (plus:HI +- (zero_extend:HI (match_dup 1)) +- (zero_extend:HI (match_dup 2)))) ++ (plus:HI (zero_extend:HI (match_dup 1)) ++ (zero_extend:HI (match_dup 2)))) + (clobber (reg:CC REG_CC))])]) + + +@@ -2152,7 +2169,8 @@ + (define_expand "mulqi3_call" + [(set (reg:QI 24) (match_operand:QI 1 "register_operand" "")) + (set (reg:QI 22) (match_operand:QI 2 "register_operand" "")) +- (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) ++ (parallel [(set (reg:QI 24) ++ (mult:QI (reg:QI 24) (reg:QI 22))) + (clobber (reg:QI 22))]) + (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))] + "" +@@ -2166,12 +2184,14 @@ + "!AVR_HAVE_MUL" + "#" + "&& reload_completed" +- [(parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) ++ [(parallel [(set (reg:QI 24) ++ (mult:QI (reg:QI 24) (reg:QI 22))) + (clobber (reg:QI 22)) + (clobber (reg:CC REG_CC))])]) + + (define_insn "*mulqi3_call" +- [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22))) ++ [(set (reg:QI 24) ++ (mult:QI (reg:QI 24) (reg:QI 22))) + (clobber (reg:QI 22)) + (clobber (reg:CC REG_CC))] + "!AVR_HAVE_MUL && reload_completed" +@@ -2307,7 +2327,7 @@ + [(set (match_operand:PSI 0 "register_operand" "=r") + (plus:PSI (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "r") + (const_int 23)) +- (match_operand:PSI 2 "register_operand" "0"))) ++ (match_operand:PSI 2 "register_operand" "0"))) + (clobber (reg:CC REG_CC))] + "reload_completed" + "mov __tmp_reg__,%C1\;lsl __tmp_reg__ +@@ -2433,7 +2453,7 @@ + [(set (match_operand:HI 0 "register_operand" "=r") + (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a")) + (zero_extend:HI (match_operand:QI 2 "register_operand" "a")))) +- (clobber (reg:CC REG_CC))] ++ (clobber (reg:CC REG_CC))] + "AVR_HAVE_MUL && reload_completed" + "mulsu %1,%2 + movw %0,r0 +@@ -3088,7 +3108,7 @@ + [(parallel [(set (match_dup 0) + (mult:HI (zero_extend:HI (match_dup 1)) + (match_dup 2))) +- (clobber (reg:CC REG_CC))])]) ++ (clobber (reg:CC REG_CC))])]) + + (define_insn "*muluqihi3" + [(set (match_operand:HI 0 "register_operand" "=&r") +@@ -3706,17 +3726,17 @@ + ;; CSE has problems to operate on hard regs. + ;; + (define_insn_and_split "divmodqi4" +- [(set (match_operand:QI 0 "pseudo_register_operand" "") +- (div:QI (match_operand:QI 1 "pseudo_register_operand" "") +- (match_operand:QI 2 "pseudo_register_operand" ""))) +- (set (match_operand:QI 3 "pseudo_register_operand" "") ++ [(set (match_operand:QI 0 "pseudo_register_operand") ++ (div:QI (match_operand:QI 1 "pseudo_register_operand") ++ (match_operand:QI 2 "pseudo_register_operand"))) ++ (set (match_operand:QI 3 "pseudo_register_operand") + (mod:QI (match_dup 1) (match_dup 2))) + (clobber (reg:QI 22)) + (clobber (reg:QI 23)) + (clobber (reg:QI 24)) + (clobber (reg:QI 25))] + "" +- "this divmodqi4 pattern should have been splitted;" ++ { gcc_unreachable(); } + "" + [(set (reg:QI 24) (match_dup 1)) + (set (reg:QI 22) (match_dup 2)) +@@ -3752,17 +3772,17 @@ + [(set_attr "type" "xcall")]) + + (define_insn_and_split "udivmodqi4" +- [(set (match_operand:QI 0 "pseudo_register_operand" "") +- (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "") +- (match_operand:QI 2 "pseudo_register_operand" ""))) +- (set (match_operand:QI 3 "pseudo_register_operand" "") +- (umod:QI (match_dup 1) (match_dup 2))) +- (clobber (reg:QI 22)) +- (clobber (reg:QI 23)) +- (clobber (reg:QI 24)) +- (clobber (reg:QI 25))] +- "" +- "this udivmodqi4 pattern should have been splitted;" ++ [(set (match_operand:QI 0 "pseudo_register_operand") ++ (udiv:QI (match_operand:QI 1 "pseudo_register_operand") ++ (match_operand:QI 2 "pseudo_register_operand"))) ++ (set (match_operand:QI 3 "pseudo_register_operand") ++ (umod:QI (match_dup 1) (match_dup 2))) ++ (clobber (reg:QI 22)) ++ (clobber (reg:QI 23)) ++ (clobber (reg:QI 24)) ++ (clobber (reg:QI 25))] ++ "" ++ { gcc_unreachable(); } + "" + [(set (reg:QI 24) (match_dup 1)) + (set (reg:QI 22) (match_dup 2)) +@@ -3794,17 +3814,17 @@ + [(set_attr "type" "xcall")]) + + (define_insn_and_split "divmodhi4" +- [(set (match_operand:HI 0 "pseudo_register_operand" "") +- (div:HI (match_operand:HI 1 "pseudo_register_operand" "") +- (match_operand:HI 2 "pseudo_register_operand" ""))) +- (set (match_operand:HI 3 "pseudo_register_operand" "") ++ [(set (match_operand:HI 0 "pseudo_register_operand") ++ (div:HI (match_operand:HI 1 "pseudo_register_operand") ++ (match_operand:HI 2 "pseudo_register_operand"))) ++ (set (match_operand:HI 3 "pseudo_register_operand") + (mod:HI (match_dup 1) (match_dup 2))) + (clobber (reg:QI 21)) + (clobber (reg:HI 22)) + (clobber (reg:HI 24)) + (clobber (reg:HI 26))] + "" +- "this should have been splitted;" ++ { gcc_unreachable(); } + "" + [(set (reg:HI 24) (match_dup 1)) + (set (reg:HI 22) (match_dup 2)) +@@ -3840,17 +3860,17 @@ + [(set_attr "type" "xcall")]) + + (define_insn_and_split "udivmodhi4" +- [(set (match_operand:HI 0 "pseudo_register_operand" "") +- (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "") +- (match_operand:HI 2 "pseudo_register_operand" ""))) +- (set (match_operand:HI 3 "pseudo_register_operand" "") ++ [(set (match_operand:HI 0 "pseudo_register_operand") ++ (udiv:HI (match_operand:HI 1 "pseudo_register_operand") ++ (match_operand:HI 2 "pseudo_register_operand"))) ++ (set (match_operand:HI 3 "pseudo_register_operand") + (umod:HI (match_dup 1) (match_dup 2))) + (clobber (reg:QI 21)) + (clobber (reg:HI 22)) + (clobber (reg:HI 24)) + (clobber (reg:HI 26))] + "" +- "this udivmodhi4 pattern should have been splitted.;" ++ { gcc_unreachable(); } + "" + [(set (reg:HI 24) (match_dup 1)) + (set (reg:HI 22) (match_dup 2)) +@@ -3925,7 +3945,7 @@ + [(parallel [(set (match_dup 0) + (mult:PSI (zero_extend:PSI (match_dup 1)) + (zero_extend:PSI (match_dup 2)))) +- (clobber (reg:CC REG_CC))])]) ++ (clobber (reg:CC REG_CC))])]) + + (define_insn "*umulqihipsi3" + [(set (match_operand:PSI 0 "register_operand" "=&r") +@@ -4091,14 +4111,14 @@ + ;; implementation works the other way round. + + (define_insn_and_split "divmodpsi4" +- [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "") +- (div:PSI (match_operand:PSI 1 "pseudo_register_operand" "") +- (match_operand:PSI 2 "pseudo_register_operand" ""))) +- (set (match_operand:PSI 3 "pseudo_register_operand" "") +- (mod:PSI (match_dup 1) +- (match_dup 2))) +- (clobber (reg:DI 18)) +- (clobber (reg:QI 26))])] ++ [(set (match_operand:PSI 0 "pseudo_register_operand") ++ (div:PSI (match_operand:PSI 1 "pseudo_register_operand") ++ (match_operand:PSI 2 "pseudo_register_operand"))) ++ (set (match_operand:PSI 3 "pseudo_register_operand") ++ (mod:PSI (match_dup 1) ++ (match_dup 2))) ++ (clobber (reg:DI 18)) ++ (clobber (reg:QI 26))] + "" + { gcc_unreachable(); } + "" +@@ -4140,14 +4160,14 @@ + [(set_attr "type" "xcall")]) + + (define_insn_and_split "udivmodpsi4" +- [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "") +- (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand" "") +- (match_operand:PSI 2 "pseudo_register_operand" ""))) +- (set (match_operand:PSI 3 "pseudo_register_operand" "") +- (umod:PSI (match_dup 1) +- (match_dup 2))) +- (clobber (reg:DI 18)) +- (clobber (reg:QI 26))])] ++ [(set (match_operand:PSI 0 "pseudo_register_operand") ++ (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand") ++ (match_operand:PSI 2 "pseudo_register_operand"))) ++ (set (match_operand:PSI 3 "pseudo_register_operand") ++ (umod:PSI (match_dup 1) ++ (match_dup 2))) ++ (clobber (reg:DI 18)) ++ (clobber (reg:QI 26))] + "" + { gcc_unreachable(); } + "" +@@ -4191,17 +4211,18 @@ + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + (define_insn_and_split "divmodsi4" +- [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "") +- (div:SI (match_operand:SI 1 "pseudo_register_operand" "") +- (match_operand:SI 2 "pseudo_register_operand" ""))) +- (set (match_operand:SI 3 "pseudo_register_operand" "") +- (mod:SI (match_dup 1) (match_dup 2))) +- (clobber (reg:SI 18)) +- (clobber (reg:SI 22)) +- (clobber (reg:HI 26)) +- (clobber (reg:HI 30))])] ++ [(set (match_operand:SI 0 "pseudo_register_operand") ++ (div:SI (match_operand:SI 1 "pseudo_register_operand") ++ (match_operand:SI 2 "pseudo_register_operand"))) ++ (set (match_operand:SI 3 "pseudo_register_operand") ++ (mod:SI (match_dup 1) ++ (match_dup 2))) ++ (clobber (reg:SI 18)) ++ (clobber (reg:SI 22)) ++ (clobber (reg:HI 26)) ++ (clobber (reg:HI 30))] + "" +- "this divmodsi4 pattern should have been splitted;" ++ { gcc_unreachable(); } + "" + [(set (reg:SI 22) (match_dup 1)) + (set (reg:SI 18) (match_dup 2)) +@@ -4237,17 +4258,18 @@ + [(set_attr "type" "xcall")]) + + (define_insn_and_split "udivmodsi4" +- [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "") +- (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "") +- (match_operand:SI 2 "pseudo_register_operand" ""))) +- (set (match_operand:SI 3 "pseudo_register_operand" "") +- (umod:SI (match_dup 1) (match_dup 2))) +- (clobber (reg:SI 18)) +- (clobber (reg:SI 22)) +- (clobber (reg:HI 26)) +- (clobber (reg:HI 30))])] ++ [(set (match_operand:SI 0 "pseudo_register_operand") ++ (udiv:SI (match_operand:SI 1 "pseudo_register_operand") ++ (match_operand:SI 2 "pseudo_register_operand"))) ++ (set (match_operand:SI 3 "pseudo_register_operand") ++ (umod:SI (match_dup 1) ++ (match_dup 2))) ++ (clobber (reg:SI 18)) ++ (clobber (reg:SI 22)) ++ (clobber (reg:HI 26)) ++ (clobber (reg:HI 30))] + "" +- "this udivmodsi4 pattern should have been splitted;" ++ { gcc_unreachable(); } + "" + [(set (reg:SI 22) (match_dup 1)) + (set (reg:SI 18) (match_dup 2)) +@@ -4712,7 +4734,8 @@ + [(parallel [(set (match_operand:HISI 0 "register_operand") + (bitop:HISI (match_dup 0) + (match_operand:HISI 1 "register_operand"))) +- (clobber (scratch:QI))])] ++ (clobber (scratch:QI)) ++ (clobber (reg:CC REG_CC))])] + "optimize + && reload_completed" + [(const_int 1)] +@@ -4726,6 +4749,43 @@ + DONE; + }) + ++;; If $0 = $0 const requires a QI scratch, and d-reg $1 dies after ++;; the first insn, then we can replace ++;; $0 = $1 ++;; $0 = $0 const ++;; by ++;; $1 = $1 const ++;; $0 = $1 ++;; This transorms constraint alternative "r,0,n,&d" of the first operation ++;; to alternative "d,0,n,X". ++;; "*addhi3_clobber" "*addpsi3" "*addsi3" ++;; "*addhq3" "*adduhq3" "*addha3" "*adduha3" ++;; "*addsq3" "*addusq3" "*addsa3" "*addusa3" ++;; "*iorhi3" "*iorpsi3" "*iorsi3" ++;; "*andhi3" "*andpsi3" "*andsi3" ++(define_peephole2 ++ [(parallel [(set (match_operand:ORDERED234 0 "register_operand") ++ (match_operand:ORDERED234 1 "d_register_operand")) ++ (clobber (reg:CC REG_CC))]) ++ (parallel [(set (match_dup 0) ++ (piaop:ORDERED234 (match_dup 0) ++ (match_operand:ORDERED234 2 "const_operand"))) ++ ; A d-reg as scratch tells that this insn is expensive, and ++ ; that $0 is not a d-register: l-reg or something like SI:14 etc. ++ (clobber (match_operand:QI 3 "d_register_operand")) ++ (clobber (reg:CC REG_CC))])] ++ "peep2_reg_dead_p (1, operands[1])" ++ [(parallel [(set (match_dup 1) ++ (piaop:ORDERED234 (match_dup 1) ++ (match_dup 2))) ++ (clobber (scratch:QI)) ++ (clobber (reg:CC REG_CC))]) ++ ; Unfortunately, the following insn misses a REG_DEAD note for $1, ++ ; so this peep2 works only once. ++ (parallel [(set (match_dup 0) ++ (match_dup 1)) ++ (clobber (reg:CC REG_CC))])]) ++ + + ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap + ;; swap +@@ -5684,7 +5744,7 @@ + ;; "lshrha3" "lshruha3" + (define_insn_and_split "lshr3" + [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r") +- (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0") ++ (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0") + (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))] + "" + "#" +@@ -5696,7 +5756,7 @@ + + (define_insn "*lshr3" + [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r") +- (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0") ++ (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0") + (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm"))) + (clobber (reg:CC REG_CC))] + "reload_completed" +@@ -6449,80 +6509,41 @@ + ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=> + ;; compare + +-; Optimize negated tests into reverse compare if overflow is undefined. +-(define_insn "*negated_tstqi" ++;; "*swapped_tstqi" "*swapped_tstqq" ++(define_insn "*swapped_tst" + [(set (reg:CC REG_CC) +- (compare:CC (neg:QI (match_operand:QI 0 "register_operand" "r")) +- (const_int 0)))] +- "reload_completed && !flag_wrapv && !flag_trapv" +- "cp __zero_reg__,%0" +- [(set_attr "length" "1")]) +- +-(define_insn "*reversed_tstqi" +- [(set (reg:CC REG_CC) +- (compare:CC (const_int 0) +- (match_operand:QI 0 "register_operand" "r")))] ++ (compare:CC (match_operand:ALLs1 0 "const0_operand" "Y00") ++ (match_operand:ALLs1 1 "register_operand" "r")))] + "reload_completed" +- "cp __zero_reg__,%0" +-[(set_attr "length" "2")]) ++ "cp __zero_reg__,%1" ++[(set_attr "length" "1")]) + +-(define_insn "*negated_tsthi" +- [(set (reg:CC REG_CC) +- (compare:CC (neg:HI (match_operand:HI 0 "register_operand" "r")) +- (const_int 0)))] +- "reload_completed && !flag_wrapv && !flag_trapv" +- "cp __zero_reg__,%A0 +- cpc __zero_reg__,%B0" +-[(set_attr "length" "2")]) +- +-;; Leave here the clobber used by the cmphi pattern for simplicity, even +-;; though it is unused, because this pattern is synthesized by avr_reorg. +-(define_insn "*reversed_tsthi" ++ ++;; "*swapped_tsthi" "*swapped_tsthq" "*swapped_tstha" ++(define_insn "*swapped_tst" + [(set (reg:CC REG_CC) +- (compare:CC (const_int 0) +- (match_operand:HI 0 "register_operand" "r"))) +- (clobber (match_scratch:QI 1 "=X"))] ++ (compare:CC (match_operand:ALLs2 0 "const0_operand" "Y00") ++ (match_operand:ALLs2 1 "register_operand" "r")))] + "reload_completed" +- "cp __zero_reg__,%A0 +- cpc __zero_reg__,%B0" +-[(set_attr "length" "2")]) ++ "cp __zero_reg__,%A1 ++ cpc __zero_reg__,%B1" ++ [(set_attr "length" "2")]) + +-(define_insn "*negated_tstpsi" +- [(set (reg:CC REG_CC) +- (compare:CC (neg:PSI (match_operand:PSI 0 "register_operand" "r")) +- (const_int 0)))] +- "reload_completed && !flag_wrapv && !flag_trapv" +- "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0" +- [(set_attr "length" "3")]) + +-(define_insn "*reversed_tstpsi" ++(define_insn "*swapped_tstpsi" + [(set (reg:CC REG_CC) + (compare:CC (const_int 0) +- (match_operand:PSI 0 "register_operand" "r"))) +- (clobber (match_scratch:QI 1 "=X"))] ++ (match_operand:PSI 0 "register_operand" "r")))] + "reload_completed" + "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0" + [(set_attr "length" "3")]) + +-(define_insn "*negated_tstsi" +- [(set (reg:CC REG_CC) +- (compare:CC (neg:SI (match_operand:SI 0 "register_operand" "r")) +- (const_int 0)))] +- "reload_completed && !flag_wrapv && !flag_trapv" +- "cp __zero_reg__,%A0 +- cpc __zero_reg__,%B0 +- cpc __zero_reg__,%C0 +- cpc __zero_reg__,%D0" +- [(set_attr "length" "4")]) + +-;; "*reversed_tstsi" +-;; "*reversed_tstsq" "*reversed_tstusq" +-;; "*reversed_tstsa" "*reversed_tstusa" +-(define_insn "*reversed_tst" ++;; "*swapped_tstsi" "*swapped_tstsq" "*swapped_tstsa" ++(define_insn "*swapped_tst" + [(set (reg:CC REG_CC) +- (compare:CC (match_operand:ALL4 0 "const0_operand" "Y00") +- (match_operand:ALL4 1 "register_operand" "r"))) +- (clobber (match_scratch:QI 2 "=X"))] ++ (compare:CC (match_operand:ALLs4 0 "const0_operand" "Y00") ++ (match_operand:ALLs4 1 "register_operand" "r")))] + "reload_completed" + "cp __zero_reg__,%A1 + cpc __zero_reg__,%B1 +@@ -6536,38 +6557,40 @@ + (define_insn "cmp3" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:ALL1 0 "register_operand" "r ,r,d") +- (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))] ++ (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))] + "reload_completed" + "@ +- tst %0 ++ cp %0, __zero_reg__ + cp %0,%1 + cpi %0,lo8(%1)" + [(set_attr "length" "1,1,1")]) + +-(define_insn "*cmpqi_sign_extend" +- [(set (reg:CC REG_CC) +- (compare:CC (sign_extend:HI (match_operand:QI 0 "register_operand" "d")) +- (match_operand:HI 1 "s8_operand" "n")))] +- "reload_completed" +- "cpi %0,lo8(%1)" +- [(set_attr "length" "1")]) + +- +-(define_insn "*cmphi.zero-extend.0" ++;; May be generated by "*cbranch..0/1". ++(define_insn "*cmp..0" + [(set (reg:CC REG_CC) +- (compare:CC (zero_extend:HI (match_operand:QI 0 "register_operand" "r")) +- (match_operand:HI 1 "register_operand" "r")))] +- "reload_completed" +- "cp %0,%A1\;cpc __zero_reg__,%B1" +- [(set_attr "length" "2")]) ++ (compare:CC (any_extend:HISI (match_operand:QIPSI 0 "register_operand" "r")) ++ (match_operand:HISI 1 "register_operand" "r")))] ++ "reload_completed ++ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" ++ { ++ return avr_out_cmp_ext (operands, , nullptr); ++ } ++ [(set_attr "adjust_len" "cmp_ext")]) + +-(define_insn "*cmphi.zero-extend.1" ++;; Swapped version of the above. ++;; May be generated by "*cbranch..0/1". ++(define_insn "*cmp..1" + [(set (reg:CC REG_CC) +- (compare:CC (match_operand:HI 0 "register_operand" "r") +- (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))))] +- "reload_completed" +- "cp %A0,%1\;cpc %B0,__zero_reg__" +- [(set_attr "length" "2")]) ++ (compare:CC (match_operand:HISI 0 "register_operand" "r") ++ (any_extend:HISI (match_operand:QIPSI 1 "register_operand" "r"))))] ++ "reload_completed ++ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" ++ { ++ return avr_out_cmp_ext (operands, , nullptr); ++ } ++ [(set_attr "adjust_len" "cmp_ext")]) ++ + + ;; "cmphi3" + ;; "cmphq3" "cmpuhq3" +@@ -6575,8 +6598,8 @@ + (define_insn "cmp3" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:ALL2 0 "register_operand" "!w ,r ,r,d ,r ,d,r") +- (match_operand:ALL2 1 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn"))) +- (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d ,X,&d"))] ++ (match_operand:ALL2 1 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn"))) ++ (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d ,X,&d"))] + "reload_completed" + { + switch (which_alternative) +@@ -6603,14 +6626,14 @@ + + return avr_out_compare (insn, operands, NULL); + } +- [(set_attr "length" "1,2,2,3,4,2,4") ++ [(set_attr "length" "2,2,2,3,4,2,4") + (set_attr "adjust_len" "tsthi,tsthi,*,*,*,compare,compare")]) + + (define_insn "*cmppsi" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:PSI 0 "register_operand" "r,r,d ,r ,d,r") +- (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s ,M,n"))) +- (clobber (match_scratch:QI 2 "=X,X,&d,&d ,X,&d"))] ++ (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s ,M,n"))) ++ (clobber (match_scratch:QI 2 "=X,X,&d,&d ,X,&d"))] + "reload_completed" + { + switch (which_alternative) +@@ -6641,8 +6664,8 @@ + (define_insn "*cmp" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:ALL4 0 "register_operand" "r ,r ,d,r ,r") +- (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn"))) +- (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d"))] ++ (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn"))) ++ (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d"))] + "reload_completed" + { + if (0 == which_alternative) +@@ -6656,6 +6679,13 @@ + (set_attr "adjust_len" "tstsi,*,compare,compare,compare")]) + + ++;; A helper for avr_pass_ifelse::avr_rest_of_handle_ifelse(). ++(define_expand "gen_compare" ++ [(parallel [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:HISI 0 "register_operand") ++ (match_operand:HISI 1 "const_int_operand"))) ++ (clobber (match_operand:QI 2 "scratch_operand"))])]) ++ + ;; ---------------------------------------------------------------------- + ;; JUMP INSTRUCTIONS + ;; ---------------------------------------------------------------------- +@@ -6664,53 +6694,67 @@ + (define_expand "cbranch4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL1 1 "register_operand" "") +- (match_operand:ALL1 2 "nonmemory_operand" "")]) +- (label_ref (match_operand 3 "" "")) +- (pc)))]) ++ [(match_operand:ALL1 1 "register_operand") ++ (match_operand:ALL1 2 "nonmemory_operand")]) ++ (label_ref (match_operand 3)) ++ (pc)))] ++ "" ++ { ++ int icode = (int) GET_CODE (operands[0]); ++ ++ targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false); ++ PUT_CODE (operands[0], (enum rtx_code) icode); ++ }) + + (define_expand "cbranch4" + [(parallel + [(set (pc) +- (if_then_else +- (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ORDERED234 1 "register_operand" "") +- (match_operand:ORDERED234 2 "nonmemory_operand" "")]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:QI 4 ""))])]) +- +-;; "*cbranchqi4" +-;; "*cbranchqq4" "*cbranchuqq4" +-(define_insn_and_split "*cbranch4" ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:ALL234 1 "register_operand") ++ (match_operand:ALL234 2 "nonmemory_operand")]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber (match_scratch:QI 4))])] ++ "" ++ { ++ int icode = (int) GET_CODE (operands[0]); ++ ++ targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false); ++ PUT_CODE (operands[0], (enum rtx_code) icode); ++ }) ++ ++ ++;; "cbranchqi4_insn" ++;; "cbranchqq4_insn" "cbranchuqq4_insn" ++(define_insn_and_split "cbranch4_insn" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL1 1 "register_operand" "r ,r,d") ++ [(match_operand:ALL1 1 "register_operand" "r ,r,d") + (match_operand:ALL1 2 "nonmemory_operand" "Y00,r,i")]) +- (label_ref (match_operand 3 "" "")) +- (pc)))] ++ (label_ref (match_operand 3)) ++ (pc)))] + "" + "#" + "reload_completed" + [(set (reg:CC REG_CC) +- (compare:CC (match_dup 1) (match_dup 2))) ++ (compare:CC (match_dup 1) (match_dup 2))) + (set (pc) + (if_then_else (match_op_dup 0 + [(reg:CC REG_CC) (const_int 0)]) + (label_ref (match_dup 3)) +- (pc)))] +- "") ++ (pc)))]) + +-;; "*cbranchsi4" "*cbranchsq4" "*cbranchusq4" "*cbranchsa4" "*cbranchusa4" +-(define_insn_and_split "*cbranch4" ++;; "cbranchsi4_insn" ++;; "cbranchsq4_insn" "cbranchusq4_insn" "cbranchsa4_insn" "cbranchusa4_insn" ++(define_insn_and_split "cbranch4_insn" + [(set (pc) +- (if_then_else +- (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL4 1 "register_operand" "r ,r ,d,r ,r") +- (match_operand:ALL4 2 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d"))] ++ (if_then_else ++ (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:ALL4 1 "register_operand" "r ,r,d,r ,r") ++ (match_operand:ALL4 2 "nonmemory_operand" "Y00,r,M,M ,n Ynn")]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber (match_scratch:QI 4 "=X ,X,X,&d,&d"))] + "" + "#" + "reload_completed" +@@ -6721,19 +6765,18 @@ + (if_then_else (match_op_dup 0 + [(reg:CC REG_CC) (const_int 0)]) + (label_ref (match_dup 3)) +- (pc)))] +- "") ++ (pc)))]) + +-;; "*cbranchpsi4" +-(define_insn_and_split "*cbranchpsi4" ++;; "cbranchpsi4_insn" ++(define_insn_and_split "cbranchpsi4_insn" + [(set (pc) +- (if_then_else +- (match_operator 0 "ordered_comparison_operator" +- [(match_operand:PSI 1 "register_operand" "r,r,d ,r ,d,r") +- (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s ,M,n")]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:QI 4 "=X,X,&d,&d ,X,&d"))] ++ (if_then_else ++ (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:PSI 1 "register_operand" "r,r,d ,r ,d,r") ++ (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s ,M,n")]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber (match_scratch:QI 4 "=X,X,&d,&d,X,&d"))] + "" + "#" + "reload_completed" +@@ -6744,19 +6787,19 @@ + (if_then_else (match_op_dup 0 + [(reg:CC REG_CC) (const_int 0)]) + (label_ref (match_dup 3)) +- (pc)))] +- "") ++ (pc)))]) + +-;; "*cbranchhi4" "*cbranchhq4" "*cbranchuhq4" "*cbranchha4" "*cbranchuha4" +-(define_insn_and_split "*cbranch4" ++;; "cbranchhi4_insn" ++;; "cbranchhq4_insn" "cbranchuhq4_insn" "cbranchha4_insn" "cbranchuha4_insn" ++(define_insn_and_split "cbranch4_insn" + [(set (pc) +- (if_then_else +- (match_operator 0 "ordered_comparison_operator" +- [(match_operand:ALL2 1 "register_operand" "!w ,r ,r,d ,r ,d,r") +- (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d ,X,&d"))] ++ (if_then_else ++ (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:ALL2 1 "register_operand" "!w ,r ,r,d ,r ,d,r") ++ (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d,X,&d"))] + "" + "#" + "reload_completed" +@@ -6767,8 +6810,71 @@ + (if_then_else (match_op_dup 0 + [(reg:CC REG_CC) (const_int 0)]) + (label_ref (match_dup 3)) +- (pc)))] +- "") ++ (pc)))]) ++ ++;; Combiner pattern to compare sign- or zero-extended register against ++;; a wider register, like comparing uint8_t against uint16_t. ++(define_insn_and_split "*cbranch..0" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(any_extend:HISI (match_operand:QIPSI 1 "register_operand" "r")) ++ (match_operand:HISI 2 "register_operand" "r")]) ++ (label_ref (match_operand 3)) ++ (pc)))] ++ "optimize ++ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" ++ "#" ++ "&& reload_completed" ++ [; "*cmp..0" ++ (set (reg:CC REG_CC) ++ (compare:CC (match_dup 1) ++ (match_dup 2))) ++ ; "branch" ++ (set (pc) ++ (if_then_else (match_op_dup 0 [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_dup 3)) ++ (pc)))] ++ { ++ operands[1] = gen_rtx_ (mode, operands[1]); ++ if (difficult_comparison_operator (operands[0], VOIDmode)) ++ { ++ PUT_CODE (operands[0], swap_condition (GET_CODE (operands[0]))); ++ std::swap (operands[1], operands[2]); ++ } ++ }) ++ ++;; Same combiner pattern, but with swapped operands. ++(define_insn_and_split "*cbranch..0" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:HISI 1 "register_operand" "r") ++ (any_extend:HISI (match_operand:QIPSI 2 "register_operand" "r"))]) ++ (label_ref (match_operand 3)) ++ (pc)))] ++ "optimize ++ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" ++ "#" ++ "&& reload_completed" ++ [; "*cmp..0" ++ (set (reg:CC REG_CC) ++ (compare:CC (match_dup 1) ++ (match_dup 2))) ++ ; "branch" ++ (set (pc) ++ (if_then_else (match_op_dup 0 [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_dup 3)) ++ (pc)))] ++ { ++ operands[2] = gen_rtx_ (mode, operands[2]); ++ if (difficult_comparison_operator (operands[0], VOIDmode)) ++ { ++ PUT_CODE (operands[0], swap_condition (GET_CODE (operands[0]))); ++ std::swap (operands[1], operands[2]); ++ } ++ }) ++ + + ;; Test a single bit in a QI/HI/SImode register. + ;; Combine will create zero extract patterns for single bit tests. +@@ -6842,14 +6948,11 @@ + "#" + "&& reload_completed" + [(parallel [(set (pc) +- (if_then_else +- (match_op_dup 0 +- [(and:QISI +- (match_dup 1) +- (match_dup 2)) +- (const_int 0)]) +- (label_ref (match_dup 3)) +- (pc))) ++ (if_then_else (match_op_dup 0 [(and:QISI (match_dup 1) ++ (match_dup 2)) ++ (const_int 0)]) ++ (label_ref (match_dup 3)) ++ (pc))) + (clobber (reg:CC REG_CC))])]) + + (define_insn "*sbrx_and_branch" +@@ -6878,163 +6981,77 @@ + (const_int 2) + (const_int 4))))]) + +-;; Convert sign tests to bit 7/15/31 tests that match the above insns. +-(define_peephole2 +- [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "") +- (const_int 0))) +- (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0) +- (const_int 1) +- (const_int 7)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) + +-(define_peephole2 +- [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "") +- (const_int 0))) +- (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0) +- (const_int 1) +- (const_int 7)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_peephole2 +- [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "") +- (const_int 0))) +- (clobber (match_operand:HI 2 ""))]) +- (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_peephole2 +- [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "") +- (const_int 0))) +- (clobber (match_operand:HI 2 ""))]) +- (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) ++;; Convert sign tests to bit 7 tests that match the above insns. ++(define_peephole2 ; "*sbrx_branch" ++ [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:ALLs1 0 "register_operand") ++ (match_operand:ALLs1 1 "const0_operand"))) ++ (set (pc) ++ (if_then_else (gelt (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (2, REG_CC)" ++ [(parallel [(set (pc) ++ (if_then_else ( (zero_extract:HI (match_dup 0) ++ (const_int 1) ++ (match_dup 1)) ++ (const_int 0)) ++ (label_ref (match_dup 2)) ++ (pc))) + (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) ++ { ++ operands[0] = avr_to_int_mode (operands[0]); ++ operands[1] = GEN_INT (GET_MODE_BITSIZE (mode) - 1); ++ }) + +-(define_peephole2 +- [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "") +- (const_int 0))) +- (clobber (match_operand:SI 2 ""))]) +- (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) ++;; Convert sign tests to bit 15/23/31 tests that match the above insns. ++(define_peephole2 ; "*sbrx_branch" ++ [(parallel [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:ALLs234 0 "register_operand") ++ (match_operand:ALLs234 1 "const0_operand"))) ++ (clobber (match_operand:QI 3 "scratch_operand"))]) ++ (set (pc) ++ (if_then_else (gelt (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (2, REG_CC)" ++ [(parallel [(set (pc) ++ (if_then_else ( (zero_extract:HI (match_dup 0) ++ (const_int 1) ++ (match_dup 1)) ++ (const_int 0)) ++ (label_ref (match_dup 2)) ++ (pc))) + (clobber (reg:CC REG_CC))])] +- "operands[2] = gen_int_mode (-2147483647 - 1, SImode);") ++ { ++ operands[0] = avr_to_int_mode (operands[0]); ++ operands[1] = GEN_INT (GET_MODE_BITSIZE (mode) - 1); ++ }) + +-(define_peephole2 +- [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "") +- (const_int 0))) +- (clobber (match_operand:SI 2 ""))]) +- (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" +- [(parallel [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2)) +- (const_int 0)) +- (label_ref (match_dup 1)) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "operands[2] = gen_int_mode (-2147483647 - 1, SImode);") + + ;; ************************************************************************ + ;; Implementation of conditional jumps here. + ;; Compare with 0 (test) jumps + ;; ************************************************************************ + +-(define_insn_and_split "branch" ++(define_insn "branch" + [(set (pc) + (if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_operand 0 "" "")) ++ [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_operand 0)) + (pc)))] + "reload_completed" +- "#" +- "&& reload_completed" +- [(parallel [(set (pc) +- (if_then_else (match_op_dup 1 +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_dup 0)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_insn "*branch" +- [(set (pc) +- (if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_operand 0 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))] +- "reload_completed" +- { +- return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0); +- } +- [(set_attr "type" "branch")]) +- +- +-;; Same as above but wrap SET_SRC so that this branch won't be transformed +-;; or optimized in the remainder. +- +-(define_insn "branch_unspec" +- [(set (pc) +- (unspec [(if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_operand 0 "" "")) +- (pc)) +- ] UNSPEC_IDENTITY)) +- (clobber (reg:CC REG_CC))] +- "reload_completed" + { + return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0); + } + [(set_attr "type" "branch")]) + +-;; **************************************************************** +-;; AVR does not have following conditional jumps: LE,LEU,GT,GTU. +-;; Convert them all to proper jumps. +-;; ****************************************************************/ + +-(define_insn_and_split "difficult_branch" ++(define_insn "difficult_branch" + [(set (pc) + (if_then_else (match_operator 1 "difficult_comparison_operator" + [(reg:CC REG_CC) +@@ -7042,95 +7059,11 @@ + (label_ref (match_operand 0 "" "")) + (pc)))] + "reload_completed" +- "#" +- "&& reload_completed" +- [(parallel [(set (pc) +- (if_then_else (match_op_dup 1 +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_dup 0)) +- (pc))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_insn "*difficult_branch" +- [(set (pc) +- (if_then_else (match_operator 1 "difficult_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (label_ref (match_operand 0 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))] +- "reload_completed" + { + return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0); + } + [(set_attr "type" "branch1")]) + +-;; revers branch +- +-(define_insn_and_split "rvbranch" +- [(set (pc) +- (if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_operand 0 "" ""))))] +- "reload_completed" +- "#" +- "&& reload_completed" +- [(parallel [(set (pc) +- (if_then_else (match_op_dup 1 +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_dup 0)))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_insn "*rvbranch" +- [(set (pc) +- (if_then_else (match_operator 1 "simple_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_operand 0 "" "")))) +- (clobber (reg:CC REG_CC))] +- "reload_completed" +- { +- return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1); +- } +- [(set_attr "type" "branch1")]) +- +-(define_insn_and_split "difficult_rvbranch" +- [(set (pc) +- (if_then_else (match_operator 1 "difficult_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_operand 0 "" ""))))] +- "reload_completed" +- "#" +- "&& reload_completed" +- [(parallel [(set (pc) +- (if_then_else (match_op_dup 1 +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_dup 0)))) +- (clobber (reg:CC REG_CC))])]) +- +-(define_insn "*difficult_rvbranch" +- [(set (pc) +- (if_then_else (match_operator 1 "difficult_comparison_operator" +- [(reg:CC REG_CC) +- (const_int 0)]) +- (pc) +- (label_ref (match_operand 0 "" "")))) +- (clobber (reg:CC REG_CC))] +- "reload_completed" +- { +- return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1); +- } +- [(set_attr "type" "branch")]) + + ;; ************************************************************************** + ;; Unconditional and other jump instructions. +@@ -7656,15 +7589,14 @@ + (clobber (reg:CC REG_CC))]) + (parallel [(set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) +- (clobber (match_operand:QI 1 "d_register_operand" ""))]) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (const_int -1))) ++ (clobber (match_operand:QI 1 "scratch_or_d_register_operand"))]) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7700,15 +7632,14 @@ + (clobber (reg:CC REG_CC))]) + (parallel [(set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) ++ (const_int -1))) + (clobber (match_operand:QI 1 "d_register_operand" ""))]) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7742,15 +7673,14 @@ + (clobber (reg:CC REG_CC))]) + (parallel [(set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) +- (clobber (match_operand:QI 1 "d_register_operand" ""))]) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (const_int -1))) ++ (clobber (match_operand:QI 1 "scratch_or_d_register_operand"))]) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7784,15 +7714,14 @@ + (clobber (reg:CC REG_CC))]) + (parallel [(set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) ++ (const_int -1))) + (clobber (match_operand:QI 1 "d_register_operand" ""))]) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7822,14 +7751,13 @@ + (clobber (reg:CC REG_CC))]) + (set (reg:CC REG_CC) + (compare:CC (match_dup 0) +- (const_int -1))) +- (parallel [(set (pc) +- (if_then_else (eqne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 1 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "" ++ (const_int -1))) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 1)) ++ (pc)))] ++ "dead_or_set_regno_p (insn, REG_CC)" + { + const char *op; + int jump_mode; +@@ -7855,14 +7783,14 @@ + (define_peephole ; "*cpse.eq" + [(set (reg:CC REG_CC) + (compare:CC (match_operand:ALL1 1 "register_operand" "r,r") +- (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00"))) +- (parallel [(set (pc) +- (if_then_else (eq (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 0 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "jump_over_one_insn_p (insn, operands[0])" ++ (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00"))) ++ (set (pc) ++ (if_then_else (eq (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 0)) ++ (pc)))] ++ "jump_over_one_insn_p (insn, operands[0]) ++ && dead_or_set_regno_p (insn, REG_CC)" + "@ + cpse %1,%2 + cpse %1,__zero_reg__") +@@ -7890,16 +7818,16 @@ + + (define_peephole ; "*cpse.ne" + [(set (reg:CC REG_CC) +- (compare:CC (match_operand:ALL1 1 "register_operand" "") +- (match_operand:ALL1 2 "reg_or_0_operand" ""))) +- (parallel [(set (pc) +- (if_then_else (ne (reg:CC REG_CC) +- (const_int 0)) +- (label_ref (match_operand 0 "" "")) +- (pc))) +- (clobber (reg:CC REG_CC))])] +- "!AVR_HAVE_JMP_CALL +- || !TARGET_SKIP_BUG" ++ (compare:CC (match_operand:ALL1 1 "register_operand") ++ (match_operand:ALL1 2 "reg_or_0_operand"))) ++ (set (pc) ++ (if_then_else (ne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 0)) ++ (pc)))] ++ "(!AVR_HAVE_JMP_CALL ++ || !TARGET_SKIP_BUG) ++ && dead_or_set_regno_p (insn, REG_CC)" + { + if (operands[2] == CONST0_RTX (mode)) + operands[2] = zero_reg_rtx; +@@ -8094,7 +8022,7 @@ + (const_int 1)] + UNSPECV_DELAY_CYCLES) + (set (match_dup 1) +- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) ++ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (clobber (match_dup 2)) + (clobber (reg:CC REG_CC))])]) + +@@ -8126,7 +8054,7 @@ + (const_int 2)] + UNSPECV_DELAY_CYCLES) + (set (match_dup 1) +- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) ++ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (clobber (match_dup 2)) + (clobber (reg:CC REG_CC))])] + "" +@@ -8163,7 +8091,7 @@ + (const_int 3)] + UNSPECV_DELAY_CYCLES) + (set (match_dup 1) +- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) ++ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_dup 4)) +@@ -8206,7 +8134,7 @@ + (const_int 4)] + UNSPECV_DELAY_CYCLES) + (set (match_dup 1) +- (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) ++ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_dup 4)) +@@ -9095,16 +9023,20 @@ + "bst %3,0\;bld %0,%4" + [(set_attr "length" "2")]) + +-;; Move bit $3.0 into bit $0.0. +-;; For bit 0, combiner generates slightly different pattern. +-(define_insn "*movbitqi.0" +- [(set (match_operand:QI 0 "register_operand" "=r") +- (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0") +- (match_operand:QI 2 "single_zero_operand" "n")) +- (and:QI (match_operand:QI 3 "register_operand" "r") +- (const_int 1))))] +- "0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))" +- "bst %3,0\;bld %0,0" ++;; Move bit $3.x into bit $0.x. ++(define_insn "*movbit.0-6" ++ [(set (match_operand:QISI 0 "register_operand" "=r") ++ (ior:QISI (and:QISI (match_operand:QISI 1 "register_operand" "0") ++ (match_operand:QISI 2 "single_zero_operand" "n")) ++ (and:QISI (match_operand:QISI 3 "register_operand" "r") ++ (match_operand:QISI 4 "single_one_operand" "n"))))] ++ "GET_MODE_MASK(mode) ++ == (GET_MODE_MASK(mode) & (INTVAL(operands[2]) ^ INTVAL(operands[4])))" ++ { ++ auto bitmask = GET_MODE_MASK (mode) & UINTVAL (operands[4]); ++ operands[4] = GEN_INT (exact_log2 (bitmask)); ++ return "bst %T3%T4" CR_TAB "bld %T0%T4"; ++ } + [(set_attr "length" "2")]) + + ;; Move bit $2.0 into bit $0.7. +@@ -9489,6 +9421,258 @@ + (clobber (reg:CC REG_CC))])]) + + ++;; Try optimize decrement-and-branch. When we have an addition followed ++;; by a comparison of the result against zero, we can output the addition ++;; in such a way that SREG.N and SREG.Z are set according to the result. ++ ++;; { -1, +1 } for QImode, otherwise the empty set. ++(define_mode_attr p1m1 [(QI "N P") ++ (HI "Yxx") (PSI "Yxx") (SI "Yxx")]) ++ ++;; FIXME: reload1.cc::do_output_reload() does not support output reloads ++;; for JUMP_INSNs, hence letting combine doing decrement-and-branch like ++;; the following might run into ICE. Doing reloads by hand is too painful... ++; ++; (define_insn_and_split "*add.for.eqne..cbranch" ++; [(set (pc) ++; (if_then_else (eqne (match_operand:QISI 1 "register_operand" "0") ++; (match_operand:QISI 2 "const_int_operand" "n")) ++; (label_ref (match_operand 4)) ++; (pc))) ++; (set (match_operand:QISI 0 "register_operand" "=r") ++; (plus:QISI (match_dup 1) ++; (match_operand:QISI 3 "const_int_operand" "n")))] ++; ;; No clobber for now as combine might not have one handy. ++; ;; We pop a scatch in split1. ++; "!reload_completed ++; && const0_rtx == simplify_binary_operation (PLUS, mode, ++; operands[2], operands[3])" ++; { gcc_unreachable(); } ++; "&& 1" ++; [(parallel [(set (pc) ++; (if_then_else (eqne (match_dup 1) ++; (match_dup 2)) ++; (label_ref (match_dup 4)) ++; (pc))) ++; (set (match_dup 0) ++; (plus:QISI (match_dup 1) ++; (match_dup 3))) ++; (clobber (scratch:QI))])]) ++; ++;; ...Hence, stick with RTL peepholes for now. Unfortunately, there is no ++;; canonical form, and if reload shuffles registers around, we might miss ++;; opportunities to match a decrement-and-branch. ++;; doloop_end doesn't reload either, so doloop_end also won't work. ++ ++(define_expand "gen_add_for__" ++ ; "*add.for.eqne." ++ [(parallel [(set (reg:CC REG_CC) ++ (compare:CC (plus:QISI (match_operand:QISI 0 "register_operand") ++ (match_operand:QISI 1 "const_int_operand")) ++ (const_int 0))) ++ (set (match_dup 0) ++ (plus:QISI (match_dup 0) ++ (match_dup 1))) ++ (clobber (match_operand:QI 3))]) ++ ; "branch" ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_dup 2)) ++ (pc)))]) ++ ++ ++;; 1/3: A version without clobber: d-reg or 8-bit adds +/-1. ++(define_peephole2 ++ [(parallel [(set (match_operand:QISI 0 "register_operand") ++ (plus:QISI (match_dup 0) ++ (match_operand:QISI 1 "const_int_operand"))) ++ (clobber (reg:CC REG_CC))]) ++ (set (reg:CC REG_CC) ++ (compare:CC (match_dup 0) ++ (const_int 0))) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (3, REG_CC) ++ && (d_register_operand (operands[0], mode) ++ || (mode == QImode ++ && (INTVAL (operands[1]) == 1 ++ || INTVAL (operands[1]) == -1)))" ++ [(scratch)] ++ { ++ emit (gen_gen_add_for__ (operands[0], operands[1], operands[2], ++ gen_rtx_SCRATCH (QImode))); ++ DONE; ++ }) ++ ++;; 2/3: A version with clobber from the insn. ++(define_peephole2 ++ [(parallel [(set (match_operand:QISI 0 "register_operand") ++ (plus:QISI (match_dup 0) ++ (match_operand:QISI 1 "const_int_operand"))) ++ (clobber (match_operand:QI 3 "scratch_or_d_register_operand")) ++ (clobber (reg:CC REG_CC))]) ++ (parallel [(set (reg:CC REG_CC) ++ (compare:CC (match_dup 0) ++ (const_int 0))) ++ (clobber (match_operand:QI 4 "scratch_or_d_register_operand"))]) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (3, REG_CC)" ++ [(scratch)] ++ { ++ rtx scratch = REG_P (operands[3]) ? operands[3] : operands[4]; ++ ++ // We need either a d-register or a scratch register to clobber. ++ if (! REG_P (scratch) ++ && ! d_register_operand (operands[0], mode) ++ && ! (QImode == mode ++ && (INTVAL (operands[1]) == 1 ++ || INTVAL (operands[1]) == -1))) ++ { ++ FAIL; ++ } ++ emit (gen_gen_add_for__ (operands[0], operands[1], operands[2], ++ scratch)); ++ DONE; ++ }) ++ ++;; 3/3 A version with a clobber from peephole2. ++(define_peephole2 ++ [(match_scratch:QI 3 "d") ++ (parallel [(set (match_operand:QISI 0 "register_operand") ++ (plus:QISI (match_dup 0) ++ (match_operand:QISI 1 "const_int_operand"))) ++ (clobber (reg:CC REG_CC))]) ++ (set (reg:CC REG_CC) ++ (compare:CC (match_dup 0) ++ (const_int 0))) ++ (set (pc) ++ (if_then_else (eqne (reg:CC REG_CC) ++ (const_int 0)) ++ (label_ref (match_operand 2)) ++ (pc)))] ++ "peep2_regno_dead_p (3, REG_CC)" ++ [(scratch)] ++ { ++ emit (gen_gen_add_for__ (operands[0], operands[1], operands[2], ++ operands[3])); ++ DONE; ++ }) ++ ++;; Result of the above three peepholes is an addition that also ++;; performs an EQ or NE comparison (of the result) against zero. ++;; FIXME: Using (match_dup 0) instead of operands[3/4] makes rnregs ++;; barf in regrename.cc::merge_overlapping_regs(). For now, use the ++;; fix from PR50788: Constrain as "0". ++(define_insn "*add.for.eqne." ++ [(set (reg:CC REG_CC) ++ (compare:CC ++ (plus:QISI (match_operand:QISI 3 "register_operand" "0,0 ,0") ++ (match_operand:QISI 1 "const_int_operand" "n,,n")) ++ (const_int 0))) ++ (set (match_operand:QISI 0 "register_operand" "=d,*r ,r") ++ (plus:QISI (match_operand:QISI 4 "register_operand" "0,0 ,0") ++ (match_dup 1))) ++ (clobber (match_scratch:QI 2 "=X,X ,&d"))] ++ "reload_completed" ++ { ++ return avr_out_plus_set_ZN (operands, nullptr); ++ } ++ [(set_attr "adjust_len" "add_set_ZN")]) ++ ++ ++;; Swapping both comparison and branch condition. This can turn difficult ++;; branches to easy ones. And in some cases, a comparison against one can ++;; be turned into a comparison against zero. ++ ++(define_peephole2 ; "*swapped_tst" ++ [(parallel [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:ALLs234 1 "register_operand") ++ (match_operand:ALLs234 2 "const_operand"))) ++ (clobber (match_operand:QI 3 "scratch_operand"))]) ++ (set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_operand 4)) ++ (pc)))] ++ "peep2_regno_dead_p (2, REG_CC)" ++ [(set (reg:CC REG_CC) ++ (compare:CC (match_dup 2) ++ (match_dup 1))) ++ ; "branch" ++ (set (pc) ++ (if_then_else (match_op_dup 0 [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_dup 4)) ++ (pc)))] ++ { ++ rtx xval = avr_to_int_mode (operands[2]); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT && xval == const0_rtx) ++ code = LT; ++ else if (code == GE && xval == const1_rtx) ++ code = LT; ++ else if (code == LE && xval == const0_rtx) ++ code = GE; ++ else if (code == LT && xval == const1_rtx) ++ code = GE; ++ else ++ FAIL; ++ ++ operands[2] = CONST0_RTX (mode); ++ PUT_CODE (operands[0], code); ++ }) ++ ++;; Same, but for 8-bit modes which have no scratch reg. ++(define_peephole2 ; "*swapped_tst" ++ [(set (reg:CC REG_CC) ++ (compare:CC (match_operand:ALLs1 1 "register_operand") ++ (match_operand:ALLs1 2 "const_operand"))) ++ (set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_operand 4)) ++ (pc)))] ++ "peep2_regno_dead_p (2, REG_CC)" ++ [(set (reg:CC REG_CC) ++ (compare:CC (match_dup 2) ++ (match_dup 1))) ++ ; "branch" ++ (set (pc) ++ (if_then_else (match_op_dup 0 [(reg:CC REG_CC) ++ (const_int 0)]) ++ (label_ref (match_dup 4)) ++ (pc)))] ++ { ++ rtx xval = avr_to_int_mode (operands[2]); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT && xval == const0_rtx) ++ code = LT; ++ else if (code == GE && xval == const1_rtx) ++ code = LT; ++ else if (code == LE && xval == const0_rtx) ++ code = GE; ++ else if (code == LT && xval == const1_rtx) ++ code = GE; ++ else ++ FAIL; ++ ++ operands[2] = CONST0_RTX (mode); ++ PUT_CODE (operands[0], code); ++ }) ++ ++ + (define_expand "extzv" + [(set (match_operand:QI 0 "register_operand" "") + (zero_extract:QI (match_operand:QI 1 "register_operand" "") +diff --git a/gcc/config/avr/constraints.md b/gcc/config/avr/constraints.md +index 57397d1469b..3ce2108d6ce 100644 +--- a/gcc/config/avr/constraints.md ++++ b/gcc/config/avr/constraints.md +@@ -245,6 +245,11 @@ + (match_test "INTVAL (avr_to_int_mode (op)) == -2")) + (match_test "satisfies_constraint_Cm2 (op)"))) + ++;; Constraint that's the empty set. Useful with mode and code iterators. ++(define_constraint "Yxx" ++ "A constraints that is always false" ++ (match_test "false")) ++ + (define_constraint "Yx2" + "Fixed-point or integer constant not in the range @minus{}2 @dots{} 2" + (and (ior (match_code "const_int") +diff --git a/gcc/config/avr/predicates.md b/gcc/config/avr/predicates.md +index c7f417d405c..1d63f7ee67c 100644 +--- a/gcc/config/avr/predicates.md ++++ b/gcc/config/avr/predicates.md +@@ -27,6 +27,11 @@ + (and (match_code "reg") + (match_test "REGNO (op) >= 16 && REGNO (op) <= 31"))) + ++(define_predicate "scratch_or_d_register_operand" ++ (ior (match_operand 0 "d_register_operand") ++ (and (match_code ("scratch")) ++ (match_operand 0 "scratch_operand")))) ++ + (define_predicate "even_register_operand" + (and (match_code "reg") + (and (match_test "REGNO (op) <= 31") +diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h +index d06eda369cf..5412c5d4479 100644 +--- a/gcc/config/i386/cygwin.h ++++ b/gcc/config/i386/cygwin.h +@@ -57,7 +57,7 @@ along with GCC; see the file COPYING3. If not see + + #undef ENDFILE_SPEC + #define ENDFILE_SPEC \ +- "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}\ ++ "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \ + %{!shared:%:if-exists(default-manifest.o%s)}\ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end.o%s; \ +diff --git a/gcc/config/i386/darwin.h b/gcc/config/i386/darwin.h +index a55f6b2b874..2f773924d6e 100644 +--- a/gcc/config/i386/darwin.h ++++ b/gcc/config/i386/darwin.h +@@ -109,8 +109,8 @@ along with GCC; see the file COPYING3. If not see + "%{!force_cpusubtype_ALL:-force_cpusubtype_ALL} " + + #undef ENDFILE_SPEC +-#define ENDFILE_SPEC \ +- "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \ ++#define ENDFILE_SPEC ++\ "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \ + %{mpc32:crtprec32.o%s} \ + %{mpc64:crtprec64.o%s} \ + %{mpc80:crtprec80.o%s}" TM_DESTRUCTOR +diff --git a/gcc/config/i386/gnu-user-common.h b/gcc/config/i386/gnu-user-common.h +index 23b54c5be52..3d2a33f1714 100644 +--- a/gcc/config/i386/gnu-user-common.h ++++ b/gcc/config/i386/gnu-user-common.h +@@ -47,7 +47,7 @@ along with GCC; see the file COPYING3. If not see + + /* Similar to standard GNU userspace, but adding -ffast-math support. */ + #define GNU_USER_TARGET_MATHFILE_SPEC \ +- "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \ ++ "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \ + %{mpc32:crtprec32.o%s} \ + %{mpc64:crtprec64.o%s} \ + %{mpc80:crtprec80.o%s}" +diff --git a/gcc/config/i386/i386-builtins.cc b/gcc/config/i386/i386-builtins.cc +index 050c6228a18..8ed32e14f0a 100644 +--- a/gcc/config/i386/i386-builtins.cc ++++ b/gcc/config/i386/i386-builtins.cc +@@ -1790,7 +1790,7 @@ ix86_vectorize_builtin_gather (const_tree mem_vectype, + ? !TARGET_USE_GATHER_2PARTS + : (known_eq (TYPE_VECTOR_SUBPARTS (mem_vectype), 4u) + ? !TARGET_USE_GATHER_4PARTS +- : !TARGET_USE_GATHER))) ++ : !TARGET_USE_GATHER_8PARTS))) + return NULL_TREE; + + if ((TREE_CODE (index_type) != INTEGER_TYPE +diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc +index 6fe41c3c24f..6a2444eb6b6 100644 +--- a/gcc/config/i386/i386-features.cc ++++ b/gcc/config/i386/i386-features.cc +@@ -1875,8 +1875,7 @@ public: + /* opt_pass methods: */ + virtual bool gate (function *) + { +- return TARGET_AVX && TARGET_VZEROUPPER +- && flag_expensive_optimizations && !optimize_size; ++ return TARGET_AVX && TARGET_VZEROUPPER; + } + + virtual unsigned int execute (function *) +diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc +index 099cec4b610..318f6c61455 100644 +--- a/gcc/config/i386/i386-options.cc ++++ b/gcc/config/i386/i386-options.cc +@@ -137,6 +137,11 @@ along with GCC; see the file COPYING3. If not see + #define m_GOLDMONT_PLUS (HOST_WIDE_INT_1U<x_ix86_tune_string + = ggc_strdup (option_strings[IX86_FUNCTION_SPECIFIC_TUNE]); +- else if (orig_tune_defaulted) ++ /* If we have explicit arch string and no tune string specified, set ++ tune_string to NULL and later it will be overriden by arch_string ++ so target clones can get proper optimization. */ ++ else if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH] ++ || orig_tune_defaulted) + opts->x_ix86_tune_string = NULL; + + /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */ +@@ -1696,20 +1705,46 @@ parse_mtune_ctrl_str (struct gcc_options *opts, bool dump) + curr_feature_string++; + clear = true; + } +- for (i = 0; i < X86_TUNE_LAST; i++) +- { +- if (!strcmp (curr_feature_string, ix86_tune_feature_names[i])) +- { +- ix86_tune_features[i] = !clear; +- if (dump) +- fprintf (stderr, "Explicitly %s feature %s\n", +- clear ? "clear" : "set", ix86_tune_feature_names[i]); +- break; +- } +- } +- if (i == X86_TUNE_LAST) +- error ("unknown parameter to option %<-mtune-ctrl%>: %s", +- clear ? curr_feature_string - 1 : curr_feature_string); ++ ++ if (!strcmp (curr_feature_string, "use_gather")) ++ { ++ ix86_tune_features[X86_TUNE_USE_GATHER_2PARTS] = !clear; ++ ix86_tune_features[X86_TUNE_USE_GATHER_4PARTS] = !clear; ++ ix86_tune_features[X86_TUNE_USE_GATHER_8PARTS] = !clear; ++ if (dump) ++ fprintf (stderr, "Explicitly %s features use_gather_2parts," ++ " use_gather_4parts, use_gather_8parts\n", ++ clear ? "clear" : "set"); ++ ++ } ++ else if (!strcmp (curr_feature_string, "use_scatter")) ++ { ++ ix86_tune_features[X86_TUNE_USE_SCATTER_2PARTS] = !clear; ++ ix86_tune_features[X86_TUNE_USE_SCATTER_4PARTS] = !clear; ++ ix86_tune_features[X86_TUNE_USE_SCATTER_8PARTS] = !clear; ++ if (dump) ++ fprintf (stderr, "Explicitly %s features use_scatter_2parts," ++ " use_scatter_4parts, use_scatter_8parts\n", ++ clear ? "clear" : "set"); ++ } ++ else ++ { ++ for (i = 0; i < X86_TUNE_LAST; i++) ++ { ++ if (!strcmp (curr_feature_string, ix86_tune_feature_names[i])) ++ { ++ ix86_tune_features[i] = !clear; ++ if (dump) ++ fprintf (stderr, "Explicitly %s feature %s\n", ++ clear ? "clear" : "set", ix86_tune_feature_names[i]); ++ break; ++ } ++ } ++ ++ if (i == X86_TUNE_LAST) ++ error ("unknown parameter to option %<-mtune-ctrl%>: %s", ++ clear ? curr_feature_string - 1 : curr_feature_string); ++ } + curr_feature_string = next_feature_string; + } + while (curr_feature_string); +@@ -2676,7 +2711,9 @@ ix86_option_override_internal (bool main_args_p, + sorry ("%<-mcall-ms2sysv-xlogues%> isn%'t currently supported with SEH"); + + if (!(opts_set->x_target_flags & MASK_VZEROUPPER) +- && TARGET_EMIT_VZEROUPPER) ++ && TARGET_EMIT_VZEROUPPER ++ && flag_expensive_optimizations ++ && !optimize_size) + opts->x_target_flags |= MASK_VZEROUPPER; + if (!(opts_set->x_target_flags & MASK_STV)) + opts->x_target_flags |= MASK_STV; +diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc +index 9a9ff3b34b8..6b6142f4aa0 100644 +--- a/gcc/config/i386/i386.cc ++++ b/gcc/config/i386/i386.cc +@@ -8268,10 +8268,11 @@ ix86_elim_entry_set_got (rtx reg) + rtx pat = PATTERN (c_insn); + if (GET_CODE (pat) == PARALLEL) + { +- rtx vec = XVECEXP (pat, 0, 0); +- if (GET_CODE (vec) == SET +- && XINT (XEXP (vec, 1), 1) == UNSPEC_SET_GOT +- && REGNO (XEXP (vec, 0)) == REGNO (reg)) ++ rtx set = XVECEXP (pat, 0, 0); ++ if (GET_CODE (set) == SET ++ && GET_CODE (SET_SRC (set)) == UNSPEC ++ && XINT (SET_SRC (set), 1) == UNSPEC_SET_GOT ++ && REGNO (SET_DEST (set)) == REGNO (reg)) + delete_insn (c_insn); + } + } +@@ -12238,8 +12239,8 @@ output_pic_addr_const (FILE *file, rtx x, int code) + assemble_name (asm_out_file, buf); + break; + +- case CONST_INT: +- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); ++ CASE_CONST_SCALAR_INT: ++ output_addr_const (file, x); + break; + + case CONST: +@@ -14416,8 +14417,12 @@ ix86_avx_u128_mode_needed (rtx_insn *insn) + modes wider than 256 bits. It's only safe to issue a + vzeroupper if all SSE registers are clobbered. */ + const function_abi &abi = insn_callee_abi (insn); +- if (!hard_reg_set_subset_p (reg_class_contents[SSE_REGS], +- abi.mode_clobbers (V4DImode))) ++ /* Should be safe to issue an vzeroupper before sibling_call_p. ++ Also there not mode_exit for sibling_call, so there could be ++ missing vzeroupper for that. */ ++ if (!(SIBLING_CALL_P (insn) ++ || hard_reg_set_subset_p (reg_class_contents[SSE_REGS], ++ abi.mode_clobbers (V4DImode)))) + return AVX_U128_ANY; + + return AVX_U128_CLEAN; +@@ -14555,7 +14560,19 @@ ix86_avx_u128_mode_after (int mode, rtx_insn *insn) + bool avx_upper_reg_found = false; + note_stores (insn, ix86_check_avx_upper_stores, &avx_upper_reg_found); + +- return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN; ++ if (avx_upper_reg_found) ++ return AVX_U128_DIRTY; ++ ++ /* If the function desn't clobber any sse registers or only clobber ++ 128-bit part, Then vzeroupper isn't issued before the function exit. ++ the status not CLEAN but ANY after the function. */ ++ const function_abi &abi = insn_callee_abi (insn); ++ if (!(SIBLING_CALL_P (insn) ++ || hard_reg_set_subset_p (reg_class_contents[SSE_REGS], ++ abi.mode_clobbers (V4DImode)))) ++ return AVX_U128_ANY; ++ ++ return AVX_U128_CLEAN; + } + + /* Otherwise, return current mode. Remember that if insn +@@ -18396,8 +18413,10 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) + tree itype = GET_MODE_INNER (TYPE_MODE (type)) == E_SFmode + ? intSI_type_node : intDI_type_node; + type = get_same_sized_vectype (itype, type); +- arg2 = gimple_build (&stmts, VIEW_CONVERT_EXPR, type, arg2); + } ++ else ++ type = signed_type_for (type); ++ arg2 = gimple_build (&stmts, VIEW_CONVERT_EXPR, type, arg2); + tree zero_vec = build_zero_cst (type); + tree cmp_type = truth_type_for (type); + tree cmp = gimple_build (&stmts, LT_EXPR, cmp_type, arg2, zero_vec); +@@ -18935,7 +18954,7 @@ ix86_vectorize_builtin_scatter (const_tree vectype, + ? !TARGET_USE_SCATTER_2PARTS + : (known_eq (TYPE_VECTOR_SUBPARTS (vectype), 4u) + ? !TARGET_USE_SCATTER_4PARTS +- : !TARGET_USE_SCATTER)) ++ : !TARGET_USE_SCATTER_8PARTS)) + return NULL_TREE; + + if ((TREE_CODE (index_type) != INTEGER_TYPE +diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h +index fce0b3564a8..5cea7157a1c 100644 +--- a/gcc/config/i386/i386.h ++++ b/gcc/config/i386/i386.h +@@ -398,10 +398,10 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; + ix86_tune_features[X86_TUNE_USE_GATHER_4PARTS] + #define TARGET_USE_SCATTER_4PARTS \ + ix86_tune_features[X86_TUNE_USE_SCATTER_4PARTS] +-#define TARGET_USE_GATHER \ +- ix86_tune_features[X86_TUNE_USE_GATHER] +-#define TARGET_USE_SCATTER \ +- ix86_tune_features[X86_TUNE_USE_SCATTER] ++#define TARGET_USE_GATHER_8PARTS \ ++ ix86_tune_features[X86_TUNE_USE_GATHER_8PARTS] ++#define TARGET_USE_SCATTER_8PARTS \ ++ ix86_tune_features[X86_TUNE_USE_SCATTER_8PARTS] + #define TARGET_FUSE_CMP_AND_BRANCH_32 \ + ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] + #define TARGET_FUSE_CMP_AND_BRANCH_64 \ +diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md +index be07be10d8a..a3fea6ba41e 100644 +--- a/gcc/config/i386/i386.md ++++ b/gcc/config/i386/i386.md +@@ -2398,7 +2398,10 @@ + (clobber (reg:CC FLAGS_REG))])] + { + int shift = ctz_hwi (UINTVAL (operands[1])); +- operands[1] = gen_int_mode (UINTVAL (operands[1]) >> shift, DImode); ++ rtx op1 = gen_int_mode (UINTVAL (operands[1]) >> shift, DImode); ++ if (ix86_endbr_immediate_operand (op1, VOIDmode)) ++ FAIL; ++ operands[1] = op1; + operands[2] = gen_int_mode (shift, QImode); + }) + +@@ -3582,9 +3585,9 @@ + ;; Possible store forwarding (partial memory) stall in alternatives 4, 6 and 7. + (define_insn "*movdf_internal" + [(set (match_operand:DF 0 "nonimmediate_operand" +- "=Yf*f,m ,Yf*f,?r ,!o,?*r ,!o,!o,?r,?m,?r,?r,v,v,v,m,*x,*x,*x,m ,r ,v,r ,o ,r ,m") ++ "=Yf*f,m ,Yf*f,?r ,!o,?*r ,!o,!o,?r,?m,?r,?r,v,v,v,m,*x,*x,*x,m ,?r,?v,r ,o ,r ,m") + (match_operand:DF 1 "general_operand" +- "Yf*fm,Yf*f,G ,roF,r ,*roF,*r,F ,rm,rC,C ,F ,C,v,m,v,C ,*x,m ,*x,v,r ,roF,rF,rmF,rC"))] ++ "Yf*fm,Yf*f,G ,roF,r ,*roF,*r,F ,rm,rC,C ,F ,C,v,m,v,C ,*x,m ,*x, v, r,roF,rF,rmF,rC"))] + "!(MEM_P (operands[0]) && MEM_P (operands[1])) + && (lra_in_progress || reload_completed + || !CONST_DOUBLE_P (operands[1]) +@@ -14160,7 +14163,8 @@ + (const_int 1) + (and:SI + (match_operand:SI 2 "register_operand") +- (match_operand 3 "const_int_operand")))]) ++ (match_operand 3 "const_int_operand"))) ++ (const_int 0)]) + (label_ref (match_operand 4)) + (pc))) + (clobber (reg:CC FLAGS_REG))] +@@ -17066,8 +17070,10 @@ + "! TARGET_POPCNT" + { + rtx scratch = gen_reg_rtx (QImode); ++ rtx tmp = gen_reg_rtx (HImode); + +- emit_insn (gen_parityhi2_cmp (operands[1])); ++ emit_move_insn (tmp, operands[1]); ++ emit_insn (gen_parityhi2_cmp (tmp)); + + ix86_expand_setcc (scratch, ORDERED, + gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx); +diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt +index a3675e515bc..ed31cab0a46 100644 +--- a/gcc/config/i386/i386.opt ++++ b/gcc/config/i386/i386.opt +@@ -420,6 +420,10 @@ mpc80 + Target RejectNegative + Set 80387 floating-point precision to 80-bit. + ++mdaz-ftz ++Target ++Set the FTZ and DAZ Flags. ++ + mpreferred-stack-boundary= + Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) + Attempt to keep stack aligned to this power of 2. +@@ -1214,3 +1218,11 @@ Do not use GOT to access external symbols. + -param=x86-stlf-window-ninsns= + Target Joined UInteger Var(x86_stlf_window_ninsns) Init(64) Param + Instructions number above which STFL stall penalty can be compensated. ++ ++mgather ++Target Alias(mtune-ctrl=, use_gather, ^use_gather) ++Enable vectorization for gather instruction. ++ ++mscatter ++Target Alias(mtune-ctrl=, use_scatter, ^use_scatter) ++Enable vectorization for scatter instruction. +diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h +index d3ca0cd0279..ddbe6a4054b 100644 +--- a/gcc/config/i386/mingw32.h ++++ b/gcc/config/i386/mingw32.h +@@ -197,7 +197,7 @@ along with GCC; see the file COPYING3. If not see + + #undef ENDFILE_SPEC + #define ENDFILE_SPEC \ +- "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \ ++ "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \ + %{!shared:%:if-exists(default-manifest.o%s)}\ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end.o%s; \ +diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md +index 197f19e4b1a..2ca01c144d5 100644 +--- a/gcc/config/i386/mmx.md ++++ b/gcc/config/i386/mmx.md +@@ -1211,7 +1211,10 @@ + (match_operand:V2SF 1 "register_operand") 0) + (match_dup 2)))] + "TARGET_MMX_WITH_SSE" +- "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1);") ++{ ++ operands[1] = force_reg (V2SFmode, operands[1]); ++ operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1); ++}) + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ;; +diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md +index eb767e56ca4..924effce2b5 100644 +--- a/gcc/config/i386/sse.md ++++ b/gcc/config/i386/sse.md +@@ -1411,12 +1411,12 @@ + }) + + (define_insn "*_load_mask" +- [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") +- (vec_merge:VI12_AVX512VL +- (unspec:VI12_AVX512VL +- [(match_operand:VI12_AVX512VL 1 "memory_operand" "m")] ++ [(set (match_operand:VI12HF_AVX512VL 0 "register_operand" "=v") ++ (vec_merge:VI12HF_AVX512VL ++ (unspec:VI12HF_AVX512VL ++ [(match_operand:VI12HF_AVX512VL 1 "memory_operand" "m")] + UNSPEC_MASKLOAD) +- (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C") ++ (match_operand:VI12HF_AVX512VL 2 "nonimm_or_0_operand" "0C") + (match_operand: 3 "register_operand" "Yk")))] + "TARGET_AVX512BW" + "vmovdqu\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" +@@ -1425,9 +1425,9 @@ + (set_attr "mode" "")]) + + (define_insn_and_split "*_load" +- [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") +- (unspec:VI12_AVX512VL +- [(match_operand:VI12_AVX512VL 1 "memory_operand" "m")] ++ [(set (match_operand:VI12HF_AVX512VL 0 "register_operand" "=v") ++ (unspec:VI12HF_AVX512VL ++ [(match_operand:VI12HF_AVX512VL 1 "memory_operand" "m")] + UNSPEC_MASKLOAD))] + "TARGET_AVX512BW" + "#" +@@ -1554,7 +1554,7 @@ + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +-(define_insn "_store_mask" ++(define_insn "*_store_mask" + [(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m") + (vec_merge:V48_AVX512VL + (match_operand:V48_AVX512VL 1 "register_operand" "v") +@@ -1582,7 +1582,7 @@ + (set_attr "memory" "store") + (set_attr "mode" "")]) + +-(define_insn "_store_mask" ++(define_insn "*_store_mask" + [(set (match_operand:VI12HF_AVX512VL 0 "memory_operand" "=m") + (vec_merge:VI12HF_AVX512VL + (match_operand:VI12HF_AVX512VL 1 "register_operand" "v") +@@ -4848,7 +4848,10 @@ + (match_operand:VF1_AVX2 1 "register_operand") 0) + (match_dup 2)))] + "TARGET_SSE2" +- "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (mode)-1);") ++{ ++ operands[1] = force_reg (mode, operands[1]); ++ operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (mode)-1); ++}) + + ;; Also define scalar versions. These are used for abs, neg, and + ;; conditional move. Using subregs into vector modes causes register +@@ -6318,6 +6321,14 @@ + [(UNSPEC_COMPLEX_FMA_PAIR "fmaddc") + (UNSPEC_COMPLEX_FCMA_PAIR "fcmaddc")]) + ++(define_int_attr int_comm ++ [(UNSPEC_COMPLEX_FMA "") ++ (UNSPEC_COMPLEX_FMA_PAIR "") ++ (UNSPEC_COMPLEX_FCMA "") ++ (UNSPEC_COMPLEX_FCMA_PAIR "") ++ (UNSPEC_COMPLEX_FMUL "%") ++ (UNSPEC_COMPLEX_FCMUL "")]) ++ + (define_int_attr conj_op + [(UNSPEC_COMPLEX_FMA "") + (UNSPEC_COMPLEX_FCMA "_conj") +@@ -6431,7 +6442,7 @@ + (define_insn "fma__" + [(set (match_operand:VF_AVX512FP16VL 0 "register_operand" "=&v") + (unspec:VF_AVX512FP16VL +- [(match_operand:VF_AVX512FP16VL 1 "" "%v") ++ [(match_operand:VF_AVX512FP16VL 1 "" "v") + (match_operand:VF_AVX512FP16VL 2 "" "") + (match_operand:VF_AVX512FP16VL 3 "" "0")] + UNSPEC_COMPLEX_F_C_MA))] +@@ -6495,7 +6506,7 @@ + (define_insn "fma___pair" + [(set (match_operand:VF1_AVX512VL 0 "register_operand" "=&v") + (unspec:VF1_AVX512VL +- [(match_operand:VF1_AVX512VL 1 "vector_operand" "%v") ++ [(match_operand:VF1_AVX512VL 1 "vector_operand" "v") + (match_operand:VF1_AVX512VL 2 "bcst_vector_operand" "vmBr") + (match_operand:VF1_AVX512VL 3 "vector_operand" "0")] + UNSPEC_COMPLEX_F_C_MA_PAIR))] +@@ -6562,7 +6573,7 @@ + [(set (match_operand:VF_AVX512FP16VL 0 "register_operand" "=&v") + (vec_merge:VF_AVX512FP16VL + (unspec:VF_AVX512FP16VL +- [(match_operand:VF_AVX512FP16VL 1 "nonimmediate_operand" "%v") ++ [(match_operand:VF_AVX512FP16VL 1 "nonimmediate_operand" "v") + (match_operand:VF_AVX512FP16VL 2 "nonimmediate_operand" "") + (match_operand:VF_AVX512FP16VL 3 "register_operand" "0")] + UNSPEC_COMPLEX_F_C_MA) +@@ -6586,7 +6597,7 @@ + (define_insn "__" + [(set (match_operand:VF_AVX512FP16VL 0 "register_operand" "=&v") + (unspec:VF_AVX512FP16VL +- [(match_operand:VF_AVX512FP16VL 1 "nonimmediate_operand" "%v") ++ [(match_operand:VF_AVX512FP16VL 1 "nonimmediate_operand" "v") + (match_operand:VF_AVX512FP16VL 2 "nonimmediate_operand" "")] + UNSPEC_COMPLEX_F_C_MUL))] + "TARGET_AVX512FP16 && " +@@ -16350,7 +16361,7 @@ + (match_dup 4))] + UNSPEC_BLENDV))] + { +- if (INTVAL (operands[5]) == 1) ++ if (INTVAL (operands[5]) == 5) + std::swap (operands[1], operands[2]); + operands[3] = gen_lowpart (mode, operands[3]); + }) +@@ -16380,7 +16391,7 @@ + (match_dup 4))] + UNSPEC_BLENDV))] + { +- if (INTVAL (operands[5]) == 1) ++ if (INTVAL (operands[5]) == 5) + std::swap (operands[1], operands[2]); + }) + +@@ -25973,17 +25984,21 @@ + "TARGET_AVX") + + (define_expand "maskload" +- [(set (match_operand:V48H_AVX512VL 0 "register_operand") +- (vec_merge:V48H_AVX512VL +- (match_operand:V48H_AVX512VL 1 "memory_operand") ++ [(set (match_operand:V48_AVX512VL 0 "register_operand") ++ (vec_merge:V48_AVX512VL ++ (unspec:V48_AVX512VL ++ [(match_operand:V48_AVX512VL 1 "memory_operand")] ++ UNSPEC_MASKLOAD) + (match_dup 0) + (match_operand: 2 "register_operand")))] + "TARGET_AVX512F") + + (define_expand "maskload" +- [(set (match_operand:VI12_AVX512VL 0 "register_operand") +- (vec_merge:VI12_AVX512VL +- (match_operand:VI12_AVX512VL 1 "memory_operand") ++ [(set (match_operand:VI12HF_AVX512VL 0 "register_operand") ++ (vec_merge:VI12HF_AVX512VL ++ (unspec:VI12HF_AVX512VL ++ [(match_operand:VI12HF_AVX512VL 1 "memory_operand")] ++ UNSPEC_MASKLOAD) + (match_dup 0) + (match_operand: 2 "register_operand")))] + "TARGET_AVX512BW") +@@ -25998,21 +26013,66 @@ + "TARGET_AVX") + + (define_expand "maskstore" +- [(set (match_operand:V48H_AVX512VL 0 "memory_operand") +- (vec_merge:V48H_AVX512VL +- (match_operand:V48H_AVX512VL 1 "register_operand") +- (match_dup 0) +- (match_operand: 2 "register_operand")))] ++ [(set (match_operand:V48_AVX512VL 0 "memory_operand") ++ (unspec:V48_AVX512VL ++ [(match_operand:V48_AVX512VL 1 "register_operand") ++ (match_dup 0) ++ (match_operand: 2 "register_operand")] ++ UNSPEC_MASKMOV))] + "TARGET_AVX512F") + + (define_expand "maskstore" +- [(set (match_operand:VI12_AVX512VL 0 "memory_operand") +- (vec_merge:VI12_AVX512VL +- (match_operand:VI12_AVX512VL 1 "register_operand") +- (match_dup 0) +- (match_operand: 2 "register_operand")))] ++ [(set (match_operand:VI12HF_AVX512VL 0 "memory_operand") ++ (unspec:VI12HF_AVX512VL ++ [(match_operand:VI12HF_AVX512VL 1 "register_operand") ++ (match_dup 0) ++ (match_operand: 2 "register_operand")] ++ UNSPEC_MASKMOV))] + "TARGET_AVX512BW") + ++(define_insn "_store_mask" ++ [(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m") ++ (unspec:V48_AVX512VL ++ [(match_operand:V48_AVX512VL 1 "register_operand" "v") ++ (match_dup 0) ++ (match_operand: 2 "register_operand" "Yk")] ++ UNSPEC_MASKMOV))] ++ "TARGET_AVX512F" ++{ ++ if (FLOAT_MODE_P (GET_MODE_INNER (mode))) ++ { ++ if (misaligned_operand (operands[0], mode)) ++ return "vmovu\t{%1, %0%{%2%}|%0%{%2%}, %1}"; ++ else ++ return "vmova\t{%1, %0%{%2%}|%0%{%2%}, %1}"; ++ } ++ else ++ { ++ if (misaligned_operand (operands[0], mode)) ++ return "vmovdqu\t{%1, %0%{%2%}|%0%{%2%}, %1}"; ++ else ++ return "vmovdqa\t{%1, %0%{%2%}|%0%{%2%}, %1}"; ++ } ++} ++ [(set_attr "type" "ssemov") ++ (set_attr "prefix" "evex") ++ (set_attr "memory" "store") ++ (set_attr "mode" "")]) ++ ++(define_insn "_store_mask" ++ [(set (match_operand:VI12HF_AVX512VL 0 "memory_operand" "=m") ++ (unspec:VI12HF_AVX512VL ++ [(match_operand:VI12HF_AVX512VL 1 "register_operand" "v") ++ (match_dup 0) ++ (match_operand: 2 "register_operand" "Yk")] ++ UNSPEC_MASKMOV))] ++ "TARGET_AVX512BW" ++ "vmovdqu\t{%1, %0%{%2%}|%0%{%2%}, %1}" ++ [(set_attr "type" "ssemov") ++ (set_attr "prefix" "evex") ++ (set_attr "memory" "store") ++ (set_attr "mode" "")]) ++ + (define_expand "cbranch4" + [(set (reg:CC FLAGS_REG) + (compare:CC (match_operand:VI48_AVX 1 "register_operand") +diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def +index e6b9e21250f..bdb455d20ba 100644 +--- a/gcc/config/i386/x86-tune.def ++++ b/gcc/config/i386/x86-tune.def +@@ -467,7 +467,8 @@ DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes", + /* X86_TUNE_USE_GATHER_2PARTS: Use gather instructions for vectors with 2 + elements. */ + DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts", +- ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE | m_GENERIC)) ++ ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE ++ | m_GENERIC | m_GDS)) + + /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2 + elements. */ +@@ -477,7 +478,8 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts", + /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4 + elements. */ + DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts", +- ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE | m_GENERIC)) ++ ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE ++ | m_GENERIC | m_GDS)) + + /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4 + elements. */ +@@ -486,12 +488,13 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts", + + /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more + elements. */ +-DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather", +- ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER4 | m_ALDERLAKE | m_GENERIC)) ++DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts", ++ ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER4 | m_ALDERLAKE ++ | m_GENERIC | m_GDS)) + + /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more + elements. */ +-DEF_TUNE (X86_TUNE_USE_SCATTER, "use_scatter", ++DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts", + ~(m_ZNVER4)) + + /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or +diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h +index 664dc9206ad..f050078da52 100644 +--- a/gcc/config/loongarch/gnu-user.h ++++ b/gcc/config/loongarch/gnu-user.h +@@ -33,9 +33,14 @@ along with GCC; see the file COPYING3. If not see + #define GLIBC_DYNAMIC_LINKER \ + "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1" + ++#define MUSL_ABI_SPEC \ ++ "%{mabi=lp64d:}" \ ++ "%{mabi=lp64f:-sp}" \ ++ "%{mabi=lp64s:-sf}" ++ + #undef MUSL_DYNAMIC_LINKER + #define MUSL_DYNAMIC_LINKER \ +- "/lib" ABI_GRLEN_SPEC "/ld-musl-loongarch-" ABI_SPEC ".so.1" ++ "/lib/ld-musl-loongarch" ABI_GRLEN_SPEC MUSL_ABI_SPEC ".so.1" + + #undef GNU_USER_TARGET_LINK_SPEC + #define GNU_USER_TARGET_LINK_SPEC \ +diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc +index 22901cb6101..41819eba3d5 100644 +--- a/gcc/config/loongarch/loongarch.cc ++++ b/gcc/config/loongarch/loongarch.cc +@@ -1098,7 +1098,9 @@ loongarch_first_stack_step (struct loongarch_frame_info *frame) + static void + loongarch_emit_stack_tie (void) + { +- emit_insn (gen_stack_tie (Pmode, stack_pointer_rtx, hard_frame_pointer_rtx)); ++ emit_insn (gen_stack_tie (Pmode, stack_pointer_rtx, ++ frame_pointer_needed ? hard_frame_pointer_rtx ++ : stack_pointer_rtx)); + } + + #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) +@@ -4319,27 +4321,27 @@ loongarch_memmodel_needs_rel_acq_fence (enum memmodel model) + } + } + +-/* Return true if a FENCE should be emitted to before a memory access to +- implement the release portion of memory model MODEL. */ ++/* Return true if a FENCE should be emitted after a failed CAS to ++ implement the acquire semantic of failure_memorder. */ + + static bool +-loongarch_memmodel_needs_release_fence (enum memmodel model) ++loongarch_cas_failure_memorder_needs_acquire (enum memmodel model) + { +- switch (model) ++ switch (memmodel_base (model)) + { ++ case MEMMODEL_ACQUIRE: + case MEMMODEL_ACQ_REL: + case MEMMODEL_SEQ_CST: +- case MEMMODEL_SYNC_SEQ_CST: +- case MEMMODEL_RELEASE: +- case MEMMODEL_SYNC_RELEASE: + return true; + +- case MEMMODEL_ACQUIRE: +- case MEMMODEL_CONSUME: +- case MEMMODEL_SYNC_ACQUIRE: + case MEMMODEL_RELAXED: ++ case MEMMODEL_RELEASE: + return false; + ++ /* MEMMODEL_CONSUME is deliberately not handled because it's always ++ replaced by MEMMODEL_ACQUIRE as at now. If you see an ICE caused by ++ MEMMODEL_CONSUME, read the change (re)introducing it carefully and ++ decide what to do. See PR 59448 and get_memmodel in builtins.cc. */ + default: + gcc_unreachable (); + } +@@ -4366,7 +4368,8 @@ loongarch_memmodel_needs_release_fence (enum memmodel model) + 'V' Print exact log2 of CONST_INT OP element 0 of a replicated + CONST_VECTOR in decimal. + 'A' Print a _DB suffix if the memory model requires a release. +- 'G' Print a DBAR insn if the memory model requires a release. ++ 'G' Print a DBAR insn for CAS failure (with an acquire semantic if ++ needed, otherwise a simple load-load barrier). + 'i' Print i if the operand is not a register. */ + + static void +@@ -4487,8 +4490,11 @@ loongarch_print_operand (FILE *file, rtx op, int letter) + break; + + case 'G': +- if (loongarch_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) +- fputs ("dbar\t0", file); ++ if (loongarch_cas_failure_memorder_needs_acquire ( ++ memmodel_from_int (INTVAL (op)))) ++ fputs ("dbar\t0b10100", file); ++ else ++ fputs ("dbar\t0x700", file); + break; + + case 'i': +diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h +index 714401f2dc2..f34a7a604cc 100644 +--- a/gcc/config/loongarch/loongarch.h ++++ b/gcc/config/loongarch/loongarch.h +@@ -1148,3 +1148,8 @@ struct GTY (()) machine_function + (TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT_ABI ? 8 : 4) : 0) + + #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) ++ ++/* LoongArch maintains ICache/DCache coherency by hardware, ++ we just need "ibar" to avoid instruction hazard here. */ ++#undef CLEAR_INSN_CACHE ++#define CLEAR_INSN_CACHE(beg, end) __builtin_loongarch_ibar (0) +diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md +index 8f8412fba84..b49e058407c 100644 +--- a/gcc/config/loongarch/loongarch.md ++++ b/gcc/config/loongarch/loongarch.md +@@ -93,6 +93,7 @@ + + (define_constants + [(RETURN_ADDR_REGNUM 1) ++ (TP_REGNUM 2) + (T0_REGNUM 12) + (T1_REGNUM 13) + (S0_REGNUM 23) +@@ -2622,6 +2623,10 @@ + } + [(set_attr "type" "branch")]) + ++;; Micro-architecture unconditionally treats a "jr $ra" as "return from subroutine", ++;; non-returning indirect jumps through $ra would interfere with both subroutine ++;; return prediction and the more general indirect branch prediction. ++ + (define_expand "indirect_jump" + [(set (pc) (match_operand 0 "register_operand"))] + "" +@@ -2632,7 +2637,7 @@ + }) + + (define_insn "@indirect_jump" +- [(set (pc) (match_operand:P 0 "register_operand" "r"))] ++ [(set (pc) (match_operand:P 0 "register_operand" "e"))] + "" + "jr\t%0" + [(set_attr "type" "jump") +@@ -2655,7 +2660,7 @@ + + (define_insn "@tablejump" + [(set (pc) +- (match_operand:P 0 "register_operand" "r")) ++ (match_operand:P 0 "register_operand" "e")) + (use (label_ref (match_operand 1 "" "")))] + "" + "jr\t%0" +@@ -3291,6 +3296,12 @@ + [(set_attr "length" "0") + (set_attr "type" "ghost")]) + ++;; Named pattern for expanding thread pointer reference. ++(define_expand "get_thread_pointer" ++ [(set (match_operand:P 0 "register_operand" "=r") ++ (reg:P TP_REGNUM))] ++ "HAVE_AS_TLS" ++ {}) + + (define_split + [(match_operand 0 "small_data_pattern")] +diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md +index 45be1442439..b8763b8f9d1 100644 +--- a/gcc/config/loongarch/sync.md ++++ b/gcc/config/loongarch/sync.md +@@ -129,19 +129,18 @@ + (clobber (match_scratch:GPR 6 "=&r"))] + "" + { +- return "%G5\\n\\t" +- "1:\\n\\t" ++ return "1:\\n\\t" + "ll.\\t%0,%1\\n\\t" + "bne\\t%0,%z2,2f\\n\\t" + "or%i3\\t%6,$zero,%3\\n\\t" + "sc.\\t%6,%1\\n\\t" +- "beq\\t$zero,%6,1b\\n\\t" ++ "beqz\\t%6,1b\\n\\t" + "b\\t3f\\n\\t" + "2:\\n\\t" +- "dbar\\t0x700\\n\\t" ++ "%G5\\n\\t" + "3:\\n\\t"; + } +- [(set (attr "length") (const_int 32))]) ++ [(set (attr "length") (const_int 28))]) + + (define_expand "atomic_compare_and_swap" + [(match_operand:SI 0 "register_operand" "") ;; bool output +@@ -234,8 +233,7 @@ + (clobber (match_scratch:GPR 7 "=&r"))] + "" + { +- return "%G6\\n\\t" +- "1:\\n\\t" ++ return "1:\\n\\t" + "ll.\\t%0,%1\\n\\t" + "and\\t%7,%0,%2\\n\\t" + "bne\\t%7,%z4,2f\\n\\t" +@@ -245,10 +243,10 @@ + "beq\\t$zero,%7,1b\\n\\t" + "b\\t3f\\n\\t" + "2:\\n\\t" +- "dbar\\t0x700\\n\\t" ++ "%G6\\n\\t" + "3:\\n\\t"; + } +- [(set (attr "length") (const_int 40))]) ++ [(set (attr "length") (const_int 36))]) + + (define_expand "atomic_compare_and_swap" + [(match_operand:SI 0 "register_operand" "") ;; bool output +@@ -303,8 +301,7 @@ + (clobber (match_scratch:GPR 8 "=&r"))] + "" + { +- return "%G6\\n\\t" +- "1:\\n\\t" ++ return "1:\\n\\t" + "ll.\\t%0,%1\\n\\t" + "and\\t%7,%0,%3\\n\\t" + "add.w\\t%8,%0,%z5\\n\\t" +@@ -314,7 +311,7 @@ + "beq\\t$zero,%7,1b"; + } + +- [(set (attr "length") (const_int 32))]) ++ [(set (attr "length") (const_int 28))]) + + (define_insn "atomic_cas_value_sub_7_" + [(set (match_operand:GPR 0 "register_operand" "=&r") ;; res +@@ -330,8 +327,7 @@ + (clobber (match_scratch:GPR 8 "=&r"))] + "" + { +- return "%G6\\n\\t" +- "1:\\n\\t" ++ return "1:\\n\\t" + "ll.\\t%0,%1\\n\\t" + "and\\t%7,%0,%3\\n\\t" + "sub.w\\t%8,%0,%z5\\n\\t" +@@ -340,7 +336,7 @@ + "sc.\\t%7,%1\\n\\t" + "beq\\t$zero,%7,1b"; + } +- [(set (attr "length") (const_int 32))]) ++ [(set (attr "length") (const_int 28))]) + + (define_insn "atomic_cas_value_and_7_" + [(set (match_operand:GPR 0 "register_operand" "=&r") ;; res +@@ -356,8 +352,7 @@ + (clobber (match_scratch:GPR 8 "=&r"))] + "" + { +- return "%G6\\n\\t" +- "1:\\n\\t" ++ return "1:\\n\\t" + "ll.\\t%0,%1\\n\\t" + "and\\t%7,%0,%3\\n\\t" + "and\\t%8,%0,%z5\\n\\t" +@@ -366,7 +361,7 @@ + "sc.\\t%7,%1\\n\\t" + "beq\\t$zero,%7,1b"; + } +- [(set (attr "length") (const_int 32))]) ++ [(set (attr "length") (const_int 28))]) + + (define_insn "atomic_cas_value_xor_7_" + [(set (match_operand:GPR 0 "register_operand" "=&r") ;; res +@@ -382,8 +377,7 @@ + (clobber (match_scratch:GPR 8 "=&r"))] + "" + { +- return "%G6\\n\\t" +- "1:\\n\\t" ++ return "1:\\n\\t" + "ll.\\t%0,%1\\n\\t" + "and\\t%7,%0,%3\\n\\t" + "xor\\t%8,%0,%z5\\n\\t" +@@ -393,7 +387,7 @@ + "beq\\t$zero,%7,1b"; + } + +- [(set (attr "length") (const_int 32))]) ++ [(set (attr "length") (const_int 28))]) + + (define_insn "atomic_cas_value_or_7_" + [(set (match_operand:GPR 0 "register_operand" "=&r") ;; res +@@ -409,8 +403,7 @@ + (clobber (match_scratch:GPR 8 "=&r"))] + "" + { +- return "%G6\\n\\t" +- "1:\\n\\t" ++ return "1:\\n\\t" + "ll.\\t%0,%1\\n\\t" + "and\\t%7,%0,%3\\n\\t" + "or\\t%8,%0,%z5\\n\\t" +@@ -420,7 +413,7 @@ + "beq\\t$zero,%7,1b"; + } + +- [(set (attr "length") (const_int 32))]) ++ [(set (attr "length") (const_int 28))]) + + (define_insn "atomic_cas_value_nand_7_" + [(set (match_operand:GPR 0 "register_operand" "=&r") ;; res +@@ -436,8 +429,7 @@ + (clobber (match_scratch:GPR 8 "=&r"))] + "" + { +- return "%G6\\n\\t" +- "1:\\n\\t" ++ return "1:\\n\\t" + "ll.\\t%0,%1\\n\\t" + "and\\t%7,%0,%3\\n\\t" + "and\\t%8,%0,%z5\\n\\t" +@@ -446,7 +438,7 @@ + "sc.\\t%7,%1\\n\\t" + "beq\\t$zero,%7,1b"; + } +- [(set (attr "length") (const_int 32))]) ++ [(set (attr "length") (const_int 28))]) + + (define_insn "atomic_cas_value_exchange_7_" + [(set (match_operand:GPR 0 "register_operand" "=&r") +@@ -461,8 +453,7 @@ + (clobber (match_scratch:GPR 7 "=&r"))] + "" + { +- return "%G6\\n\\t" +- "1:\\n\\t" ++ return "1:\\n\\t" + "ll.\\t%0,%1\\n\\t" + "and\\t%7,%0,%z3\\n\\t" + "or%i5\\t%7,%7,%5\\n\\t" +diff --git a/gcc/config/loongarch/t-loongarch b/gcc/config/loongarch/t-loongarch +index 6d6e3435d59..e73f4f437ef 100644 +--- a/gcc/config/loongarch/t-loongarch ++++ b/gcc/config/loongarch/t-loongarch +@@ -16,6 +16,10 @@ + # along with GCC; see the file COPYING3. If not see + # . + ++TM_H += $(srcdir)/config/loongarch/loongarch-driver.h ++OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \ ++ $(srcdir)/config/loongarch/loongarch-tune.h ++ + # Canonical target triplet from config.gcc + LA_MULTIARCH_TRIPLET = $(patsubst LA_MULTIARCH_TRIPLET=%,%,$\ + $(filter LA_MULTIARCH_TRIPLET=%,$(tm_defines))) +diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc +index 65f8fe814c6..ec81f403a01 100644 +--- a/gcc/config/pa/pa.cc ++++ b/gcc/config/pa/pa.cc +@@ -10400,7 +10400,7 @@ pa_asm_trampoline_template (FILE *f) + fputs ("\tldw 0(%r22),%r21\n", f); + fputs ("\tldw 4(%r22),%r19\n", f); + fputs ("\tbve (%r21)\n", f); +- fputs ("\tldw 52(%r1),%r29\n", f); ++ fputs ("\tldw 52(%r20),%r29\n", f); + fputs ("\t.word 0\n", f); + fputs ("\t.word 0\n", f); + fputs ("\t.word 0\n", f); +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 4939d9964db..dddd72aa237 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -5600,9 +5600,8 @@ riscv_asan_shadow_offset (void) + /* We only have libsanitizer support for RV64 at present. + + This number must match kRiscv*_ShadowOffset* in the file +- libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64, +- even though 1<<36 makes more sense. */ +- return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0; ++ libsanitizer/asan/asan_mapping.h. */ ++ return TARGET_64BIT ? HOST_WIDE_INT_UC (0xd55550000) : 0; + } + + /* Initialize the GCC target structure. */ +diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md +index 8db9d68fbda..3849db5ca3c 100644 +--- a/gcc/config/rs6000/altivec.md ++++ b/gcc/config/rs6000/altivec.md +@@ -385,14 +385,22 @@ + + (define_insn_and_split "sldoi_to_mov" + [(set (match_operand:VM 0 "altivec_register_operand") +- (unspec:VM [(match_operand:VM 1 "easy_vector_constant") ++ (unspec:VM [(match_operand:VM 1 "const_vector_each_byte_same") + (match_dup 1) + (match_operand:QI 2 "u5bit_cint_operand")] + UNSPEC_VSLDOI))] +- "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && can_create_pseudo_p ()" ++ "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && can_create_pseudo_p ()" + "#" + "&& 1" +- [(set (match_dup 0) (match_dup 1))]) ++ [(set (match_dup 0) (match_dup 1))] ++ "{ ++ if (!easy_vector_constant (operands[1], mode)) ++ { ++ rtx dest = gen_reg_rtx (mode); ++ emit_move_insn (dest, operands[1]); ++ operands[1] = dest; ++ } ++ }") + + (define_insn "get_vrsave_internal" + [(set (match_operand:SI 0 "register_operand" "=r") +diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md +index 15f0c16f705..4067ee76215 100644 +--- a/gcc/config/rs6000/fusion.md ++++ b/gcc/config/rs6000/fusion.md +@@ -22,7 +22,7 @@ + ;; load mode is DI result mode is clobber compare mode is CC extend is none + (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") + (match_operand:DI 3 "const_m1_to_1_operand" "n"))) + (clobber (match_scratch:DI 0 "=r"))] + "(TARGET_P10_FUSION)" +@@ -43,7 +43,7 @@ + ;; load mode is DI result mode is clobber compare mode is CCUNS extend is none + (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") +- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m") ++ (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") + (match_operand:DI 3 "const_0_to_1_operand" "n"))) + (clobber (match_scratch:DI 0 "=r"))] + "(TARGET_P10_FUSION)" +@@ -64,7 +64,7 @@ + ;; load mode is DI result mode is DI compare mode is CC extend is none + (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") + (match_operand:DI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION)" +@@ -85,7 +85,7 @@ + ;; load mode is DI result mode is DI compare mode is CCUNS extend is none + (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") +- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m") ++ (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") + (match_operand:DI 3 "const_0_to_1_operand" "n"))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION)" +@@ -104,17 +104,17 @@ + + ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 + ;; load mode is SI result mode is clobber compare mode is CC extend is none +-(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none" ++(define_insn_and_split "*lwz_cmpwi_cr0_SI_clobber_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_m1_to_1_operand" "n"))) + (clobber (match_scratch:SI 0 "=r"))] + "(TARGET_P10_FUSION)" +- "lwa%X1 %0,%1\;cmpdi %2,%0,%3" ++ "lwz%X1 %0,%1\;cmpwi %2,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), +- SImode, NON_PREFIXED_DS))" ++ SImode, NON_PREFIXED_D))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CC (match_dup 0) (match_dup 3)))] +@@ -146,17 +146,17 @@ + + ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 + ;; load mode is SI result mode is SI compare mode is CC extend is none +-(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none" ++(define_insn_and_split "*lwz_cmpwi_cr0_SI_SI_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION)" +- "lwa%X1 %0,%1\;cmpdi %2,%0,%3" ++ "lwz%X1 %0,%1\;cmpwi %2,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), +- SImode, NON_PREFIXED_DS))" ++ SImode, NON_PREFIXED_D))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CC (match_dup 0) (match_dup 3)))] +@@ -190,7 +190,7 @@ + ;; load mode is SI result mode is EXTSI compare mode is CC extend is sign + (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") +- (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") ++ (compare:CC (match_operand:SI 1 "non_update_memory_operand" "YZ") + (match_operand:SI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))] + "(TARGET_P10_FUSION)" +@@ -205,6 +205,7 @@ + "" + [(set_attr "type" "fused_load_cmpi") + (set_attr "cost" "8") ++ (set_attr "sign_extend" "yes") + (set_attr "length" "8")]) + + ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl +index 81cc2255f53..d0517970ace 100755 +--- a/gcc/config/rs6000/genfusion.pl ++++ b/gcc/config/rs6000/genfusion.pl +@@ -53,92 +53,136 @@ sub mode_to_ldst_char + return '?'; + } + ++sub gen_ld_cmpi_p10_one ++{ ++ my ($lmode, $result, $ccmode) = @_; ++ ++ my $np = "NON_PREFIXED_D"; ++ my $mempred = "non_update_memory_operand"; ++ my $extend; ++ ++ # We need to special case lwa. The prefixed_load_p function in rs6000.cc ++ # (which determines if a load instruction is prefixed) uses the fact that the ++ # register mode is different from the memory mode, and that the sign_extend ++ # attribute is set to use DS-form rules for the address instead of D-form. ++ # If the register size is the same, prefixed_load_p assumes we are doing a ++ # lwz. We change to use an lwz and word compare if we don't need to sign ++ # extend the SImode value. Otherwise if we need the value, we need to ++ # make sure the insn is marked as ds-form. ++ my $cmp_size_char = ($lmode eq "SI" ++ && $ccmode eq "CC" ++ && $result !~ /^EXT|^DI$/) ? "w" : "d"; ++ ++ if ($ccmode eq "CC") { ++ # ld and lwa are both DS-FORM. ++ ($lmode eq "DI") and $np = "NON_PREFIXED_DS"; ++ ($lmode eq "SI" && $cmp_size_char eq "d") and $np = "NON_PREFIXED_DS"; ++ } else { ++ if ($lmode eq "DI") { ++ # ld is DS-form, but lwz is not. ++ $np = "NON_PREFIXED_DS"; ++ } ++ } ++ ++ my $cmpl = ($ccmode eq "CC") ? "" : "l"; ++ my $echr = ($ccmode eq "CC" && $cmp_size_char eq "d") ? "a" : "z"; ++ if ($lmode eq "DI") { $echr = ""; } ++ my $constpred = ($ccmode eq "CC") ? "const_m1_to_1_operand" ++ : "const_0_to_1_operand"; ++ ++ # For clobber, we need a SI/DI reg in case we ++ # split because we have to sign/zero extend. ++ my $clobbermode = ($lmode =~ /^[QH]I$/) ? "GPR" : $lmode; ++ if ($result =~ /^EXT/ || $result eq "GPR" || $clobbermode eq "GPR") { ++ # We always need extension if result > lmode. ++ $extend = ($ccmode eq "CC") ? "sign" : "zero"; ++ } else { ++ # Result of SI/DI does not need sign extension. ++ $extend = "none"; ++ } ++ ++ my $ldst = mode_to_ldst_char($lmode); ++ ++ # DS-form addresses need YZ, and not m. ++ my $constraint = ($np eq "NON_PREFIXED_DS") ? "YZ" : "m"; ++ print < lmode. +- if ( $ccmode eq 'CC' ) { +- $extend = "sign"; +- } else { +- $extend = "zero"; +- } +- } else { +- # Result of SI/DI does not need sign extension. +- $extend = "none"; +- } +- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n"; +- print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n"; +- +- print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n"; +- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n"; +- print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n"; +- if ($ccmode eq 'CCUNS') { print " "; } +- print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n"; +- if ($result eq 'clobber') { +- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n"; +- } elsif ($result eq $lmode) { +- print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n"; +- } else { +- print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n"; +- } +- print " \"(TARGET_P10_FUSION)\"\n"; +- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n"; +- print " \"&& reload_completed\n"; +- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n"; +- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n"; +- print " ${lmode}mode, ${np}))\"\n"; +- +- if ($extend eq "none") { +- print " [(set (match_dup 0) (match_dup 1))\n"; +- } else { +- $resultmode = $result; +- if ( $result eq 'clobber' ) { $resultmode = $clobbermode } +- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n"; +- } +- print " (set (match_dup 2)\n"; +- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n"; +- print " \"\"\n"; +- print " [(set_attr \"type\" \"fused_load_cmpi\")\n"; +- print " (set_attr \"cost\" \"8\")\n"; +- print " (set_attr \"length\" \"8\")])\n"; +- print "\n"; ++ foreach my $lmode (qw/DI SI HI QI/) { ++ foreach my $result ("clobber", $lmode, "EXT$lmode") { ++ # EXTDI does not exist, and we cannot directly produce HI/QI results. ++ next if $result =~ /^(QI|HI|EXTDI)$/; ++ ++ # Don't allow EXTQI because that would allow HI result which we can't do. ++ $result = "GPR" if $result eq "EXTQI"; ++ ++ foreach my $ccmode (qw/CC CCUNS/) { ++ # We do not have signed single-byte loads. ++ next if ($lmode eq "QI" and $ccmode eq "CC"); ++ ++ gen_ld_cmpi_p10_one($lmode, $result, $ccmode); + } + } + } +diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md +index b1fcc69bb60..129664da94c 100644 +--- a/gcc/config/rs6000/predicates.md ++++ b/gcc/config/rs6000/predicates.md +@@ -798,6 +798,43 @@ + (and (match_test "easy_altivec_constant (op, mode)") + (match_test "vspltis_shifted (op) != 0"))))) + ++;; Return true if this is a vector constant and each byte in ++;; it is the same. ++(define_predicate "const_vector_each_byte_same" ++ (match_code "const_vector") ++{ ++ rtx elt; ++ if (!const_vec_duplicate_p (op, &elt)) ++ return false; ++ ++ machine_mode emode = GET_MODE_INNER (mode); ++ unsigned HOST_WIDE_INT eval; ++ if (CONST_INT_P (elt)) ++ eval = INTVAL (elt); ++ else if (CONST_DOUBLE_AS_FLOAT_P (elt)) ++ { ++ gcc_assert (emode == SFmode || emode == DFmode); ++ long l[2]; ++ real_to_target (l, CONST_DOUBLE_REAL_VALUE (elt), emode); ++ /* real_to_target puts 32-bit pieces in each long. */ ++ eval = zext_hwi (l[0], 32); ++ eval |= zext_hwi (l[1], 32) << 32; ++ } ++ else ++ return false; ++ ++ unsigned int esize = GET_MODE_SIZE (emode); ++ unsigned char byte0 = eval & 0xff; ++ for (unsigned int i = 1; i < esize; i++) ++ { ++ eval >>= BITS_PER_UNIT; ++ if (byte0 != (eval & 0xff)) ++ return false; ++ } ++ ++ return true; ++}) ++ + ;; Return 1 if operand is a vector int register or is either a vector constant + ;; of all 0 bits of a vector constant of all 1 bits. + (define_predicate "vector_int_reg_or_same_bit" +@@ -1088,20 +1125,6 @@ + return INTVAL (offset) % 4 == 0; + }) + +-;; Return 1 if the operand is a memory operand that has a valid address for +-;; a DS-form instruction. I.e. the address has to be either just a register, +-;; or register + const where the two low order bits of const are zero. +-(define_predicate "ds_form_mem_operand" +- (match_code "subreg,mem") +-{ +- if (!any_memory_operand (op, mode)) +- return false; +- +- rtx addr = XEXP (op, 0); +- +- return address_to_insn_form (addr, mode, NON_PREFIXED_DS) == INSN_FORM_DS; +-}) +- + ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. + (define_predicate "symbol_ref_operand" + (and (match_code "symbol_ref") +diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def +index afc3cd692c1..d2c0565dc62 100644 +--- a/gcc/config/rs6000/rs6000-builtins.def ++++ b/gcc/config/rs6000/rs6000-builtins.def +@@ -2008,6 +2008,13 @@ + const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>); + XXSPLTD_V2DI vsx_xxspltd_v2di {} + ++ const vsq __builtin_pack_vector_int128 (unsigned long long, \ ++ unsigned long long); ++ PACK_V1TI packv1ti {} ++ ++ const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); ++ UNPACK_V1TI unpackv1ti {} ++ + + ; Power7 builtins (ISA 2.06). + [power7] +@@ -2029,16 +2036,9 @@ + const unsigned int __builtin_divweu (unsigned int, unsigned int); + DIVWEU diveu_si {} + +- const vsq __builtin_pack_vector_int128 (unsigned long long, \ +- unsigned long long); +- PACK_V1TI packv1ti {} +- + void __builtin_ppc_speculation_barrier (); + SPECBARR speculation_barrier {} + +- const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); +- UNPACK_V1TI unpackv1ti {} +- + + ; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing). + [power7-64] +@@ -2796,6 +2796,19 @@ + const vsi __builtin_vsx_xxbrw_v4si (vsi); + XXBRW_V4SI p9_xxbrw_v4si {} + ++ const signed int __builtin_vsx_scalar_cmp_exp_qp_eq (_Float128, _Float128); ++ VSCEQPEQ xscmpexpqp_eq_kf {} ++ ++ const signed int __builtin_vsx_scalar_cmp_exp_qp_gt (_Float128, _Float128); ++ VSCEQPGT xscmpexpqp_gt_kf {} ++ ++ const signed int __builtin_vsx_scalar_cmp_exp_qp_lt (_Float128, _Float128); ++ VSCEQPLT xscmpexpqp_lt_kf {} ++ ++ const signed int \ ++ __builtin_vsx_scalar_cmp_exp_qp_unordered (_Float128, _Float128); ++ VSCEQPUO xscmpexpqp_unordered_kf {} ++ + + ; Miscellaneous P9 functions + [power9] +@@ -2878,19 +2891,6 @@ + fpmath _Float128 __builtin_mulf128_round_to_odd (_Float128, _Float128); + MULF128_ODD mulkf3_odd {} + +- const signed int __builtin_vsx_scalar_cmp_exp_qp_eq (_Float128, _Float128); +- VSCEQPEQ xscmpexpqp_eq_kf {} +- +- const signed int __builtin_vsx_scalar_cmp_exp_qp_gt (_Float128, _Float128); +- VSCEQPGT xscmpexpqp_gt_kf {} +- +- const signed int __builtin_vsx_scalar_cmp_exp_qp_lt (_Float128, _Float128); +- VSCEQPLT xscmpexpqp_lt_kf {} +- +- const signed int \ +- __builtin_vsx_scalar_cmp_exp_qp_unordered (_Float128, _Float128); +- VSCEQPUO xscmpexpqp_unordered_kf {} +- + fpmath _Float128 __builtin_sqrtf128_round_to_odd (_Float128); + SQRTF128_ODD sqrtkf2_odd {} + +diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc +index 59d901ac68d..162f8562897 100644 +--- a/gcc/config/rs6000/rs6000-string.cc ++++ b/gcc/config/rs6000/rs6000-string.cc +@@ -2811,11 +2811,17 @@ expand_block_move (rtx operands[], bool might_overlap) + gen_func.mov = gen_vsx_movv2di_64bit; + } + else if (TARGET_BLOCK_OPS_UNALIGNED_VSX +- && TARGET_POWER10 && bytes < 16 ++ /* Only use lxvl/stxvl on 64bit POWER10. */ ++ && TARGET_POWER10 ++ && TARGET_64BIT ++ && bytes < 16 + && orig_bytes > 16 +- && !(bytes == 1 || bytes == 2 +- || bytes == 4 || bytes == 8) +- && (align >= 128 || !STRICT_ALIGNMENT)) ++ && !(bytes == 1 ++ || bytes == 2 ++ || bytes == 4 ++ || bytes == 8) ++ && (align >= 128 ++ || !STRICT_ALIGNMENT)) + { + /* Only use lxvl/stxvl if it could replace multiple ordinary + loads+stores. Also don't use it unless we likely already +diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc +index f678561071a..70406c21c1c 100644 +--- a/gcc/config/rs6000/rs6000.cc ++++ b/gcc/config/rs6000/rs6000.cc +@@ -8128,7 +8128,8 @@ darwin_rs6000_special_round_type_align (tree type, unsigned int computed, + type = TREE_TYPE (type); + } while (AGGREGATE_TYPE_P (type)); + +- if (! AGGREGATE_TYPE_P (type) && type != error_mark_node) ++ if (type != error_mark_node && ! AGGREGATE_TYPE_P (type) ++ && ! TYPE_PACKED (type) && maximum_field_alignment == 0) + align = MAX (align, TYPE_ALIGN (type)); + + return align; +@@ -17116,7 +17117,7 @@ output_toc (FILE *file, rtx x, int labelno, machine_mode mode) + if (DECIMAL_FLOAT_MODE_P (GET_MODE (x))) + REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k); + else +- REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k); ++ real_to_target (k, CONST_DOUBLE_REAL_VALUE (x), GET_MODE (x)); + + if (TARGET_64BIT) + { +@@ -21906,7 +21907,9 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, + *total = rs6000_cost->divsi; + } + /* Add in shift and subtract for MOD unless we have a mod instruction. */ +- if (!TARGET_MODULO && (code == MOD || code == UMOD)) ++ if ((!TARGET_MODULO ++ || (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode))) ++ && (code == MOD || code == UMOD)) + *total += COSTS_N_INSNS (2); + return false; + +@@ -25250,15 +25253,21 @@ rs6000_need_ipa_fn_target_info (const_tree decl, + static bool + rs6000_update_ipa_fn_target_info (unsigned int &info, const gimple *stmt) + { ++#ifndef HAVE_AS_POWER10_HTM + /* Assume inline asm can use any instruction features. */ + if (gimple_code (stmt) == GIMPLE_ASM) + { +- /* Should set any bits we concerned, for now OPTION_MASK_HTM is +- the only bit we care about. */ +- info |= RS6000_FN_TARGET_INFO_HTM; ++ const char *asm_str = gimple_asm_string (as_a (stmt)); ++ /* Ignore empty inline asm string. */ ++ if (strlen (asm_str) > 0) ++ /* Should set any bits we concerned, for now OPTION_MASK_HTM is ++ the only bit we care about. */ ++ info |= RS6000_FN_TARGET_INFO_HTM; + return false; + } +- else if (gimple_code (stmt) == GIMPLE_CALL) ++#endif ++ ++ if (gimple_code (stmt) == GIMPLE_CALL) + { + tree fndecl = gimple_call_fndecl (stmt); + if (fndecl && fndecl_built_in_p (fndecl, BUILT_IN_MD)) +@@ -25286,49 +25295,44 @@ rs6000_can_inline_p (tree caller, tree callee) + tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller); + tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee); + +- /* If the callee has no option attributes, then it is ok to inline. */ ++ /* If the caller/callee has option attributes, then use them. ++ Otherwise, use the command line options. */ + if (!callee_tree) +- ret = true; ++ callee_tree = target_option_default_node; ++ if (!caller_tree) ++ caller_tree = target_option_default_node; + +- else +- { +- HOST_WIDE_INT caller_isa; +- struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); +- HOST_WIDE_INT callee_isa = callee_opts->x_rs6000_isa_flags; +- HOST_WIDE_INT explicit_isa = callee_opts->x_rs6000_isa_flags_explicit; ++ struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); ++ struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree); + +- /* If the caller has option attributes, then use them. +- Otherwise, use the command line options. */ +- if (caller_tree) +- caller_isa = TREE_TARGET_OPTION (caller_tree)->x_rs6000_isa_flags; +- else +- caller_isa = rs6000_isa_flags; ++ HOST_WIDE_INT callee_isa = callee_opts->x_rs6000_isa_flags; ++ HOST_WIDE_INT caller_isa = caller_opts->x_rs6000_isa_flags; ++ HOST_WIDE_INT explicit_isa = callee_opts->x_rs6000_isa_flags_explicit; + +- cgraph_node *callee_node = cgraph_node::get (callee); +- if (ipa_fn_summaries && ipa_fn_summaries->get (callee_node) != NULL) ++ cgraph_node *callee_node = cgraph_node::get (callee); ++ if (ipa_fn_summaries && ipa_fn_summaries->get (callee_node) != NULL) ++ { ++ unsigned int info = ipa_fn_summaries->get (callee_node)->target_info; ++ if ((info & RS6000_FN_TARGET_INFO_HTM) == 0) + { +- unsigned int info = ipa_fn_summaries->get (callee_node)->target_info; +- if ((info & RS6000_FN_TARGET_INFO_HTM) == 0) +- { +- callee_isa &= ~OPTION_MASK_HTM; +- explicit_isa &= ~OPTION_MASK_HTM; +- } ++ callee_isa &= ~OPTION_MASK_HTM; ++ explicit_isa &= ~OPTION_MASK_HTM; + } ++ } + +- /* Ignore -mpower8-fusion and -mpower10-fusion options for inlining +- purposes. */ +- callee_isa &= ~(OPTION_MASK_P8_FUSION | OPTION_MASK_P10_FUSION); +- explicit_isa &= ~(OPTION_MASK_P8_FUSION | OPTION_MASK_P10_FUSION); ++ /* Ignore -mpower8-fusion and -mpower10-fusion options for inlining ++ purposes. */ ++ callee_isa &= ~(OPTION_MASK_P8_FUSION | OPTION_MASK_P10_FUSION); ++ explicit_isa &= ~(OPTION_MASK_P8_FUSION | OPTION_MASK_P10_FUSION); + +- /* The callee's options must be a subset of the caller's options, i.e. +- a vsx function may inline an altivec function, but a no-vsx function +- must not inline a vsx function. However, for those options that the +- callee has explicitly enabled or disabled, then we must enforce that +- the callee's and caller's options match exactly; see PR70010. */ +- if (((caller_isa & callee_isa) == callee_isa) +- && (caller_isa & explicit_isa) == (callee_isa & explicit_isa)) +- ret = true; +- } ++ /* The callee's options must be a subset of the caller's options, i.e. ++ a vsx function may inline an altivec function, but a no-vsx function ++ must not inline a vsx function. However, for those options that the ++ callee has explicitly enabled or disabled, then we must enforce that ++ the callee's and caller's options match exactly; see PR70010. */ ++ if (((caller_isa & callee_isa) == callee_isa) ++ && (caller_isa & explicit_isa) == (callee_isa & explicit_isa)) ++ ret = true; + + if (TARGET_DEBUG_TARGET) + fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n", +@@ -28603,7 +28607,6 @@ vec_const_128bit_to_bytes (rtx op, + + info->all_words_same + = (info->words[0] == info->words[1] +- && info->words[0] == info->words[1] + && info->words[0] == info->words[2] + && info->words[0] == info->words[3]); + +diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h +index 5c886d909aa..9577e715d67 100644 +--- a/gcc/config/rs6000/rs6000.h ++++ b/gcc/config/rs6000/rs6000.h +@@ -2632,3 +2632,9 @@ while (0) + rs6000_asm_output_opcode (STREAM); \ + } \ + while (0) ++ ++/* Disable generation of scalar modulo instructions due to performance issues ++ with certain input values. This can be removed in the future when the ++ issues have been resolved. */ ++#define RS6000_DISABLE_SCALAR_MODULO 1 ++ +diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md +index 914ddcc8884..5cbf25dc76b 100644 +--- a/gcc/config/rs6000/rs6000.md ++++ b/gcc/config/rs6000/rs6000.md +@@ -287,7 +287,7 @@ + ;; Whether this insn has a prefixed form and a non-prefixed form. + (define_attr "maybe_prefixed" "no,yes" + (if_then_else (eq_attr "type" "load,fpload,vecload,store,fpstore,vecstore, +- integer,add") ++ integer,add,fused_load_cmpi") + (const_string "yes") + (const_string "no"))) + +@@ -302,7 +302,7 @@ + (eq_attr "maybe_prefixed" "no")) + (const_string "no") + +- (eq_attr "type" "load,fpload,vecload") ++ (eq_attr "type" "load,fpload,vecload,fused_load_cmpi") + (if_then_else (match_test "prefixed_load_p (insn)") + (const_string "yes") + (const_string "no")) +@@ -3359,6 +3359,17 @@ + FAIL; + + operands[2] = force_reg (mode, operands[2]); ++ ++ if (RS6000_DISABLE_SCALAR_MODULO) ++ { ++ temp1 = gen_reg_rtx (mode); ++ temp2 = gen_reg_rtx (mode); ++ ++ emit_insn (gen_div3 (temp1, operands[1], operands[2])); ++ emit_insn (gen_mul3 (temp2, temp1, operands[2])); ++ emit_insn (gen_sub3 (operands[0], operands[1], temp2)); ++ DONE; ++ } + } + else + { +@@ -3378,17 +3389,36 @@ + [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r") + (mod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r")))] +- "TARGET_MODULO" ++ "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO" + "mods %0,%1,%2" + [(set_attr "type" "div") + (set_attr "size" "")]) + ++;; This define_expand can be removed when RS6000_DISABLE_SCALAR_MODULO is ++;; removed. ++(define_expand "umod3" ++ [(set (match_operand:GPR 0 "gpc_reg_operand") ++ (umod:GPR (match_operand:GPR 1 "gpc_reg_operand") ++ (match_operand:GPR 2 "gpc_reg_operand")))] ++ "TARGET_MODULO" ++{ ++ if (RS6000_DISABLE_SCALAR_MODULO) ++ { ++ rtx temp1 = gen_reg_rtx (mode); ++ rtx temp2 = gen_reg_rtx (mode); ++ ++ emit_insn (gen_udiv3 (temp1, operands[1], operands[2])); ++ emit_insn (gen_mul3 (temp2, temp1, operands[2])); ++ emit_insn (gen_sub3 (operands[0], operands[1], temp2)); ++ DONE; ++ } ++}) + +-(define_insn "umod3" ++(define_insn "*umod3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r") + (umod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r")))] +- "TARGET_MODULO" ++ "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO" + "modu %0,%1,%2" + [(set_attr "type" "div") + (set_attr "size" "")]) +@@ -3445,7 +3475,7 @@ + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (umod:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] +- "TARGET_POWER10 && TARGET_POWERPC64" ++ "TARGET_POWER10 && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO" + "vmoduq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) +@@ -3454,7 +3484,7 @@ + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (mod:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] +- "TARGET_POWER10 && TARGET_POWERPC64" ++ "TARGET_POWER10 && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO" + "vmodsq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) +@@ -12215,33 +12245,26 @@ + DONE; + }) + +-(define_insn "stack_protect_setsi" +- [(set (match_operand:SI 0 "memory_operand" "=m") +- (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) +- (set (match_scratch:SI 2 "=&r") (const_int 0))] +- "TARGET_32BIT" +- "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0" +- [(set_attr "type" "three") +- (set_attr "length" "12")]) +- + ;; We can't use the prefixed attribute here because there are two memory + ;; instructions. We can't split the insn due to the fact that this operation + ;; needs to be done in one piece. +-(define_insn "stack_protect_setdi" +- [(set (match_operand:DI 0 "memory_operand" "=Y") +- (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET)) +- (set (match_scratch:DI 2 "=&r") (const_int 0))] +- "TARGET_64BIT" ++(define_insn "stack_protect_set" ++ [(set (match_operand:P 0 "memory_operand" "=YZ") ++ (unspec:P [(match_operand:P 1 "memory_operand" "YZ")] UNSPEC_SP_SET)) ++ (set (match_scratch:P 2 "=&r") (const_int 0))] ++ "" + { +- if (prefixed_memory (operands[1], DImode)) +- output_asm_insn ("pld %2,%1", operands); ++ if (prefixed_memory (operands[1], mode)) ++ /* Prefixed load only supports D-form but no update and X-form. */ ++ output_asm_insn ("p %2,%1", operands); + else +- output_asm_insn ("ld%U1%X1 %2,%1", operands); ++ output_asm_insn ("%U1%X1 %2,%1", operands); + +- if (prefixed_memory (operands[0], DImode)) +- output_asm_insn ("pstd %2,%0", operands); ++ if (prefixed_memory (operands[0], mode)) ++ /* Prefixed store only supports D-form but no update and X-form. */ ++ output_asm_insn ("pst %2,%0", operands); + else +- output_asm_insn ("std%U0%X0 %2,%0", operands); ++ output_asm_insn ("st%U0%X0 %2,%0", operands); + + return "li %2,0"; + } +@@ -12287,45 +12310,33 @@ + DONE; + }) + +-(define_insn "stack_protect_testsi" +- [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") +- (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m") +- (match_operand:SI 2 "memory_operand" "m,m")] +- UNSPEC_SP_TEST)) +- (set (match_scratch:SI 4 "=r,r") (const_int 0)) +- (clobber (match_scratch:SI 3 "=&r,&r"))] +- "TARGET_32BIT" +- "@ +- lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0 +- lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0" +- [(set_attr "length" "16,20")]) +- + ;; We can't use the prefixed attribute here because there are two memory + ;; instructions. We can't split the insn due to the fact that this operation + ;; needs to be done in one piece. +-(define_insn "stack_protect_testdi" ++(define_insn "stack_protect_test" + [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") +- (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y") +- (match_operand:DI 2 "memory_operand" "Y,Y")] ++ (unspec:CCEQ [(match_operand:P 1 "memory_operand" "YZ,YZ") ++ (match_operand:P 2 "memory_operand" "YZ,YZ")] + UNSPEC_SP_TEST)) +- (set (match_scratch:DI 4 "=r,r") (const_int 0)) +- (clobber (match_scratch:DI 3 "=&r,&r"))] +- "TARGET_64BIT" ++ (set (match_scratch:P 4 "=r,r") (const_int 0)) ++ (clobber (match_scratch:P 3 "=&r,&r"))] ++ "" + { +- if (prefixed_memory (operands[1], DImode)) +- output_asm_insn ("pld %3,%1", operands); ++ if (prefixed_memory (operands[1], mode)) ++ /* Prefixed load only supports D-form but no update and X-form. */ ++ output_asm_insn ("p %3,%1", operands); + else +- output_asm_insn ("ld%U1%X1 %3,%1", operands); ++ output_asm_insn ("%U1%X1 %3,%1", operands); + +- if (prefixed_memory (operands[2], DImode)) +- output_asm_insn ("pld %4,%2", operands); ++ if (prefixed_memory (operands[2], mode)) ++ output_asm_insn ("p %4,%2", operands); + else +- output_asm_insn ("ld%U2%X2 %4,%2", operands); ++ output_asm_insn ("%U2%X2 %4,%2", operands); + + if (which_alternative == 0) + output_asm_insn ("xor. %3,%3,%4", operands); + else +- output_asm_insn ("cmpld %0,%3,%4\;li %3,0", operands); ++ output_asm_insn ("cmpl %0,%3,%4\;li %3,0", operands); + + return "li %4,0"; + } +diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md +index 068abc1d62e..c45794fb9ed 100644 +--- a/gcc/config/rs6000/vsx.md ++++ b/gcc/config/rs6000/vsx.md +@@ -2018,22 +2018,20 @@ + "xtsqrtp %0,%x1" + [(set_attr "type" "")]) + +-;; Fused vector multiply/add instructions. Support the classical Altivec +-;; versions of fma, which allows the target to be a separate register from the +-;; 3 inputs. Under VSX, the target must be either the addend or the first +-;; multiply. +- ++;; Fused vector multiply/add instructions. Do not generate the Altivec versions ++;; of fma (vmaddfp and vnmsubfp). These instructions allows the target to be a ++;; separate register from the 3 inputs, but they have different rounding ++;; behaviors than the VSX instructions. + (define_insn "*vsx_fmav4sf4" +- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v") ++ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa") + (fma:V4SF +- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v") +- (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v") +- (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))] ++ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa") ++ (match_operand:V4SF 2 "vsx_register_operand" "wa,0") ++ (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))] + "VECTOR_UNIT_VSX_P (V4SFmode)" + "@ + xvmaddasp %x0,%x1,%x2 +- xvmaddmsp %x0,%x1,%x3 +- vmaddfp %0,%1,%2,%3" ++ xvmaddmsp %x0,%x1,%x3" + [(set_attr "type" "vecfloat")]) + + (define_insn "*vsx_fmav2df4" +@@ -2075,18 +2073,17 @@ + [(set_attr "type" "")]) + + (define_insn "*vsx_nfmsv4sf4" +- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v") ++ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa") + (neg:V4SF + (fma:V4SF +- (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v") +- (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v") ++ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa") ++ (match_operand:V4SF 2 "vsx_register_operand" "wa,0") + (neg:V4SF +- (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))] ++ (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))))] + "VECTOR_UNIT_VSX_P (V4SFmode)" + "@ + xvnmsubasp %x0,%x1,%x2 +- xvnmsubmsp %x0,%x1,%x3 +- vnmsubfp %0,%1,%2,%3" ++ xvnmsubmsp %x0,%x1,%x3" + [(set_attr "type" "vecfloat")]) + + (define_insn "*vsx_nfmsv2df4" +@@ -6560,7 +6557,7 @@ + (match_operand:QI 4 "u8bit_cint_operand" "n")] + UNSPEC_XXEVAL))] + "TARGET_POWER10" +- "xxeval %0,%1,%2,%3,%4" ++ "xxeval %x0,%x1,%x2,%x3,%4" + [(set_attr "type" "vecperm") + (set_attr "prefixed" "yes")]) + +diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md +index 59a7b216433..e11e8a5a40d 100644 +--- a/gcc/config/sh/sh.md ++++ b/gcc/config/sh/sh.md +@@ -842,7 +842,7 @@ + if (SUBREG_P (reg)) + reg = SUBREG_REG (reg); + gcc_assert (REG_P (reg)); +- if (find_regno_note (curr_insn, REG_DEAD, REGNO (reg)) != NULL_RTX) ++ if (find_regno_note (curr_insn, REG_DEAD, REGNO (reg)) == NULL_RTX) + FAIL; + + /* FIXME: Maybe also search the predecessor basic blocks to catch +@@ -10680,6 +10680,45 @@ + && peep2_reg_dead_p (2, operands[1]) && peep2_reg_dead_p (3, operands[0])" + [(const_int 0)] + { ++ if (MEM_P (operands[3]) && reg_overlap_mentioned_p (operands[0], operands[3])) ++ { ++ // Take care when the eliminated operand[0] register is part of ++ // the destination memory address. ++ rtx addr = XEXP (operands[3], 0); ++ ++ if (REG_P (addr)) ++ operands[3] = replace_equiv_address (operands[3], operands[1]); ++ ++ else if (GET_CODE (addr) == PLUS && REG_P (XEXP (addr, 0)) ++ && CONST_INT_P (XEXP (addr, 1)) ++ && REGNO (operands[0]) == REGNO (XEXP (addr, 0))) ++ operands[3] = replace_equiv_address (operands[3], ++ gen_rtx_PLUS (SImode, operands[1], XEXP (addr, 1))); ++ ++ else if (GET_CODE (addr) == PLUS && REG_P (XEXP (addr, 0)) ++ && REG_P (XEXP (addr, 1))) ++ { ++ // register + register address @(R0, Rn) ++ // can change only the Rn in the address, not R0. ++ if (REGNO (operands[0]) == REGNO (XEXP (addr, 0)) ++ && REGNO (XEXP (addr, 0)) != 0) ++ { ++ operands[3] = replace_equiv_address (operands[3], ++ gen_rtx_PLUS (SImode, operands[1], XEXP (addr, 1))); ++ } ++ else if (REGNO (operands[0]) == REGNO (XEXP (addr, 1)) ++ && REGNO (XEXP (addr, 1)) != 0) ++ { ++ operands[3] = replace_equiv_address (operands[3], ++ gen_rtx_PLUS (SImode, XEXP (addr, 0), operands[1])); ++ } ++ else ++ FAIL; ++ } ++ else ++ FAIL; ++ } ++ + emit_insn (gen_addsi3 (operands[1], operands[1], operands[2])); + sh_peephole_emit_move_insn (operands[3], operands[1]); + }) +diff --git a/gcc/config/sh/sh_treg_combine.cc b/gcc/config/sh/sh_treg_combine.cc +index f6553c04a0d..685ca542046 100644 +--- a/gcc/config/sh/sh_treg_combine.cc ++++ b/gcc/config/sh/sh_treg_combine.cc +@@ -732,7 +732,14 @@ sh_treg_combine::record_set_of_reg (rtx reg, rtx_insn *start_insn, + } + else if (REG_P (new_entry.cstore.set_src ())) + { +- // If it's a reg-reg copy follow the copied reg. ++ // If it's a reg-reg copy follow the copied reg, but ignore ++ // nop copies of the reg onto itself. ++ if (REGNO (new_entry.cstore.set_src ()) == REGNO (reg)) ++ { ++ i = prev_nonnote_nondebug_insn_bb (i); ++ continue; ++ } ++ + new_entry.cstore_reg_reg_copies.push_back (new_entry.cstore); + reg = new_entry.cstore.set_src (); + i = new_entry.cstore.insn; +diff --git a/gcc/config/vax/vax.cc b/gcc/config/vax/vax.cc +index f44e23d1796..db797dc393a 100644 +--- a/gcc/config/vax/vax.cc ++++ b/gcc/config/vax/vax.cc +@@ -1833,7 +1833,9 @@ nonindexed_address_p (rtx x, bool strict) + } + + /* True if PROD is either a reg times size of mode MODE and MODE is less +- than or equal 8 bytes, or just a reg if MODE is one byte. */ ++ than or equal 8 bytes, or just a reg if MODE is one byte. For a MULT ++ RTX we accept its operands in either order, however ASHIFT is not ++ commutative, so in that case reg has to be the left operand. */ + + static bool + index_term_p (rtx prod, machine_mode mode, bool strict) +@@ -1852,8 +1854,9 @@ index_term_p (rtx prod, machine_mode mode, bool strict) + xfoo0 = XEXP (prod, 0); + xfoo1 = XEXP (prod, 1); + +- if (CONST_INT_P (xfoo0) +- && GET_MODE_SIZE (mode) == (log_p ? 1 << INTVAL (xfoo0) : INTVAL (xfoo0)) ++ if (!log_p ++ && CONST_INT_P (xfoo0) ++ && GET_MODE_SIZE (mode) == INTVAL (xfoo0) + && INDEX_REGISTER_P (xfoo1, strict)) + return true; + +diff --git a/gcc/configure b/gcc/configure +index c749ace011d..b4907d258be 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -27959,6 +27959,49 @@ if test $gcc_cv_as_powerpc_mfcrf = yes; then + + $as_echo "#define HAVE_AS_MFCRF 1" >>confdefs.h + ++fi ++ ++ ++ case $target in ++ *-*-aix*) conftest_s=' .machine "pwr10" ++ .csect .text[PR] ++ tend. 0';; ++ *-*-darwin*) conftest_s=' .text ++ tend. 0';; ++ *) conftest_s=' .machine power10 ++ .text ++ tend. 0';; ++ esac ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for htm support on Power10" >&5 ++$as_echo_n "checking assembler for htm support on Power10... " >&6; } ++if ${gcc_cv_as_power10_htm+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_as_power10_htm=no ++ if test x$gcc_cv_as != x; then ++ $as_echo "$conftest_s" > conftest.s ++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5' ++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } ++ then ++ gcc_cv_as_power10_htm=yes ++ else ++ echo "configure: failed program was" >&5 ++ cat conftest.s >&5 ++ fi ++ rm -f conftest.o conftest.s ++ fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_power10_htm" >&5 ++$as_echo "$gcc_cv_as_power10_htm" >&6; } ++if test $gcc_cv_as_power10_htm = yes; then ++ ++$as_echo "#define HAVE_AS_POWER10_HTM 1" >>confdefs.h ++ + fi + + +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 992a50e7b20..d369c4717b2 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5032,6 +5032,23 @@ gd: + [AC_DEFINE(HAVE_AS_MFCRF, 1, + [Define if your assembler supports mfcr field.])]) + ++ case $target in ++ *-*-aix*) conftest_s=' .machine "pwr10" ++ .csect .text[[PR]] ++ tend. 0';; ++ *-*-darwin*) conftest_s=' .text ++ tend. 0';; ++ *) conftest_s=' .machine power10 ++ .text ++ tend. 0';; ++ esac ++ ++ gcc_GAS_CHECK_FEATURE([htm support on Power10], ++ gcc_cv_as_power10_htm,, ++ [$conftest_s],, ++ [AC_DEFINE(HAVE_AS_POWER10_HTM, 1, ++ [Define if your assembler supports htm insns on power10.])]) ++ + case $target in + *-*-aix*) conftest_s=' .csect .text[[PR]] + LCF..0: +diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog +index 8de4af385a8..bd8c34b7179 100644 +--- a/gcc/cp/ChangeLog ++++ b/gcc/cp/ChangeLog +@@ -1,3 +1,173 @@ ++2023-12-24 Patrick Palka ++ ++ Backported from master: ++ 2023-09-22 Patrick Palka ++ ++ PR c++/111485 ++ * pt.cc (is_compatible_template_arg): New parameter 'args'. ++ Add the outer template arguments 'args' to 'new_args'. ++ (convert_template_argument): Pass 'args' to ++ is_compatible_template_arg. ++ ++2023-12-20 Patrick Palka ++ ++ Backported from master: ++ 2023-04-25 Patrick Palka ++ ++ PR c++/108975 ++ * pt.cc (value_dependent_expression_p) : ++ Suppress conservative early exit for reference variables ++ when DECL_HAS_VALUE_EXPR_P. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-08 Jakub Jelinek ++ ++ PR sanitizer/112727 ++ * cp-gimplify.cc (cp_fold): If SAVE_EXPR has been previously ++ folded, unshare_expr what is returned. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-04 Jakub Jelinek ++ ++ PR c++/112795 ++ * parser.cc (cp_parser_pragma_unroll): Use fold_non_dependent_expr ++ instead of maybe_constant_value. ++ ++2023-11-27 Patrick Palka ++ ++ Backported from master: ++ 2023-11-16 Patrick Palka ++ ++ PR c++/111703 ++ PR c++/107939 ++ * constexpr.cc (potential_constant_expression_1) : ++ Fix FUNCTION_POINTER_TYPE_P test. ++ ++2023-11-27 Patrick Palka ++ ++ Backported from master: ++ 2023-11-15 Patrick Palka ++ ++ PR c++/111703 ++ PR c++/112269 ++ * constexpr.cc (potential_constant_expression_1) : ++ Only consider var_in_maybe_constexpr_fn if 'now' is false. ++ : Likewise. ++ ++2023-11-17 Jason Merrill ++ ++ PR c++/112301 ++ PR c++/102191 ++ PR c++/33799 ++ * except.cc (maybe_splice_retval_cleanup): Clear ++ current_retval_sentinel when destroying retval. ++ * semantics.cc (nrv_data): Add in_nrv_cleanup. ++ (finalize_nrv): Set it. ++ (finalize_nrv_r): Fix handling of throwing cleanups. ++ ++2023-11-17 Jason Merrill ++ ++ * semantics.cc (finalize_nrv_r): [RETURN_EXPR]: Only replace the ++ INIT_EXPR. ++ ++2023-11-17 Jason Merrill ++ ++ PR c++/33799 ++ * except.cc (maybe_splice_retval_cleanup): Change ++ recognition of function body and try scopes. ++ * semantics.cc (do_poplevel): Call it after poplevel. ++ (at_try_scope): New. ++ * cp-tree.h (maybe_splice_retval_cleanup): Adjust. ++ ++2023-08-11 Jason Merrill ++ ++ PR c++/106310 ++ * parser.cc (cp_parser_template_name): Skip non-member ++ lookup after the template keyword. ++ (cp_parser_lookup_name): Pass down template_keyword_p. ++ ++2023-08-11 Jason Merrill ++ ++ PR c++/106890 ++ PR c++/109666 ++ * name-lookup.cc (maybe_push_to_top_level) ++ (maybe_pop_from_top_level): Split out... ++ * pt.cc (instantiate_body): ...from here. ++ * init.cc (maybe_instantiate_nsdmi_init): Use them. ++ * name-lookup.h: Declare them.. ++ ++2023-08-11 Jason Merrill ++ ++ PR c++/108099 ++ * decl.cc (grokdeclarator): Don't clear typedef_decl after 'unsigned ++ typedef' pedwarn. Use c_common_signed_or_unsigned_type. Also ++ handle 'signed typedef'. ++ ++2023-08-07 Patrick Palka ++ ++ Backported from master: ++ 2023-05-09 Patrick Palka ++ ++ PR c++/109761 ++ * parser.cc (cp_parser_class_specifier): Don't pass a class ++ context to noexcept_override_late_checks. ++ (noexcept_override_late_checks): Remove 'type' parameter ++ and use DECL_CONTEXT of 'fndecl' instead. ++ ++2023-07-12 Patrick Palka ++ ++ Backported from master: ++ 2023-06-29 Patrick Palka ++ ++ PR c++/110468 ++ * init.cc (maybe_instantiate_nsdmi_init): Mask out all ++ tsubst flags except for tf_warning_or_error. ++ ++2023-05-17 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-17 Jakub Jelinek ++ ++ PR c++/109868 ++ * init.cc (build_zero_init_1): Don't initialize zero-width bitfields. ++ For unions only initialize the first FIELD_DECL. ++ ++2023-05-15 Jason Merrill ++ ++ PR c++/109241 ++ * pt.cc (find_parameter_packs_r): Handle null TREE_BINFO. ++ ++2023-05-09 Patrick Palka ++ ++ Backported from master: ++ 2023-04-01 Patrick Palka ++ ++ PR c++/109160 ++ * cp-tree.h (do_auto_deduction): Add defaulted tmpl parameter. ++ * pt.cc (convert_template_argument): Pass 'in_decl' as 'tmpl' to ++ do_auto_deduction. ++ (tsubst_decl) : Pass 'tmpl' instead of 't' as ++ 'in_decl' to coerce_template_parms. ++ (unify) : Pass TPARMS_PRIMARY_TEMPLATE ++ as 'tmpl' to do_auto_deduction. ++ (do_auto_deduction): Document default arguments. Rename local ++ variable 'tmpl' to 'ctmpl'. Use 'tmpl' to obtain a full set of ++ template arguments for satisfaction in the adc_unify case. ++ ++2023-05-09 Jason Merrill ++ ++ PR c++/106740 ++ PR c++/105852 ++ * decl.cc (duplicate_decls): Change non-templated friend ++ check to an assert. ++ * pt.cc (tsubst_function_decl): Don't set DECL_TEMPLATE_INFO ++ on non-templated friends. ++ (tsubst_friend_function): Adjust. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc +index 46b2b0296c3..d2d02c282cd 100644 +--- a/gcc/cp/constexpr.cc ++++ b/gcc/cp/constexpr.cc +@@ -8777,7 +8777,12 @@ potential_constant_expression_1 (tree t, bool want_rval, bool strict, bool now, + } + else if (fun) + { +- if (RECUR (fun, FUNCTION_POINTER_TYPE_P (fun) ? rval : any)) ++ if (TREE_TYPE (fun) ++ && FUNCTION_POINTER_TYPE_P (TREE_TYPE (fun))) ++ want_rval = rval; ++ else ++ want_rval = any; ++ if (RECUR (fun, want_rval)) + /* Might end up being a constant function pointer. But it + could also be a function object with constexpr op(), so + we pass 'any' so that the underlying VAR_DECL is deemed +@@ -8847,7 +8852,7 @@ potential_constant_expression_1 (tree t, bool want_rval, bool strict, bool now, + return RECUR (DECL_VALUE_EXPR (t), rval); + } + if (want_rval +- && !var_in_maybe_constexpr_fn (t) ++ && (now || !var_in_maybe_constexpr_fn (t)) + && !type_dependent_expression_p (t) + && !decl_maybe_constant_var_p (t) + && (strict +@@ -8956,7 +8961,7 @@ potential_constant_expression_1 (tree t, bool want_rval, bool strict, bool now, + STRIP_NOPS (x); + if (is_this_parameter (x) && !is_capture_proxy (x)) + { +- if (!var_in_maybe_constexpr_fn (x)) ++ if (now || !var_in_maybe_constexpr_fn (x)) + { + if (flags & tf_error) + error_at (loc, "use of % in a constant expression"); +diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc +index 07620b4e01b..7ae5327f693 100644 +--- a/gcc/cp/cp-gimplify.cc ++++ b/gcc/cp/cp-gimplify.cc +@@ -2453,7 +2453,14 @@ cp_fold (tree x) + fold_cache = hash_map::create_ggc (101); + + if (tree *cached = fold_cache->get (x)) +- return *cached; ++ { ++ /* unshare_expr doesn't recurse into SAVE_EXPRs. If SAVE_EXPR's ++ argument has been folded into a tree invariant, make sure it is ++ unshared. See PR112727. */ ++ if (TREE_CODE (x) == SAVE_EXPR && *cached != x) ++ return unshare_expr (*cached); ++ return *cached; ++ } + + uid_sensitive_constexpr_evaluation_checker c; + +diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h +index 64b3196d1e9..5b3836422d6 100644 +--- a/gcc/cp/cp-tree.h ++++ b/gcc/cp/cp-tree.h +@@ -7014,7 +7014,7 @@ extern tree begin_eh_spec_block (void); + extern void finish_eh_spec_block (tree, tree); + extern tree build_eh_type_type (tree); + extern tree cp_protect_cleanup_actions (void); +-extern void maybe_splice_retval_cleanup (tree); ++extern void maybe_splice_retval_cleanup (tree, bool); + extern tree maybe_set_retval_sentinel (void); + + extern tree template_parms_to_args (tree); +@@ -7295,7 +7295,8 @@ extern tree do_auto_deduction (tree, tree, tree, + auto_deduction_context + = adc_unspecified, + tree = NULL_TREE, +- int = LOOKUP_NORMAL); ++ int = LOOKUP_NORMAL, ++ tree = NULL_TREE); + extern tree type_uses_auto (tree); + extern tree type_uses_auto_or_concept (tree); + extern void append_type_to_template_for_access_check (tree, tree, tree, +diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc +index ab9a009fb7e..22060b11176 100644 +--- a/gcc/cp/decl.cc ++++ b/gcc/cp/decl.cc +@@ -2666,10 +2666,11 @@ duplicate_decls (tree newdecl, tree olddecl, bool hiding, bool was_hidden) + = TINFO_USED_TEMPLATE_ID (new_template_info); + } + +- if (non_templated_friend_p (olddecl)) +- /* Don't copy tinfo from a non-templated friend (PR105761). */; +- else +- DECL_TEMPLATE_INFO (newdecl) = DECL_TEMPLATE_INFO (olddecl); ++ /* We don't want to copy template info from a non-templated friend ++ (PR105761), but these shouldn't have DECL_TEMPLATE_INFO now. */ ++ gcc_checking_assert (!DECL_TEMPLATE_INFO (olddecl) ++ || !non_templated_friend_p (olddecl)); ++ DECL_TEMPLATE_INFO (newdecl) = DECL_TEMPLATE_INFO (olddecl); + } + + if (DECL_DECLARES_FUNCTION_P (newdecl)) +@@ -12300,11 +12301,14 @@ grokdeclarator (const cp_declarator *declarator, + { + if (typedef_decl) + { +- pedwarn (loc, OPT_Wpedantic, "%qs specified with %qT", +- key, type); ++ pedwarn (loc, OPT_Wpedantic, ++ "%qs specified with typedef-name %qD", ++ key, typedef_decl); + ok = !flag_pedantic_errors; +- type = DECL_ORIGINAL_TYPE (typedef_decl); +- typedef_decl = NULL_TREE; ++ /* PR108099: __int128_t comes from c_common_nodes_and_builtins, ++ and is not built as a typedef. */ ++ if (is_typedef_decl (typedef_decl)) ++ type = DECL_ORIGINAL_TYPE (typedef_decl); + } + else if (declspecs->decltype_p) + error_at (loc, "%qs specified with %", key); +@@ -12357,7 +12361,7 @@ grokdeclarator (const cp_declarator *declarator, + else if (type == char_type_node) + type = unsigned_char_type_node; + else if (typedef_decl) +- type = unsigned_type_for (type); ++ type = c_common_unsigned_type (type); + else + type = unsigned_type_node; + } +@@ -12371,6 +12375,8 @@ grokdeclarator (const cp_declarator *declarator, + type = long_integer_type_node; + else if (short_p) + type = short_integer_type_node; ++ else if (signed_p && typedef_decl) ++ type = c_common_signed_type (type); + + if (decl_spec_seq_has_spec_p (declspecs, ds_complex)) + { +diff --git a/gcc/cp/except.cc b/gcc/cp/except.cc +index 58d8772fc95..b9f49d1bfc6 100644 +--- a/gcc/cp/except.cc ++++ b/gcc/cp/except.cc +@@ -1318,21 +1318,20 @@ maybe_set_retval_sentinel () + on throw. */ + + void +-maybe_splice_retval_cleanup (tree compound_stmt) ++maybe_splice_retval_cleanup (tree compound_stmt, bool is_try) + { +- /* If we need a cleanup for the return value, add it in at the same level as ++ if (!current_function_decl || !cfun ++ || DECL_CONSTRUCTOR_P (current_function_decl) ++ || DECL_DESTRUCTOR_P (current_function_decl) ++ || !current_retval_sentinel) ++ return; ++ ++ /* if we need a cleanup for the return value, add it in at the same level as + pushdecl_outermost_localscope. And also in try blocks. */ +- const bool function_body +- = (current_binding_level->level_chain +- && current_binding_level->level_chain->kind == sk_function_parms +- /* When we're processing a default argument, c_f_d may not have been +- set. */ +- && current_function_decl); +- +- if ((function_body || current_binding_level->kind == sk_try) +- && !DECL_CONSTRUCTOR_P (current_function_decl) +- && !DECL_DESTRUCTOR_P (current_function_decl) +- && current_retval_sentinel) ++ cp_binding_level *b = current_binding_level; ++ const bool function_body = b->kind == sk_function_parms; ++ ++ if (function_body || is_try) + { + location_t loc = DECL_SOURCE_LOCATION (current_function_decl); + tree_stmt_iterator iter = tsi_start (compound_stmt); +@@ -1358,6 +1357,14 @@ maybe_splice_retval_cleanup (tree compound_stmt) + tsi_delink (&iter); + } + tree dtor = build_cleanup (retval); ++ if (!function_body) ++ { ++ /* Clear the sentinel so we don't try to destroy the retval again on ++ rethrow (c++/112301). */ ++ tree clear = build2 (MODIFY_EXPR, boolean_type_node, ++ current_retval_sentinel, boolean_false_node); ++ dtor = build2 (COMPOUND_EXPR, void_type_node, clear, dtor); ++ } + tree cond = build3 (COND_EXPR, void_type_node, current_retval_sentinel, + dtor, void_node); + tree cleanup = build_stmt (loc, CLEANUP_STMT, +diff --git a/gcc/cp/init.cc b/gcc/cp/init.cc +index 75dbfe112b5..202e820d8b2 100644 +--- a/gcc/cp/init.cc ++++ b/gcc/cp/init.cc +@@ -189,15 +189,21 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p, + init = build_zero_cst (type); + else if (RECORD_OR_UNION_CODE_P (TREE_CODE (type))) + { +- tree field; ++ tree field, next; + vec *v = NULL; + + /* Iterate over the fields, building initializations. */ +- for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) ++ for (field = TYPE_FIELDS (type); field; field = next) + { ++ next = DECL_CHAIN (field); ++ + if (TREE_CODE (field) != FIELD_DECL) + continue; + ++ /* For unions, only the first field is initialized. */ ++ if (TREE_CODE (type) == UNION_TYPE) ++ next = NULL_TREE; ++ + if (TREE_TYPE (field) == error_mark_node) + continue; + +@@ -212,6 +218,11 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p, + continue; + } + ++ /* Don't add zero width bitfields. */ ++ if (DECL_C_BIT_FIELD (field) ++ && integer_zerop (DECL_SIZE (field))) ++ continue; ++ + /* Note that for class types there will be FIELD_DECLs + corresponding to base classes as well. Thus, iterating + over TYPE_FIELDs will result in correct initialization of +@@ -230,10 +241,6 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p, + if (value) + CONSTRUCTOR_APPEND_ELT(v, field, value); + } +- +- /* For unions, only the first field is initialized. */ +- if (TREE_CODE (type) == UNION_TYPE) +- break; + } + + /* Build a constructor to contain the initializations. */ +@@ -572,6 +579,10 @@ maybe_instantiate_nsdmi_init (tree member, tsubst_flags_t complain) + tree init = DECL_INITIAL (member); + if (init && DECL_LANG_SPECIFIC (member) && DECL_TEMPLATE_INFO (member)) + { ++ /* Clear any special tsubst flags; the result of NSDMI instantiation ++ should be independent of the substitution context. */ ++ complain &= tf_warning_or_error; ++ + init = DECL_INITIAL (DECL_TI_TEMPLATE (member)); + location_t expr_loc + = cp_expr_loc_or_loc (init, DECL_SOURCE_LOCATION (member)); +@@ -599,15 +610,9 @@ maybe_instantiate_nsdmi_init (tree member, tsubst_flags_t complain) + bool pushed = false; + tree ctx = DECL_CONTEXT (member); + +- processing_template_decl_sentinel ptds (/*reset*/false); ++ bool push_to_top = maybe_push_to_top_level (member); + if (!currently_open_class (ctx)) + { +- if (!LOCAL_CLASS_P (ctx)) +- push_to_top_level (); +- else +- /* push_to_top_level would lose the necessary function context, +- just reset processing_template_decl. */ +- processing_template_decl = 0; + push_nested_class (ctx); + push_deferring_access_checks (dk_no_deferred); + pushed = true; +@@ -635,9 +640,8 @@ maybe_instantiate_nsdmi_init (tree member, tsubst_flags_t complain) + { + pop_deferring_access_checks (); + pop_nested_class (); +- if (!LOCAL_CLASS_P (ctx)) +- pop_from_top_level (); + } ++ maybe_pop_from_top_level (push_to_top); + + input_location = sloc; + } +diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc +index 56256babda8..48c7badc865 100644 +--- a/gcc/cp/name-lookup.cc ++++ b/gcc/cp/name-lookup.cc +@@ -8451,6 +8451,43 @@ pop_from_top_level (void) + free_saved_scope = s; + } + ++/* Like push_to_top_level, but not if D is function-local. Returns whether we ++ did push to top. */ ++ ++bool ++maybe_push_to_top_level (tree d) ++{ ++ /* Push if D isn't function-local, or is a lambda function, for which name ++ resolution is already done. */ ++ bool push_to_top ++ = !(current_function_decl ++ && !LAMBDA_FUNCTION_P (d) ++ && decl_function_context (d) == current_function_decl); ++ ++ if (push_to_top) ++ push_to_top_level (); ++ else ++ { ++ gcc_assert (!processing_template_decl); ++ push_function_context (); ++ cp_unevaluated_operand = 0; ++ c_inhibit_evaluation_warnings = 0; ++ } ++ ++ return push_to_top; ++} ++ ++/* Return from whatever maybe_push_to_top_level did. */ ++ ++void ++maybe_pop_from_top_level (bool push_to_top) ++{ ++ if (push_to_top) ++ pop_from_top_level (); ++ else ++ pop_function_context (); ++} ++ + /* Push into the scope of the namespace NS, even if it is deeply + nested within another namespace. */ + +diff --git a/gcc/cp/name-lookup.h b/gcc/cp/name-lookup.h +index fa039028847..7336df76741 100644 +--- a/gcc/cp/name-lookup.h ++++ b/gcc/cp/name-lookup.h +@@ -468,6 +468,8 @@ extern void push_nested_namespace (tree); + extern void pop_nested_namespace (tree); + extern void push_to_top_level (void); + extern void pop_from_top_level (void); ++extern bool maybe_push_to_top_level (tree); ++extern void maybe_pop_from_top_level (bool); + extern void push_using_decl_bindings (tree, tree); + + /* Lower level interface for modules. */ +diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc +index d2c3fc1d0b9..194f9b07d83 100644 +--- a/gcc/cp/parser.cc ++++ b/gcc/cp/parser.cc +@@ -249,7 +249,7 @@ static cp_token_cache *cp_token_cache_new + static tree cp_parser_late_noexcept_specifier + (cp_parser *, tree); + static void noexcept_override_late_checks +- (tree, tree); ++ (tree); + + static void cp_parser_initial_pragma + (cp_token *); +@@ -2660,7 +2660,7 @@ static tree cp_parser_objc_struct_declaration + /* Utility Routines */ + + static cp_expr cp_parser_lookup_name +- (cp_parser *, tree, enum tag_types, bool, bool, bool, tree *, location_t); ++ (cp_parser *, tree, enum tag_types, int, bool, bool, tree *, location_t); + static tree cp_parser_lookup_name_simple + (cp_parser *, tree, location_t); + static tree cp_parser_maybe_treat_template_as_class +@@ -18590,7 +18590,7 @@ cp_parser_template_name (cp_parser* parser, + /* Look up the name. */ + decl = cp_parser_lookup_name (parser, identifier, + tag_type, +- /*is_template=*/true, ++ /*is_template=*/1 + template_keyword_p, + /*is_namespace=*/false, + check_dependency_p, + /*ambiguous_decls=*/NULL, +@@ -26151,7 +26151,7 @@ cp_parser_class_specifier_1 (cp_parser* parser) + /* The finish_struct call above performed various override checking, + but it skipped unparsed noexcept-specifier operands. Now that we + have resolved them, check again. */ +- noexcept_override_late_checks (type, decl); ++ noexcept_override_late_checks (decl); + + /* Remove any member-function parameters from the symbol table. */ + pop_injected_parms (); +@@ -27876,14 +27876,13 @@ cp_parser_late_noexcept_specifier (cp_parser *parser, tree default_arg) + } + + /* Perform late checking of overriding function with respect to their +- noexcept-specifiers. TYPE is the class and FNDECL is the function +- that potentially overrides some virtual function with the same +- signature. */ ++ noexcept-specifiers. FNDECL is the member function that potentially ++ overrides some virtual function with the same signature. */ + + static void +-noexcept_override_late_checks (tree type, tree fndecl) ++noexcept_override_late_checks (tree fndecl) + { +- tree binfo = TYPE_BINFO (type); ++ tree binfo = TYPE_BINFO (DECL_CONTEXT (fndecl)); + tree base_binfo; + + if (DECL_STATIC_FUNCTION_P (fndecl)) +@@ -30389,7 +30388,7 @@ prefer_type_arg (tag_types tag_type) + refer to types are ignored. + + If IS_TEMPLATE is TRUE, bindings that do not refer to templates are +- ignored. ++ ignored. If IS_TEMPLATE IS 2, the 'template' keyword was specified. + + If IS_NAMESPACE is TRUE, bindings that do not refer to namespaces + are ignored. +@@ -30404,7 +30403,7 @@ prefer_type_arg (tag_types tag_type) + static cp_expr + cp_parser_lookup_name (cp_parser *parser, tree name, + enum tag_types tag_type, +- bool is_template, ++ int is_template, + bool is_namespace, + bool check_dependency, + tree *ambiguous_decls, +@@ -30589,7 +30588,14 @@ cp_parser_lookup_name (cp_parser *parser, tree name, + else + decl = NULL_TREE; + +- if (!decl) ++ /* If we didn't find a member and have dependent bases, the member lookup ++ is now dependent. */ ++ if (!dep && !decl && any_dependent_bases_p (object_type)) ++ dep = true; ++ ++ if (dep && is_template == 2) ++ /* The template keyword specifies a dependent template. */; ++ else if (!decl) + /* Look it up in the enclosing context. DR 141: When looking for a + template-name after -> or ., only consider class templates. */ + decl = lookup_name (name, is_namespace ? LOOK_want::NAMESPACE +@@ -30602,8 +30608,7 @@ cp_parser_lookup_name (cp_parser *parser, tree name, + + /* If we know we're looking for a type (e.g. A in p->A::x), + mock up a typename. */ +- if (!decl && object_type && tag_type != none_type +- && dependentish_scope_p (object_type)) ++ if (!decl && dep && tag_type != none_type) + { + tree type = build_typename_type (object_type, name, name, + typename_type); +@@ -47664,7 +47669,7 @@ cp_parser_pragma_unroll (cp_parser *parser, cp_token *pragma_tok) + location_t location = cp_lexer_peek_token (parser->lexer)->location; + tree expr = cp_parser_constant_expression (parser); + unsigned short unroll; +- expr = maybe_constant_value (expr); ++ expr = fold_non_dependent_expr (expr); + HOST_WIDE_INT lunroll = 0; + if (!INTEGRAL_TYPE_P (TREE_TYPE (expr)) + || TREE_CODE (expr) != INTEGER_CST +diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc +index b5fabe4341e..dc8121e1b4b 100644 +--- a/gcc/cp/pt.cc ++++ b/gcc/cp/pt.cc +@@ -4106,10 +4106,14 @@ find_parameter_packs_r (tree *tp, int *walk_subtrees, void* data) + case TAG_DEFN: + t = TREE_TYPE (t); + if (CLASS_TYPE_P (t)) +- /* Local class, need to look through the whole definition. */ +- for (tree bb : BINFO_BASE_BINFOS (TYPE_BINFO (t))) +- cp_walk_tree (&BINFO_TYPE (bb), &find_parameter_packs_r, +- ppd, ppd->visited); ++ { ++ /* Local class, need to look through the whole definition. ++ TYPE_BINFO might be unset for a partial instantiation. */ ++ if (TYPE_BINFO (t)) ++ for (tree bb : BINFO_BASE_BINFOS (TYPE_BINFO (t))) ++ cp_walk_tree (&BINFO_TYPE (bb), &find_parameter_packs_r, ++ ppd, ppd->visited); ++ } + else + /* Enum, look at the values. */ + for (tree l = TYPE_VALUES (t); l; l = TREE_CHAIN (l)) +@@ -8322,7 +8326,7 @@ canonicalize_expr_argument (tree arg, tsubst_flags_t complain) + constrained than the parameter. */ + + static bool +-is_compatible_template_arg (tree parm, tree arg) ++is_compatible_template_arg (tree parm, tree arg, tree args) + { + tree parm_cons = get_constraints (parm); + +@@ -8343,6 +8347,7 @@ is_compatible_template_arg (tree parm, tree arg) + { + tree aparms = DECL_INNERMOST_TEMPLATE_PARMS (arg); + new_args = template_parms_level_to_args (aparms); ++ new_args = add_to_template_args (args, new_args); + ++processing_template_decl; + parm_cons = tsubst_constraint_info (parm_cons, new_args, + tf_none, NULL_TREE); +@@ -8601,7 +8606,7 @@ convert_template_argument (tree parm, + // Check that the constraints are compatible before allowing the + // substitution. + if (val != error_mark_node) +- if (!is_compatible_template_arg (parm, arg)) ++ if (!is_compatible_template_arg (parm, arg, args)) + { + if (in_decl && (complain & tf_error)) + { +@@ -8636,7 +8641,7 @@ convert_template_argument (tree parm, + else if (tree a = type_uses_auto (t)) + { + t = do_auto_deduction (t, arg, a, complain, adc_unify, args, +- LOOKUP_IMPLICIT); ++ LOOKUP_IMPLICIT, /*tmpl=*/in_decl); + if (t == error_mark_node) + return error_mark_node; + } +@@ -11339,9 +11344,10 @@ tsubst_friend_function (tree decl, tree args) + tree new_friend_template_info = DECL_TEMPLATE_INFO (new_friend); + tree new_friend_result_template_info = NULL_TREE; + bool new_friend_is_defn = +- (DECL_INITIAL (DECL_TEMPLATE_RESULT +- (template_for_substitution (new_friend))) +- != NULL_TREE); ++ (new_friend_template_info ++ && (DECL_INITIAL (DECL_TEMPLATE_RESULT ++ (template_for_substitution (new_friend))) ++ != NULL_TREE)); + tree not_tmpl = new_friend; + + if (TREE_CODE (new_friend) == TEMPLATE_DECL) +@@ -14175,6 +14181,10 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain, + && !LAMBDA_FUNCTION_P (t)) + return t; + ++ /* A non-templated friend doesn't get DECL_TEMPLATE_INFO. */ ++ if (non_templated_friend_p (t)) ++ goto friend_case; ++ + /* Calculate the most general template of which R is a + specialization. */ + gen_tmpl = most_general_template (DECL_TI_TEMPLATE (t)); +@@ -14220,6 +14230,7 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain, + tsubst_friend_function, and we want only to create a + new decl (R) with appropriate types so that we can call + determine_specialization. */ ++ friend_case: + gen_tmpl = NULL_TREE; + argvec = NULL_TREE; + } +@@ -14415,7 +14426,7 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain, + /* If this is an instantiation of a member template, clone it. + If it isn't, that'll be handled by + clone_constructors_and_destructors. */ +- if (PRIMARY_TEMPLATE_P (gen_tmpl)) ++ if (gen_tmpl && PRIMARY_TEMPLATE_P (gen_tmpl)) + clone_cdtor (r, /*update_methods=*/false); + } + else if ((complain & tf_error) != 0 +@@ -15022,7 +15033,7 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain) + if (argvec != error_mark_node) + argvec = (coerce_innermost_template_parms + (DECL_TEMPLATE_PARMS (gen_tmpl), +- argvec, t, complain, ++ argvec, tmpl, complain, + /*all*/true, /*defarg*/true)); + if (argvec == error_mark_node) + RETURN (error_mark_node); +@@ -24449,7 +24460,9 @@ unify (tree tparms, tree targs, tree parm, tree arg, int strict, + if (tree a = type_uses_auto (tparm)) + { + tparm = do_auto_deduction (tparm, arg, a, +- complain, adc_unify, targs); ++ complain, adc_unify, targs, ++ LOOKUP_NORMAL, ++ TPARMS_PRIMARY_TEMPLATE (tparms)); + if (tparm == error_mark_node) + return 1; + } +@@ -26493,20 +26506,7 @@ instantiate_body (tree pattern, tree args, tree d, bool nested_p) + if (current_function_decl) + save_omp_privatization_clauses (omp_privatization_save); + +- bool push_to_top +- = !(current_function_decl +- && !LAMBDA_FUNCTION_P (d) +- && decl_function_context (d) == current_function_decl); +- +- if (push_to_top) +- push_to_top_level (); +- else +- { +- gcc_assert (!processing_template_decl); +- push_function_context (); +- cp_unevaluated_operand = 0; +- c_inhibit_evaluation_warnings = 0; +- } ++ bool push_to_top = maybe_push_to_top_level (d); + + if (VAR_P (d)) + { +@@ -26619,10 +26619,7 @@ instantiate_body (tree pattern, tree args, tree d, bool nested_p) + if (!nested_p) + TI_PENDING_TEMPLATE_FLAG (DECL_TEMPLATE_INFO (d)) = 0; + +- if (push_to_top) +- pop_from_top_level (); +- else +- pop_function_context (); ++ maybe_pop_from_top_level (push_to_top); + + if (current_function_decl) + restore_omp_privatization_clauses (omp_privatization_save); +@@ -27644,9 +27641,7 @@ value_dependent_expression_p (tree expression) + case VAR_DECL: + /* A constant with literal type and is initialized + with an expression that is value-dependent. */ +- if (DECL_DEPENDENT_INIT_P (expression) +- /* FIXME cp_finish_decl doesn't fold reference initializers. */ +- || TYPE_REF_P (TREE_TYPE (expression))) ++ if (DECL_DEPENDENT_INIT_P (expression)) + return true; + if (DECL_HAS_VALUE_EXPR_P (expression)) + { +@@ -27661,6 +27656,9 @@ value_dependent_expression_p (tree expression) + && value_expr == error_mark_node)) + return true; + } ++ else if (TYPE_REF_P (TREE_TYPE (expression))) ++ /* FIXME cp_finish_decl doesn't fold reference initializers. */ ++ return true; + return false; + + case DYNAMIC_CAST_EXPR: +@@ -30334,13 +30332,20 @@ do_class_deduction (tree ptype, tree tmpl, tree init, + adc_requirement contexts to communicate the necessary template arguments + to satisfaction. OUTER_TARGS is ignored in other contexts. + +- For partial-concept-ids, extra args may be appended to the list of deduced +- template arguments prior to determining constraint satisfaction. */ ++ Additionally for adc_unify contexts TMPL is the template for which TYPE ++ is a template parameter type. ++ ++ For partial-concept-ids, extra args from OUTER_TARGS, TMPL and the current ++ scope may be appended to the list of deduced template arguments prior to ++ determining constraint satisfaction as appropriate. */ + + tree + do_auto_deduction (tree type, tree init, tree auto_node, +- tsubst_flags_t complain, auto_deduction_context context, +- tree outer_targs, int flags) ++ tsubst_flags_t complain /* = tf_warning_or_error */, ++ auto_deduction_context context /* = adc_unspecified */, ++ tree outer_targs /* = NULL_TREE */, ++ int flags /* = LOOKUP_NORMAL */, ++ tree tmpl /* = NULL_TREE */) + { + if (init == error_mark_node) + return error_mark_node; +@@ -30359,9 +30364,9 @@ do_auto_deduction (tree type, tree init, tree auto_node, + auto_node. */ + complain &= ~tf_partial; + +- if (tree tmpl = CLASS_PLACEHOLDER_TEMPLATE (auto_node)) ++ if (tree ctmpl = CLASS_PLACEHOLDER_TEMPLATE (auto_node)) + /* C++17 class template argument deduction. */ +- return do_class_deduction (type, tmpl, init, flags, complain); ++ return do_class_deduction (type, ctmpl, init, flags, complain); + + if (init == NULL_TREE || TREE_TYPE (init) == NULL_TREE) + /* Nothing we can do with this, even in deduction context. */ +@@ -30521,7 +30526,10 @@ do_auto_deduction (tree type, tree init, tree auto_node, + } + } + +- tree full_targs = add_to_template_args (outer_targs, targs); ++ tree full_targs = outer_targs; ++ if (context == adc_unify && tmpl) ++ full_targs = add_outermost_template_args (tmpl, full_targs); ++ full_targs = add_to_template_args (full_targs, targs); + + /* HACK: Compensate for callers not always communicating all levels of + outer template arguments by filling in the outermost missing levels +diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc +index ee0db331f34..c42402c7c14 100644 +--- a/gcc/cp/semantics.cc ++++ b/gcc/cp/semantics.cc +@@ -627,6 +627,17 @@ set_cleanup_locs (tree stmts, location_t loc) + set_cleanup_locs (stmt, loc); + } + ++/* True iff the innermost block scope is a try block. */ ++ ++static bool ++at_try_scope () ++{ ++ cp_binding_level *b = current_binding_level; ++ while (b && b->kind == sk_cleanup) ++ b = b->level_chain; ++ return b && b->kind == sk_try; ++} ++ + /* Finish a scope. */ + + tree +@@ -634,11 +645,14 @@ do_poplevel (tree stmt_list) + { + tree block = NULL; + +- maybe_splice_retval_cleanup (stmt_list); ++ bool was_try = at_try_scope (); + + if (stmts_are_full_exprs_p ()) + block = poplevel (kept_level_p (), 1, 0); + ++ /* This needs to come after poplevel merges sk_cleanup statement_lists. */ ++ maybe_splice_retval_cleanup (stmt_list, was_try); ++ + stmt_list = pop_stmt_list (stmt_list); + + /* input_location is the last token of the scope, usually a }. */ +@@ -4829,6 +4843,7 @@ public: + tree var; + tree result; + hash_table > visited; ++ bool in_nrv_cleanup; + }; + + /* Helper function for walk_tree, used by finalize_nrv below. */ +@@ -4845,14 +4860,50 @@ finalize_nrv_r (tree* tp, int* walk_subtrees, void* data) + *walk_subtrees = 0; + /* Change all returns to just refer to the RESULT_DECL; this is a nop, + but differs from using NULL_TREE in that it indicates that we care +- about the value of the RESULT_DECL. */ ++ about the value of the RESULT_DECL. But preserve anything appended ++ by check_return_expr. */ + else if (TREE_CODE (*tp) == RETURN_EXPR) +- TREE_OPERAND (*tp, 0) = dp->result; ++ { ++ tree *p = &TREE_OPERAND (*tp, 0); ++ while (TREE_CODE (*p) == COMPOUND_EXPR) ++ p = &TREE_OPERAND (*p, 0); ++ gcc_checking_assert (TREE_CODE (*p) == INIT_EXPR ++ && TREE_OPERAND (*p, 0) == dp->result); ++ *p = dp->result; ++ } + /* Change all cleanups for the NRV to only run when an exception is + thrown. */ + else if (TREE_CODE (*tp) == CLEANUP_STMT + && CLEANUP_DECL (*tp) == dp->var) +- CLEANUP_EH_ONLY (*tp) = 1; ++ { ++ dp->in_nrv_cleanup = true; ++ cp_walk_tree (&CLEANUP_BODY (*tp), finalize_nrv_r, data, 0); ++ dp->in_nrv_cleanup = false; ++ cp_walk_tree (&CLEANUP_EXPR (*tp), finalize_nrv_r, data, 0); ++ *walk_subtrees = 0; ++ ++ CLEANUP_EH_ONLY (*tp) = true; ++ ++ /* If a cleanup might throw, we need to clear current_retval_sentinel on ++ the exception path so an outer cleanup added by ++ maybe_splice_retval_cleanup doesn't run. */ ++ if (cp_function_chain->throwing_cleanup) ++ { ++ tree clear = build2 (MODIFY_EXPR, boolean_type_node, ++ current_retval_sentinel, ++ boolean_false_node); ++ ++ /* We're already only on the EH path, just prepend it. */ ++ tree &exp = CLEANUP_EXPR (*tp); ++ exp = build2 (COMPOUND_EXPR, void_type_node, clear, exp); ++ } ++ } ++ /* Disable maybe_splice_retval_cleanup within the NRV cleanup scope, we don't ++ want to destroy the retval before the variable goes out of scope. */ ++ else if (TREE_CODE (*tp) == CLEANUP_STMT ++ && dp->in_nrv_cleanup ++ && CLEANUP_DECL (*tp) == dp->result) ++ CLEANUP_EXPR (*tp) = void_node; + /* Replace the DECL_EXPR for the NRV with an initialization of the + RESULT_DECL, if needed. */ + else if (TREE_CODE (*tp) == DECL_EXPR +@@ -4908,6 +4959,7 @@ finalize_nrv (tree *tp, tree var, tree result) + + data.var = var; + data.result = result; ++ data.in_nrv_cleanup = false; + cp_walk_tree (tp, finalize_nrv_r, &data, 0); + } + +diff --git a/gcc/cprop.cc b/gcc/cprop.cc +index 2a99553a5a5..f049e6df857 100644 +--- a/gcc/cprop.cc ++++ b/gcc/cprop.cc +@@ -22,6 +22,7 @@ along with GCC; see the file COPYING3. If not see + #include "coretypes.h" + #include "backend.h" + #include "rtl.h" ++#include "rtlanal.h" + #include "cfghooks.h" + #include "df.h" + #include "insn-config.h" +@@ -795,7 +796,8 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + /* If we've failed perform the replacement, have a single SET to + a REG destination and don't yet have a note, add a REG_EQUAL note + to not lose information. */ +- if (!success && note == 0 && set != 0 && REG_P (SET_DEST (set))) ++ if (!success && note == 0 && set != 0 && REG_P (SET_DEST (set)) ++ && !contains_paradoxical_subreg_p (SET_SRC (set))) + note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); + } + +diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog +index 4218c9aec47..09a22fac30f 100644 +--- a/gcc/d/ChangeLog ++++ b/gcc/d/ChangeLog +@@ -1,3 +1,117 @@ ++2023-10-29 Iain Buclaw ++ ++ Backported from master: ++ 2023-10-29 Iain Buclaw ++ ++ PR d/110712 ++ * d-codegen.cc (d_build_call): Update call to convert_for_argument. ++ * d-convert.cc (is_valist_parameter_type): New function. ++ (check_valist_conversion): New function. ++ (convert_for_assignment): Update signature. Add check whether ++ assigning va_list is permissible. ++ (convert_for_argument): Likewise. ++ * d-tree.h (convert_for_assignment): Update signature. ++ (convert_for_argument): Likewise. ++ * expr.cc (ExprVisitor::visit (AssignExp *)): Update call to ++ convert_for_assignment. ++ ++2023-10-28 Iain Buclaw ++ ++ Backported from master: ++ 2023-10-28 Iain Buclaw ++ ++ PR d/112270 ++ * d-builtins.cc (d_build_d_type_nodes): Initialize d_bool_false_node, ++ d_bool_true_node. ++ * d-codegen.cc (build_array_struct_comparison): Use d_bool_false_node ++ instead of boolean_false_node. ++ * d-convert.cc (d_truthvalue_conversion): Use d_bool_false_node and ++ d_bool_true_node instead of boolean_false_node and boolean_true_node. ++ * d-tree.h (enum d_tree_index): Add DTI_BOOL_FALSE and DTI_BOOL_TRUE. ++ (d_bool_false_node): New macro. ++ (d_bool_true_node): New macro. ++ * modules.cc (build_dso_cdtor_fn): Use d_bool_false_node and ++ d_bool_true_node instead of boolean_false_node and boolean_true_node. ++ (register_moduleinfo): Use d_bool_type instead of boolean_type_node. ++ ++2023-08-15 Iain Buclaw ++ ++ PR d/110959 ++ * dmd/canthrow.d (Dsymbol_canThrow): Use foreachVar. ++ * dmd/declaration.d (TupleDeclaration::needThis): Likewise. ++ (TupleDeclaration::foreachVar): New function. ++ (VarDeclaration::setFieldOffset): Use foreachVar. ++ * dmd/dinterpret.d (Interpreter::visit (DeclarationExp)): Likewise. ++ * dmd/dsymbolsem.d (DsymbolSemanticVisitor::visit (VarDeclaration)): ++ Don't push tuple field members to the scope symbol table. ++ (determineFields): Handle pushing tuple field members here instead. ++ * dmd/dtoh.d (ToCppBuffer::visit (VarDeclaration)): Visit all tuple ++ fields. ++ (ToCppBuffer::visit (TupleDeclaration)): New function. ++ * dmd/expression.d (expandAliasThisTuples): Use foreachVar. ++ * dmd/foreachvar.d (VarWalker::visit (DeclarationExp)): Likewise. ++ * dmd/ob.d (genKill): Likewise. ++ (checkObErrors): Likewise. ++ * dmd/semantic2.d (Semantic2Visitor::visit (TupleDeclaration)): Visit ++ all tuple fields. ++ ++2023-07-07 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-07 Iain Buclaw ++ ++ PR d/108842 ++ * decl.cc (DeclVisitor::visit (VarDeclaration *)): Only emit scalar ++ manifest constants. ++ (get_symbol_decl): Don't generate CONST_DECL for non-scalar manifest ++ constants. ++ * imports.cc (ImportVisitor::visit (VarDeclaration *)): New method. ++ ++2023-07-02 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-02 Iain Buclaw ++ ++ PR d/110516 ++ * intrinsics.cc (expand_volatile_load): Set TREE_SIDE_EFFECTS on the ++ expanded expression. ++ (expand_volatile_store): Likewise. ++ ++2023-07-01 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-01 Iain Buclaw ++ ++ PR d/110514 ++ * decl.cc (get_symbol_decl): Set TREE_READONLY on certain kinds of ++ const and immutable variables. ++ * expr.cc (ExprVisitor::visit (ArrayLiteralExp *)): Set TREE_READONLY ++ on immutable dynamic array literals. ++ ++2023-06-26 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-26 Iain Buclaw ++ ++ PR d/110359 ++ * d-convert.cc (convert_for_rvalue): Only apply the @safe boolean ++ conversion to boolean fields of a union. ++ (convert_for_condition): Call convert_for_rvalue in the default case. ++ ++2023-06-26 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-26 Iain Buclaw ++ ++ PR d/110113 ++ * dmd/escape.d (checkMutableArguments): Always allocate new buffer for ++ computing escapeBy. ++ ++2023-06-06 Iain Buclaw ++ ++ * dmd/MERGE: Merge upstream dmd 316b89f1e3. ++ * dmd/VERSION: Bump version to v2.100.2. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/gcc/d/d-builtins.cc b/gcc/d/d-builtins.cc +index 7e7fb75bdc5..7d659494184 100644 +--- a/gcc/d/d-builtins.cc ++++ b/gcc/d/d-builtins.cc +@@ -846,6 +846,9 @@ d_build_d_type_nodes (void) + d_bool_type = make_unsigned_type (1); + TREE_SET_CODE (d_bool_type, BOOLEAN_TYPE); + ++ d_bool_false_node = TYPE_MIN_VALUE (d_bool_type); ++ d_bool_true_node = TYPE_MAX_VALUE (d_bool_type); ++ + char8_type_node = make_unsigned_type (8); + TYPE_STRING_FLAG (char8_type_node) = 1; + +diff --git a/gcc/d/d-codegen.cc b/gcc/d/d-codegen.cc +index dfeae831801..bdcac5d9825 100644 +--- a/gcc/d/d-codegen.cc ++++ b/gcc/d/d-codegen.cc +@@ -1105,7 +1105,7 @@ build_array_struct_comparison (tree_code code, StructDeclaration *sd, + if (length == 0 || result OP 0) break; */ + t = build_boolop (EQ_EXPR, length, d_convert (lentype, integer_zero_node)); + t = build_boolop (TRUTH_ORIF_EXPR, t, build_boolop (code, result, +- boolean_false_node)); ++ d_bool_false_node)); + t = build1 (EXIT_EXPR, void_type_node, t); + add_stmt (t); + +@@ -2197,14 +2197,16 @@ d_build_call (TypeFunction *tf, tree callable, tree object, + for (size_t i = 0; i < arguments->length; ++i) + { + Expression *arg = (*arguments)[i]; +- tree targ = build_expr (arg); ++ tree targ; + + if (i - varargs < nparams && i >= varargs) + { + /* Actual arguments for declared formal arguments. */ + Parameter *parg = tf->parameterList[i - varargs]; +- targ = convert_for_argument (targ, parg); ++ targ = convert_for_argument (arg, parg); + } ++ else ++ targ = build_expr (arg); + + /* Don't pass empty aggregates by value. */ + if (empty_aggregate_p (TREE_TYPE (targ)) && !TREE_ADDRESSABLE (targ) +diff --git a/gcc/d/d-convert.cc b/gcc/d/d-convert.cc +index ec5da6c10a6..13fc5e7d2e2 100644 +--- a/gcc/d/d-convert.cc ++++ b/gcc/d/d-convert.cc +@@ -132,13 +132,13 @@ d_truthvalue_conversion (tree expr) + return expr; + + case INTEGER_CST: +- return integer_zerop (expr) ? boolean_false_node +- : boolean_true_node; ++ return integer_zerop (expr) ? d_bool_false_node ++ : d_bool_true_node; + + case REAL_CST: + return real_compare (NE_EXPR, &TREE_REAL_CST (expr), &dconst0) +- ? boolean_true_node +- : boolean_false_node; ++ ? d_bool_true_node ++ : d_bool_false_node; + + case ADDR_EXPR: + /* If we are taking the address of a decl that can never be null, +@@ -148,7 +148,7 @@ d_truthvalue_conversion (tree expr) + warning (OPT_Waddress, + "the address of %qD will always evaluate as %", + TREE_OPERAND (expr, 0)); +- return boolean_true_node; ++ return d_bool_true_node; + } + break; + +@@ -620,7 +620,7 @@ convert_expr (tree exp, Type *etype, Type *totype) + return result ? result : convert (build_ctype (totype), exp); + } + +-/* Return a TREE represenwation of EXPR, whose type has been converted from ++/* Return a TREE representation of EXPR, whose type has been converted from + * ETYPE to TOTYPE, and is being used in an rvalue context. */ + + tree +@@ -635,20 +635,27 @@ convert_for_rvalue (tree expr, Type *etype, Type *totype) + { + /* If casting from bool, the result is either 0 or 1, any other value + violates @safe code, so enforce that it is never invalid. */ +- if (CONSTANT_CLASS_P (expr)) +- result = d_truthvalue_conversion (expr); +- else ++ for (tree ref = expr; TREE_CODE (ref) == COMPONENT_REF; ++ ref = TREE_OPERAND (ref, 0)) + { +- /* Reinterpret the boolean as an integer and test the first bit. +- The generated code should end up being equivalent to: ++ /* If the expression is a field that's part of a union, reinterpret ++ the boolean as an integer and test the first bit. The generated ++ code should end up being equivalent to: + *cast(ubyte *)&expr & 1; */ +- machine_mode bool_mode = TYPE_MODE (TREE_TYPE (expr)); +- tree mtype = lang_hooks.types.type_for_mode (bool_mode, 1); +- result = fold_build2 (BIT_AND_EXPR, mtype, +- build_vconvert (mtype, expr), +- build_one_cst (mtype)); ++ if (TREE_CODE (TREE_TYPE (TREE_OPERAND (ref, 0))) == UNION_TYPE) ++ { ++ machine_mode bool_mode = TYPE_MODE (TREE_TYPE (expr)); ++ tree mtype = lang_hooks.types.type_for_mode (bool_mode, 1); ++ result = fold_build2 (BIT_AND_EXPR, mtype, ++ build_vconvert (mtype, expr), ++ build_one_cst (mtype)); ++ break; ++ } + } + ++ if (result == NULL_TREE) ++ result = d_truthvalue_conversion (expr); ++ + result = convert (build_ctype (tbtype), result); + } + +@@ -688,16 +695,86 @@ convert_for_rvalue (tree expr, Type *etype, Type *totype) + return result ? result : convert_expr (expr, etype, totype); + } + ++/* Helper for convert_for_assigment and convert_for_argument. ++ Returns true if EXPR is a va_list static array parameter. */ ++ ++static bool ++is_valist_parameter_type (Expression *expr) ++{ ++ Declaration *decl = NULL; ++ ++ if (VarExp *ve = expr->isVarExp ()) ++ decl = ve->var; ++ else if (SymOffExp *se = expr->isSymOffExp ()) ++ decl = se->var; ++ ++ if (decl != NULL && decl->isParameter () && valist_array_p (decl->type)) ++ return true; ++ ++ return false; ++} ++ ++/* Helper for convert_for_assigment and convert_for_argument. ++ Report erroneous uses of assigning or passing a va_list parameter. */ ++ ++static void ++check_valist_conversion (Expression *expr, Type *totype, bool in_assignment) ++{ ++ /* Parameter symbol and its converted type. */ ++ Declaration *decl = NULL; ++ /* Type of parameter when evaluated in the expression. */ ++ Type *type = NULL; ++ ++ if (VarExp *ve = expr->isVarExp ()) ++ { ++ decl = ve->var; ++ type = ve->var->type->nextOf ()->pointerTo (); ++ } ++ else if (SymOffExp *se = expr->isSymOffExp ()) ++ { ++ decl = se->var; ++ type = se->var->type->nextOf ()->pointerTo ()->pointerTo (); ++ } ++ ++ /* Should not be called unless is_valist_parameter_type also matched. */ ++ gcc_assert (decl != NULL && decl->isParameter () ++ && valist_array_p (decl->type)); ++ ++ /* OK if conversion between types is allowed. */ ++ if (type->implicitConvTo (totype) != MATCH::nomatch) ++ return; ++ ++ if (in_assignment) ++ { ++ error_at (make_location_t (expr->loc), "cannot convert parameter %qs " ++ "from type %qs to type %qs in assignment", ++ expr->toChars(), type->toChars (), totype->toChars ()); ++ } ++ else ++ { ++ error_at (make_location_t (expr->loc), "cannot convert parameter %qs " ++ "from type %qs to type %qs in argument passing", ++ expr->toChars(), type->toChars (), totype->toChars ()); ++ } ++ ++ inform (make_location_t (decl->loc), "parameters of type % " ++ "{aka %qs} are decayed to pointer types, and require % " ++ "to be converted back into a static array type", ++ decl->type->toChars ()); ++} ++ + /* Apply semantics of assignment to a value of type TOTYPE to EXPR +- (e.g., pointer = array -> pointer = &array[0]) ++ For example: `pointer = array' gets lowered to `pointer = &array[0]'. ++ If LITERALP is true, then EXPR is a value used in the initialization ++ of another literal. + + Return a TREE representation of EXPR implicitly converted to TOTYPE + for use in assignment expressions MODIFY_EXPR, INIT_EXPR. */ + + tree +-convert_for_assignment (tree expr, Type *etype, Type *totype) ++convert_for_assignment (Expression *expr, Type *totype, bool literalp) + { +- Type *ebtype = etype->toBasetype (); ++ Type *ebtype = expr->type->toBasetype (); + Type *tbtype = totype->toBasetype (); + + /* Assuming this only has to handle converting a non Tsarray type to +@@ -717,8 +794,8 @@ convert_for_assignment (tree expr, Type *etype, Type *totype) + vec *ce = NULL; + tree index = build2 (RANGE_EXPR, build_ctype (Type::tsize_t), + size_zero_node, size_int (count - 1)); +- tree value = convert_for_assignment (expr, etype, sa_type->next); +- ++ tree value = convert_for_assignment (expr, sa_type->next, ++ literalp); + /* Can't use VAR_DECLs in CONSTRUCTORS. */ + if (VAR_P (value)) + { +@@ -739,38 +816,53 @@ convert_for_assignment (tree expr, Type *etype, Type *totype) + if ((tbtype->ty == TY::Tsarray || tbtype->ty == TY::Tstruct) + && ebtype->isintegral ()) + { +- if (!integer_zerop (expr)) +- gcc_unreachable (); +- +- return expr; ++ tree ret = build_expr (expr, false, literalp); ++ gcc_assert (integer_zerop (ret)); ++ return ret; + } + +- return convert_for_rvalue (expr, etype, totype); ++ /* Assigning a va_list by value or reference, check whether RHS is a parameter ++ that has has been lowered by declaration_type or parameter_type. */ ++ if (is_valist_parameter_type (expr)) ++ check_valist_conversion (expr, totype, true); ++ ++ return convert_for_rvalue (build_expr (expr, false, literalp), ++ expr->type, totype); + } + + /* Return a TREE representation of EXPR converted to represent + the parameter type ARG. */ + + tree +-convert_for_argument (tree expr, Parameter *arg) ++convert_for_argument (Expression *expr, Parameter *arg) + { ++ tree targ = build_expr (expr); ++ + /* Lazy arguments: expr should already be a delegate. */ + if (arg->storageClass & STClazy) +- return expr; ++ return targ; + ++ /* Passing a va_list by value, check whether the target requires it to ++ be decayed to a pointer type. */ + if (valist_array_p (arg->type)) + { +- /* Do nothing if the va_list has already been decayed to a pointer. */ +- if (!POINTER_TYPE_P (TREE_TYPE (expr))) +- return build_address (expr); +- } +- else if (parameter_reference_p (arg)) +- { +- /* Front-end shouldn't automatically take the address. */ +- return convert (parameter_type (arg), build_address (expr)); ++ if (!POINTER_TYPE_P (TREE_TYPE (targ))) ++ return build_address (targ); ++ ++ /* Do nothing if the va_list has already been converted. */ ++ return targ; + } + +- return expr; ++ /* Passing a va_list by reference, check if types are really compatible ++ after conversion from static array to pointer type. */ ++ if (is_valist_parameter_type (expr)) ++ check_valist_conversion (expr, arg->type, false); ++ ++ /* Front-end shouldn't automatically take the address of `ref' parameters. */ ++ if (parameter_reference_p (arg)) ++ return convert (parameter_type (arg), build_address (targ)); ++ ++ return targ; + } + + /* Perform default promotions for data used in expressions. +@@ -845,7 +937,7 @@ convert_for_condition (tree expr, Type *type) + break; + + default: +- result = expr; ++ result = convert_for_rvalue (expr, type, type); + break; + } + +diff --git a/gcc/d/d-tree.h b/gcc/d/d-tree.h +index aedbdd80a73..30524fedbcf 100644 +--- a/gcc/d/d-tree.h ++++ b/gcc/d/d-tree.h +@@ -426,6 +426,9 @@ enum d_tree_index + DTI_NULL_ARRAY, + DTI_BOTTOM_TYPE, + ++ DTI_BOOL_FALSE, ++ DTI_BOOL_TRUE, ++ + DTI_MAX + }; + +@@ -462,6 +465,9 @@ extern GTY(()) tree d_global_trees[DTI_MAX]; + #define null_array_node d_global_trees[DTI_NULL_ARRAY] + /* The bottom type, referred to as `noreturn` in code. */ + #define noreturn_type_node d_global_trees[DTI_BOTTOM_TYPE] ++/* D boolean values are always byte-sized, unlike boolean_type_node. */ ++#define d_bool_false_node d_global_trees[DTI_BOOL_FALSE] ++#define d_bool_true_node d_global_trees[DTI_BOOL_TRUE] + + /* A prefix for internal variables, which are not user-visible. */ + #if !defined (NO_DOT_IN_LABEL) +@@ -600,8 +606,8 @@ extern tree d_truthvalue_conversion (tree); + extern tree d_convert (tree, tree); + extern tree convert_expr (tree, Type *, Type *); + extern tree convert_for_rvalue (tree, Type *, Type *); +-extern tree convert_for_assignment (tree, Type *, Type *); +-extern tree convert_for_argument (tree, Parameter *); ++extern tree convert_for_assignment (Expression *, Type *, bool = false); ++extern tree convert_for_argument (Expression *, Parameter *); + extern tree convert_for_condition (tree, Type *); + extern tree d_array_convert (Expression *); + extern tree d_array_convert (Type *, Expression *); +diff --git a/gcc/d/decl.cc b/gcc/d/decl.cc +index 1cdfc24666e..8f0026b7be9 100644 +--- a/gcc/d/decl.cc ++++ b/gcc/d/decl.cc +@@ -781,7 +781,7 @@ public: + { + /* Do not store variables we cannot take the address of, + but keep the values for purposes of debugging. */ +- if (!d->type->isscalar ()) ++ if (d->type->isscalar () && !d->type->hasPointers ()) + { + tree decl = get_symbol_decl (d); + d_pushdecl (decl); +@@ -1199,6 +1199,20 @@ get_symbol_decl (Declaration *decl) + return decl->csym; + } + ++ if (VarDeclaration *vd = decl->isVarDeclaration ()) ++ { ++ /* CONST_DECL was initially intended for enumerals and may be used for ++ scalars in general, but not for aggregates. Here a non-constant ++ value is generated anyway so as its value can be used. */ ++ if (!vd->canTakeAddressOf () && !vd->type->isscalar ()) ++ { ++ gcc_assert (vd->_init && !vd->_init->isVoidInitializer ()); ++ Expression *ie = initializerToExpression (vd->_init); ++ decl->csym = build_expr (ie, false); ++ return decl->csym; ++ } ++ } ++ + /* Build the tree for the symbol. */ + FuncDeclaration *fd = decl->isFuncDeclaration (); + if (fd) +@@ -1246,24 +1260,30 @@ get_symbol_decl (Declaration *decl) + if (vd->storage_class & STCextern) + DECL_EXTERNAL (decl->csym) = 1; + +- /* CONST_DECL was initially intended for enumerals and may be used for +- scalars in general, but not for aggregates. Here a non-constant +- value is generated anyway so as the CONST_DECL only serves as a +- placeholder for the value, however the DECL itself should never be +- referenced in any generated code, or passed to the back-end. */ +- if (vd->storage_class & STCmanifest) ++ if (!vd->canTakeAddressOf ()) + { + /* Cannot make an expression out of a void initializer. */ +- if (vd->_init && !vd->_init->isVoidInitializer ()) +- { +- Expression *ie = initializerToExpression (vd->_init); ++ gcc_assert (vd->_init && !vd->_init->isVoidInitializer ()); ++ /* Non-scalar manifest constants have already been dealt with. */ ++ gcc_assert (vd->type->isscalar ()); + +- if (!vd->type->isscalar ()) +- DECL_INITIAL (decl->csym) = build_expr (ie, false); +- else +- DECL_INITIAL (decl->csym) = build_expr (ie, true); +- } ++ Expression *ie = initializerToExpression (vd->_init); ++ DECL_INITIAL (decl->csym) = build_expr (ie, true); + } ++ ++ /* [type-qualifiers/const-and-immutable] ++ ++ `immutable` applies to data that cannot change. Immutable data values, ++ once constructed, remain the same for the duration of the program's ++ execution. */ ++ if (vd->isImmutable () && !vd->setInCtorOnly ()) ++ TREE_READONLY (decl->csym) = 1; ++ ++ /* `const` applies to data that cannot be changed by the const reference ++ to that data. It may, however, be changed by another reference to that ++ same data. */ ++ if (vd->isConst () && !vd->isDataseg ()) ++ TREE_READONLY (decl->csym) = 1; + } + + /* Set the declaration mangled identifier if static. */ +diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE +index d79ebfae806..51736565a57 100644 +--- a/gcc/d/dmd/MERGE ++++ b/gcc/d/dmd/MERGE +@@ -1,4 +1,4 @@ +-76e3b41375e3e1cb4dbca692b587d8e916c0b49f ++316b89f1e3dffcad488c26f56f58c8adfcb84b26 + + The first line of this file holds the git revision number of the last + merge done from the dlang/dmd repository. +diff --git a/gcc/d/dmd/VERSION b/gcc/d/dmd/VERSION +index 83a14f57e16..868f8007d2f 100644 +--- a/gcc/d/dmd/VERSION ++++ b/gcc/d/dmd/VERSION +@@ -1 +1 @@ +-v2.100.1 ++v2.100.2 +diff --git a/gcc/d/dmd/canthrow.d b/gcc/d/dmd/canthrow.d +index a38cbb1610b..fe6e1e344b9 100644 +--- a/gcc/d/dmd/canthrow.d ++++ b/gcc/d/dmd/canthrow.d +@@ -270,18 +270,7 @@ private CT Dsymbol_canThrow(Dsymbol s, FuncDeclaration func, bool mustNotThrow) + } + else if (auto td = s.isTupleDeclaration()) + { +- for (size_t i = 0; i < td.objects.dim; i++) +- { +- RootObject o = (*td.objects)[i]; +- if (o.dyncast() == DYNCAST.expression) +- { +- Expression eo = cast(Expression)o; +- if (auto se = eo.isDsymbolExp()) +- { +- result |= Dsymbol_canThrow(se.s, func, mustNotThrow); +- } +- } +- } ++ td.foreachVar(&symbolDg); + } + return result; + } +diff --git a/gcc/d/dmd/declaration.d b/gcc/d/dmd/declaration.d +index 7b50c050487..6c83c196f72 100644 +--- a/gcc/d/dmd/declaration.d ++++ b/gcc/d/dmd/declaration.d +@@ -656,23 +656,46 @@ extern (C++) final class TupleDeclaration : Declaration + override bool needThis() + { + //printf("TupleDeclaration::needThis(%s)\n", toChars()); +- for (size_t i = 0; i < objects.dim; i++) ++ return isexp ? foreachVar((s) { return s.needThis(); }) != 0 : false; ++ } ++ ++ /*********************************************************** ++ * Calls dg(Dsymbol) for each Dsymbol, which should be a VarDeclaration ++ * inside DsymbolExp (isexp == true). ++ * Params: ++ * dg = delegate to call for each Dsymbol ++ */ ++ extern (D) void foreachVar(scope void delegate(Dsymbol) dg) ++ { ++ assert(isexp); ++ foreach (o; *objects) + { +- RootObject o = (*objects)[i]; +- if (o.dyncast() == DYNCAST.expression) +- { +- Expression e = cast(Expression)o; +- if (DsymbolExp ve = e.isDsymbolExp()) +- { +- Declaration d = ve.s.isDeclaration(); +- if (d && d.needThis()) +- { +- return true; +- } +- } +- } ++ if (auto e = o.isExpression()) ++ if (auto se = e.isDsymbolExp()) ++ dg(se.s); + } +- return false; ++ } ++ ++ /*********************************************************** ++ * Calls dg(Dsymbol) for each Dsymbol, which should be a VarDeclaration ++ * inside DsymbolExp (isexp == true). ++ * If dg returns !=0, stops and returns that value else returns 0. ++ * Params: ++ * dg = delegate to call for each Dsymbol ++ * Returns: ++ * last value returned by dg() ++ */ ++ extern (D) int foreachVar(scope int delegate(Dsymbol) dg) ++ { ++ assert(isexp); ++ foreach (o; *objects) ++ { ++ if (auto e = o.isExpression()) ++ if (auto se = e.isDsymbolExp()) ++ if(auto ret = dg(se.s)) ++ return ret; ++ } ++ return 0; + } + + override inout(TupleDeclaration) isTupleDeclaration() inout +@@ -1142,15 +1165,7 @@ extern (C++) class VarDeclaration : Declaration + // If this variable was really a tuple, set the offsets for the tuple fields + TupleDeclaration v2 = aliassym.isTupleDeclaration(); + assert(v2); +- for (size_t i = 0; i < v2.objects.dim; i++) +- { +- RootObject o = (*v2.objects)[i]; +- assert(o.dyncast() == DYNCAST.expression); +- Expression e = cast(Expression)o; +- assert(e.op == EXP.dSymbol); +- DsymbolExp se = e.isDsymbolExp(); +- se.s.setFieldOffset(ad, fieldState, isunion); +- } ++ v2.foreachVar((s) { s.setFieldOffset(ad, fieldState, isunion); }); + return; + } + +diff --git a/gcc/d/dmd/dinterpret.d b/gcc/d/dmd/dinterpret.d +index e96f1806982..485b2dec1a1 100644 +--- a/gcc/d/dmd/dinterpret.d ++++ b/gcc/d/dmd/dinterpret.d +@@ -2291,16 +2291,12 @@ public: + result = null; + + // Reserve stack space for all tuple members +- if (!td.objects) +- return; +- foreach (o; *td.objects) ++ td.foreachVar((s) + { +- Expression ex = isExpression(o); +- DsymbolExp ds = ex ? ex.isDsymbolExp() : null; +- VarDeclaration v2 = ds ? ds.s.isVarDeclaration() : null; ++ VarDeclaration v2 = s.isVarDeclaration(); + assert(v2); + if (v2.isDataseg() && !v2.isCTFE()) +- continue; ++ return 0; + + ctfeGlobals.stack.push(v2); + if (v2._init) +@@ -2310,7 +2306,7 @@ public: + { + einit = interpretRegion(ie.exp, istate, goal); + if (exceptionOrCant(einit)) +- return; ++ return 1; + } + else if (v2._init.isVoidInitializer()) + { +@@ -2320,11 +2316,12 @@ public: + { + e.error("declaration `%s` is not yet implemented in CTFE", e.toChars()); + result = CTFEExp.cantexp; +- return; ++ return 1; + } + setValue(v2, einit); + } +- } ++ return 0; ++ }); + return; + } + if (v.isStatic()) +diff --git a/gcc/d/dmd/dsymbolsem.d b/gcc/d/dmd/dsymbolsem.d +index c5766787bf0..dfaaff93d35 100644 +--- a/gcc/d/dmd/dsymbolsem.d ++++ b/gcc/d/dmd/dsymbolsem.d +@@ -650,7 +650,7 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor + else + ti = dsym._init ? dsym._init.syntaxCopy() : null; + +- StorageClass storage_class = STC.temp | STC.local | dsym.storage_class; ++ StorageClass storage_class = STC.temp | dsym.storage_class; + if ((dsym.storage_class & STC.parameter) && (arg.storageClass & STC.parameter)) + storage_class |= arg.storageClass; + auto v = new VarDeclaration(dsym.loc, arg.type, id, ti, storage_class); +@@ -659,14 +659,6 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor + + v.dsymbolSemantic(sc); + +- if (sc.scopesym) +- { +- //printf("adding %s to %s\n", v.toChars(), sc.scopesym.toChars()); +- if (sc.scopesym.members) +- // Note this prevents using foreach() over members, because the limits can change +- sc.scopesym.members.push(v); +- } +- + Expression e = new DsymbolExp(dsym.loc, v); + (*exps)[i] = e; + } +@@ -6819,7 +6811,12 @@ bool determineFields(AggregateDeclaration ad) + return 1; + + if (v.aliassym) +- return 0; // If this variable was really a tuple, skip it. ++ { ++ // If this variable was really a tuple, process each element. ++ if (auto tup = v.aliassym.isTupleDeclaration()) ++ return tup.foreachVar(tv => tv.apply(&func, ad)); ++ return 0; ++ } + + if (v.storage_class & (STC.static_ | STC.extern_ | STC.tls | STC.gshared | STC.manifest | STC.ctfe | STC.templateparameter)) + return 0; +diff --git a/gcc/d/dmd/dtoh.d b/gcc/d/dmd/dtoh.d +index 17abb7d3b00..ecc637eff53 100644 +--- a/gcc/d/dmd/dtoh.d ++++ b/gcc/d/dmd/dtoh.d +@@ -877,7 +877,11 @@ public: + // Tuple field are expanded into multiple VarDeclarations + // (we'll visit them later) + if (vd.type && vd.type.isTypeTuple()) ++ { ++ assert(vd.aliassym); ++ vd.toAlias().accept(this); + return; ++ } + + if (vd.originalType && vd.type == AST.Type.tsize_t) + origType = vd.originalType; +@@ -1667,6 +1671,13 @@ public: + assert(false, "This node type should be handled in the EnumDeclaration"); + } + ++ override void visit(AST.TupleDeclaration tup) ++ { ++ debug (Debug_DtoH) mixin(traceVisit!tup); ++ ++ tup.foreachVar((s) { s.accept(this); }); ++ } ++ + /** + * Prints a member/parameter/variable declaration into `buf`. + * +diff --git a/gcc/d/dmd/escape.d b/gcc/d/dmd/escape.d +index 7c7ba96db0d..ab85f8706ec 100644 +--- a/gcc/d/dmd/escape.d ++++ b/gcc/d/dmd/escape.d +@@ -77,22 +77,7 @@ bool checkMutableArguments(Scope* sc, FuncDeclaration fd, TypeFunction tf, + bool isMutable; // true if reference to mutable + } + +- /* Store escapeBy as static data escapeByStorage so we can keep reusing the same +- * arrays rather than reallocating them. +- */ +- __gshared EscapeBy[] escapeByStorage; +- auto escapeBy = escapeByStorage; +- if (escapeBy.length < len) +- { +- auto newPtr = cast(EscapeBy*)mem.xrealloc(escapeBy.ptr, len * EscapeBy.sizeof); +- // Clear the new section +- memset(newPtr + escapeBy.length, 0, (len - escapeBy.length) * EscapeBy.sizeof); +- escapeBy = newPtr[0 .. len]; +- escapeByStorage = escapeBy; +- } +- else +- escapeBy = escapeBy[0 .. len]; +- ++ auto escapeBy = new EscapeBy[len]; + const paramLength = tf.parameterList.length; + + // Fill in escapeBy[] with arguments[], ethis, and outerVars[] +@@ -212,13 +197,6 @@ bool checkMutableArguments(Scope* sc, FuncDeclaration fd, TypeFunction tf, + escape(i, eb, false); + } + +- /* Reset the arrays in escapeBy[] so we can reuse them next time through +- */ +- foreach (ref eb; escapeBy) +- { +- eb.er.reset(); +- } +- + return errors; + } + +diff --git a/gcc/d/dmd/expression.d b/gcc/d/dmd/expression.d +index 107e85b0793..832ab7dda37 100644 +--- a/gcc/d/dmd/expression.d ++++ b/gcc/d/dmd/expression.d +@@ -348,14 +348,16 @@ int expandAliasThisTuples(Expressions* exps, size_t starti = 0) + if (TupleDeclaration td = exp.isAliasThisTuple) + { + exps.remove(u); +- foreach (i, o; *td.objects) ++ size_t i; ++ td.foreachVar((s) + { +- auto d = o.isExpression().isDsymbolExp().s.isDeclaration(); ++ auto d = s.isDeclaration(); + auto e = new DotVarExp(exp.loc, exp, d); + assert(d.type); + e.type = d.type; + exps.insert(u + i, e); +- } ++ ++i; ++ }); + version (none) + { + printf("expansion ->\n"); +diff --git a/gcc/d/dmd/foreachvar.d b/gcc/d/dmd/foreachvar.d +index 53ed62efd70..63281b5760c 100644 +--- a/gcc/d/dmd/foreachvar.d ++++ b/gcc/d/dmd/foreachvar.d +@@ -75,19 +75,7 @@ void foreachVar(Expression e, void delegate(VarDeclaration) dgVar) + if (!v) + return; + if (TupleDeclaration td = v.toAlias().isTupleDeclaration()) +- { +- if (!td.objects) +- return; +- foreach (o; *td.objects) +- { +- Expression ex = isExpression(o); +- DsymbolExp s = ex ? ex.isDsymbolExp() : null; +- assert(s); +- VarDeclaration v2 = s.s.isVarDeclaration(); +- assert(v2); +- dgVar(v2); +- } +- } ++ td.foreachVar((s) { dgVar(s.isVarDeclaration()); }); + else + dgVar(v); + Dsymbol s = v.toAlias(); +diff --git a/gcc/d/dmd/ob.d b/gcc/d/dmd/ob.d +index 121a266b428..5ff73c983f0 100644 +--- a/gcc/d/dmd/ob.d ++++ b/gcc/d/dmd/ob.d +@@ -1407,16 +1407,7 @@ void genKill(ref ObState obstate, ObNode* ob) + } + else if (auto td = s.isTupleDeclaration()) + { +- foreach (o; *td.objects) +- { +- if (auto eo = o.isExpression()) +- { +- if (auto se = eo.isDsymbolExp()) +- { +- Dsymbol_visit(se.s); +- } +- } +- } ++ td.foreachVar(&Dsymbol_visit); + } + } + +@@ -2107,16 +2098,7 @@ void checkObErrors(ref ObState obstate) + } + else if (auto td = s.isTupleDeclaration()) + { +- foreach (o; *td.objects) +- { +- if (auto eo = o.isExpression()) +- { +- if (auto se = eo.isDsymbolExp()) +- { +- Dsymbol_visit(se.s); +- } +- } +- } ++ td.foreachVar(&Dsymbol_visit); + } + } + +diff --git a/gcc/d/dmd/semantic2.d b/gcc/d/dmd/semantic2.d +index 73dcaa6c960..bf18a2140fb 100644 +--- a/gcc/d/dmd/semantic2.d ++++ b/gcc/d/dmd/semantic2.d +@@ -677,6 +677,11 @@ private extern(C++) final class Semantic2Visitor : Visitor + { + visit(cast(AggregateDeclaration) cd); + } ++ ++ override void visit(TupleDeclaration td) ++ { ++ td.foreachVar((s) { s.accept(this); }); ++ } + } + + /** +diff --git a/gcc/d/expr.cc b/gcc/d/expr.cc +index 6654244292e..7afd98975b1 100644 +--- a/gcc/d/expr.cc ++++ b/gcc/d/expr.cc +@@ -1057,8 +1057,7 @@ public: + Declaration *decl = e->e1->isVarExp ()->var; + if (decl->storage_class & (STCout | STCref)) + { +- tree t2 = convert_for_assignment (build_expr (e->e2), +- e->e2->type, e->e1->type); ++ tree t2 = convert_for_assignment (e->e2, e->e1->type); + tree t1 = build_expr (e->e1); + /* Want reference to lhs, not indirect ref. */ + t1 = TREE_OPERAND (t1, 0); +@@ -1078,8 +1077,7 @@ public: + if (tb1->ty == TY::Tstruct) + { + tree t1 = build_expr (e->e1); +- tree t2 = convert_for_assignment (build_expr (e->e2, false, true), +- e->e2->type, e->e1->type); ++ tree t2 = convert_for_assignment (e->e2, e->e1->type, true); + StructDeclaration *sd = tb1->isTypeStruct ()->sym; + + /* Look for struct = 0. */ +@@ -1157,8 +1155,7 @@ public: + || (e->op == EXP::blit || e->e1->type->size () == 0)) + { + tree t1 = build_expr (e->e1); +- tree t2 = convert_for_assignment (build_expr (e->e2), +- e->e2->type, e->e1->type); ++ tree t2 = convert_for_assignment (e->e2, e->e1->type); + + this->result_ = build_assign (modifycode, t1, t2); + return; +@@ -1192,8 +1189,7 @@ public: + + /* Simple assignment. */ + tree t1 = build_expr (e->e1); +- tree t2 = convert_for_assignment (build_expr (e->e2), +- e->e2->type, e->e1->type); ++ tree t2 = convert_for_assignment (e->e2, e->e1->type); + + this->result_ = build_assign (modifycode, t1, t2); + } +@@ -2708,6 +2704,10 @@ public: + if (tb->ty == TY::Tarray) + ctor = d_array_value (type, size_int (e->elements->length), ctor); + ++ /* Immutable literals can be placed in rodata. */ ++ if (tb->isImmutable ()) ++ TREE_READONLY (decl) = 1; ++ + d_pushdecl (decl); + rest_of_decl_compilation (decl, 1, 0); + } +diff --git a/gcc/d/imports.cc b/gcc/d/imports.cc +index 6a59ef61b9c..c8447b9674c 100644 +--- a/gcc/d/imports.cc ++++ b/gcc/d/imports.cc +@@ -127,6 +127,15 @@ public: + this->result_ = this->make_import (TYPE_STUB_DECL (type)); + } + ++ void visit (VarDeclaration *d) ++ { ++ /* Not all kinds of manifest constants create a CONST_DECL. */ ++ if (!d->canTakeAddressOf () && !d->type->isscalar ()) ++ return; ++ ++ visit ((Declaration *) d); ++ } ++ + /* For now, ignore importing other kinds of dsymbols. */ + void visit (ScopeDsymbol *) + { +diff --git a/gcc/d/intrinsics.cc b/gcc/d/intrinsics.cc +index 4222b8a0290..8ec94a6b8f9 100644 +--- a/gcc/d/intrinsics.cc ++++ b/gcc/d/intrinsics.cc +@@ -721,6 +721,7 @@ expand_volatile_load (tree callexp) + tree type = build_qualified_type (TREE_TYPE (ptrtype), TYPE_QUAL_VOLATILE); + tree result = indirect_ref (type, ptr); + TREE_THIS_VOLATILE (result) = 1; ++ TREE_SIDE_EFFECTS (result) = 1; + + return result; + } +@@ -748,6 +749,7 @@ expand_volatile_store (tree callexp) + tree type = build_qualified_type (TREE_TYPE (ptrtype), TYPE_QUAL_VOLATILE); + tree result = indirect_ref (type, ptr); + TREE_THIS_VOLATILE (result) = 1; ++ TREE_SIDE_EFFECTS (result) = 1; + + /* (*(volatile T *) ptr) = value; */ + tree value = CALL_EXPR_ARG (callexp, 1); +diff --git a/gcc/d/modules.cc b/gcc/d/modules.cc +index 0aac8fe3545..ce35a726c52 100644 +--- a/gcc/d/modules.cc ++++ b/gcc/d/modules.cc +@@ -329,7 +329,7 @@ static tree + build_dso_cdtor_fn (bool ctor_p) + { + const char *name = ctor_p ? GDC_PREFIX ("dso_ctor") : GDC_PREFIX ("dso_dtor"); +- tree condition = ctor_p ? boolean_true_node : boolean_false_node; ++ tree condition = ctor_p ? d_bool_true_node : d_bool_false_node; + + /* Declaration of dso_ctor/dso_dtor is: + +@@ -452,7 +452,7 @@ register_moduleinfo (Module *decl, tree minfo) + d_finish_decl (dso_slot_node); + + dso_initialized_node = build_dso_registry_var (GDC_PREFIX ("dso_initialized"), +- boolean_type_node); ++ d_bool_type); + d_finish_decl (dso_initialized_node); + + /* Declare dso_ctor() and dso_dtor(). */ +diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi +index 33a776a7978..0eb9bdcfac5 100644 +--- a/gcc/doc/extend.texi ++++ b/gcc/doc/extend.texi +@@ -14618,6 +14618,7 @@ instructions, but allow the compiler to schedule those calls. + * Blackfin Built-in Functions:: + * BPF Built-in Functions:: + * FR-V Built-in Functions:: ++* LoongArch Base Built-in Functions:: + * MIPS DSP Built-in Functions:: + * MIPS Paired-Single Support:: + * MIPS Loongson Built-in Functions:: +@@ -16068,6 +16069,139 @@ Use the @code{nldub} instruction to load the contents of address @var{x} + into the data cache. The instruction is issued in slot I1@. + @end table + ++@node LoongArch Base Built-in Functions ++@subsection LoongArch Base Built-in Functions ++ ++These built-in functions are available for LoongArch. ++ ++Data Type Description: ++@itemize ++@item @code{imm0_31}, a compile-time constant in range 0 to 31; ++@item @code{imm0_16383}, a compile-time constant in range 0 to 16383; ++@item @code{imm0_32767}, a compile-time constant in range 0 to 32767; ++@item @code{imm_n2048_2047}, a compile-time constant in range -2048 to 2047; ++@end itemize ++ ++The intrinsics provided are listed below: ++@smallexample ++ unsigned int __builtin_loongarch_movfcsr2gr (imm0_31) ++ void __builtin_loongarch_movgr2fcsr (imm0_31, unsigned int) ++ void __builtin_loongarch_cacop_d (imm0_31, unsigned long int, imm_n2048_2047) ++ unsigned int __builtin_loongarch_cpucfg (unsigned int) ++ void __builtin_loongarch_asrtle_d (long int, long int) ++ void __builtin_loongarch_asrtgt_d (long int, long int) ++ long int __builtin_loongarch_lddir_d (long int, imm0_31) ++ void __builtin_loongarch_ldpte_d (long int, imm0_31) ++ ++ int __builtin_loongarch_crc_w_b_w (char, int) ++ int __builtin_loongarch_crc_w_h_w (short, int) ++ int __builtin_loongarch_crc_w_w_w (int, int) ++ int __builtin_loongarch_crc_w_d_w (long int, int) ++ int __builtin_loongarch_crcc_w_b_w (char, int) ++ int __builtin_loongarch_crcc_w_h_w (short, int) ++ int __builtin_loongarch_crcc_w_w_w (int, int) ++ int __builtin_loongarch_crcc_w_d_w (long int, int) ++ ++ unsigned int __builtin_loongarch_csrrd_w (imm0_16383) ++ unsigned int __builtin_loongarch_csrwr_w (unsigned int, imm0_16383) ++ unsigned int __builtin_loongarch_csrxchg_w (unsigned int, unsigned int, imm0_16383) ++ unsigned long int __builtin_loongarch_csrrd_d (imm0_16383) ++ unsigned long int __builtin_loongarch_csrwr_d (unsigned long int, imm0_16383) ++ unsigned long int __builtin_loongarch_csrxchg_d (unsigned long int, unsigned long int, imm0_16383) ++ ++ unsigned char __builtin_loongarch_iocsrrd_b (unsigned int) ++ unsigned short __builtin_loongarch_iocsrrd_h (unsigned int) ++ unsigned int __builtin_loongarch_iocsrrd_w (unsigned int) ++ unsigned long int __builtin_loongarch_iocsrrd_d (unsigned int) ++ void __builtin_loongarch_iocsrwr_b (unsigned char, unsigned int) ++ void __builtin_loongarch_iocsrwr_h (unsigned short, unsigned int) ++ void __builtin_loongarch_iocsrwr_w (unsigned int, unsigned int) ++ void __builtin_loongarch_iocsrwr_d (unsigned long int, unsigned int) ++ ++ void __builtin_loongarch_dbar (imm0_32767) ++ void __builtin_loongarch_ibar (imm0_32767) ++ ++ void __builtin_loongarch_syscall (imm0_32767) ++ void __builtin_loongarch_break (imm0_32767) ++@end smallexample ++ ++@emph{Note:}Since the control register is divided into 32-bit and 64-bit, ++but the access instruction is not distinguished. So GCC renames the control ++instructions when implementing intrinsics. ++ ++Take the csrrd instruction as an example, built-in functions are implemented as follows: ++@smallexample ++ __builtin_loongarch_csrrd_w // When reading the 32-bit control register use. ++ __builtin_loongarch_csrrd_d // When reading the 64-bit control register use. ++@end smallexample ++ ++For the convenience of use, the built-in functions are encapsulated, ++the encapsulated functions and @code{__drdtime_t, __rdtime_t} are ++defined in the @code{larchintrin.h}. So if you call the following ++function you need to include @code{larchintrin.h}. ++ ++@smallexample ++ typedef struct drdtime@{ ++ unsigned long dvalue; ++ unsigned long dtimeid; ++ @} __drdtime_t; ++ ++ typedef struct rdtime@{ ++ unsigned int value; ++ unsigned int timeid; ++ @} __rdtime_t; ++@end smallexample ++ ++@smallexample ++ __drdtime_t __rdtime_d (void) ++ __rdtime_t __rdtimel_w (void) ++ __rdtime_t __rdtimeh_w (void) ++ unsigned int __movfcsr2gr (imm0_31) ++ void __movgr2fcsr (imm0_31, unsigned int) ++ void __cacop_d (imm0_31, unsigned long, imm_n2048_2047) ++ unsigned int __cpucfg (unsigned int) ++ void __asrtle_d (long int, long int) ++ void __asrtgt_d (long int, long int) ++ long int __lddir_d (long int, imm0_31) ++ void __ldpte_d (long int, imm0_31) ++ ++ int __crc_w_b_w (char, int) ++ int __crc_w_h_w (short, int) ++ int __crc_w_w_w (int, int) ++ int __crc_w_d_w (long int, int) ++ int __crcc_w_b_w (char, int) ++ int __crcc_w_h_w (short, int) ++ int __crcc_w_w_w (int, int) ++ int __crcc_w_d_w (long int, int) ++ ++ unsigned int __csrrd_w (imm0_16383) ++ unsigned int __csrwr_w (unsigned int, imm0_16383) ++ unsigned int __csrxchg_w (unsigned int, unsigned int, imm0_16383) ++ unsigned long __csrrd_d (imm0_16383) ++ unsigned long __csrwr_d (unsigned long, imm0_16383) ++ unsigned long __csrxchg_d (unsigned long, unsigned long, imm0_16383) ++ ++ unsigned char __iocsrrd_b (unsigned int) ++ unsigned short __iocsrrd_h (unsigned int) ++ unsigned int __iocsrrd_w (unsigned int) ++ unsigned long __iocsrrd_d (unsigned int) ++ void __iocsrwr_b (unsigned char, unsigned int) ++ void __iocsrwr_h (unsigned short, unsigned int) ++ void __iocsrwr_w (unsigned int, unsigned int) ++ void __iocsrwr_d (unsigned long, unsigned int) ++ ++ void __dbar (imm0_32767) ++ void __ibar (imm0_32767) ++ ++ void __syscall (imm0_32767) ++ void __break (imm0_32767) ++@end smallexample ++ ++Returns the value that is currently set in the @samp{tp} register. ++@smallexample ++ void * __builtin_thread_pointer (void) ++@end smallexample ++ + @node MIPS DSP Built-in Functions + @subsection MIPS DSP Built-in Functions + +diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi +index 19d073256a9..d488b768987 100644 +--- a/gcc/doc/install.texi ++++ b/gcc/doc/install.texi +@@ -375,6 +375,9 @@ tables. + + Used by @command{automake}. + ++If available, enables parallel testing of @samp{libgomp} in case that ++@command{flock} is not available. ++ + @end table + + Several support libraries are necessary to build GCC, some are required, +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index cb83dd8a1cc..f1599ba04ad 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -1434,7 +1434,7 @@ See RS/6000 and PowerPC Options. + -m96bit-long-double -mlong-double-64 -mlong-double-80 -mlong-double-128 @gol + -mregparm=@var{num} -msseregparm @gol + -mveclibabi=@var{type} -mvect8-ret-in-mem @gol +--mpc32 -mpc64 -mpc80 -mstackrealign @gol ++-mpc32 -mpc64 -mpc80 -mdaz-ftz -mstackrealign @gol + -momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol + -mcmodel=@var{code-model} -mabi=@var{name} -maddress-mode=@var{mode} @gol + -m32 -m64 -mx32 -m16 -miamcu -mlarge-data-threshold=@var{num} @gol +@@ -6647,7 +6647,7 @@ This warning is enabled by @option{-Wall}. + @item -Wmissing-include-dirs @r{(C, C++, Objective-C, Objective-C++ and Fortran only)} + @opindex Wmissing-include-dirs + @opindex Wno-missing-include-dirs +-Warn if a user-supplied include directory does not exist. This opions is disabled ++Warn if a user-supplied include directory does not exist. This option is disabled + by default for C, C++, Objective-C and Objective-C++. For Fortran, it is partially + enabled by default by warning for -I and -J, only. + +@@ -32078,6 +32078,15 @@ are enabled by default; routines in such libraries could suffer significant + loss of accuracy, typically through so-called ``catastrophic cancellation'', + when this option is used to set the precision to less than extended precision. + ++@item -mdaz-ftz ++@opindex mdaz-ftz ++ ++The flush-to-zero (FTZ) and denormals-are-zero (DAZ) flags in the MXCSR register ++are used to control floating-point calculations.SSE and AVX instructions ++including scalar and vector instructions could benefit from enabling the FTZ ++and DAZ flags when @option{-mdaz-ftz} is specified. Don't set FTZ/DAZ flags ++when @option{-mno-daz-ftz} is specified. ++ + @item -mstackrealign + @opindex mstackrealign + Realign the stack at entry. On the x86, the @option{-mstackrealign} +@@ -33092,7 +33101,7 @@ on x86-64 processors in 64-bit environments. + Generate code for a 16-bit, 32-bit or 64-bit environment. + The @option{-m32} option sets @code{int}, @code{long}, and pointer types + to 32 bits, and +-generates code that runs on any i386 system. ++generates code that runs in 32-bit mode. + + The @option{-m64} option sets @code{int} to 32 bits and @code{long} and pointer + types to 64 bits, and generates code for the x86-64 architecture. +diff --git a/gcc/dwarf2out.cc b/gcc/dwarf2out.cc +index 0a5c081d85e..d14ec0261b6 100644 +--- a/gcc/dwarf2out.cc ++++ b/gcc/dwarf2out.cc +@@ -26508,7 +26508,8 @@ process_scope_var (tree stmt, tree decl, tree origin, dw_die_ref context_die) + + if (die != NULL && die->die_parent == NULL) + add_child_die (context_die, die); +- else if (TREE_CODE (decl_or_origin) == IMPORTED_DECL) ++ ++ if (TREE_CODE (decl_or_origin) == IMPORTED_DECL) + { + if (early_dwarf) + dwarf2out_imported_module_or_decl_1 (decl_or_origin, DECL_NAME (decl_or_origin), +@@ -30107,8 +30108,13 @@ prune_unused_types_walk (dw_die_ref die) + case DW_TAG_reference_type: + case DW_TAG_rvalue_reference_type: + case DW_TAG_volatile_type: ++ case DW_TAG_restrict_type: ++ case DW_TAG_shared_type: ++ case DW_TAG_atomic_type: ++ case DW_TAG_immutable_type: + case DW_TAG_typedef: + case DW_TAG_array_type: ++ case DW_TAG_coarray_type: + case DW_TAG_friend: + case DW_TAG_enumeration_type: + case DW_TAG_subroutine_type: +@@ -30117,6 +30123,8 @@ prune_unused_types_walk (dw_die_ref die) + case DW_TAG_subrange_type: + case DW_TAG_ptr_to_member_type: + case DW_TAG_file_type: ++ case DW_TAG_unspecified_type: ++ case DW_TAG_dynamic_type: + /* Type nodes are useful only when other DIEs reference them --- don't + mark them. */ + /* FALLTHROUGH */ +diff --git a/gcc/fold-const.cc b/gcc/fold-const.cc +index d7923974c85..cd410e50d77 100644 +--- a/gcc/fold-const.cc ++++ b/gcc/fold-const.cc +@@ -14273,7 +14273,7 @@ multiple_of_p (tree type, const_tree top, const_tree bottom, bool nowrap) + && TREE_CODE (op2) == INTEGER_CST + && integer_pow2p (bottom) + && wi::multiple_of_p (wi::to_widest (op2), +- wi::to_widest (bottom), UNSIGNED)) ++ wi::to_widest (bottom), SIGNED)) + return 1; + + op1 = gimple_assign_rhs1 (stmt); +diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog +index c8ecd75c778..6a23225f93c 100644 +--- a/gcc/fortran/ChangeLog ++++ b/gcc/fortran/ChangeLog +@@ -1,3 +1,90 @@ ++2023-12-01 Harald Anlauf ++ ++ Backported from master: ++ 2023-11-26 Harald Anlauf ++ ++ PR fortran/111880 ++ * resolve.cc (resolve_common_vars): Do not call gfc_add_in_common ++ for symbols that are USE associated or used in a submodule. ++ ++2023-10-21 Harald Anlauf ++ ++ Backported from master: ++ 2023-10-17 Harald Anlauf ++ ++ PR fortran/111837 ++ * frontend-passes.cc (traverse_io_block): Dependency check of loop ++ nest shall be triangular, not banded. ++ ++2023-08-06 Steve Kargl ++ ++ Backported from master: ++ 2022-12-18 Steve Kargl ++ ++ PR fortran/107397 ++ * decl.cc (add_init_expr_to_sym): Add check with new error message. ++ ++2023-07-20 Harald Anlauf ++ ++ Backported from master: ++ 2023-07-17 Harald Anlauf ++ ++ PR fortran/95947 ++ PR fortran/110658 ++ * trans-expr.cc (gfc_conv_procedure_call): For intrinsic procedures ++ whose result characteristics depends on the first argument and which ++ can be of type character, the character length will not be deferred. ++ ++2023-07-14 Harald Anlauf ++ ++ Backported from master: ++ 2023-07-11 Harald Anlauf ++ ++ PR fortran/110288 ++ * symbol.cc (gfc_copy_formal_args_intr): When deriving the formal ++ argument attributes from the actual ones for intrinsic procedure ++ calls, take special care of CHARACTER arguments that we do not ++ wrongly treat them formally as deferred-length. ++ ++2023-07-08 Harald Anlauf ++ ++ Backported from master: ++ 2023-07-08 Harald Anlauf ++ ++ PR fortran/110585 ++ * arith.cc (gfc_compare_expr): Handle equality comparison of constant ++ complex gfc_expr arguments. ++ ++2023-06-09 Jakub Jelinek ++ ++ Backported from master: ++ 2023-06-09 Jakub Jelinek ++ ++ PR fortran/96024 ++ * primary.cc (gfc_convert_to_structure_constructor): Only do ++ constant string ctor length verification and truncation/padding ++ if constant length has INTEGER type. ++ ++2023-06-04 Steve Kargl ++ ++ Backported from master: ++ 2023-06-02 Steve Kargl ++ ++ PR fortran/100607 ++ * resolve.cc (resolve_select_rank): Remove duplicate error. ++ (resolve_fl_var_and_proc): Prevent NULL pointer dereference and ++ suppress error message for temporary. ++ ++2023-05-20 Harald Anlauf ++ ++ Backported from master: ++ 2023-05-15 Harald Anlauf ++ ++ PR fortran/109846 ++ * expr.cc (gfc_check_vardef_context): Check appropriate pointer ++ attribute for CLASS vs. non-CLASS function result in variable ++ definition context. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/gcc/fortran/arith.cc b/gcc/fortran/arith.cc +index 1e521cc0cc5..bdde333293e 100644 +--- a/gcc/fortran/arith.cc ++++ b/gcc/fortran/arith.cc +@@ -1080,6 +1080,11 @@ gfc_compare_expr (gfc_expr *op1, gfc_expr *op2, gfc_intrinsic_op op) + || (op1->value.logical && !op2->value.logical)); + break; + ++ case BT_COMPLEX: ++ gcc_assert (op == INTRINSIC_EQ); ++ rc = mpc_cmp (op1->value.complex, op2->value.complex); ++ break; ++ + default: + gfc_internal_error ("gfc_compare_expr(): Bad basic type"); + } +diff --git a/gcc/fortran/decl.cc b/gcc/fortran/decl.cc +index de0fa9d0726..d98f98d7ec6 100644 +--- a/gcc/fortran/decl.cc ++++ b/gcc/fortran/decl.cc +@@ -2220,6 +2220,14 @@ add_init_expr_to_sym (const char *name, gfc_expr **initp, locus *var_locus) + sym->ts.f90_type = init->ts.f90_type; + } + ++ /* Catch the case: type(t), parameter :: x = z'1'. */ ++ if (sym->ts.type == BT_DERIVED && init->ts.type == BT_BOZ) ++ { ++ gfc_error ("Entity %qs at %L is incompatible with a BOZ " ++ "literal constant", name, &sym->declared_at); ++ return false; ++ } ++ + /* Add initializer. Make sure we keep the ranks sane. */ + if (sym->attr.dimension && init->rank == 0) + { +diff --git a/gcc/fortran/expr.cc b/gcc/fortran/expr.cc +index 1369f25011f..c04403a2b89 100644 +--- a/gcc/fortran/expr.cc ++++ b/gcc/fortran/expr.cc +@@ -6254,7 +6254,7 @@ gfc_check_vardef_context (gfc_expr* e, bool pointer, bool alloc_obj, + && !(sym->attr.flavor == FL_PROCEDURE && sym == sym->result) + && !(sym->attr.flavor == FL_PROCEDURE && sym->attr.proc_pointer) + && !(sym->attr.flavor == FL_PROCEDURE +- && sym->attr.function && sym->attr.pointer)) ++ && sym->attr.function && attr.pointer)) + { + if (context) + gfc_error ("%qs in variable definition context (%s) at %L is not" +diff --git a/gcc/fortran/frontend-passes.cc b/gcc/fortran/frontend-passes.cc +index 5eba6345145..53567307cec 100644 +--- a/gcc/fortran/frontend-passes.cc ++++ b/gcc/fortran/frontend-passes.cc +@@ -1326,7 +1326,7 @@ traverse_io_block (gfc_code *code, bool *has_reached, gfc_code *prev) + if (iters[i]) + { + gfc_expr *var = iters[i]->var; +- for (int j = i - 1; j < i; j++) ++ for (int j = 0; j < i; j++) + { + if (iters[j] + && (var_in_expr (var, iters[j]->start) +diff --git a/gcc/fortran/primary.cc b/gcc/fortran/primary.cc +index e48ba755c8a..1ae6a12e0b7 100644 +--- a/gcc/fortran/primary.cc ++++ b/gcc/fortran/primary.cc +@@ -3196,10 +3196,11 @@ gfc_convert_to_structure_constructor (gfc_expr *e, gfc_symbol *sym, gfc_expr **c + goto cleanup; + + /* For a constant string constructor, make sure the length is +- correct; truncate of fill with blanks if needed. */ ++ correct; truncate or fill with blanks if needed. */ + if (this_comp->ts.type == BT_CHARACTER && !this_comp->attr.allocatable + && this_comp->ts.u.cl && this_comp->ts.u.cl->length + && this_comp->ts.u.cl->length->expr_type == EXPR_CONSTANT ++ && this_comp->ts.u.cl->length->ts.type == BT_INTEGER + && actual->expr->ts.type == BT_CHARACTER + && actual->expr->expr_type == EXPR_CONSTANT) + { +diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc +index 14baf63e6af..9264322f671 100644 +--- a/gcc/fortran/resolve.cc ++++ b/gcc/fortran/resolve.cc +@@ -965,8 +965,8 @@ resolve_common_vars (gfc_common_head *common_block, bool named_common) + + /* gfc_add_in_common may have been called before, but the reported errors + have been ignored to continue parsing. +- We do the checks again here. */ +- if (!csym->attr.use_assoc) ++ We do the checks again here, unless the symbol is USE associated. */ ++ if (!csym->attr.use_assoc && !csym->attr.used_in_submodule) + { + gfc_add_in_common (&csym->attr, csym->name, &common_block->where); + gfc_notify_std (GFC_STD_F2018_OBS, "COMMON block at %L", +@@ -9923,11 +9923,6 @@ resolve_select_rank (gfc_code *code, gfc_namespace *old_ns) + || gfc_expr_attr (code->expr1).pointer)) + gfc_error ("RANK (*) at %L cannot be used with the pointer or " + "allocatable selector at %L", &c->where, &code->expr1->where); +- +- if (case_value == -1 && (gfc_expr_attr (code->expr1).allocatable +- || gfc_expr_attr (code->expr1).pointer)) +- gfc_error ("RANK (*) at %L cannot be used with the pointer or " +- "allocatable selector at %L", &c->where, &code->expr1->where); + } + + /* Add EXEC_SELECT to switch on rank. */ +@@ -12913,7 +12908,10 @@ resolve_fl_var_and_proc (gfc_symbol *sym, int mp_flag) + + if (allocatable) + { +- if (dimension && as->type != AS_ASSUMED_RANK) ++ if (dimension ++ && as ++ && as->type != AS_ASSUMED_RANK ++ && !sym->attr.select_rank_temporary) + { + gfc_error ("Allocatable array %qs at %L must have a deferred " + "shape or assumed rank", sym->name, &sym->declared_at); +diff --git a/gcc/fortran/symbol.cc b/gcc/fortran/symbol.cc +index af5a2e41bf5..e7de5a8f525 100644 +--- a/gcc/fortran/symbol.cc ++++ b/gcc/fortran/symbol.cc +@@ -4719,6 +4719,13 @@ gfc_copy_formal_args_intr (gfc_symbol *dest, gfc_intrinsic_sym *src, + formal_arg->sym->attr.flavor = FL_VARIABLE; + formal_arg->sym->attr.dummy = 1; + ++ /* Do not treat an actual deferred-length character argument wrongly ++ as template for the formal argument. */ ++ if (formal_arg->sym->ts.type == BT_CHARACTER ++ && !(formal_arg->sym->attr.allocatable ++ || formal_arg->sym->attr.pointer)) ++ formal_arg->sym->ts.deferred = false; ++ + if (formal_arg->sym->ts.type == BT_CHARACTER) + formal_arg->sym->ts.u.cl = gfc_new_charlen (gfc_current_ns, NULL); + +diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc +index 057cb8a3041..27b34984705 100644 +--- a/gcc/fortran/trans-expr.cc ++++ b/gcc/fortran/trans-expr.cc +@@ -7428,7 +7428,12 @@ gfc_conv_procedure_call (gfc_se * se, gfc_symbol * sym, + (and other intrinsics?) and dummy functions. In the case of SPREAD, + we take the character length of the first argument for the result. + For dummies, we have to look through the formal argument list for +- this function and use the character length found there.*/ ++ this function and use the character length found there. ++ Likewise, we handle the case of deferred-length character dummy ++ arguments to intrinsics that determine the characteristics of ++ the result, which cannot be deferred-length. */ ++ if (expr->value.function.isym) ++ ts.deferred = false; + if (ts.deferred) + cl.backend_decl = gfc_create_var (gfc_charlen_type_node, "slen"); + else if (!sym->attr.dummy) +diff --git a/gcc/fwprop.cc b/gcc/fwprop.cc +index d12fc2f34ac..5451e663ad6 100644 +--- a/gcc/fwprop.cc ++++ b/gcc/fwprop.cc +@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3. If not see + #include "coretypes.h" + #include "backend.h" + #include "rtl.h" ++#include "rtlanal.h" + #include "df.h" + #include "rtl-ssa.h" + +@@ -353,21 +354,6 @@ reg_single_def_p (rtx x) + return REG_P (x) && crtl->ssa->single_dominating_def (REGNO (x)); + } + +-/* Return true if X contains a paradoxical subreg. */ +- +-static bool +-contains_paradoxical_subreg_p (rtx x) +-{ +- subrtx_var_iterator::array_type array; +- FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST) +- { +- x = *iter; +- if (SUBREG_P (x) && paradoxical_subreg_p (x)) +- return true; +- } +- return false; +-} +- + /* Try to substitute (set DEST SRC), which defines DEF, into note NOTE of + USE_INSN. Return the number of substitutions on success, otherwise return + -1 and leave USE_INSN unchanged. +diff --git a/gcc/genmatch.cc b/gcc/genmatch.cc +index 5b25fc8da86..80c64d88928 100644 +--- a/gcc/genmatch.cc ++++ b/gcc/genmatch.cc +@@ -2548,7 +2548,8 @@ expr::gen_transform (FILE *f, int indent, const char *dest, bool gimple, + { + fprintf_indent (f, indent, "if (TREE_TYPE (_o%d[0]) != %s)\n", + depth, type); +- indent += 2; ++ fprintf_indent (f, indent + 2, "{\n"); ++ indent += 4; + } + if (opr->kind == id_base::CODE) + fprintf_indent (f, indent, "_r%d = fold_build%d_loc (loc, %s, %s", +@@ -2571,7 +2572,8 @@ expr::gen_transform (FILE *f, int indent, const char *dest, bool gimple, + } + if (*opr == CONVERT_EXPR) + { +- indent -= 2; ++ fprintf_indent (f, indent - 2, "}\n"); ++ indent -= 4; + fprintf_indent (f, indent, "else\n"); + fprintf_indent (f, indent, " _r%d = _o%d[0];\n", depth, depth); + } +diff --git a/gcc/gimple-fold.cc b/gcc/gimple-fold.cc +index 863ee3d3912..010be0b2b89 100644 +--- a/gcc/gimple-fold.cc ++++ b/gcc/gimple-fold.cc +@@ -7770,12 +7770,11 @@ get_base_constructor (tree base, poly_int64_pod *bit_offset, + } + } + +-/* CTOR is CONSTRUCTOR of an array type. Fold a reference of SIZE bits +- to the memory at bit OFFSET. When non-null, TYPE is the expected +- type of the reference; otherwise the type of the referenced element +- is used instead. When SIZE is zero, attempt to fold a reference to +- the entire element which OFFSET refers to. Increment *SUBOFF by +- the bit offset of the accessed element. */ ++/* CTOR is a CONSTRUCTOR of an array or vector type. Fold a reference of SIZE ++ bits to the memory at bit OFFSET. If non-null, TYPE is the expected type of ++ the reference; otherwise the type of the referenced element is used instead. ++ When SIZE is zero, attempt to fold a reference to the entire element OFFSET ++ refers to. Increment *SUBOFF by the bit offset of the accessed element. */ + + static tree + fold_array_ctor_reference (tree type, tree ctor, +@@ -7940,13 +7939,11 @@ fold_array_ctor_reference (tree type, tree ctor, + return type ? build_zero_cst (type) : NULL_TREE; + } + +-/* CTOR is CONSTRUCTOR of an aggregate or vector. Fold a reference +- of SIZE bits to the memory at bit OFFSET. When non-null, TYPE +- is the expected type of the reference; otherwise the type of +- the referenced member is used instead. When SIZE is zero, +- attempt to fold a reference to the entire member which OFFSET +- refers to; in this case. Increment *SUBOFF by the bit offset +- of the accessed member. */ ++/* CTOR is a CONSTRUCTOR of a record or union type. Fold a reference of SIZE ++ bits to the memory at bit OFFSET. If non-null, TYPE is the expected type of ++ the reference; otherwise the type of the referenced member is used instead. ++ When SIZE is zero, attempt to fold a reference to the entire member OFFSET ++ refers to. Increment *SUBOFF by the bit offset of the accessed member. */ + + static tree + fold_nonarray_ctor_reference (tree type, tree ctor, +@@ -7958,8 +7955,7 @@ fold_nonarray_ctor_reference (tree type, tree ctor, + unsigned HOST_WIDE_INT cnt; + tree cfield, cval; + +- FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), cnt, cfield, +- cval) ++ FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), cnt, cfield, cval) + { + tree byte_offset = DECL_FIELD_OFFSET (cfield); + tree field_offset = DECL_FIELD_BIT_OFFSET (cfield); +@@ -8031,6 +8027,19 @@ fold_nonarray_ctor_reference (tree type, tree ctor, + return NULL_TREE; + + offset_int inner_offset = offset_int (offset) - bitoffset; ++ ++ /* Integral bit-fields are left-justified on big-endian targets, so ++ we must arrange for native_encode_int to start at their MSB. */ ++ if (DECL_BIT_FIELD (cfield) && INTEGRAL_TYPE_P (TREE_TYPE (cfield))) ++ { ++ if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN) ++ return NULL_TREE; ++ const unsigned int encoding_size ++ = GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE (TREE_TYPE (cfield))); ++ if (BYTES_BIG_ENDIAN) ++ inner_offset += encoding_size - wi::to_offset (field_size); ++ } ++ + return fold_ctor_reference (type, cval, + inner_offset.to_uhwi (), size, + from_decl, suboff); +@@ -8043,7 +8052,7 @@ fold_nonarray_ctor_reference (tree type, tree ctor, + return build_zero_cst (type); + } + +-/* CTOR is value initializing memory. Fold a reference of TYPE and ++/* CTOR is a value initializing memory. Fold a reference of TYPE and + bit size POLY_SIZE to the memory at bit POLY_OFFSET. When POLY_SIZE + is zero, attempt to fold a reference to the entire subobject + which OFFSET refers to. This is used when folding accesses to +@@ -8084,7 +8093,8 @@ fold_ctor_reference (tree type, tree ctor, const poly_uint64 &poly_offset, + } + return ret; + } +- /* For constants and byte-aligned/sized reads try to go through ++ ++ /* For constants and byte-aligned/sized reads, try to go through + native_encode/interpret. */ + if (CONSTANT_CLASS_P (ctor) + && BITS_PER_UNIT == 8 +@@ -8100,7 +8110,12 @@ fold_ctor_reference (tree type, tree ctor, const poly_uint64 &poly_offset, + if (len > 0) + return native_interpret_expr (type, buf, len); + } +- if (TREE_CODE (ctor) == CONSTRUCTOR) ++ ++ /* For constructors, try first a recursive local processing, but in any case ++ this requires the native storage order. */ ++ if (TREE_CODE (ctor) == CONSTRUCTOR ++ && !(AGGREGATE_TYPE_P (TREE_TYPE (ctor)) ++ && TYPE_REVERSE_STORAGE_ORDER (TREE_TYPE (ctor)))) + { + unsigned HOST_WIDE_INT dummy = 0; + if (!suboff) +@@ -8115,9 +8130,9 @@ fold_ctor_reference (tree type, tree ctor, const poly_uint64 &poly_offset, + ret = fold_nonarray_ctor_reference (type, ctor, offset, size, + from_decl, suboff); + +- /* Fall back to native_encode_initializer. Needs to be done +- only in the outermost fold_ctor_reference call (because it itself +- recurses into CONSTRUCTORs) and doesn't update suboff. */ ++ /* Otherwise fall back to native_encode_initializer. This may be done ++ only from the outermost fold_ctor_reference call (because it itself ++ recurses into CONSTRUCTORs and doesn't update suboff). */ + if (ret == NULL_TREE + && suboff == &dummy + && BITS_PER_UNIT == 8 +diff --git a/gcc/gimple-range-cache.cc b/gcc/gimple-range-cache.cc +index 421ea1a20ef..d42387443b6 100644 +--- a/gcc/gimple-range-cache.cc ++++ b/gcc/gimple-range-cache.cc +@@ -448,7 +448,7 @@ block_range_cache::set_bb_range (tree name, const_basic_block bb, + { + unsigned v = SSA_NAME_VERSION (name); + if (v >= m_ssa_ranges.length ()) +- m_ssa_ranges.safe_grow_cleared (num_ssa_names + 1); ++ m_ssa_ranges.safe_grow_cleared (num_ssa_names); + + if (!m_ssa_ranges[v]) + { +@@ -515,7 +515,7 @@ void + block_range_cache::dump (FILE *f) + { + unsigned x; +- for (x = 0; x < m_ssa_ranges.length (); ++x) ++ for (x = 1; x < m_ssa_ranges.length (); ++x) + { + if (m_ssa_ranges[x]) + { +@@ -538,9 +538,12 @@ block_range_cache::dump (FILE *f, basic_block bb, bool print_varying) + bool summarize_varying = false; + for (x = 1; x < m_ssa_ranges.length (); ++x) + { ++ if (!m_ssa_ranges[x]) ++ continue; ++ + if (!gimple_range_ssa_p (ssa_name (x))) + continue; +- if (m_ssa_ranges[x] && m_ssa_ranges[x]->get_bb_range (r, bb)) ++ if (m_ssa_ranges[x]->get_bb_range (r, bb)) + { + if (!print_varying && r.varying_p ()) + { +@@ -557,11 +560,14 @@ block_range_cache::dump (FILE *f, basic_block bb, bool print_varying) + if (summarize_varying) + { + fprintf (f, "VARYING_P on entry : "); +- for (x = 1; x < num_ssa_names; ++x) ++ for (x = 1; x < m_ssa_ranges.length (); ++x) + { ++ if (!m_ssa_ranges[x]) ++ continue; ++ + if (!gimple_range_ssa_p (ssa_name (x))) + continue; +- if (m_ssa_ranges[x] && m_ssa_ranges[x]->get_bb_range (r, bb)) ++ if (m_ssa_ranges[x]->get_bb_range (r, bb)) + { + if (r.varying_p ()) + { +diff --git a/gcc/gimple-range-gori.cc b/gcc/gimple-range-gori.cc +index 772ccb88d55..263360862fe 100644 +--- a/gcc/gimple-range-gori.cc ++++ b/gcc/gimple-range-gori.cc +@@ -880,6 +880,7 @@ gori_compute::logical_combine (irange &r, enum tree_code code, + res = false; + if (idx) + tracer.trailer (idx, "logical_combine", res, NULL_TREE, r); ++ return res; + } + + switch (code) +diff --git a/gcc/gimple-ssa-store-merging.cc b/gcc/gimple-ssa-store-merging.cc +index 5ec4a94ca70..48733e5f8cf 100644 +--- a/gcc/gimple-ssa-store-merging.cc ++++ b/gcc/gimple-ssa-store-merging.cc +@@ -4605,12 +4605,13 @@ imm_store_chain_info::output_merged_store (merged_store_group *group) + } + else if ((BYTES_BIG_ENDIAN ? start_gap : end_gap) > 0) + { +- const unsigned HOST_WIDE_INT imask +- = (HOST_WIDE_INT_1U << info->bitsize) - 1; ++ wide_int imask ++ = wi::mask (info->bitsize, false, ++ TYPE_PRECISION (TREE_TYPE (tem))); + tem = gimple_build (&seq, loc, + BIT_AND_EXPR, TREE_TYPE (tem), tem, +- build_int_cst (TREE_TYPE (tem), +- imask)); ++ wide_int_to_tree (TREE_TYPE (tem), ++ imask)); + } + const HOST_WIDE_INT shift + = (BYTES_BIG_ENDIAN ? end_gap : start_gap); +diff --git a/gcc/gimplify.cc b/gcc/gimplify.cc +index a551c574a2d..947fe570e1e 100644 +--- a/gcc/gimplify.cc ++++ b/gcc/gimplify.cc +@@ -6847,7 +6847,12 @@ gimplify_asm_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p) + stmt = gimple_build_asm_vec (TREE_STRING_POINTER (ASM_STRING (expr)), + inputs, outputs, clobbers, labels); + +- gimple_asm_set_volatile (stmt, ASM_VOLATILE_P (expr) || noutputs == 0); ++ /* asm is volatile if it was marked by the user as volatile or ++ there are no outputs or this is an asm goto. */ ++ gimple_asm_set_volatile (stmt, ++ ASM_VOLATILE_P (expr) ++ || noutputs == 0 ++ || labels); + gimple_asm_set_input (stmt, ASM_INPUT_P (expr)); + gimple_asm_set_inline (stmt, ASM_INLINE_P (expr)); + +diff --git a/gcc/go/ChangeLog b/gcc/go/ChangeLog +index 9d5675465a7..e0df7a5dfeb 100644 +--- a/gcc/go/ChangeLog ++++ b/gcc/go/ChangeLog +@@ -1,3 +1,11 @@ ++2023-06-28 Paul E. Murphy ++ ++ Backported from master: ++ 2023-06-22 Paul E. Murphy ++ ++ * go-backend.cc [TARGET_AIX]: Rename and update usage to TARGET_AIX_OS. ++ * go-lang.cc: Likewise. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/gcc/go/go-backend.cc b/gcc/go/go-backend.cc +index 7eed943416a..0a05a0b0645 100644 +--- a/gcc/go/go-backend.cc ++++ b/gcc/go/go-backend.cc +@@ -45,8 +45,8 @@ along with GCC; see the file COPYING3. If not see + #define GO_EXPORT_SECTION_NAME ".go_export" + #endif + +-#ifndef TARGET_AIX +-#define TARGET_AIX 0 ++#ifndef TARGET_AIX_OS ++#define TARGET_AIX_OS 0 + #endif + + /* This file holds all the cases where the Go frontend needs +@@ -107,7 +107,7 @@ go_write_export_data (const char *bytes, unsigned int size) + { + gcc_assert (targetm_common.have_named_sections); + sec = get_section (GO_EXPORT_SECTION_NAME, +- TARGET_AIX ? SECTION_EXCLUDE : SECTION_DEBUG, ++ TARGET_AIX_OS ? SECTION_EXCLUDE : SECTION_DEBUG, + NULL); + } + +diff --git a/gcc/go/go-lang.cc b/gcc/go/go-lang.cc +index c8365d2590a..89fba02026a 100644 +--- a/gcc/go/go-lang.cc ++++ b/gcc/go/go-lang.cc +@@ -39,8 +39,8 @@ along with GCC; see the file COPYING3. If not see + #include "go-c.h" + #include "go-gcc.h" + +-#ifndef TARGET_AIX +-#define TARGET_AIX 0 ++#ifndef TARGET_AIX_OS ++#define TARGET_AIX_OS 0 + #endif + + /* Language-dependent contents of a type. */ +@@ -119,9 +119,9 @@ go_langhook_init (void) + args.compiling_runtime = go_compiling_runtime; + args.debug_escape_level = go_debug_escape_level; + args.debug_escape_hash = go_debug_escape_hash; +- args.nil_check_size_threshold = TARGET_AIX ? -1 : 4096; ++ args.nil_check_size_threshold = TARGET_AIX_OS ? -1 : 4096; + args.debug_optimization = go_debug_optimization; +- args.need_eqtype = TARGET_AIX ? true : false; ++ args.need_eqtype = TARGET_AIX_OS ? true : false; + args.linemap = go_get_linemap(); + args.backend = go_get_backend(); + go_create_gogo (&args); +diff --git a/gcc/go/gofrontend/expressions.cc b/gcc/go/gofrontend/expressions.cc +index 1b3b3bf135e..88b4ceacc07 100644 +--- a/gcc/go/gofrontend/expressions.cc ++++ b/gcc/go/gofrontend/expressions.cc +@@ -12325,7 +12325,8 @@ Call_expression::intrinsify(Gogo* gogo, + return Runtime::make_call(code, loc, 3, a1, a2, a3); + } + } +- else if (package == "internal/abi") ++ else if (package == "internal/abi" ++ || package == "bootstrap/internal/abi") // for bootstrapping gc + { + if (is_method) + return NULL; +diff --git a/gcc/go/gofrontend/gogo.cc b/gcc/go/gofrontend/gogo.cc +index d35c6baf582..cca03dcdc35 100644 +--- a/gcc/go/gofrontend/gogo.cc ++++ b/gcc/go/gofrontend/gogo.cc +@@ -3331,6 +3331,9 @@ class Create_function_descriptors : public Traverse + int + expression(Expression**); + ++ static bool ++ skip_descriptor(Gogo* gogo, const Named_object*); ++ + private: + Gogo* gogo_; + }; +@@ -3341,6 +3344,9 @@ class Create_function_descriptors : public Traverse + int + Create_function_descriptors::function(Named_object* no) + { ++ if (Create_function_descriptors::skip_descriptor(this->gogo_, no)) ++ return TRAVERSE_CONTINUE; ++ + if (no->is_function() + && no->func_value()->enclosing() == NULL + && !no->func_value()->is_method() +@@ -3428,6 +3434,28 @@ Create_function_descriptors::expression(Expression** pexpr) + return TRAVERSE_CONTINUE; + } + ++// The gc compiler has some special cases that it always compiles as ++// intrinsics. For those we don't want to generate a function ++// descriptor, as there will be no code for it to refer to. ++ ++bool ++Create_function_descriptors::skip_descriptor(Gogo* gogo, ++ const Named_object* no) ++{ ++ const std::string& pkgpath(no->package() == NULL ++ ? gogo->pkgpath() ++ : no->package()->pkgpath()); ++ ++ // internal/abi is the standard library package, ++ // bootstrap/internal/abi is the name used when bootstrapping the gc ++ // compiler. ++ ++ return ((pkgpath == "internal/abi" ++ || pkgpath == "bootstrap/internal/abi") ++ && (no->name() == "FuncPCABI0" ++ || no->name() == "FuncPCABIInternal")); ++} ++ + // Create function descriptors as needed. We need a function + // descriptor for all exported functions and for all functions that + // are referenced without being called. +@@ -3449,7 +3477,8 @@ Gogo::create_function_descriptors() + if (no->is_function_declaration() + && !no->func_declaration_value()->type()->is_method() + && !Linemap::is_predeclared_location(no->location()) +- && !Gogo::is_hidden_name(no->name())) ++ && !Gogo::is_hidden_name(no->name()) ++ && !Create_function_descriptors::skip_descriptor(this, no)) + fndecls.push_back(no); + } + for (std::vector::const_iterator p = fndecls.begin(); +diff --git a/gcc/lra-eliminations.cc b/gcc/lra-eliminations.cc +index c630ff4af2d..7642d9857a8 100644 +--- a/gcc/lra-eliminations.cc ++++ b/gcc/lra-eliminations.cc +@@ -397,8 +397,8 @@ lra_eliminate_regs_1 (rtx_insn *insn, rtx x, machine_mode mem_mode, + rtx to = subst_p ? ep->to_rtx : ep->from_rtx; + + if (! update_p && ! full_p) +- return gen_rtx_PLUS (Pmode, to, XEXP (x, 1)); +- ++ return simplify_gen_binary (PLUS, Pmode, to, XEXP (x, 1)); ++ + if (maybe_ne (update_sp_offset, 0)) + offset = ep->to_rtx == stack_pointer_rtx ? update_sp_offset : 0; + else +diff --git a/gcc/match.pd b/gcc/match.pd +index fc2833bbdca..a9aae484b2b 100644 +--- a/gcc/match.pd ++++ b/gcc/match.pd +@@ -1723,7 +1723,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + /* (x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2) */ + (simplify + (bit_and (bit_ior @0 CONSTANT_CLASS_P@1) CONSTANT_CLASS_P@2) +- (bit_ior (bit_and @0 @2) (bit_and @1 @2))) ++ (bit_ior (bit_and @0 @2) (bit_and! @1 @2))) + + /* Combine successive equal operations with constants. */ + (for bitop (bit_and bit_ior bit_xor) +@@ -1732,7 +1732,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + (if (!CONSTANT_CLASS_P (@0)) + /* This is the canonical form regardless of whether (bitop @1 @2) can be + folded to a constant. */ +- (bitop @0 (bitop @1 @2)) ++ (bitop @0 (bitop! @1 @2)) + /* In this case we have three constants and (bitop @0 @1) doesn't fold + to a constant. This can happen if @0 or @1 is a POLY_INT_CST and if + the values involved are such that the operation can't be decided at +@@ -2635,13 +2635,13 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + forever if something doesn't simplify into a constant. */ + (if (!CONSTANT_CLASS_P (@0)) + (if (outer_op == PLUS_EXPR) +- (plus (view_convert @0) (inner_op @2 (view_convert @1))) +- (minus (view_convert @0) (neg_inner_op @2 (view_convert @1))))) ++ (plus (view_convert @0) (inner_op! @2 (view_convert @1))) ++ (minus (view_convert @0) (neg_inner_op! @2 (view_convert @1))))) + (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0)) + || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0))) + (if (outer_op == PLUS_EXPR) +- (view_convert (plus @0 (inner_op (view_convert @2) @1))) +- (view_convert (minus @0 (neg_inner_op (view_convert @2) @1)))) ++ (view_convert (plus @0 (inner_op! (view_convert @2) @1))) ++ (view_convert (minus @0 (neg_inner_op! (view_convert @2) @1)))) + /* If the constant operation overflows we cannot do the transform + directly as we would introduce undefined overflow, for example + with (a - 1) + INT_MIN. */ +@@ -2672,10 +2672,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + /* If all 3 captures are CONSTANT_CLASS_P, punt, as we might recurse + forever if something doesn't simplify into a constant. */ + (if (!CONSTANT_CLASS_P (@0)) +- (minus (outer_op (view_convert @1) @2) (view_convert @0))) ++ (minus (outer_op! (view_convert @1) @2) (view_convert @0))) + (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0)) + || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0))) +- (view_convert (minus (outer_op @1 (view_convert @2)) @0)) ++ (view_convert (minus (outer_op! @1 (view_convert @2)) @0)) + (if (types_match (type, @0)) + (with { tree cst = const_binop (outer_op, type, @1, @2); } + (if (cst && !TREE_OVERFLOW (cst)) +@@ -2691,10 +2691,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + /* If all 3 captures are CONSTANT_CLASS_P, punt, as we might recurse + forever if something doesn't simplify into a constant. */ + (if (!CONSTANT_CLASS_P (@0)) +- (plus (view_convert @0) (minus @1 (view_convert @2)))) ++ (plus (view_convert @0) (minus! @1 (view_convert @2)))) + (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0)) + || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0))) +- (view_convert (plus @0 (minus (view_convert @1) @2))) ++ (view_convert (plus @0 (minus! (view_convert @1) @2))) + (if (types_match (type, @0)) + (with { tree cst = const_binop (MINUS_EXPR, type, @1, @2); } + (if (cst && !TREE_OVERFLOW (cst)) +@@ -3711,19 +3711,19 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + int inside_ptr = POINTER_TYPE_P (inside_type); + int inside_float = FLOAT_TYPE_P (inside_type); + int inside_vec = VECTOR_TYPE_P (inside_type); +- unsigned int inside_prec = TYPE_PRECISION (inside_type); ++ unsigned int inside_prec = element_precision (inside_type); + int inside_unsignedp = TYPE_UNSIGNED (inside_type); + int inter_int = INTEGRAL_TYPE_P (inter_type); + int inter_ptr = POINTER_TYPE_P (inter_type); + int inter_float = FLOAT_TYPE_P (inter_type); + int inter_vec = VECTOR_TYPE_P (inter_type); +- unsigned int inter_prec = TYPE_PRECISION (inter_type); ++ unsigned int inter_prec = element_precision (inter_type); + int inter_unsignedp = TYPE_UNSIGNED (inter_type); + int final_int = INTEGRAL_TYPE_P (type); + int final_ptr = POINTER_TYPE_P (type); + int final_float = FLOAT_TYPE_P (type); + int final_vec = VECTOR_TYPE_P (type); +- unsigned int final_prec = TYPE_PRECISION (type); ++ unsigned int final_prec = element_precision (type); + int final_unsignedp = TYPE_UNSIGNED (type); + } + (switch +@@ -4186,6 +4186,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + /* (v ? w : 0) ? a : b is just (v & w) ? a : b + Currently disabled after pass lvec because ARM understands + VEC_COND_EXPR but not a plain v==w fed to BIT_IOR_EXPR. */ ++#if GIMPLE ++/* These can only be done in gimple as fold likes to convert: ++ (CMP) & N into (CMP) ? N : 0 ++ and we try to match the same pattern again and again. */ + (simplify + (vec_cond (vec_cond:s @0 @3 integer_zerop) @1 @2) + (if (optimize_vectors_before_lowering_p () && types_match (@0, @3)) +@@ -4220,6 +4224,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + (vec_cond @0 @3 (vec_cond:s @1 @2 @3)) + (if (optimize_vectors_before_lowering_p () && types_match (@0, @1)) + (vec_cond (bit_and (bit_not @0) @1) @2 @3))) ++#endif + + /* Canonicalize mask ? { 0, ... } : { -1, ...} to ~mask if the mask + types are compatible. */ +diff --git a/gcc/omp-expand.cc b/gcc/omp-expand.cc +index c3d6447440d..09190a79ab2 100644 +--- a/gcc/omp-expand.cc ++++ b/gcc/omp-expand.cc +@@ -2564,7 +2564,8 @@ expand_omp_for_init_vars (struct omp_for_data *fd, gimple_stmt_iterator *gsi, + tree factor = fd->factor; + gcond *cond_stmt + = expand_omp_build_cond (gsi, NE_EXPR, factor, +- build_zero_cst (TREE_TYPE (factor))); ++ build_zero_cst (TREE_TYPE (factor)), ++ true); + edge e = split_block (gsi_bb (*gsi), cond_stmt); + basic_block bb0 = e->src; + e->flags = EDGE_TRUE_VALUE; +diff --git a/gcc/rtlanal.cc b/gcc/rtlanal.cc +index c436c640c37..78a740cb54b 100644 +--- a/gcc/rtlanal.cc ++++ b/gcc/rtlanal.cc +@@ -6990,3 +6990,18 @@ vec_series_lowpart_p (machine_mode result_mode, machine_mode op_mode, rtx sel) + } + return false; + } ++ ++/* Return true if X contains a paradoxical subreg. */ ++ ++bool ++contains_paradoxical_subreg_p (rtx x) ++{ ++ subrtx_var_iterator::array_type array; ++ FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST) ++ { ++ x = *iter; ++ if (SUBREG_P (x) && paradoxical_subreg_p (x)) ++ return true; ++ } ++ return false; ++} +diff --git a/gcc/rtlanal.h b/gcc/rtlanal.h +index 9fd84a74fc3..606d2047265 100644 +--- a/gcc/rtlanal.h ++++ b/gcc/rtlanal.h +@@ -338,4 +338,6 @@ vec_series_highpart_p (machine_mode result_mode, machine_mode op_mode, + bool + vec_series_lowpart_p (machine_mode result_mode, machine_mode op_mode, rtx sel); + ++bool ++contains_paradoxical_subreg_p (rtx x); + #endif +diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog +index c2333b51c6e..51f12cc7709 100644 +--- a/gcc/testsuite/ChangeLog ++++ b/gcc/testsuite/ChangeLog +@@ -1,3 +1,5056 @@ ++2023-12-24 Patrick Palka ++ ++ Backported from master: ++ 2023-09-22 Patrick Palka ++ ++ PR c++/111485 ++ * g++.dg/cpp2a/concepts-ttp5.C: New test. ++ * g++.dg/cpp2a/concepts-ttp6.C: New test. ++ ++2023-12-20 Patrick Palka ++ ++ Backported from master: ++ 2023-04-25 Patrick Palka ++ ++ PR c++/108975 ++ * g++.dg/cpp0x/lambda/lambda-const11a.C: New test. ++ ++2023-12-19 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-19 Jakub Jelinek ++ ++ PR target/112816 ++ * gcc.target/i386/sse2-pr112816-2.c: New test. ++ ++2023-12-18 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-18 Jakub Jelinek ++ ++ PR tree-optimization/113013 ++ * gcc.dg/pr113013.c: New test. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-08 Jakub Jelinek ++ ++ PR sanitizer/112727 ++ * c-c++-common/ubsan/pr112727.c: New test. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-11-29 Jakub Jelinek ++ ++ PR middle-end/112733 ++ * gcc.dg/pr112733.c: New test. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-05 Jakub Jelinek ++ ++ PR target/112845 ++ * gcc.dg/pr112845.c: New file. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-04 Jakub Jelinek ++ ++ PR target/112837 ++ * gcc.dg/pr112837.c: New test. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-04 Jakub Jelinek ++ ++ PR target/112816 ++ * gcc.target/i386/sse2-pr112816.c: New test. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-12-04 Jakub Jelinek ++ ++ PR c++/112795 ++ * g++.dg/ext/unroll-5.C: New test. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-11-25 Jakub Jelinek ++ ++ PR target/111408 ++ * gcc.c-torture/execute/pr111408.c: New test. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-11-13 Jakub Jelinek ++ ++ PR tree-optimization/111967 ++ * gcc.dg/tree-ssa/pr111967.c: New test. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-11-09 Jakub Jelinek ++ ++ PR c/112339 ++ * c-c++-common/ubsan/Wno-attributes-1.c: New test. ++ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-07-19 Jakub Jelinek ++ ++ PR tree-optimization/110731 ++ * gcc.dg/pr110731.c: New test. ++ ++2023-12-15 Richard Biener ++ ++ Backported from master: ++ 2023-08-24 Richard Biener ++ ++ PR debug/111080 ++ * gcc.dg/debug/dwarf2/pr111080.c: New testcase. ++ ++2023-12-15 Richard Biener ++ ++ Backported from master: ++ 2023-08-25 Richard Biener ++ ++ PR tree-optimization/111137 ++ * gcc.dg/torture/pr111137.c: New testcase. ++ ++2023-12-15 Richard Biener ++ ++ Backported from master: ++ 2023-08-31 Richard Biener ++ ++ PR middle-end/111253 ++ * gcc.dg/Wfree-nonheap-object-7.c: New testcase. ++ ++2023-12-12 liuhongt ++ ++ Backported from master: ++ 2023-12-12 liuhongt ++ ++ * gcc.target/i386/pr112891.c: New test. ++ * gcc.target/i386/pr112891-2.c: New test. ++ ++2023-12-01 Harald Anlauf ++ ++ Backported from master: ++ 2023-11-26 Harald Anlauf ++ ++ PR fortran/111880 ++ * gfortran.dg/pr111880.f90: New test. ++ ++2023-11-27 Patrick Palka ++ ++ Backported from master: ++ 2023-11-16 Patrick Palka ++ ++ PR c++/111703 ++ PR c++/107939 ++ * g++.dg/cpp2a/concepts-fn8.C: Extend test. ++ * g++.dg/diagnostic/constexpr4.C: New test. ++ ++2023-11-27 Patrick Palka ++ ++ Backported from master: ++ 2023-11-15 Patrick Palka ++ ++ PR c++/111703 ++ PR c++/112269 ++ * g++.dg/cpp2a/concepts-fn8.C: New test. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-10-23 Richard Biener ++ ++ PR tree-optimization/111917 ++ * gcc.dg/torture/pr111917.c: New testcase. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-10-17 Richard Biener ++ ++ PR middle-end/111818 ++ * gcc.dg/torture/pr111818.c: New testcase. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-09-28 Richard Biener ++ ++ PR tree-optimization/111614 ++ * gcc.dg/torture/pr111614.c: New testcase. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-10-12 Richard Biener ++ ++ PR tree-optimization/111764 ++ * gcc.dg/vect/pr111764.c: New testcase. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-10-20 Richard Biener ++ ++ PR tree-optimization/111445 ++ * gcc.dg/torture/pr111445.c: New testcase. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-08-18 Richard Biener ++ ++ PR tree-optimization/111019 ++ * g++.dg/torture/pr111019.C: New testcase. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-08-03 Richard Biener ++ ++ PR tree-optimization/110702 ++ * gcc.dg/torture/pr110702.c: New testcase. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-07-06 Richard Biener ++ ++ PR tree-optimization/110556 ++ * gcc.dg/torture/pr110556.c: New testcase. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-07-06 Richard Biener ++ ++ PR tree-optimization/110515 ++ * g++.dg/opt/pr110515.C: New testcase. ++ ++2023-11-27 Richard Biener ++ ++ Backported from master: ++ 2023-06-20 Richard Biener ++ ++ PR debug/110295 ++ * g++.dg/debug/pr110295.C: New testcase. ++ ++2023-11-24 Uros Bizjak ++ ++ Backported from master: ++ 2023-11-23 Uros Bizjak ++ ++ PR target/112672 ++ * gcc.target/i386/pr112672.c: New test. ++ ++2023-11-22 Maciej W. Rozycki ++ ++ Backported from master: ++ 2023-11-22 Maciej W. Rozycki ++ ++ PR target/111815 ++ * gcc.dg/torture/pr111815.c: New test. ++ ++2023-11-17 Jason Merrill ++ ++ PR c++/112301 ++ PR c++/102191 ++ PR c++/33799 ++ * g++.dg/eh/return1.C: Add more cases. ++ ++2023-11-17 Jason Merrill ++ ++ PR c++/33799 ++ * g++.dg/eh/return1.C: Add label cases. ++ ++2023-11-16 Eric Botcazou ++ ++ * gnat.dg/varsize4.adb (Func): Initialize Byte_Read parameter. ++ ++2023-11-16 Eric Botcazou ++ ++ * gnat.dg/varsize4.ads, gnat.dg/varsize4.adb: New test. ++ * gnat.dg/varsize4_pkg.ads: New helper. ++ ++2023-11-16 Xi Ruoyao ++ ++ Backported from master: ++ 2023-11-15 Xi Ruoyao ++ ++ * gcc.target/loongarch/cas-acquire.c: New test. ++ ++2023-11-15 Kewen Lin ++ ++ Backported from master: ++ 2023-11-06 Kewen Lin ++ ++ PR target/111828 ++ * lib/target-supports.exp ++ (check_effective_target_powerpc_as_p10_htm): New proc. ++ * g++.target/powerpc/pr111828-1.C: New test. ++ * g++.target/powerpc/pr111828-2.C: New test. ++ ++2023-11-10 liuhongt ++ ++ Backported from master: ++ 2023-11-10 liuhongt ++ ++ * g++.target/i386/pr112443.C: New test. ++ ++2023-10-29 Iain Buclaw ++ ++ Backported from master: ++ 2023-10-29 Iain Buclaw ++ ++ PR d/110712 ++ * gdc.dg/pr110712.d: New test. ++ ++2023-10-28 Iain Buclaw ++ ++ Backported from master: ++ 2023-10-28 Iain Buclaw ++ ++ PR d/112270 ++ * gdc.dg/pr112270.d: New test. ++ ++2023-10-26 chenxiaolong ++ ++ Backported from master: ++ 2023-10-25 chenxiaolong ++ ++ * gcc.target/loongarch/builtin_thread_pointer.c: New test. ++ ++2023-10-26 liuhongt ++ ++ Backported from master: ++ 2023-07-06 liuhongt ++ ++ * gcc.target/i386/pr110170-3.c: New test. ++ ++2023-10-23 Kewen Lin ++ ++ Backported from master: ++ 2023-10-12 Kewen Lin ++ ++ PR target/111367 ++ * g++.target/powerpc/pr111367.C: New test. ++ ++2023-10-21 Harald Anlauf ++ ++ Backported from master: ++ 2023-10-17 Harald Anlauf ++ ++ PR fortran/111837 ++ * gfortran.dg/implied_do_io_8.f90: New test. ++ ++2023-10-16 Kewen Lin ++ ++ Backported from master: ++ 2023-09-25 Kewen Lin ++ ++ PR target/111380 ++ * gcc.target/powerpc/pr111380-1.c: New test. ++ * gcc.target/powerpc/pr111380-2.c: New test. ++ ++2023-10-16 Kewen Lin ++ ++ Backported from master: ++ 2023-09-25 Kewen Lin ++ ++ PR target/111366 ++ * g++.target/powerpc/pr111366.C: New test. ++ ++2023-10-07 Andrew Pinski ++ ++ Backported from master: ++ 2023-10-06 Andrew Pinski ++ ++ PR middle-end/111699 ++ * gcc.c-torture/compile/pr111699-1.c: New test. ++ ++2023-10-02 Pat Haugen ++ ++ Backported from master: ++ 2023-09-19 Pat Haugen ++ ++ * gcc.target/powerpc/clone1.c: Add xfails. ++ * gcc.target/powerpc/clone3.c: Likewise. ++ * gcc.target/powerpc/mod-1.c: Update scan strings and add xfails. ++ * gcc.target/powerpc/mod-2.c: Likewise. ++ * gcc.target/powerpc/p10-vdivq-vmodq.c: Add xfails. ++ ++2023-09-29 Wilco Dijkstra ++ ++ Backported from master: ++ 2023-09-28 Wilco Dijkstra ++ ++ PR target/111121 ++ * gcc.target/aarch64/mops_4.c: Add memmove testcases. ++ ++2023-09-26 Eric Botcazou ++ ++ * gnat.dg/opt102.adb:New test. ++ * gnat.dg/opt102_pkg.adb, gnat.dg/opt102_pkg.ads: New helper. ++ ++2023-09-20 Richard Sandiford ++ ++ Backported from master: ++ 2023-09-15 Richard Sandiford ++ ++ PR target/111411 ++ * gcc.dg/rtl/aarch64/pr111411.c: New test. ++ ++2023-09-12 Uros Bizjak ++ ++ PR target/111340 ++ * gcc.target/i386/pr111340.c: New test. ++ ++2023-09-12 Richard Sandiford ++ ++ * gcc.target/aarch64/stack-protector-8.c: New test. ++ * gcc.target/aarch64/stack-protector-9.c: Likewise. ++ ++2023-09-12 Richard Sandiford ++ ++ * gcc.target/aarch64/sve/pcs/stack_clash_3.c: Avoid redundant probes. ++ ++2023-09-12 Richard Sandiford ++ ++ * gcc.target/aarch64/stack-check-prologue-17.c: Expect the probe ++ to be at offset 1024 rather than offset 0. ++ * gcc.target/aarch64/stack-check-prologue-18.c: Likewise. ++ * gcc.target/aarch64/stack-check-prologue-19.c: Likewise. ++ ++2023-09-12 Richard Sandiford ++ ++ * gcc.target/aarch64/stack-check-prologue-18.c: New test. ++ * gcc.target/aarch64/stack-check-prologue-19.c: Likewise. ++ * gcc.target/aarch64/stack-check-prologue-20.c: Likewise. ++ ++2023-09-12 Richard Sandiford ++ ++ * gcc.target/aarch64/stack-check-prologue-17.c: New test. ++ ++2023-09-12 Haochen Gui ++ ++ Backported from master: ++ 2023-08-31 Haochen Gui ++ ++ PR target/96762 ++ * gcc.target/powerpc/pr96762.c: New. ++ ++2023-09-11 liuhongt ++ ++ Backported from master: ++ 2023-09-11 liuhongt ++ ++ * gcc.target/i386/pr111306.c: New test. ++ ++2023-08-30 Jakub Jelinek ++ ++ Backported from master: ++ 2023-08-30 Jakub Jelinek ++ ++ PR tree-optimization/110914 ++ * gcc.c-torture/execute/pr110914.c: New test. ++ ++2023-08-30 Jakub Jelinek ++ ++ Backported from master: ++ 2023-08-30 Jakub Jelinek ++ ++ PR tree-optimization/111015 ++ * gcc.dg/pr111015.c: New test. ++ ++2023-08-16 liuhongt ++ ++ Backported from master: ++ 2023-08-16 liuhongt ++ ++ * gcc.target/i386/avx2-gather-2.c: Adjust options to keep ++ gather vectorization. ++ * gcc.target/i386/avx2-gather-6.c: Ditto. ++ * gcc.target/i386/avx512f-pr88464-1.c: Ditto. ++ * gcc.target/i386/avx512f-pr88464-5.c: Ditto. ++ * gcc.target/i386/avx512vl-pr88464-1.c: Ditto. ++ * gcc.target/i386/avx512vl-pr88464-11.c: Ditto. ++ * gcc.target/i386/avx512vl-pr88464-3.c: Ditto. ++ * gcc.target/i386/avx512vl-pr88464-9.c: Ditto. ++ * gcc.target/i386/pr88531-1b.c: Ditto. ++ * gcc.target/i386/pr88531-1c.c: Ditto. ++ ++2023-08-15 Iain Buclaw ++ ++ PR d/110959 ++ * gdc.dg/pr110959.d: New test. ++ * gdc.test/runnable/test23010.d: New test. ++ ++2023-08-11 Jason Merrill ++ ++ PR c++/106310 ++ * g++.dg/template/template-keyword4.C: New test. ++ ++2023-08-11 Jason Merrill ++ ++ PR c++/106890 ++ PR c++/109666 ++ * g++.dg/cpp0x/nsdmi-array2.C: New test. ++ * g++.dg/cpp0x/nsdmi-template25.C: New test. ++ ++2023-08-11 Jason Merrill ++ ++ PR c++/108099 ++ * g++.dg/ext/int128-7.C: New test. ++ * g++.dg/ext/int128-8.C: New test. ++ * g++.dg/ext/unsigned-typedef2.C: New test. ++ * g++.dg/ext/unsigned-typedef3.C: New test. ++ ++2023-08-07 Patrick Palka ++ ++ Backported from master: ++ 2023-05-09 Patrick Palka ++ ++ PR c++/109761 ++ * g++.dg/cpp0x/noexcept78.C: New test. ++ ++2023-08-06 Jakub Jelinek ++ ++ Backported from master: ++ 2022-12-19 Jakub Jelinek ++ ++ PR fortran/107397 ++ * gfortran.dg/pr107397.f90: Adjust expected diagnostic wording and ++ add space between dg-error string and closing }. ++ ++2023-08-06 Steve Kargl ++ ++ Backported from master: ++ 2022-12-18 Steve Kargl ++ ++ PR fortran/107397 ++ * gfortran.dg/pr107397.f90: New test. ++ ++2023-08-01 Kewen Lin ++ ++ Backported from master: ++ 2023-07-26 Kewen Lin ++ ++ PR target/110741 ++ * g++.target/powerpc/pr110741.C: New test. ++ ++2023-07-20 Harald Anlauf ++ ++ Backported from master: ++ 2023-07-17 Harald Anlauf ++ ++ PR fortran/95947 ++ PR fortran/110658 ++ * gfortran.dg/deferred_character_37.f90: New test. ++ ++2023-07-19 Maciej W. Rozycki ++ ++ Backported from master: ++ 2023-07-11 Maciej W. Rozycki ++ ++ * gcc.dg/vect/pr97428.c: Limit to `vect_double' targets. ++ ++2023-07-14 Uros Bizjak ++ ++ Backported from master: ++ 2023-07-14 Uros Bizjak ++ ++ PR target/110206 ++ * gcc.target/i386/pr110206.c: New test. ++ ++2023-07-14 Harald Anlauf ++ ++ Backported from master: ++ 2023-07-11 Harald Anlauf ++ ++ PR fortran/110288 ++ * gfortran.dg/findloc_10.f90: New test. ++ ++2023-07-13 Uros Bizjak ++ ++ Backported from master: ++ 2023-07-13 Uros Bizjak ++ ++ PR target/106966 ++ * gcc.target/alpha/pr106966.c: New test. ++ ++2023-07-12 Patrick Palka ++ ++ Backported from master: ++ 2023-06-29 Patrick Palka ++ ++ PR c++/110468 ++ * g++.dg/cpp0x/noexcept79.C: New test. ++ ++2023-07-08 Harald Anlauf ++ ++ Backported from master: ++ 2023-07-08 Harald Anlauf ++ ++ PR fortran/110585 ++ * gfortran.dg/findloc_9.f90: New test. ++ ++2023-07-07 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-07 Iain Buclaw ++ ++ PR d/108842 ++ * gdc.dg/pr98277.d: Add more tests. ++ * gdc.dg/pr108842.d: New test. ++ ++2023-07-05 Michael Meissner ++ ++ Backported from master: ++ 2023-06-23 Michael Meissner ++ Aaron Sawdey ++ ++ PR target/105325 ++ * g++.target/powerpc/pr105325.C: New test. ++ * gcc.target/powerpc/fusion-p10-ldcmpi.c: Update insn counts. ++ ++2023-07-02 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-02 Iain Buclaw ++ ++ PR d/110516 ++ * gdc.dg/torture/pr110516a.d: New test. ++ * gdc.dg/torture/pr110516b.d: New test. ++ ++2023-07-01 Iain Buclaw ++ ++ Backported from master: ++ 2023-07-01 Iain Buclaw ++ ++ PR d/110514 ++ * gdc.dg/pr110514a.d: New test. ++ * gdc.dg/pr110514b.d: New test. ++ * gdc.dg/pr110514c.d: New test. ++ * gdc.dg/pr110514d.d: New test. ++ ++2023-06-30 Eric Botcazou ++ ++ * gcc.c-torture/execute/20230630-1.c: New test. ++ * gcc.c-torture/execute/20230630-2.c: Likewise. ++ * gcc.c-torture/execute/20230630-3.c: Likewise ++ * gcc.c-torture/execute/20230630-4.c: Likewise ++ ++2023-06-29 liuhongt ++ ++ * gcc.target/i386/pr110309.c: New test. ++ ++2023-06-29 Hongyu Wang ++ ++ Backported from master: ++ 2023-06-26 Hongyu Wang ++ ++ * gcc.target/i386/mvc17.c: New test. ++ ++2023-06-28 liuhongt ++ ++ * gcc.target/i386/avx-vzeroupper-29.c: New testcase. ++ * gcc.target/i386/avx-vzeroupper-12.c: Adjust testcase. ++ * gcc.target/i386/avx-vzeroupper-7.c: Ditto. ++ * gcc.target/i386/avx-vzeroupper-9.c: Ditto. ++ ++2023-06-27 Andrew Pinski ++ ++ Backported from master: ++ 2023-06-27 Andrew Pinski ++ ++ PR middle-end/110420 ++ PR middle-end/103979 ++ PR middle-end/98619 ++ * gcc.c-torture/compile/asmgoto-6.c: New test. ++ ++2023-06-26 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-26 Iain Buclaw ++ ++ PR d/110359 ++ * gdc.dg/pr110359.d: New test. ++ ++2023-06-26 Iain Buclaw ++ ++ Backported from master: ++ 2023-06-26 Iain Buclaw ++ ++ PR d/110113 ++ * gdc.test/compilable/test23978.d: New test. ++ ++2023-06-23 Richard Biener ++ ++ Backported from master: ++ 2023-06-19 Richard Biener ++ ++ PR tree-optimization/110298 ++ * gcc.dg/torture/pr110298.c: New testcase. ++ ++2023-06-22 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110132 ++ * lib/target-supports.exp (check_effective_target_aarch64_asm_FUNC_ok): ++ Extend to ls64. ++ * g++.target/aarch64/acle/acle.exp: New. ++ * g++.target/aarch64/acle/ls64.C: New test. ++ * g++.target/aarch64/acle/ls64_lto.C: New test. ++ * gcc.target/aarch64/acle/ls64_lto.c: New test. ++ * gcc.target/aarch64/acle/pr110132.c: New test. ++ ++2023-06-22 Alex Coplan ++ ++ Backported from master: ++ 2023-06-07 Alex Coplan ++ ++ PR target/110100 ++ * gcc.target/aarch64/acle/pr110100.c: New test. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-13 Kewen Lin ++ ++ PR testsuite/110230 ++ PR target/109932 ++ * gcc.target/powerpc/pr109932-1.c: Adjust with int128 effective target. ++ * gcc.target/powerpc/pr109932-2.c: Ditto. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-12 Kewen Lin ++ ++ PR target/109932 ++ * gcc.target/powerpc/pr109932-1.c: New test. ++ * gcc.target/powerpc/pr109932-2.c: New test. ++ ++2023-06-20 Kewen Lin ++ ++ Backported from master: ++ 2023-06-12 Kewen Lin ++ ++ PR target/110011 ++ * gcc.target/powerpc/pr110011.c: New test. ++ ++2023-06-15 Xi Ruoyao ++ ++ Backported from master: ++ 2023-03-07 Xi Ruoyao ++ ++ * gcc.target/aarch64/shrink_wrap_1.c (dg-options): Add ++ -fno-stack-protector. ++ * gcc.target/aarch64/stack-check-cfa-1.c (dg-options): Add ++ -fno-stack-protector. ++ * gcc.target/aarch64/stack-check-cfa-2.c (dg-options): Add ++ -fno-stack-protector. ++ * gcc.target/aarch64/test_frame_17.c (dg-options): Add ++ -fno-stack-protector. ++ ++2023-06-15 Xi Ruoyao ++ ++ Backported from master: ++ 2023-03-07 Xi Ruoyao ++ ++ * gcc.target/aarch64/pr104005.c (dg-options): Add ++ -fno-stack-protector. ++ ++2023-06-15 Xi Ruoyao ++ ++ Backported from master: ++ 2023-03-07 Xi Ruoyao ++ ++ * gcc.target/aarch64/auto-init-7.c (dg-options): Add ++ -fno-stack-protector. ++ ++2023-06-15 Xi Ruoyao ++ ++ Backported from master: ++ 2023-03-07 Xi Ruoyao ++ ++ * gcc.target/aarch64/pr103147-10.c (dg-options): Add ++ -fno-stack-protector. ++ * g++.target/aarch64/pr103147-10.C: Likewise. ++ ++2023-06-15 Xi Ruoyao ++ ++ Backported from master: ++ 2023-03-07 Xi Ruoyao ++ ++ * gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp (sve_flags): ++ Add -fno-stack-protector. ++ ++2023-06-15 Xi Ruoyao ++ ++ Backported from master: ++ 2023-03-07 Xi Ruoyao ++ ++ PR testsuite/70150 ++ * gcc.target/aarch64/fuse_adrp_add_1.c (dg-options): Add ++ -fno-pie. ++ ++2023-06-15 Xi Ruoyao ++ ++ Backported from master: ++ 2023-03-07 Xi Ruoyao ++ ++ PR testsuite/70150 ++ * gcc.dg/tls/pr78796.c (dg-additional-options): Add -fno-pie ++ -no-pie for aarch64-*-*. ++ * gcc.target/aarch64/pr63304_1.c (dg-options): Add -fno-pie. ++ * gcc.target/aarch64/pr70120-2.c (dg-options): Add -fno-pie. ++ * gcc.target/aarch64/pr78733.c (dg-options): Add -fno-pie. ++ * gcc.target/aarch64/pr79041-2.c (dg-options): Add -fno-pie. ++ * gcc.target/aarch64/pr94530.c (dg-options): Add -fno-pie. ++ * gcc.target/aarch64/pr94577.c (dg-options): Add -fno-pie. ++ * gcc.target/aarch64/reload-valid-spoff.c (dg-options): Add ++ -fno-pie. ++ ++2023-06-15 Xi Ruoyao ++ ++ Backported from master: ++ 2023-03-07 Xi Ruoyao ++ ++ PR testsuite/70150 ++ * gcc.target/aarch64/aapcs64/aapcs64.exp (additional_flags): ++ Add -fno-pie -no-pie. ++ ++2023-06-10 Georg-Johann Lay ++ ++ PR target/109650 ++ Backport from 2023-05-10 master r14-1688. ++ * gcc.target/avr/torture/pr109650-1.c: New test. ++ * gcc.target/avr/torture/pr109650-2.c: New test. ++ ++2023-06-09 Iain Sandoe ++ ++ Backported from master: ++ 2023-06-02 Iain Sandoe ++ ++ PR target/110044 ++ * gcc.target/powerpc/darwin-abi-13-0.c: New test. ++ * gcc.target/powerpc/darwin-abi-13-1.c: New test. ++ * gcc.target/powerpc/darwin-abi-13-2.c: New test. ++ * gcc.target/powerpc/darwin-structs-0.h: New test. ++ ++2023-06-09 liuhongt ++ ++ * gcc.target/i386/pr110108-2.c: New test. ++ ++2023-06-08 Alex Coplan ++ ++ Backported from master: ++ 2023-05-25 Alex Coplan ++ ++ PR target/109800 ++ * gcc.target/arm/pure-code/pr109800.c: New test. ++ ++2023-06-08 Kyrylo Tkachov ++ ++ Backported from master: ++ 2023-05-24 Kyrylo Tkachov ++ ++ PR target/109939 ++ * gcc.target/arm/pr109939.c: New test. ++ ++2023-06-04 Steve Kargl ++ ++ Backported from master: ++ 2023-06-02 Steve Kargl ++ ++ PR fortran/100607 ++ * gfortran.dg/select_rank_6.f90: New test. ++ ++2023-05-30 Christophe Lyon ++ ++ Backported from master: ++ 2023-05-30 Christophe Lyon ++ ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: ++ Support both definitions of int32_t. ++ ++2023-05-25 Georg-Johann Lay ++ ++ PR target/82931 ++ * gcc.target/avr/pr82931.c: New test. ++ ++2023-05-22 Michael Meissner ++ ++ PR target/70243 ++ * gcc.target/powerpc/pr70243.c: New test. Back port from master ++ 04/10/2023 change. ++ ++2023-05-22 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-21 Jakub Jelinek ++ ++ PR tree-optimization/109505 ++ * gcc.target/aarch64/sve/pr109505.c: New test. ++ ++2023-05-20 Harald Anlauf ++ ++ Backported from master: ++ 2023-05-15 Harald Anlauf ++ ++ PR fortran/109846 ++ * gfortran.dg/ptr-func-5.f90: New test. ++ ++2023-05-20 Triffid Hunter ++ ++ PR target/105753 ++ Backport from 2023-05-20 https://gcc.gnu.org/r14-1016 ++ * gcc.target/avr/torture/pr105753.c: New test. ++ ++2023-05-19 Patrick Palka ++ ++ Backported from master: ++ 2023-05-15 Patrick Palka ++ ++ * g++.dg/cpp23/feat-cxx2b.C: Test __cpp_auto_cast. ++ ++2023-05-18 Alexandre Oliva ++ ++ * gcc.target/arm/acle/cde-mve-full-assembly.c: Drop blank ++ after tab after vmsr, and lower the case of P0. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/intrinsics/srshr.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/urshr.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value. ++ * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx. ++ * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx. ++ * gcc.target/arm/mve/mve_const_shifts.c: New test. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ PR target/109697 ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: XFAIL check. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: XFAIL check. ++ * gcc.target/arm/mve/pr108177-1.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-10.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-11.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-12.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-13.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-13-run.c: use mve_fp ++ * gcc.target/arm/mve/pr108177-14.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-14-run.c: use mve_fp ++ * gcc.target/arm/mve/pr108177-2.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-3.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-4.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-5.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-6.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-7.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-8.c: Relax registers. ++ * gcc.target/arm/mve/pr108177-9.c: Relax registers. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c: Removed. ++ * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Removed. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Removed. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Add testcases. ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Add testcases. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2023-05-18 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: New. ++ ++2023-05-18 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/asrl.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/lsll.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/sqrshr.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/sqshl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/sqshll.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/srshr.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/srshrl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/uqrshl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/uqrshll_sat48.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/uqshl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/uqshll.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/urshr.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/urshrl.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp16q.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpnot.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vld1q_f16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2023-04-06 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Remove unused variables. ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Remove unused variables. ++ ++2023-05-18 Murray Steele ++ ++ Backported from master: ++ 2023-01-18 Murray Steele ++ ++ * gcc.target/arm/mve/general/preserve_user_namespace_1.c: New test. ++ ++2023-05-18 Andre Vieira ++ ++ Backported from master: ++ 2023-01-24 Andre Vieira ++ ++ * gcc.target/arm/mve/pr108177-1-run.c: New test. ++ * gcc.target/arm/mve/pr108177-1.c: New test. ++ * gcc.target/arm/mve/pr108177-10-run.c: New test. ++ * gcc.target/arm/mve/pr108177-10.c: New test. ++ * gcc.target/arm/mve/pr108177-11-run.c: New test. ++ * gcc.target/arm/mve/pr108177-11.c: New test. ++ * gcc.target/arm/mve/pr108177-12-run.c: New test. ++ * gcc.target/arm/mve/pr108177-12.c: New test. ++ * gcc.target/arm/mve/pr108177-13-run.c: New test. ++ * gcc.target/arm/mve/pr108177-13.c: New test. ++ * gcc.target/arm/mve/pr108177-14-run.c: New test. ++ * gcc.target/arm/mve/pr108177-14.c: New test. ++ * gcc.target/arm/mve/pr108177-2-run.c: New test. ++ * gcc.target/arm/mve/pr108177-2.c: New test. ++ * gcc.target/arm/mve/pr108177-3-run.c: New test. ++ * gcc.target/arm/mve/pr108177-3.c: New test. ++ * gcc.target/arm/mve/pr108177-4-run.c: New test. ++ * gcc.target/arm/mve/pr108177-4.c: New test. ++ * gcc.target/arm/mve/pr108177-5-run.c: New test. ++ * gcc.target/arm/mve/pr108177-5.c: New test. ++ * gcc.target/arm/mve/pr108177-6-run.c: New test. ++ * gcc.target/arm/mve/pr108177-6.c: New test. ++ * gcc.target/arm/mve/pr108177-7-run.c: New test. ++ * gcc.target/arm/mve/pr108177-7.c: New test. ++ * gcc.target/arm/mve/pr108177-8-run.c: New test. ++ * gcc.target/arm/mve/pr108177-8.c: New test. ++ * gcc.target/arm/mve/pr108177-9-run.c: New test. ++ * gcc.target/arm/mve/pr108177-9.c: New test. ++ * gcc.target/arm/mve/pr108177-main.x: New test include. ++ * gcc.target/arm/mve/pr108177.x: New test include. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2023-04-04 Stam Markianos-Wright ++ ++ * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Tighten test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Tighten test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Tighten test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Tighten test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Tighten test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Tighten test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Tighten test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Tighten test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Tighten test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Tighten test. ++ ++2023-05-18 Stam Markianos-Wright ++ ++ Backported from master: ++ 2023-01-16 Stam Markianos-Wright ++ ++ PR target/96795 ++ PR target/107515 ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: New test. ++ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: New test. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Add missing extern ++ "C". ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vld2q_f16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vld2q_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld2q_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld2q_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld2q_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld2q_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld2q_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vld2q_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vcmlaq_f16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise. ++ * gcc.target/arm/simd/mve-vneg.c: Update test. ++ * gcc.target/arm/simd/mve-vshr.c: Likewise ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vclzq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use ++ extern "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vclzq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclzq_x_u8.c: Likewise. ++ * gcc.target/arm/simd/mve-vclz.c: Update test. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2023-01-25 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vclsq_m_s16.c: Use ++ check-function-bodies instead of scan-assembler checks. Use extern ++ "C" for C++ testing. ++ * gcc.target/arm/mve/intrinsics/vclsq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclsq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclsq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclsq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vclsq_x_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-12-08 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Extern functions ++ as "C". ++ * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise. ++ ++2023-05-18 Christophe Lyon ++ ++ Backported from master: ++ 2022-09-30 Christophe Lyon ++ ++ * gcc.target/arm/mve/mve_load_memory_modes.c: Update expected ++ registers. ++ * gcc.target/arm/mve/mve_store_memory_modes.c: Likewise. ++ ++2023-05-18 Christophe Lyon ++ ++ Backported from master: ++ 2022-10-03 Christophe Lyon ++ ++ * gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c: New test. ++ ++2023-05-18 Christophe Lyon ++ ++ Backported from master: ++ 2022-12-01 Christophe Lyon ++ ++ * gcc.target/arm/simd/mve-compare-1.c: Update. ++ * gcc.target/arm/simd/mve-compare-scalar-1.c: Update. ++ * gcc.target/arm/simd/mve-vabs.c: Update. ++ * gcc.target/arm/simd/mve-vadd-1.c: Update. ++ * gcc.target/arm/simd/mve-vadd-scalar-1.c: Update. ++ * gcc.target/arm/simd/mve-vcmp.c: Update. ++ * gcc.target/arm/simd/pr101325.c: Update. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Improve tests. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: ++ * gcc.target/arm/mve/intrinsics/vqsubq_u8.c: ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: ++ * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Improve tests. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Improve tests. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Improve tests. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Improve tests. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vabsq_f16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vabdq_f16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Improve tests. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c : Improve test. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c : Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_n_u16.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c : Likewise. ++ * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c : Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: ++ Update test. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: ++ Likewise. ++ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: ++ Likewise. ++ ++2023-05-18 Andrea Corallo ++ ++ Backported from master: ++ 2022-11-28 Andrea Corallo ++ ++ * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Improve test. ++ * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise. ++ * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise. ++ ++2023-05-17 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-17 Jakub Jelinek ++ ++ PR c++/109868 ++ * g++.dg/init/pr109868.C: New test. ++ ++2023-05-15 Jason Merrill ++ ++ PR c++/109241 ++ * g++.dg/cpp1y/lambda-generic-local-class2.C: New test. ++ ++2023-05-15 Richard Biener ++ ++ PR testsuite/108776 ++ * c-c++-common/rotate-11.c: Add --param logical-op-non-short-circuit=1. ++ ++2023-05-15 Richard Biener ++ ++ Backported from master: ++ 2023-05-15 Richard Biener ++ ++ * gcc.dg/vect/pr108950.c: Re-order dg-require-effective-target ++ and dg-do. ++ ++2023-05-10 Richard Biener ++ ++ Backported from master: ++ 2023-05-10 Richard Biener ++ ++ * g++.dg/torture/pr106922.C: Force _GLIBCXX_USE_CXX11_ABI to 1. ++ ++2023-05-09 Patrick Palka ++ ++ Backported from master: ++ 2023-04-01 Patrick Palka ++ ++ PR c++/109160 ++ * g++.dg/cpp2a/concepts-placeholder12.C: New test. ++ ++2023-05-09 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-09 Jakub Jelinek ++ ++ PR tree-optimization/109778 ++ * gcc.dg/lto/pr109778_0.c: New test. ++ * gcc.dg/lto/pr109778_1.c: New file. ++ ++2023-05-09 Jakub Jelinek ++ ++ Backported from master: ++ 2023-05-09 Jakub Jelinek ++ ++ PR tree-optimization/109778 ++ * gcc.c-torture/execute/pr109778.c: New test. ++ ++2023-05-09 Martin Uecker ++ ++ Backported from master: ++ 2023-02-18 Martin Uecker ++ ++ PR c/105660 ++ PR c/105660 ++ * gcc.dg/pr105660-1.c: New test. ++ * gcc.dg/pr105660-2.c: New test. ++ ++2023-05-09 Kewen Lin ++ ++ Backported from master: ++ 2023-04-26 Kewen Lin ++ ++ PR target/109069 ++ * gcc.target/powerpc/pr109069-1.c: New test. ++ * gcc.target/powerpc/pr109069-2-run.c: New test. ++ * gcc.target/powerpc/pr109069-2.c: New test. ++ * gcc.target/powerpc/pr109069-2.h: New test. ++ ++2023-05-09 Jason Merrill ++ ++ PR c++/106740 ++ PR c++/105852 ++ * g++.dg/template/friend78.C: New test. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/gcc/testsuite/c-c++-common/rotate-11.c b/gcc/testsuite/c-c++-common/rotate-11.c +index e57db19d949..85cde2786e2 100644 +--- a/gcc/testsuite/c-c++-common/rotate-11.c ++++ b/gcc/testsuite/c-c++-common/rotate-11.c +@@ -1,6 +1,6 @@ + /* PR tree-optimization/108440 */ + /* { dg-do compile { target { { ilp32 || lp64 } || llp64 } } } */ +-/* { dg-options "-O2 -fdump-tree-optimized" } */ ++/* { dg-options "-O2 -fdump-tree-optimized --param logical-op-non-short-circuit=1" } */ + /* { dg-final { scan-tree-dump-times " r<< " 5 "optimized" } } */ + /* { dg-final { scan-tree-dump-times " \\\& 7;" 4 "optimized" } } */ + +diff --git a/gcc/testsuite/c-c++-common/ubsan/Wno-attributes-1.c b/gcc/testsuite/c-c++-common/ubsan/Wno-attributes-1.c +new file mode 100644 +index 00000000000..8e392c7fd6e +--- /dev/null ++++ b/gcc/testsuite/c-c++-common/ubsan/Wno-attributes-1.c +@@ -0,0 +1,9 @@ ++/* PR c/112339 */ ++/* { dg-do compile { target { c++11 || c } } } */ ++/* { dg-options "-Wno-attributes=foo::no_sanitize -fsanitize=undefined" } */ ++/* { dg-additional-options "-std=c2x" { target c } } */ ++ ++[[foo::no_sanitize("bounds")]] void ++foo (void) ++{ ++} +diff --git a/gcc/testsuite/c-c++-common/ubsan/pr112727.c b/gcc/testsuite/c-c++-common/ubsan/pr112727.c +new file mode 100644 +index 00000000000..cc8b3e2a565 +--- /dev/null ++++ b/gcc/testsuite/c-c++-common/ubsan/pr112727.c +@@ -0,0 +1,17 @@ ++/* PR sanitizer/112727 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fsanitize=shift-exponent,bounds-strict -Wuninitialized" } */ ++ ++#ifndef __cplusplus ++#define bool _Bool ++#endif ++ ++struct S { bool s[8]; }; ++ ++void ++foo (const struct S *x) ++{ ++ unsigned n = 0; ++ for (unsigned j = 0; j < 8; j++) ++ n |= ((!x->s[j]) ? 1 : 0) << (16 + j); ++} +diff --git a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const11a.C b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const11a.C +new file mode 100644 +index 00000000000..7fc3d48a8dd +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const11a.C +@@ -0,0 +1,21 @@ ++// PR c++/108975 ++// A version of lambda-const11.C using a generic lambda. ++// { dg-do compile { target c++14 } } ++ ++template void g(); ++template struct A { }; ++ ++template ++void f() { ++ constexpr int dim = 1; ++ auto l = [&](auto) { ++ int n[dim * 1]; ++ using ty1 = decltype(g()); ++ using ty2 = A; ++ }; ++ l(0); ++ // In f, we shouldn't actually capture dim. ++ static_assert (sizeof(l) == 1, ""); ++} ++ ++template void f(); +diff --git a/gcc/testsuite/g++.dg/cpp0x/noexcept78.C b/gcc/testsuite/g++.dg/cpp0x/noexcept78.C +new file mode 100644 +index 00000000000..e8156eb7c6f +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp0x/noexcept78.C +@@ -0,0 +1,16 @@ ++// PR c++/109761 ++// { dg-do compile { target c++11 } } ++ ++struct base { ++ virtual void foo() noexcept { } ++ virtual ~base() { } ++}; ++ ++struct outer : base { ++ struct nested { ++ void foo() noexcept(noexcept(g())); // { dg-bogus "looser" } ++ ~nested() noexcept(noexcept(g())); // { dg-bogus "looser" } ++ }; ++ static void g(); ++}; ++ +diff --git a/gcc/testsuite/g++.dg/cpp0x/noexcept79.C b/gcc/testsuite/g++.dg/cpp0x/noexcept79.C +new file mode 100644 +index 00000000000..d1f54d14431 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp0x/noexcept79.C +@@ -0,0 +1,18 @@ ++// PR c++/110468 ++// { dg-do compile { target c++11 } } ++ ++template ++struct variant { ++ variant() noexcept(T > 0); ++}; ++ ++template ++struct A { ++ variant m = {}; ++}; ++ ++struct B { ++ B(A<1>); ++}; ++ ++B b = {{}}; +diff --git a/gcc/testsuite/g++.dg/cpp0x/nsdmi-array2.C b/gcc/testsuite/g++.dg/cpp0x/nsdmi-array2.C +new file mode 100644 +index 00000000000..5ad60f56510 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp0x/nsdmi-array2.C +@@ -0,0 +1,15 @@ ++// PR c++/109666 ++// { dg-do compile { target c++11 } } ++ ++struct Point { ++ int value_; ++}; ++template struct StaticVector { ++ static StaticVector create() { ++ StaticVector output; ++ return output; ++ } ++ Point _M_elems[n]{}; ++ ++}; ++void f() { StaticVector<3>::create(); } +diff --git a/gcc/testsuite/g++.dg/cpp0x/nsdmi-template25.C b/gcc/testsuite/g++.dg/cpp0x/nsdmi-template25.C +new file mode 100644 +index 00000000000..368e745540e +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp0x/nsdmi-template25.C +@@ -0,0 +1,18 @@ ++// PR c++/106890 ++// { dg-do compile { target c++11 } } ++ ++struct A ++{ ++ int p; ++}; ++ ++template ++struct B : virtual public A ++{ ++ B() { } ++ B(int) { } ++ ++ int k = this->p; ++}; ++ ++template struct B; +diff --git a/gcc/testsuite/g++.dg/cpp1y/lambda-generic-local-class2.C b/gcc/testsuite/g++.dg/cpp1y/lambda-generic-local-class2.C +new file mode 100644 +index 00000000000..83856de1f41 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp1y/lambda-generic-local-class2.C +@@ -0,0 +1,13 @@ ++// PR c++/109241 ++// { dg-do compile { target c++14 } } ++// { dg-options "" } no pedantic ++ ++void g() { ++ [](auto) { ++ [](auto) { ++ ({ ++ struct A {}; ++ }); ++ }; ++ }(1); ++} +diff --git a/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C b/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C +index c1f91e78e66..d8a1acd17df 100644 +--- a/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C ++++ b/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C +@@ -557,3 +557,9 @@ + #elif __cpp_multidimensional_subscript != 202110 + # error "__cpp_multidimensional_subscript != 202110" + #endif ++ ++#ifndef __cpp_auto_cast ++# error "__cpp_auto_cast" ++#elif __cpp_auto_cast != 202110 ++# error "__cpp_auto_cast != 202110" ++#endif +diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-fn8.C b/gcc/testsuite/g++.dg/cpp2a/concepts-fn8.C +new file mode 100644 +index 00000000000..c63d26c931d +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp2a/concepts-fn8.C +@@ -0,0 +1,26 @@ ++// PR c++/111703 ++// { dg-do compile { target c++20 } } ++ ++template ++constexpr bool always_true() { return true; } ++ ++struct P { ++ P() = default; ++ ++ template ++ requires (always_true()) // { dg-bogus "used before its definition" } ++ constexpr P(const T&) { } ++ ++ int n, m; ++}; ++ ++void (*f)(P); ++P (*h)(P); ++ ++template ++constexpr bool g() { ++ P x; ++ f(x); // { dg-bogus "from here" } ++ f(h(x)); // { dg-bogus "from here" } ++ return true; ++} +diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-placeholder12.C b/gcc/testsuite/g++.dg/cpp2a/concepts-placeholder12.C +new file mode 100644 +index 00000000000..22f0ac5e26a +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp2a/concepts-placeholder12.C +@@ -0,0 +1,29 @@ ++// PR c++/109160 ++// { dg-do compile { target c++20 } } ++ ++template ++concept C = B; ++ ++template struct X { }; ++ ++template ++struct A { ++ template auto V> static void f(); ++ template auto V> static void g(X); ++ template auto V> static inline int value; ++ template auto V> struct D { }; ++}; ++ ++int main() { ++ A::f<0>(); ++ A::f<0>(); // { dg-error "no match|constraints" } ++ ++ A::g(X<0>{}); ++ A::g(X<0>{}); // { dg-error "no match|constraints" } ++ ++ bool v1 = A::value<0>; ++ bool v2 = A::value<0>; // { dg-error "constraints" } ++ ++ A::D<0> d1; ++ A::D<0> d2; // { dg-error "constraints" } ++} +diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-ttp5.C b/gcc/testsuite/g++.dg/cpp2a/concepts-ttp5.C +new file mode 100644 +index 00000000000..abc22ce59d8 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp2a/concepts-ttp5.C +@@ -0,0 +1,24 @@ ++// PR c++/111485 ++// { dg-do compile { target c++20 } } ++ ++template constexpr bool always_true = true; ++ ++template concept C = always_true; ++template concept D = C || true; ++ ++template class TT> struct example; ++template class UU> using example_t = example; ++ ++template ++struct A { ++ template class TT> struct example; ++ ++ template class UU> using example_t = example; ++ ++ template ++ struct B { ++ template class UU> using example_t = example; ++ }; ++}; ++ ++template struct A::B; +diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-ttp6.C b/gcc/testsuite/g++.dg/cpp2a/concepts-ttp6.C +new file mode 100644 +index 00000000000..6396e99cc05 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp2a/concepts-ttp6.C +@@ -0,0 +1,17 @@ ++// PR c++/111485 ++// { dg-do compile { target c++20 } } ++ ++template constexpr bool always_true = true; ++ ++template concept C = always_true; ++ ++template requires C class TT> ++void f(); ++ ++template requires C ++struct A; ++ ++int main() { ++ f(); ++ f(); // { dg-error "no match|constraint mismatch" } ++} +diff --git a/gcc/testsuite/g++.dg/debug/pr110295.C b/gcc/testsuite/g++.dg/debug/pr110295.C +new file mode 100644 +index 00000000000..10cad557095 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/debug/pr110295.C +@@ -0,0 +1,19 @@ ++// { dg-do compile } ++// { dg-options "-g" } ++ ++template ++struct QCachedT ++{ ++ void operator delete(void *, T *) {} ++}; ++template ++void exercise() ++{ ++ struct thing_t ++ : QCachedT ++ { ++ }; ++ thing_t *list[1]; ++ new thing_t; // { dg-warning "" } ++} ++int main() { exercise<1>(); } +diff --git a/gcc/testsuite/g++.dg/diagnostic/constexpr4.C b/gcc/testsuite/g++.dg/diagnostic/constexpr4.C +new file mode 100644 +index 00000000000..f37c01cac55 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/diagnostic/constexpr4.C +@@ -0,0 +1,9 @@ ++// Verify we diagnose a call to a non-constant function pointer ahead of time. ++// { dg-do compile { target c++11 } } ++ ++bool (*f)(int); ++ ++template ++void g() { ++ static_assert(f(N), ""); // { dg-error "non-constant|'f' is not usable" } ++} +diff --git a/gcc/testsuite/g++.dg/eh/return1.C b/gcc/testsuite/g++.dg/eh/return1.C +index ac2225405da..5148ead016e 100644 +--- a/gcc/testsuite/g++.dg/eh/return1.C ++++ b/gcc/testsuite/g++.dg/eh/return1.C +@@ -16,13 +16,14 @@ extern "C" int printf (const char *, ...); + + struct X + { +- X(bool throws) : throws_(throws) { ++c; DEBUG; } +- X(const X& x); // not defined ++ X(bool throws) : i(-42), throws_(throws) { ++c; DEBUG; } ++ X(const X& x): i(x.i), throws_(x.throws_) { ++c; DEBUG; } + ~X() THROWS + { +- ++d; DEBUG; ++ i = ++d; DEBUG; + if (throws_) { throw 1; } + } ++ int i; + private: + bool throws_; + }; +@@ -33,6 +34,13 @@ X f() + return X(false); + } + ++X f2() ++{ ++ foo: ++ X x(true); ++ return X(false); ++} ++ + X g() + { + return X(true),X(false); +@@ -54,6 +62,85 @@ X i() + return X(false); + } + ++X i2() ++{ ++ try { ++ foo: ++ X x(true); ++ return X(false); ++ } catch(...) {} ++ return X(false); ++} ++ ++// c++/112301 ++X i3() ++{ ++ try { ++ X x(true); ++ return X(false); ++ } catch(...) { throw; } ++} ++ ++X i4() ++{ ++ try { ++ X x(true); ++ X x2(false); ++ return x2; ++ } catch(...) { throw; } ++} ++ ++X i4a() ++{ ++ try { ++ X x2(false); ++ X x(true); ++ return x2; ++ } catch(...) { throw; } ++} ++ ++X i4b() ++{ ++ X x(true); ++ X x2(false); ++ return x2; ++} ++ ++X i4c() ++{ ++ X x2(false); ++ X x(true); ++ return x2; ++} ++ ++X i5() ++{ ++ X x2(false); ++ ++ try { ++ X x(true); ++ return x2; ++ } catch(...) { ++ if (x2.i != -42) ++ d += 42; ++ throw; ++ } ++} ++ ++X i6() ++{ ++ X x2(false); ++ ++ try { ++ X x(true); ++ return x2; ++ } catch(...) { ++ if (x2.i != -42) ++ d += 42; ++ } ++ return x2; ++} ++ + X j() + { + try { +@@ -84,6 +171,8 @@ int main() + try { f(); } + catch (...) {} + ++ try { f2(); } catch (...) {} ++ + try { g(); } + catch (...) {} + +@@ -93,6 +182,15 @@ int main() + try { i(); } + catch (...) {} + ++ try { i2(); } catch (...) {} ++ try { i3(); } catch (...) {} ++ try { i4(); } catch (...) {} ++ try { i4a(); } catch (...) {} ++ try { i4b(); } catch (...) {} ++ try { i4c(); } catch (...) {} ++ try { i5(); } catch (...) {} ++ try { i6(); } catch (...) {} ++ + try { j(); } catch (...) {} + + try { k(); } catch (...) {} +diff --git a/gcc/testsuite/g++.dg/ext/int128-7.C b/gcc/testsuite/g++.dg/ext/int128-7.C +new file mode 100644 +index 00000000000..bf5e8c40a4b +--- /dev/null ++++ b/gcc/testsuite/g++.dg/ext/int128-7.C +@@ -0,0 +1,4 @@ ++// PR c++/108099 ++// { dg-do compile { target { c++11 && int128 } } } ++ ++using i128 = signed __int128_t; // { dg-error "specified with" } +diff --git a/gcc/testsuite/g++.dg/ext/int128-8.C b/gcc/testsuite/g++.dg/ext/int128-8.C +new file mode 100644 +index 00000000000..07535a9820e +--- /dev/null ++++ b/gcc/testsuite/g++.dg/ext/int128-8.C +@@ -0,0 +1,24 @@ ++// PR c++/108099 ++// { dg-do compile { target { c++11 && int128 } } } ++// { dg-options "" } ++ ++using u128 = unsigned __int128_t; ++using s128 = signed __int128_t; ++template struct integral_constant { ++ static constexpr T value = v; ++}; ++typedef integral_constant false_type; ++typedef integral_constant true_type; ++template ++struct is_same : false_type {}; ++template ++struct is_same : true_type {}; ++static_assert (is_same <__int128, s128>::value, ""); ++static_assert (is_same ::value, ""); ++static_assert (is_same <__int128_t, s128>::value, ""); ++static_assert (is_same ::value, ""); ++static_assert (is_same <__uint128_t, u128>::value, ""); ++static_assert (sizeof (s128) == sizeof (__int128), ""); ++static_assert (sizeof (u128) == sizeof (unsigned __int128), ""); ++static_assert (s128(-1) < 0, ""); ++static_assert (u128(-1) > 0, ""); +diff --git a/gcc/testsuite/g++.dg/ext/unroll-5.C b/gcc/testsuite/g++.dg/ext/unroll-5.C +new file mode 100644 +index 00000000000..f0bc51b2239 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/ext/unroll-5.C +@@ -0,0 +1,23 @@ ++// PR c++/112795 ++// { dg-do compile { target c++11 } } ++// { dg-options "-O2 -fdump-tree-cunrolli-details" } ++ ++void baz (int); ++constexpr int n = 3; ++ ++template ++void ++foo () ++{ ++#pragma GCC unroll(n) ++ for (int i = 0; i != n; ++i) ++ baz (i); ++} ++ ++void ++qux () ++{ ++ foo <2> (); ++} ++ ++// { dg-final { scan-tree-dump "loop with 3 iterations completely unrolled" "cunrolli" } } +diff --git a/gcc/testsuite/g++.dg/ext/unsigned-typedef2.C b/gcc/testsuite/g++.dg/ext/unsigned-typedef2.C +new file mode 100644 +index 00000000000..936c0ccb748 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/ext/unsigned-typedef2.C +@@ -0,0 +1,25 @@ ++// PR c++/108099 ++// { dg-do compile { target c++11 } } ++// { dg-options "" } ++ ++typedef long long t64; ++template struct integral_constant { ++ static constexpr T value = v; ++}; ++typedef integral_constant false_type; ++typedef integral_constant true_type; ++template ++struct is_same : false_type {}; ++template ++struct is_same : true_type {}; ++ ++using s64 = signed t64; ++static_assert (is_same ::value, ""); ++static_assert (is_same ::value, ""); ++static_assert (sizeof (s64) == sizeof (long long), ""); ++static_assert (s64(-1) < 0, ""); ++ ++using u64 = unsigned t64; ++static_assert (is_same ::value, ""); ++static_assert (sizeof (u64) == sizeof (unsigned long long), ""); ++static_assert (u64(-1) > 0, ""); +diff --git a/gcc/testsuite/g++.dg/ext/unsigned-typedef3.C b/gcc/testsuite/g++.dg/ext/unsigned-typedef3.C +new file mode 100644 +index 00000000000..bb99ca0ccc9 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/ext/unsigned-typedef3.C +@@ -0,0 +1,25 @@ ++// PR c++/108099 ++// { dg-do compile { target c++11 } } ++// { dg-options "" } ++ ++typedef unsigned long long t64; ++template struct integral_constant { ++ static constexpr T value = v; ++}; ++typedef integral_constant false_type; ++typedef integral_constant true_type; ++template ++struct is_same : false_type {}; ++template ++struct is_same : true_type {}; ++ ++using s64 = signed t64; ++static_assert (is_same ::value, ""); ++static_assert (is_same ::value, ""); ++static_assert (sizeof (s64) == sizeof (long long), ""); ++static_assert (s64(-1) < 0, ""); ++ ++using u64 = unsigned t64; ++static_assert (is_same ::value, ""); ++static_assert (sizeof (u64) == sizeof (unsigned long long), ""); ++static_assert (u64(-1) > 0, ""); +diff --git a/gcc/testsuite/g++.dg/init/pr109868.C b/gcc/testsuite/g++.dg/init/pr109868.C +new file mode 100644 +index 00000000000..0926f406e4f +--- /dev/null ++++ b/gcc/testsuite/g++.dg/init/pr109868.C +@@ -0,0 +1,13 @@ ++// PR c++/109868 ++// { dg-do compile } ++// { dg-options "-O2" } ++ ++struct A { virtual void foo (); }; ++struct B { long b; int : 0; }; ++struct C : A { B c; }; ++ ++void ++bar (C *p) ++{ ++ *p = C (); ++} +diff --git a/gcc/testsuite/g++.dg/opt/pr110515.C b/gcc/testsuite/g++.dg/opt/pr110515.C +new file mode 100644 +index 00000000000..7a75cea3b4b +--- /dev/null ++++ b/gcc/testsuite/g++.dg/opt/pr110515.C +@@ -0,0 +1,223 @@ ++// { dg-do run } ++// { dg-require-effective-target c++11 } ++// { dg-options "-O2" } ++ ++typedef __UINT64_TYPE__ u64; ++ ++struct SmallDenseMap { ++ static constexpr u64 EmptyKey = 0xC0FFEUL; ++ struct V { u64 v; }; ++ ++ bool contains(u64 Val) { ++ V *TheSlot = nullptr; ++ return (LookupSlotFor(Val, TheSlot) ? 1 : 0); ++ } ++ ++ void try_emplace(u64 Key) { ++ V *TheSlot = nullptr; ++ if (LookupSlotFor(Key, TheSlot)) ++ return; ++ ++ // Otherwise, insert the new element. ++ InsertIntoSlot(TheSlot, Key); ++ } ++ ++ void moveFromOldSlots(V *OldSlotsBegin, V *OldSlotsEnd) { ++ Size = 0; ++ ++ V *B_ = u.o.Slots; ++ V *E_ = B_ + u.o.Capacity; ++ for (; B_ != E_; ++B_) ++ B_->v = EmptyKey; ++ ++ // Insert all the old elements. ++ V *O = OldSlotsBegin; ++ V *E = OldSlotsEnd; ++ for (; O != E; ++O) { ++ if (O->v != EmptyKey) { ++ // Insert the key/value into the new table. ++ V * N = nullptr; ++ LookupSlotFor(O->v, N); ++ N->v = O->v; ++ Size++; ++ } ++ } ++ } ++ ++ void InsertIntoSlot(V *TheSlot, u64 Key) { ++ unsigned NewSize = Size + 1; ++ unsigned Capacity = getCapacity(); ++ // Make sure we always keep at least one Empty value ++ if (NewSize >= Capacity) { ++ //fprintf(stderr, "GROW: size=%u capacity=%u -> ...\n", Size, Capacity); ++ grow(); ++ LookupSlotFor(Key, TheSlot); ++ Capacity = getCapacity(); ++ //fprintf(stderr, "GROW: ... -> size=%u capacity=%u\n", NewSize, Capacity); ++ } ++ ++ Size++; ++ ++ TheSlot->v = Key; ++ } ++ ++ bool LookupSlotFor(u64 Val, ++ V *&FoundSlot) { ++ V *SlotsPtr = getSlots(); ++ const unsigned Capacity = getCapacity(); ++ ++ for (unsigned i = 0; i < Capacity; ++i) { ++ V *ThisSlot = SlotsPtr + i; ++ if (Val == ThisSlot->v) { ++ FoundSlot = ThisSlot; ++ return true; ++ } ++ ++ if (ThisSlot->v == EmptyKey) { ++ FoundSlot = ThisSlot; ++ return false; ++ } ++ } ++ // Guarantee that within an array there is a match ++ // or Empty value where to insert a new vaue. ++ __builtin_trap(); ++ } ++ ++ // Needs to bea at least 1 to hld one empty value ++ static constexpr unsigned InlineSlots = 2; ++ ++ bool Small; ++ unsigned Size; ++ ++ struct LargeRep { ++ V *Slots; ++ unsigned Capacity; ++ }; ++ ++ union { ++ V i[InlineSlots]; // Small = true ++ LargeRep o; // Small = false ++ } u; ++ ++ explicit SmallDenseMap() : Small(true), Size(0) { ++ Size = 0; ++ ++ V *B = u.i; ++ V *E = B + InlineSlots; ++ for (; B != E; ++B) ++ B->v = EmptyKey; ++ } ++ ++ void grow() { ++ // assert: ++ if (!Small) __builtin_trap(); ++ ++ // First move the inline Slots into a temporary storage. ++ V TmpStorage[InlineSlots]; ++ V *TmpBegin = TmpStorage; ++ V *TmpEnd = TmpBegin; ++ ++ // Loop over the Slots, moving non-empty, non-tombstones into the ++ // temporary storage. Have the loop move the TmpEnd forward as it goes. ++ V *P = u.i; ++ V *E = P + InlineSlots; ++ for (; P != E; ++P) { ++ if (P->v != EmptyKey) { ++ TmpEnd->v = P->v; ++ ++TmpEnd; ++ } ++ } ++ ++ Small = false; ++ u.o = LargeRep{new V[128], 128}; ++ moveFromOldSlots(TmpBegin, TmpEnd); ++ } ++ ++ V *getSlots() { ++ if (Small) { ++ V * inl = u.i; ++ return inl; ++ } ++ else { ++ LargeRep * rep = &u.o; ++ return rep->Slots; ++ } ++ } ++ ++ unsigned getCapacity() { ++ if (Small) { ++ return InlineSlots; ++ } ++ else { ++ LargeRep * rep = &u.o; ++ return rep->Capacity; ++ } ++ } ++}; ++ ++#pragma GCC optimize(0) ++ ++struct P { ++ u64 f; ++ bool s; ++}; ++ ++static u64 ws = 0; ++static P WorkList[128]; ++ ++__attribute__((noipa)) ++static void popupateIni() { ++ for (u64 Var : (u64[]){8,7,6,5,4,3,0}) { ++ WorkList[ws++] = P{Var, false}; ++ } ++} ++ ++__attribute__((noipa)) ++static void checkCycle(u64 Var) { ++ // Detect cycles. ++ static bool seen[256]; ++ if (Var >= 256 || seen[Var]) __builtin_trap(); ++ seen[Var] = true; ++} ++ ++ ++__attribute__((noipa)) ++static void populateDeps(u64 Var) { ++ ++ WorkList[ws++] = P{Var, true}; ++ if (Var == 8) ++ WorkList[ws++] = P{0, false}; ++} ++ ++ ++__attribute__((noipa)) __attribute__((optimize(3))) ++static void bug() { ++ ++ // triggers growth on insert ++ SmallDenseMap Visited; ++ ++ popupateIni(); ++ ++ while (ws > 0) { ++ P Item = WorkList[--ws]; ++ u64 Var = Item.f; ++ bool visitedAllDependencies = Item.s; ++ ++ if (Visited.contains(Var)) { ++ continue; ++ } ++ ++ if (visitedAllDependencies) { ++ Visited.try_emplace(Var); ++ continue; ++ } ++ ++ checkCycle(Var); ++ populateDeps(Var); ++ } ++} ++ ++__attribute__((noipa)) ++int main() { ++ bug(); ++} +diff --git a/gcc/testsuite/g++.dg/template/friend78.C b/gcc/testsuite/g++.dg/template/friend78.C +new file mode 100644 +index 00000000000..6100528468e +--- /dev/null ++++ b/gcc/testsuite/g++.dg/template/friend78.C +@@ -0,0 +1,18 @@ ++// PR c++/106740 ++// { dg-additional-options -Wno-non-template-friend } ++ ++template struct EnumClass { friend int toString(EnumClass); }; ++struct AmhsConvInfoCoFw { ++ enum AftnTypeXMsgTypeEnum {}; ++ typedef EnumClass AftnTypeXMsgType; ++ const int getAftnTypeXMsgTypeAsStr() const; ++ struct MtcuAxgwInfo { ++ AftnTypeXMsgType mAftnTypeXMsgType; ++ }; ++}; ++const int AmhsConvInfoCoFw::getAftnTypeXMsgTypeAsStr() const { ++ MtcuAxgwInfo __trans_tmp_1; ++ toString(__trans_tmp_1.mAftnTypeXMsgType); ++ return 0; ++} ++int toString(AmhsConvInfoCoFw::AftnTypeXMsgType); +diff --git a/gcc/testsuite/g++.dg/template/template-keyword4.C b/gcc/testsuite/g++.dg/template/template-keyword4.C +new file mode 100644 +index 00000000000..a7ab9bb8ca6 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/template/template-keyword4.C +@@ -0,0 +1,18 @@ ++// PR c++/106310 ++ ++template ++struct set{}; ++ ++template< typename T > ++struct Base ++{ ++ template< int > int set(T const &); ++}; ++ ++template< typename T > ++struct Derived : Base< T > ++{ ++ void f(T const &arg) { ++ this->template set< 0 >(arg); ++ } ++}; +diff --git a/gcc/testsuite/g++.dg/torture/pr106922.C b/gcc/testsuite/g++.dg/torture/pr106922.C +index 046fc6cce76..b0c1489fbdc 100644 +--- a/gcc/testsuite/g++.dg/torture/pr106922.C ++++ b/gcc/testsuite/g++.dg/torture/pr106922.C +@@ -4,8 +4,16 @@ + // -O1 doesn't iterate VN and thus has bogus uninit diagnostics + // { dg-skip-if "" { *-*-* } { "-O1" } { "" } } + ++// The testcase still emits bogus diagnostics with the pre-C++11 ABI ++#undef _GLIBCXX_USE_CXX11_ABI ++#define _GLIBCXX_USE_CXX11_ABI 1 ++ + #include + ++// When the library is not dual-ABI and defaults to old just compile ++// an empty TU ++#if _GLIBCXX_USE_CXX11_ABI ++ + #include + template + using Optional = std::optional; +@@ -46,3 +54,4 @@ void test() + externals.external2 = internal2; + } + } ++#endif +diff --git a/gcc/testsuite/g++.dg/torture/pr111019.C b/gcc/testsuite/g++.dg/torture/pr111019.C +new file mode 100644 +index 00000000000..ce21a311c96 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/torture/pr111019.C +@@ -0,0 +1,65 @@ ++// { dg-do run } ++// { dg-additional-options "-fstrict-aliasing" } ++ ++#include ++#include ++#include ++ ++class Base ++{ ++public: ++ Base* previous = nullptr; ++ Base* next = nullptr; ++ Base* target = nullptr; ++}; ++ ++class Target : public Base ++{ ++public: ++ __attribute__((always_inline)) ~Target() ++ { ++ while (this->next) ++ { ++ Base* n = this->next; ++ ++ if (n->previous) ++ n->previous->next = n->next; ++ if (n->next) ++ n->next->previous = n->previous; ++ n->previous = nullptr; ++ n->next = nullptr; ++ n->target = nullptr; ++ } ++ } ++}; ++ ++template ++class TargetWithData final : public Target ++{ ++public: ++ TargetWithData(T data) ++ : data(data) ++ {} ++ T data; ++}; ++ ++void test() ++{ ++ printf("test\n"); ++ Base ptr; ++ { ++ auto data = std::make_unique>(std::string("asdf")); ++ ptr.target = &*data; ++ ptr.previous = &*data; ++ data->next = &ptr; ++ ++ assert(ptr.target != nullptr); ++ } ++ assert(ptr.target == nullptr); ++} ++ ++int main(int, char**) ++{ ++ test(); ++ return 0; ++} +diff --git a/gcc/testsuite/g++.target/aarch64/acle/acle.exp b/gcc/testsuite/g++.target/aarch64/acle/acle.exp +new file mode 100644 +index 00000000000..9e1cbf4a0c6 +--- /dev/null ++++ b/gcc/testsuite/g++.target/aarch64/acle/acle.exp +@@ -0,0 +1,35 @@ ++# Copyright (C) 2014-2023 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with GCC; see the file COPYING3. If not see ++# . ++ ++# GCC testsuite that uses the `dg.exp' driver. ++ ++# Exit immediately if this isn't an AArch64 target. ++if ![istarget aarch64*-*-*] then { ++ return ++} ++ ++# Load support procs. ++load_lib g++-dg.exp ++ ++# Initialize `dg'. ++dg-init ++ ++# Main loop. ++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ ++ "" "" ++ ++# All done. ++dg-finish +diff --git a/gcc/testsuite/g++.target/aarch64/acle/ls64.C b/gcc/testsuite/g++.target/aarch64/acle/ls64.C +new file mode 100644 +index 00000000000..d9002785b57 +--- /dev/null ++++ b/gcc/testsuite/g++.target/aarch64/acle/ls64.C +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-additional-options "-march=armv8.7-a" } */ ++#include ++int main() ++{ ++ data512_t d = __arm_ld64b ((const void *)0x1000); ++ __arm_st64b ((void *)0x2000, d); ++ uint64_t x = __arm_st64bv ((void *)0x3000, d); ++ x += __arm_st64bv0 ((void *)0x4000, d); ++} +diff --git a/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C b/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C +new file mode 100644 +index 00000000000..274a4771e1c +--- /dev/null ++++ b/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C +@@ -0,0 +1,10 @@ ++/* { dg-do link { target aarch64_asm_ls64_ok } } */ ++/* { dg-additional-options "-march=armv8.7-a -flto" } */ ++#include ++int main() ++{ ++ data512_t d = __arm_ld64b ((const void *)0x1000); ++ __arm_st64b ((void *)0x2000, d); ++ uint64_t x = __arm_st64bv ((void *)0x3000, d); ++ x += __arm_st64bv0 ((void *)0x4000, d); ++} +diff --git a/gcc/testsuite/g++.target/aarch64/pr103147-10.C b/gcc/testsuite/g++.target/aarch64/pr103147-10.C +index 914fdf9c692..e12771533f7 100644 +--- a/gcc/testsuite/g++.target/aarch64/pr103147-10.C ++++ b/gcc/testsuite/g++.target/aarch64/pr103147-10.C +@@ -1,4 +1,4 @@ +-/* { dg-options "-O2 -fpack-struct -mstrict-align" } */ ++/* { dg-options "-O2 -fpack-struct -mstrict-align -fno-stack-protector" } */ + /* { dg-final { check-function-bodies "**" "" "" } } */ + + #include +diff --git a/gcc/testsuite/g++.target/i386/pr112443.C b/gcc/testsuite/g++.target/i386/pr112443.C +new file mode 100644 +index 00000000000..ebfa9b4a753 +--- /dev/null ++++ b/gcc/testsuite/g++.target/i386/pr112443.C +@@ -0,0 +1,108 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target avx512bw } */ ++/* { dg-require-effective-target avx512vl } */ ++/* { dg-options "-O2 -std=c++17 -mavx512bw -mavx512vl" } */ ++ ++#include ++#include ++#include ++#include ++ ++#define AVX512BW ++#define AVX512VL ++ ++#include "avx512f-helper.h" ++ ++struct TensorIteratorBase{ ++ char* in; ++ char* out; ++ ++ void for_each(std::function loop){ ++ loop(out, in, 32); ++ } ++}; ++ ++class Vectorized { ++protected: ++ __m256i values; ++ ++ static inline __m256i invert(const __m256i& v) { ++ const auto ones = _mm256_set1_epi64x(-1); ++ return _mm256_xor_si256(ones, v); ++ } ++public: ++ operator __m256i() const { ++ return values; ++ } ++ ++ static constexpr int size() { ++ return 32; ++ } ++ ++ Vectorized() {} ++ Vectorized(__m256i v) : values(v) {} ++ Vectorized(uint8_t v) { values = _mm256_set1_epi8(v); } ++ static Vectorized blendv(const Vectorized& a, const Vectorized& b, ++ const Vectorized& mask) { ++ return _mm256_blendv_epi8(a, b, mask); ++ } ++ static Vectorized loadu(const void* ptr) { ++ return _mm256_loadu_si256(reinterpret_cast(ptr)); ++ } ++ void store(void* ptr) const { ++ _mm256_storeu_si256(reinterpret_cast<__m256i*>(ptr), values); ++ } ++ ++ Vectorized operator<(const Vectorized& other) const { ++ __m256i max = _mm256_max_epu8(values, other); ++ return invert(_mm256_cmpeq_epi8(max, values)); ++ } ++ Vectorized operator-(const Vectorized& b) { ++ return _mm256_sub_epi8(values, b); ++ } ++}; ++ ++std::ostream& operator<<(std::ostream& stream, const Vectorized& vec) { ++ uint8_t buf[Vectorized::size()]; ++ vec.store(buf); ++ stream << "vec["; ++ for (int i = 0; i != Vectorized::size(); i++) { ++ if (i != 0) ++ stream << ", "; ++ stream << buf[i]*1; ++ } ++ stream << "]"; ++ return stream; ++} ++ ++void run(TensorIteratorBase iter){ ++ Vectorized zero_vec(0); ++ Vectorized one_vec(1); ++ ++ iter.for_each([=](char* out, char* in, int64_t size) { ++ for (int64_t i = 0; i <= size - Vectorized::size(); i += Vectorized::size()) { ++ auto self_vec = Vectorized::loadu(in + i); ++ auto left = Vectorized::blendv(zero_vec, one_vec, zero_vec < self_vec); ++ auto right = Vectorized::blendv(zero_vec, one_vec, self_vec < zero_vec); ++ auto outv = left - right; ++ outv.store(out + i); ++ } ++ }); ++} ++ ++void ++test_256 (){ ++ char in[32]; ++ char out[32]; ++ for(auto& x: in) x = 1; ++ run(TensorIteratorBase{in, out}); ++ Vectorized::loadu (out); ++ for (int i = 0; i != 32; i++) ++ if (out[i] != 1) ++ __builtin_abort (); ++} ++ ++void ++test_128 () ++{ ++} +diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C +new file mode 100644 +index 00000000000..18a2e520d6c +--- /dev/null ++++ b/gcc/testsuite/g++.target/powerpc/pr105325.C +@@ -0,0 +1,28 @@ ++/* { dg-do assemble } */ ++/* { dg-require-effective-target lp64 } */ ++/* { dg-require-effective-target power10_ok } */ ++/* { dg-require-effective-target powerpc_prefixed_addr } */ ++/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */ ++ ++/* PR target/105324. Test that power10 fusion does not generate an LWA/CMPDI ++ with a large offset that the assembler rejects. Instead it should a ++ PLWZ/CMPWI combination. ++ ++ Originally, the code was dying because the fusion load + compare -1/0/1 ++ patterns did not handle the possibility that the load might be prefixed. ++ The -fstack-protector option is needed to show the bug. */ ++ ++struct Ath__array1D { ++ int _current; ++ int getCnt() { return _current; } ++}; ++struct extMeasure { ++ int _mapTable[10000]; ++ Ath__array1D _metRCTable; ++}; ++void measureRC() { ++ extMeasure m; ++ for (; m._metRCTable.getCnt();) ++ for (;;) ++ ; ++} +diff --git a/gcc/testsuite/g++.target/powerpc/pr110741.C b/gcc/testsuite/g++.target/powerpc/pr110741.C +new file mode 100644 +index 00000000000..0214936b06d +--- /dev/null ++++ b/gcc/testsuite/g++.target/powerpc/pr110741.C +@@ -0,0 +1,552 @@ ++/* { dg-do run { target { power10_hw } } } */ ++/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ ++ ++#include ++ ++typedef unsigned char uint8_t; ++ ++template ++static inline vector unsigned long long ++VSXTernaryLogic (vector unsigned long long a, vector unsigned long long b, ++ vector unsigned long long c) ++{ ++ return vec_ternarylogic (a, b, c, kTernLogOp); ++} ++ ++static vector unsigned long long ++VSXTernaryLogic (vector unsigned long long a, vector unsigned long long b, ++ vector unsigned long long c, int ternary_logic_op) ++{ ++ switch (ternary_logic_op & 0xFF) ++ { ++ case 0: ++ return VSXTernaryLogic<0> (a, b, c); ++ case 1: ++ return VSXTernaryLogic<1> (a, b, c); ++ case 2: ++ return VSXTernaryLogic<2> (a, b, c); ++ case 3: ++ return VSXTernaryLogic<3> (a, b, c); ++ case 4: ++ return VSXTernaryLogic<4> (a, b, c); ++ case 5: ++ return VSXTernaryLogic<5> (a, b, c); ++ case 6: ++ return VSXTernaryLogic<6> (a, b, c); ++ case 7: ++ return VSXTernaryLogic<7> (a, b, c); ++ case 8: ++ return VSXTernaryLogic<8> (a, b, c); ++ case 9: ++ return VSXTernaryLogic<9> (a, b, c); ++ case 10: ++ return VSXTernaryLogic<10> (a, b, c); ++ case 11: ++ return VSXTernaryLogic<11> (a, b, c); ++ case 12: ++ return VSXTernaryLogic<12> (a, b, c); ++ case 13: ++ return VSXTernaryLogic<13> (a, b, c); ++ case 14: ++ return VSXTernaryLogic<14> (a, b, c); ++ case 15: ++ return VSXTernaryLogic<15> (a, b, c); ++ case 16: ++ return VSXTernaryLogic<16> (a, b, c); ++ case 17: ++ return VSXTernaryLogic<17> (a, b, c); ++ case 18: ++ return VSXTernaryLogic<18> (a, b, c); ++ case 19: ++ return VSXTernaryLogic<19> (a, b, c); ++ case 20: ++ return VSXTernaryLogic<20> (a, b, c); ++ case 21: ++ return VSXTernaryLogic<21> (a, b, c); ++ case 22: ++ return VSXTernaryLogic<22> (a, b, c); ++ case 23: ++ return VSXTernaryLogic<23> (a, b, c); ++ case 24: ++ return VSXTernaryLogic<24> (a, b, c); ++ case 25: ++ return VSXTernaryLogic<25> (a, b, c); ++ case 26: ++ return VSXTernaryLogic<26> (a, b, c); ++ case 27: ++ return VSXTernaryLogic<27> (a, b, c); ++ case 28: ++ return VSXTernaryLogic<28> (a, b, c); ++ case 29: ++ return VSXTernaryLogic<29> (a, b, c); ++ case 30: ++ return VSXTernaryLogic<30> (a, b, c); ++ case 31: ++ return VSXTernaryLogic<31> (a, b, c); ++ case 32: ++ return VSXTernaryLogic<32> (a, b, c); ++ case 33: ++ return VSXTernaryLogic<33> (a, b, c); ++ case 34: ++ return VSXTernaryLogic<34> (a, b, c); ++ case 35: ++ return VSXTernaryLogic<35> (a, b, c); ++ case 36: ++ return VSXTernaryLogic<36> (a, b, c); ++ case 37: ++ return VSXTernaryLogic<37> (a, b, c); ++ case 38: ++ return VSXTernaryLogic<38> (a, b, c); ++ case 39: ++ return VSXTernaryLogic<39> (a, b, c); ++ case 40: ++ return VSXTernaryLogic<40> (a, b, c); ++ case 41: ++ return VSXTernaryLogic<41> (a, b, c); ++ case 42: ++ return VSXTernaryLogic<42> (a, b, c); ++ case 43: ++ return VSXTernaryLogic<43> (a, b, c); ++ case 44: ++ return VSXTernaryLogic<44> (a, b, c); ++ case 45: ++ return VSXTernaryLogic<45> (a, b, c); ++ case 46: ++ return VSXTernaryLogic<46> (a, b, c); ++ case 47: ++ return VSXTernaryLogic<47> (a, b, c); ++ case 48: ++ return VSXTernaryLogic<48> (a, b, c); ++ case 49: ++ return VSXTernaryLogic<49> (a, b, c); ++ case 50: ++ return VSXTernaryLogic<50> (a, b, c); ++ case 51: ++ return VSXTernaryLogic<51> (a, b, c); ++ case 52: ++ return VSXTernaryLogic<52> (a, b, c); ++ case 53: ++ return VSXTernaryLogic<53> (a, b, c); ++ case 54: ++ return VSXTernaryLogic<54> (a, b, c); ++ case 55: ++ return VSXTernaryLogic<55> (a, b, c); ++ case 56: ++ return VSXTernaryLogic<56> (a, b, c); ++ case 57: ++ return VSXTernaryLogic<57> (a, b, c); ++ case 58: ++ return VSXTernaryLogic<58> (a, b, c); ++ case 59: ++ return VSXTernaryLogic<59> (a, b, c); ++ case 60: ++ return VSXTernaryLogic<60> (a, b, c); ++ case 61: ++ return VSXTernaryLogic<61> (a, b, c); ++ case 62: ++ return VSXTernaryLogic<62> (a, b, c); ++ case 63: ++ return VSXTernaryLogic<63> (a, b, c); ++ case 64: ++ return VSXTernaryLogic<64> (a, b, c); ++ case 65: ++ return VSXTernaryLogic<65> (a, b, c); ++ case 66: ++ return VSXTernaryLogic<66> (a, b, c); ++ case 67: ++ return VSXTernaryLogic<67> (a, b, c); ++ case 68: ++ return VSXTernaryLogic<68> (a, b, c); ++ case 69: ++ return VSXTernaryLogic<69> (a, b, c); ++ case 70: ++ return VSXTernaryLogic<70> (a, b, c); ++ case 71: ++ return VSXTernaryLogic<71> (a, b, c); ++ case 72: ++ return VSXTernaryLogic<72> (a, b, c); ++ case 73: ++ return VSXTernaryLogic<73> (a, b, c); ++ case 74: ++ return VSXTernaryLogic<74> (a, b, c); ++ case 75: ++ return VSXTernaryLogic<75> (a, b, c); ++ case 76: ++ return VSXTernaryLogic<76> (a, b, c); ++ case 77: ++ return VSXTernaryLogic<77> (a, b, c); ++ case 78: ++ return VSXTernaryLogic<78> (a, b, c); ++ case 79: ++ return VSXTernaryLogic<79> (a, b, c); ++ case 80: ++ return VSXTernaryLogic<80> (a, b, c); ++ case 81: ++ return VSXTernaryLogic<81> (a, b, c); ++ case 82: ++ return VSXTernaryLogic<82> (a, b, c); ++ case 83: ++ return VSXTernaryLogic<83> (a, b, c); ++ case 84: ++ return VSXTernaryLogic<84> (a, b, c); ++ case 85: ++ return VSXTernaryLogic<85> (a, b, c); ++ case 86: ++ return VSXTernaryLogic<86> (a, b, c); ++ case 87: ++ return VSXTernaryLogic<87> (a, b, c); ++ case 88: ++ return VSXTernaryLogic<88> (a, b, c); ++ case 89: ++ return VSXTernaryLogic<89> (a, b, c); ++ case 90: ++ return VSXTernaryLogic<90> (a, b, c); ++ case 91: ++ return VSXTernaryLogic<91> (a, b, c); ++ case 92: ++ return VSXTernaryLogic<92> (a, b, c); ++ case 93: ++ return VSXTernaryLogic<93> (a, b, c); ++ case 94: ++ return VSXTernaryLogic<94> (a, b, c); ++ case 95: ++ return VSXTernaryLogic<95> (a, b, c); ++ case 96: ++ return VSXTernaryLogic<96> (a, b, c); ++ case 97: ++ return VSXTernaryLogic<97> (a, b, c); ++ case 98: ++ return VSXTernaryLogic<98> (a, b, c); ++ case 99: ++ return VSXTernaryLogic<99> (a, b, c); ++ case 100: ++ return VSXTernaryLogic<100> (a, b, c); ++ case 101: ++ return VSXTernaryLogic<101> (a, b, c); ++ case 102: ++ return VSXTernaryLogic<102> (a, b, c); ++ case 103: ++ return VSXTernaryLogic<103> (a, b, c); ++ case 104: ++ return VSXTernaryLogic<104> (a, b, c); ++ case 105: ++ return VSXTernaryLogic<105> (a, b, c); ++ case 106: ++ return VSXTernaryLogic<106> (a, b, c); ++ case 107: ++ return VSXTernaryLogic<107> (a, b, c); ++ case 108: ++ return VSXTernaryLogic<108> (a, b, c); ++ case 109: ++ return VSXTernaryLogic<109> (a, b, c); ++ case 110: ++ return VSXTernaryLogic<110> (a, b, c); ++ case 111: ++ return VSXTernaryLogic<111> (a, b, c); ++ case 112: ++ return VSXTernaryLogic<112> (a, b, c); ++ case 113: ++ return VSXTernaryLogic<113> (a, b, c); ++ case 114: ++ return VSXTernaryLogic<114> (a, b, c); ++ case 115: ++ return VSXTernaryLogic<115> (a, b, c); ++ case 116: ++ return VSXTernaryLogic<116> (a, b, c); ++ case 117: ++ return VSXTernaryLogic<117> (a, b, c); ++ case 118: ++ return VSXTernaryLogic<118> (a, b, c); ++ case 119: ++ return VSXTernaryLogic<119> (a, b, c); ++ case 120: ++ return VSXTernaryLogic<120> (a, b, c); ++ case 121: ++ return VSXTernaryLogic<121> (a, b, c); ++ case 122: ++ return VSXTernaryLogic<122> (a, b, c); ++ case 123: ++ return VSXTernaryLogic<123> (a, b, c); ++ case 124: ++ return VSXTernaryLogic<124> (a, b, c); ++ case 125: ++ return VSXTernaryLogic<125> (a, b, c); ++ case 126: ++ return VSXTernaryLogic<126> (a, b, c); ++ case 127: ++ return VSXTernaryLogic<127> (a, b, c); ++ case 128: ++ return VSXTernaryLogic<128> (a, b, c); ++ case 129: ++ return VSXTernaryLogic<129> (a, b, c); ++ case 130: ++ return VSXTernaryLogic<130> (a, b, c); ++ case 131: ++ return VSXTernaryLogic<131> (a, b, c); ++ case 132: ++ return VSXTernaryLogic<132> (a, b, c); ++ case 133: ++ return VSXTernaryLogic<133> (a, b, c); ++ case 134: ++ return VSXTernaryLogic<134> (a, b, c); ++ case 135: ++ return VSXTernaryLogic<135> (a, b, c); ++ case 136: ++ return VSXTernaryLogic<136> (a, b, c); ++ case 137: ++ return VSXTernaryLogic<137> (a, b, c); ++ case 138: ++ return VSXTernaryLogic<138> (a, b, c); ++ case 139: ++ return VSXTernaryLogic<139> (a, b, c); ++ case 140: ++ return VSXTernaryLogic<140> (a, b, c); ++ case 141: ++ return VSXTernaryLogic<141> (a, b, c); ++ case 142: ++ return VSXTernaryLogic<142> (a, b, c); ++ case 143: ++ return VSXTernaryLogic<143> (a, b, c); ++ case 144: ++ return VSXTernaryLogic<144> (a, b, c); ++ case 145: ++ return VSXTernaryLogic<145> (a, b, c); ++ case 146: ++ return VSXTernaryLogic<146> (a, b, c); ++ case 147: ++ return VSXTernaryLogic<147> (a, b, c); ++ case 148: ++ return VSXTernaryLogic<148> (a, b, c); ++ case 149: ++ return VSXTernaryLogic<149> (a, b, c); ++ case 150: ++ return VSXTernaryLogic<150> (a, b, c); ++ case 151: ++ return VSXTernaryLogic<151> (a, b, c); ++ case 152: ++ return VSXTernaryLogic<152> (a, b, c); ++ case 153: ++ return VSXTernaryLogic<153> (a, b, c); ++ case 154: ++ return VSXTernaryLogic<154> (a, b, c); ++ case 155: ++ return VSXTernaryLogic<155> (a, b, c); ++ case 156: ++ return VSXTernaryLogic<156> (a, b, c); ++ case 157: ++ return VSXTernaryLogic<157> (a, b, c); ++ case 158: ++ return VSXTernaryLogic<158> (a, b, c); ++ case 159: ++ return VSXTernaryLogic<159> (a, b, c); ++ case 160: ++ return VSXTernaryLogic<160> (a, b, c); ++ case 161: ++ return VSXTernaryLogic<161> (a, b, c); ++ case 162: ++ return VSXTernaryLogic<162> (a, b, c); ++ case 163: ++ return VSXTernaryLogic<163> (a, b, c); ++ case 164: ++ return VSXTernaryLogic<164> (a, b, c); ++ case 165: ++ return VSXTernaryLogic<165> (a, b, c); ++ case 166: ++ return VSXTernaryLogic<166> (a, b, c); ++ case 167: ++ return VSXTernaryLogic<167> (a, b, c); ++ case 168: ++ return VSXTernaryLogic<168> (a, b, c); ++ case 169: ++ return VSXTernaryLogic<169> (a, b, c); ++ case 170: ++ return VSXTernaryLogic<170> (a, b, c); ++ case 171: ++ return VSXTernaryLogic<171> (a, b, c); ++ case 172: ++ return VSXTernaryLogic<172> (a, b, c); ++ case 173: ++ return VSXTernaryLogic<173> (a, b, c); ++ case 174: ++ return VSXTernaryLogic<174> (a, b, c); ++ case 175: ++ return VSXTernaryLogic<175> (a, b, c); ++ case 176: ++ return VSXTernaryLogic<176> (a, b, c); ++ case 177: ++ return VSXTernaryLogic<177> (a, b, c); ++ case 178: ++ return VSXTernaryLogic<178> (a, b, c); ++ case 179: ++ return VSXTernaryLogic<179> (a, b, c); ++ case 180: ++ return VSXTernaryLogic<180> (a, b, c); ++ case 181: ++ return VSXTernaryLogic<181> (a, b, c); ++ case 182: ++ return VSXTernaryLogic<182> (a, b, c); ++ case 183: ++ return VSXTernaryLogic<183> (a, b, c); ++ case 184: ++ return VSXTernaryLogic<184> (a, b, c); ++ case 185: ++ return VSXTernaryLogic<185> (a, b, c); ++ case 186: ++ return VSXTernaryLogic<186> (a, b, c); ++ case 187: ++ return VSXTernaryLogic<187> (a, b, c); ++ case 188: ++ return VSXTernaryLogic<188> (a, b, c); ++ case 189: ++ return VSXTernaryLogic<189> (a, b, c); ++ case 190: ++ return VSXTernaryLogic<190> (a, b, c); ++ case 191: ++ return VSXTernaryLogic<191> (a, b, c); ++ case 192: ++ return VSXTernaryLogic<192> (a, b, c); ++ case 193: ++ return VSXTernaryLogic<193> (a, b, c); ++ case 194: ++ return VSXTernaryLogic<194> (a, b, c); ++ case 195: ++ return VSXTernaryLogic<195> (a, b, c); ++ case 196: ++ return VSXTernaryLogic<196> (a, b, c); ++ case 197: ++ return VSXTernaryLogic<197> (a, b, c); ++ case 198: ++ return VSXTernaryLogic<198> (a, b, c); ++ case 199: ++ return VSXTernaryLogic<199> (a, b, c); ++ case 200: ++ return VSXTernaryLogic<200> (a, b, c); ++ case 201: ++ return VSXTernaryLogic<201> (a, b, c); ++ case 202: ++ return VSXTernaryLogic<202> (a, b, c); ++ case 203: ++ return VSXTernaryLogic<203> (a, b, c); ++ case 204: ++ return VSXTernaryLogic<204> (a, b, c); ++ case 205: ++ return VSXTernaryLogic<205> (a, b, c); ++ case 206: ++ return VSXTernaryLogic<206> (a, b, c); ++ case 207: ++ return VSXTernaryLogic<207> (a, b, c); ++ case 208: ++ return VSXTernaryLogic<208> (a, b, c); ++ case 209: ++ return VSXTernaryLogic<209> (a, b, c); ++ case 210: ++ return VSXTernaryLogic<210> (a, b, c); ++ case 211: ++ return VSXTernaryLogic<211> (a, b, c); ++ case 212: ++ return VSXTernaryLogic<212> (a, b, c); ++ case 213: ++ return VSXTernaryLogic<213> (a, b, c); ++ case 214: ++ return VSXTernaryLogic<214> (a, b, c); ++ case 215: ++ return VSXTernaryLogic<215> (a, b, c); ++ case 216: ++ return VSXTernaryLogic<216> (a, b, c); ++ case 217: ++ return VSXTernaryLogic<217> (a, b, c); ++ case 218: ++ return VSXTernaryLogic<218> (a, b, c); ++ case 219: ++ return VSXTernaryLogic<219> (a, b, c); ++ case 220: ++ return VSXTernaryLogic<220> (a, b, c); ++ case 221: ++ return VSXTernaryLogic<221> (a, b, c); ++ case 222: ++ return VSXTernaryLogic<222> (a, b, c); ++ case 223: ++ return VSXTernaryLogic<223> (a, b, c); ++ case 224: ++ return VSXTernaryLogic<224> (a, b, c); ++ case 225: ++ return VSXTernaryLogic<225> (a, b, c); ++ case 226: ++ return VSXTernaryLogic<226> (a, b, c); ++ case 227: ++ return VSXTernaryLogic<227> (a, b, c); ++ case 228: ++ return VSXTernaryLogic<228> (a, b, c); ++ case 229: ++ return VSXTernaryLogic<229> (a, b, c); ++ case 230: ++ return VSXTernaryLogic<230> (a, b, c); ++ case 231: ++ return VSXTernaryLogic<231> (a, b, c); ++ case 232: ++ return VSXTernaryLogic<232> (a, b, c); ++ case 233: ++ return VSXTernaryLogic<233> (a, b, c); ++ case 234: ++ return VSXTernaryLogic<234> (a, b, c); ++ case 235: ++ return VSXTernaryLogic<235> (a, b, c); ++ case 236: ++ return VSXTernaryLogic<236> (a, b, c); ++ case 237: ++ return VSXTernaryLogic<237> (a, b, c); ++ case 238: ++ return VSXTernaryLogic<238> (a, b, c); ++ case 239: ++ return VSXTernaryLogic<239> (a, b, c); ++ case 240: ++ return VSXTernaryLogic<240> (a, b, c); ++ case 241: ++ return VSXTernaryLogic<241> (a, b, c); ++ case 242: ++ return VSXTernaryLogic<242> (a, b, c); ++ case 243: ++ return VSXTernaryLogic<243> (a, b, c); ++ case 244: ++ return VSXTernaryLogic<244> (a, b, c); ++ case 245: ++ return VSXTernaryLogic<245> (a, b, c); ++ case 246: ++ return VSXTernaryLogic<246> (a, b, c); ++ case 247: ++ return VSXTernaryLogic<247> (a, b, c); ++ case 248: ++ return VSXTernaryLogic<248> (a, b, c); ++ case 249: ++ return VSXTernaryLogic<249> (a, b, c); ++ case 250: ++ return VSXTernaryLogic<250> (a, b, c); ++ case 251: ++ return VSXTernaryLogic<251> (a, b, c); ++ case 252: ++ return VSXTernaryLogic<252> (a, b, c); ++ case 253: ++ return VSXTernaryLogic<253> (a, b, c); ++ case 254: ++ return VSXTernaryLogic<254> (a, b, c); ++ case 255: ++ return VSXTernaryLogic<255> (a, b, c); ++ default: ++ return a; ++ } ++} ++ ++int ++main (int argc, char **argv) ++{ ++ vector unsigned long long a = {0xD8, 0xDB}; ++ vector unsigned long long b = {0x6C, 0x6C}; ++ vector unsigned long long c = {0x56, 0x56}; ++ vector unsigned long long ternlog_result = VSXTernaryLogic (a, b, c, 0xB6); ++ ++ if (ternlog_result[0] != 0xffffffffffffff3dull ++ || ternlog_result[1] != 0xffffffffffffff3eull) ++ __builtin_abort (); ++ ++ return 0; ++} +diff --git a/gcc/testsuite/g++.target/powerpc/pr111366.C b/gcc/testsuite/g++.target/powerpc/pr111366.C +new file mode 100644 +index 00000000000..6d3d8ebc552 +--- /dev/null ++++ b/gcc/testsuite/g++.target/powerpc/pr111366.C +@@ -0,0 +1,48 @@ ++/* { dg-do compile } */ ++/* Use -Wno-attributes to suppress the possible warning on always_inline. */ ++/* { dg-options "-O2 -mdejagnu-cpu=power9 -Wno-attributes" } */ ++ ++/* Verify it doesn't emit any error messages. */ ++ ++#include ++#define HWY_PRAGMA(tokens) _Pragma (#tokens) ++#define HWY_PUSH_ATTRIBUTES(targets_str) HWY_PRAGMA (GCC target targets_str) ++__attribute__ ((always_inline)) void ++PreventElision () ++{ ++ asm(""); ++} ++#define HWY_BEFORE_NAMESPACE() HWY_PUSH_ATTRIBUTES (",cpu=power10") ++HWY_BEFORE_NAMESPACE () namespace detail ++{ ++ template struct CappedTagChecker ++ { ++ }; ++} ++template ++using CappedTag = detail::CappedTagChecker; ++template struct ForeachCappedR ++{ ++ static void Do (size_t, size_t) ++ { ++ CappedTag d; ++ Test () (int(), d); ++ } ++}; ++template struct ForPartialVectors ++{ ++ template void operator() (T) ++ { ++ ForeachCappedR::Do (1, 1); ++ } ++}; ++struct TestFloorLog2 ++{ ++ template void operator() (T, DF) { PreventElision (); } ++}; ++void ++TestAllFloorLog2 () ++{ ++ ForPartialVectors () (float()); ++} ++ +diff --git a/gcc/testsuite/g++.target/powerpc/pr111367.C b/gcc/testsuite/g++.target/powerpc/pr111367.C +new file mode 100644 +index 00000000000..8f9d4415672 +--- /dev/null ++++ b/gcc/testsuite/g++.target/powerpc/pr111367.C +@@ -0,0 +1,22 @@ ++/* { dg-do assemble } */ ++/* { dg-require-effective-target power10_ok } */ ++/* { dg-options "-mdejagnu-cpu=power10 -fstack-protector-strong" } */ ++ ++/* Verify object file can be generated successfully. */ ++ ++struct SortAscending ++{ ++}; ++ ++typedef unsigned long long size_t; ++ ++void VQSort (long long *, size_t, SortAscending); ++ ++void ++BenchAllColdSort () ++{ ++ typedef long long T; ++ constexpr size_t kSize = 10 * 1000; ++ alignas (16) T items[kSize]; ++ VQSort (items, kSize, SortAscending ()); ++} +diff --git a/gcc/testsuite/g++.target/powerpc/pr111828-1.C b/gcc/testsuite/g++.target/powerpc/pr111828-1.C +new file mode 100644 +index 00000000000..d76a084bdcf +--- /dev/null ++++ b/gcc/testsuite/g++.target/powerpc/pr111828-1.C +@@ -0,0 +1,49 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target powerpc_as_p10_htm } */ ++/* Use -Wno-attributes to suppress the possible warning on always_inline. */ ++/* { dg-options "-O2 -mdejagnu-cpu=power9 -Wno-attributes" } */ ++ ++/* Verify it doesn't emit any error messages. */ ++ ++#include ++#define HWY_PRAGMA(tokens) _Pragma (#tokens) ++#define HWY_PUSH_ATTRIBUTES(targets_str) HWY_PRAGMA (GCC target targets_str) ++__attribute__ ((always_inline)) void ++PreventElision (int output) ++{ ++ asm("nop" : "+r"(output) : : "memory"); ++} ++#define HWY_BEFORE_NAMESPACE() HWY_PUSH_ATTRIBUTES (",cpu=power10") ++HWY_BEFORE_NAMESPACE () namespace detail ++{ ++ template struct CappedTagChecker ++ { ++ }; ++} ++template ++using CappedTag = detail::CappedTagChecker; ++template struct ForeachCappedR ++{ ++ static void Do (size_t, size_t) ++ { ++ CappedTag d; ++ Test () (int(), d); ++ } ++}; ++template struct ForPartialVectors ++{ ++ template void operator() (T) ++ { ++ ForeachCappedR::Do (1, 1); ++ } ++}; ++struct TestFloorLog2 ++{ ++ template void operator() (T, DF) { PreventElision (0x10); } ++}; ++void ++TestAllFloorLog2 () ++{ ++ ForPartialVectors () (float()); ++} ++ +diff --git a/gcc/testsuite/g++.target/powerpc/pr111828-2.C b/gcc/testsuite/g++.target/powerpc/pr111828-2.C +new file mode 100644 +index 00000000000..0b7331675f7 +--- /dev/null ++++ b/gcc/testsuite/g++.target/powerpc/pr111828-2.C +@@ -0,0 +1,52 @@ ++/* { dg-do compile } */ ++/* { dg-skip-if "HTM inline asm supported" { powerpc_as_p10_htm } } */ ++/* Use -Wno-attributes to suppress the possible warning on always_inline. */ ++/* { dg-options "-O2 -mdejagnu-cpu=power9 -Wno-attributes" } */ ++ ++/* Verify it emits error messages on non-empty inline asm. */ ++ ++#include ++#define HWY_PRAGMA(tokens) _Pragma (#tokens) ++#define HWY_PUSH_ATTRIBUTES(targets_str) HWY_PRAGMA (GCC target targets_str) ++__attribute__ ((always_inline)) void ++PreventElision (int output) /* { dg-error "inlining failed in call to .* target specific option mismatch" } */ ++{ ++ asm("nop" : "+r"(output) : : "memory"); ++} ++#define HWY_BEFORE_NAMESPACE() HWY_PUSH_ATTRIBUTES (",cpu=power10") ++HWY_BEFORE_NAMESPACE () namespace detail ++{ ++ template struct CappedTagChecker ++ { ++ }; ++} ++template ++using CappedTag = detail::CappedTagChecker; ++template struct ForeachCappedR ++{ ++ static void Do (size_t, size_t) ++ { ++ CappedTag d; ++ Test () (int(), d); ++ } ++}; ++template struct ForPartialVectors ++{ ++ template void operator() (T) ++ { ++ ForeachCappedR::Do (1, 1); ++ } ++}; ++struct TestFloorLog2 ++{ ++ template void operator() (T, DF) ++ { ++ PreventElision (0x10); /* { dg-message "called from here" } */ ++ } ++}; ++void ++TestAllFloorLog2 () ++{ ++ ForPartialVectors () (float()); ++} ++ +diff --git a/gcc/testsuite/gcc.c-torture/compile/asmgoto-6.c b/gcc/testsuite/gcc.c-torture/compile/asmgoto-6.c +new file mode 100644 +index 00000000000..0652bd4e4e1 +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/compile/asmgoto-6.c +@@ -0,0 +1,26 @@ ++ ++/* { dg-do compile } */ ++/* PR middle-end/110420 */ ++/* PR middle-end/103979 */ ++/* PR middle-end/98619 */ ++/* Test that the middle-end does not remove the asm goto ++ with an output. */ ++ ++static int t; ++void g(void); ++ ++void f(void) ++{ ++ int __gu_val; ++ asm goto("#my asm " ++ : "=&r"(__gu_val) ++ : ++ : ++ : Efault); ++ t = __gu_val; ++ g(); ++Efault: ++} ++ ++/* Make sure "my asm " is still in the assembly. */ ++/* { dg-final { scan-assembler "my asm " } } */ +diff --git a/gcc/testsuite/gcc.c-torture/compile/pr111699-1.c b/gcc/testsuite/gcc.c-torture/compile/pr111699-1.c +new file mode 100644 +index 00000000000..87b127ed199 +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/compile/pr111699-1.c +@@ -0,0 +1,7 @@ ++typedef unsigned char __attribute__((__vector_size__ (8))) V; ++ ++void ++foo (V *v) ++{ ++ *v = (V) 0x107B9A7FF >= (*v <= 0); ++} +diff --git a/gcc/testsuite/gcc.c-torture/execute/20230630-1.c b/gcc/testsuite/gcc.c-torture/execute/20230630-1.c +new file mode 100644 +index 00000000000..7c1f15c177f +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/execute/20230630-1.c +@@ -0,0 +1,23 @@ ++struct S { ++ short int i : 12; ++ char c1 : 1; ++ char c2 : 1; ++ char c3 : 1; ++ char c4 : 1; ++}; ++ ++int main (void) ++{ ++ struct S s0 = { 341, 1, 1, 1, 1 }; ++ char *p = (char *) &s0; ++ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++ if (*p != 85) ++ __builtin_abort (); ++#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ++ if (*p != 21) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.c-torture/execute/20230630-2.c b/gcc/testsuite/gcc.c-torture/execute/20230630-2.c +new file mode 100644 +index 00000000000..c05c1666516 +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/execute/20230630-2.c +@@ -0,0 +1,29 @@ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++#define REVERSE_SSO __attribute__((scalar_storage_order("big-endian"))); ++#else ++#define REVERSE_SSO __attribute__((scalar_storage_order("little-endian"))); ++#endif ++ ++struct S { ++ short int i : 12; ++ char c1 : 1; ++ char c2 : 1; ++ char c3 : 1; ++ char c4 : 1; ++} REVERSE_SSO; ++ ++int main (void) ++{ ++ struct S s0 = { 341, 1, 1, 1, 1 }; ++ char *p = (char *) &s0; ++ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++ if (*p != 21) ++ __builtin_abort (); ++#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ++ if (*p != 85) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.c-torture/execute/20230630-3.c b/gcc/testsuite/gcc.c-torture/execute/20230630-3.c +new file mode 100644 +index 00000000000..fc106c97b5b +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/execute/20230630-3.c +@@ -0,0 +1,27 @@ ++struct S { ++ int i : 24; ++ char c1 : 1; ++ char c2 : 1; ++ char c3 : 1; ++ char c4 : 1; ++ char c5 : 1; ++ char c6 : 1; ++ char c7 : 1; ++ char c8 : 1; ++}; ++ ++int main (void) ++{ ++ struct S s0 = { 1193046, 1, 1, 1, 1, 1, 1, 1, 1 }; ++ char *p = (char *) &s0; ++ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++ if (*p != 86) ++ __builtin_abort (); ++#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ++ if (*p != 18) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.c-torture/execute/20230630-4.c b/gcc/testsuite/gcc.c-torture/execute/20230630-4.c +new file mode 100644 +index 00000000000..df33c18a8cd +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/execute/20230630-4.c +@@ -0,0 +1,33 @@ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++#define REVERSE_SSO __attribute__((scalar_storage_order("big-endian"))); ++#else ++#define REVERSE_SSO __attribute__((scalar_storage_order("little-endian"))); ++#endif ++ ++struct S { ++ int i : 24; ++ char c1 : 1; ++ char c2 : 1; ++ char c3 : 1; ++ char c4 : 1; ++ char c5 : 1; ++ char c6 : 1; ++ char c7 : 1; ++ char c8 : 1; ++} REVERSE_SSO; ++ ++int main (void) ++{ ++ struct S s0 = { 1193046, 1, 1, 1, 1, 1, 1, 1, 1 }; ++ char *p = (char *) &s0; ++ ++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ++ if (*p != 18) ++ __builtin_abort (); ++#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ++ if (*p != 86) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.c-torture/execute/pr109778.c b/gcc/testsuite/gcc.c-torture/execute/pr109778.c +new file mode 100644 +index 00000000000..309fbf413e0 +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/execute/pr109778.c +@@ -0,0 +1,26 @@ ++/* PR tree-optimization/109778 */ ++ ++int a, b, c, d, *e = &c; ++ ++static inline unsigned ++foo (unsigned char x) ++{ ++ x = 1 | x << 1; ++ x = x >> 4 | x << 4; ++ return x; ++} ++ ++static inline void ++bar (unsigned x) ++{ ++ *e = 8 > foo (x + 86) - 86; ++} ++ ++int ++main () ++{ ++ d = a && b; ++ bar (d + 4); ++ if (c != 1) ++ __builtin_abort (); ++} +diff --git a/gcc/testsuite/gcc.c-torture/execute/pr110914.c b/gcc/testsuite/gcc.c-torture/execute/pr110914.c +new file mode 100644 +index 00000000000..ccc04e1bdd4 +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/execute/pr110914.c +@@ -0,0 +1,22 @@ ++/* PR tree-optimization/110914 */ ++ ++__attribute__ ((noipa)) int ++foo (const char *s, unsigned long l) ++{ ++ unsigned char r = 0; ++ __builtin_memcpy (&r, s, l != 0); ++ return r; ++} ++ ++int ++main () ++{ ++ const char *p = "123456"; ++ int a = foo (p, __builtin_strlen (p) - 5); ++ int b = foo (p, __builtin_strlen (p) - 6); ++ if (a != '1') ++ __builtin_abort (); ++ if (b != 0) ++ __builtin_abort (); ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.c-torture/execute/pr111408.c b/gcc/testsuite/gcc.c-torture/execute/pr111408.c +new file mode 100644 +index 00000000000..6dfb0a384f1 +--- /dev/null ++++ b/gcc/testsuite/gcc.c-torture/execute/pr111408.c +@@ -0,0 +1,26 @@ ++/* PR target/111408 */ ++ ++int a, b, c, d; ++short e; ++ ++int ++foo () ++{ ++ c = a % (sizeof (int) * 8); ++ if (b & 1 << c) ++ return -1; ++ return 0; ++} ++ ++int ++main () ++{ ++ for (; e != 1; e++) ++ { ++ int g = foo (); ++ if (g + d - 9 + d) ++ continue; ++ for (;;) ++ __builtin_abort (); ++ } ++} +diff --git a/gcc/testsuite/gcc.dg/Wfree-nonheap-object-7.c b/gcc/testsuite/gcc.dg/Wfree-nonheap-object-7.c +new file mode 100644 +index 00000000000..6116bfa4d8e +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/Wfree-nonheap-object-7.c +@@ -0,0 +1,26 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -Wfree-nonheap-object" } */ ++ ++struct local_caches *get_local_caches_lcs; ++void *calloc(long, long); ++void *realloc(); ++ ++struct local_caches { ++ int *t_mem_caches; ++}; ++ ++struct local_caches *get_local_caches() { ++ if (get_local_caches_lcs) ++ return get_local_caches_lcs; ++ get_local_caches_lcs = calloc(1, 0); ++ return get_local_caches_lcs; ++} ++ ++void libtrace_ocache_free() { ++ struct local_caches lcs = *get_local_caches(), __trans_tmp_1 = lcs; ++ { ++ struct local_caches *lcs = &__trans_tmp_1; ++ lcs->t_mem_caches += 10; ++ __trans_tmp_1.t_mem_caches = realloc(__trans_tmp_1.t_mem_caches, sizeof(int)); // { dg-warning "called on pointer (?:(?!PHI).)*nonzero offset" } ++ } ++} +diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/pr111080.c b/gcc/testsuite/gcc.dg/debug/dwarf2/pr111080.c +new file mode 100644 +index 00000000000..3949d7e7c64 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/debug/dwarf2/pr111080.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-save-temps -gdwarf-3 -dA" } */ ++ ++struct foo { ++ int field_number_1; ++ int field_number_2; ++ int field_number_3; ++ int field_number_4; ++ int field_number_5; ++}; ++ ++typedef int fun_t(struct foo *restrict); ++ ++int main() { ++ return 0; ++} ++ ++/* { dg-final { scan-assembler-not "DW_TAG_structure_type" } } */ +diff --git a/gcc/testsuite/gcc.dg/lto/pr109778_0.c b/gcc/testsuite/gcc.dg/lto/pr109778_0.c +new file mode 100644 +index 00000000000..3c6e1b8f7b7 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/lto/pr109778_0.c +@@ -0,0 +1,22 @@ ++/* PR tree-optimization/109778 */ ++/* { dg-lto-do run } */ ++/* { dg-lto-options { "-O2 -flto" } } */ ++/* { dg-require-effective-target int32 } */ ++ ++int bar (int); ++ ++__attribute__((noipa)) int ++foo (int x) ++{ ++ x = bar (x); ++ x = (x << 16) | (int) ((unsigned) x >> 16); ++ return x & 0x10000000; ++} ++ ++int ++main () ++{ ++ if (foo (0) || foo (-1)) ++ __builtin_abort (); ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.dg/lto/pr109778_1.c b/gcc/testsuite/gcc.dg/lto/pr109778_1.c +new file mode 100644 +index 00000000000..d18a7209983 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/lto/pr109778_1.c +@@ -0,0 +1,7 @@ ++int ++bar (int x) ++{ ++ x &= 0x22222222; ++ x |= (int) 0xf1234567U; ++ return x; ++} +diff --git a/gcc/testsuite/gcc.dg/pr105660-1.c b/gcc/testsuite/gcc.dg/pr105660-1.c +new file mode 100644 +index 00000000000..d4454f04c43 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/pr105660-1.c +@@ -0,0 +1,13 @@ ++/* PR105660 ++ * { dg-do compile } ++ * { dg-options "-std=c17" } ++ */ ++ ++void gatherConservativeVars(int, int, int, int, int, int, int Hnvar, int, ++ int Hnyt, int Hnxyt, int, int Hstep, double[Hnyt], ++ double[Hnvar][Hstep][Hnxyt]); ++void gatherConservativeVars(int, int, int, int, int, int, int Hnvar, int, int Hnyt, ++ int Hnxyt, int, int Hstep, double[Hnyt], ++ double[Hnvar][Hstep][Hnxyt]); ++ ++ +diff --git a/gcc/testsuite/gcc.dg/pr105660-2.c b/gcc/testsuite/gcc.dg/pr105660-2.c +new file mode 100644 +index 00000000000..29fd82f923b +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/pr105660-2.c +@@ -0,0 +1,12 @@ ++/* PR105660 ++ * { dg-do compile } ++ * { dg-options "-Wall -std=c17" } ++ */ ++ ++ ++struct bat_gen_conf_s; ++void batch_generator_create2(struct bat_gen_conf_s* config, int D, int N, const long bat_dims[D][N], const long tot_dims[D][N], const long tot_strs[D][N], const _Complex float* data[D]); ++void batch_generator_create2(struct bat_gen_conf_s* config, int D, int N, const long bat_dims[D][N], const long tot_dims[D][N], const long tot_strs[D][N], const _Complex float* data[D]); ++ ++ ++ +diff --git a/gcc/testsuite/gcc.dg/pr110731.c b/gcc/testsuite/gcc.dg/pr110731.c +new file mode 100644 +index 00000000000..7da905d3163 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/pr110731.c +@@ -0,0 +1,17 @@ ++/* PR tree-optimization/110731 */ ++/* { dg-do run { target int128 } } */ ++/* { dg-options "-O2" } */ ++ ++__int128 ++foo (void) ++{ ++ struct S { __int128 f : 119; } s = { ((__int128) -18014398509481984) << 64 }; ++ return s.f / 2; ++} ++ ++int ++main () ++{ ++ if (foo () != (((__int128) -9007199254740992) << 64)) ++ __builtin_abort (); ++} +diff --git a/gcc/testsuite/gcc.dg/pr111015.c b/gcc/testsuite/gcc.dg/pr111015.c +new file mode 100644 +index 00000000000..599a14e6ecc +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/pr111015.c +@@ -0,0 +1,28 @@ ++/* PR tree-optimization/111015 */ ++/* { dg-do run { target int128 } } */ ++/* { dg-options "-O2" } */ ++ ++struct S { unsigned a : 4, b : 4; unsigned __int128 c : 70; } d; ++ ++__attribute__((noipa)) void ++foo (unsigned __int128 x, unsigned char y, unsigned char z) ++{ ++ d.a = y; ++ d.b = z; ++ d.c = x; ++} ++ ++int ++main () ++{ ++ foo (-1, 12, 5); ++ if (d.a != 12 ++ || d.b != 5 ++ || d.c != (-1ULL | (((unsigned __int128) 0x3f) << 64))) ++ __builtin_abort (); ++ foo (0x123456789abcdef0ULL | (((unsigned __int128) 26) << 64), 7, 11); ++ if (d.a != 7 ++ || d.b != 11 ++ || d.c != (0x123456789abcdef0ULL | (((unsigned __int128) 26) << 64))) ++ __builtin_abort (); ++} +diff --git a/gcc/testsuite/gcc.dg/pr112733.c b/gcc/testsuite/gcc.dg/pr112733.c +new file mode 100644 +index 00000000000..d6f99f76077 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/pr112733.c +@@ -0,0 +1,16 @@ ++/* PR middle-end/112733 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++signed char a, c; ++short b; ++ ++void ++foo (void) ++{ ++ signed char *e = &a; ++ c = foo != 0; ++ *e &= c; ++ for (; b; --b) ++ *e &= -128; ++} +diff --git a/gcc/testsuite/gcc.dg/pr112837.c b/gcc/testsuite/gcc.dg/pr112837.c +new file mode 100644 +index 00000000000..2de43f5479a +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/pr112837.c +@@ -0,0 +1,11 @@ ++/* PR target/112837 */ ++/* { dg-do compile } */ ++/* { dg-options "-fcompare-elim -fprofile" } */ ++/* { dg-additional-options "-fpie" { target pie } } */ ++/* { dg-require-profiling "-fprofile" } */ ++ ++void ++foo (int i) ++{ ++ foo (i); ++} +diff --git a/gcc/testsuite/gcc.dg/pr112845.c b/gcc/testsuite/gcc.dg/pr112845.c +new file mode 100644 +index 00000000000..ece6f451e75 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/pr112845.c +@@ -0,0 +1,9 @@ ++/* PR target/112845 */ ++/* { dg-do compile { target cet } } */ ++/* { dg-options "-Os -fcf-protection" } */ ++ ++unsigned long long ++foo (void) ++{ ++ return 0xfa1e0ff3ULL << 3; ++} +diff --git a/gcc/testsuite/gcc.dg/pr113013.c b/gcc/testsuite/gcc.dg/pr113013.c +new file mode 100644 +index 00000000000..b34964071b7 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/pr113013.c +@@ -0,0 +1,14 @@ ++/* PR tree-optimization/113013 */ ++/* { dg-do compile } */ ++/* { dg-options "-std=gnu99 -O2" } */ ++ ++struct S { short x; } s; ++void *foo () __attribute__((__alloc_size__(1))); ++struct S *p; ++ ++__SIZE_TYPE__ ++bar (void) ++{ ++ p = foo (s); ++ return __builtin_dynamic_object_size (p, 0); ++} +diff --git a/gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c b/gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c +new file mode 100644 +index 00000000000..ad07e9c6c89 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c +@@ -0,0 +1,57 @@ ++/* { dg-do compile { target aarch64*-*-* } } */ ++/* { dg-require-effective-target lp64 } */ ++/* { dg-options "-O -fdisable-rtl-postreload -fpeephole2 -fno-schedule-fusion" } */ ++ ++extern int data[]; ++ ++void __RTL (startwith ("ira")) foo (void *ptr) ++{ ++ (function "foo" ++ (param "ptr" ++ (DECL_RTL (reg/v:DI <0> [ ptr ])) ++ (DECL_RTL_INCOMING (reg/v:DI x0 [ ptr ])) ++ ) ;; param "ptr" ++ (insn-chain ++ (block 2 ++ (edge-from entry (flags "FALLTHRU")) ++ (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) ++ (insn 4 (set (reg:DI <0>) (reg:DI x0))) ++ (insn 5 (set (reg:DI <1>) ++ (plus:DI (reg:DI <0>) (const_int 768)))) ++ (insn 6 (set (mem:SI (plus:DI (reg:DI <0>) ++ (const_int 508)) [1 &data+508 S4 A4]) ++ (const_int 0))) ++ (insn 7 (set (mem:SI (plus:DI (reg:DI <1>) ++ (const_int -256)) [1 &data+512 S4 A4]) ++ (const_int 0))) ++ (edge-to exit (flags "FALLTHRU")) ++ ) ;; block 2 ++ ) ;; insn-chain ++ ) ;; function ++} ++ ++void __RTL (startwith ("ira")) bar (void *ptr) ++{ ++ (function "bar" ++ (param "ptr" ++ (DECL_RTL (reg/v:DI <0> [ ptr ])) ++ (DECL_RTL_INCOMING (reg/v:DI x0 [ ptr ])) ++ ) ;; param "ptr" ++ (insn-chain ++ (block 2 ++ (edge-from entry (flags "FALLTHRU")) ++ (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) ++ (insn 4 (set (reg:DI <0>) (reg:DI x0))) ++ (insn 5 (set (reg:DI <1>) ++ (plus:DI (reg:DI <0>) (const_int 768)))) ++ (insn 6 (set (mem:SI (plus:DI (reg:DI <1>) ++ (const_int -256)) [1 &data+512 S4 A4]) ++ (const_int 0))) ++ (insn 7 (set (mem:SI (plus:DI (reg:DI <0>) ++ (const_int 508)) [1 &data+508 S4 A4]) ++ (const_int 0))) ++ (edge-to exit (flags "FALLTHRU")) ++ ) ;; block 2 ++ ) ;; insn-chain ++ ) ;; function ++} +diff --git a/gcc/testsuite/gcc.dg/tls/pr78796.c b/gcc/testsuite/gcc.dg/tls/pr78796.c +index 038e5366e41..96f87d47ba4 100644 +--- a/gcc/testsuite/gcc.dg/tls/pr78796.c ++++ b/gcc/testsuite/gcc.dg/tls/pr78796.c +@@ -1,7 +1,7 @@ + /* PR target/78796 */ + /* { dg-do run } */ + /* { dg-options "-O2" } */ +-/* { dg-additional-options "-mcmodel=large" { target aarch64-*-* } } */ ++/* { dg-additional-options "-mcmodel=large -fno-pie -no-pie" { target aarch64-*-* } } */ + /* { dg-require-effective-target tls_runtime } */ + /* { dg-add-options tls } */ + +diff --git a/gcc/testsuite/gcc.dg/torture/pr110298.c b/gcc/testsuite/gcc.dg/torture/pr110298.c +new file mode 100644 +index 00000000000..139f5c77d89 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/torture/pr110298.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++ ++int a, b, c, d, e; ++int f() { ++ c = 0; ++ for (; c >= 0; c--) { ++ d = 0; ++ for (; d <= 0; d++) { ++ e = 0; ++ for (; d + c + e >= 0; e--) ++ ; ++ a = 1; ++ b = 0; ++ for (; a; ++b) ++ a *= 2; ++ for (; b + d >= 0;) ++ return 0; ++ } ++ } ++} +diff --git a/gcc/testsuite/gcc.dg/torture/pr110556.c b/gcc/testsuite/gcc.dg/torture/pr110556.c +new file mode 100644 +index 00000000000..bc60db885e2 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/torture/pr110556.c +@@ -0,0 +1,42 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target lp64 } */ ++/* { dg-additional-options "-fno-tree-fre -fno-delete-dead-exceptions -fnon-call-exceptions" } */ ++ ++typedef __INT32_TYPE__ int32_t; ++typedef __INT64_TYPE__ int64_t; ++ ++static int64_t __attribute__((noinline,noclone)) ++safe_mul_func_int64_t_s_s(int64_t si1, int64_t si2) ++{ ++ return ((((si1 > 0) && (si2 > 0) && (si1 > ( (9223372036854775807L) / si2))) ++ || ((si1 > 0) && (si2 <= 0) && (si2 < ( (-9223372036854775807L -1) / si1))) ++ || ((si1 <= 0) && (si2 > 0) && (si1 < ( (-9223372036854775807L -1) / si2))) ++ || ((si1 <= 0) && (si2 <= 0) && (si1 != 0) && (si2 < ( (9223372036854775807L) / si1)))) ++ ? ((si1)) : si1 * si2); ++} ++ ++static int32_t g_93 = 0x947A4BBFL; ++static int32_t tt = 6; ++int64_t ty, ty1; ++ ++static void func_34(void) ++{ ++ ty=safe_mul_func_int64_t_s_s (g_93, -1L) ; ++} ++static void func_30(void) ++{ ++ ty1=safe_mul_func_int64_t_s_s(0, tt); ++} ++static void func_6(void) ++{ ++ for (int g_9 = 5; (g_9 >= 0); g_9 -= 1) ++ { ++ func_34(); ++ func_30 (); ++ } ++} ++ ++int main () ++{ ++ func_6(); ++} +diff --git a/gcc/testsuite/gcc.dg/torture/pr110702.c b/gcc/testsuite/gcc.dg/torture/pr110702.c +new file mode 100644 +index 00000000000..aab9c7d923e +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/torture/pr110702.c +@@ -0,0 +1,31 @@ ++/* { dg-do run } */ ++ ++void abort (void); ++ ++int a, b, c, d; ++long e[9][7][4]; ++ ++void f() ++{ ++ for (; a >= 0; a--) ++ { ++ b = 0; ++ for (; b <= 3; b++) ++ { ++ c = 0; ++ for (; c <= 3; c++) ++ { ++ int *g = &d; ++ *g = e[0][0][b] | e[a][b][a]; ++ } ++ } ++ } ++} ++ ++int main() ++{ ++ f(); ++ if (a != -1) ++ abort (); ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.dg/torture/pr111137.c b/gcc/testsuite/gcc.dg/torture/pr111137.c +new file mode 100644 +index 00000000000..77560487926 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/torture/pr111137.c +@@ -0,0 +1,30 @@ ++/* { dg-do run } */ ++ ++int b[3][8]; ++short d; ++volatile int t = 1; ++ ++void __attribute__((noipa)) ++foo() ++{ ++ int g = t; ++ for (int e = 1; e >= 0; e--) ++ { ++ d = 1; ++ for (; d >= 0; d--) ++ { ++ b[0][d * 2 + 1] = 0; ++ b[g - 1 + d][0] ^= 1; ++ b[0][d * 2 + 2] = 0; ++ b[g - 1 + d][1] ^= 1; ++ } ++ } ++} ++ ++int ++main() ++{ ++ foo (); ++ if (b[0][1] != 1) ++ __builtin_abort(); ++} +diff --git a/gcc/testsuite/gcc.dg/torture/pr111445.c b/gcc/testsuite/gcc.dg/torture/pr111445.c +new file mode 100644 +index 00000000000..320e0b90675 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/torture/pr111445.c +@@ -0,0 +1,29 @@ ++/* { dg-do run } */ ++ ++extern void abort (void); ++short a, b; ++unsigned char c = 255; ++unsigned cnt; ++void __attribute__((noipa)) ++check (int x) ++{ ++ if (x != 0) ++ abort (); ++ cnt++; ++} ++int main() ++{ ++ int d; ++ unsigned char e; ++ d = 0; ++ for (; a >= 0; a--) { ++ int *f = &d; ++ *f = c; ++ } ++ e = 0; ++ for (; (unsigned char)(d - 255) + e <= 1; e++) ++ check (b); ++ if (cnt != 2) ++ abort (); ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.dg/torture/pr111614.c b/gcc/testsuite/gcc.dg/torture/pr111614.c +new file mode 100644 +index 00000000000..0f3ecbae86c +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/torture/pr111614.c +@@ -0,0 +1,23 @@ ++/* { dg-do compile } */ ++ ++int a, b, c, d, e; ++static void f() { ++ int *g = &b; ++ b = 1; ++ for (; b >= 0; b--) { ++ c = 0; ++ for (; c <= 1; c++) ++ e = 0; ++ for (; e <= 1; e++) { ++ int h, i = h = 13; ++ for (; h; h--) ++ i = i << a; ++ d &= i + c + 9 + *g; ++ } ++ } ++} ++int main() { ++ f(); ++ for (;;) ++ ; ++} +diff --git a/gcc/testsuite/gcc.dg/torture/pr111815.c b/gcc/testsuite/gcc.dg/torture/pr111815.c +new file mode 100644 +index 00000000000..5e80b77d13e +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/torture/pr111815.c +@@ -0,0 +1,26 @@ ++/* { dg-do run } */ ++ ++char x[] = { ++ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ++ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, ++}; ++ ++__attribute__ ((noinline)) char * ++p (char *a, int o, int i) ++{ ++ return a + ++o + (1 << ++i); ++} ++ ++int ++main (void) ++{ ++ if (*p (x, 0, 0) != 3) ++ return 1; ++ if (*p (x, 1, 2) != 10) ++ return 1; ++ if (*p (x, 2, 1) != 7) ++ return 1; ++ if (*p (x, 3, 3) != 20) ++ return 1; ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.dg/torture/pr111818.c b/gcc/testsuite/gcc.dg/torture/pr111818.c +new file mode 100644 +index 00000000000..a7a91111d71 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/torture/pr111818.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++ ++static void foo(const volatile unsigned int x, void *p) ++{ ++ __builtin_memcpy(p, (void *)&x, sizeof x); ++} ++ ++void bar(void *number) ++{ ++ foo(0, number); ++} +diff --git a/gcc/testsuite/gcc.dg/torture/pr111917.c b/gcc/testsuite/gcc.dg/torture/pr111917.c +new file mode 100644 +index 00000000000..532e30200b5 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/torture/pr111917.c +@@ -0,0 +1,23 @@ ++/* { dg-do compile } */ ++/* { dg-additional-options "-funswitch-loops" } */ ++ ++long t; ++long a() { ++ long b = t, c = t; ++ for (; b < 31; b++) ++ c <<= 1; ++ return c; ++} ++long t1; ++static ++int d() { ++ if (!t1) ++ return 0; ++e: ++f: ++ for (; a();) ++ ; ++ goto f; ++ return 0; ++} ++int main() { d(); } +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr111967.c b/gcc/testsuite/gcc.dg/tree-ssa/pr111967.c +new file mode 100644 +index 00000000000..bbef390228a +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr111967.c +@@ -0,0 +1,15 @@ ++/* PR tree-optimization/111967 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fno-tree-forwprop -fdump-tree-evrp-all" } */ ++ ++void bar (char *); ++int a; ++char *b; ++ ++void ++foo (void) ++{ ++ long c = a & 3; ++ if (c) ++ bar (b + c); ++} +diff --git a/gcc/testsuite/gcc.dg/vect/pr108950.c b/gcc/testsuite/gcc.dg/vect/pr108950.c +index ecf076c964b..563c4b9df38 100644 +--- a/gcc/testsuite/gcc.dg/vect/pr108950.c ++++ b/gcc/testsuite/gcc.dg/vect/pr108950.c +@@ -1,5 +1,5 @@ +-/* { dg-require-effective-target vect_simd_clones } */ + /* { dg-do compile } */ ++/* { dg-require-effective-target vect_simd_clones } */ + + int m; + short int n; +diff --git a/gcc/testsuite/gcc.dg/vect/pr111764.c b/gcc/testsuite/gcc.dg/vect/pr111764.c +new file mode 100644 +index 00000000000..f4e110f3bbf +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/vect/pr111764.c +@@ -0,0 +1,16 @@ ++#include "tree-vect.h" ++ ++short b = 2; ++ ++int main() ++{ ++ check_vect (); ++ ++ for (int a = 1; a <= 9; a++) ++ b = b * b; ++ if (b != 0) ++ __builtin_abort (); ++ ++ return 0; ++} ++ +diff --git a/gcc/testsuite/gcc.dg/vect/pr97428.c b/gcc/testsuite/gcc.dg/vect/pr97428.c +index bbd743a76c4..ad6416096aa 100644 +--- a/gcc/testsuite/gcc.dg/vect/pr97428.c ++++ b/gcc/testsuite/gcc.dg/vect/pr97428.c +@@ -1,4 +1,5 @@ + /* { dg-do compile } */ ++/* { dg-require-effective-target vect_double } */ + + typedef struct { double re, im; } dcmlx_t; + typedef struct { double re[4], im[4]; } dcmlx4_t; +diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp b/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp +index 3e652c483c7..eb7c531615c 100644 +--- a/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp ++++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp +@@ -27,7 +27,7 @@ if { ![istarget aarch64*-*-*] } then { + + torture-init + set-torture-options $C_TORTURE_OPTIONS +-set additional_flags "-W -Wall -Wno-abi" ++set additional_flags "-W -Wall -Wno-abi -fno-pie -no-pie" + + # Test parameter passing. This uses abitest.S which relies on weak + # symbols. +diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c +new file mode 100644 +index 00000000000..8b4f2427771 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c +@@ -0,0 +1,10 @@ ++/* { dg-do link { target aarch64_asm_ls64_ok } } */ ++/* { dg-additional-options "-march=armv8.7-a -flto" } */ ++#include ++int main(void) ++{ ++ data512_t d = __arm_ld64b ((const void *)0x1000); ++ __arm_st64b ((void *)0x2000, d); ++ uint64_t x = __arm_st64bv ((void *)0x3000, d); ++ x += __arm_st64bv0 ((void *)0x4000, d); ++} +diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c b/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c +new file mode 100644 +index 00000000000..f56d5e619e8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c +@@ -0,0 +1,7 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=armv8.7-a -O2" } */ ++#include ++void do_st64b(data512_t data) { ++ __arm_st64b((void*)0x10000000, data); ++} ++/* { dg-final { scan-assembler {mov\tx([123])?[0-9], 268435456} } } */ +diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c b/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c +new file mode 100644 +index 00000000000..fb88d633dd2 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-additional-options "-march=armv8.7-a" } */ ++ ++/* Check that ls64 builtins can be invoked using a preprocesed testcase ++ without triggering bogus builtin warnings, see PR110132. ++ ++ Note that this is purely to test GCC internals and user code should ++ include arm_acle.h to make use of these builtins. */ ++ ++#pragma GCC aarch64 "arm_acle.h" ++typedef __arm_data512_t data512_t; ++void f(void *p, data512_t d) ++{ ++ __arm_st64b (p, d); ++} +diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-7.c b/gcc/testsuite/gcc.target/aarch64/auto-init-7.c +index ac27fbe92f4..fde6e568532 100644 +--- a/gcc/testsuite/gcc.target/aarch64/auto-init-7.c ++++ b/gcc/testsuite/gcc.target/aarch64/auto-init-7.c +@@ -1,6 +1,6 @@ + /* Verify zero initialization for array, union, and structure type automatic variables. */ + /* { dg-do compile } */ +-/* { dg-options "-ftrivial-auto-var-init=zero -fdump-rtl-expand" } */ ++/* { dg-options "-ftrivial-auto-var-init=zero -fdump-rtl-expand -fno-stack-protector" } */ + + struct S + { +diff --git a/gcc/testsuite/gcc.target/aarch64/fuse_adrp_add_1.c b/gcc/testsuite/gcc.target/aarch64/fuse_adrp_add_1.c +index e49aadaa639..d66fe3a4b23 100644 +--- a/gcc/testsuite/gcc.target/aarch64/fuse_adrp_add_1.c ++++ b/gcc/testsuite/gcc.target/aarch64/fuse_adrp_add_1.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* { dg-require-effective-target aarch64_small } */ +-/* { dg-options "-O3 -mcpu=cortex-a57" } */ ++/* { dg-options "-O3 -mcpu=cortex-a57 -fno-pie" } */ + + enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS, + XGRF_REGS, ALL_REGS, LIM_REG_CLASSES }; +diff --git a/gcc/testsuite/gcc.target/aarch64/mops_4.c b/gcc/testsuite/gcc.target/aarch64/mops_4.c +index 1b87759cb5e..dd796115cb4 100644 +--- a/gcc/testsuite/gcc.target/aarch64/mops_4.c ++++ b/gcc/testsuite/gcc.target/aarch64/mops_4.c +@@ -50,6 +50,54 @@ copy3 (int *x, int *y, long z, long *res) + *res = z; + } + ++/* ++** move1: ++** mov (x[0-9]+), x0 ++** cpyp \[\1\]!, \[x1\]!, x2! ++** cpym \[\1\]!, \[x1\]!, x2! ++** cpye \[\1\]!, \[x1\]!, x2! ++** str x0, \[x3\] ++** ret ++*/ ++void ++move1 (int *x, int *y, long z, int **res) ++{ ++ __builtin_memmove (x, y, z); ++ *res = x; ++} ++ ++/* ++** move2: ++** mov (x[0-9]+), x1 ++** cpyp \[x0\]!, \[\1\]!, x2! ++** cpym \[x0\]!, \[\1\]!, x2! ++** cpye \[x0\]!, \[\1\]!, x2! ++** str x1, \[x3\] ++** ret ++*/ ++void ++move2 (int *x, int *y, long z, int **res) ++{ ++ __builtin_memmove (x, y, z); ++ *res = y; ++} ++ ++/* ++** move3: ++** mov (x[0-9]+), x2 ++** cpyp \[x0\]!, \[x1\]!, \1! ++** cpym \[x0\]!, \[x1\]!, \1! ++** cpye \[x0\]!, \[x1\]!, \1! ++** str x2, \[x3\] ++** ret ++*/ ++void ++move3 (int *x, int *y, long z, long *res) ++{ ++ __builtin_memmove (x, y, z); ++ *res = z; ++} ++ + /* + ** set1: + ** mov (x[0-9]+), x0 +diff --git a/gcc/testsuite/gcc.target/aarch64/pr103147-10.c b/gcc/testsuite/gcc.target/aarch64/pr103147-10.c +index b2c34e4155d..57942bfd10a 100644 +--- a/gcc/testsuite/gcc.target/aarch64/pr103147-10.c ++++ b/gcc/testsuite/gcc.target/aarch64/pr103147-10.c +@@ -1,4 +1,4 @@ +-/* { dg-options "-O2 -fpack-struct -mstrict-align" } */ ++/* { dg-options "-O2 -fpack-struct -mstrict-align -fno-stack-protector" } */ + /* { dg-final { check-function-bodies "**" "" "" } } */ + + #include +diff --git a/gcc/testsuite/gcc.target/aarch64/pr104005.c b/gcc/testsuite/gcc.target/aarch64/pr104005.c +index 09dd81910eb..9f1ef2dc308 100644 +--- a/gcc/testsuite/gcc.target/aarch64/pr104005.c ++++ b/gcc/testsuite/gcc.target/aarch64/pr104005.c +@@ -1,4 +1,4 @@ +-/* { dg-options "-O2 -funroll-loops" } */ ++/* { dg-options "-O2 -funroll-loops -fno-stack-protector" } */ + + typedef int v2 __attribute__((vector_size(8))); + +diff --git a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c +index 9f1ed947806..5d519d817cc 100644 +--- a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c ++++ b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c +@@ -1,6 +1,6 @@ + /* { dg-do assemble } */ + /* { dg-require-effective-target lp64 } */ +-/* { dg-options "-O1 --save-temps" } */ ++/* { dg-options "-O1 --save-temps -fno-pie" } */ + #pragma GCC push_options + #pragma GCC target ("+nothing+simd,cmodel=small") + +diff --git a/gcc/testsuite/gcc.target/aarch64/pr70120-2.c b/gcc/testsuite/gcc.target/aarch64/pr70120-2.c +index 663bf2ed147..8f5cdc93fe3 100644 +--- a/gcc/testsuite/gcc.target/aarch64/pr70120-2.c ++++ b/gcc/testsuite/gcc.target/aarch64/pr70120-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* { dg-require-effective-target lp64 } */ +-/* { dg-options "-Og -freorder-functions -g3 -mcmodel=large" } */ ++/* { dg-options "-Og -freorder-functions -g3 -mcmodel=large -fno-pie" } */ + + typedef short v32u16 __attribute__ ((vector_size (32))); + typedef int v32u32 __attribute__ ((vector_size (32))); +diff --git a/gcc/testsuite/gcc.target/aarch64/pr78733.c b/gcc/testsuite/gcc.target/aarch64/pr78733.c +index 4695b5c1b2b..8556ef3f371 100644 +--- a/gcc/testsuite/gcc.target/aarch64/pr78733.c ++++ b/gcc/testsuite/gcc.target/aarch64/pr78733.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */ ++/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads -fno-pie" } */ + /* { dg-require-effective-target lp64 } */ + /* { dg-skip-if "-mcmodel=large, no support for -fpic" { aarch64-*-* } { "-fpic" } { "" } } */ + +diff --git a/gcc/testsuite/gcc.target/aarch64/pr79041-2.c b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c +index 4695b5c1b2b..8556ef3f371 100644 +--- a/gcc/testsuite/gcc.target/aarch64/pr79041-2.c ++++ b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */ ++/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads -fno-pie" } */ + /* { dg-require-effective-target lp64 } */ + /* { dg-skip-if "-mcmodel=large, no support for -fpic" { aarch64-*-* } { "-fpic" } { "" } } */ + +diff --git a/gcc/testsuite/gcc.target/aarch64/pr94530.c b/gcc/testsuite/gcc.target/aarch64/pr94530.c +index 2797d116dcf..5dfdbe3311d 100644 +--- a/gcc/testsuite/gcc.target/aarch64/pr94530.c ++++ b/gcc/testsuite/gcc.target/aarch64/pr94530.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* { dg-require-effective-target lp64 } */ +-/* { dg-options "-Os -mcpu=falkor -mpc-relative-literal-loads -mcmodel=large" } */ ++/* { dg-options "-Os -mcpu=falkor -mpc-relative-literal-loads -mcmodel=large -fno-pie" } */ + + extern void bar(const char *); + +diff --git a/gcc/testsuite/gcc.target/aarch64/pr94577.c b/gcc/testsuite/gcc.target/aarch64/pr94577.c +index 6f2d3612c26..d51799fb0bb 100644 +--- a/gcc/testsuite/gcc.target/aarch64/pr94577.c ++++ b/gcc/testsuite/gcc.target/aarch64/pr94577.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-mcmodel=large -mabi=ilp32" } */ ++/* { dg-options "-mcmodel=large -mabi=ilp32 -fno-pie" } */ + + void + foo () +diff --git a/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c b/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c +index 7b1982abb61..37e00ac9aa1 100644 +--- a/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c ++++ b/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* { dg-require-effective-target lp64 } */ +-/* { dg-options "-O2 -mcmodel=large -fno-builtin" } */ ++/* { dg-options "-O2 -mcmodel=large -fno-builtin -fno-pie" } */ + /* { dg-skip-if "-mcmodel=large -fPIC not currently supported" { aarch64-*-* } { "-fPIC" } { "" } } */ + + typedef long unsigned int size_t; +diff --git a/gcc/testsuite/gcc.target/aarch64/shrink_wrap_1.c b/gcc/testsuite/gcc.target/aarch64/shrink_wrap_1.c +index ab7cd74ec3b..067220c04a0 100644 +--- a/gcc/testsuite/gcc.target/aarch64/shrink_wrap_1.c ++++ b/gcc/testsuite/gcc.target/aarch64/shrink_wrap_1.c +@@ -1,5 +1,5 @@ + /* { dg-do compile { target { aarch64*-*-* } } } */ +-/* { dg-options "-O2" } */ ++/* { dg-options "-O2 -fno-stack-protector" } */ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-1.c b/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-1.c +index 6885894a97e..412a9ed1aab 100644 +--- a/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-1.c ++++ b/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-1.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables" } */ ++/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables -fno-stack-protector" } */ + /* { dg-require-effective-target supports_stack_clash_protection } */ + + #define SIZE 128*1024 +diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-2.c b/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-2.c +index 5796a53be06..e440569a078 100644 +--- a/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-2.c ++++ b/gcc/testsuite/gcc.target/aarch64/stack-check-cfa-2.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables" } */ ++/* { dg-options "-O2 -fstack-clash-protection --param stack-clash-protection-guard-size=16 -funwind-tables -fno-stack-protector" } */ + /* { dg-require-effective-target supports_stack_clash_protection } */ + + #define SIZE 1280*1024 + 512 +diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-17.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-17.c +new file mode 100644 +index 00000000000..f0ec1389771 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-17.c +@@ -0,0 +1,55 @@ ++/* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++void f(int, ...); ++void g(); ++ ++/* ++** test1: ++** ... ++** str x30, \[sp\] ++** sub sp, sp, #1024 ++** cbnz w0, .* ++** bl g ++** ... ++*/ ++int test1(int z) { ++ __uint128_t x = 0; ++ int y[0x400]; ++ if (z) ++ { ++ f(0, 0, 0, 0, 0, 0, 0, &y, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x); ++ } ++ g(); ++ return 1; ++} ++ ++/* ++** test2: ++** ... ++** str x30, \[sp\] ++** sub sp, sp, #1040 ++** str xzr, \[sp, #?1024\] ++** cbnz w0, .* ++** bl g ++** ... ++*/ ++int test2(int z) { ++ __uint128_t x = 0; ++ int y[0x400]; ++ if (z) ++ { ++ f(0, 0, 0, 0, 0, 0, 0, &y, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x); ++ } ++ g(); ++ return 1; ++} +diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-18.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-18.c +new file mode 100644 +index 00000000000..6383bec5ebc +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-18.c +@@ -0,0 +1,100 @@ ++/* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++void f(int, ...); ++void g(); ++ ++/* ++** test1: ++** ... ++** str x30, \[sp\] ++** sub sp, sp, #4064 ++** str xzr, \[sp, #?1024\] ++** cbnz w0, .* ++** bl g ++** ... ++** str x26, \[sp, #?4128\] ++** ... ++*/ ++int test1(int z) { ++ __uint128_t x = 0; ++ int y[0x400]; ++ if (z) ++ { ++ asm volatile ("" ::: ++ "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26"); ++ f(0, 0, 0, 0, 0, 0, 0, &y, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x); ++ } ++ g(); ++ return 1; ++} ++ ++/* ++** test2: ++** ... ++** str x30, \[sp\] ++** sub sp, sp, #1040 ++** str xzr, \[sp, #?1024\] ++** cbnz w0, .* ++** bl g ++** ... ++*/ ++int test2(int z) { ++ __uint128_t x = 0; ++ int y[0x400]; ++ if (z) ++ { ++ asm volatile ("" ::: ++ "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26"); ++ f(0, 0, 0, 0, 0, 0, 0, &y, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x); ++ } ++ g(); ++ return 1; ++} ++ ++/* ++** test3: ++** ... ++** str x30, \[sp\] ++** sub sp, sp, #1024 ++** cbnz w0, .* ++** bl g ++** ... ++*/ ++int test3(int z) { ++ __uint128_t x = 0; ++ int y[0x400]; ++ if (z) ++ { ++ asm volatile ("" ::: ++ "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26"); ++ f(0, 0, 0, 0, 0, 0, 0, &y, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x); ++ } ++ g(); ++ return 1; ++} +diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c +new file mode 100644 +index 00000000000..562039b5e9b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-19.c +@@ -0,0 +1,100 @@ ++/* { dg-options "-O2 -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12 -fsanitize=shadow-call-stack -ffixed-x18" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++void f(int, ...); ++void g(); ++ ++/* ++** test1: ++** ... ++** str x30, \[sp\] ++** sub sp, sp, #4064 ++** str xzr, \[sp, #?1024\] ++** cbnz w0, .* ++** bl g ++** ... ++** str x26, \[sp, #?4128\] ++** ... ++*/ ++int test1(int z) { ++ __uint128_t x = 0; ++ int y[0x400]; ++ if (z) ++ { ++ asm volatile ("" ::: ++ "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26"); ++ f(0, 0, 0, 0, 0, 0, 0, &y, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x); ++ } ++ g(); ++ return 1; ++} ++ ++/* ++** test2: ++** ... ++** str x30, \[sp\] ++** sub sp, sp, #1040 ++** str xzr, \[sp, #?1024\] ++** cbnz w0, .* ++** bl g ++** ... ++*/ ++int test2(int z) { ++ __uint128_t x = 0; ++ int y[0x400]; ++ if (z) ++ { ++ asm volatile ("" ::: ++ "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26"); ++ f(0, 0, 0, 0, 0, 0, 0, &y, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x); ++ } ++ g(); ++ return 1; ++} ++ ++/* ++** test3: ++** ... ++** str x30, \[sp\] ++** sub sp, sp, #1024 ++** cbnz w0, .* ++** bl g ++** ... ++*/ ++int test3(int z) { ++ __uint128_t x = 0; ++ int y[0x400]; ++ if (z) ++ { ++ asm volatile ("" ::: ++ "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26"); ++ f(0, 0, 0, 0, 0, 0, 0, &y, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, ++ x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x); ++ } ++ g(); ++ return 1; ++} +diff --git a/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-20.c b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-20.c +new file mode 100644 +index 00000000000..690aae8dfd5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/stack-check-prologue-20.c +@@ -0,0 +1,3 @@ ++/* { dg-options "-O2 -fstack-protector-all -fstack-clash-protection -fomit-frame-pointer --param stack-clash-protection-guard-size=12 -fsanitize=shadow-call-stack -ffixed-x18" } */ ++ ++#include "stack-check-prologue-19.c" +diff --git a/gcc/testsuite/gcc.target/aarch64/stack-protector-8.c b/gcc/testsuite/gcc.target/aarch64/stack-protector-8.c +new file mode 100644 +index 00000000000..e71d820e365 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/stack-protector-8.c +@@ -0,0 +1,95 @@ ++/* { dg-options " -O -fstack-protector-strong -mstack-protector-guard=sysreg -mstack-protector-guard-reg=tpidr2_el0 -mstack-protector-guard-offset=16" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++void g(void *); ++__SVBool_t *h(void *); ++ ++/* ++** test1: ++** sub sp, sp, #288 ++** stp x29, x30, \[sp, #?272\] ++** add x29, sp, #?272 ++** mrs (x[0-9]+), tpidr2_el0 ++** ldr (x[0-9]+), \[\1, #?16\] ++** str \2, \[sp, #?264\] ++** mov \2, #?0 ++** add x0, sp, #?8 ++** bl g ++** ... ++** mrs .* ++** ... ++** bne .* ++** ... ++** ldp x29, x30, \[sp, #?272\] ++** add sp, sp, #?288 ++** ret ++** bl __stack_chk_fail ++*/ ++int test1() { ++ int y[0x40]; ++ g(y); ++ return 1; ++} ++ ++/* ++** test2: ++** stp x29, x30, \[sp, #?-16\]! ++** mov x29, sp ++** sub sp, sp, #1040 ++** mrs (x[0-9]+), tpidr2_el0 ++** ldr (x[0-9]+), \[\1, #?16\] ++** str \2, \[sp, #?1032\] ++** mov \2, #?0 ++** add x0, sp, #?8 ++** bl g ++** ... ++** mrs .* ++** ... ++** bne .* ++** ... ++** add sp, sp, #?1040 ++** ldp x29, x30, \[sp\], #?16 ++** ret ++** bl __stack_chk_fail ++*/ ++int test2() { ++ int y[0x100]; ++ g(y); ++ return 1; ++} ++ ++#pragma GCC target "+sve" ++ ++/* ++** test3: ++** stp x29, x30, \[sp, #?-16\]! ++** mov x29, sp ++** addvl sp, sp, #-18 ++** ... ++** str p4, \[sp\] ++** ... ++** sub sp, sp, #272 ++** mrs (x[0-9]+), tpidr2_el0 ++** ldr (x[0-9]+), \[\1, #?16\] ++** str \2, \[sp, #?264\] ++** mov \2, #?0 ++** add x0, sp, #?8 ++** bl h ++** ... ++** mrs .* ++** ... ++** bne .* ++** ... ++** add sp, sp, #?272 ++** ... ++** ldr p4, \[sp\] ++** ... ++** addvl sp, sp, #18 ++** ldp x29, x30, \[sp\], #?16 ++** ret ++** bl __stack_chk_fail ++*/ ++__SVBool_t test3() { ++ int y[0x40]; ++ return *h(y); ++} +diff --git a/gcc/testsuite/gcc.target/aarch64/stack-protector-9.c b/gcc/testsuite/gcc.target/aarch64/stack-protector-9.c +new file mode 100644 +index 00000000000..58f322aa480 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/stack-protector-9.c +@@ -0,0 +1,33 @@ ++/* { dg-options "-O2 -mcpu=neoverse-v1 -fstack-protector-all" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** main: ++** ... ++** stp x29, x30, \[sp, #?-[0-9]+\]! ++** ... ++** sub sp, sp, #[0-9]+ ++** ... ++** str x[0-9]+, \[x29, #?-8\] ++** ... ++*/ ++int f(const char *); ++void g(void *); ++int main(int argc, char* argv[]) ++{ ++ int a; ++ int b; ++ char c[2+f(argv[1])]; ++ int d[0x100]; ++ char y; ++ ++ y=42; a=4; b=10; ++ c[0] = 'h'; c[1] = '\0'; ++ ++ c[f(argv[2])] = '\0'; ++ ++ __builtin_printf("%d %d\n%s\n", a, b, c); ++ g(d); ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp b/gcc/testsuite/gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp +index 83786733f35..76f5fd4ffd8 100644 +--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp ++++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp +@@ -37,11 +37,12 @@ if ![info exists DEFAULT_CFLAGS] then { + # Initialize `dg'. + dg-init + +-# Force SVE if we're not testing it already. ++# Force SVE if we're not testing it already. And, disable stack protector ++# to avoid test failures with --enable-default-ssp. + if { [check_effective_target_aarch64_sve] } { +- set sve_flags "" ++ set sve_flags "-fno-stack-protector" + } else { +- set sve_flags "-march=armv8.2-a+sve" ++ set sve_flags "-march=armv8.2-a+sve -fno-stack-protector" + } + + # Main loop. +diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_3.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_3.c +index 3e01ec36c3a..3530a0d504b 100644 +--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_3.c ++++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_3.c +@@ -11,11 +11,10 @@ + ** mov x11, sp + ** ... + ** sub sp, sp, x13 +-** str p4, \[sp\] + ** cbz w0, [^\n]* ++** str p4, \[sp\] + ** ... + ** ptrue p0\.b, all +-** ldr p4, \[sp\] + ** addvl sp, sp, #1 + ** ldr x24, \[sp\], 32 + ** ret +@@ -39,13 +38,12 @@ test_1 (int n) + ** mov x11, sp + ** ... + ** sub sp, sp, x13 +-** str p4, \[sp\] + ** cbz w0, [^\n]* ++** str p4, \[sp\] + ** str p5, \[sp, #1, mul vl\] + ** str p6, \[sp, #2, mul vl\] + ** ... + ** ptrue p0\.b, all +-** ldr p4, \[sp\] + ** addvl sp, sp, #1 + ** ldr x24, \[sp\], 32 + ** ret +diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr109505.c b/gcc/testsuite/gcc.target/aarch64/sve/pr109505.c +new file mode 100644 +index 00000000000..b975ae75ae6 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/aarch64/sve/pr109505.c +@@ -0,0 +1,12 @@ ++/* PR tree-optimization/109505 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv8.2-a+sve" } */ ++ ++#pragma GCC aarch64 "arm_sve.h" ++ ++unsigned long ++foo (unsigned long x) ++{ ++ unsigned long y = svcntb (); ++ return (x | 15) & y; ++} +diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_17.c b/gcc/testsuite/gcc.target/aarch64/test_frame_17.c +index 44f13291128..5d432ad0854 100644 +--- a/gcc/testsuite/gcc.target/aarch64/test_frame_17.c ++++ b/gcc/testsuite/gcc.target/aarch64/test_frame_17.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2" } */ ++/* { dg-options "-O2 -fno-stack-protector" } */ + + /* Test reuse of stack adjustment temporaries. */ + +diff --git a/gcc/testsuite/gcc.target/alpha/pr106966.c b/gcc/testsuite/gcc.target/alpha/pr106966.c +new file mode 100644 +index 00000000000..7145c2096c6 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/alpha/pr106966.c +@@ -0,0 +1,13 @@ ++/* PR target/106906 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mbuild-constants" } */ ++ ++void ++do_console (unsigned short *vga) ++{ ++ vga[0] = 'H'; ++ vga[1] = 'e'; ++ vga[2] = 'l'; ++ vga[3] = 'l'; ++ vga[4] = 'o'; ++} +diff --git a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c +index 501cc84da10..e3e7f7ef3e5 100644 +--- a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c ++++ b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c +@@ -567,80 +567,80 @@ + contain back references). */ + /* + ** test_cde_vcx1q_mfloat16x8_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1q_mfloat32x4_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1q_muint8x16_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1q_muint16x8_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1q_muint32x4_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1q_muint64x2_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1q_mint8x16_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1q_mint16x8_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1q_mint32x4_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1q_mint64x2_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1t p0, q0, #32 + ** bx lr +@@ -649,80 +649,80 @@ + + /* + ** test_cde_vcx1qa_mfloat16x8_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1qa_mfloat32x4_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1qa_muint8x16_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1qa_muint16x8_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1qa_muint32x4_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1qa_muint64x2_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1qa_mint8x16_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1qa_mint16x8_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1qa_mint32x4_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr + */ + /* + ** test_cde_vcx1qa_mint64x2_tintint: +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +-** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) ++** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr p0, r2 @ movhi) + ** vpst + ** vcx1at p0, q0, #32 + ** bx lr +@@ -731,8 +731,8 @@ + + /* + ** test_cde_vcx2q_mfloat16x8_tuint16x8_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -740,8 +740,8 @@ + */ + /* + ** test_cde_vcx2q_mfloat16x8_tfloat32x4_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -749,8 +749,8 @@ + */ + /* + ** test_cde_vcx2q_mfloat32x4_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -758,8 +758,8 @@ + */ + /* + ** test_cde_vcx2q_mint64x2_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -767,8 +767,8 @@ + */ + /* + ** test_cde_vcx2q_mint8x16_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -776,8 +776,8 @@ + */ + /* + ** test_cde_vcx2q_muint16x8_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -785,8 +785,8 @@ + */ + /* + ** test_cde_vcx2q_muint8x16_tint64x2_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -794,8 +794,8 @@ + */ + /* + ** test_cde_vcx2q_muint8x16_tint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -803,8 +803,8 @@ + */ + /* + ** test_cde_vcx2q_muint8x16_tuint16x8_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -812,8 +812,8 @@ + */ + /* + ** test_cde_vcx2q_muint8x16_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2t p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -823,8 +823,8 @@ + + /* + ** test_cde_vcx2qa_mfloat16x8_tuint16x8_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -832,8 +832,8 @@ + */ + /* + ** test_cde_vcx2qa_mfloat16x8_tfloat32x4_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -841,8 +841,8 @@ + */ + /* + ** test_cde_vcx2qa_mfloat32x4_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -850,8 +850,8 @@ + */ + /* + ** test_cde_vcx2qa_mint64x2_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -859,8 +859,8 @@ + */ + /* + ** test_cde_vcx2qa_mint8x16_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -868,8 +868,8 @@ + */ + /* + ** test_cde_vcx2qa_muint16x8_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -877,8 +877,8 @@ + */ + /* + ** test_cde_vcx2qa_muint8x16_tint64x2_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -886,8 +886,8 @@ + */ + /* + ** test_cde_vcx2qa_muint8x16_tint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -895,8 +895,8 @@ + */ + /* + ** test_cde_vcx2qa_muint8x16_tuint16x8_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -904,8 +904,8 @@ + */ + /* + ** test_cde_vcx2qa_muint8x16_tuint8x16_tint: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r1 @ movhi) + ** vpst + ** vcx2at p0, (q[0-7]), q0, #32 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -915,8 +915,8 @@ + + /* + ** test_cde_vcx3q_muint8x16_tuint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -924,8 +924,8 @@ + */ + /* + ** test_cde_vcx3q_mfloat16x8_tfloat16x8_tfloat16x8_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -933,8 +933,8 @@ + */ + /* + ** test_cde_vcx3q_mfloat32x4_tuint64x2_tfloat16x8_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -942,8 +942,8 @@ + */ + /* + ** test_cde_vcx3q_muint16x8_tuint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -951,8 +951,8 @@ + */ + /* + ** test_cde_vcx3q_muint8x16_tuint16x8_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -960,8 +960,8 @@ + */ + /* + ** test_cde_vcx3q_muint8x16_tuint8x16_tuint16x8_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -969,8 +969,8 @@ + */ + /* + ** test_cde_vcx3q_mint8x16_tuint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -978,8 +978,8 @@ + */ + /* + ** test_cde_vcx3q_muint8x16_tint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -987,8 +987,8 @@ + */ + /* + ** test_cde_vcx3q_muint8x16_tuint8x16_tint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -996,8 +996,8 @@ + */ + /* + ** test_cde_vcx3q_mint64x2_tuint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1005,8 +1005,8 @@ + */ + /* + ** test_cde_vcx3q_muint8x16_tint64x2_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1014,8 +1014,8 @@ + */ + /* + ** test_cde_vcx3q_muint8x16_tuint8x16_tint64x2_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1023,8 +1023,8 @@ + */ + /* + ** test_cde_vcx3q_muint8x16_tint64x2_tint64x2_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3t p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1034,8 +1034,8 @@ + + /* + ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1043,8 +1043,8 @@ + */ + /* + ** test_cde_vcx3qa_mfloat16x8_tfloat16x8_tfloat16x8_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1052,8 +1052,8 @@ + */ + /* + ** test_cde_vcx3qa_mfloat32x4_tuint64x2_tfloat16x8_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1061,8 +1061,8 @@ + */ + /* + ** test_cde_vcx3qa_muint16x8_tuint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1070,8 +1070,8 @@ + */ + /* + ** test_cde_vcx3qa_muint8x16_tuint16x8_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1079,8 +1079,8 @@ + */ + /* + ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint16x8_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1088,8 +1088,8 @@ + */ + /* + ** test_cde_vcx3qa_mint8x16_tuint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1097,8 +1097,8 @@ + */ + /* + ** test_cde_vcx3qa_muint8x16_tint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1106,8 +1106,8 @@ + */ + /* + ** test_cde_vcx3qa_muint8x16_tuint8x16_tint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1115,8 +1115,8 @@ + */ + /* + ** test_cde_vcx3qa_mint64x2_tuint8x16_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1124,8 +1124,8 @@ + */ + /* + ** test_cde_vcx3qa_muint8x16_tint64x2_tuint8x16_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1133,8 +1133,8 @@ + */ + /* + ** test_cde_vcx3qa_muint8x16_tuint8x16_tint64x2_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +@@ -1142,8 +1142,8 @@ + */ + /* + ** test_cde_vcx3qa_muint8x16_tint64x2_tint64x2_t: +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +-** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) ++** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr p0, r0 @ movhi) + ** vpst + ** vcx3at p0, (q[0-7]), q0, q1, #15 + ** vmov q0, \1([[:space:]]+@ [^\n]*)? +diff --git a/gcc/testsuite/gcc.target/arm/mve/general/preserve_user_namespace_1.c b/gcc/testsuite/gcc.target/arm/mve/general/preserve_user_namespace_1.c +new file mode 100644 +index 00000000000..f107ac44ca9 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/general/preserve_user_namespace_1.c +@@ -0,0 +1,6 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#define __ARM_MVE_PRESERVE_USER_NAMESPACE ++#include +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c +index a2d5160e518..1aa576afae3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** asrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64_t +-asrl_reg (int64_t longval3, int32_t x) ++foo (int64_t value, int32_t shift) + { +- return asrl (longval3, x); ++ return asrl (value, shift); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "asrl\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c +index 9c1b62fb9f2..5542ac8c316 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** lsll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint64_t +-lsll_reg (uint64_t longval3, int32_t x) ++foo (uint64_t value, int32_t shift) + { +- return lsll (longval3, x); ++ return lsll (value, shift); ++} ++ ++/* ++**foo1: ++** ... ++** lsll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint64_t ++foo1 (int32_t shift) ++{ ++ return lsll (1, shift); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "lsll\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c +deleted file mode 100644 +index 714fbf9bfe7..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c ++++ /dev/null +@@ -1,47 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include +-int8x16_t foo (int8x16_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-int16x8_t foo1 (int16x8_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-int32x4_t foo2 (int32x4_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint8x16_t foo3 (uint8x16_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint16x8_t foo4 (uint16x8_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint32x4_t foo5 (uint32x4_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-float16x8_t foo6 (float16x8_t a) +-{ +- return vaddq (a, (float16_t)23.6); +-} +-float32x4_t foo7 (float32x4_t a) +-{ +- return vaddq (a, (float32_t)23.46); +-} +-float16x8_t foo8 (float16x8_t a) +-{ +- return vaddq (a, 23.6); +-} +-float32x4_t foo9 (float32x4_t a) +-{ +- return vaddq (a, 23.46); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c +new file mode 100644 +index 00000000000..ee52be54f7b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c +@@ -0,0 +1,61 @@ ++/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ ++/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */ ++/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */ ++#include "arm_mve.h" ++ ++float f1; ++double f2; ++float16_t f3; ++float32_t f4; ++__fp16 f5; ++#ifndef __cplusplus ++_Float16 f6; ++#endif ++ ++float16x8_t floatvec; ++ ++/* Test a few different supported ways of passing a scalar int value. ++The intrinsic vmulq was chosen arbitrarily, but it is representative of ++all intrinsics that take a non-const scalar value. */ ++void ++test_scalars (void) ++{ ++ /* Test a few different supported ways of passing a float value. */ ++ floatvec = vmulq(floatvec, 0.5); ++ floatvec = vmulq(floatvec, 0.5f); ++ floatvec = vmulq(floatvec, (__fp16) 0.5); ++ floatvec = vmulq(floatvec, f1); ++ floatvec = vmulq(floatvec, f2); ++ floatvec = vmulq(floatvec, f3); ++ floatvec = vmulq(floatvec, f4); ++ floatvec = vmulq(floatvec, f5); ++#ifndef __cplusplus ++ floatvec = vmulq(floatvec, f6); ++ floatvec = vmulq(floatvec, 0.15f16); ++ floatvec = vmulq(floatvec, (_Float16) 0.15); ++#endif ++} ++ ++/* Next, test a number of valid pointer overloads. */ ++void ++foo11 (__fp16 * addr, float16x8_t value) ++{ ++ vst1q (addr, value); ++} ++ ++#ifndef __cplusplus ++void ++foo12 (_Float16 * addr, float16x8_t value) ++{ ++ vst1q (addr, value); ++} ++#endif ++ ++void ++foo13 (float * addr, float32x4_t value) ++{ ++ vst1q (addr, value); ++} ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c +new file mode 100644 +index 00000000000..ab51cc8b323 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c +@@ -0,0 +1,100 @@ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */ ++/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */ ++#include "arm_mve.h" ++ ++int i1; ++short i2; ++long i3; ++long long i4; ++int8_t i5; ++int16_t i6; ++int32_t i7; ++int64_t i8; ++ ++int16x8_t intvec; ++ ++/* Test a few different supported ways of passing a scalar int value. ++The intrinsic vmulq was chosen arbitrarily, but it is representative of ++all intrinsics that take a non-const scalar value. */ ++void ++test_scalars (void) ++{ ++ intvec = vmulq(intvec, 2); ++ intvec = vmulq(intvec, (int32_t) 2); ++ intvec = vmulq(intvec, (short) 2); ++ intvec = vmulq(intvec, i1); ++ intvec = vmulq(intvec, i2); ++ intvec = vmulq(intvec, i3); ++ intvec = vmulq(intvec, i4); ++ intvec = vmulq(intvec, i5); ++ intvec = vmulq(intvec, i6); ++ intvec = vmulq(intvec, i7); ++ intvec = vmulq(intvec, i8); ++} ++ ++/* Next, test a number of valid pointer overloads. */ ++void ++foo1 (signed char * addr, int8x16_t value) ++{ ++ vst1q (addr, value); ++} ++ ++void ++foo2 (short * addr, int16x8_t value) ++{ ++ vst1q (addr, value); ++} ++ ++/* Glibc defines int32_t as 'int' while newlib defines it as 'long int'. ++ ++ Although these correspond to the same size, g++ complains when using the ++ 'wrong' version: ++ invalid conversion from 'long int*' to 'int32_t*' {aka 'int*'} [-fpermissive] ++ ++ The trick below is to make this test pass whether using glibc-based or ++ newlib-based toolchains. */ ++ ++#if defined(__GLIBC__) ++#define word_type int ++#else ++#define word_type long int ++#endif ++void ++foo3 (word_type * addr, int32x4_t value) ++{ ++ vst1q (addr, value); ++} ++ ++void ++foo5 (long long * addr, uint64x2_t value) ++{ ++ vldrdq_gather_offset (addr, value); ++} ++ ++void ++foo6 (unsigned char * addr, uint8x16_t value) ++{ ++ vst1q (addr, value); ++} ++ ++void ++foo7 (unsigned short * addr, uint16x8_t value) ++{ ++ vst1q (addr, value); ++} ++ ++void ++foo8 (unsigned word_type * addr, uint32x4_t value) ++{ ++ vst1q (addr, value); ++} ++ ++void ++foo10 (unsigned long long * addr, uint64x2_t value) ++{ ++ vldrdq_gather_offset (addr, value); ++} ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c +deleted file mode 100644 +index 719b95d9020..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include +-mve_pred16_t p; +- +-int32x4_t fn1 (int32x4_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_s32(), vecIdx, 1, p); +-} +- +-int16x8_t fn2 (int16x8_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_s16(), vecIdx, 1, p); +-} +- +-int8x16_t fn3 (int8x16_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_s8(), vecIdx, 1, p); +-} +- +-uint32x4_t fn4 (uint32x4_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_u32(), vecIdx, 1, p); +-} +- +-uint16x8_t fn5 (uint16x8_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_u16(), vecIdx, 1, p); +-} +- +-uint8x16_t fn6 (uint8x16_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_u8(), vecIdx, 1, p); +-} +- +-float32x4_t fn7 (float32x4_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_f32(), vecIdx, (float32_t) 1.23, p); +-} +- +-float16x8_t fn8 (float16x8_t vecIdx) +-{ +- return vaddq_m(vuninitializedq_f16(), vecIdx, (float16_t) 1.40, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c +deleted file mode 100644 +index baa7fabe061..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include +-int8x16_t foo (int8x16_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-int16x8_t foo1 (int16x8_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-int32x4_t foo2 (int32x4_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint8x16_t foo3 (uint8x16_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint16x8_t foo4 (uint16x8_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +-uint32x4_t foo5 (uint32x4_t a, int16_t b) +-{ +- return vaddq (a, (b<<3)); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c +deleted file mode 100644 +index 15587802925..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vddupq_m (inactive, a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c +deleted file mode 100644 +index 8a9ed6327d3..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vddupq_m (inactive, a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c +deleted file mode 100644 +index fe4aceeea97..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vddupq_m (inactive, a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c +deleted file mode 100644 +index 05a68cbe559..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (int32_t a) +-{ +- return vddupq_u16 (a, 4); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c +deleted file mode 100644 +index f702c4cdb0a..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (int32_t a) +-{ +- return vddupq_u32 (a, 1); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c +deleted file mode 100644 +index f272056c423..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (int32_t a) +-{ +- return vddupq_u8 (a, 1); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c +deleted file mode 100644 +index 31e37827e60..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint16x8_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vddupq_x_u16 (a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c +deleted file mode 100644 +index 9989d0b0f00..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vddupq_x_u32 (a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c +deleted file mode 100644 +index 19f1501fe4e..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint8x16_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vddupq_x_u8 (a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c +deleted file mode 100644 +index 07ea2d7d14c..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return vdwdupq_x_u16 (a, b, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c +deleted file mode 100644 +index 9889b0b2b66..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return vdwdupq_x_u32 (a, b, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c +deleted file mode 100644 +index 13ad8d69e18..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return vdwdupq_x_u8 (a, b, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c +deleted file mode 100644 +index cbe998e2faa..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vidupq_m (inactive, a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c +deleted file mode 100644 +index c9aa5c661de..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vidupq_m (inactive, a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c +deleted file mode 100644 +index 7b075744d9a..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p) +-{ +- return vidupq_m (inactive, a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c +deleted file mode 100644 +index a461a1e64b1..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (int32_t a) +-{ +- return vidupq_u16 (a, 4); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c +deleted file mode 100644 +index c5b01a7ac90..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (int32_t a) +-{ +- return vidupq_u32 (a, 1); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c +deleted file mode 100644 +index f963d51ac0f..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (int32_t a) +-{ +- return vidupq_u8 (a, 1); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c +deleted file mode 100644 +index aecd4be5e71..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint16x8_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vidupq_x_u16 (a, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c +deleted file mode 100644 +index d3d33053f92..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vidupq_x_u32 (a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c +deleted file mode 100644 +index f71953aeef4..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint8x16_t +-foo1 (int32_t a, mve_pred16_t p) +-{ +- return vidupq_x_u8 (a, 1, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c +deleted file mode 100644 +index 312966773e6..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return viwdupq_x_u16 (a, b, 2, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c +deleted file mode 100644 +index a5d758126d4..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return viwdupq_x_u32 (a, b, 4, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c +deleted file mode 100644 +index aa4e7375d39..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint8x16_t +-foo1 (int32_t a, uint32_t b, mve_pred16_t p) +-{ +- return viwdupq_x_u8 (a, b, 8, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c +deleted file mode 100644 +index e5b635983bf..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int64x2_t +-foo1 (int64_t * base, uint64x2_t offset) +-{ +- return vldrdq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c +deleted file mode 100644 +index 8d96527c6df..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint64x2_t +-foo1 (uint64_t * base, uint64x2_t offset) +-{ +- return vldrdq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c +deleted file mode 100644 +index e66e4465b19..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int64x2_t +-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p) +-{ +- return vldrdq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c +deleted file mode 100644 +index 7ca9590c12c..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint64x2_t +-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p) +-{ +- return vldrdq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c +deleted file mode 100644 +index b8491680536..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int64x2_t +-foo1 (int64_t * base, uint64x2_t offset) +-{ +- return vldrdq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c +deleted file mode 100644 +index 851d4a1f435..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint64x2_t +-foo1 (uint64_t * base, uint64x2_t offset) +-{ +- return vldrdq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c +deleted file mode 100644 +index 586e38cfe43..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int64x2_t +-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p) +-{ +- return vldrdq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c +deleted file mode 100644 +index dd6f482422f..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint64x2_t +-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p) +-{ +- return vldrdq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c +deleted file mode 100644 +index 3c0ae4b4262..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c +deleted file mode 100644 +index bc7a51b38a5..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int16x8_t +-foo1 (int16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c +deleted file mode 100644 +index d6e83072995..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int32x4_t +-foo1 (int16_t * base, uint32x4_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c +deleted file mode 100644 +index 21b0b1cf52e..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint16x8_t +-foo1 (uint16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c +deleted file mode 100644 +index 3a9c47e9c47..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint16_t * base, uint32x4_t offset) +-{ +- return vldrhq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c +deleted file mode 100644 +index e31d0bc05bb..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c +deleted file mode 100644 +index 6a40159be42..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int16x8_t +-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c +deleted file mode 100644 +index 1d9a70db727..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int32x4_t +-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c +deleted file mode 100644 +index 8fedbef9aef..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c +deleted file mode 100644 +index db410437c02..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c +deleted file mode 100644 +index c12bd91a733..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c +deleted file mode 100644 +index df291626299..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int16x8_t +-foo1 (int16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c +deleted file mode 100644 +index 9bc6627accf..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int16_t * base, uint32x4_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c +deleted file mode 100644 +index c470871617d..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint16x8_t +-foo1 (uint16_t * base, uint16x8_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c +deleted file mode 100644 +index 2d4fe4c1d25..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint16_t * base, uint32x4_t offset) +-{ +- return vldrhq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c +deleted file mode 100644 +index 755540d93b6..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler "vldrht.f16" } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c +deleted file mode 100644 +index b9fc8d3242b..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int16x8_t +-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler "vldrht.u16" } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c +deleted file mode 100644 +index c65df114f15..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-int32x4_t +-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c +deleted file mode 100644 +index 8bb493bc6c0..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint16x8_t +-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c +deleted file mode 100644 +index cac933f0f36..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-uint32x4_t +-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrhq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c +deleted file mode 100644 +index 6d10e1ce9e8..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c +deleted file mode 100644 +index 0f29a6a8aa1..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c +deleted file mode 100644 +index 29e231757ec..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c +deleted file mode 100644 +index 77a949fc1a6..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c +deleted file mode 100644 +index 849783ab89f..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c +deleted file mode 100644 +index 3fe47cbeab5..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c +deleted file mode 100644 +index 0d166348de5..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c +deleted file mode 100644 +index 78e520b159e..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c +deleted file mode 100644 +index 6b8b72818d9..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32_t * base, uint32x4_t offset) +-{ +- return vldrwq_gather_shifted_offset (base, offset); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c +deleted file mode 100644 +index db79e57a2f5..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c +deleted file mode 100644 +index e060fee10ca..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int32x4_t +-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c +deleted file mode 100644 +index 72446470ae3..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +-/* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-uint32x4_t +-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p) +-{ +- return vldrwq_gather_shifted_offset_z (base, offset, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c +deleted file mode 100644 +index 62dfb450a6d..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c ++++ /dev/null +@@ -1,141 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-int +-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc); +- uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[4]); +- vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs1, vecIn1); +- vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foowf32( float32_t * pDataSrc, float32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- float32x4_t vecIn1 = vldrwq_f32 ((float32_t const *) pDataSrc); +- float32x4_t vecIn2 = vldrwq_f32 ((float32_t const *) &pDataSrc[4]); +- vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs1, vecIn1); +- vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- uint16x8_t vecIn1 = vldrhq_u16 ((uint16_t const *) pDataSrc); +- uint16x8_t vecIn2 = vldrhq_u16 ((uint16_t const *) &pDataSrc[8]); +- vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs2, vecIn2); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- uint32x4_t vecIn1 = vldrhq_u32 ((uint16_t const *) pDataSrc); +- uint32x4_t vecIn2 = vldrhq_u32 ((uint16_t const *) &pDataSrc[4]); +- vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohf16( float16_t * pDataSrc, float16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- float16x8_t vecIn1 = vldrhq_f16 ((float16_t const *) pDataSrc); +- float16x8_t vecIn2 = vldrhq_f16 ((float16_t const *) &pDataSrc[8]); +- vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs2, vecIn2); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest) +-{ +- const uint64x2_t vecOffs1 = { 0, 1}; +- const uint64x2_t vecOffs2 = { 2, 3}; +- uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc); +- uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[2]); +- +- vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1); +- vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2); +- +- pDataDest[2] = pDataSrc[2]; +- return 0; +-} +- +-int +-foows32( int32_t * pDataSrc, int32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc); +- int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[4]); +- vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs1, vecIn1); +- vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohs16( int16_t * pDataSrc, int16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- int16x8_t vecIn1 = vldrhq_s16 ((int16_t const *) pDataSrc); +- int16x8_t vecIn2 = vldrhq_s16 ((int16_t const *) &pDataSrc[8]); +- vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs2, vecIn2); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foohs32( int32_t * pDataSrc, int32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- int32x4_t vecIn1 = vldrhq_s32 ((int16_t const *) pDataSrc); +- int32x4_t vecIn2 = vldrhq_s32 ((int16_t const *) &pDataSrc[4]); +- vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1); +- vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foods64( int64_t * pDataSrc, int64_t * pDataDest) +-{ +- const uint64x2_t vecOffs1 = { 0, 1}; +- const uint64x2_t vecOffs2 = { 2, 3}; +- int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc); +- int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[2]); +- +- vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1); +- vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2); +- +- pDataDest[2] = pDataSrc[2]; +- return 0; +-} +- +-/* { dg-final { scan-assembler-times "vstr\[a-z\]" 20 } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c +deleted file mode 100644 +index a51d3a21167..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c ++++ /dev/null +@@ -1,142 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +- +-mve_pred16_t __p; +-int +-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p); +- uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[4], __p); +- vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs1, vecIn1, __p); +- vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foowf32( float32_t * pDataSrc, float32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- float32x4_t vecIn1 = vldrwq_z_f32 ((float32_t const *) pDataSrc, __p); +- float32x4_t vecIn2 = vldrwq_z_f32 ((float32_t const *) &pDataSrc[4], __p); +- vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs1, vecIn1, __p); +- vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- uint16x8_t vecIn1 = vldrhq_z_u16 ((uint16_t const *) pDataSrc, __p); +- uint16x8_t vecIn2 = vldrhq_z_u16 ((uint16_t const *) &pDataSrc[8], __p); +- vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- uint32x4_t vecIn1 = vldrhq_z_u32 ((uint16_t const *) pDataSrc, __p); +- uint32x4_t vecIn2 = vldrhq_z_u32 ((uint16_t const *) &pDataSrc[4], __p); +- vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohf16( float16_t * pDataSrc, float16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- float16x8_t vecIn1 = vldrhq_z_f16 ((float16_t const *) pDataSrc, __p); +- float16x8_t vecIn2 = vldrhq_z_f16 ((float16_t const *) &pDataSrc[8], __p); +- vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest) +-{ +- const uint64x2_t vecOffs1 = { 0, 1}; +- const uint64x2_t vecOffs2 = { 2, 3}; +- uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p); +- uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[2], __p); +- +- vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1, __p); +- vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2, __p); +- +- pDataDest[2] = pDataSrc[2]; +- return 0; +-} +- +-int +-foows32( int32_t * pDataSrc, int32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p); +- int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[4], __p); +- vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs1, vecIn1, __p); +- vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foohs16( int16_t * pDataSrc, int16_t * pDataDest) +-{ +- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5}; +- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14}; +- int16x8_t vecIn1 = vldrhq_z_s16 ((int16_t const *) pDataSrc, __p); +- int16x8_t vecIn2 = vldrhq_z_s16 ((int16_t const *) &pDataSrc[8], __p); +- vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[16] = pDataSrc[16]; +- return 0; +-} +- +-int +-foohs32( int32_t * pDataSrc, int32_t * pDataDest) +-{ +- const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; +- const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; +- int32x4_t vecIn1 = vldrhq_z_s32 ((int16_t const *) pDataSrc, __p); +- int32x4_t vecIn2 = vldrhq_z_s32 ((int16_t const *) &pDataSrc[4], __p); +- vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1, __p); +- vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2, __p); +- pDataDest[8] = pDataSrc[8]; +- return 0; +-} +- +-int +-foods64( int64_t * pDataSrc, int64_t * pDataDest) +-{ +- const uint64x2_t vecOffs1 = { 0, 1}; +- const uint64x2_t vecOffs2 = { 2, 3}; +- int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p); +- int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[2], __p); +- +- vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1, __p); +- vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2, __p); +- +- pDataDest[2] = pDataSrc[2]; +- return 0; +-} +- +-/* { dg-final { scan-assembler-times "vstr\[a-z\]t" 20 } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c +index 1f0a228e4b4..ea8c7a0ce4a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** sqrshr (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32_t +-sqrshr_reg (int32_t longval3, int32_t x) ++foo (int32_t value, int32_t shift) + { +- return sqrshr (longval3, x); ++ return sqrshr (value, shift); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "sqrshr\\tr\[0-9\]+, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c +index 2f1612cde77..affa12c526d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** sqrshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64_t +-sqrshrl_reg (int64_t longval3, int32_t x) ++foo (int64_t value, int32_t shift) + { +- return sqrshrl_sat48 (longval3, x); ++ return sqrshrl_sat48 (value, shift); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c +index 8cb8c74b268..e8c9c441163 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** sqshl (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-sqshl_imm (int32_t longval3) ++foo (int32_t value) + { +- return sqshl (longval3, 25); ++ return sqshl (value, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "sqshl\\tr\[0-9\]+, #25" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c +index 016ef2a336e..03dc91f3758 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** sqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-sqshll_imm(int64_t value) ++foo (int64_t value) + { +- return sqshll (value, 21); ++ return sqshll (value, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "sqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c +index 264f0bf09ce..734375d58c0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + int32_t +-srshr_imm (int32_t longval3) ++foo (int32_t value) + { +- return srshr (longval3, 25); ++ return srshr (value, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "srshr\\tr\[0-9\]+, #25" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c +index ab12d0da635..a91943c38a0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + int64_t +-srshrl_imm(int64_t value) ++foo (int64_t value) + { +- return srshrl (value, 21); ++ return srshrl (value, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "srshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c +index 0064aa19fbc..4b6fd041210 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** uqrshl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32_t +-uqrshl_reg (uint32_t longval3, int32_t x) ++foo (uint32_t value, int32_t shift) + { +- return uqrshl (longval3, x); ++ return uqrshl (value, shift); ++} ++ ++/* ++**foo1: ++** ... ++** uqrshl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32_t ++foo1 (int32_t shift) ++{ ++ return uqrshl (1, shift); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "uqrshl\\tr\[0-9\]+, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c +index 24cd2324413..eaf36911eb6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** uqrshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint64_t +-uqrshll_reg (uint64_t longval3, int32_t x) ++foo (uint64_t value, int32_t shift) + { +- return uqrshll_sat48 (longval3, x); ++ return uqrshll_sat48 (value, shift); ++} ++ ++/* ++**foo1: ++** ... ++** uqrshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint64_t ++foo1 (int32_t shift) ++{ ++ return uqrshll_sat48 (1, shift); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c +index 9e6ff649805..462531cad54 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + uint32_t +-uqshl_imm (uint32_t longval3) ++foo (uint32_t value) + { +- return uqshl (longval3, 21); ++ return uqshl (value, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "uqshl\\tr\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c +index 52560721d6f..6fa97a561e3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + uint64_t +-uqshll_imm(uint64_t value) ++foo (uint64_t value) + { +- return uqshll (value, 21); ++ return uqshll (value, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "uqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c +index ec5d84bb009..ff97bf5c473 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-uint64_t +-urshr_imm (uint32_t longval3) ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ ++uint32_t ++foo (uint32_t value) ++{ ++ return urshr (value, 1); ++} ++ ++/* ++**foo1: ++** ... ++** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ ++uint32_t ++foo1 () + { +- return urshr (longval3, 21); ++ return urshr (1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "urshr\\tr\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c +index ea29412ab7a..ff6a69d300f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ + uint64_t +-urshrl_imm(uint64_t value) ++foo (uint64_t value) + { +- return urshrl (value, 21); ++ return urshrl (value, 1); ++} ++ ++/* ++**foo1: ++** ... ++** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ++** ... ++*/ ++uint64_t ++foo1 () ++{ ++ return urshrl (1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "urshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c +index 78ac801fa3c..3b95fb140f7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vabavq_p_s16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vabavq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.s16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int16x8_t b, int16x8_t c, mve_pred16_t p) ++{ ++ return vabavq_p (1, b, c, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c +index af4e30b6127..b9f84e581bd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vabavq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vabavq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.s32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int32x4_t b, int32x4_t c, mve_pred16_t p) ++{ ++ return vabavq_p (1, b, c, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c +index a76b6bd4bda..fa76cd20e1b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vabavq_p_s8 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vabavq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.s8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int8x16_t b, int8x16_t c, mve_pred16_t p) ++{ ++ return vabavq_p (1, b, c, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c +index 9627a00b812..93deb664eda 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) + { + return vabavq_p_u16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) + { + return vabavq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint16x8_t b, uint16x8_t c, mve_pred16_t p) ++{ ++ return vabavq_p (1, b, c, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c +index 298c2c38101..c11fc704b34 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) + { + return vabavq_p_u32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) + { + return vabavq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p) ++{ ++ return vabavq_p (1, b, c, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c +index 775072225f8..04b9a6e2e35 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) + { + return vabavq_p_u8 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) + { + return vabavq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vabavt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint8x16_t b, uint8x16_t c, mve_pred16_t p) ++{ ++ return vabavq_p (1, b, c, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c +index c2383f1865b..d1a1c967581 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int16x8_t b, int16x8_t c) + { + return vabavq_s16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.s16" } } */ + ++/* ++**foo1: ++** ... ++** vabav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int16x8_t b, int16x8_t c) + { + return vabavq (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.s16" } } */ ++/* ++**foo2: ++** ... ++** vabav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int16x8_t b, int16x8_t c) ++{ ++ return vabavq (1, b, c); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c +index 7170d013c3b..9ccfc73f79c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int32x4_t b, int32x4_t c) + { + return vabavq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.s32" } } */ + ++/* ++**foo1: ++** ... ++** vabav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int32x4_t b, int32x4_t c) + { + return vabavq (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.s32" } } */ ++/* ++**foo2: ++** ... ++** vabav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int32x4_t b, int32x4_t c) ++{ ++ return vabavq (1, b, c); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c +index d75ecdbdbdf..5184d7a068d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int8x16_t b, int8x16_t c) + { + return vabavq_s8 (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.s8" } } */ + ++/* ++**foo1: ++** ... ++** vabav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int8x16_t b, int8x16_t c) + { + return vabavq (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.s8" } } */ ++/* ++**foo2: ++** ... ++** vabav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int8x16_t b, int8x16_t c) ++{ ++ return vabavq (1, b, c); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c +index 40ab94d9083..c800d79d351 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint16x8_t b, uint16x8_t c) + { + return vabavq_u16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.u16" } } */ + ++/* ++**foo1: ++** ... ++** vabav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint16x8_t b, uint16x8_t c) + { + return vabavq (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.u16" } } */ ++/* ++**foo2: ++** ... ++** vabav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint16x8_t b, uint16x8_t c) ++{ ++ return vabavq (1, b, c); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c +index 4b9f5c32f3d..b1733bae333 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint32x4_t b, uint32x4_t c) + { + return vabavq_u32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.u32" } } */ + ++/* ++**foo1: ++** ... ++** vabav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint32x4_t b, uint32x4_t c) + { + return vabavq (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.u32" } } */ ++/* ++**foo2: ++** ... ++** vabav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint32x4_t b, uint32x4_t c) ++{ ++ return vabavq (1, b, c); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c +index 3638e9d7106..897cd32b1bb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint8x16_t b, uint8x16_t c) + { + return vabavq_u8 (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.u8" } } */ + ++/* ++**foo1: ++** ... ++** vabav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint8x16_t b, uint8x16_t c) + { + return vabavq (a, b, c); + } + +-/* { dg-final { scan-assembler "vabav.u8" } } */ ++/* ++**foo2: ++** ... ++** vabav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint8x16_t b, uint8x16_t c) ++{ ++ return vabavq (1, b, c); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c +index b55e826e4b6..338514621ea 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabd.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vabdq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vabd.f16" } } */ + ++/* ++**foo1: ++** ... ++** vabd.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vabdq (a, b); + } + +-/* { dg-final { scan-assembler "vabd.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c +index f1a95b14e03..9a600384822 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabd.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vabdq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vabd.f32" } } */ + ++/* ++**foo1: ++** ... ++** vabd.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vabdq (a, b); + } + +-/* { dg-final { scan-assembler "vabd.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c +index f92e671edec..3584f182e9a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vabdq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vabdq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c +index 5e30997c997..8b64f39a758 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vabdq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vabdq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c +index 35809895dea..aeb9879f91c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vabdq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vabdq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c +index 77d97e1db63..294c6f17467 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vabdq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vabdq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c +index a0004d9f290..c4c414691cb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vabdq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vabdq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c +index c4dc9a469da..4567b0f7da8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vabdq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vabdq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c +index 18a64d3a19d..fc58f5c9001 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vabdq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vabdq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c +index 494f39cb857..6c5e2fe479a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vabdq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vabdq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c +index 73773ac9ebc..ac300d287dc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vabdq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vabd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vabd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vabdq (a, b); + } + +-/* { dg-final { scan-assembler "vabd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c +index 3c552a2969e..6170a59c0b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vabdq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vabd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vabd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vabdq (a, b); + } + +-/* { dg-final { scan-assembler "vabd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c +index f7de6f707ac..9cf62f9742d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vabdq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vabd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vabd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vabdq (a, b); + } + +-/* { dg-final { scan-assembler "vabd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c +index 90d1c873cca..c283d7482cc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vabdq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vabd.u16" } } */ + ++/* ++**foo1: ++** ... ++** vabd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vabdq (a, b); + } + +-/* { dg-final { scan-assembler "vabd.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c +index 405dca51466..be9abda0cab 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vabdq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vabd.u32" } } */ + ++/* ++**foo1: ++** ... ++** vabd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vabdq (a, b); + } + +-/* { dg-final { scan-assembler "vabd.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c +index 2b693c16520..227af07d0e5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vabdq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vabd.u8" } } */ + ++/* ++**foo1: ++** ... ++** vabd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vabdq (a, b); + } + +-/* { dg-final { scan-assembler "vabd.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c +index 9d771a3325f..ae54ef21c3e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vabdq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vabdq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c +index 498851348d5..d8781db3fb8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vabdq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vabdq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c +index 1fa77cc5cae..9d141616047 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vabdq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vabdq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c +index 24a62702482..7eb6fad3499 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vabdq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vabdq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c +index f96c2dfd147..8431703f4ef 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vabdq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vabdq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c +index 820b8416330..7d2f3dcea48 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vabdq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vabdq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c +index 2d81930348a..b94358fb4ae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vabdq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vabdq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c +index 7f956850b52..a88e1e5346f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vabdq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabdt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabdt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vabdq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c +index 08e141baedc..d4bc9110f38 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabs.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vabsq_f16 (a); + } + +-/* { dg-final { scan-assembler "vabs.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vabs.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vabsq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c +index 3614a44fbdc..9f2955829f8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabs.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vabsq_f32 (a); + } + +-/* { dg-final { scan-assembler "vabs.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vabs.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vabsq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c +index 30c14a151af..33d113241e9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vabsq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vabsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c +index 652056aa98c..a588f5fc94c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vabsq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vabsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c +index 2dcf488bd0d..360087db4e3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vabsq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vabsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c +index 183909fef93..590d0204385 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vabsq_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vabsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c +index cd17974838e..518c19fdf79 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vabsq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vabsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c +index 243afebc38c..6f40447eb1d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabs.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vabsq_s16 (a); + } + +-/* { dg-final { scan-assembler "vabs.s16" } } */ + ++/* ++**foo1: ++** ... ++** vabs.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vabsq (a); + } + +-/* { dg-final { scan-assembler "vabs.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c +index d9843503a48..3da8b740fc8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabs.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vabsq_s32 (a); + } + +-/* { dg-final { scan-assembler "vabs.s32" } } */ + ++/* ++**foo1: ++** ... ++** vabs.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vabsq (a); + } + +-/* { dg-final { scan-assembler "vabs.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c +index 93bf1520dd3..5fa4ce42f5d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vabs.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vabsq_s8 (a); + } + +-/* { dg-final { scan-assembler "vabs.s8" } } */ + ++/* ++**foo1: ++** ... ++** vabs.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vabsq (a); + } + +-/* { dg-final { scan-assembler "vabs.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c +index d1fc7002ccb..fda43efcf96 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vabsq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vabsq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c +index 0beccac030d..281e07468ca 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vabsq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vabsq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c +index fd67fd5ccac..93d4ff5a473 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vabsq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vabsq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c +index 22d561d1e46..1ddc8b81cf6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vabsq_x_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vabsq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c +index 6908a6ca20c..0dfcf3e62fb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vabsq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vabst.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vabsq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c +index 1bfc101d5e8..a6a059a19e9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c +@@ -1,23 +1,57 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vadciq_m_s32 (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadcit.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vadciq_m (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadcit.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c +index f72fe34c33b..942111339f0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c +@@ -1,23 +1,57 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vadciq_m_u32 (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadcit.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vadciq_m (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadcit.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c +index ff13841c581..3b68bb6ac33 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, unsigned * carry_out) ++foo (int32x4_t a, int32x4_t b, unsigned *carry_out) + { + return vadciq_s32 (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vadci.i32" } } */ + ++/* ++**foo1: ++** ... ++** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out) ++foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out) + { + return vadciq (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vadci.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c +index e3560362225..82228491043 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out) ++foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out) + { + return vadciq_u32 (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vadci.i32" } } */ + ++/* ++**foo1: ++** ... ++** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out) ++foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out) + { + return vadciq (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vadci.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c +index 668c4fdc82c..da29bb765dd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c +@@ -1,23 +1,77 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) ++foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) + { + return vadcq_m_s32 (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadct.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) ++foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) + { + return vadcq_m (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadct.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c +index 368c7c5c5f2..be490aaaae7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c +@@ -1,23 +1,77 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) ++foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) + { + return vadcq_m_u32 (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadct.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) ++foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) + { + return vadcq_m (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vadct.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c +index 9c8777c45ee..d72190d53b5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c +@@ -1,21 +1,69 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, unsigned * carry) ++foo (int32x4_t a, int32x4_t b, unsigned *carry) + { + return vadcq_s32 (a, b, carry); + } + +-/* { dg-final { scan-assembler "vadc.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, unsigned * carry) ++foo1 (int32x4_t a, int32x4_t b, unsigned *carry) + { + return vadcq (a, b, carry); + } + +-/* { dg-final { scan-assembler "vadc.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c +index 78f48da5107..dbc1ebf3c46 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c +@@ -1,21 +1,69 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, unsigned * carry) ++foo (uint32x4_t a, uint32x4_t b, unsigned *carry) + { + return vadcq_u32 (a, b, carry); + } + +-/* { dg-final { scan-assembler "vadc.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry) ++foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry) + { + return vadcq (a, b, carry); + } + +-/* { dg-final { scan-assembler "vadc.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c +index 0991ac1b355..174f3e3b958 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddlvat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, mve_pred16_t p) + { + return vaddlvaq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddlvat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddlvat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, mve_pred16_t p) + { + return vaddlvaq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddlvat.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c +index 5af786e8e76..41b93675b74 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddlvat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint64_t a, uint32x4_t b, mve_pred16_t p) + { + return vaddlvaq_p_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddlvat.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddlvat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint64_t a, uint32x4_t b, mve_pred16_t p) + { + return vaddlvaq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddlvat.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddlvat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint32x4_t b, mve_pred16_t p) ++{ ++ return vaddlvaq_p (1, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c +index 78f155f1586..d692df30d55 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddlva.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b) + { + return vaddlvaq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vaddlva.s32" } } */ + ++/* ++**foo1: ++** ... ++** vaddlva.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b) + { + return vaddlvaq (a, b); + } + +-/* { dg-final { scan-assembler "vaddlva.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c +index a7dfa2541ab..4daba29620c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddlva.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint64_t a, uint32x4_t b) + { + return vaddlvaq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vaddlva.u32" } } */ + ++/* ++**foo1: ++** ... ++** vaddlva.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint64_t a, uint32x4_t b) + { + return vaddlvaq (a, b); + } + +-/* { dg-final { scan-assembler "vaddlva.u32" } } */ ++/* ++**foo2: ++** ... ++** vaddlva.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint32x4_t b) ++{ ++ return vaddlvaq (1, b); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c +index 8aa18323b53..df71bf107b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddlvt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, mve_pred16_t p) + { + return vaddlvq_p_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vaddlvt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddlvt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vaddlvq_p (a, p); + } + +-/* { dg-final { scan-assembler "vaddlvt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c +index a9cee74e2ee..40d6f4c1082 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddlvt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vaddlvq_p_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vaddlvt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddlvt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vaddlvq_p (a, p); + } + +-/* { dg-final { scan-assembler "vaddlvt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c +index 4bd70aacc05..4c87fb6dd2a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddlv.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a) + { + return vaddlvq_s32 (a); + } + +-/* { dg-final { scan-assembler "vaddlv.s32" } } */ + ++/* ++**foo1: ++** ... ++** vaddlv.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a) + { +- return vaddlvq_s32 (a); ++ return vaddlvq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vaddlv.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c +index 2148bd9a32e..3a9037addbb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddlv.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint32x4_t a) + { +- return vaddlvq_u32 (a); ++ return vaddlvq_u32 (a); + } + +-/* { dg-final { scan-assembler "vaddlv.u32" } } */ + ++/* ++**foo1: ++** ... ++** vaddlv.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint32x4_t a) + { +- return vaddlvq (a); ++ return vaddlvq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vaddlv.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c +index 3d1100a9e81..b0e6d5d2c59 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vaddq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.f16" } } */ + ++/* ++**foo1: ++** ... ++** vadd.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c +index e15e0d13e4f..be459e68d3c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vaddq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.f32" } } */ + ++/* ++**foo1: ++** ... ++** vadd.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c +index 51d7020bd1f..1631969a87f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vaddq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c +index 7821bc241ff..bd00b2056a3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vaddq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c +deleted file mode 100644 +index 8348098f948..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vaddq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c +index 796bed47613..5622365dd96 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) + { + return vaddq_m_n_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) ++{ ++ return vaddq_m (inactive, a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c +deleted file mode 100644 +index c34cc98385f..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vaddq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c +index afa3c4c722e..e8bdb6a6a98 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) + { + return vaddq_m_n_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) ++{ ++ return vaddq_m (inactive, a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c +index 0ef433724ba..b1c41e2b3bf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vaddq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c +index 46ac88e940d..1ff3dff685a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vaddq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c +index 1867d5603d1..3c7ed0f8e3e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vaddq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c +index 1da993b5e31..a8e7b989ba9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vaddq_m_n_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) ++{ ++ return vaddq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c +index d7404c9f4ce..0cbc89d37d8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vaddq_m_n_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) ++{ ++ return vaddq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c +index 013e83938b2..db95f28d548 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vaddq_m_n_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) ++{ ++ return vaddq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c +index 244c88fcf89..4306e61b57b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vaddq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c +index 7a59d75af11..fad289c8a41 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vaddq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c +index 5b8c74ab017..0b39c3dce21 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vaddq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c +index f28e3d789ab..c7a846a2dba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vaddq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c +index aeb836ce87d..bbead6073ce 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vaddq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c +index c698df3a146..3097756d53e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vaddq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c +index 024fab5c0b2..dbb86b7083c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16_t b) + { + return vaddq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.f16" } } */ + ++/* ++**foo1: ++** ... ++** vadd.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.f16" } } */ ++/* ++**foo2: ++** ... ++** vadd.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t a) ++{ ++ return vaddq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c +index 06b1528460e..61cbe4d03cc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32_t b) + { + return vaddq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.f32" } } */ + ++/* ++**foo1: ++** ... ++** vadd.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.f32" } } */ ++/* ++**foo2: ++** ... ++** vadd.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t a) ++{ ++ return vaddq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c +index 63765f41deb..237838cb0e6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b) + { + return vaddq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i16" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c +index e462fbfab8e..c2cee5dc69b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vaddq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i32" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c +index ad7181fd8f5..d815eaaa16e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b) + { + return vaddq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i8" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c +index dac7a9fb9ba..35527a63ef4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b) + { + return vaddq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i16" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i16" } } */ ++/* ++**foo2: ++** ... ++** vadd.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a) ++{ ++ return vaddq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c +index 2f1feb89d32..66de687bef0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b) + { + return vaddq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i32" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i32" } } */ ++/* ++**foo2: ++** ... ++** vadd.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a) ++{ ++ return vaddq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c +index 325bdade765..9d4f8073810 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b) + { + return vaddq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i8" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i8" } } */ ++/* ++**foo2: ++** ... ++** vadd.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a) ++{ ++ return vaddq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c +index 31f6cb42e9f..370e4332e65 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vaddq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i16" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c +index 96aead168cc..8c3bd3316d6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vaddq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i32" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c +index 6676a2e269b..3d126df3c3c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vaddq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i8" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c +index 1b19876e09a..e8ed91457b3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vaddq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i16" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c +index 8f5acc69e79..172ed24016a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vaddq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i32" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c +index e5be2fa1b59..b60b877bdba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vadd.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vaddq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i8" } } */ + ++/* ++**foo1: ++** ... ++** vadd.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vaddq (a, b); + } + +-/* { dg-final { scan-assembler "vadd.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c +index bd2a198eb72..e7a3693f4a6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vaddq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c +index 5369f4d4876..f38c6b1f7af 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vaddq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c +deleted file mode 100644 +index 3bb01676947..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vaddq_x (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c +index d2eed8cf66f..e092b28afa8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vaddq_x_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vaddq_x (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c +deleted file mode 100644 +index 66dedc7d7e5..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vaddq_x (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c +index 40d56da12b1..c58a5e50608 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vaddq_x_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.f32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t a, mve_pred16_t p) ++{ ++ return vaddq_x (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c +index e974cdf914b..876afc7367b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vaddq_x_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c +index a6ac9ccd3af..c25ec006918 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vaddq_x_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c +index f5539ef9c67..b6389224fe6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vaddq_x_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c +index f167df122a0..006a872034a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vaddq_x_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vaddq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c +index 653c3eed7a0..0cc940b449c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vaddq_x_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vaddq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c +index 0ad65c8dde5..214a8decd83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vaddq_x_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vaddq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c +index 75b1491e17d..a79531abf14 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vaddq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c +index 1aadebda459..019ed62813c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vaddq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c +index d6b07cee79a..4f390d109dd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vaddq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c +index 5c9abc2492a..e528a9ef1bf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vaddq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c +index d55ec735460..fa622f0a520 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vaddq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c +index bcc058b3769..8ce1fe36015 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vaddq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c +index c4bfe34aa91..95224809f66 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b, mve_pred16_t p) + { + return vaddvaq_p_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b, mve_pred16_t p) + { + return vaddvaq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c +index cdc32807a24..80281819f06 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, mve_pred16_t p) + { + return vaddvaq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, mve_pred16_t p) + { + return vaddvaq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c +index d330411115a..53a92513511 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b, mve_pred16_t p) + { + return vaddvaq_p_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b, mve_pred16_t p) + { + return vaddvaq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c +index 74d9246cd63..da61820c552 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint16x8_t b, mve_pred16_t p) + { + return vaddvaq_p_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint16x8_t b, mve_pred16_t p) + { + return vaddvaq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint16x8_t b, mve_pred16_t p) ++{ ++ return vaddvaq_p (1, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c +index e4ec42b2544..0b7892c8b9a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint32x4_t b, mve_pred16_t p) + { + return vaddvaq_p_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) + { + return vaddvaq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint32x4_t b, mve_pred16_t p) ++{ ++ return vaddvaq_p (1, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c +index f9bed8379a4..51cba0385a9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint8x16_t b, mve_pred16_t p) + { + return vaddvaq_p_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint8x16_t b, mve_pred16_t p) + { + return vaddvaq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vaddvat.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvat.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint8x16_t b, mve_pred16_t p) ++{ ++ return vaddvaq_p (1, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c +index 5f6a8cf9d89..2a4dd6c33d9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddva.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b) + { + return vaddvaq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.s16" } } */ + ++/* ++**foo1: ++** ... ++** vaddva.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b) + { + return vaddvaq (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c +index 29e27f59328..9f1c8515142 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddva.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b) + { + return vaddvaq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.s32" } } */ + ++/* ++**foo1: ++** ... ++** vaddva.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b) + { + return vaddvaq (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c +index cac43464679..6f77cdb46f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddva.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b) + { + return vaddvaq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.s8" } } */ + ++/* ++**foo1: ++** ... ++** vaddva.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b) + { + return vaddvaq (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c +index c943fa5789f..a3e0e39502f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddva.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint16x8_t b) + { + return vaddvaq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.u16" } } */ + ++/* ++**foo1: ++** ... ++** vaddva.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint16x8_t b) + { + return vaddvaq (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.u16" } } */ ++/* ++**foo2: ++** ... ++** vaddva.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint16x8_t b) ++{ ++ return vaddvaq (1, b); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c +index 0950ff50d0f..e6b2f85cdae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddva.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint32x4_t b) + { + return vaddvaq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.u32" } } */ + ++/* ++**foo1: ++** ... ++** vaddva.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint32x4_t b) + { + return vaddvaq (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.u32" } } */ ++/* ++**foo2: ++** ... ++** vaddva.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint32x4_t b) ++{ ++ return vaddvaq (1, b); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c +index 2a58225fbe3..5bad0ca996e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddva.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint8x16_t b) + { + return vaddvaq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.u8" } } */ + ++/* ++**foo1: ++** ... ++** vaddva.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint8x16_t b) + { + return vaddvaq (a, b); + } + +-/* { dg-final { scan-assembler "vaddva.u8" } } */ ++/* ++**foo2: ++** ... ++** vaddva.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint8x16_t b) ++{ ++ return vaddvaq (1, b); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c +index a786b8974b7..f4e499b631e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a, mve_pred16_t p) + { + return vaddvq_p_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vaddvq_p (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c +index c688782180f..9417d86d6fe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a, mve_pred16_t p) + { + return vaddvq_p_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vaddvq_p (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c +index 8438448f86c..757bc5759ca 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a, mve_pred16_t p) + { + return vaddvq_p_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vaddvq_p (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c +index ec7a5fa5a7f..cc9673f7326 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vaddvq_p_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vaddvq_p (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c +index b70968880ce..9ead886d3e9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vaddvq_p_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vaddvq_p (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c +index 69381b78cc4..45ed62f8b58 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vaddvq_p_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vaddvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vaddvq_p (a, p); + } + +-/* { dg-final { scan-assembler "vaddvt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c +index b4fc11f4aa4..468cc810cc4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a) + { + return vaddvq_s16 (a); + } + +-/* { dg-final { scan-assembler "vaddv.s16" } } */ + ++/* ++**foo1: ++** ... ++** vaddv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a) + { +- return vaddvq_s16 (a); ++ return vaddvq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vaddv.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c +index 438b46ec246..791e27bdbb5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a) + { + return vaddvq_s32 (a); + } + +-/* { dg-final { scan-assembler "vaddv.s32" } } */ + ++/* ++**foo1: ++** ... ++** vaddv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a) + { +- return vaddvq_s32 (a); ++ return vaddvq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vaddv.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c +index b60b1f2da98..3a13efc93dd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a) + { + return vaddvq_s8 (a); + } + +-/* { dg-final { scan-assembler "vaddv.s8" } } */ + ++/* ++**foo1: ++** ... ++** vaddv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a) + { + return vaddvq (a); + } + +-/* { dg-final { scan-assembler "vaddv.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c +index de782127faf..6aabcdce2c6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint16x8_t a) + { +- return vaddvq_u16 (a); ++ return vaddvq_u16 (a); + } + +-/* { dg-final { scan-assembler "vaddv.u16" } } */ + ++/* ++**foo1: ++** ... ++** vaddv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint16x8_t a) + { +- return vaddvq (a); ++ return vaddvq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vaddv.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c +index c4672e42288..8b5ba816623 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32x4_t a) + { +- return vaddvq_u32 (a); ++ return vaddvq_u32 (a); + } + +-/* { dg-final { scan-assembler "vaddv.u32" } } */ + ++/* ++**foo1: ++** ... ++** vaddv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32x4_t a) + { +- return vaddvq (a); ++ return vaddvq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vaddv.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c +index e4e149cfb61..2576d9c66d0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vaddv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint8x16_t a) + { +- return vaddvq_u8 (a); ++ return vaddvq_u8 (a); + } + +-/* { dg-final { scan-assembler "vaddv.u8" } } */ + ++/* ++**foo1: ++** ... ++** vaddv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint8x16_t a) + { +- return vaddvq (a); ++ return vaddvq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vaddv.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c +index 2303b598a28..cb1820347bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vandq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c +index 905f2b410c0..1034bcbaa62 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vandq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c +index d061dbc390b..d6752a6fdc4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vandq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c +index 77b2813dfad..fb8410d0b71 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vandq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c +index 2840a33b433..5797ffa9a16 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vandq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c +index 2e8ec7e14de..d2ede670e40 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vandq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c +index 36226f6d9ac..76ed60c64a9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vandq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c +index 49f0502f607..b3f7833e546 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vandq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c +index 194c7800a05..7d761c86622 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vandq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c +index 9b27c44ee82..8fd17e4f258 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vandq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vandq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c +index 86aa64fec96..9f3e9b0c078 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vandq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c +index 907fe89ced8..ab0e9627fb9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vandq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c +index 783ad042c87..980ba6b5f7a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vandq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c +index ae483869f11..fdd18e92476 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vandq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c +index 532926d894a..01df1828788 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vandq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c +index 4018308f66d..a4f0cec4483 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vandq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ + ++/* ++**foo1: ++** ... ++** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vandq (a, b); + } + +-/* { dg-final { scan-assembler "vand" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c +index 6aa98910c7b..99c586d5604 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vandq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c +index fd74ee6eee7..eda9d618409 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vandq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c +index d8821d59be7..f0159ee7668 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vandq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c +index 980b01436b6..09277b2d56b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vandq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c +index 93dead71416..f1232168a7d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vandq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c +index aa99c69bd84..836385f44f4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vandq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c +index 1178837d78a..06b5010738b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vandq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c +index d46e2b235b9..37f4fc51f9a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vandq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vandt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vandq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c +index c15f1f91d07..38a1a4adafa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vbicq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c +index c8659d460a0..224b535992b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vbicq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c +index 39a12a9fba3..e197a2aa1e3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vbicq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c +index 091027c4b19..b441e205a64 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vbicq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c +index 3d0d09859c1..4e2be3e4516 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vbicq_m_n_s16 (a, 16, p); ++ return vbicq_m_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { +- return vbicq_m_n (a, 16, p); ++ return vbicq_m_n (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c +index 47a9459580b..d8beab58024 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vbicq_m_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vbicq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c +index 7c0c691fd46..34b62aa557f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vbicq_m_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vbicq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c +index e97b17aa27d..60681e3f045 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vbicq_m_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vbicq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c +index 31a9e986b8d..c30658cf34c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vbicq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c +index 9e7a2940b42..6a861cb80e5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vbicq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c +index b5e3253384c..c19caf53658 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vbicq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c +index 54370ab9548..443fcac6605 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vbicq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c +index cfcae7c74a9..31b1e22ef7a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vbicq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c +index cd9856f629e..6bddc5c2d30 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vbicq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vbicq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c +index 6258727d82f..8726b2c57a4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vbicq_n_s16 (a, 1); + } + ++ ++/* ++**foo1: ++** ... ++** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vbicq (a, 1); + } + +-/* { dg-final { scan-assembler-times "vbic.i16" 2 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c +index be641abf556..015af580ed0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vbicq_n_s32 (a, 1); + } + ++ ++/* ++**foo1: ++** ... ++** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vbicq (a, 1); + } + +-/* { dg-final { scan-assembler-times "vbic.i32" 2 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c +index 0b26ffda0dc..1ad03b9d17f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { + return vbicq_n_u16 (a, 1); + } + ++ ++/* ++**foo1: ++** ... ++** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { + return vbicq (a, 1); + } + +-/* { dg-final { scan-assembler-times "vbic.i16" 2 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c +index 47820bd184a..f3fe58fdf37 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { + return vbicq_n_u32 (a, 1); + } + ++ ++/* ++**foo1: ++** ... ++** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { + return vbicq (a, 1); + } + +-/* { dg-final { scan-assembler-times "vbic.i32" 2 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c +index 4ffacdd9733..6fd2a9e5c0c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vbicq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c +index 13fbff40746..37859e0dc6e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vbicq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c +index b9fba943a83..23db9afbcf1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vbicq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c +index 5d94a6396c4..9ed4e533e52 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vbicq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c +index 893dc3deefc..abaf2a9cf7b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vbicq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c +index bd5e9bc0197..4a47bb9d0e7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vbicq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ + ++/* ++**foo1: ++** ... ++** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vbicq (a, b); + } + +-/* { dg-final { scan-assembler "vbic" } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c +index 975d60c713e..aa4812568d7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vbicq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c +index e779224b5d5..db295df1cd5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vbicq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c +index be554c4b2fb..2b7a3594dd7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vbicq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c +index e49aabf11d6..bf3b755f9ee 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vbicq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c +index c36cd1e6dc5..30df0904539 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vbicq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c +index 3b611591deb..eaa50a84fd4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vbicq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c +index fce2fab3dd6..aea2592d9cf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vbicq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c +index 672b3fb1e39..4ffee473ea6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vbicq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbict" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vbicq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c +index 8f8d1bffd73..5985b7fed01 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c +index 336c8194cd7..1fff5a8bf95 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c +index f597d8ccb9d..a5221f8d864 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c +index 76f0463af1e..99106e81a30 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c +index 30c6519236c..6bd4c8f4455 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c +index 7052b8b5ff5..03ad4896029 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c +index e19e02fbbd8..e65077001ec 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c +index ce658432fd9..61ca255e431 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m_n_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c +index 9b8dea6e7e8..6dc4c657cbf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, int32_t b) + { + return vbrsrq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c +index cd335197c3b..810cd1b86ac 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, int32_t b) + { + return vbrsrq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c +index efb17dd5250..109ccd72f0a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b) + { + return vbrsrq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c +index fda78e6aa4b..78b2db49c87 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vbrsrq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c +index cd75a2b88fa..dfd485240ea 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b) + { + return vbrsrq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.8" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c +index ef7708e33f8..59e1fcc0fd9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b) + { + return vbrsrq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c +index b33c533aeda..2d7792dd1cb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b) + { + return vbrsrq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c +index 91156bd4325..5f4398ddbe1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b) + { + return vbrsrq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.8" } } */ + ++/* ++**foo1: ++** ... ++** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b) + { + return vbrsrq (a, b); + } + +-/* { dg-final { scan-assembler "vbrsr.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c +index 0710b59b1ab..d9d404ccf82 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c +index 67ab8cf80c9..8b176fe701c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c +index ac0c13c0b4d..77f4f1852a8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c +index 98c87f17588..fc4a1c9c7e0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c +index 8159f5da999..10322ac328a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c +index dbad2940616..72d8a9e23b0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c +index 04c812a2747..535af3600c7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c +index b3836936750..5f8f8c928fd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vbrsrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vbrsrt.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c +index b50a5d54bb2..fb83a1cd8fc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vcaddq_rot270_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c +index 0a12ff6fdcf..f8341a74e4a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vcaddq_rot270_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c +index e78bbd5446c..b4e2ffda280 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c +index 8b53c665463..e7adc1be243 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c +index 61948bb3552..fdde2f56b20 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c +index 0bbe24b3b4a..1cb6afb4e4d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c +index e9cab3df37f..39f063970f7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcaddq_rot270_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c +index 25c71257920..fd285288487 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c +index ee437eeb41f..053a61197d6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c +index 419ba7e98ee..869983a0a0b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcaddq_rot270_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c +index 832be006af8..67b0d0a4d0f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vcaddq_rot270_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c +index dbebe22183c..ab28458130e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vcaddq_rot270_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c +index 5f7852f69d4..842d6adf96d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vcaddq_rot270_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c +index 80b6c0ff3a9..97773d8daa9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vcaddq_rot270_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c +index 260c5b81e22..17d5c147295 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vcaddq_rot270_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c +index ae9c4f436ad..faf01a18824 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vcaddq_rot270_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c +index 4b99c638830..f35aaf01a59 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c +index 2532ef7d535..6446d9edc42 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c +index 676efa8cfd7..b92fd2ee8aa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c +index 9aa05d5bfdf..b8acc67feb9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c +index 4532296494c..78ec7862574 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcaddq_rot270_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c +index 51db9379e9b..ea781622424 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c +index a2e51c13268..a43d806ac3d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c +index 6ae7f693664..eb9cf0cffb6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcaddq_rot270_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c +index e1b21e6c5c3..1e78bd144b2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vcaddq_rot90_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c +index 118489e923f..9611f8938dc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vcaddq_rot90_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c +index e47e242f061..58608b4961e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c +index 833aa9c2367..125dbe5405c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c +index 46babedb949..38e0e47b500 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c +index 15774e5a142..455d8388f0f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c +index 6f2bb4da3e3..7217dadaac0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcaddq_rot90_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c +index b9113fe4f39..d3edbaa478c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c +index b7fe5106414..eb1bf2a4274 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c +index e6c4e9f66fb..3343399b2c3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcaddq_rot90_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c +index 8279da9ed45..134fba6280f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vcaddq_rot90_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c +index 6d59da7757d..b8e81679e9e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vcaddq_rot90_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c +index b4f5a22c03e..2a37b8e7b83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vcaddq_rot90_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c +index e203bd017cd..51e1871b690 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vcaddq_rot90_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c +index 0cba5d5bda8..5905062064a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vcaddq_rot90_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c +index f4f0476427a..37374637eb3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcadd.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vcaddq_rot90_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcadd.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcadd.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c +index 476648ad459..4223c4d0f33 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c +index ae9a196af7f..9e67c56b5e8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c +index 16b5949a2a2..553fc2801fb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c +index d30150e0f1c..1cd7338d162 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c +index fa79ce24eaf..13373d46154 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcaddq_rot90_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c +index e18a39ed125..3f8957783e3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c +index b9b95fe360e..34cb0363574 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c +index b8b8978c1e6..d383404052d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcaddq_rot90_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcaddt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcaddt.i8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c +index d0eb7008537..1996ac8b03e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vclsq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclst.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vclsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c +index b6d7088a8e7..f51841d024e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vclsq_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclst.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vclsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c +index 28d4d966802..2975c4cda56 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vclsq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclst.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vclsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c +index e57fbb97080..ed1b5c75b40 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcls.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vclsq_s16 (a); + } + +-/* { dg-final { scan-assembler "vcls.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcls.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vclsq (a); + } + +-/* { dg-final { scan-assembler "vcls.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c +index 7fa3038d361..9e5369e04c6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcls.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vclsq_s32 (a); + } + +-/* { dg-final { scan-assembler "vcls.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcls.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vclsq (a); + } + +-/* { dg-final { scan-assembler "vcls.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c +index b0985484d1d..c4a9468f8e1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcls.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vclsq_s8 (a); + } + +-/* { dg-final { scan-assembler "vcls.s8" } } */ + ++/* ++**foo1: ++** ... ++** vcls.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vclsq (a); + } + +-/* { dg-final { scan-assembler "vcls.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c +index ab09c9944ae..ea11eceb730 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vclsq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclst.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vclsq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c +index 09a8dab2f51..1737c561a0b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vclsq_x_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclst.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vclsq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c +index af40f7fa510..a7cdb612ee1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vclsq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclst.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vclsq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c +index 9670f8f56f3..620314e4ff2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vclzq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vclzq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c +index 18427354570..dfda1e67287 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vclzq_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vclzq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c +index 2697d039d70..1300fe6f8c4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vclzq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vclzq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c +index 8405b16314c..922819d388e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vclzq_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vclzq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c +index 350e6e7e661..6e75a0463cf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vclzq_m_u32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vclzq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c +index d455526f975..3c450e8eca0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vclzq_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vclzq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c +index f71a0a4eded..17be53f395b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vclz.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vclzq_s16 (a); + } + +-/* { dg-final { scan-assembler "vclz.i16" } } */ + ++/* ++**foo1: ++** ... ++** vclz.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vclzq (a); + } + +-/* { dg-final { scan-assembler "vclz.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c +index 46a002bc1c5..5e440febb29 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vclz.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vclzq_s32 (a); + } + +-/* { dg-final { scan-assembler "vclz.i32" } } */ + ++/* ++**foo1: ++** ... ++** vclz.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vclzq (a); + } + +-/* { dg-final { scan-assembler "vclz.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c +index 3cab6f32310..9eaa9a4269a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vclz.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vclzq_s8 (a); + } + +-/* { dg-final { scan-assembler "vclz.i8" } } */ + ++/* ++**foo1: ++** ... ++** vclz.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vclzq (a); + } + +-/* { dg-final { scan-assembler "vclz.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c +index cada68b6d65..37179b22a5c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vclz.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vclzq_u16 (a); ++ return vclzq_u16 (a); + } + +-/* { dg-final { scan-assembler "vclz.i16" } } */ + ++/* ++**foo1: ++** ... ++** vclz.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vclzq (a); ++ return vclzq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vclz.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c +index 0291b0cea4c..65ee44d41d5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vclz.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vclzq_u32 (a); ++ return vclzq_u32 (a); + } + +-/* { dg-final { scan-assembler "vclz.i32" } } */ + ++/* ++**foo1: ++** ... ++** vclz.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { +- return vclzq (a); ++ return vclzq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vclz.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c +index 5eb7bab5e0d..bed4ab1878a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vclz.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vclzq_u8 (a); ++ return vclzq_u8 (a); + } + +-/* { dg-final { scan-assembler "vclz.i8" } } */ + ++/* ++**foo1: ++** ... ++** vclz.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vclzq (a); ++ return vclzq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vclz.i8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c +index daddd1b4421..ea78bf20066 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vclzq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vclzq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c +index d4f443f7f56..cc85d4d27e2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vclzq_x_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vclzq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c +index b33d2c51c3f..0f809167a4f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vclzq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vclzq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c +index 6d9bc79261b..a9b662d40f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vclzq_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vclzq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c +index c3b053b9f1f..5446938c3fd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vclzq_x_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vclzq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c +index 678b2eb898d..548a74e8367 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vclzq_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vclzt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vclzt.i8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vclzq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c +index fa7d0c05e8c..bb8a99790a0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmla.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, float16x8_t c) + { + return vcmlaq_f16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmla.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, float16x8_t c) + { + return vcmlaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c +index 166bf421f14..71ec4b8479c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmla.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, float32x4_t c) + { + return vcmlaq_f32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmla.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, float32x4_t c) + { + return vcmlaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c +index 0929f5a0a89..3db345d0791 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) + { + return vcmlaq_m_f16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) + { + return vcmlaq_m (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c +index 1f4ba453cbc..dcbd2dccce5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) + { + return vcmlaq_m_f32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) + { + return vcmlaq_m (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c +index fc6ba30b36a..f76ae2383a2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmla.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, float16x8_t c) + { + return vcmlaq_rot180_f16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmla.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, float16x8_t c) + { + return vcmlaq_rot180 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c +index dbe3f26b3b9..c97d0d0d852 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmla.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, float32x4_t c) + { + return vcmlaq_rot180_f32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmla.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, float32x4_t c) + { + return vcmlaq_rot180 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c +index 84a3bd81ad9..132cdf9954f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) + { + return vcmlaq_rot180_m_f16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) + { + return vcmlaq_rot180_m (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c +index 61f5716f0b7..99e96ebe3a9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) + { + return vcmlaq_rot180_m_f32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) + { + return vcmlaq_rot180_m (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c +index 1b0bef91f37..fae85105feb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmla.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, float16x8_t c) + { + return vcmlaq_rot270_f16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmla.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, float16x8_t c) + { + return vcmlaq_rot270 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c +index 83e15025e44..54a9b662772 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmla.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, float32x4_t c) + { + return vcmlaq_rot270_f32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmla.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, float32x4_t c) + { + return vcmlaq_rot270 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c +index 6e033b1d7ab..e34f83165c3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) + { + return vcmlaq_rot270_m_f16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) + { + return vcmlaq_rot270_m (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c +index 4928341076d..cdba91b8e8c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) + { + return vcmlaq_rot270_m_f32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) + { + return vcmlaq_rot270_m (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c +index 16744a4582c..f767b2b6e6b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmla.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, float16x8_t c) + { + return vcmlaq_rot90_f16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmla.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, float16x8_t c) + { + return vcmlaq_rot90 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c +index f1f19a87ba7..6c9b24f271d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmla.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, float32x4_t c) + { + return vcmlaq_rot90_f32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmla.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, float32x4_t c) + { + return vcmlaq_rot90 (a, b, c); + } + +-/* { dg-final { scan-assembler "vcmla.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c +index 7133ddc7ad5..9141c9e6f90 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) + { + return vcmlaq_rot90_m_f16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) + { + return vcmlaq_rot90_m (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c +index 6022e3be538..f317d411806 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) + { + return vcmlaq_rot90_m_f32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmlat.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) + { + return vcmlaq_rot90_m (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmlat.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c +index a1640133012..373acbd31b9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vcmpcsq_m_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vcmpcsq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vcmpcsq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c +index d269ec7e3ab..25263654930 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vcmpcsq_m_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vcmpcsq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vcmpcsq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c +index 52c16b3e70f..60120e88ef9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vcmpcsq_m_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vcmpcsq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vcmpcsq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c +index e68afa316a9..fcdc41fdc81 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcmpcsq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcmpcsq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c +index 05d1b21b279..b294c8593d1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcmpcsq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcmpcsq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c +index 4c8a9d0aa2c..00c118a68c6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcmpcsq_m_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcmpcsq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c +index 4124036003e..9f8111438a1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16_t b) + { + return vcmpcsq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16_t b) + { + return vcmpcsq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint16x8_t a) ++{ ++ return vcmpcsq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c +index 463c1ee12b4..799d3bcdab1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32_t b) + { + return vcmpcsq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32_t b) + { + return vcmpcsq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint32x4_t a) ++{ ++ return vcmpcsq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c +index 92bc44a4bb6..16c3617c104 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8_t b) + { + return vcmpcsq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vcmpcsq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u8" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint8x16_t a) ++{ ++ return vcmpcsq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c +index 26c7d750cef..5ae4d0ceaef 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u16 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16x8_t b) + { + return vcmpcsq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u16 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vcmpcsq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c +index c91b0e1c2e3..4695e7e3405 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u32 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32x4_t b) + { + return vcmpcsq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u32 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vcmpcsq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c +index 51ddab91500..3075050a943 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u8 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vcmpcsq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u8 cs, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vcmpcsq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c +index 556351f4984..82b24a83f8b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b) + { + return vcmpeqq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c +index 65b2f240520..1d7bda0a986 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b) + { + return vcmpeqq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c +index 91b0ffa0afd..0a0406b3b74 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpeqq_m_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c +index d66e9c8be34..ba8a946591c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpeqq_m_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c +deleted file mode 100644 +index 909ca936492..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpeqq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c +index 46b3f4499d3..f095b4aff1e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpeqq_m_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vcmpeqq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c +deleted file mode 100644 +index 8f993af20af..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpeqq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c +index 7d672c129db..dd244db5e46 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpeqq_m_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a, mve_pred16_t p) ++{ ++ return vcmpeqq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c +index 912d4ad893d..bbf5326d2b3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpeqq_m_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c +index 947c331622d..b66949b7633 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpeqq_m_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c +index e215d655ea2..5730eebb47b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpeqq_m_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c +index ea4716c450e..6009e951beb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vcmpeqq_m_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vcmpeqq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c +index 489c6ec0cb3..2bce70de33e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vcmpeqq_m_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vcmpeqq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c +index e8dfce432d1..6c6fa8a7720 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vcmpeqq_m_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vcmpeqq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c +index 7e4c141e5d2..4b5feb26a62 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpeqq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c +index 904cfb6fe37..60db456c60d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpeqq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c +index a7e12164e32..45cdc28fb2b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpeqq_m_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c +index 283e1fd036e..41c3653b892 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcmpeqq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c +index ad1739bd609..2e7bf175e63 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcmpeqq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c +index 595142e9cda..e9d333f6661 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcmpeqq_m_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcmpeqq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c +deleted file mode 100644 +index 223cffc17e5..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpeqq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c +index f97209d2322..2f84d751c53 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b) + { + return vcmpeqq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a) ++{ ++ return vcmpeqq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c +deleted file mode 100644 +index 81669bd7c60..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpeqq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c +index c80843288b2..6cfe7338fce 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b) + { + return vcmpeqq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a) ++{ ++ return vcmpeqq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c +index 69f1f531af4..2f146d937ec 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b) + { + return vcmpeqq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c +index 06032dbcc20..f77743c00d3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b) + { + return vcmpeqq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c +index 3ebd88be85b..690ed1b811d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b) + { + return vcmpeqq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c +index 2f6c53a525e..362e830c908 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16_t b) + { + return vcmpeqq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint16x8_t a) ++{ ++ return vcmpeqq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c +index 22fb5be97c5..583beb97849 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32_t b) + { + return vcmpeqq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint32x4_t a) ++{ ++ return vcmpeqq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c +index 79eaeed6950..db7f1877d73 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8_t b) + { + return vcmpeqq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint8x16_t a) ++{ ++ return vcmpeqq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c +index 7951ead8a31..24f34a24ee3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b) + { + return vcmpeqq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c +index 659ccb4ac14..ae5d870d2b4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b) + { + return vcmpeqq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c +index 9282ec2a97a..81538a9957a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b) + { + return vcmpeqq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c +index 318b7aa9306..39778cf1b6c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16x8_t b) + { + return vcmpeqq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c +index 88e015f1fa3..8afd39e89b5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32x4_t b) + { + return vcmpeqq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c +index 990a96f7b3f..84610a10445 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vcmpeqq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vcmpeqq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c +index eea63a2fe50..f11dc28376d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b) + { + return vcmpgeq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c +index 64243fe3e8c..8eb38db2021 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b) + { + return vcmpgeq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c +index 3588b0a536f..c3a8df2ec46 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpgeq_m_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c +index 8ed1d22e919..8069e426b73 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpgeq_m_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c +deleted file mode 100644 +index 4a4e4b34fde..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpgeq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c +index d106af8f53b..3a9be99bc0a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpgeq_m_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vcmpgeq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c +deleted file mode 100644 +index c406a63aae2..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpgeq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c +index 1feef8adb7f..a785cfb52f8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpgeq_m_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a, mve_pred16_t p) ++{ ++ return vcmpgeq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c +index c0ad38f6c6f..0a2544e7ac4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpgeq_m_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c +index 8974ce4d11a..fa453774d06 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpgeq_m_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c +index 981aa1b516c..34d632b03e7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpgeq_m_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c +index 587432a6af1..1c5ce785a63 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpgeq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c +index e460a8dcafc..3ac4d59bf1f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpgeq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c +index cde28a314b9..3c3a584e075 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpgeq_m_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpgeq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c +deleted file mode 100644 +index a65ed4421a8..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpgeq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c +index 907fa5d50f6..978bd7d4b52 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b) + { + return vcmpgeq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a) ++{ ++ return vcmpgeq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c +deleted file mode 100644 +index 2e2fc0170eb..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpgeq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c +index e4d1406c049..66b6d8b0056 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b) + { + return vcmpgeq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a) ++{ ++ return vcmpgeq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c +index f4aad09e783..e0488dc0003 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b) + { + return vcmpgeq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c +index 2baa5204819..b448e8a15e3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b) + { + return vcmpgeq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c +index 1dcffcc3050..9f609b9f243 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s8 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b) + { + return vcmpgeq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s8 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c +index 817ffb2d8ac..c835d99b47a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s16 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b) + { + return vcmpgeq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s16 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c +index d608b7fc9cf..37d9524b4f8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s32 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b) + { + return vcmpgeq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s32 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c +index 506e6cede95..a752510621b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s8 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b) + { + return vcmpgeq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s8 ge, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vcmpgeq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c +index e2bfd7ed156..d8f151a19f3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b) + { + return vcmpgtq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c +index 1b4433f0e76..6f601889e85 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b) + { + return vcmpgtq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c +index def3f90a79d..f724387023e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpgtq_m_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c +index 41a11563f36..6eebe92b797 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpgtq_m_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c +deleted file mode 100644 +index 08c91a72e05..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpgtq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c +index 80c86f65825..be4da4b50da 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpgtq_m_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vcmpgtq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c +deleted file mode 100644 +index 0b74482211d..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpgtq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c +index 9b7aaadfe71..e8244345eb2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpgtq_m_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a, mve_pred16_t p) ++{ ++ return vcmpgtq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c +index c0719d0110c..12d5540ba39 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpgtq_m_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c +index 26df8cea9fc..dca726fde38 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpgtq_m_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c +index f20c50d69c1..07216ac242f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpgtq_m_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c +index da97abceb2e..bd0ac3d927a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpgtq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c +index ab7c218c7af..0c2f3acf2bd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpgtq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c +index 13520d1067b..3f2f28b839b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpgtq_m_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpgtq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c +deleted file mode 100644 +index 3b2faeaf64f..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpgtq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c +index 98e152cd999..9c5f1f2f5c8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b) + { + return vcmpgtq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a) ++{ ++ return vcmpgtq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c +deleted file mode 100644 +index 16862e0209c..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpgtq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c +index 5691e2f9d35..2723aa7f98f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b) + { + return vcmpgtq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a) ++{ ++ return vcmpgtq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c +index bc3bdbae2da..9c8611d924c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b) + { + return vcmpgtq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c +index 409a3f9d808..ef285c9692b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b) + { + return vcmpgtq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c +index 2624307be9d..8cabf987c9a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s8 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b) + { + return vcmpgtq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s8 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c +index be19e19f09f..da107d414b2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s16 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b) + { + return vcmpgtq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s16 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c +index 95f6c703b9d..4508698a856 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s32 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b) + { + return vcmpgtq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s32 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c +index 8ba180d8e39..d65d27704d0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s8 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b) + { + return vcmpgtq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s8 gt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vcmpgtq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c +index 26e5fe3f900..403ad11fee8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vcmphiq_m_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vcmphiq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vcmphiq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c +index 51396b8d0cd..a9c9816976d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vcmphiq_m_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vcmphiq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vcmphiq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c +index 475f2e82345..16e3af1d556 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vcmphiq_m_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vcmphiq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vcmphiq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c +index 98ba895fde0..139f69e392b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcmphiq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u16 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcmphiq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c +index ee561b02d0c..a33aed0a005 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcmphiq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u32 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcmphiq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c +index 0c5b29e2673..18e9b1907b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcmphiq_m_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.u8 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcmphiq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c +index d39b755441d..5712db2ceef 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16_t b) + { + return vcmphiq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16_t b) + { + return vcmphiq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint16x8_t a) ++{ ++ return vcmphiq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c +index dbedea9b078..f7a25af8574 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32_t b) + { + return vcmphiq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32_t b) + { + return vcmphiq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint32x4_t a) ++{ ++ return vcmphiq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c +index 967bb206886..8cd28fb1681 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8_t b) + { + return vcmphiq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vcmphiq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u8" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint8x16_t a) ++{ ++ return vcmphiq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c +index f9399498a99..3cff050425d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u16 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16x8_t b) + { + return vcmphiq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u16 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vcmphiq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c +index becdef0696a..39f0c12a75b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u32 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32x4_t b) + { + return vcmphiq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u32 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vcmphiq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c +index 933cc69507d..69103f502f5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.u8 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vcmphiq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.u8 hi, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vcmphiq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c +index c2e69a5de92..fb92b67325f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b) + { + return vcmpleq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c +index 923aee050d3..61ab55d83da 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b) + { + return vcmpleq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c +index 66a37192985..f866469eadb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpleq_m_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c +index e679b338d58..5704e6d7a0b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpleq_m_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c +deleted file mode 100644 +index 50e53bdac47..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpleq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c +index 42049fd57a4..5fa3be11c2a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpleq_m_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vcmpleq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c +deleted file mode 100644 +index b16da273a91..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpleq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c +index c68bd4e5900..cbab9606b3c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpleq_m_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a, mve_pred16_t p) ++{ ++ return vcmpleq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c +index 0cdc14455a3..d16b5c49e83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpleq_m_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c +index a955af8fa2b..e9504fad271 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpleq_m_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c +index d9951e4a8cf..10709a8520c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpleq_m_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c +index f16aff86ef0..59102a6eb60 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpleq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c +index 2c4e659e9cf..42d7d7fdbb3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpleq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c +index 69b88cfb389..3d1407baebf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpleq_m_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpleq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c +deleted file mode 100644 +index 4a4b97312b0..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpleq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c +index 3fa3c5e0310..1d1f4bf0e58 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b) + { + return vcmpleq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a) ++{ ++ return vcmpleq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c +deleted file mode 100644 +index 8d8f1051933..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpleq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c +index 8349de7b68c..bf77a808064 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b) + { + return vcmpleq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a) ++{ ++ return vcmpleq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c +index 5ecae572227..6aad8de937a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b) + { + return vcmpleq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c +index 02320e7a552..fedc87fa318 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b) + { + return vcmpleq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c +index a0ac97328b7..066dd808771 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s8 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b) + { + return vcmpleq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s8 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c +index 2fb4acd3d74..00872c3503c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s16 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b) + { + return vcmpleq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s16 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c +index 2ae998efb7c..8f595a0d24b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s32 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b) + { + return vcmpleq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s32 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c +index da06b019cc1..a827b9b6f5d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s8 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b) + { + return vcmpleq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s8 le, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vcmpleq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c +index eab80b2ddd9..15855e1bbed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b) + { + return vcmpltq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c +index f17d16482dd..d11c9e2f1e5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b) + { + return vcmpltq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c +index 93c36f3a613..efb525cacce 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpltq_m_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c +index a17f0b02a95..6c788202199 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpltq_m_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c +deleted file mode 100644 +index 62ab53fb2ef..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpltq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c +index 45d0f51b4d7..2b29d72bbf6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpltq_m_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vcmpltq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c +deleted file mode 100644 +index 55886fccff1..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpltq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c +index 16e37ccaf8d..0c89d2982e5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpltq_m_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a, mve_pred16_t p) ++{ ++ return vcmpltq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c +index d0e322fbede..34984fa7772 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpltq_m_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c +index 7ec7963267a..bb7c0a26bf1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpltq_m_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c +index 22434e88cd6..035ce454073 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpltq_m_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c +index 359c0640784..9776a4a64e9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpltq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s16 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c +index 3df7e89a6f5..6a7459806ef 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpltq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s32 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c +index 1055c2b661c..ca08e1dadf1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpltq_m_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.s8 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpltq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c +deleted file mode 100644 +index cd95daea48c..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpltq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c +index 2d55af20dd3..f9f091cd9b3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b) + { + return vcmpltq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a) ++{ ++ return vcmpltq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c +deleted file mode 100644 +index db76687d53e..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpltq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c +index 2590ca83c45..d22ea1aca30 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b) + { + return vcmpltq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a) ++{ ++ return vcmpltq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c +index 169f6ad4610..4c9d1d3d887 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b) + { + return vcmpltq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c +index 534047c2df3..632c4aeca13 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b) + { + return vcmpltq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c +index da659f1f2be..1eabc2e70bd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s8 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b) + { + return vcmpltq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s8 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c +index da4c90a07de..85117199a90 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s16 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b) + { + return vcmpltq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s16 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c +index 5dc218a5f40..11379cf7ff8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s32 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b) + { + return vcmpltq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s32 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c +index ea5853c212c..686ccd8eedb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.s8 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b) + { + return vcmpltq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.s8 lt, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vcmpltq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c +index 8d1c6096c56..20d722ca649 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b) + { + return vcmpneq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c +index 860bd69c129..1e4dcde89b1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b) + { + return vcmpneq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c +index a4e62de7272..bafb7e8a956 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpneq_m_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c +index b18a2e5fd88..168633d05c3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpneq_m_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c +deleted file mode 100644 +index 30618e87101..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vcmpneq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c +index c127b3a68f6..3b7951f4ee1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpneq_m_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vcmpneq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c +deleted file mode 100644 +index 4ecfda6d75c..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vcmpneq_m (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c +index a8423d45708..47b972cdeeb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpneq_m_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a, mve_pred16_t p) ++{ ++ return vcmpneq_m (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c +index 63ee1c3bffb..b16c6445942 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpneq_m_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c +index 10f6d448d76..2f8057050f1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpneq_m_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c +index 66e5d158c51..4637bd10d2e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpneq_m_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c +index ffe6ff919cf..90b23531f49 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vcmpneq_m_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vcmpneq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c +index 55e796a1138..c8b0c952730 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vcmpneq_m_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vcmpneq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c +index 3c8bd16647a..d458b9ad15b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c +@@ -1,22 +1,71 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vcmpneq_m_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vcmpneq_m (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c +index d3e1ce0e690..ea83993bd72 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpneq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c +index f5602ffd0da..817060f8d73 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpneq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c +index 84b8b1617b0..9c0473d228e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpneq_m_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c +index 3c8943719bb..4f10b5a787e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcmpneq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c +index 980cc4124b2..ba440459d5d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcmpneq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c +index 2615dcb37b9..ffe091bd082 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcmpneq_m_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmpt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmpt.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vcmpneq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c +deleted file mode 100644 +index 75a0090fcdc..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vcmpneq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c +index e9e2a9c7b04..83beca964d6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float16x8_t a, float16_t b) + { + return vcmpneq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float16x8_t a, float16_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float16x8_t a) ++{ ++ return vcmpneq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c +deleted file mode 100644 +index 11ae14cff56..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-mve_pred16_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vcmpneq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c +index eb64b17969c..abe1abfed2a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (float32x4_t a, float32_t b) + { + return vcmpneq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (float32x4_t a, float32_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.f32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (float32x4_t a) ++{ ++ return vcmpneq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c +index 14689242ee4..2e39b66b34c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16_t b) + { + return vcmpneq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c +index 53418ff3923..9471935d96f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32_t b) + { + return vcmpneq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c +index fa405c281b4..7d3d4ddd2c5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8_t b) + { + return vcmpneq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c +index cc8540b3a6c..ca55fe2f76c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16_t b) + { + return vcmpneq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint16x8_t a) ++{ ++ return vcmpneq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c +index 07c9b1ade96..77bac757d68 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32_t b) + { + return vcmpneq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint32x4_t a) ++{ ++ return vcmpneq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c +index eac5e96384e..352afa798d1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c +@@ -1,21 +1,59 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8_t b) + { + return vcmpneq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ ++/* ++**foo2: { xfail *-*-* } ++** ... ++** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ ++mve_pred16_t ++foo2 (uint8x16_t a) ++{ ++ return vcmpneq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c +index 6b04ce70ffc..a3b0572c011 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int16x8_t a, int16x8_t b) + { + return vcmpneq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int16x8_t a, int16x8_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c +index cfb98d7e650..c6bf6ca82d7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int32x4_t a, int32x4_t b) + { + return vcmpneq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int32x4_t a, int32x4_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c +index ae69be4ba0b..99b343b0427 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (int8x16_t a, int8x16_t b) + { + return vcmpneq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c +index 51059f21191..d676d9b3c22 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint16x8_t a, uint16x8_t b) + { + return vcmpneq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c +index 42e4a3f4f2d..56c39968035 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32x4_t a, uint32x4_t b) + { + return vcmpneq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c +index addacc15833..f906574d5e4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmp.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vcmpneq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ + ++/* ++**foo1: ++** ... ++** vcmp.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vcmpneq (a, b); + } + +-/* { dg-final { scan-assembler "vcmp.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c +index 142c315ecf5..456370e1de1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vcmulq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmulq (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c +index 158d750793d..64db652a1a1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vcmulq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmulq (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c +index b38e0d9fb52..b60f5d718f8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c +index 7bf68735e52..22157d4e58f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c +index fc7162aaa9c..f01b0f3421f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vcmulq_rot180_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmulq_rot180 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c +index 13a4553b6bd..537385c5209 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vcmulq_rot180_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmulq_rot180 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c +index 8767e2beee8..bc8692eb043 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot180_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot180_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c +index 3f951039f35..d2a0b6d3f2c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot180_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot180_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c +index f8e835f158f..37d7b79a75c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot180_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot180_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c +index d0d30c59d44..1e57fba4bd3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot180_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot180_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c +index 225b8910f88..05c444af804 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vcmulq_rot270_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmulq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c +index 1c8b0ebcf7e..b599c9fc171 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vcmulq_rot270_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmulq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c +index 20ccb5e9423..fded8a05089 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot270_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c +index 7499f4271a6..54d939eb378 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot270_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c +index d1b52e74d6d..d1e58cb84bb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot270_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c +index 35da5936f66..07c781f5103 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot270_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c +index 17f96cb0a78..53b1930c045 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vcmulq_rot90_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f16" } } */ + ++/* ++**foo1: ++** ... ++** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vcmulq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c +index 739fc9cd1fa..147f1807c29 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vcmulq_rot90_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f32" } } */ + ++/* ++**foo1: ++** ... ++** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vcmulq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vcmul.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c +index 8259baa82cc..8c4b0902b09 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot90_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c +index 751a9a6c03d..b3131a5e984 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot90_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c +index c4aef6cbf30..000610367b9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot90_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c +index 9c54f0870e7..8e31ad563c6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot90_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c +index 7634d61b6ea..b53324738f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vcmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c +index 21b6acf9733..a73482a09e1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vcmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c +index fb3601edb94..8d6764d8938 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + float16x8_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++float16x8_t ++foo1 () ++{ ++ return vcreateq_f16 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c +index 4f4da62eed7..6ab05ced809 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + float32x4_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++float32x4_t ++foo1 () ++{ ++ return vcreateq_f32 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c +index 103be6310bd..290637595a4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + int16x8_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++int16x8_t ++foo1 () ++{ ++ return vcreateq_s16 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c +index 96f7a972d93..4aeead1175e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + int32x4_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++int32x4_t ++foo1 () ++{ ++ return vcreateq_s32 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c +index 74c554506c0..9f6df427a8f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + int64x2_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_s64 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++int64x2_t ++foo1 () ++{ ++ return vcreateq_s64 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c +index 03c50a0928a..196c147fb65 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + int8x16_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++int8x16_t ++foo1 () ++{ ++ return vcreateq_s8 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c +index 411cec8471e..20b18e2ac15 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + uint16x8_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++uint16x8_t ++foo1 () ++{ ++ return vcreateq_u16 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c +index 8bc8f60640e..febfd3bd782 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + uint32x4_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++uint32x4_t ++foo1 () ++{ ++ return vcreateq_u32 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c +index e74641c32f3..5a49b346bf4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + uint64x2_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_u64 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++uint64x2_t ++foo1 () ++{ ++ return vcreateq_u64 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c +index de79f471d63..c0ac5e51225 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c +@@ -1,13 +1,42 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2 ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3 ++** ... ++*/ + uint8x16_t + foo (uint64_t a, uint64_t b) + { + return vcreateq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vmov" } } */ ++/* ++**foo1: ++** ... ++** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] ++** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] ++** ... ++*/ ++uint8x16_t ++foo1 () ++{ ++ return vcreateq_u8 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c +index 2659f061cd9..1575966073d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c +@@ -1,21 +1,44 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vctp.16 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a) + { + return vctp16q (a); + } + +-/* { dg-final { scan-assembler "vctp.16" } } */ +- ++/* ++**foo1: ++** ... ++** vctp.16 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a) ++foo1 () + { +- return vctp16q (a); ++ return vctp16q (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vctp.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c +index d901c9ece0d..a14fbe97f86 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c +@@ -1,22 +1,52 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.16 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a, mve_pred16_t p) + { + return vctp16q_m (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vctpt.16" } } */ +- ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.16 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a, mve_pred16_t p) ++foo1 (mve_pred16_t p) + { +- return vctp16q_m (a, p); ++ return vctp16q_m (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c +index f54ecc33e4a..c53b6190019 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c +@@ -1,21 +1,44 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vctp.32 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a) + { + return vctp32q (a); + } + +-/* { dg-final { scan-assembler "vctp.32" } } */ +- ++/* ++**foo1: ++** ... ++** vctp.32 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a) ++foo1 () + { +- return vctp32q (a); ++ return vctp32q (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vctp.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c +index 3d2f101fb0c..6fa790d7039 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c +@@ -1,22 +1,52 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.32 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a, mve_pred16_t p) + { + return vctp32q_m (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vctpt.32" } } */ +- ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.32 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a, mve_pred16_t p) ++foo1 (mve_pred16_t p) + { +- return vctp32q_m (a, p); ++ return vctp32q_m (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c +index 8502ad3b600..dba63bae1a8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c +@@ -1,21 +1,44 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vctp.64 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a) + { + return vctp64q (a); + } + +-/* { dg-final { scan-assembler "vctp.64" } } */ +- ++/* ++**foo1: ++** ... ++** vctp.64 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a) ++foo1 () + { +- return vctp64q (a); ++ return vctp64q (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vctp.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c +index 6f3d1c21d01..1faf8a0063c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c +@@ -1,22 +1,52 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.64 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a, mve_pred16_t p) + { + return vctp64q_m (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vctpt.64" } } */ +- ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.64 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a, mve_pred16_t p) ++foo1 (mve_pred16_t p) + { +- return vctp64q_m (a, p); ++ return vctp64q_m (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c +index 91283f82db1..56267fd861d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c +@@ -1,21 +1,44 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vctp.8 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a) + { + return vctp8q (a); + } + +-/* { dg-final { scan-assembler "vctp.8" } } */ +- ++/* ++**foo1: ++** ... ++** vctp.8 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a) ++foo1 () + { +- return vctp8q (a); ++ return vctp8q (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vctp.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c +index 2c640ba6801..937c33cbb83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c +@@ -1,22 +1,52 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.8 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (uint32_t a, mve_pred16_t p) + { + return vctp8q_m (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vctpt.8" } } */ +- ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vctpt.8 (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t +-foo1 (uint32_t a, mve_pred16_t p) ++foo1 (mve_pred16_t p) + { +- return vctp8q_m (a, p); ++ return vctp8q_m (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c +index ad8b7d9eb06..fcf4cf817ff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtaq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c +index 5649e342d1a..8aa640de6ac 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtaq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c +index b73c3418758..8fdd3c1b1b0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtaq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c +index 56c04f9f782..246941e7523 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtaq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c +index e2d70e8901f..c45ba6ccfbf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvta.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtaq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvta.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c +index d6fd45ae01e..baa20cc5f9a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvta.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtaq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvta.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c +index 8f3b12d9101..de4ea927385 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvta.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtaq_u16_f16 (a); ++ return vcvtaq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvta.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c +index 45e2916e288..93bf292980e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvta.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { +- return vcvtaq_u32_f32 (a); ++ return vcvtaq_u32_f32 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvta.u32.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c +index 26ff128217e..b046b7ad94d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtaq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c +index 3a79e3aecd4..77a740867be 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtaq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c +index 1f26e7f52d4..b8a10822bdb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtaq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c +index 987e524d789..51184231b7a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtaq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c +index f45e07de375..76b76a2f66e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtb.f16.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float32x4_t b) + { + return vcvtbq_f16_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcvtb.f16.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c +index 39471a0a43b..347d4129b99 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtb.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float16x8_t a) + { + return vcvtbq_f32_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c +index 6c8d9192417..0545d1e8e27 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c +@@ -1,22 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtbt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float32x4_t b, mve_pred16_t p) + { + return vcvtbq_m_f16_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtbt.f16.f32" } } */ +- +-float16x8_t +-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vcvtbq_m (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c +index 91775436e67..1b220ddfa19 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c +@@ -1,22 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtbt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtbq_m_f32_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */ +- +-float32x4_t +-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p) +-{ +- return vcvtbq_m (inactive, a, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c +index 0dcdb19d1e4..2a3559d2522 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtbt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtbq_x_f32_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c +index 75ff107ab15..b8f6ed855d6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtmq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c +index b364533e08d..61445594524 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtmq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c +index 249ef0e92b1..3e57ba58d0f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtmq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c +index 52ff77ca4c5..8b8a1565332 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtmq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c +index 70f43ddc220..4eafb5783b2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtm.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtmq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtm.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c +index c2f62cf0717..bd3bfc1b4bd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtm.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtmq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvtm.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c +index 62e4acd73b5..a1917eaf11a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtm.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtmq_u16_f16 (a); ++ return vcvtmq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtm.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c +index f7f59df1be9..c9f62479e85 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtm.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { +- return vcvtmq_u32_f32 (a); ++ return vcvtmq_u32_f32 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtm.u32.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c +index 22597fb9cb1..211c2d0df83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtmq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c +index 17a583c2641..7ca2cb6eb15 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtmq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c +index b6e296f29ea..df212089bf5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtmq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c +index 5f9909b5adb..8b5818fd029 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtmq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c +index a7c3b66a2eb..67fa9cb720d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtnq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c +index 38913a9e26c..26c0b09f7b5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtnq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c +index 42d9e5ea79c..ee2a64747a2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtnq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c +index 321fa35ceb3..cc61951abf5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtnq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c +index d66c058834e..39c00f6ed04 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtn.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtnq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtn.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c +index 3dec6661411..c371598db24 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtn.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtnq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvtn.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c +index 07637e84bf7..17ae06a57be 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtn.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtnq_u16_f16 (a); ++ return vcvtnq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtn.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c +index b6d5eb90493..4777b1b205a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtn.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { + return vcvtnq_u32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvtn.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c +index f552d633231..a9c91831881 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtnq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c +index c3aa2e3daed..2ffb1d98736 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtnq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c +index 9d9d12f9f2c..ce2ceb108b2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtnq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c +index e7df48de88d..c2c48ef1558 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtnq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c +index c613fc8883d..f09c78b77c2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtpq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c +index 7f4c7f600e5..7a3d7763406 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtpq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c +index 192891021f0..f82103ca831 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtpq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c +index 61858f7844a..7c848aa5157 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtpq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c +index 8615e50bbaa..87258346b53 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtp.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtpq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtp.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c +index fed7a4b83f7..e4a7d0baaf1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtp.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtpq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvtp.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c +index 37d1411067f..94edfcb0244 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtp.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtpq_u16_f16 (a); ++ return vcvtpq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtp.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c +index fcea4c51885..b84501ca72c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtp.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { +- return vcvtpq_u32_f32 (a); ++ return vcvtpq_u32_f32 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvtp.u32.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c +index 5d550772bfc..2b51cc56867 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtpq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c +index 31823ab9528..6c4d6655300 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtpq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c +index 0d1808c0fe8..2e663c8a472 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtpq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c +index d73df212942..2d32425fdbf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtpq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c +index 560127b7c9f..9f1647c1ac8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (int16x8_t a) + { + return vcvtq_f16_s16 (a); + } + +-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ ++ ++/* ++**foo1: ++** ... ++** vcvt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (int16x8_t a) ++{ ++ return vcvtq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c +index f571c535778..6704626bd1e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (uint16x8_t a) + { + return vcvtq_f16_u16 (a); + } + +-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ ++ ++/* ++**foo1: ++** ... ++** vcvt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (uint16x8_t a) ++{ ++ return vcvtq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c +index 898c74bfba4..898126468d9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (int32x4_t a) + { + return vcvtq_f32_s32 (a); + } + +-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ ++ ++/* ++**foo1: ++** ... ++** vcvt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (int32x4_t a) ++{ ++ return vcvtq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c +index a44add5d178..9e9aa1d703e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t a) + { + return vcvtq_f32_u32 (a); + } + +-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ ++ ++/* ++**foo1: ++** ... ++** vcvt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (uint32x4_t a) ++{ ++ return vcvtq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c +index 45e9b045af6..b01a9a148c6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vcvtq_m_f16_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c +index b50f57234c3..805e26e72fd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vcvtq_m_f16_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c +index 4c1af180b58..7faa130fa3f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vcvtq_m_f32_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c +index 49acef80489..589d4efa61b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vcvtq_m_f32_u32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c +index d5ba7a690a6..3e23f1d88d8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n_f16_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c +index e53d7fa6ef1..f6f309cba25 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n_f16_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c +index 58519c04ff4..e6ff2fd6f44 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n_f32_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c +index 782d1f9e259..7368f127aab 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vcvtq_m_n_f32_u32 (inactive, a, 16, p); ++ return vcvtq_m_n_f32_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vcvtq_m_n (inactive, a, 16, p); ++ return vcvtq_m_n (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c +index cd3f373aa77..edfb01203dd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n_s16_f16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c +index d1ff5072223..8084160e7e9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n_s32_f32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c +index 4bf12e8b64e..1d217387ac6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n_u16_f16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c +index 4d0b1bf7a7f..868a1bcc1b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n_u32_f32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c +index 606e43614ea..a998cdcb11a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_s16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c +index 2204e7929ec..fdaeac453a4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_s32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c +index 1f814251c4f..f168d371615 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m_u16_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c +index 13cd6f28884..83e5ae38106 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m_u32_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vcvtq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c +index 565012e4e93..5c017221889 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (int16x8_t a) + { + return vcvtq_n_f16_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vcvt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (int16x8_t a) + { + return vcvtq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c +index 95acc29683f..1080a5a0309 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (uint16x8_t a) + { + return vcvtq_n_f16_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vcvt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (uint16x8_t a) + { + return vcvtq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c +index 5285099bc2a..020138b0084 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (int32x4_t a) + { + return vcvtq_n_f32_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vcvt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (int32x4_t a) + { + return vcvtq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c +index ad6335116bc..3f1c3c8c9e4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t a) + { + return vcvtq_n_f32_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vcvt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (uint32x4_t a) + { + return vcvtq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c +index ed3dd1a87d6..d16c114e00b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtq_n_s16_f16 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c +index e7f63f8cdd2..9256cb48a26 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtq_n_s32_f32 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c +index ca2fdca9b49..1038af8f890 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { + return vcvtq_n_u16_f16 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c +index 2919ea5b364..5c06365b320 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { + return vcvtq_n_u32_f32 (a, 1); + } + +-/* { dg-final { scan-assembler "vcvt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c +index 8269bf949bf..ecec3727529 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a) + { + return vcvtq_s16_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c +index 2af96d25917..9be17c0696c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a) + { + return vcvtq_s32_f32 (a); + } + +-/* { dg-final { scan-assembler "vcvt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c +index afac0f4d414..3c33f2ce5b1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a) + { +- return vcvtq_u16_f16 (a); ++ return vcvtq_u16_f16 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvt.u16.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c +index 7380f73301a..8e70df955b9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a) + { +- return vcvtq_u32_f32 (a); ++ return vcvtq_u32_f32 (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vcvt.u32.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c +index c6b9c1005f5..73b368fdd4f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vcvtq_x_f16_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vcvtq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c +index d3ef02c1931..13d7fed2f5b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vcvtq_x_f16_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vcvtq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c +index fa73ad69ce5..d14099c87a6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vcvtq_x_f32_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vcvtq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c +index 99ca3881553..800d8aa8e8e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vcvtq_x_f32_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vcvtq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c +index 718c83e74df..f91021d5735 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n_f16_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c +index 510c29c383a..f4c444b5540 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n_f16_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c +index 34f7cc1e061..7c11f1f0c34 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vcvtq_x_n_f32_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vcvtq_x_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c +index b5b20efc1b8..96a1d2c8876 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { +- return vcvtq_x_n_f32_u32 (a, 16, p); ++ return vcvtq_x_n_f32_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { +- return vcvtq_x_n (a, 16, p); ++ return vcvtq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c +index 3c3343ae4e1..7c0f551d66f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n_s16_f16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c +index 17ef866af39..c22eeb75a17 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtq_x_n_s32_f32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c +index 62e6f1638d5..7f07b0fac53 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtq_x_n_u16_f16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c +index 306e32016ff..7531db7d575 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtq_x_n_u32_f32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c +index 56867da3bb0..fd90d67b46c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtq_x_s16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c +index 4449bd68c54..e6cbbeaca2a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtq_x_s32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c +index 580bb775c59..29d1d9d5c56 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvtq_x_u16_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c +index 3722de632e5..0181850d857 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vcvtq_x_u32_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c +index 599e30e3d26..3c9a6844e01 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float32x4_t b) + { + return vcvttq_f16_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vcvtt.f16.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c +index a4a7997d2dd..9d389382ae9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vcvtt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float16x8_t a) + { + return vcvttq_f32_f16 (a); + } + +-/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c +index 065974d7e76..2eeb670a5a2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c +@@ -1,22 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvttt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float32x4_t b, mve_pred16_t p) + { + return vcvttq_m_f16_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvttt.f16.f32" } } */ +- +-float16x8_t +-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vcvttq_m (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c +index 1eb69e4fee9..ba309114dae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c +@@ -1,22 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvttt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p) + { + return vcvttq_m_f32_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */ +- +-float32x4_t +-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p) +-{ +- return vcvttq_m (inactive, a, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c +index 921caba0e1b..29688a939dd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vcvttt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float16x8_t a, mve_pred16_t p) + { + return vcvttq_x_f32_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c +index 7332711f6a7..86e6e0ed5c0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p) + { + return vddupq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p) + { + return vddupq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, mve_pred16_t p) ++{ ++ return vddupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c +index 54ad91f2803..c5aa5323edc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p) + { +- return vddupq_m_n_u32 (inactive, a, 4, p); ++ return vddupq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p) + { +- return vddupq_m (inactive, a, 4, p); ++ return vddupq_m (inactive, a, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, mve_pred16_t p) ++{ ++ return vddupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c +index 3746b5db6e5..e326a00062f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p) + { +- return vddupq_m_n_u8 (inactive, a, 4, p); ++ return vddupq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p) + { +- return vddupq_m (inactive, a, 4, p); ++ return vddupq_m (inactive, a, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, mve_pred16_t p) ++{ ++ return vddupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c +index 8b5d9e86469..2a907417b40 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) + { + return vddupq_m_wb_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) + { + return vddupq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, mve_pred16_t p) ++{ ++ return vddupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c +index 7a8c363ac70..ffaf3734923 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) + { +- return vddupq_m_wb_u32 (inactive, a, 4, p); ++ return vddupq_m_wb_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) + { +- return vddupq_m (inactive, a, 4, p); ++ return vddupq_m (inactive, a, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, mve_pred16_t p) ++{ ++ return vddupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c +index 45784a5c9cd..ae7a4e25fe2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) + { +- return vddupq_m_wb_u8 (inactive, a, 4, p); ++ return vddupq_m_wb_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) + { +- return vddupq_m (inactive, a, 4, p); ++ return vddupq_m (inactive, a, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, mve_pred16_t p) ++{ ++ return vddupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c +index 4684e2af553..dbaf372e446 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t a) + { +- return vddupq_n_u16 (a, 4); ++ return vddupq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u16" } } */ + ++/* ++**foo1: ++** ... ++** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t a) + { +- return vddupq_u16 (a, 4); ++ return vddupq_u16 (a, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 () ++{ ++ return vddupq_u16 (1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vddup.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c +index aeaa83eb6bc..cf932541023 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a) + { + return vddupq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u32" } } */ + ++/* ++**foo1: ++** ... ++** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t a) + { + return vddupq_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u32" } } */ ++/* ++**foo2: ++** ... ++** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 () ++{ ++ return vddupq_u32 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c +index 255a9f80b6b..60088880776 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t a) + { + return vddupq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u8" } } */ + ++/* ++**foo1: ++** ... ++** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t a) + { + return vddupq_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u8" } } */ ++/* ++**foo2: ++** ... ++** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 () ++{ ++ return vddupq_u8 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c +index 40fc6cf2197..6c54e325155 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t *a) + { +- return vddupq_wb_u16 (a, 4); ++ return vddupq_wb_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u16" } } */ + ++/* ++**foo1: ++** ... ++** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t *a) + { +- return vddupq_u16 (a, 4); ++ return vddupq_u16 (a, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 () ++{ ++ return vddupq_u16 (1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vddup.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c +index 09b5b1f2f80..a8de90f7b12 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t *a) + { + return vddupq_wb_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u32" } } */ + ++/* ++**foo1: ++** ... ++** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t *a) + { + return vddupq_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u32" } } */ ++/* ++**foo2: ++** ... ++** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 () ++{ ++ return vddupq_u32 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c +index 00dfa906748..5a90e069b1d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t *a) + { + return vddupq_wb_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u8" } } */ + ++/* ++**foo1: ++** ... ++** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t *a) + { + return vddupq_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vddup.u8" } } */ ++/* ++**foo2: ++** ... ++** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 () ++{ ++ return vddupq_u8 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c +index 5b0fc0b6340..12e13ad5af7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t a, mve_pred16_t p) + { + return vddupq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t a, mve_pred16_t p) + { + return vddupq_x_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (mve_pred16_t p) ++{ ++ return vddupq_x_u16 (1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c +index 66def991b65..ebe7270f28d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a, mve_pred16_t p) + { +- return vddupq_x_n_u32 (a, 4, p); ++ return vddupq_x_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t a, mve_pred16_t p) + { +- return vddupq_x_u32 (a, 4, p); ++ return vddupq_x_u32 (a, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (mve_pred16_t p) ++{ ++ return vddupq_x_u32 (1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c +index 8ac322ed52d..d53d45fc852 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t a, mve_pred16_t p) + { +- return vddupq_x_n_u8 (a, 4, p); ++ return vddupq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t a, mve_pred16_t p) + { +- return vddupq_x_u8 (a, 4, p); ++ return vddupq_x_u8 (a, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (mve_pred16_t p) ++{ ++ return vddupq_x_u8 (1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c +index 030048f840a..dab65e08320 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c +@@ -1,25 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-uint32_t *a; ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (mve_pred16_t p) ++foo (uint32_t *a, mve_pred16_t p) + { +- return vddupq_x_wb_u16 (a, 2, p); ++ return vddupq_x_wb_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (mve_pred16_t p) ++foo1 (uint32_t *a, mve_pred16_t p) + { +- return vddupq_x_u16 (a, 2, p); ++ return vddupq_x_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (mve_pred16_t p) ++{ ++ return vddupq_x_u16 (1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c +index 95bf28e4052..c7abcaef942 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c +@@ -1,25 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-uint32_t *a; ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (mve_pred16_t p) ++foo (uint32_t *a, mve_pred16_t p) + { +- return vddupq_x_wb_u32 (a, 8, p); ++ return vddupq_x_wb_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (mve_pred16_t p) ++foo1 (uint32_t *a, mve_pred16_t p) + { +- return vddupq_x_u32 (a, 8, p); ++ return vddupq_x_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (mve_pred16_t p) ++{ ++ return vddupq_x_u32 (1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c +index 2fe81dded55..d2c299d4e3f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c +@@ -1,25 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-uint32_t *a; ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (mve_pred16_t p) ++foo (uint32_t *a, mve_pred16_t p) + { +- return vddupq_x_wb_u8 (a, 8, p); ++ return vddupq_x_wb_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (mve_pred16_t p) ++foo1 (uint32_t *a, mve_pred16_t p) + { +- return vddupq_x_u8 (a, 8, p); ++ return vddupq_x_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vddupt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (mve_pred16_t p) ++{ ++ return vddupq_x_u8 (1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c +index 0b749be3527..df7438bf0a0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c +@@ -1,22 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16_t a, mve_pred16_t p) + { + return vdupq_m_n_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16_t a, mve_pred16_t p) + { + return vdupq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t inactive, mve_pred16_t p) ++{ ++ return vdupq_m (inactive, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c +index 9cca5310c7a..6397b902705 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c +@@ -1,22 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32_t a, mve_pred16_t p) + { + return vdupq_m_n_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32_t a, mve_pred16_t p) + { + return vdupq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t inactive, mve_pred16_t p) ++{ ++ return vdupq_m (inactive, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c +index b521f13e94f..bf05c73fc1d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16_t a, mve_pred16_t p) + { + return vdupq_m_n_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16_t a, mve_pred16_t p) + { + return vdupq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c +index 96aa195dc18..71789bb620e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32_t a, mve_pred16_t p) + { + return vdupq_m_n_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32_t a, mve_pred16_t p) + { + return vdupq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c +index f1d222000c1..48c4fbd1f82 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8_t a, mve_pred16_t p) + { + return vdupq_m_n_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8_t a, mve_pred16_t p) + { + return vdupq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c +index 39d0c9f502d..511be48ebae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c +@@ -1,22 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16_t a, mve_pred16_t p) + { + return vdupq_m_n_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16_t a, mve_pred16_t p) + { + return vdupq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, mve_pred16_t p) ++{ ++ return vdupq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c +index fc107172e16..f3a2c25f5ab 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c +@@ -1,22 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p) + { + return vdupq_m_n_u32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p) + { + return vdupq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, mve_pred16_t p) ++{ ++ return vdupq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c +index 9fd3bc443cb..a99d8f3d86b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c +@@ -1,22 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8_t a, mve_pred16_t p) + { + return vdupq_m_n_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8_t a, mve_pred16_t p) + { + return vdupq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, mve_pred16_t p) ++{ ++ return vdupq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c +index 62bfc194533..44112190fb8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16_t a) + { + return vdupq_n_f16 (a); + } + +-/* { dg-final { scan-assembler "vdup.16" } } */ ++/* ++**foo1: ++** ... ++** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 () ++{ ++ return vdupq_n_f16 (1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c +index f5ad2286d8d..059e3e42dd0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32_t a) + { + return vdupq_n_f32 (a); + } + +-/* { dg-final { scan-assembler "vdup.32" } } */ ++/* ++**foo1: ++** ... ++** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 () ++{ ++ return vdupq_n_f32 (1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c +index 1378522a18e..d8ba299cb15 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c +@@ -1,13 +1,28 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16_t a) + { + return vdupq_n_s16 (a); + } + +-/* { dg-final { scan-assembler "vdup.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c +index 43affe856c0..a81c6d1e220 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c +@@ -1,13 +1,28 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32_t a) + { + return vdupq_n_s32 (a); + } + +-/* { dg-final { scan-assembler "vdup.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c +index 3f934dc5d59..b0bac4fce89 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdup.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8_t a) + { + return vdupq_n_s8 (a); + } + +-/* { dg-final { scan-assembler "vdup.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c +index 93268643fec..55e0a601110 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16_t a) + { +- return vdupq_n_u16 (a); ++ return vdupq_n_u16 (a); ++} ++ ++/* ++**foo1: ++** ... ++** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 () ++{ ++ return vdupq_n_u16 (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vdup.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c +index 276e9ddc67f..bf73bc17fc7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a) + { +- return vdupq_n_u32 (a); ++ return vdupq_n_u32 (a); ++} ++ ++/* ++**foo1: ++** ... ++** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 () ++{ ++ return vdupq_n_u32 (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vdup.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c +index d0361c15047..48cbdb2a1da 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c +@@ -1,13 +1,40 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdup.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8_t a) + { +- return vdupq_n_u8 (a); ++ return vdupq_n_u8 (a); ++} ++ ++/* ++**foo1: ++** ... ++** vdup.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 () ++{ ++ return vdupq_n_u8 (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vdup.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c +index c91ee62791c..7821e365293 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c +@@ -1,14 +1,48 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16_t a, mve_pred16_t p) + { + return vdupq_x_n_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.16" } } */ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (mve_pred16_t p) ++{ ++ return vdupq_x_n_f16 (1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c +index c2b39051f5b..af82b3ebdbc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c +@@ -1,14 +1,48 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32_t a, mve_pred16_t p) + { + return vdupq_x_n_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.32" } } */ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (mve_pred16_t p) ++{ ++ return vdupq_x_n_f32 (1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c +index cc8a5bfeca1..6756502ab21 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16_t a, mve_pred16_t p) + { + return vdupq_x_n_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c +index b3ed3eb68e8..b04afb3834b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32_t a, mve_pred16_t p) + { + return vdupq_x_n_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c +index 3be865dcc84..b23facd5e94 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8_t a, mve_pred16_t p) + { + return vdupq_x_n_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c +index d01338aeb91..62dc42c6eae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c +@@ -1,14 +1,48 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16_t a, mve_pred16_t p) + { + return vdupq_x_n_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.16" } } */ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (mve_pred16_t p) ++{ ++ return vdupq_x_n_u16 (1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c +index 8fa7d4552bc..098fdfbd233 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c +@@ -1,14 +1,48 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a, mve_pred16_t p) + { + return vdupq_x_n_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.32" } } */ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (mve_pred16_t p) ++{ ++ return vdupq_x_n_u32 (1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c +index 96ad899c9c2..02a4253e74a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c +@@ -1,14 +1,48 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8_t a, mve_pred16_t p) + { + return vdupq_x_n_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdupt.8" } } */ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (mve_pred16_t p) ++{ ++ return vdupq_x_n_u8 (1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c +index 5303fd7d361..dc4dbb9f432 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 1, p); ++ return vdwdupq_m_n_u16 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { + return vdwdupq_m (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, mve_pred16_t p) ++{ ++ return vdwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c +index 9f22bd7f852..edfc4c464be 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 4, p); ++ return vdwdupq_m_n_u32 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 4, p); ++ return vdwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, mve_pred16_t p) ++{ ++ return vdwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c +index 0591e731958..009048fdb05 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 4, p); ++ return vdwdupq_m_n_u8 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 4, p); ++ return vdwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, mve_pred16_t p) ++{ ++ return vdwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c +index e4e7b47e082..b24e7a2f5af 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) ++foo (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 8, p); ++ return vdwdupq_m_wb_u16 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) ++foo1 (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 8, p); ++ return vdwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, mve_pred16_t p) ++{ ++ return vdwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c +index 42917dc9886..75c41450a38 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) ++foo (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 1, p); ++ return vdwdupq_m_wb_u32 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) ++foo1 (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { + return vdwdupq_m (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, mve_pred16_t p) ++{ ++ return vdwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c +index 32c3153ffb3..90d64671dcf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) ++foo (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 2, p); ++ return vdwdupq_m_wb_u8 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) ++foo1 (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_m (inactive, a, b, 2, p); ++ return vdwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, mve_pred16_t p) ++{ ++ return vdwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c +index 725a6e4bc0e..6235b1422b1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t a, uint32_t b) + { +- return vdwdupq_n_u16 (a, b, 2); ++ return vdwdupq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vdwdup.u16" } } */ + ++/* ++**foo1: ++** ... ++** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t a, uint32_t b) + { +- return vdwdupq_u16 (a, b, 2); ++ return vdwdupq_u16 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 () ++{ ++ return vdwdupq_u16 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vdwdup.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c +index 6ceaadb984d..b6ce427015a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a, uint32_t b) + { +- return vdwdupq_n_u32 (a, b, 8); ++ return vdwdupq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vdwdup.u32" } } */ + ++/* ++**foo1: ++** ... ++** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t a, uint32_t b) + { +- return vdwdupq_u32 (a, b, 8); ++ return vdwdupq_u32 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 () ++{ ++ return vdwdupq_u32 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vdwdup.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c +index a1712e418be..bec1eb5165d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t a, uint32_t b) + { +- return vdwdupq_n_u8 (a, b, 4); ++ return vdwdupq_n_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vdwdup.u8" } } */ + ++/* ++**foo1: ++** ... ++** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t a, uint32_t b) + { +- return vdwdupq_u8 (a, b, 4); ++ return vdwdupq_u8 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 () ++{ ++ return vdwdupq_u8 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vdwdup.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c +index 0164ea9502c..87af2b6817a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t *a, uint32_t b) + { +- return vdwdupq_wb_u16 (a, b, 2); ++ return vdwdupq_wb_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vdwdup.u16" } } */ + ++/* ++**foo1: ++** ... ++** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t *a, uint32_t b) + { +- return vdwdupq_u16 (a, b, 2); ++ return vdwdupq_u16 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 () ++{ ++ return vdwdupq_u16 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vdwdup.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c +index 7681371b016..ec136dc3222 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t *a, uint32_t b) + { +- return vdwdupq_wb_u32 (a, b, 8); ++ return vdwdupq_wb_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vdwdup.u32" } } */ + ++/* ++**foo1: ++** ... ++** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t *a, uint32_t b) + { +- return vdwdupq_u32 (a, b, 8); ++ return vdwdupq_u32 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 () ++{ ++ return vdwdupq_u32 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vdwdup.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c +index 6f60bb09b24..3653d00bc5d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t *a, uint32_t b) + { +- return vdwdupq_wb_u8 (a, b, 4); ++ return vdwdupq_wb_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vdwdup.u8" } } */ + ++/* ++**foo1: ++** ... ++** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t *a, uint32_t b) + { +- return vdwdupq_u8 (a, b, 4); ++ return vdwdupq_u8 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 () ++{ ++ return vdwdupq_u8 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vdwdup.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c +index ce975267531..e9ef2df77c8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t a, uint32_t b, mve_pred16_t p) + { + return vdwdupq_x_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t a, uint32_t b, mve_pred16_t p) + { + return vdwdupq_x_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (mve_pred16_t p) ++{ ++ return vdwdupq_x_u16 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c +index 9ed75d292d8..6cc1582c22b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_x_n_u32 (a, b, 4, p); ++ return vdwdupq_x_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_x_u32 (a, b, 4, p); ++ return vdwdupq_x_u32 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (mve_pred16_t p) ++{ ++ return vdwdupq_x_u32 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c +index 3705094c4df..3216d250aa4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_x_n_u8 (a, b, 4, p); ++ return vdwdupq_x_n_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_x_u8 (a, b, 4, p); ++ return vdwdupq_x_u8 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (mve_pred16_t p) ++{ ++ return vdwdupq_x_u8 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c +index caf744d7255..e9d994ccfc5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_x_wb_u16 (a, b, 8, p); ++ return vdwdupq_x_wb_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_x_u16 (a, b, 8, p); ++ return vdwdupq_x_u16 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (mve_pred16_t p) ++{ ++ return vdwdupq_x_u16 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c +index 8c8be86bce6..07438b02351 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo (uint32_t *a, uint32_t b, mve_pred16_t p) + { + return vdwdupq_x_wb_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) + { + return vdwdupq_x_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (mve_pred16_t p) ++{ ++ return vdwdupq_x_u32 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c +index 1c6ef4ed33f..96280225351 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_x_wb_u8 (a, b, 2, p); ++ return vdwdupq_x_wb_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return vdwdupq_x_u8 (a, b, 2, p); ++ return vdwdupq_x_u8 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (mve_pred16_t p) ++{ ++ return vdwdupq_x_u8 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vdwdupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c +index 90cd663c7f3..0c27a1c5664 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return veorq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c +index e9ad87a9796..cbf67e335ef 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return veorq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c +index a39d680e0cd..5d9831f8d34 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return veorq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c +index a5dbfc4725e..ea992de1fbc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return veorq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c +index 9ab271ac987..f2b8b91aa13 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return veorq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c +index 45d5074e32b..c9573f732aa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return veorq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c +index 5b8ac0a286e..86cb8ed31c8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return veorq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c +index e436a9e6536..7b2b1ea1596 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return veorq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c +index 631abb515fd..3d3b2bbb4e6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return veorq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c +index ba65042f986..7d2baba6e8e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return veorq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return veorq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c +index b49e35c887f..8275da1d7fe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return veorq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c +index 9b6414b8458..ea111b4256d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return veorq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c +index 4a18bf5a165..f40dddcbb6e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return veorq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c +index 90d5a5a6021..f16ddc14e09 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return veorq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c +index b6103d68638..33213c53aa7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return veorq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c +index 86fccc1bef0..aba155b1023 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return veorq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ + ++/* ++**foo1: ++** ... ++** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return veorq (a, b); + } + +-/* { dg-final { scan-assembler "veor" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c +index eb9e44cb777..8eac5ee6ae0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return veorq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c +index 3503250e5c3..3e71870daf0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return veorq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c +index 837210bb609..fd032647117 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return veorq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c +index 93796e333ab..ec67ddc761b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return veorq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c +index ed88d43834d..35a1dfdab8a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return veorq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c +index e6e82d8076d..7aad6d6f5c1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return veorq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c +index 17393d80233..315241581f8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return veorq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c +index 027968dab2d..615b1e645b1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return veorq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return veorq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "veort" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c +index 8c926bdf1c3..18a184a0e98 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16x8_t c) ++foo (float16x8_t add, float16x8_t m1, float16x8_t m2) + { +- return vfmaq_f16 (a, b, c); ++ return vfmaq_f16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfma.f16" } } */ + ++/* ++**foo1: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16x8_t c) ++foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2) + { +- return vfmaq (a, b, c); ++ return vfmaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfma.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c +index c2fff9a43ea..5d67439b11e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32x4_t c) ++foo (float32x4_t add, float32x4_t m1, float32x4_t m2) + { +- return vfmaq_f32 (a, b, c); ++ return vfmaq_f32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfma.f32" } } */ + ++/* ++**foo1: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32x4_t c) ++foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2) + { +- return vfmaq (a, b, c); ++ return vfmaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfma.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c +index e8453e0cb41..e094cba8acb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) ++foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p) + { +- return vfmaq_m_f16 (a, b, c, p); ++ return vfmaq_m_f16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) ++foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p) + { +- return vfmaq_m (a, b, c, p); ++ return vfmaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c +index 9d1844eba5a..3003eff236a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) ++foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p) + { +- return vfmaq_m_f32 (a, b, c, p); ++ return vfmaq_m_f32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) ++foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p) + { +- return vfmaq_m (a, b, c, p); ++ return vfmaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c +deleted file mode 100644 +index e47ae6d8e3b..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) +-{ +- return vfmaq_m (a, b, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c +index 888016e8164..4603f038467 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) ++foo (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p) + { +- return vfmaq_m_n_f16 (a, b, c, p); ++ return vfmaq_m_n_f16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) ++foo1 (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p) + { +- return vfmaq_m (a, b, c, p); ++ return vfmaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t add, float16x8_t m1, mve_pred16_t p) ++{ ++ return vfmaq_m (add, m1, 1.1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c +deleted file mode 100644 +index 78c39f0b2c9..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) +-{ +- return vfmaq_m (a, b, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c +index f9afc8845b0..ad0ff907810 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) ++foo (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p) + { +- return vfmaq_m_n_f32 (a, b, c, p); ++ return vfmaq_m_n_f32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) ++foo1 (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p) + { +- return vfmaq_m (a, b, c, p); ++ return vfmaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t add, float32x4_t m1, mve_pred16_t p) ++{ ++ return vfmaq_m (add, m1, 1.1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmat.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c +deleted file mode 100644 +index f7867f2c0c3..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c) +-{ +- return vfmaq (a, b, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c +index 208c46f5960..8e8738bc10a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16_t c) ++foo (float16x8_t add, float16x8_t m1, float16_t m2) + { +- return vfmaq_n_f16 (a, b, c); ++ return vfmaq_n_f16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfma.f16" } } */ + ++/* ++**foo1: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c) ++foo1 (float16x8_t add, float16x8_t m1, float16_t m2) + { +- return vfmaq (a, b, c); ++ return vfmaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t add, float16x8_t m1) ++{ ++ return vfmaq (add, m1, 1.1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfma.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c +deleted file mode 100644 +index f0bc45bfed9..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c) +-{ +- return vfmaq (a, b, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c +index 664533239b7..4781e089ffb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32_t c) ++foo (float32x4_t add, float32x4_t m1, float32_t m2) + { +- return vfmaq_n_f32 (a, b, c); ++ return vfmaq_n_f32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfma.f32" } } */ + ++/* ++**foo1: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c) ++foo1 (float32x4_t add, float32x4_t m1, float32_t m2) + { +- return vfmaq (a, b, c); ++ return vfmaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t add, float32x4_t m1) ++{ ++ return vfmaq (add, m1, 1.1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfma.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c +deleted file mode 100644 +index 4750e108b6d..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) +-{ +- return vfmasq_m (a, b, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c +index 06d2d114e46..3f57b80874e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmast.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) ++foo (float16x8_t m1, float16x8_t m2, float16_t add, mve_pred16_t p) + { +- return vfmasq_m_n_f16 (a, b, c, p); ++ return vfmasq_m_n_f16 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmast.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmast.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p) ++foo1 (float16x8_t m1, float16x8_t m2, float16_t add, mve_pred16_t p) + { +- return vfmasq_m (a, b, c, p); ++ return vfmasq_m (m1, m2, add, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmast.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t m1, float16x8_t m2, mve_pred16_t p) ++{ ++ return vfmasq_m (m1, m2, 1.1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmast.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c +deleted file mode 100644 +index 4a379711386..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) +-{ +- return vfmasq_m (a, b, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c +index bf1773d0eeb..728633f5c9e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmast.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) ++foo (float32x4_t m1, float32x4_t m2, float32_t add, mve_pred16_t p) + { +- return vfmasq_m_n_f32 (a, b, c, p); ++ return vfmasq_m_n_f32 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmast.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmast.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p) ++foo1 (float32x4_t m1, float32x4_t m2, float32_t add, mve_pred16_t p) + { +- return vfmasq_m (a, b, c, p); ++ return vfmasq_m (m1, m2, add, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmast.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t m1, float32x4_t m2, mve_pred16_t p) ++{ ++ return vfmasq_m (m1, m2, 1.1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmast.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c +deleted file mode 100644 +index db824512b2b..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c) +-{ +- return vfmasq (a, b, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c +index ce9bf48d657..def309387fa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16_t c) ++foo (float16x8_t m1, float16x8_t m2, float16_t add) + { +- return vfmasq_n_f16 (a, b, c); ++ return vfmasq_n_f16 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vfmas.f16" } } */ + ++/* ++**foo1: ++** ... ++** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16_t c) ++foo1 (float16x8_t m1, float16x8_t m2, float16_t add) + { +- return vfmasq (a, b, c); ++ return vfmasq (m1, m2, add); ++} ++ ++/* ++**foo2: ++** ... ++** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t m1, float16x8_t m2) ++{ ++ return vfmasq (m1, m2, 1.1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfmas.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c +deleted file mode 100644 +index 12b1410c008..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c) +-{ +- return vfmasq (a, b, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c +index 46c5a320644..c761bdcb109 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32_t c) ++foo (float32x4_t m1, float32x4_t m2, float32_t add) + { +- return vfmasq_n_f32 (a, b, c); ++ return vfmasq_n_f32 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vfmas.f32" } } */ + ++/* ++**foo1: ++** ... ++** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32_t c) ++foo1 (float32x4_t m1, float32x4_t m2, float32_t add) + { +- return vfmasq (a, b, c); ++ return vfmasq (m1, m2, add); ++} ++ ++/* ++**foo2: ++** ... ++** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t m1, float32x4_t m2) ++{ ++ return vfmasq (m1, m2, 1.1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfmas.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c +index 32475013fd4..607668ebc47 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfms.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16x8_t c) ++foo (float16x8_t add, float16x8_t m1, float16x8_t m2) + { +- return vfmsq_f16 (a, b, c); ++ return vfmsq_f16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfms.f16" } } */ + ++/* ++**foo1: ++** ... ++** vfms.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16x8_t c) ++foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2) + { +- return vfmsq (a, b, c); ++ return vfmsq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfms.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c +index fbdabd188d5..ac18e9e3d9c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vfms.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32x4_t c) ++foo (float32x4_t add, float32x4_t m1, float32x4_t m2) + { +- return vfmsq_f32 (a, b, c); ++ return vfmsq_f32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vfms.f32" } } */ + ++/* ++**foo1: ++** ... ++** vfms.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32x4_t c) ++foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2) + { +- return vfmsq (a, b, c); ++ return vfmsq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vfms.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c +index ccbbfc1606c..f530e0b0614 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmst.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) ++foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p) + { +- return vfmsq_m_f16 (a, b, c, p); ++ return vfmsq_m_f16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmst.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmst.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p) ++foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p) + { +- return vfmsq_m (a, b, c, p); ++ return vfmsq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmst.f16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c +index 219492a2ad9..6faca5a2e84 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmst.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) ++foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p) + { +- return vfmsq_m_f32 (a, b, c, p); ++ return vfmsq_m_f32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmst.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vfmst.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p) ++foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p) + { +- return vfmsq_m (a, b, c, p); ++ return vfmsq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vfmst.f32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c +index e90af963697..dbcc3b3aec2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vhaddq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c +index fcce85fd1bd..134409e8f09 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vhaddq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c +index 56558b7033a..fb295f2d245 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vhaddq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c +index d7ee0febab9..2ed1262e5ec 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vhaddq_m_n_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) ++{ ++ return vhaddq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c +index 1117b9813ce..852fe64cf8e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vhaddq_m_n_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) ++{ ++ return vhaddq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c +index 90c66595d3f..5700f7ec818 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vhaddq_m_n_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) ++{ ++ return vhaddq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c +index e8b87283a73..fce31dada68 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhaddq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c +index ddcfd11198e..dbc1b835482 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhaddq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c +index ef5fcd02cc5..32e6bebf8ba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhaddq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c +index d7b9aaab62c..d824bd3d39a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vhaddq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c +index c8d7f6c4cf3..5f033d255f4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vhaddq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c +index 9792941b091..f3ea63f75b4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vhaddq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c +index d0d77f5a7fd..31f78b30ed8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b) + { + return vhaddq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c +index a8b4f3415a1..77c0521161c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vhaddq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c +index 2459ba0a7ab..1cf93d50379 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b) + { + return vhaddq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c +index cd681e7a5f9..98d80e42da9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b) + { + return vhaddq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u16" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u16" } } */ ++/* ++**foo2: ++** ... ++** vhadd.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a) ++{ ++ return vhaddq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c +index d2cb7f6284e..9b7e611c0e5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b) + { + return vhaddq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u32" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u32" } } */ ++/* ++**foo2: ++** ... ++** vhadd.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a) ++{ ++ return vhaddq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c +index 509e1746259..4d82970e7ec 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b) + { + return vhaddq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u8" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u8" } } */ ++/* ++**foo2: ++** ... ++** vhadd.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a) ++{ ++ return vhaddq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c +index 47afc591cdb..2788eb2f8ff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vhaddq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c +index fdc6476d0ee..67872a77076 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vhaddq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c +index 3321765e909..1ec890591ad 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vhaddq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c +index ad46355feab..bc84618b036 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vhaddq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u16" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c +index 7477585fe55..6abdfce981f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vhaddq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u32" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c +index 9edf8e5eb90..0c68c68206b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vhaddq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u8" } } */ + ++/* ++**foo1: ++** ... ++** vhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vhadd.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c +index 5a9302129c7..d5bff94a46e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vhaddq_x_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c +index 0a4ef00afa1..af3e219b3f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vhaddq_x_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c +index ae6c27a8878..a4551e207c2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vhaddq_x_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c +index ddc99a82f79..71facc46ad9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vhaddq_x_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vhaddq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c +index dce9bc212e2..d45421c76d7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vhaddq_x_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vhaddq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c +index 262c5937a91..5f16fbd9121 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vhaddq_x_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vhaddq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c +index 65df0093401..4e332733459 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhaddq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c +index 7ff76e7170a..5cdfd3921a5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhaddq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c +index 23f545c45cd..7a2ed232f29 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhaddq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c +index 97674c1f73c..e24ff1668db 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vhaddq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c +index b6404ce9d17..e9f13956b96 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vhaddq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c +index 7c2d74a2662..cba0a302e2a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vhaddq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c +index f4a1311980a..7e39b75a7bf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c +index 4697eb25458..57096076913 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c +index ff547e83588..d47a99e29a8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot270_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c +index 75346b2e349..01324c003c7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vhcaddq_rot270_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vhcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c +index 0d458f100af..344d1ebf4a7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vhcaddq_rot270_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vhcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c +index 5106bb7d45b..0ee4cfb4095 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vhcaddq_rot270_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vhcaddq_rot270 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c +index 73f4784cd35..c3e70ad9e2a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c +index 69c7cb7b0e6..6f14d2af44d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c +index df4aff74bff..32bfb6cf3bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot270_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c +index 5461fc26741..a7a870e78df 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c +index 20d2711aadb..1e6ef8f9aaa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c +index 55475753512..147d647d27f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot90_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c +index 539f9b00bd2..76747d669bb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vhcaddq_rot90_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vhcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c +index 841c5294253..8b9b8ad7aa9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vhcaddq_rot90_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vhcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c +index d2992c2f280..5e9b004f7cc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vhcaddq_rot90_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vhcaddq_rot90 (a, b); + } + +-/* { dg-final { scan-assembler "vhcadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c +index 0d677f7f149..d3416d65658 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c +index a54af77440f..b0255e5141c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c +index 5205cd37deb..10f5f31f26e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhcaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhcaddq_rot90_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c +index 27dcb7be957..0f9eb59646f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vhsubq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c +index 75ae735f30d..5b41bf193b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vhsubq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c +index 84cdeb42952..48e88781ce3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vhsubq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c +index bc6610c3812..3d7314673b7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vhsubq_m_n_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) ++{ ++ return vhsubq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c +index e94bfc95027..f6509a5472e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vhsubq_m_n_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) ++{ ++ return vhsubq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c +index c2a5674afd1..db75b389138 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vhsubq_m_n_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) ++{ ++ return vhsubq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c +index 9f62a385554..d8f3f3c9504 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhsubq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c +index 486ae6b7d58..94252c80324 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhsubq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c +index 9faaa4fbb0d..d4f6c247503 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhsubq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c +index aa5838cdad2..a921ba6ab51 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vhsubq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c +index 00282ad6444..73a544f9147 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vhsubq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c +index 187d5bcf8a1..fd2aa22de0e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vhsubq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vhsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c +index ce766486aed..4d1bab9641e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b) + { + return vhsubq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s16" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c +index 1d820ffaf5a..8effffaf377 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vhsubq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s32" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c +index 90110b78f0d..f55cd8f5528 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b) + { + return vhsubq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s8" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c +index e744ef58663..73575a401c5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b) + { + return vhsubq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u16" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u16" } } */ ++/* ++**foo2: ++** ... ++** vhsub.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a) ++{ ++ return vhsubq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c +index b1ce3f07904..f152ef10a9d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b) + { + return vhsubq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u32" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u32" } } */ ++/* ++**foo2: ++** ... ++** vhsub.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a) ++{ ++ return vhsubq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c +index 68872a8f900..0a58b1ed355 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b) + { + return vhsubq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u8" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u8" } } */ ++/* ++**foo2: ++** ... ++** vhsub.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a) ++{ ++ return vhsubq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c +index 03bd6d595cb..ec8d9aaed0d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vhsubq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s16" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c +index 515acb84e66..e98635a8c11 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vhsubq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s32" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c +index 41fb2589924..3107bb55844 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vhsubq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s8" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c +index dda18779dca..783309fdbed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vhsubq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u16" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c +index 86a5576bedf..99bc278d16f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vhsubq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u32" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c +index d339ca0e5e4..ae186512b78 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vhsub.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vhsubq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u8" } } */ + ++/* ++**foo1: ++** ... ++** vhsub.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vhsubq (a, b); + } + +-/* { dg-final { scan-assembler "vhsub.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c +index 09da5c2f040..260ba9ee509 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vhsubq_x_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c +index f3c032987bc..be5cc04c2b4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vhsubq_x_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c +index 1d86f7d72b3..b0c28be7872 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vhsubq_x_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c +index df6b7ea427a..f31bb3fa632 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vhsubq_x_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vhsubq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c +index bea6f2d1f96..a35346d9b2e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vhsubq_x_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vhsubq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c +index e1fafd7a9f5..25c85449081 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vhsubq_x_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vhsubq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c +index c9d3ffb45b7..dc3433cb81a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhsubq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c +index 36343cffc85..a1e1faeacb5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhsubq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c +index d1b134fe480..bbfce818be4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhsubq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c +index 4da0fb3f340..86fc9d7cf33 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vhsubq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c +index dfb0a6d371f..53274267515 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vhsubq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c +index d549892ef8b..04d89c6c6bd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vhsubq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vhsubt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vhsubt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vhsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c +index 822d41197e6..397be9f3e1e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p) + { +- return vidupq_m_n_u16 (inactive, a, 4, p); ++ return vidupq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p) + { +- return vidupq_m (inactive, a, 4, p); ++ return vidupq_m (inactive, a, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, mve_pred16_t p) ++{ ++ return vidupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c +index c01826e15dc..02b38cc6415 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p) + { + return vidupq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p) + { + return vidupq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, mve_pred16_t p) ++{ ++ return vidupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c +index e269665813c..f44aa21f324 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p) + { + return vidupq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p) + { + return vidupq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, mve_pred16_t p) ++{ ++ return vidupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c +index 8d21bc7db80..19d04601809 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) + { +- return vidupq_m_wb_u16 (inactive, a, 4, p); ++ return vidupq_m_wb_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) + { +- return vidupq_m (inactive, a, 4, p); ++ return vidupq_m (inactive, a, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, mve_pred16_t p) ++{ ++ return vidupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c +index e7bc06cd826..36a8ac30564 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) + { + return vidupq_m_wb_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) + { + return vidupq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, mve_pred16_t p) ++{ ++ return vidupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c +index a8a2f9a1c49..75695304c65 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) + { + return vidupq_m_wb_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) + { + return vidupq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, mve_pred16_t p) ++{ ++ return vidupq_m (inactive, 1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c +index c59ca1ebf74..6b5d8815e1d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t a) + { +- return vidupq_n_u16 (a, 4); ++ return vidupq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u16" } } */ + ++/* ++**foo1: ++** ... ++** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t a) + { +- return vidupq_u16 (a, 4); ++ return vidupq_u16 (a, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 () ++{ ++ return vidupq_u16 (1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vidup.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c +index 7e835e0868c..0b829a43a10 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a) + { + return vidupq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u32" } } */ + ++/* ++**foo1: ++** ... ++** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t a) + { + return vidupq_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u32" } } */ ++/* ++**foo2: ++** ... ++** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 () ++{ ++ return vidupq_u32 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c +index 06d1a1a1480..12523757737 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t a) + { + return vidupq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u8" } } */ + ++/* ++**foo1: ++** ... ++** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t a) + { + return vidupq_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u8" } } */ ++/* ++**foo2: ++** ... ++** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 () ++{ ++ return vidupq_u8 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c +index 1cb0ded198f..83d9cc2a563 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t *a) + { +- return vidupq_wb_u16 (a, 4); ++ return vidupq_wb_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u16" } } */ + ++/* ++**foo1: ++** ... ++** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t *a) + { +- return vidupq_u16 (a, 4); ++ return vidupq_u16 (a, 1); ++} ++ ++/* ++**foo2: ++** ... ++** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 () ++{ ++ return vidupq_u16 (1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vidup.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c +index e5d9c5327fb..d73face505d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t *a) + { + return vidupq_wb_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u32" } } */ + ++/* ++**foo1: ++** ... ++** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t *a) + { + return vidupq_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u32" } } */ ++/* ++**foo2: ++** ... ++** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 () ++{ ++ return vidupq_u32 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c +index 57e1bb46776..75187b0eb25 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t *a) + { + return vidupq_wb_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u8" } } */ + ++/* ++**foo1: ++** ... ++** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t *a) + { + return vidupq_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vidup.u8" } } */ ++/* ++**foo2: ++** ... ++** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 () ++{ ++ return vidupq_u8 (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c +index bdf8ec2b047..5df5035e340 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t a, mve_pred16_t p) + { +- return vidupq_x_n_u16 (a, 4, p); ++ return vidupq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t a, mve_pred16_t p) + { +- return vidupq_x_u16 (a, 4, p); ++ return vidupq_x_u16 (a, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (mve_pred16_t p) ++{ ++ return vidupq_x_u16 (1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c +index 8be549cb446..02c6d7784dc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a, mve_pred16_t p) + { + return vidupq_x_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t a, mve_pred16_t p) + { + return vidupq_x_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (mve_pred16_t p) ++{ ++ return vidupq_x_u32 (1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c +index 1e1975017de..3a1d3c0317f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t a, mve_pred16_t p) + { + return vidupq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t a, mve_pred16_t p) + { + return vidupq_x_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (mve_pred16_t p) ++{ ++ return vidupq_x_u8 (1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c +index 31197a76cfa..31ddde4bd3a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c +@@ -1,25 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-uint32_t *a; ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (mve_pred16_t p) ++foo (uint32_t *a, mve_pred16_t p) + { +- return vidupq_x_wb_u16 (a, 8, p); ++ return vidupq_x_wb_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (mve_pred16_t p) ++foo1 (uint32_t *a, mve_pred16_t p) + { +- return vidupq_x_u16 (a, 8, p); ++ return vidupq_x_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (mve_pred16_t p) ++{ ++ return vidupq_x_u16 (1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c +index cef56f133e8..c8193465a72 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c +@@ -1,25 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-uint32_t *a; ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (mve_pred16_t p) ++foo (uint32_t *a, mve_pred16_t p) + { +- return vidupq_x_wb_u32 (a, 2, p); ++ return vidupq_x_wb_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (mve_pred16_t p) ++foo1 (uint32_t *a, mve_pred16_t p) + { +- return vidupq_x_u32 (a, 2, p); ++ return vidupq_x_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (mve_pred16_t p) ++{ ++ return vidupq_x_u32 (1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c +index 0403ba1174c..f7a628990c9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c +@@ -1,25 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-uint32_t * a; ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (mve_pred16_t p) ++foo (uint32_t *a, mve_pred16_t p) + { +- return vidupq_x_wb_u8 (a, 2, p); ++ return vidupq_x_wb_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (mve_pred16_t p) ++foo1 (uint32_t *a, mve_pred16_t p) + { +- return vidupq_x_u8 (a, 2, p); ++ return vidupq_x_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vidupt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (mve_pred16_t p) ++{ ++ return vidupq_x_u8 (1, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c +index 0f999cc672b..d96a89017e6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m_n_u16 (inactive, a, b, 2, p); ++ return viwdupq_m_n_u16 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m (inactive, a, b, 2, p); ++ return viwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, mve_pred16_t p) ++{ ++ return viwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c +index f79c91eaf4c..ca1ac6ebe24 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m_n_u32 (inactive, a, b, 4, p); ++ return viwdupq_m_n_u32 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m (inactive, a, b, 4, p); ++ return viwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, mve_pred16_t p) ++{ ++ return viwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c +index c0fee9fa752..9590e023335 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m_n_u8 (inactive, a, b, 8, p); ++ return viwdupq_m_n_u8 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m (inactive, a, b, 8, p); ++ return viwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, mve_pred16_t p) ++{ ++ return viwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c +index 468ba179f62..84733f94e7c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m_wb_u16 (inactive, a, b, 2, p); ++ return viwdupq_m_wb_u16 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m (inactive, a, b, 2, p); ++ return viwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, mve_pred16_t p) ++{ ++ return viwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c +index e9190302717..a175744b654 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m_wb_u32 (inactive, a, b, 4, p); ++ return viwdupq_m_wb_u32 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m (inactive, a, b, 4, p); ++ return viwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, mve_pred16_t p) ++{ ++ return viwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c +index 309ce95a333..7240b6e72bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m_wb_u8 (inactive, a, b, 8, p); ++ return viwdupq_m_wb_u8 (inactive, a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_m (inactive, a, b, 8, p); ++ return viwdupq_m (inactive, a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, mve_pred16_t p) ++{ ++ return viwdupq_m (inactive, 1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c +index 599d9078464..a5eb3094d44 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** viwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t a, uint32_t b) + { +- return viwdupq_n_u16 (a, b, 2); ++ return viwdupq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "viwdup.u16" } } */ + ++/* ++**foo1: ++** ... ++** viwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t a, uint32_t b) + { +- return viwdupq_u16 (a, b, 2); ++ return viwdupq_u16 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** viwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 () ++{ ++ return viwdupq_u16 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "viwdup.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c +index 7c2af74b3f0..63f6bdf52b1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** viwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a, uint32_t b) + { +- return viwdupq_n_u32 (a, b, 4); ++ return viwdupq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "viwdup.u32" } } */ + ++/* ++**foo1: ++** ... ++** viwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t a, uint32_t b) + { +- return viwdupq_u32 (a, b, 4); ++ return viwdupq_u32 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** viwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 () ++{ ++ return viwdupq_u32 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "viwdup.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c +index 4ff60791f3b..65d1062ac96 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** viwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t a, uint32_t b) + { + return viwdupq_n_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "viwdup.u8" } } */ + ++/* ++**foo1: ++** ... ++** viwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t a, uint32_t b) + { + return viwdupq_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "viwdup.u8" } } */ ++/* ++**foo2: ++** ... ++** viwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 () ++{ ++ return viwdupq_u8 (1, 1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c +index 1e5ce88dcca..eaa496bb2da 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** viwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint32_t * a, uint32_t b) ++foo (uint32_t *a, uint32_t b) + { +- return viwdupq_wb_u16 (a, b, 4); ++ return viwdupq_wb_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "viwdup.u16" } } */ + ++/* ++**foo1: ++** ... ++** viwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint32_t * a, uint32_t b) ++foo1 (uint32_t *a, uint32_t b) + { +- return viwdupq_u16 (a, b, 4); ++ return viwdupq_u16 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** viwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 () ++{ ++ return viwdupq_u16 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "viwdup.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c +index 0c076f7b751..c1912d77486 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** viwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t * a, uint32_t b) ++foo (uint32_t *a, uint32_t b) + { +- return viwdupq_wb_u32 (a, b, 8); ++ return viwdupq_wb_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "viwdup.u32" } } */ + ++/* ++**foo1: ++** ... ++** viwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t * a, uint32_t b) ++foo1 (uint32_t *a, uint32_t b) + { +- return viwdupq_u32 (a, b, 8); ++ return viwdupq_u32 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** viwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 () ++{ ++ return viwdupq_u32 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "viwdup.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c +index 9e5118ba2b6..f0d66a9ba29 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** viwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint32_t * a, uint32_t b) ++foo (uint32_t *a, uint32_t b) + { +- return viwdupq_wb_u8 (a, b, 2); ++ return viwdupq_wb_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "viwdup.u8" } } */ + ++/* ++**foo1: ++** ... ++** viwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint32_t * a, uint32_t b) ++foo1 (uint32_t *a, uint32_t b) + { +- return viwdupq_u8 (a, b, 2); ++ return viwdupq_u8 (a, b, 1); ++} ++ ++/* ++**foo2: ++** ... ++** viwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 () ++{ ++ return viwdupq_u8 (1, 1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "viwdup.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c +index fdaf6be282d..7f8cc38e4c2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_n_u16 (a, b, 2, p); ++ return viwdupq_x_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_u16 (a, b, 2, p); ++ return viwdupq_x_u16 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (mve_pred16_t p) ++{ ++ return viwdupq_x_u16 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c +index affc6162015..f97b599373c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_n_u32 (a, b, 4, p); ++ return viwdupq_x_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_u32 (a, b, 4, p); ++ return viwdupq_x_u32 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (mve_pred16_t p) ++{ ++ return viwdupq_x_u32 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c +index 8137c623c2a..c0ceead5267 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_n_u8 (a, b, 8, p); ++ return viwdupq_x_n_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint32_t a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_u8 (a, b, 8, p); ++ return viwdupq_x_u8 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (mve_pred16_t p) ++{ ++ return viwdupq_x_u8 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c +index d7aa141f384..265aef42c92 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_wb_u16 (a, b, 8, p); ++ return viwdupq_x_wb_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_u16 (a, b, 8, p); ++ return viwdupq_x_u16 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (mve_pred16_t p) ++{ ++ return viwdupq_x_u16 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c +index 7fe56963452..585e41075db 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_wb_u32 (a, b, 2, p); ++ return viwdupq_x_wb_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_u32 (a, b, 2, p); ++ return viwdupq_x_u32 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (mve_pred16_t p) ++{ ++ return viwdupq_x_u32 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c +index 8e3ecefdedb..ca39081dfc5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_wb_u8 (a, b, 4, p); ++ return viwdupq_x_wb_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) ++foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) + { +- return viwdupq_x_u8 (a, b, 4, p); ++ return viwdupq_x_u8 (a, b, 1, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** viwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (mve_pred16_t p) ++{ ++ return viwdupq_x_u8 (1, 1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "viwdupt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c +index 699e40d0e3b..f0a9243a6d5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base) ++foo (float16_t const *base) + { + return vld1q_f16 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base) ++foo1 (float16_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c +index 86592303362..129d256dd86 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base) ++foo (float32_t const *base) + { + return vld1q_f32 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base) ++foo1 (float32_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c +index f4f04f534db..a95bf6c4260 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base) ++foo (int16_t const *base) + { + return vld1q_s16 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base) ++foo1 (int16_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c +index e0f66166751..bb24e52d164 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base) ++foo (int32_t const *base) + { + return vld1q_s32 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base) ++foo1 (int32_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c +index 1b7edead6b1..0d89c2f19cd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base) ++foo (int8_t const *base) + { + return vld1q_s8 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8_t const * base) ++foo1 (int8_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c +index 50e1f5cedcb..a31baf75fed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base) ++foo (uint16_t const *base) + { + return vld1q_u16 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base) ++foo1 (uint16_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c +index a13fe824382..7d4f858c784 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base) ++foo (uint32_t const *base) + { + return vld1q_u32 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base) ++foo1 (uint32_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c +index dfd1deb93f0..455ec5ce105 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c +@@ -1,20 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base) ++foo (uint8_t const *base) + { + return vld1q_u8 (base); + } + ++ ++/* ++**foo1: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8_t const * base) ++foo1 (uint8_t const *base) + { + return vld1q (base); + } + +-/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c +index 3c32e408e42..951b795fd59 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, mve_pred16_t p) ++foo (float16_t const *base, mve_pred16_t p) + { + return vld1q_z_f16 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, mve_pred16_t p) ++foo1 (float16_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c +index 3fc935c889b..4b43f0f4be3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, mve_pred16_t p) ++foo (float32_t const *base, mve_pred16_t p) + { + return vld1q_z_f32 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, mve_pred16_t p) ++foo1 (float32_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c +index 49cc81092f3..a65c10c5fc1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, mve_pred16_t p) ++foo (int16_t const *base, mve_pred16_t p) + { + return vld1q_z_s16 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, mve_pred16_t p) ++foo1 (int16_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c +index ec317cd70e8..31749046fc6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, mve_pred16_t p) ++foo (int32_t const *base, mve_pred16_t p) + { + return vld1q_z_s32 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, mve_pred16_t p) ++foo1 (int32_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c +index 538c140e78e..990522faee8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base, mve_pred16_t p) ++foo (int8_t const *base, mve_pred16_t p) + { + return vld1q_z_s8 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8_t const * base, mve_pred16_t p) ++foo1 (int8_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c +index e5e588a187e..8a41b42306c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, mve_pred16_t p) ++foo (uint16_t const *base, mve_pred16_t p) + { + return vld1q_z_u16 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, mve_pred16_t p) ++foo1 (uint16_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c +index 999beefa7e8..67b200f6028 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, mve_pred16_t p) ++foo (uint32_t const *base, mve_pred16_t p) + { + return vld1q_z_u32 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, mve_pred16_t p) ++foo1 (uint32_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c +index 172053c7142..c113a0db3e1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base, mve_pred16_t p) ++foo (uint8_t const *base, mve_pred16_t p) + { + return vld1q_z_u8 (base, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8_t const * base, mve_pred16_t p) ++foo1 (uint8_t const *base, mve_pred16_t p) + { + return vld1q_z (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 2 } } */ +-/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c +index 24e7a2ea4d0..81690b1022e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8x2_t +-foo (float16_t const * addr) ++foo (float16_t const *addr) + { + return vld2q_f16 (addr); + } + +-/* { dg-final { scan-assembler "vld20.16" } } */ +-/* { dg-final { scan-assembler "vld21.16" } } */ + ++/* ++**foo1: ++** ... ++** vld20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8x2_t +-foo1 (float16_t const * addr) ++foo1 (float16_t const *addr) + { + return vld2q (addr); + } + +-/* { dg-final { scan-assembler "vld20.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c +index 727484caaf6..d2ae31fa9e5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4x2_t +-foo (float32_t const * addr) ++foo (float32_t const *addr) + { + return vld2q_f32 (addr); + } + +-/* { dg-final { scan-assembler "vld20.32" } } */ +-/* { dg-final { scan-assembler "vld21.32" } } */ + ++/* ++**foo1: ++** ... ++** vld20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4x2_t +-foo1 (float32_t const * addr) ++foo1 (float32_t const *addr) + { + return vld2q (addr); + } + +-/* { dg-final { scan-assembler "vld20.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c +index f2864a00478..fb4dc1b4fcf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8x2_t +-foo (int16_t const * addr) ++foo (int16_t const *addr) + { + return vld2q_s16 (addr); + } + +-/* { dg-final { scan-assembler "vld20.16" } } */ +-/* { dg-final { scan-assembler "vld21.16" } } */ + ++/* ++**foo1: ++** ... ++** vld20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8x2_t +-foo1 (int16_t const * addr) ++foo1 (int16_t const *addr) + { + return vld2q (addr); + } + +-/* { dg-final { scan-assembler "vld20.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c +index 9fe2e0459b5..aeb85238fd2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4x2_t +-foo (int32_t const * addr) ++foo (int32_t const *addr) + { + return vld2q_s32 (addr); + } + +-/* { dg-final { scan-assembler "vld20.32" } } */ +-/* { dg-final { scan-assembler "vld21.32" } } */ + ++/* ++**foo1: ++** ... ++** vld20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4x2_t +-foo1 (int32_t const * addr) ++foo1 (int32_t const *addr) + { + return vld2q (addr); + } + +-/* { dg-final { scan-assembler "vld20.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c +index 736080a94a7..687e5ded48c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16x2_t +-foo (int8_t const * addr) ++foo (int8_t const *addr) + { + return vld2q_s8 (addr); + } + +-/* { dg-final { scan-assembler "vld20.8" } } */ +-/* { dg-final { scan-assembler "vld21.8" } } */ + ++/* ++**foo1: ++** ... ++** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16x2_t +-foo1 (int8_t const * addr) ++foo1 (int8_t const *addr) + { + return vld2q (addr); + } + +-/* { dg-final { scan-assembler "vld20.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c +index 2d89ebdcf6b..281fe5eaf10 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8x2_t +-foo (uint16_t const * addr) ++foo (uint16_t const *addr) + { + return vld2q_u16 (addr); + } + +-/* { dg-final { scan-assembler "vld20.16" } } */ +-/* { dg-final { scan-assembler "vld21.16" } } */ + ++/* ++**foo1: ++** ... ++** vld20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8x2_t +-foo1 (uint16_t const * addr) ++foo1 (uint16_t const *addr) + { + return vld2q (addr); + } + +-/* { dg-final { scan-assembler "vld20.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c +index 28d311eca68..524afee72e9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4x2_t +-foo (uint32_t const * addr) ++foo (uint32_t const *addr) + { + return vld2q_u32 (addr); + } + +-/* { dg-final { scan-assembler "vld20.32" } } */ +-/* { dg-final { scan-assembler "vld21.32" } } */ + ++/* ++**foo1: ++** ... ++** vld20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4x2_t +-foo1 (uint32_t const * addr) ++foo1 (uint32_t const *addr) + { + return vld2q (addr); + } + +-/* { dg-final { scan-assembler "vld20.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c +index 790c9743c9a..9eebbd42719 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16x2_t +-foo (uint8_t const * addr) ++foo (uint8_t const *addr) + { + return vld2q_u8 (addr); + } + +-/* { dg-final { scan-assembler "vld20.8" } } */ +-/* { dg-final { scan-assembler "vld21.8" } } */ + ++/* ++**foo1: ++** ... ++** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16x2_t +-foo1 (uint8_t const * addr) ++foo1 (uint8_t const *addr) + { + return vld2q (addr); + } + +-/* { dg-final { scan-assembler "vld20.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c +index db50f27bb60..e554cdab33d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + float16x8x4_t +-foo (float16_t const * addr) ++foo (float16_t const *addr) + { + return vld4q_f16 (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ +-/* { dg-final { scan-assembler "vld41.16" } } */ +-/* { dg-final { scan-assembler "vld42.16" } } */ +-/* { dg-final { scan-assembler "vld43.16" } } */ + ++/* ++**foo1: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + float16x8x4_t +-foo1 (float16_t const * addr) ++foo1 (float16_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c +index de3fe0e79fc..be61054d331 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + float32x4x4_t +-foo (float32_t const * addr) ++foo (float32_t const *addr) + { + return vld4q_f32 (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ +-/* { dg-final { scan-assembler "vld41.32" } } */ +-/* { dg-final { scan-assembler "vld42.32" } } */ +-/* { dg-final { scan-assembler "vld43.32" } } */ + ++/* ++**foo1: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + float32x4x4_t +-foo1 (float32_t const * addr) ++foo1 (float32_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c +index 41a9dd86a4f..f9cbc17da61 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int16x8x4_t +-foo (int16_t const * addr) ++foo (int16_t const *addr) + { + return vld4q_s16 (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ +-/* { dg-final { scan-assembler "vld41.16" } } */ +-/* { dg-final { scan-assembler "vld42.16" } } */ +-/* { dg-final { scan-assembler "vld43.16" } } */ + ++/* ++**foo1: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int16x8x4_t +-foo1 (int16_t const * addr) ++foo1 (int16_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c +index 6f29c1b28c0..056e26023a9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int32x4x4_t +-foo (int32_t const * addr) ++foo (int32_t const *addr) + { + return vld4q_s32 (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ +-/* { dg-final { scan-assembler "vld41.32" } } */ +-/* { dg-final { scan-assembler "vld42.32" } } */ +-/* { dg-final { scan-assembler "vld43.32" } } */ + ++/* ++**foo1: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int32x4x4_t +-foo1 (int32_t const * addr) ++foo1 (int32_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c +index 7701facb55c..2bec51ab4f6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int8x16x4_t +-foo (int8_t const * addr) ++foo (int8_t const *addr) + { + return vld4q_s8 (addr); + } + +-/* { dg-final { scan-assembler "vld40.8" } } */ +-/* { dg-final { scan-assembler "vld41.8" } } */ +-/* { dg-final { scan-assembler "vld42.8" } } */ +-/* { dg-final { scan-assembler "vld43.8" } } */ + ++/* ++**foo1: ++** ... ++** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + int8x16x4_t +-foo1 (int8_t const * addr) ++foo1 (int8_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c +index 5a5e22d36d0..a2c98670174 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint16x8x4_t +-foo (uint16_t const * addr) ++foo (uint16_t const *addr) + { + return vld4q_u16 (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ +-/* { dg-final { scan-assembler "vld41.16" } } */ +-/* { dg-final { scan-assembler "vld42.16" } } */ +-/* { dg-final { scan-assembler "vld43.16" } } */ + ++/* ++**foo1: ++** ... ++** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint16x8x4_t +-foo1 (uint16_t const * addr) ++foo1 (uint16_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c +index e40d9b24fb4..4bbe56db205 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint32x4x4_t +-foo (uint32_t const * addr) ++foo (uint32_t const *addr) + { + return vld4q_u32 (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ +-/* { dg-final { scan-assembler "vld41.32" } } */ +-/* { dg-final { scan-assembler "vld42.32" } } */ +-/* { dg-final { scan-assembler "vld43.32" } } */ + ++/* ++**foo1: ++** ... ++** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint32x4x4_t +-foo1 (uint32_t const * addr) ++foo1 (uint32_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c +index 0d9abc36190..63353dba4b6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c +@@ -1,24 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint8x16x4_t +-foo (uint8_t const * addr) ++foo (uint8_t const *addr) + { + return vld4q_u8 (addr); + } + +-/* { dg-final { scan-assembler "vld40.8" } } */ +-/* { dg-final { scan-assembler "vld41.8" } } */ +-/* { dg-final { scan-assembler "vld42.8" } } */ +-/* { dg-final { scan-assembler "vld43.8" } } */ + ++/* ++**foo1: ++** ... ++** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + uint8x16x4_t +-foo1 (uint8_t const * addr) ++foo1 (uint8_t const *addr) + { + return vld4q (addr); + } + +-/* { dg-final { scan-assembler "vld40.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c +index 0f6c24dde0a..ce4255b8430 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int8_t const * base, uint16x8_t offset) ++foo (int8_t const *base, uint16x8_t offset) + { + return vldrbq_gather_offset_s16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int8_t const * base, uint16x8_t offset) ++foo1 (int8_t const *base, uint16x8_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c +index 4c1415d2c5f..cd5eb6b9e66 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int8_t const * base, uint32x4_t offset) ++foo (int8_t const *base, uint32x4_t offset) + { + return vldrbq_gather_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int8_t const * base, uint32x4_t offset) ++foo1 (int8_t const *base, uint32x4_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c +index 4108bbae3e2..5ef4a895082 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base, uint8x16_t offset) ++foo (int8_t const *base, uint8x16_t offset) + { + return vldrbq_gather_offset_s8 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u8" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8_t const * base, uint8x16_t offset) ++foo1 (int8_t const *base, uint8x16_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c +index 5d5b005a8f4..cfec3c66a54 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint8_t const * base, uint16x8_t offset) ++foo (uint8_t const *base, uint16x8_t offset) + { + return vldrbq_gather_offset_u16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint8_t const * base, uint16x8_t offset) ++foo1 (uint8_t const *base, uint16x8_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c +index 7c2d92b7c58..f416a03c325 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint8_t const * base, uint32x4_t offset) ++foo (uint8_t const *base, uint32x4_t offset) + { + return vldrbq_gather_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint8_t const * base, uint32x4_t offset) ++foo1 (uint8_t const *base, uint32x4_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c +index 110f9db0296..e8bdd1eabb6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base, uint8x16_t offset) ++foo (uint8_t const *base, uint8x16_t offset) + { + return vldrbq_gather_offset_u8 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u8" } } */ + ++/* ++**foo1: ++** ... ++** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8_t const * base, uint8x16_t offset) ++foo1 (uint8_t const *base, uint8x16_t offset) + { + return vldrbq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrb.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c +index f0616b5ab8d..9a134609780 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (int8_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_s16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (int8_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c +index 5bf291d4ba5..f47e02076b2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int8_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int8_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c +index a3798a01b5f..e2b58b47f1d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p) ++foo (int8_t const *base, uint8x16_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_s8 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p) ++foo1 (int8_t const *base, uint8x16_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c +index 578bd15c66e..2a1801fc941 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (uint8_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_u16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (uint8_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c +index a58044af176..c415fe26ba8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint8_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint8_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c +index 0e06833961b..90a19680999 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) ++foo (uint8_t const *base, uint8x16_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z_u8 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p) ++foo1 (uint8_t const *base, uint8x16_t offset, mve_pred16_t p) + { + return vldrbq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c +index 4403092b988..c54e04dbdda 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int8_t const * base) ++foo (int8_t const *base) + { + return vldrbq_s16 (base); + } + +-/* { dg-final { scan-assembler "vldrb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c +index 95ea9364ffc..1623f53d971 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int8_t const * base) ++foo (int8_t const *base) + { + return vldrbq_s32 (base); + } + +-/* { dg-final { scan-assembler "vldrb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c +index ec2f2176ccf..b1c141ae287 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base) ++foo (int8_t const *base) + { + return vldrbq_s8 (base); + } + +-/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c +index 2fb297f92ad..203e2e9de83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint8_t const * base) ++foo (uint8_t const *base) + { + return vldrbq_u16 (base); + } + +-/* { dg-final { scan-assembler "vldrb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c +index dc555c1be2d..2005c3a2bbf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint8_t const * base) ++foo (uint8_t const *base) + { + return vldrbq_u32 (base); + } + +-/* { dg-final { scan-assembler "vldrb.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c +index d07b472a4ff..b4c109eb147 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base) ++foo (uint8_t const *base) + { + return vldrbq_u8 (base); + } + +-/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c +index 8bd08ab5cff..813f6a31a25 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int8_t const * base, mve_pred16_t p) ++foo (int8_t const *base, mve_pred16_t p) + { + return vldrbq_z_s16 (base, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c +index 0309ff4111b..10e1dbf6ad9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int8_t const * base, mve_pred16_t p) ++foo (int8_t const *base, mve_pred16_t p) + { + return vldrbq_z_s32 (base, p); + } + +-/* { dg-final { scan-assembler "vldrbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c +index aed3c910063..de361d4c9a0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8_t const * base, mve_pred16_t p) ++foo (int8_t const *base, mve_pred16_t p) + { + return vldrbq_z_s8 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c +index adcb0cfa2ae..ba4401045e7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint8_t const * base, mve_pred16_t p) ++foo (uint8_t const *base, mve_pred16_t p) + { + return vldrbq_z_u16 (base, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c +index 6b7bce60d62..adc88a59a71 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint8_t const * base, mve_pred16_t p) ++foo (uint8_t const *base, mve_pred16_t p) + { + return vldrbq_z_u32 (base, p); + } + +-/* { dg-final { scan-assembler "vldrbt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c +index 54c61e74454..b13d9fb426f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8_t const * base, mve_pred16_t p) ++foo (uint8_t const *base, mve_pred16_t p) + { + return vldrbq_z_u8 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c +index 6499f930c40..3539c1e40ba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t + foo (uint64x2_t addr) + { +- return vldrdq_gather_base_s64 (addr, 8); ++ return vldrdq_gather_base_s64 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c +index 9a11638a261..2245df61a4e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint64x2_t addr) + { +- return vldrdq_gather_base_u64 (addr, 8); ++ return vldrdq_gather_base_u64 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c +index a9b1f81b62d..e3fd7f16a31 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + int64x2_t +-foo (uint64x2_t * addr) ++foo (uint64x2_t *addr) + { +- return vldrdq_gather_base_wb_s64 (addr, 8); ++ return vldrdq_gather_base_wb_s64 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c +index e32a06695ae..161cf00b65e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64x2_t * addr) ++foo (uint64x2_t *addr) + { +- return vldrdq_gather_base_wb_u64 (addr, 8); ++ return vldrdq_gather_base_wb_u64 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c +index bb06cf88e32..0716baa635a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ + #include "arm_mve.h" + +-int64x2_t foo (uint64x2_t * addr, mve_pred16_t p) ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ ++int64x2_t ++foo (uint64x2_t *addr, mve_pred16_t p) + { +- return vldrdq_gather_base_wb_z_s64 (addr, 1016, p); ++ return vldrdq_gather_base_wb_z_s64 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c +index 558115d49ef..242c7c06e27 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ + #include "arm_mve.h" + +-uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p) ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ ++uint64x2_t ++foo (uint64x2_t *addr, mve_pred16_t p) + { +- return vldrdq_gather_base_wb_z_u64 (addr, 8, p); ++ return vldrdq_gather_base_wb_z_u64 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */ +-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c +index d7455b49206..d451f4e693f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t + foo (uint64x2_t addr, mve_pred16_t p) + { +- return vldrdq_gather_base_z_s64 (addr, 8, p); ++ return vldrdq_gather_base_z_s64 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c +index 07f72d422b4..508db3ca538 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint64x2_t addr, mve_pred16_t p) + { +- return vldrdq_gather_base_z_u64 (addr, 8, p); ++ return vldrdq_gather_base_z_u64 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c +index 1d2d904efc4..9431491f3fd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo (int64_t const * base, uint64x2_t offset) ++foo (int64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_offset_s64 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo1 (int64_t const * base, uint64x2_t offset) ++foo1 (int64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c +index 49a3b134d2f..11c0872f5a7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64_t const * base, uint64x2_t offset) ++foo (uint64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_offset_u64 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo1 (uint64_t const * base, uint64x2_t offset) ++foo1 (uint64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c +index 1ff5f2acd1b..f474cbef788 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_offset_z_s64 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c +index 63b2254d171..19136d7f451 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_offset_z_u64 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c +index 4feb9c06fcd..ad11d8fa5cb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo (int64_t const * base, uint64x2_t offset) ++foo (int64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_shifted_offset_s64 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo1 (int64_t const * base, uint64x2_t offset) ++foo1 (int64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c +index 999735039c8..a466494974b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64_t const * base, uint64x2_t offset) ++foo (uint64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_shifted_offset_u64 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo1 (uint64_t const * base, uint64x2_t offset) ++foo1 (uint64_t const *base, uint64x2_t offset) + { + return vldrdq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrd.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c +index 77303a47a08..3555105d09e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_shifted_offset_z_s64 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + int64x2_t +-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c +index 0273b242031..f7cfbfcddb3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_shifted_offset_z_u64 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + uint64x2_t +-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p) ++foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p) + { + return vldrdq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrdt.u64" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c +index 05bef418d82..87c746f4ad7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base) ++foo (float16_t const *base) + { + return vldrhq_f16 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c +index 525e54c72f5..287276e41f9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, uint16x8_t offset) ++foo (float16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset_f16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.f16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, uint16x8_t offset) ++foo1 (float16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c +index 47ef03445b4..e2493a62b3a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, uint16x8_t offset) ++foo (int16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset_s16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, uint16x8_t offset) ++foo1 (int16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c +index 39379aaedd3..5d1e348cc86 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, uint32x4_t offset) ++foo (int16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int16_t const * base, uint32x4_t offset) ++foo1 (int16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c +index fa345e24b48..6d5f6f877dc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, uint16x8_t offset) ++foo (uint16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset_u16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, uint16x8_t offset) ++foo1 (uint16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c +index b888660dc37..c39afbe6119 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, uint32x4_t offset) ++foo (uint16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint16_t const * base, uint32x4_t offset) ++foo1 (uint16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c +index 7ee84232f04..53c673e3644 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_f16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c +index 9b354fad50d..1e68a77824e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_s16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c +index 0e252291944..06c208f31c5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c +index 763e33d90bb..f50f026b00e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_u16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c +index 36baa252aa4..eff32dc6718 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c +index 843904a7041..f8468be41fa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, uint16x8_t offset) ++foo (float16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset_f16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.f16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, uint16x8_t offset) ++foo1 (float16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c +index 6d013c835b5..ac2491ea143 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, uint16x8_t offset) ++foo (int16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset_s16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, uint16x8_t offset) ++foo1 (int16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c +index 5ec8e8c1dc8..6919b3a3cc2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, uint32x4_t offset) ++foo (int16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_shifted_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int16_t const * base, uint32x4_t offset) ++foo1 (int16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c +index fa5f3d04548..7e8fdf3799d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, uint16x8_t offset) ++foo (uint16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset_u16 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, uint16x8_t offset) ++foo1 (uint16_t const *base, uint16x8_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c +index 227b18d7864..de2d22d985d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, uint32x4_t offset) ++foo (uint16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_shifted_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint16_t const * base, uint32x4_t offset) ++foo1 (uint16_t const *base, uint32x4_t offset) + { + return vldrhq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrh.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c +index cae37837c7e..a55ada003ed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_f16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c +index 1aff290a6b0..ee57d77e3db 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_s16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c +index 92ee073adf9..9f8963f56bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c +index 792510d3639..90be7020ac2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_u16 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) ++foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c +index 8ae845418e8..0ff6d021b51 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrhq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrht.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c +index 7c977b6a699..107ce22856b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base) ++foo (int16_t const *base) + { + return vldrhq_s16 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c +index 229b52163fa..5cc864c38e4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base) ++foo (int16_t const *base) + { + return vldrhq_s32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.s32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c +index 07f6d9e3944..12f807da03b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base) ++foo (uint16_t const *base) + { + return vldrhq_u16 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c +index cd24f01831f..5d4f34f9789 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base) ++foo (uint16_t const *base) + { + return vldrhq_u32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrh.u32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c +index dd0fc9c7b73..582061bbab3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float16x8_t +-foo (float16_t const * base, mve_pred16_t p) ++foo (float16_t const *base, mve_pred16_t p) + { + return vldrhq_z_f16 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c +index 36d3458d95c..dc32460ccdd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16_t const * base, mve_pred16_t p) ++foo (int16_t const *base, mve_pred16_t p) + { + return vldrhq_z_s16 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c +index 9c67b479be7..15dd77cb36c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int16_t const * base, mve_pred16_t p) ++foo (int16_t const *base, mve_pred16_t p) + { + return vldrhq_z_s32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.s32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c +index 26354b5971a..91ab2caf1c6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16_t const * base, mve_pred16_t p) ++foo (uint16_t const *base, mve_pred16_t p) + { + return vldrhq_z_u16 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c +index 948fe5ee5b4..1682ec1987a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint16_t const * base, mve_pred16_t p) ++foo (uint16_t const *base, mve_pred16_t p) + { + return vldrhq_z_u32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrht.u32" 1 } } */ +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c +index 143079aa23f..9cf47332b38 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base) ++foo (float32_t const *base) + { + return vldrwq_f32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c +index 5e0faaad8dd..c3f052efbc6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t addr) + { +- return vldrwq_gather_base_f32 (addr, 4); ++ return vldrwq_gather_base_f32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c +index 8ca44199e3e..f2dbcfb9f6e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t + foo (uint32x4_t addr) + { +- return vldrwq_gather_base_s32 (addr, 4); ++ return vldrwq_gather_base_s32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c +index 3c3e90f1c0a..0926689805f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t addr) + { +- return vldrwq_gather_base_u32 (addr, 4); ++ return vldrwq_gather_base_u32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c +index 8e2994f75d7..f9cd0a3ffe0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (uint32x4_t * addr) ++foo (uint32x4_t *addr) + { +- return vldrwq_gather_base_wb_f32 (addr, 8); ++ return vldrwq_gather_base_wb_f32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c +index e5054738b75..b8f16969a31 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (uint32x4_t * addr) ++foo (uint32x4_t *addr) + { +- return vldrwq_gather_base_wb_s32 (addr, 8); ++ return vldrwq_gather_base_wb_s32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c +index 7f39414143b..387d0115f46 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c +@@ -1,16 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t * addr) ++foo (uint32x4_t *addr) + { +- return vldrwq_gather_base_wb_u32 (addr, 8); ++ return vldrwq_gather_base_wb_u32 (addr, 0); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c +index f3219e2e825..bea7ecdee83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c +@@ -1,18 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + float32x4_t +-foo (uint32x4_t * addr, mve_pred16_t p) ++foo (uint32x4_t *addr, mve_pred16_t p) + { +- return vldrwq_gather_base_wb_z_f32 (addr, 8, p); ++ return vldrwq_gather_base_wb_z_f32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c +index 4d093d243fe..4469ac14a0a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c +@@ -1,18 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (uint32x4_t * addr, mve_pred16_t p) ++foo (uint32x4_t *addr, mve_pred16_t p) + { +- return vldrwq_gather_base_wb_z_s32 (addr, 8, p); ++ return vldrwq_gather_base_wb_z_s32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c +index e796522a49c..9d4d81b3afe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c +@@ -1,18 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t * addr, mve_pred16_t p) ++foo (uint32x4_t *addr, mve_pred16_t p) + { +- return vldrwq_gather_base_wb_z_u32 (addr, 8, p); ++ return vldrwq_gather_base_wb_z_u32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ +-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ +-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c +index 81aac523728..905000a31a8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t + foo (uint32x4_t addr, mve_pred16_t p) + { +- return vldrwq_gather_base_z_f32 (addr, 4, p); ++ return vldrwq_gather_base_z_f32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c +index fec49bbde06..3ee6a219b80 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t + foo (uint32x4_t addr, mve_pred16_t p) + { +- return vldrwq_gather_base_z_s32 (addr, 4, p); ++ return vldrwq_gather_base_z_s32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c +index b64a11d6620..488adf58b78 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c +@@ -1,13 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t addr, mve_pred16_t p) + { +- return vldrwq_gather_base_z_u32 (addr, 4, p); ++ return vldrwq_gather_base_z_u32 (addr, 0, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c +index 6a4ea041137..a513452a12d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, uint32x4_t offset) ++foo (float32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset_f32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, uint32x4_t offset) ++foo1 (float32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c +index ee15fa4a0b0..57ad6583153 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, uint32x4_t offset) ++foo (int32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, uint32x4_t offset) ++foo1 (int32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c +index d344779058f..30fc36c6f97 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, uint32x4_t offset) ++foo (uint32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, uint32x4_t offset) ++foo1 (uint32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c +index 93253119418..1f84edcdb8e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z_f32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c +index 4537427bef3..3fe5a986cc3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c +index e59c4c996bf..087e5d0ce1e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c +index 1ba2cb0ccde..bed16f5fa72 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, uint32x4_t offset) ++foo (float32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset_f32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, uint32x4_t offset) ++foo1 (float32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c +index 39d976bb676..e6c589020f3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, uint32x4_t offset) ++foo (int32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset_s32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, uint32x4_t offset) ++foo1 (int32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c +index 971f482dfff..8e287da0dbf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, uint32x4_t offset) ++foo (uint32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset_u32 (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, uint32x4_t offset) ++foo1 (uint32_t const *base, uint32x4_t offset) + { + return vldrwq_gather_shifted_offset (base, offset); + } + +-/* { dg-final { scan-assembler "vldrw.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c +index e4110cd50aa..f69d67fd2aa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z_f32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c +index 71dd8a757ce..3aff6de03b6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z_s32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c +index f95d6f0f708..ed8873d0c53 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z_u32 (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p) ++foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p) + { + return vldrwq_gather_shifted_offset_z (base, offset, p); + } + +-/* { dg-final { scan-assembler "vldrwt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c +index 860dd324d25..87c3ac9f9d2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base) ++foo (int32_t const *base) + { + return vldrwq_s32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c +index 513ed49fb6e..5b560c534a1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c +@@ -1,14 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base) ++foo (uint32_t const *base) + { + return vldrwq_u32 (base); + } + +-/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c +index 3e0a6a60bcf..14a61fcfbd4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + float32x4_t +-foo (float32_t const * base, mve_pred16_t p) ++foo (float32_t const *base, mve_pred16_t p) + { + return vldrwq_z_f32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c +index 82b914885b5..5c90707becc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32_t const * base, mve_pred16_t p) ++foo (int32_t const *base, mve_pred16_t p) + { + return vldrwq_z_s32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c +index 6a66e167881..16b50335fe7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c +@@ -1,15 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32_t const * base, mve_pred16_t p) ++foo (uint32_t const *base, mve_pred16_t p) + { + return vldrwq_z_u32 (base, p); + } + +-/* { dg-final { scan-assembler-times "vpst" 1 } } */ +-/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */ ++#ifdef __cplusplus ++} ++#endif ++ + /* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c +index 48d213277df..6d011177c21 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxat.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmaxaq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxat.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmaxaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c +index 49273819861..f8f960af752 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxat.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmaxaq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxat.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmaxaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c +index 5ecdb2c19dc..69313d5ecc3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxat.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmaxaq_m_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxat.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxat.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmaxaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c +index f9a9f896aa2..aefe76a63e9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxa.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b) + { + return vmaxaq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmaxa.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmaxa.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b) + { + return vmaxaq (a, b); + } + +-/* { dg-final { scan-assembler "vmaxa.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c +index efe2fc16ff7..f5e018e3be5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxa.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b) + { + return vmaxaq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmaxa.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmaxa.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b) + { + return vmaxaq (a, b); + } + +-/* { dg-final { scan-assembler "vmaxa.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c +index 5c2e35f71a6..186b92a3d2f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxa.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b) + { + return vmaxaq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmaxa.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmaxa.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b) + { + return vmaxaq (a, b); + } + +-/* { dg-final { scan-assembler "vmaxa.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c +index 74ffad4e726..10478e9d97b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo (uint16_t a, int16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo1 (uint16_t a, int16x8_t b, mve_pred16_t p) + { + return vmaxavq_p (a, b, p); + } + +- +-int16_t +-foo2 (uint8_t a, int16x8_t b, mve_pred16_t p) ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint16_t ++foo2 (int16x8_t b, mve_pred16_t p) + { +- return vmaxavq_p (a, b, p); ++ return vmaxavq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxavt.s16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c +index 40800b0f12e..d43afbce273 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int32x4_t b, mve_pred16_t p) + { + return vmaxavq_p (a, b, p); + } + +- +-int32_t +-foo2 (uint16_t a, int32x4_t b, mve_pred16_t p) ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int32x4_t b, mve_pred16_t p) + { +- return vmaxavq_p (a, b, p); ++ return vmaxavq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxavt.s32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c +index 7638737fb84..beb34db720c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo (uint8_t a, int8x16_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo1 (uint8_t a, int8x16_t b, mve_pred16_t p) + { + return vmaxavq_p (a, b, p); + } + +- +-int8_t +-foo2 (uint32_t a, int8x16_t b, mve_pred16_t p) ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint8_t ++foo2 (int8x16_t b, mve_pred16_t p) + { +- return vmaxavq_p (a, b, p); ++ return vmaxavq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxavt.s8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c +index 0dca149b3e8..b997f308963 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo (uint16_t a, int16x8_t b) + { +@@ -11,18 +22,32 @@ foo (uint16_t a, int16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo1 (uint16_t a, int16x8_t b) + { + return vmaxavq (a, b); + } + +- +-int16_t +-foo2 (uint8_t a, int16x8_t b) ++/* ++**foo2: ++** ... ++** vmaxav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint16_t ++foo2 (int16x8_t b) + { +- return vmaxavq (a, b); ++ return vmaxavq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxav.s16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c +index f419a771017..e969f572bd4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int32x4_t b) + { +@@ -11,18 +22,32 @@ foo (uint32_t a, int32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int32x4_t b) + { + return vmaxavq (a, b); + } + +- +-int32_t +-foo2 (uint16_t a, int32x4_t b) ++/* ++**foo2: ++** ... ++** vmaxav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int32x4_t b) + { +- return vmaxavq (a, b); ++ return vmaxavq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxav.s32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c +index 214ad88f4aa..e668c378a03 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo (uint8_t a, int8x16_t b) + { +@@ -11,18 +22,32 @@ foo (uint8_t a, int8x16_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo1 (uint8_t a, int8x16_t b) + { + return vmaxavq (a, b); + } + +- +-int8_t +-foo2 (uint32_t a, int8x16_t b) ++/* ++**foo2: ++** ... ++** vmaxav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint8_t ++foo2 (int8x16_t b) + { +- return vmaxavq (a, b); ++ return vmaxavq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxav.s8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c +index f19707125db..1f6902e952c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxnma.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vmaxnmaq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vmaxnma.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmaxnma.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vmaxnmaq (a, b); + } + +-/* { dg-final { scan-assembler "vmaxnma.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c +index 94fc3a2aa28..dc79d1bf14b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxnma.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vmaxnmaq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vmaxnma.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmaxnma.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vmaxnmaq (a, b); + } + +-/* { dg-final { scan-assembler "vmaxnma.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c +index b2e82f5464c..aa6d3a5f2a6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmaxnmaq_m_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxnmat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmaxnmaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c +index 8fa7344b054..8637c6efa7a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmaxnmaq_m_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxnmat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmaxnmaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c +deleted file mode 100644 +index 7c2349d1ee4..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b) +-{ +- return vmaxnmavq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c +index 6d8cf19a341..7e3708cc5cc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo (float16_t a, float16x8_t b) + { +@@ -11,18 +22,32 @@ foo (float16_t a, float16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo1 (float16_t a, float16x8_t b) + { + return vmaxnmavq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vmaxnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t +-foo2 (float32_t a, float16x8_t b) ++foo2 (float16x8_t b) + { +- return vmaxnmavq (a, b); ++ return vmaxnmavq (1.1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxnmav.f16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c +deleted file mode 100644 +index 0deef79487a..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b) +-{ +- return vmaxnmavq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c +index ef79030d8eb..5f63fa52a1c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo (float32_t a, float32x4_t b) + { +@@ -11,18 +22,32 @@ foo (float32_t a, float32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo1 (float32_t a, float32x4_t b) + { + return vmaxnmavq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vmaxnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t +-foo2 (float16_t a, float32x4_t b) ++foo2 (float32x4_t b) + { +- return vmaxnmavq (a, b); ++ return vmaxnmavq (1.1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxnmav.f32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c +deleted file mode 100644 +index 56a7ac001f9..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +-{ +- return vmaxnmavq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c +index f7f39f59dad..1cc89f89a27 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo (float16_t a, float16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo1 (float16_t a, float16x8_t b, mve_pred16_t p) + { + return vmaxnmavq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t +-foo2 (float32_t a, float16x8_t b, mve_pred16_t p) ++foo2 (float16x8_t b, mve_pred16_t p) + { +- return vmaxnmavq_p (a, b, p); ++ return vmaxnmavq_p (1.1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxnmavt.f16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c +deleted file mode 100644 +index 36c10a90633..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vmaxnmavq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c +index 341f6254a5a..339be113753 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo (float32_t a, float32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo1 (float32_t a, float32x4_t b, mve_pred16_t p) + { + return vmaxnmavq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t +-foo2 (float16_t a, float32x4_t b, mve_pred16_t p) ++foo2 (float32x4_t b, mve_pred16_t p) + { +- return vmaxnmavq_p (a, b, p); ++ return vmaxnmavq_p (1.1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxnmavt.f32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c +index 59a8070e07b..2c2ac3c4edd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vmaxnmq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vmaxnm.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmaxnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vmaxnmq (a, b); + } + +-/* { dg-final { scan-assembler "vmaxnm.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c +index 5db42bd4b8c..18f4f0817ea 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vmaxnmq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vmaxnm.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmaxnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vmaxnmq (a, b); + } + +-/* { dg-final { scan-assembler "vmaxnm.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c +index 4668fd03c9d..5cf0d72b8af 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmaxnmq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxnmt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmaxnmq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxnmt.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c +index 9e8ccbc84b7..4a10383bb3b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmaxnmq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxnmt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmaxnmq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxnmt.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c +index ecca6069d22..c52bfce7425 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmaxnmq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxnmt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmaxnmq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c +index c3965dda4f1..a940a08691d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmaxnmq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxnmt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmaxnmq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c +deleted file mode 100644 +index f60641f5de0..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b) +-{ +- return vmaxnmvq (23.35, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c +index 80bd1d4cda1..d2a67445849 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo (float16_t a, float16x8_t b) + { +@@ -11,18 +22,32 @@ foo (float16_t a, float16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo1 (float16_t a, float16x8_t b) + { + return vmaxnmvq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vmaxnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t +-foo2 (float32_t a, float16x8_t b) ++foo2 (float16x8_t b) + { +- return vmaxnmvq (a, b); ++ return vmaxnmvq (1.1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxnmv.f16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c +deleted file mode 100644 +index f8c9f44ac78..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b) +-{ +- return vmaxnmvq (34.56, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c +index bb2fc46f88a..b56620693e8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo (float32_t a, float32x4_t b) + { +@@ -11,18 +22,32 @@ foo (float32_t a, float32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo1 (float32_t a, float32x4_t b) + { + return vmaxnmvq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vmaxnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t +-foo2 (float16_t a, float32x4_t b) ++foo2 (float32x4_t b) + { +- return vmaxnmvq (a, b); ++ return vmaxnmvq (1.1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxnmv.f32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c +deleted file mode 100644 +index 96820ecab91..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +-{ +- return vmaxnmvq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c +index 3efe203007b..9c4df6b2642 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo (float16_t a, float16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo1 (float16_t a, float16x8_t b, mve_pred16_t p) + { + return vmaxnmvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t +-foo2 (float32_t a, float16x8_t b, mve_pred16_t p) ++foo2 (float16x8_t b, mve_pred16_t p) + { +- return vmaxnmvq_p (a, b, p); ++ return vmaxnmvq_p (1.1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxnmvt.f16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c +deleted file mode 100644 +index 826ee8f900a..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vmaxnmvq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c +index 6c13247f1f1..fa4b5830679 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo (float32_t a, float32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo1 (float32_t a, float32x4_t b, mve_pred16_t p) + { + return vmaxnmvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t +-foo2 (float16_t a, float32x4_t b, mve_pred16_t p) ++foo2 (float32x4_t b, mve_pred16_t p) + { +- return vmaxnmvq_p (a, b, p); ++ return vmaxnmvq_p (1.1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxnmvt.f32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c +index 2791ed4c562..5ae4d8addb3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmaxq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmaxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c +index 27f7d5d7b16..6963a987176 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmaxq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmaxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c +index 23b7569f720..e7064300952 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmaxq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmaxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c +index 61e51e3b830..41117d46b25 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmaxq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmaxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c +index 23df7eeaed6..9ce6f831785 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmaxq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmaxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c +index 138d5c87894..fcd90fb6f90 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmaxq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmaxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c +index a42fc82a852..7c532dcac7b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmax.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vmaxq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmax.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmax.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmaxq (a, b); + } + +-/* { dg-final { scan-assembler "vmax.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c +index 14c094a5d11..e8e3a4eeb0c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmax.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vmaxq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmax.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmaxq (a, b); + } + +-/* { dg-final { scan-assembler "vmax.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c +index 0540a27bae9..ad529c03d8f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmax.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vmaxq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmax.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmax.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vmaxq (a, b); + } + +-/* { dg-final { scan-assembler "vmax.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c +index 6b9b5a73bcd..04d8c64fdd3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmax.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vmaxq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmax.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmax.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vmaxq (a, b); + } + +-/* { dg-final { scan-assembler "vmax.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c +index 3112302bf1a..d68ae2b43cb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmax.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vmaxq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmax.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmax.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vmaxq (a, b); + } + +-/* { dg-final { scan-assembler "vmax.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c +index b1baa5083bd..944353ef2d8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmax.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vmaxq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vmax.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmax.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vmaxq (a, b); + } + +-/* { dg-final { scan-assembler "vmax.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c +index 9d92f2ccd85..843a4cc4a70 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmaxq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmaxq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c +index 200fd4b1bb1..ff81a393f3f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmaxq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmaxq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c +index 2fe752558b9..68563747f3b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmaxq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmaxq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c +index 967622e331c..85c21e6ab1e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmaxq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmaxq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c +index 56b5d8fa8b8..b45d7bd3ea4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmaxq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmaxq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c +index 1816f959dd7..de8b2d4a48c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmaxq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmaxt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmaxq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c +index 657efc51bea..ac29f91bdf2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int16_t + foo (int16_t a, int16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,24 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int16_t + foo1 (int16_t a, int16x8_t b, mve_pred16_t p) + { + return vmaxvq_p (a, b, p); + } + +- +-int16_t +-foo2 (int8_t a, int16x8_t b, mve_pred16_t p) +-{ +- return vmaxvq_p (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxvt.s16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c +index 5882351c0fa..4290484f847 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,24 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, mve_pred16_t p) + { + return vmaxvq_p (a, b, p); + } + +- +-int32_t +-foo2 (int16_t a, int32x4_t b, mve_pred16_t p) +-{ +- return vmaxvq_p (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxvt.s32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c +index 3737ecd3307..6a9b1cedf0a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int8_t + foo (int8_t a, int8x16_t b, mve_pred16_t p) + { +@@ -11,18 +26,24 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int8_t + foo1 (int8_t a, int8x16_t b, mve_pred16_t p) + { + return vmaxvq_p (a, b, p); + } + +- +-int8_t +-foo2 (int32_t a, int8x16_t b, mve_pred16_t p) +-{ +- return vmaxvq_p (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxvt.s8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c +index 348cf39caa0..3cc1dbb0bbd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo (uint16_t a, uint16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p) + { + return vmaxvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t +-foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p) ++foo2 (uint16x8_t b, mve_pred16_t p) + { +- return vmaxvq_p (a, b, p); ++ return vmaxvq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxvt.u16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c +index f2e976216c5..99264f3a2b3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) + { + return vmaxvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p) ++foo2 (uint32x4_t b, mve_pred16_t p) + { +- return vmaxvq_p (a, b, p); ++ return vmaxvq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxvt.u32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c +index 7df5b63c9bc..6aac76b8798 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo (uint8_t a, uint8x16_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p) + { + return vmaxvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmaxvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t +-foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p) ++foo2 (uint8x16_t b, mve_pred16_t p) + { +- return vmaxvq_p (a, b, p); ++ return vmaxvq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxvt.u8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c +index 8412452cf33..18938d86396 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int16_t + foo (int16_t a, int16x8_t b) + { +@@ -11,18 +22,20 @@ foo (int16_t a, int16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int16_t + foo1 (int16_t a, int16x8_t b) + { + return vmaxvq (a, b); + } + +- +-int16_t +-foo2 (int8_t a, int16x8_t b) +-{ +- return vmaxvq (a, b); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxv.s16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c +index 09f4909c9a8..26ee10b0c27 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b) + { +@@ -11,18 +22,20 @@ foo (int32_t a, int32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b) + { + return vmaxvq (a, b); + } + +- +-int32_t +-foo2 (int16_t a, int32x4_t b) +-{ +- return vmaxvq (a, b); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxv.s32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c +index a087bbc6b64..b5bbfc3bd11 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int8_t + foo (int8_t a, int8x16_t b) + { +@@ -11,18 +22,20 @@ foo (int8_t a, int8x16_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int8_t + foo1 (int8_t a, int8x16_t b) + { + return vmaxvq (a, b); + } + +- +-int8_t +-foo2 (int32_t a, int8x16_t b) +-{ +- return vmaxvq (a, b); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxv.s8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c +index 47fe0d1cf0f..f806cfa7e36 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo (uint16_t a, uint16x8_t b) + { +@@ -11,18 +22,32 @@ foo (uint16_t a, uint16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo1 (uint16_t a, uint16x8_t b) + { + return vmaxvq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vmaxv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t +-foo2 (uint32_t a, uint16x8_t b) ++foo2 (uint16x8_t b) + { +- return vmaxvq (a, b); ++ return vmaxvq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxv.u16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c +index aa723daf5dd..b46dc06611f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint32x4_t b) + { +@@ -11,18 +22,32 @@ foo (uint32_t a, uint32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint32x4_t b) + { + return vmaxvq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vmaxv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo2 (uint8_t a, uint32x4_t b) ++foo2 (uint32x4_t b) + { +- return vmaxvq (a, b); ++ return vmaxvq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxv.u32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c +index 3aae785040c..1a64f5528c4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmaxv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo (uint8_t a, uint8x16_t b) + { +@@ -11,18 +22,32 @@ foo (uint8_t a, uint8x16_t b) + } + + ++/* ++**foo1: ++** ... ++** vmaxv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo1 (uint8_t a, uint8x16_t b) + { + return vmaxvq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vmaxv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t +-foo2 (uint16_t a, uint8x16_t b) ++foo2 (uint8x16_t b) + { +- return vmaxvq (a, b); ++ return vmaxvq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vmaxv.u8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c +index 0324110c6a8..50a98bf0780 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminat.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vminaq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminat.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vminaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c +index a2886d4f40f..3870cf5226a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminat.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vminaq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminat.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vminaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c +index 95eb038efc0..74a3122b18f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminat.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vminaq_m_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminat.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminat.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vminaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c +index 3a157e00a27..f78ee9de4f6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmina.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b) + { + return vminaq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmina.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmina.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b) + { + return vminaq (a, b); + } + +-/* { dg-final { scan-assembler "vmina.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c +index 5c732c65d63..cbe18e05e26 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmina.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b) + { + return vminaq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmina.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmina.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b) + { + return vminaq (a, b); + } + +-/* { dg-final { scan-assembler "vmina.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c +index 2e4dad141ce..e8030958284 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmina.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b) + { + return vminaq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmina.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmina.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b) + { + return vminaq (a, b); + } + +-/* { dg-final { scan-assembler "vmina.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c +index 9303ae02e39..ff77b8e72c5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo (uint16_t a, int16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo1 (uint16_t a, int16x8_t b, mve_pred16_t p) + { + return vminavq_p (a, b, p); + } + +- +-int16_t +-foo2 (uint8_t a, int16x8_t b, mve_pred16_t p) ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint16_t ++foo2 (int16x8_t b, mve_pred16_t p) + { +- return vminavq_p (a, b, p); ++ return vminavq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminavt.s16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c +index 36247f68b2c..4c1433d67f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int32x4_t b, mve_pred16_t p) + { + return vminavq_p (a, b, p); + } + +- +-int32_t +-foo2 (uint16_t a, int32x4_t b, mve_pred16_t p) ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int32x4_t b, mve_pred16_t p) + { +- return vminavq_p (a, b, p); ++ return vminavq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminavt.s32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c +index d3361615dcc..ef923f8d022 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo (uint8_t a, int8x16_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo1 (uint8_t a, int8x16_t b, mve_pred16_t p) + { + return vminavq_p (a, b, p); + } + +- +-int8_t +-foo2 (uint32_t a, int8x16_t b, mve_pred16_t p) ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint8_t ++foo2 (int8x16_t b, mve_pred16_t p) + { +- return vminavq_p (a, b, p); ++ return vminavq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminavt.s8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c +index 17e4edca2f1..3f66002e46c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo (uint16_t a, int16x8_t b) + { +@@ -11,18 +22,32 @@ foo (uint16_t a, int16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo1 (uint16_t a, int16x8_t b) + { + return vminavq (a, b); + } + +- +-int16_t +-foo2 (uint8_t a, int16x8_t b) ++/* ++**foo2: ++** ... ++** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint16_t ++foo2 (int16x8_t b) + { +- return vminavq (a, b); ++ return vminavq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminav.s16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c +index 032d02b8857..69daa328374 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, int32x4_t b) + { +@@ -11,18 +22,32 @@ foo (uint32_t a, int32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, int32x4_t b) + { + return vminavq (a, b); + } + +- +-int32_t +-foo2 (uint16_t a, int32x4_t b) ++/* ++**foo2: ++** ... ++** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (int32x4_t b) + { +- return vminavq (a, b); ++ return vminavq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminav.s32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c +index 2a2bb3d6146..95fb6cf51b4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo (uint8_t a, int8x16_t b) + { +@@ -11,18 +22,32 @@ foo (uint8_t a, int8x16_t b) + } + + ++/* ++**foo1: ++** ... ++** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo1 (uint8_t a, int8x16_t b) + { + return vminavq (a, b); + } + +- +-int8_t +-foo2 (uint32_t a, int8x16_t b) ++/* ++**foo2: ++** ... ++** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint8_t ++foo2 (int8x16_t b) + { +- return vminavq (a, b); ++ return vminavq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminav.s8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c +index cf32186d642..19c736cd318 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminnma.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vminnmaq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vminnma.f16" } } */ + ++/* ++**foo1: ++** ... ++** vminnma.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vminnmaq (a, b); + } + +-/* { dg-final { scan-assembler "vminnma.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c +index 1c3f19c9e1b..8dc7ea9a72d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminnma.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vminnmaq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vminnma.f32" } } */ + ++/* ++**foo1: ++** ... ++** vminnma.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vminnmaq (a, b); + } + +-/* { dg-final { scan-assembler "vminnma.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c +index 4423903e913..c57b3842a31 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vminnmaq_m_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminnmat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vminnmaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c +index 683f40ad3d8..8c51328c148 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vminnmaq_m_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminnmat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vminnmaq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c +deleted file mode 100644 +index 37d5136edca..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b) +-{ +- return vminnmavq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c +index fadb23e05c8..79503f2b212 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo (float16_t a, float16x8_t b) + { +@@ -11,18 +22,32 @@ foo (float16_t a, float16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo1 (float16_t a, float16x8_t b) + { + return vminnmavq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t +-foo2 (float32_t a, float16x8_t b) ++foo2 (float16x8_t b) + { +- return vminnmavq (a, b); ++ return vminnmavq (1.1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminnmav.f16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c +deleted file mode 100644 +index 78978d05054..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b) +-{ +- return vminnmavq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c +index 84714a96b9f..34dd9ddbb17 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo (float32_t a, float32x4_t b) + { +@@ -11,18 +22,32 @@ foo (float32_t a, float32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo1 (float32_t a, float32x4_t b) + { + return vminnmavq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t +-foo2 (float16_t a, float32x4_t b) ++foo2 (float32x4_t b) + { +- return vminnmavq (a, b); ++ return vminnmavq (1.1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminnmav.f32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c +deleted file mode 100644 +index 7170b747a40..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +-{ +- return vminnmavq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c +index c79fa307ae0..ae7931fc966 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo (float16_t a, float16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo1 (float16_t a, float16x8_t b, mve_pred16_t p) + { + return vminnmavq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t +-foo2 (float32_t a, float16x8_t b, mve_pred16_t p) ++foo2 (float16x8_t b, mve_pred16_t p) + { +- return vminnmavq_p (a, b, p); ++ return vminnmavq_p (1.1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminnmavt.f16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c +deleted file mode 100644 +index 09559053852..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vminnmavq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c +index bea04c7aac6..2d6aad6bc51 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo (float32_t a, float32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo1 (float32_t a, float32x4_t b, mve_pred16_t p) + { + return vminnmavq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t +-foo2 (float16_t a, float32x4_t b, mve_pred16_t p) ++foo2 (float32x4_t b, mve_pred16_t p) + { +- return vminnmavq_p (a, b, p); ++ return vminnmavq_p (1.1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminnmavt.f32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c +index 18d4a4c1330..251d35e9c6e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vminnmq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vminnm.f16" } } */ + ++/* ++**foo1: ++** ... ++** vminnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vminnmq (a, b); + } + +-/* { dg-final { scan-assembler "vminnm.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c +index 34144cad17f..7d77e215823 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vminnmq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vminnm.f32" } } */ + ++/* ++**foo1: ++** ... ++** vminnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vminnmq (a, b); + } + +-/* { dg-final { scan-assembler "vminnm.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c +index e5533d28035..fb741991a41 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vminnmq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminnmt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vminnmq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminnmt.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c +index 382d16c4489..fa3c47c23de 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vminnmq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminnmt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vminnmq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminnmt.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c +index 04d606ce5cd..632dcaa9dbf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vminnmq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminnmt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vminnmq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c +index 87cd970fd11..5c290687e60 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vminnmq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vminnmt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vminnmq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c +deleted file mode 100644 +index 132d1a123f8..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b) +-{ +- return vminnmvq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c +index 0eb3a4af14e..2ef50208def 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo (float16_t a, float16x8_t b) + { +@@ -11,18 +22,32 @@ foo (float16_t a, float16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo1 (float16_t a, float16x8_t b) + { + return vminnmvq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t +-foo2 (float32_t a, float16x8_t b) ++foo2 (float16x8_t b) + { +- return vminnmvq (a, b); ++ return vminnmvq (1.1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminnmv.f16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c +deleted file mode 100644 +index 74909075b09..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b) +-{ +- return vminnmvq (a, b); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c +index f3183508f8e..1a65fca220a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo (float32_t a, float32x4_t b) + { +@@ -11,18 +22,32 @@ foo (float32_t a, float32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo1 (float32_t a, float32x4_t b) + { + return vminnmvq (a, b); + } + +- ++/* ++**foo2: ++** ... ++** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t +-foo2 (float16_t a, float32x4_t b) ++foo2 (float32x4_t b) + { +- return vminnmvq (a, b); ++ return vminnmvq (1.1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminnmv.f32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c +deleted file mode 100644 +index c88c3b74a50..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16_t +-foo1 (float16_t a, float16x8_t b, mve_pred16_t p) +-{ +- return vminnmvq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c +index 16f6ac514c8..8cb61904dfe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo (float16_t a, float16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t + foo1 (float16_t a, float16x8_t b, mve_pred16_t p) + { + return vminnmvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float16_t +-foo2 (float32_t a, float16x8_t b, mve_pred16_t p) ++foo2 (float16x8_t b, mve_pred16_t p) + { +- return vminnmvq_p (a, b, p); ++ return vminnmvq_p (1.1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminnmvt.f16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c +deleted file mode 100644 +index e4db972fc70..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32_t +-foo1 (float32_t a, float32x4_t b, mve_pred16_t p) +-{ +- return vminnmvq_p (a, b, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c +index a8e4f9ffba7..93bad1ec334 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo (float32_t a, float32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t + foo1 (float32_t a, float32x4_t b, mve_pred16_t p) + { + return vminnmvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + float32_t +-foo2 (float16_t a, float32x4_t b, mve_pred16_t p) ++foo2 (float32x4_t b, mve_pred16_t p) + { +- return vminnmvq_p (a, b, p); ++ return vminnmvq_p (1.1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminnmvt.f32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c +index f257ddcf600..1b3bbe163fb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vminq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vminq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c +index 957da71d0e3..b45cc91f79b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vminq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vminq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c +index fea8bfd7994..fa7c43bb392 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vminq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vminq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c +index 7cc19a7dd5d..65dbf136d27 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vminq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vminq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c +index 301fbfc751f..256ee84ee40 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vminq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vminq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c +index 7a65b3557a3..9399ac4ab83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vminq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vminq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c +index d46a3c4ee18..8d3a948ec51 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmin.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vminq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmin.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmin.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vminq (a, b); + } + +-/* { dg-final { scan-assembler "vmin.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c +index 601e918a5bf..51970d67d5b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmin.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vminq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmin.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmin.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vminq (a, b); + } + +-/* { dg-final { scan-assembler "vmin.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c +index e2ae2341ad8..d5e671fe3b0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmin.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vminq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmin.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmin.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vminq (a, b); + } + +-/* { dg-final { scan-assembler "vmin.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c +index 3cac573f6ef..ade8c016637 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmin.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vminq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmin.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmin.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vminq (a, b); + } + +-/* { dg-final { scan-assembler "vmin.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c +index ca3ef245fe9..bb15d1b4575 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmin.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vminq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmin.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmin.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vminq (a, b); + } + +-/* { dg-final { scan-assembler "vmin.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c +index b7ef4db22ff..ff9b23288eb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmin.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vminq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vmin.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmin.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vminq (a, b); + } + +-/* { dg-final { scan-assembler "vmin.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c +index af93c78658e..6ae37c58b64 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vminq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vminq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c +index 76f0831e48e..395907dc7ec 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vminq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vminq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c +index fdd6e94497c..16f6ef3cd66 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vminq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vminq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c +index 9842954c761..c25dc747801 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vminq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vminq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c +index 741e4508879..bf2764d6ac0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vminq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vminq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c +index 13743fc87a1..f4a35535f68 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vminq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmint.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vminq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c +index 91bb63f6ba6..6562d6ae757 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int16_t + foo (int16_t a, int16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,24 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int16_t + foo1 (int16_t a, int16x8_t b, mve_pred16_t p) + { + return vminvq_p (a, b, p); + } + +- +-int16_t +-foo2 (int8_t a, int16x8_t b, mve_pred16_t p) +-{ +- return vminvq_p (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminvt.s16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c +index a846701312c..6e3715e3ef3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,24 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, mve_pred16_t p) + { + return vminvq_p (a, b, p); + } + +- +-int32_t +-foo2 (int16_t a, int32x4_t b, mve_pred16_t p) +-{ +- return vminvq_p (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminvt.s32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c +index 716d414f3a7..dc06d0f5e7e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int8_t + foo (int8_t a, int8x16_t b, mve_pred16_t p) + { +@@ -11,18 +26,24 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int8_t + foo1 (int8_t a, int8x16_t b, mve_pred16_t p) + { + return vminvq_p (a, b, p); + } + +- +-int8_t +-foo2 (int32_t a, int8x16_t b, mve_pred16_t p) +-{ +- return vminvq_p (a, b, p); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminvt.s8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c +index cc7f8fe8933..16cc419fce2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo (uint16_t a, uint16x8_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p) + { + return vminvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t +-foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p) ++foo2 (uint16x8_t b, mve_pred16_t p) + { +- return vminvq_p (a, b, p); ++ return vminvq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminvt.u16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c +index 6bde0be29cc..bef29dc40e3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint32x4_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) + { + return vminvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p) ++foo2 (uint32x4_t b, mve_pred16_t p) + { +- return vminvq_p (a, b, p); ++ return vminvq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminvt.u32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c +index bb894904f3c..42beaee1d45 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c +@@ -1,9 +1,24 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo (uint8_t a, uint8x16_t b, mve_pred16_t p) + { +@@ -11,18 +26,40 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p) + } + + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p) + { + return vminvq_p (a, b, p); + } + +- ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t +-foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p) ++foo2 (uint8x16_t b, mve_pred16_t p) + { +- return vminvq_p (a, b, p); ++ return vminvq_p (1, b, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminvt.u8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c +index 6d589aa4a05..9fc314d2573 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int16_t + foo (int16_t a, int16x8_t b) + { +@@ -11,17 +22,20 @@ foo (int16_t a, int16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vminv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int16_t + foo1 (int16_t a, int16x8_t b) + { + return vminvq (a, b); + } + +-int16_t +-foo2 (int8_t a, int16x8_t b) +-{ +- return vminvq (a, b); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminv.s16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c +index 7c727d6d92b..3546b69e9a8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b) + { +@@ -11,17 +22,20 @@ foo (int32_t a, int32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vminv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b) + { + return vminvq (a, b); + } + +-int32_t +-foo2 (int8_t a, int32x4_t b) +-{ +- return vminvq (a, b); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminv.s32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c +index 76309482fc5..e512a7df254 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int8_t + foo (int8_t a, int8x16_t b) + { +@@ -11,17 +22,20 @@ foo (int8_t a, int8x16_t b) + } + + ++/* ++**foo1: ++** ... ++** vminv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + int8_t + foo1 (int8_t a, int8x16_t b) + { + return vminvq (a, b); + } + +-int8_t +-foo2 (int32_t a, int8x16_t b) +-{ +- return vminvq (a, b); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminv.s8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c +index 698975f456c..29746c3184a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo (uint16_t a, uint16x8_t b) + { +@@ -11,18 +22,32 @@ foo (uint16_t a, uint16x8_t b) + } + + ++/* ++**foo1: ++** ... ++** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint16_t + foo1 (uint16_t a, uint16x8_t b) + { + return vminvq (a, b); + } + +- +-uint8_t +-foo2 (uint32_t a, uint16x8_t b) ++/* ++**foo2: ++** ... ++** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint16_t ++foo2 (uint16x8_t b) + { +- return vminvq (a, b); ++ return vminvq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminv.u16" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c +index 7489f81debf..d12764ddfa7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo (uint32_t a, uint32x4_t b) + { +@@ -11,17 +22,32 @@ foo (uint32_t a, uint32x4_t b) + } + + ++/* ++**foo1: ++** ... ++** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t + foo1 (uint32_t a, uint32x4_t b) + { + return vminvq (a, b); + } + ++/* ++**foo2: ++** ... ++** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo2 (uint16_t a, uint32x4_t b) ++foo2 (uint32x4_t b) + { +- return vminvq (a, b); ++ return vminvq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminv.u32" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c +index aa2b986d558..60175116e9f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c +@@ -1,9 +1,20 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo (uint8_t a, uint8x16_t b) + { +@@ -11,18 +22,32 @@ foo (uint8_t a, uint8x16_t b) + } + + ++/* ++**foo1: ++** ... ++** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ + uint8_t + foo1 (uint8_t a, uint8x16_t b) + { + return vminvq (a, b); + } + +- +-uint16_t +-foo2 (uint32_t a, uint8x16_t b) ++/* ++**foo2: ++** ... ++** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) ++** ... ++*/ ++uint8_t ++foo2 (uint8x16_t b) + { +- return vminvq (a, b); ++ return vminvq (1, b); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +-/* { dg-final { scan-assembler-times "vminv.u8" 3 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c +index e458204c41b..258adfa989d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavaq_p_s16 (a, b, c, p); ++ return vmladavaq_p_s16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo1 (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavaq_p (a, b, c, p); ++ return vmladavaq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavat.s16" } } */ +-/* { dg-final { scan-assembler "vmladavat.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c +index e3544787adb..78d3333a9fc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavaq_p_s32 (a, b, c, p); ++ return vmladavaq_p_s32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo1 (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavaq_p (a, b, c, p); ++ return vmladavaq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavat.s32" } } */ +-/* { dg-final { scan-assembler "vmladavat.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c +index 1d4ca722f44..1529e9466f1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) ++foo (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavaq_p_s8 (a, b, c, p); ++ return vmladavaq_p_s8 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavat.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) ++foo1 (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavaq_p (a, b, c, p); ++ return vmladavaq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavat.s8" } } */ +-/* { dg-final { scan-assembler "vmladavat.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c +index 91a11c8b8b1..3266c3a6d1d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c +@@ -1,22 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) ++foo (uint32_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmladavaq_p_u16 (a, b, c, p); ++ return vmladavaq_p_u16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavat.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) ++foo1 (uint32_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmladavaq_p (a, b, c, p); ++ return vmladavaq_p (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) ++{ ++ return vmladavaq_p (1, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavat.u16" } } */ +-/* { dg-final { scan-assembler "vmladavat.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c +index 0efe8d0902f..a555e5f3fb0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c +@@ -1,22 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) ++foo (uint32_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmladavaq_p_u32 (a, b, c, p); ++ return vmladavaq_p_u32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavat.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) ++foo1 (uint32_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmladavaq_p (a, b, c, p); ++ return vmladavaq_p (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) ++{ ++ return vmladavaq_p (1, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavat.u32" } } */ +-/* { dg-final { scan-assembler "vmladavat.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c +index a8da9b0d2ef..4f9596f4958 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c +@@ -1,22 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) ++foo (uint32_t add, uint8x16_t m1, uint8x16_t m2, mve_pred16_t p) + { +- return vmladavaq_p_u8 (a, b, c, p); ++ return vmladavaq_p_u8 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavat.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) ++foo1 (uint32_t add, uint8x16_t m1, uint8x16_t m2, mve_pred16_t p) + { +- return vmladavaq_p (a, b, c, p); ++ return vmladavaq_p (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavat.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p) ++{ ++ return vmladavaq_p (1, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavat.u8" } } */ +-/* { dg-final { scan-assembler "vmladavat.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c +index a45ea90b60f..9f7c0eeb04f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int16x8_t b, int16x8_t c) ++foo (int32_t add, int16x8_t m1, int16x8_t m2) + { +- return vmladavaq_s16 (a, b, c); ++ return vmladavaq_s16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmladava.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmladava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int16x8_t b, int16x8_t c) ++foo1 (int32_t add, int16x8_t m1, int16x8_t m2) + { +- return vmladavaq (a, b, c); ++ return vmladavaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladava.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c +index 6533addcfaf..012a06988e5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int32x4_t b, int32x4_t c) ++foo (int32_t add, int32x4_t m1, int32x4_t m2) + { +- return vmladavaq_s32 (a, b, c); ++ return vmladavaq_s32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmladava.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmladava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int32x4_t b, int32x4_t c) ++foo1 (int32_t add, int32x4_t m1, int32x4_t m2) + { +- return vmladavaq (a, b, c); ++ return vmladavaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladava.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c +index 6fed506e7c4..f41230f3ac8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int8x16_t b, int8x16_t c) ++foo (int32_t add, int8x16_t m1, int8x16_t m2) + { +- return vmladavaq_s8 (a, b, c); ++ return vmladavaq_s8 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmladava.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmladava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int8x16_t b, int8x16_t c) ++foo1 (int32_t add, int8x16_t m1, int8x16_t m2) + { +- return vmladavaq (a, b, c); ++ return vmladavaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladava.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c +index 3c5f689ba92..62a3c0e5027 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladava.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32_t a, uint16x8_t b, uint16x8_t c) ++foo (uint32_t add, uint16x8_t m1, uint16x8_t m2) + { +- return vmladavaq_u16 (a, b, c); ++ return vmladavaq_u16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmladava.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmladava.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32_t a, uint16x8_t b, uint16x8_t c) ++foo1 (uint32_t add, uint16x8_t m1, uint16x8_t m2) + { +- return vmladavaq (a, b, c); ++ return vmladavaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmladava.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint16x8_t m1, uint16x8_t m2) ++{ ++ return vmladavaq (1, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladava.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c +index 6172f82aaaa..a186953d9dd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladava.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32_t a, uint32x4_t b, uint32x4_t c) ++foo (uint32_t add, uint32x4_t m1, uint32x4_t m2) + { +- return vmladavaq_u32 (a, b, c); ++ return vmladavaq_u32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmladava.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmladava.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32_t a, uint32x4_t b, uint32x4_t c) ++foo1 (uint32_t add, uint32x4_t m1, uint32x4_t m2) + { +- return vmladavaq (a, b, c); ++ return vmladavaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmladava.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint32x4_t m1, uint32x4_t m2) ++{ ++ return vmladavaq (1, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladava.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c +index 2aff5552053..0df91990ead 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladava.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32_t a, uint8x16_t b, uint8x16_t c) ++foo (uint32_t add, uint8x16_t m1, uint8x16_t m2) + { +- return vmladavaq_u8 (a, b, c); ++ return vmladavaq_u8 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmladava.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmladava.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32_t a, uint8x16_t b, uint8x16_t c) ++foo1 (uint32_t add, uint8x16_t m1, uint8x16_t m2) + { +- return vmladavaq (a, b, c); ++ return vmladavaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmladava.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32_t ++foo2 (uint8x16_t m1, uint8x16_t m2) ++{ ++ return vmladavaq (1, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladava.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c +index 838717e3e43..5925d9e968e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavaxq_p_s16 (a, b, c, p); ++ return vmladavaxq_p_s16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavaxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo1 (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavaxq_p (a, b, c, p); ++ return vmladavaxq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavaxt.s16" } } */ +-/* { dg-final { scan-assembler "vmladavaxt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c +index a50c5ecf802..87d66e654f7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavaxq_p_s32 (a, b, c, p); ++ return vmladavaxq_p_s32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo1 (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavaxq_p (a, b, c, p); ++ return vmladavaxq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavaxt.s32" } } */ +-/* { dg-final { scan-assembler "vmladavaxt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c +index e4705cecad9..803a5becc86 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) ++foo (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavaxq_p_s8 (a, b, c, p); ++ return vmladavaxq_p_s8 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavaxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) ++foo1 (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavaxq_p (a, b, c, p); ++ return vmladavaxq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavaxt.s8" } } */ +-/* { dg-final { scan-assembler "vmladavaxt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c +index ffd542a062f..6a81b4acfcb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int16x8_t b, int16x8_t c) ++foo (int32_t add, int16x8_t m1, int16x8_t m2) + { +- return vmladavaxq_s16 (a, b, c); ++ return vmladavaxq_s16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmladavax.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmladavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int16x8_t b, int16x8_t c) ++foo1 (int32_t add, int16x8_t m1, int16x8_t m2) + { +- return vmladavaxq (a, b, c); ++ return vmladavaxq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavax.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c +index b91e54d79e6..b63ca43abba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int32x4_t b, int32x4_t c) ++foo (int32_t add, int32x4_t m1, int32x4_t m2) + { +- return vmladavaxq_s32 (a, b, c); ++ return vmladavaxq_s32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmladavax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmladavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int32x4_t b, int32x4_t c) ++foo1 (int32_t add, int32x4_t m1, int32x4_t m2) + { +- return vmladavaxq (a, b, c); ++ return vmladavaxq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavax.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c +index 61949c416fc..2430858aa51 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32_t a, int8x16_t b, int8x16_t c) ++foo (int32_t add, int8x16_t m1, int8x16_t m2) + { +- return vmladavaxq_s8 (a, b, c); ++ return vmladavaxq_s8 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmladavax.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmladavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32_t a, int8x16_t b, int8x16_t c) ++foo1 (int32_t add, int8x16_t m1, int8x16_t m2) + { +- return vmladavaxq (a, b, c); ++ return vmladavaxq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavax.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c +index 2a7a79e62ea..f05d04b1f3d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavq_p_s16 (a, b, p); ++ return vmladavq_p_s16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c +index 6b118144075..397bb9fb4ec 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavq_p_s32 (a, b, p); ++ return vmladavq_p_s32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c +index b3a4e11fa24..25c11d200ad 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int8x16_t a, int8x16_t b, mve_pred16_t p) ++foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavq_p_s8 (a, b, p); ++ return vmladavq_p_s8 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) ++foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c +index 0ff2ffdc5f2..064d2c22a23 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) ++foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmladavq_p_u16 (a, b, p); ++ return vmladavq_p_u16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) ++foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c +index c5d213d4c0b..f5f3de9f0e8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) ++foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmladavq_p_u32 (a, b, p); ++ return vmladavq_p_u32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) ++foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c +index 6fcc530c17c..243e61715e4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) ++foo (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p) + { +- return vmladavq_p_u8 (a, b, p); ++ return vmladavq_p_u8 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) ++foo1 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p) + { +- return vmladavq_p (a, b, p); ++ return vmladavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c +index a140be6204d..b0ff042fc43 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int16x8_t a, int16x8_t b) ++foo (int16x8_t m1, int16x8_t m2) + { +- return vmladavq_s16 (a, b); ++ return vmladavq_s16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int16x8_t a, int16x8_t b) ++foo1 (int16x8_t m1, int16x8_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c +index 1413e480551..a2ef4b37e4d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32x4_t a, int32x4_t b) ++foo (int32x4_t m1, int32x4_t m2) + { +- return vmladavq_s32 (a, b); ++ return vmladavq_s32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32x4_t a, int32x4_t b) ++foo1 (int32x4_t m1, int32x4_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c +index d43dbb9fefc..e3e6e2982d7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int8x16_t a, int8x16_t b) ++foo (int8x16_t m1, int8x16_t m2) + { +- return vmladavq_s8 (a, b); ++ return vmladavq_s8 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int8x16_t a, int8x16_t b) ++foo1 (int8x16_t m1, int8x16_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c +index e1c44d7b4ce..d021bc0e30d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint16x8_t a, uint16x8_t b) ++foo (uint16x8_t m1, uint16x8_t m2) + { +- return vmladavq_u16 (a, b); ++ return vmladavq_u16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint16x8_t a, uint16x8_t b) ++foo1 (uint16x8_t m1, uint16x8_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c +index 5e9bb56bae0..0848ca25b9f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint32x4_t a, uint32x4_t b) ++foo (uint32x4_t m1, uint32x4_t m2) + { +- return vmladavq_u32 (a, b); ++ return vmladavq_u32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint32x4_t a, uint32x4_t b) ++foo1 (uint32x4_t m1, uint32x4_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c +index f4223538170..2a735fbb654 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo (uint8x16_t a, uint8x16_t b) ++foo (uint8x16_t m1, uint8x16_t m2) + { +- return vmladavq_u8 (a, b); ++ return vmladavq_u8 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladav.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmladav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32_t +-foo1 (uint8x16_t a, uint8x16_t b) ++foo1 (uint8x16_t m1, uint8x16_t m2) + { +- return vmladavq (a, b); ++ return vmladavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladav.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c +index 7ee875eae6b..dc94ecada57 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavxq_p_s16 (a, b, p); ++ return vmladavxq_p_s16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmladavxq_p (a, b, p); ++ return vmladavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavxt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c +index d4f92ba9cf2..15a2abd7d13 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavxq_p_s32 (a, b, p); ++ return vmladavxq_p_s32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmladavxq_p (a, b, p); ++ return vmladavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavxt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c +index d5f14c51ae8..e56874151a8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int8x16_t a, int8x16_t b, mve_pred16_t p) ++foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavxq_p_s8 (a, b, p); ++ return vmladavxq_p_s8 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmladavxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmladavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) ++foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p) + { +- return vmladavxq_p (a, b, p); ++ return vmladavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavxt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c +index deac58d768e..e7e3b571efb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int16x8_t a, int16x8_t b) ++foo (int16x8_t m1, int16x8_t m2) + { +- return vmladavxq_s16 (a, b); ++ return vmladavxq_s16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladavx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmladavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int16x8_t a, int16x8_t b) ++foo1 (int16x8_t m1, int16x8_t m2) + { +- return vmladavxq (a, b); ++ return vmladavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavx.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c +index 56516d74173..c3841f59d57 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int32x4_t a, int32x4_t b) ++foo (int32x4_t m1, int32x4_t m2) + { +- return vmladavxq_s32 (a, b); ++ return vmladavxq_s32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladavx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmladavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int32x4_t a, int32x4_t b) ++foo1 (int32x4_t m1, int32x4_t m2) + { +- return vmladavxq (a, b); ++ return vmladavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavx.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c +index 3b1e8cd67cd..59cdc346ee5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmladavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo (int8x16_t a, int8x16_t b) ++foo (int8x16_t m1, int8x16_t m2) + { +- return vmladavxq_s8 (a, b); ++ return vmladavxq_s8 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmladavx.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmladavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t +-foo1 (int8x16_t a, int8x16_t b) ++foo1 (int8x16_t m1, int8x16_t m2) + { +- return vmladavxq (a, b); ++ return vmladavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmladavx.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c +index 246b40fbe2c..fbdbb5c16a8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p_s16 (a, b, c, p); ++ return vmlaldavaq_p_s16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p (a, b, c, p); ++ return vmlaldavaq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavat.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c +index 6563af20061..9c59d0306a1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p_s32 (a, b, c, p); ++ return vmlaldavaq_p_s32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p (a, b, c, p); ++ return vmlaldavaq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavat.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c +index 632e29f972d..b714b677339 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) ++foo (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p_u16 (a, b, c, p); ++ return vmlaldavaq_p_u16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavat.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) ++foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p (a, b, c, p); ++ return vmlaldavaq_p (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) ++{ ++ return vmlaldavaq_p (1, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavat.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c +index d2fcd5d14ed..29419a06458 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) ++foo (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p_u32 (a, b, c, p); ++ return vmlaldavaq_p_u32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavat.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) ++foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaq_p (a, b, c, p); ++ return vmlaldavaq_p (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) ++{ ++ return vmlaldavaq_p (1, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavat.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c +index 1cb9b6ebc41..d1f049923c0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int16x8_t b, int16x8_t c) ++foo (int64_t add, int16x8_t m1, int16x8_t m2) + { +- return vmlaldavaq_s16 (a, b, c); ++ return vmlaldavaq_s16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldava.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int16x8_t b, int16x8_t c) ++foo1 (int64_t add, int16x8_t m1, int16x8_t m2) + { +- return vmlaldavaq (a, b, c); ++ return vmlaldavaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldava.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c +index 56e59f5929d..dfce7d8f625 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int32x4_t b, int32x4_t c) ++foo (int64_t add, int32x4_t m1, int32x4_t m2) + { +- return vmlaldavaq_s32 (a, b, c); ++ return vmlaldavaq_s32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldava.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int32x4_t b, int32x4_t c) ++foo1 (int64_t add, int32x4_t m1, int32x4_t m2) + { +- return vmlaldavaq (a, b, c); ++ return vmlaldavaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldava.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c +index 7c95abc271c..7e42054a4f3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint64_t a, uint16x8_t b, uint16x8_t c) ++foo (uint64_t add, uint16x8_t m1, uint16x8_t m2) + { +- return vmlaldavaq_u16 (a, b, c); ++ return vmlaldavaq_u16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldava.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c) ++foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2) + { +- return vmlaldavaq (a, b, c); ++ return vmlaldavaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint16x8_t m1, uint16x8_t m2) ++{ ++ return vmlaldavaq (1, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldava.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c +index 239f5e32d8b..20ba6d377bf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint64_t a, uint32x4_t b, uint32x4_t c) ++foo (uint64_t add, uint32x4_t m1, uint32x4_t m2) + { +- return vmlaldavaq_u32 (a, b, c); ++ return vmlaldavaq_u32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldava.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c) ++foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2) + { +- return vmlaldavaq (a, b, c); ++ return vmlaldavaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint32x4_t m1, uint32x4_t m2) ++{ ++ return vmlaldavaq (1, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldava.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c +index f33d3880236..7c2f07f3495 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaxq_p_s16 (a, b, c, p); ++ return vmlaldavaxq_p_s16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavaxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) ++foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavaxq_p (a, b, c, p); ++ return vmlaldavaxq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavaxt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c +index ab072a9850e..6214235487b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaxq_p_s32 (a, b, c, p); ++ return vmlaldavaxq_p_s32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) ++foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavaxq_p (a, b, c, p); ++ return vmlaldavaxq_p (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavaxt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c +index e68fbd2df94..b5922b8c281 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int16x8_t b, int16x8_t c) ++foo (int64_t add, int16x8_t m1, int16x8_t m2) + { +- return vmlaldavaxq_s16 (a, b, c); ++ return vmlaldavaxq_s16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldavax.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int16x8_t b, int16x8_t c) ++foo1 (int64_t add, int16x8_t m1, int16x8_t m2) + { +- return vmlaldavaxq (a, b, c); ++ return vmlaldavaxq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavax.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c +index 7b6fea289da..124125e2f29 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int64_t a, int32x4_t b, int32x4_t c) ++foo (int64_t add, int32x4_t m1, int32x4_t m2) + { +- return vmlaldavaxq_s32 (a, b, c); ++ return vmlaldavaxq_s32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldavax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int64_t a, int32x4_t b, int32x4_t c) ++foo1 (int64_t add, int32x4_t m1, int32x4_t m2) + { +- return vmlaldavaxq (a, b, c); ++ return vmlaldavaxq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavax.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c +index 008efd95a35..de9cc0ed9c4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavq_p_s16 (a, b, p); ++ return vmlaldavq_p_s16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavq_p (a, b, p); ++ return vmlaldavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c +index e824e6b7ce0..a2b1c59291b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavq_p_s32 (a, b, p); ++ return vmlaldavq_p_s32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavq_p (a, b, p); ++ return vmlaldavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c +index 1fea6d5c117..6034b9b5454 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) ++foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmlaldavq_p_u16 (a, b, p); ++ return vmlaldavq_p_u16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) ++foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) + { +- return vmlaldavq_p (a, b, p); ++ return vmlaldavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c +index 99300fcb6ec..a85d7de4dad 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) ++foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmlaldavq_p_u32 (a, b, p); ++ return vmlaldavq_p_u32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) ++foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) + { +- return vmlaldavq_p (a, b, p); ++ return vmlaldavq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c +index 1cdb44920e1..b18e8eb149e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int16x8_t a, int16x8_t b) ++foo (int16x8_t m1, int16x8_t m2) + { +- return vmlaldavq_s16 (a, b); ++ return vmlaldavq_s16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldav.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int16x8_t a, int16x8_t b) ++foo1 (int16x8_t m1, int16x8_t m2) + { +- return vmlaldavq (a, b); ++ return vmlaldavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldav.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c +index 123ca0f4eeb..b0fe1c5132c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int32x4_t a, int32x4_t b) ++foo (int32x4_t m1, int32x4_t m2) + { +- return vmlaldavq_s32 (a, b); ++ return vmlaldavq_s32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldav.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int32x4_t a, int32x4_t b) ++foo1 (int32x4_t m1, int32x4_t m2) + { +- return vmlaldavq (a, b); ++ return vmlaldavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldav.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c +index c9c40eeac0a..d1fcf715cb7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldav.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint16x8_t a, uint16x8_t b) ++foo (uint16x8_t m1, uint16x8_t m2) + { +- return vmlaldavq_u16 (a, b); ++ return vmlaldavq_u16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldav.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldav.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint16x8_t a, uint16x8_t b) ++foo1 (uint16x8_t m1, uint16x8_t m2) + { +- return vmlaldavq (a, b); ++ return vmlaldavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldav.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c +index 4d1754697bf..76726e8255b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldav.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo (uint32x4_t a, uint32x4_t b) ++foo (uint32x4_t m1, uint32x4_t m2) + { +- return vmlaldavq_u32 (a, b); ++ return vmlaldavq_u32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldav.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldav.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t +-foo1 (uint32x4_t a, uint32x4_t b) ++foo1 (uint32x4_t m1, uint32x4_t m2) + { +- return vmlaldavq (a, b); ++ return vmlaldavq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldav.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c +index d41c2e16114..3b8392bcf7f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavxq_p_s16 (a, b, p); ++ return vmlaldavxq_p_s16 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p) + { +- return vmlaldavxq_p (a, b, p); ++ return vmlaldavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c +index 8ad7b219a0f..578b7b68095 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavxq_p_s32 (a, b, p); ++ return vmlaldavxq_p_s32 (m1, m2, p); + } + +-/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlaldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p) + { +- return vmlaldavxq_p (a, b, p); ++ return vmlaldavxq_p (m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c +index ebe999393e8..7061bd2c13d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int16x8_t a, int16x8_t b) ++foo (int16x8_t m1, int16x8_t m2) + { +- return vmlaldavxq_s16 (a, b); ++ return vmlaldavxq_s16 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldavx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int16x8_t a, int16x8_t b) ++foo1 (int16x8_t m1, int16x8_t m2) + { +- return vmlaldavxq (a, b); ++ return vmlaldavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavx.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c +index 0417eb867de..957dc174a36 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlaldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo (int32x4_t a, int32x4_t b) ++foo (int32x4_t m1, int32x4_t m2) + { +- return vmlaldavxq_s32 (a, b); ++ return vmlaldavxq_s32 (m1, m2); + } + +-/* { dg-final { scan-assembler "vmlaldavx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlaldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t +-foo1 (int32x4_t a, int32x4_t b) ++foo1 (int32x4_t m1, int32x4_t m2) + { +- return vmlaldavxq (a, b); ++ return vmlaldavxq (m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlaldavx.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c +index d48b020d595..f68fe8e49a3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_s16 (a, b, c, p); ++ return vmlaq_m_n_s16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c +index 315c1afc2c7..d3c49553596 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_s32 (a, b, c, p); ++ return vmlaq_m_n_s32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c +index a452f5de5e6..44dc3b57cdd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_s8 (a, b, c, p); ++ return vmlaq_m_n_s8 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c +index 6ecdc689a61..cbb92fb39b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) ++foo (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_u16 (a, b, c, p); ++ return vmlaq_m_n_u16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) ++foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t add, uint16x8_t m1, mve_pred16_t p) ++{ ++ return vmlaq_m (add, m1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c +index 2c584a635e7..569ea91af36 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) ++foo (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_u32 (a, b, c, p); ++ return vmlaq_m_n_u32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) ++foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t add, uint32x4_t m1, mve_pred16_t p) ++{ ++ return vmlaq_m (add, m1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c +index b75b3c95916..592ad3e072a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) ++foo (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p) + { +- return vmlaq_m_n_u8 (a, b, c, p); ++ return vmlaq_m_n_u8 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) ++foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p) + { +- return vmlaq_m (a, b, c, p); ++ return vmlaq_m (add, m1, m2, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t add, uint8x16_t m1, mve_pred16_t p) ++{ ++ return vmlaq_m (add, m1, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlat.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c +index 29543c8f60d..d1fa73de1c9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c) ++foo (int16x8_t add, int16x8_t m1, int16_t m2) + { +- return vmlaq_n_s16 (a, b, c); ++ return vmlaq_n_s16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmla.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c) ++foo1 (int16x8_t add, int16x8_t m1, int16_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c +index d74bacaffd7..c349c0c8d7f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c) ++foo (int32x4_t add, int32x4_t m1, int32_t m2) + { +- return vmlaq_n_s32 (a, b, c); ++ return vmlaq_n_s32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmla.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c) ++foo1 (int32x4_t add, int32x4_t m1, int32_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c +index 38dd01a6580..c1cd39e5715 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c) ++foo (int8x16_t add, int8x16_t m1, int8_t m2) + { +- return vmlaq_n_s8 (a, b, c); ++ return vmlaq_n_s8 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmla.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c) ++foo1 (int8x16_t add, int8x16_t m1, int8_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c +index 55a5d0601d5..5eb201c05e8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint16x8_t b, uint16_t c) ++foo (uint16x8_t add, uint16x8_t m1, uint16_t m2) + { +- return vmlaq_n_u16 (a, b, c); ++ return vmlaq_n_u16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c) ++foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t add, uint16x8_t m1) ++{ ++ return vmlaq (add, m1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c +index e160275a29b..d4820ea65d9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, uint32_t c) ++foo (uint32x4_t add, uint32x4_t m1, uint32_t m2) + { +- return vmlaq_n_u32 (a, b, c); ++ return vmlaq_n_u32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c) ++foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t add, uint32x4_t m1) ++{ ++ return vmlaq (add, m1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c +index 5f0edef53d4..7f83f092b07 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint8x16_t b, uint8_t c) ++foo (uint8x16_t add, uint8x16_t m1, uint8_t m2) + { +- return vmlaq_n_u8 (a, b, c); ++ return vmlaq_n_u8 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vmla.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c) ++foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2) + { +- return vmlaq (a, b, c); ++ return vmlaq (add, m1, m2); ++} ++ ++/* ++**foo2: ++** ... ++** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t add, uint8x16_t m1) ++{ ++ return vmlaq (add, m1, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmla.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c +index bf66e616ec7..83af9bb4355 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p) + { +- return vmlasq_m_n_s16 (a, b, c, p); ++ return vmlasq_m_n_s16 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p) + { +- return vmlasq_m (a, b, c, p); ++ return vmlasq_m (m1, m2, add, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c +index 53c21e2e5b6..f6bf6444bdd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p) + { +- return vmlasq_m_n_s32 (a, b, c, p); ++ return vmlasq_m_n_s32 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p) + { +- return vmlasq_m (a, b, c, p); ++ return vmlasq_m (m1, m2, add, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c +index ac08b15fdbe..021fc0373a6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p) + { +- return vmlasq_m_n_s8 (a, b, c, p); ++ return vmlasq_m_n_s8 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p) + { +- return vmlasq_m (a, b, c, p); ++ return vmlasq_m (m1, m2, add, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c +index 99f1e28c7d5..1b478da34da 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) ++foo (uint16x8_t m1, uint16x8_t m2, uint16_t add, mve_pred16_t p) + { +- return vmlasq_m_n_u16 (a, b, c, p); ++ return vmlasq_m_n_u16 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) ++foo1 (uint16x8_t m1, uint16x8_t m2, uint16_t add, mve_pred16_t p) + { +- return vmlasq_m (a, b, c, p); ++ return vmlasq_m (m1, m2, add, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p) ++{ ++ return vmlasq_m (m1, m2, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c +index 8d8edca6024..99fc605d1b2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) ++foo (uint32x4_t m1, uint32x4_t m2, uint32_t add, mve_pred16_t p) + { +- return vmlasq_m_n_u32 (a, b, c, p); ++ return vmlasq_m_n_u32 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) ++foo1 (uint32x4_t m1, uint32x4_t m2, uint32_t add, mve_pred16_t p) + { +- return vmlasq_m (a, b, c, p); ++ return vmlasq_m (m1, m2, add, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p) ++{ ++ return vmlasq_m (m1, m2, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c +index e7f685bbcaa..43128266673 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) ++foo (uint8x16_t m1, uint8x16_t m2, uint8_t add, mve_pred16_t p) + { +- return vmlasq_m_n_u8 (a, b, c, p); ++ return vmlasq_m_n_u8 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) ++foo1 (uint8x16_t m1, uint8x16_t m2, uint8_t add, mve_pred16_t p) + { +- return vmlasq_m (a, b, c, p); ++ return vmlasq_m (m1, m2, add, p); ++} ++ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlast.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p) ++{ ++ return vmlasq_m (m1, m2, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmlast.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c +index 8bfe3c31096..0ab8e9f431f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlas.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c) ++foo (int16x8_t m1, int16x8_t m2, int16_t add) + { +- return vmlasq_n_s16 (a, b, c); ++ return vmlasq_n_s16 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vmlas.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlas.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c) ++foo1 (int16x8_t m1, int16x8_t m2, int16_t add) + { +- return vmlasq (a, b, c); ++ return vmlasq (m1, m2, add); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlas.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c +index db06182abec..88f1dc53682 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlas.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c) ++foo (int32x4_t m1, int32x4_t m2, int32_t add) + { +- return vmlasq_n_s32 (a, b, c); ++ return vmlasq_n_s32 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vmlas.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlas.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c) ++foo1 (int32x4_t m1, int32x4_t m2, int32_t add) + { +- return vmlasq (a, b, c); ++ return vmlasq (m1, m2, add); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlas.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c +index 3a151650ef4..a5cb99ebf50 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlas.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c) ++foo (int8x16_t m1, int8x16_t m2, int8_t add) + { +- return vmlasq_n_s8 (a, b, c); ++ return vmlasq_n_s8 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vmlas.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmlas.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c) ++foo1 (int8x16_t m1, int8x16_t m2, int8_t add) + { +- return vmlasq (a, b, c); ++ return vmlasq (m1, m2, add); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlas.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c +index b9444f2f6a3..f455fc10146 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlas.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint16x8_t b, uint16_t c) ++foo (uint16x8_t m1, uint16x8_t m2, uint16_t add) + { +- return vmlasq_n_u16 (a, b, c); ++ return vmlasq_n_u16 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vmlas.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmlas.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c) ++foo1 (uint16x8_t m1, uint16x8_t m2, uint16_t add) + { +- return vmlasq (a, b, c); ++ return vmlasq (m1, m2, add); ++} ++ ++/* ++**foo2: ++** ... ++** vmlas.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t m1, uint16x8_t m2) ++{ ++ return vmlasq (m1, m2, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlas.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c +index 5708a0658a6..561b4f7a24e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlas.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, uint32_t c) ++foo (uint32x4_t m1, uint32x4_t m2, uint32_t add) + { +- return vmlasq_n_u32 (a, b, c); ++ return vmlasq_n_u32 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vmlas.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmlas.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c) ++foo1 (uint32x4_t m1, uint32x4_t m2, uint32_t add) + { +- return vmlasq (a, b, c); ++ return vmlasq (m1, m2, add); ++} ++ ++/* ++**foo2: ++** ... ++** vmlas.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t m1, uint32x4_t m2) ++{ ++ return vmlasq (m1, m2, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlas.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c +index d83940c7232..414cba1fba8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlas.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint8x16_t b, uint8_t c) ++foo (uint8x16_t m1, uint8x16_t m2, uint8_t add) + { +- return vmlasq_n_u8 (a, b, c); ++ return vmlasq_n_u8 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vmlas.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmlas.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c) ++foo1 (uint8x16_t m1, uint8x16_t m2, uint8_t add) + { +- return vmlasq (a, b, c); ++ return vmlasq (m1, m2, add); ++} ++ ++/* ++**foo2: ++** ... ++** vmlas.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t m1, uint8x16_t m2) ++{ ++ return vmlasq (m1, m2, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmlas.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c +index 3b250c1bf79..e8d1b5fd3d0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsdavaq_p_s16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsdavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */ +-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c +index 077c5980e66..effbf24d997 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsdavaq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsdavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */ +-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c +index 2e53f5530b1..de04f9fd089 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vmlsdavaq_p_s8 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vmlsdavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */ +-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c +index e127be940b4..f66f652f6fd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b, int16x8_t c) + { + return vmlsdavaq_s16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b, int16x8_t c) + { + return vmlsdavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c +index 20f879c6b69..79ba85ddb02 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, int32x4_t c) + { + return vmlsdavaq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, int32x4_t c) + { + return vmlsdavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c +index 3cbed73f660..3e0f9dc2649 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b, int8x16_t c) + { + return vmlsdavaq_s8 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b, int8x16_t c) + { + return vmlsdavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdava.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c +index 37aee878b97..61e88ce8fb8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsdavaxq_p_s16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsdavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */ +-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c +index 6a15d3cf97b..cbc2c71423e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsdavaxq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsdavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */ +-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c +index d090e625e1b..2b30e8a9c12 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vmlsdavaxq_p_s8 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) + { + return vmlsdavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */ +-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c +index 0ef5302ef80..90fd85a170e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int16x8_t b, int16x8_t c) + { + return vmlsdavaxq_s16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int16x8_t b, int16x8_t c) + { + return vmlsdavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c +index 71a5e1a987f..06fe27faf49 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int32x4_t b, int32x4_t c) + { + return vmlsdavaxq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int32x4_t b, int32x4_t c) + { + return vmlsdavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c +index 7df6b9f7f32..70a44b49d8e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32_t a, int8x16_t b, int8x16_t c) + { + return vmlsdavaxq_s8 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32_t a, int8x16_t b, int8x16_t c) + { + return vmlsdavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsdavax.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c +index f71dda19c57..09db9a3a90a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsdavq_p_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsdavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c +index 255235ba372..8eb9d24263a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsdavq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsdavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c +index 2fc892db2eb..166fedea45c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmlsdavq_p_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmlsdavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c +index 7376b07865b..b97252f7225 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a, int16x8_t b) + { + return vmlsdavq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmlsdavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c +index a37042eab30..5473cfe22fc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a, int32x4_t b) + { + return vmlsdavq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmlsdavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c +index b44b98bc7e4..487097118fd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a, int8x16_t b) + { + return vmlsdavq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a, int8x16_t b) + { + return vmlsdavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdav.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c +index aa4ac4e4f01..d1ff9a0fa1c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsdavxq_p_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsdavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c +index 0de81290d99..09c19c1f161 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsdavxq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsdavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c +index 68588f6951a..1f364a3e846 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmlsdavxq_p_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsdavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmlsdavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c +index 8f49d6a6106..1c0675fb44b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int16x8_t a, int16x8_t b) + { + return vmlsdavxq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmlsdavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c +index 830cd4ca8b1..5986e130ec0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int32x4_t a, int32x4_t b) + { + return vmlsdavxq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmlsdavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c +index 74feb60b005..4f8aa44b57a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsdavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo (int8x16_t a, int8x16_t b) + { + return vmlsdavxq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmlsdavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32_t + foo1 (int8x16_t a, int8x16_t b) + { + return vmlsdavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsdavx.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c +index 78d29b058a3..8d0a03c0213 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsldavaq_p_s16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavat.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsldavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavat.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c +index fca0ef1d3dc..fae2ad5c713 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsldavaq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsldavaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavat.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c +index aecfcee4571..bfe4010df68 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int16x8_t b, int16x8_t c) + { + return vmlsldavaq_s16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldava.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int16x8_t b, int16x8_t c) + { + return vmlsldavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldava.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c +index 7344a50f02b..b023b1b67ee 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vmlsldavaq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldava.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vmlsldavaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldava.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c +index 5278bd842cc..1ffa8c28ea9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsldavaxq_p_s16 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) + { + return vmlsldavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c +index 07efdf96f10..aa5001705c1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsldavaxq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vmlsldavaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c +index 6a51d9f3d93..7772b3da069 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int16x8_t b, int16x8_t c) + { + return vmlsldavaxq_s16 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldavax.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int16x8_t b, int16x8_t c) + { + return vmlsldavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldavax.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c +index 275776388d2..eba923f15d8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vmlsldavaxq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldavax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vmlsldavaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vmlsldavax.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c +index 6eedf07efd6..79ed4c94b64 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsldavq_p_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsldavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c +index b36ea49612c..44982f89edf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsldavq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsldavq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c +index f05841798c9..dbdf1deae04 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int16x8_t a, int16x8_t b) + { + return vmlsldavq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldav.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmlsldavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldav.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c +index 45bee16ab79..458f14c446f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vmlsldavq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldav.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmlsldavq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldav.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c +index 821f4eae90a..9481550f526 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsldavxq_p_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmlsldavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c +index 77e84d07486..cc20e554932 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsldavxq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmlsldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmlsldavxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c +index dcd88f8db73..7a4d9365ed6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int16x8_t a, int16x8_t b) + { + return vmlsldavxq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldavx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmlsldavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldavx.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c +index d59550ba69e..b241569d75c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmlsldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vmlsldavxq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldavx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmlsldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmlsldavxq (a, b); + } + +-/* { dg-final { scan-assembler "vmlsldavx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c +index b7ce6ce9c2a..69c2f91b50e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmovlbq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmovlbq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c +index d15df32831d..2b3cfacb5f3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmovlbq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmovlbq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c +index dcd9dc43692..39398b2cde9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmovlbq_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmovlbq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c +index dbdeb263086..30ca18ad103 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmovlbq_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmovlbq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c +index a6b5cbb1527..8ce0da68113 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a) + { + return vmovlbq_s16 (a); + } + +-/* { dg-final { scan-assembler "vmovlb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmovlb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a) + { + return vmovlbq (a); + } + +-/* { dg-final { scan-assembler "vmovlb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c +index 4ead765bb6e..36fbce37bf8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlb.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a) + { + return vmovlbq_s8 (a); + } + +-/* { dg-final { scan-assembler "vmovlb.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmovlb.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a) + { + return vmovlbq (a); + } + +-/* { dg-final { scan-assembler "vmovlb.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c +index fec88bb7f79..b90728e9956 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlb.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a) + { +- return vmovlbq_u16 (a); ++ return vmovlbq_u16 (a); + } + +-/* { dg-final { scan-assembler "vmovlb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmovlb.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a) + { +- return vmovlbq (a); ++ return vmovlbq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmovlb.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c +index af6d804696a..5299f581329 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlb.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a) + { +- return vmovlbq_u8 (a); ++ return vmovlbq_u8 (a); + } + +-/* { dg-final { scan-assembler "vmovlb.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmovlb.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a) + { +- return vmovlbq (a); ++ return vmovlbq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmovlb.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c +index 393fc5523a7..63d2ddb9015 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, mve_pred16_t p) + { + return vmovlbq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vmovlbq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c +index 3773be0b621..b573f572012 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, mve_pred16_t p) + { + return vmovlbq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vmovlbq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c +index b668eeb6fcf..f039019f5b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vmovlbq_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vmovlbq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c +index 6019e2d09d7..7fb32ece22d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vmovlbq_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovlbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vmovlbq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c +index 47897a3913f..72ca8c8bb9b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmovltq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmovltq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c +index c87b263db51..7e3b4f40bc5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmovltq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmovltq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c +index cfe7cd7a5d3..4320df794ab 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmovltq_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmovltq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c +index a9119fbb940..c9a75a590b2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmovltq_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmovltq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c +index a7fd325e330..f431cda53ac 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a) + { + return vmovltq_s16 (a); + } + +-/* { dg-final { scan-assembler "vmovlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmovlt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a) + { + return vmovltq (a); + } + +-/* { dg-final { scan-assembler "vmovlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c +index c392e56b60b..d65f8066454 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a) + { + return vmovltq_s8 (a); + } + +-/* { dg-final { scan-assembler "vmovlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmovlt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a) + { + return vmovltq (a); + } + +-/* { dg-final { scan-assembler "vmovlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c +index 7634af6f45a..5469671041b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a) + { +- return vmovltq_u16 (a); ++ return vmovltq_u16 (a); + } + +-/* { dg-final { scan-assembler "vmovlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmovlt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a) + { +- return vmovltq (a); ++ return vmovltq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmovlt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c +index 2c0d1a7c69d..a14c71cdfbc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovlt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a) + { +- return vmovltq_u8 (a); ++ return vmovltq_u8 (a); + } + +-/* { dg-final { scan-assembler "vmovlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmovlt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a) + { +- return vmovltq (a); ++ return vmovltq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmovlt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c +index ae6c8999835..f8e24c4e0d3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, mve_pred16_t p) + { + return vmovltq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vmovltq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c +index 1172643218a..b97de081858 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, mve_pred16_t p) + { + return vmovltq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vmovltq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c +index 64442dcf935..851264e45ed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vmovltq_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vmovltq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c +index 33e571890c0..82219b670db 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vmovltq_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vmovltq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c +index fdb392cbf81..3bd9b82cbb3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vmovnbq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c +index 9f32f49d24e..bc2f95c7d8a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vmovnbq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c +index ebc1599af54..1624237c67a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vmovnbq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c +index 502068713e9..1a2f1e8441e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vmovnbq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c +index a49943fd25a..d5286f11259 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vmovnbq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c +index 6dbce232399..b6b44837b8c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vmovnbq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c +index f3df71a43eb..1203ac5c7f5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vmovnbq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c +index e0369ed5fa2..de5bb111783 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vmovnbq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnb.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c +index f305ab30dc8..594f72c08f5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vmovntq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c +index 59820c610e6..b3e3e0442c5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vmovntq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c +index 079b162148e..a3e33db311e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vmovntq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c +index 7c09b2e4f9f..b5629493c72 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vmovntq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmovntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c +index 229cd5809d9..d7e369d266e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vmovntq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c +index 01921cbd66e..6d87cc21aaa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vmovntq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c +index 30e75b2169d..f85e45a666a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vmovntq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c +index 9ed963dda70..05c4af3d614 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vmovntq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vmovnt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c +index 4971869a27b..a7d8460c265 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulhq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c +index 3006de7fd24..997fdbe8d23 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulhq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c +index fbcef24ffc3..567461ff111 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulhq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c +index 7059fecf047..9b813829cd6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulhq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c +index 1c2de7081cf..248432a2fe0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulhq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c +index 5eed85fb2d9..464180c1988 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulhq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c +index a7260df0f51..0950c06ee05 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vmulhq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c +index 4fe46e62fc8..db2ab42a1e9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vmulhq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c +index acc08039bb5..8bb2239005f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vmulhq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c +index 37e40f06d72..bb88136589c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vmulhq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c +index 5673d91486c..d42c41acb73 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vmulhq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c +index 29c6312bb7c..c666a9631af 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vmulhq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vmulh.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c +index b783570be19..a323c961838 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulhq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c +index 003485be70b..98168b1be06 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulhq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c +index d2359cd371b..b50f59b3df4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulhq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c +index c052c4ac007..afa803c2917 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulhq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c +index 7eeba8be611..221795478cd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulhq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c +index ff2a53fc160..4383e2e7574 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulhq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulht.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c +index be933274d77..a4cc5e52773 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmullbq_int_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmullbq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c +index 3dfc26761be..a195884567b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmullbq_int_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmullbq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c +index f8c449b28a0..3a5d7705d45 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmullbq_int_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmullbq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c +index dd6ed6b71a6..5e327d25a9b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmullbq_int_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmullbq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c +index 85ce75e7dd8..fb2de994dd8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmullbq_int_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmullbq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c +index d131a5d9fd7..4cc06c4ef28 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmullbq_int_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmullbq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c +index 22f4d27f6cc..16c0982386b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullb.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, int16x8_t b) + { + return vmullbq_int_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmullb.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmullbq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c +index 6e677f26b84..e0a82d6e640 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullb.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int32x4_t a, int32x4_t b) + { + return vmullbq_int_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmullb.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmullbq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c +index f40b8a6c4dd..031a433c2bb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullb.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, int8x16_t b) + { + return vmullbq_int_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmullb.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a, int8x16_t b) + { + return vmullbq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c +index 3529ab2772d..4bb19bf5cff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullb.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, uint16x8_t b) + { + return vmullbq_int_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmullb.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vmullbq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c +index d843d2bf5fe..d461ed9f9c7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullb.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint32x4_t a, uint32x4_t b) + { + return vmullbq_int_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmullb.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vmullbq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c +index 6268c463ead..c0790778b2d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullb.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, uint8x16_t b) + { + return vmullbq_int_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmullb.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vmullbq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c +index 87f8e21a7d0..ee83ca61158 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmullbq_int_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmullbq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c +index 5e563728a4a..42ae3324cd9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmullbq_int_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmullbq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c +index b2ca4134ee5..8dcf9b726b0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmullbq_int_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmullbq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c +index 15269101fe5..31330da9a93 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmullbq_int_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmullbq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c +index 7a7836303ec..b882d644347 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmullbq_int_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmullbq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c +index f422a3c66f0..4b402374eb7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmullbq_int_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmullbq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c +index 527acb74e09..2efb87dff01 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmullbq_poly_m_p16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.p16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmullbq_poly_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.p16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c +index 5403394e870..b435f44cb32 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmullbq_poly_m_p8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.p8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmullbq_poly_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.p8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c +index d01d5997ff4..bfd052222fe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullb.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, uint16x8_t b) + { + return vmullbq_poly_p16 (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.p16" } } */ + ++/* ++**foo1: ++** ... ++** vmullb.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vmullbq_poly (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.p16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c +index de97134add7..a2a53e8a3dc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullb.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, uint8x16_t b) + { + return vmullbq_poly_p8 (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.p8" } } */ + ++/* ++**foo1: ++** ... ++** vmullb.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vmullbq_poly (a, b); + } + +-/* { dg-final { scan-assembler "vmullb.p8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c +index f94d9052433..bee45f95939 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmullbq_poly_x_p16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.p16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmullbq_poly_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c +index 6fdc94496bc..7cd15f3a7f1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmullbq_poly_x_p8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmullbt.p8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmullbt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmullbq_poly_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c +index 25ecf7a2c51..7f573e9109e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulltq_int_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulltq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c +index f8d02880ea0..da440dd1365 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulltq_int_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulltq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c +index 3f2fc333a65..ceb8e1d5a94 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulltq_int_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulltq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c +index b7ab408d53c..a751546ae13 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulltq_int_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulltq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c +index e43ad98d933..a6c4d272968 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulltq_int_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulltq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c +index 7f4b90b08dd..1a7466bb5b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulltq_int_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulltq_int_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c +index 34b75d4abc8..cd907f6224c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, int16x8_t b) + { + return vmulltq_int_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmullt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmulltq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c +index 7e09bf93e0e..dbc4c80b440 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int32x4_t a, int32x4_t b) + { + return vmulltq_int_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmullt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmulltq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c +index b6eb1f5e7f2..0fef6a21207 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, int8x16_t b) + { + return vmulltq_int_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmullt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a, int8x16_t b) + { + return vmulltq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c +index f4fc9c0c634..91b6fb4595d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, uint16x8_t b) + { + return vmulltq_int_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmullt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vmulltq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c +index d1bc3a8f990..71c62a12afb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint32x4_t a, uint32x4_t b) + { + return vmulltq_int_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmullt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vmulltq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c +index 87f3c4e386a..7506adce33e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, uint8x16_t b) + { + return vmulltq_int_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmullt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vmulltq_int (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c +index c13ef50147e..c2376abe268 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulltq_int_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulltq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c +index e82321ecb79..788789db120 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulltq_int_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulltq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c +index 7f093c26080..3935741d041 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulltq_int_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulltq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c +index d0f6461448b..32ee5b2e4e8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulltq_int_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulltq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c +index 55e19cb204a..cc3105650a1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulltq_int_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulltq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c +index 650c9471c7e..01713fba245 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulltq_int_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulltq_int_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c +index 944db4c2fab..6d368e2ba68 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulltq_poly_m_p16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.p16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulltq_poly_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.p16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c +index d07311943c2..75b8811fdd9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulltq_poly_m_p8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.p8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulltq_poly_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.p8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c +index 121de8e9c0e..9f08d57eef9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, uint16x8_t b) + { + return vmulltq_poly_p16 (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.p16" } } */ + ++/* ++**foo1: ++** ... ++** vmullt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vmulltq_poly (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.p16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c +index c7d9548a8ab..59e6e1bb6e0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmullt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, uint8x16_t b) + { + return vmulltq_poly_p8 (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.p8" } } */ + ++/* ++**foo1: ++** ... ++** vmullt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vmulltq_poly (a, b); + } + +-/* { dg-final { scan-assembler "vmullt.p8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c +index fb4b849b8b0..f3d3de2d1d6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulltq_poly_x_p16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.p16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.p16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulltq_poly_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c +index 1e79b2987c9..2c7a6294540 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulltq_poly_x_p8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmulltt.p8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmulltt.p8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulltq_poly_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c +index 68fb012ad34..3c9b82deed5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vmulq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmul.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c +index 512661aeec7..adebaee5f00 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vmulq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmul.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c +index d05d48f6261..4737ac3c75b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmulq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c +index 8c2ec81da3b..2c09a9ee90a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmulq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c +deleted file mode 100644 +index c8222c5c7b9..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vmulq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c +index 1f1d408d5b9..8de0d38f97c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) + { + return vmulq_m_n_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) ++{ ++ return vmulq_m (inactive, a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c +deleted file mode 100644 +index 2fae3a7f8fa..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vmulq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c +index 4aae0849e2b..36e9aa99b33 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) + { + return vmulq_m_n_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) ++{ ++ return vmulq_m (inactive, a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c +index 9a87f7d3643..163d4259338 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vmulq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c +index da7d38b9968..89e4c212147 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vmulq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c +index 227b3a50a92..4055959ec8e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vmulq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c +index e09334df1de..2ea47a6df96 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vmulq_m_n_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) ++{ ++ return vmulq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c +index 62d6c262e5a..c818c4556d8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vmulq_m_n_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) ++{ ++ return vmulq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c +index e7993ab3c31..d0380864af6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vmulq_m_n_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) ++{ ++ return vmulq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c +index 61cdf656c19..72f5d3cefc3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c +index 622407b96da..2ee86e9e163 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c +index bb2943cc727..6356f4adce0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c +index a0680174753..903bccbf0ca 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c +index 586a32560d7..8d386c0727a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c +index 0a8e49a5982..de3f6096fa4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c +deleted file mode 100644 +index cef311d981d..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vmulq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c +index a3f693f06f7..e4efd6b279f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16_t b) + { + return vmulq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmul.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.f16" } } */ ++/* ++**foo2: ++** ... ++** vmul.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t a) ++{ ++ return vmulq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c +deleted file mode 100644 +index d6d4b9a0a7c..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vmulq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c +index 5d1cfa368a7..97c71ab0a2c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32_t b) + { + return vmulq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmul.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.f32" } } */ ++/* ++**foo2: ++** ... ++** vmul.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t a) ++{ ++ return vmulq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c +index 98e84cbf202..c2f3c1df51c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b) + { + return vmulq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c +index adbfd6fe10b..50b5f0c0ccb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vmulq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c +index c845f108f88..425b576caf7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b) + { + return vmulq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c +index e52acdc53b9..1e02ad0077c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b) + { + return vmulq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i16" } } */ ++/* ++**foo2: ++** ... ++** vmul.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a) ++{ ++ return vmulq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c +index 9da4bc1f359..6a05f542a37 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b) + { + return vmulq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i32" } } */ ++/* ++**foo2: ++** ... ++** vmul.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a) ++{ ++ return vmulq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c +index e0f152db729..7ba29e6a482 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b) + { + return vmulq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i8" } } */ ++/* ++**foo2: ++** ... ++** vmul.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a) ++{ ++ return vmulq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c +index 89cc604fda0..026bbaecc9e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vmulq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c +index f87fbf1249c..75a17e07cf0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vmulq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c +index 4e40065ad22..a7762893e93 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vmulq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c +index ae95bf68afe..4150c390fab 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vmulq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c +index 4f8e9762d5f..3bdc5df35c4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vmulq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c +index a3776ff8314..dc988fd9b4a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmul.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vmulq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmul.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vmulq (a, b); + } + +-/* { dg-final { scan-assembler "vmul.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c +index 1f864cf481a..bde0536d9cf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmulq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c +index 07cc3d0277c..162569cbad4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmulq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c +deleted file mode 100644 +index ea4cab03490..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vmulq_x (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c +index 8fa6c759d54..b37a9ae7411 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vmulq_x_n_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vmulq_x (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c +deleted file mode 100644 +index a7a54c7c92c..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vmulq_x (a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c +index 654713c1348..a2be895bea5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vmulq_x_n_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.f32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t a, mve_pred16_t p) ++{ ++ return vmulq_x (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c +index 4ec5ab397e1..70e169975c5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vmulq_x_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c +index c52180067cf..4e3e2320c10 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vmulq_x_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c +index a2a7c734de8..a7a2cca4e59 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vmulq_x_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c +index 419a3cb6ea6..76b8a7e0f11 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vmulq_x_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vmulq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c +index 5acfcf6bf61..cba98561403 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vmulq_x_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vmulq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c +index 27e95ced0b5..33836662b2d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vmulq_x_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vmulq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c +index 5c232bfdc34..a1a60030a2a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c +index 685fe45e4d0..f3a2917bd45 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c +index 19ecc6bcafc..cdd311d41a0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c +index 0700ca818ab..c8d4eed010e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c +index a1cb2aa221e..497e542f9ea 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c +index 3b29852c830..e54b95f5ee4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmult.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vmulq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmult.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c +index 1b6e683700c..9d4804a0057 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, mve_pred16_t p) + { +- return vmvnq_m_n_s16 (inactive, 2, p); ++ return vmvnq_m_n_s16 (inactive, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, mve_pred16_t p) + { +- return vmvnq_m (inactive, 2, p); ++ return vmvnq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c +index dcfd69fb7f1..607cdfca33e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, mve_pred16_t p) + { +- return vmvnq_m_n_s32 (inactive, 2, p); ++ return vmvnq_m_n_s32 (inactive, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, mve_pred16_t p) + { +- return vmvnq_m (inactive, 2, p); ++ return vmvnq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c +index bd86fa806b8..7b0b5a9ef83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, mve_pred16_t p) + { +- return vmvnq_m_n_u16 (inactive, 4, p); ++ return vmvnq_m_n_u16 (inactive, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, mve_pred16_t p) + { +- return vmvnq_m (inactive, 4, p); ++ return vmvnq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c +index 2ac6ef192d7..2217420081e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, mve_pred16_t p) + { +- return vmvnq_m_n_u32 (inactive, 4, p); ++ return vmvnq_m_n_u32 (inactive, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, mve_pred16_t p) + { +- return vmvnq_m (inactive, 4, p); ++ return vmvnq_m (inactive, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c +index 5284b8fe054..e27d8111b54 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmvnq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c +index da16a5d45d6..8a264a1e76f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vmvnq_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c +index 206759247c5..c4374d0ffd4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmvnq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c +index 9940cec4bfe..3d5d56eadfe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmvnq_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c +index 25179f13f95..fd1961e0673 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vmvnq_m_u32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c +index 7237db35b33..037d1f4ce39 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmvnq_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vmvnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c +index 336c6aa63c4..975639334d5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo () + { + return vmvnq_n_s16 (1); + } + +-/* { dg-final { scan-assembler "vmvn.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c +index 354c39c8f7b..0e09343e6c3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo () + { +- return vmvnq_n_s32 (2); ++ return vmvnq_n_s32 (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c +index 178b003091b..84e158ade93 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo () + { +- return vmvnq_n_u16 (1); ++ return vmvnq_n_u16 (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c +index 4819066bdbd..168b77a400a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c +@@ -1,13 +1,28 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo () + { +- return vmvnq_n_u32 (2); ++ return vmvnq_n_u32 (1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c +index 840d834ea9e..30ddcd9118e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vmvnq_s16 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vmvnq (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c +index cf73bc088c7..48d66753c0f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vmvnq_s32 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vmvnq (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c +index 6d239391cbb..199bb0f81c3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vmvnq_s8 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vmvnq (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c +index db348328513..c2d724f5375 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vmvnq_u16 (a); ++ return vmvnq_u16 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vmvnq (a); ++ return vmvnq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c +index c007a959078..8bafe68f21c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vmvnq_u32 (a); ++ return vmvnq_u32 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { +- return vmvnq (a); ++ return vmvnq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c +index 2288a283d60..684e5bc94f1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vmvnq_u8 (a); ++ return vmvnq_u8 (a); + } + +-/* { dg-final { scan-assembler "vmvn" } } */ + ++/* ++**foo1: ++** ... ++** vmvn q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vmvnq (a); ++ return vmvnq (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vmvn" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c +index b00ccc3e672..a4d575e4aba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (mve_pred16_t p) + { +- return vmvnq_x_n_s16 (2, p); ++ return vmvnq_x_n_s16 (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c +index ea65104b4b3..9ca5c90d80e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (mve_pred16_t p) + { +- return vmvnq_x_n_s32 (2, p); ++ return vmvnq_x_n_s32 (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c +index 2fa4e40ad5d..9fbf2b978ac 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (mve_pred16_t p) + { +- return vmvnq_x_n_u16 (4, p); ++ return vmvnq_x_n_u16 (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c +index b39e681c116..883e9af1609 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c +@@ -1,14 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (mve_pred16_t p) + { +- return vmvnq_x_n_u32 (4, p); ++ return vmvnq_x_n_u32 (1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c +index d4b87a795fc..6bd04f7dd38 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vmvnq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c +index 0bcdba0c1d6..6af90408e9c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vmvnq_x_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c +index ffa7306ace6..8c6f118c36f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vmvnq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c +index 29b5ad950ea..2e9902f3858 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vmvnq_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c +index b3d5f73cd92..53b2ebdd457 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vmvnq_x_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c +index f085aa83662..ad7a5a9398c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vmvnq_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vmvnt q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vmvnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vmvnt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c +index 9572c140d7e..9853cf6e6dd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vneg.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vnegq_f16 (a); + } + +-/* { dg-final { scan-assembler "vneg.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vneg.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vnegq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c +index be73cc0c5f5..489cfc760ba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vneg.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vnegq_f32 (a); + } + +-/* { dg-final { scan-assembler "vneg.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vneg.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vnegq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c +index 0d917b80cd7..c8b307ea50e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vnegq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vnegq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c +index f1c0e9a99b0..a530a05e644 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vnegq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vnegq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c +index 9a945ee62a3..46d6e794dbe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vnegq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vnegq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c +index 811f1df0565..5fb1f5c2a4c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vnegq_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vnegq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c +index 430ebc73783..868a9680858 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vnegq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vnegq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c +index a47f9b3423e..3b518c8e0f5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vneg.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vnegq_s16 (a); + } + +-/* { dg-final { scan-assembler "vneg.s16" } } */ + ++/* ++**foo1: ++** ... ++** vneg.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vnegq (a); + } + +-/* { dg-final { scan-assembler "vneg.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c +index 50401f53bd7..f8682575892 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vneg.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vnegq_s32 (a); + } + +-/* { dg-final { scan-assembler "vneg.s32" } } */ + ++/* ++**foo1: ++** ... ++** vneg.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vnegq (a); + } + +-/* { dg-final { scan-assembler "vneg.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c +index fd5de3dab56..1be5901740e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vneg.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vnegq_s8 (a); + } + +-/* { dg-final { scan-assembler "vneg.s8" } } */ + ++/* ++**foo1: ++** ... ++** vneg.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vnegq (a); + } + +-/* { dg-final { scan-assembler "vneg.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c +index e7af36691dc..c10d6d2aebf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vnegq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vnegq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c +index d9c3818855a..0ee5ecc8262 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vnegq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vnegq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c +index 16f1fa452ce..d774a055d72 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vnegq_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vnegq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c +index d74683c6f24..77bf1a67cfe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vnegq_x_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vnegq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c +index eda4c7fcf7e..ca44512e37a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vnegq_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vnegt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vnegq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c +index 7cf00d94084..36543ee6bff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vornq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c +index d187bde1dc2..c3d73059c31 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vornq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c +index 081872bada1..7a5cabf4396 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vornq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c +index fe92dae6ec6..8fb90212c88 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vornq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c +index 56a2b64bc29..31123f853f8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vornq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c +index c2e4b1267b8..e5d6d63955b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vornq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c +index 6607808e96e..73bde2bcfde 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vornq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c +index 1905ed193ac..2872c0a7045 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vornq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c +index 6d6620c3e07..90e8df24b99 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vornq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c +index 23e8d046c73..eedbf3a1ae1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vornq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vornq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c +index 0f73ea28e0d..ac92a93f19c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vornq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c +index 7d9835fc1b8..38be3483872 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vornq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c +index f2ba62292f5..3d5e47fa1e4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vornq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c +index baa3fd80813..e69212d59b0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vornq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c +index 481db437b77..c89622c830f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vornq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c +index 575a7365487..61ce5ad294a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vornq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ + ++/* ++**foo1: ++** ... ++** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vornq (a, b); + } + +-/* { dg-final { scan-assembler "vorn" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c +index d776bff2416..2bc10776f6d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vornq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c +index 939e8fafb83..7b733cf6a6b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vornq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c +index 77569b42cc8..beba497bbf9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vornq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c +index 29cfd020c30..60e6125ed6e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vornq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c +index fd10ff8e719..f62c9b2a111 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vornq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c +index 473f22abd52..2ac693ca30f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vornq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c +index 010ac07454d..1981c8ca408 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vornq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c +index 126a6d236b3..171dc0f58b6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vornq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vornt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vornq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c +index 1481c43ae5f..3d222d5679b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vorrq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c +index 257edd99b7b..140817ee919 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vorrq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c +index 641c8f0f3bd..dbfac724131 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vorrq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c +index b537a7c74c3..e13a1df44e2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vorrq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c +index 757482a3a95..b591bd6fc11 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vorrq_m_n_s16 (a, 253, p); ++ return vorrq_m_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { +- return vorrq_m_n (a, 253, p); ++ return vorrq_m_n (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c +index 967e49e7a26..ce4dd3ee7bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vorrq_m_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vorrq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c +index 01022c32a88..9e7788484ad 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vorrq_m_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vorrq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c +index 809237d1cf6..613c0e2f889 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vorrq_m_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vorrq_m_n (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c +index 2714810d591..d475f1e939f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vorrq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c +index c960b18631a..e171e93e4eb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vorrq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c +index d1d4bc721b0..17043b26c2e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vorrq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c +index 01190ea4812..19a752ec3b7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vorrq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c +index 502ceab2fe4..7f3985d1508 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vorrq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c +index 44cf1413ca6..5a04ebdf1de 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vorrq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vorrq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c +index 63a369f9996..b95418d9668 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vorrq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vorr.i16" } } */ ++ ++/* ++**foo1: ++** ... ++** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a) ++{ ++ return vorrq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c +index cf7bbc8c46d..30248216012 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vorrq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vorr.i32" } } */ ++ ++/* ++**foo1: ++** ... ++** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a) ++{ ++ return vorrq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c +index 2d599e52f8d..1f131501aec 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { + return vorrq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vorr.i16" } } */ ++ ++/* ++**foo1: ++** ... ++** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a) ++{ ++ return vorrq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c +index 5a873d0d1a3..5bfdb0b2e14 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vorrq_n_u32 (a, 44); ++ return vorrq_n_u32 (a, 1); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint32x4_t a) ++{ ++ return vorrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vorr.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c +index 2a56912ab31..658df6f422f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vorrq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c +index e80b991c95a..a0a24b7fd45 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vorrq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c +index 3456477c07c..645c6144f46 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vorrq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c +index bb7699c1e3b..cb618a1f793 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vorrq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c +index e01f5413dc3..937102ff962 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vorrq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c +index c7ad98805c4..07121b5b1c9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vorrq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ + ++/* ++**foo1: ++** ... ++** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vorrq (a, b); + } + +-/* { dg-final { scan-assembler "vorr" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c +index 2e678febb78..b34d102f470 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vorrq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c +index 12acfb49773..d41a94e7a02 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vorrq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c +index 75fe4541845..3e1d3e97d26 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vorrq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c +index 37d17f046af..0982b3d2081 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vorrq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c +index 3558db3b7b0..0a46246e124 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vorrq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c +index 7c9a2559c87..ef83d9de2ee 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vorrq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c +index 13ff34d582a..b6abfd5b314 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vorrq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c +index 781b2b59699..b724ed0562b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vorrq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vorrt" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vorrq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c +index a84f84446c0..2b894d1d938 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c +@@ -1,21 +1,32 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpnot(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) ++** ... ++*/ + mve_pred16_t + foo (mve_pred16_t a) + { + return vpnot (a); + } + +-/* { dg-final { scan-assembler "vpnot" } } */ +- +-mve_pred16_t +-foo1 (mve_pred16_t a) +-{ +- return vpnot (a); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpnot" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c +index ff121b585ed..50127b4537d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vpselq_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c +index 35c84761f08..0733413f1ca 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vpselq_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c +index 0e0c14ed49d..06ef70c4073 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vpselq_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c +index 0e746de6e07..87b4b2242eb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vpselq_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c +index f4bbb77e268..dedb812c11b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int64x2_t a, int64x2_t b, mve_pred16_t p) + { + return vpselq_s64 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int64x2_t a, int64x2_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c +index 65cd415c789..5050fc03556 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vpselq_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c +index 742ca17ac8e..055f3c00381 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vpselq_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c +index 9d2e01c31d4..11333822b19 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vpselq_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c +index 58c4169bc0a..c08e6c54d95 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint64x2_t a, uint64x2_t b, mve_pred16_t p) + { + return vpselq_u64 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64x2_t + foo1 (uint64x2_t a, uint64x2_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c +index 5f73ba44ea8..804aed384c8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c +@@ -1,21 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vpselq_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vpselq (a, b, p); + } + +-/* { dg-final { scan-assembler "vpsel" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c +index e74e04ac92f..7172ac5cddd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqabst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vqabsq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqabst.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqabst.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vqabsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c +index f6ca8a6c3d6..297cb196f1a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqabst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vqabsq_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqabst.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqabst.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vqabsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c +index d89a5aa3fa5..83c69931239 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqabst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vqabsq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqabst.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqabst.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vqabsq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c +index e67c008cf6e..bf849fe9354 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqabs.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vqabsq_s16 (a); + } + +-/* { dg-final { scan-assembler "vqabs.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqabs.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vqabsq (a); + } + +-/* { dg-final { scan-assembler "vqabs.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c +index 8023ff8d22e..1f88821de23 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqabs.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vqabsq_s32 (a); + } + +-/* { dg-final { scan-assembler "vqabs.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqabs.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vqabsq (a); + } + +-/* { dg-final { scan-assembler "vqabs.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c +index b36d2b762e9..1399f7c1636 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqabs.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vqabsq_s8 (a); + } + +-/* { dg-final { scan-assembler "vqabs.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqabs.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vqabsq (a); + } + +-/* { dg-final { scan-assembler "vqabs.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c +index 65d3f770fe2..8884a7c8318 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqaddq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c +index 4499a0eaa41..77d4b36b94c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqaddq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c +index d3e1d555cb1..943fae8657f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vqaddq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c +index baadfe72e8d..b8808066322 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vqaddq_m_n_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) ++{ ++ return vqaddq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c +index 80808777d9a..b9815bd5ca3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vqaddq_m_n_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) ++{ ++ return vqaddq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c +index 32f2894422d..674d0c578ff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vqaddq_m_n_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) ++{ ++ return vqaddq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c +index d5b7fa63f6a..ce1cedd7e1e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqaddq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c +index 015bc3eb206..9b6717ef8f9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqaddq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c +index b241fddd069..46ce20b7cae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqaddq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c +index fa752355d64..ed1ffbf8721 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vqaddq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c +index 0729b6bb30f..50450ff3361 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vqaddq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c +index f1541658399..a260e96a95d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vqaddq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vqaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqaddt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c +index 5eeda2bc2dd..17b28cfd956 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b) + { + return vqaddq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c +index 5b914d18b98..e6bb4e0b51d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vqaddq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c +index 06f22c2b8df..f39451f6bc0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b) + { + return vqaddq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c +index 5403f0b6646..a87163c0446 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b) + { + return vqaddq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u16" } } */ ++/* ++**foo2: ++** ... ++** vqadd.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a) ++{ ++ return vqaddq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c +index 77185808a16..a6aa9b5dddc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b) + { + return vqaddq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u32" } } */ ++/* ++**foo2: ++** ... ++** vqadd.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a) ++{ ++ return vqaddq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c +index f0fa9bf3f5d..4bd47319f5e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b) + { + return vqaddq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u8" } } */ ++/* ++**foo2: ++** ... ++** vqadd.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a) ++{ ++ return vqaddq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c +index 83cd3475a6f..97e2a6039eb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vqaddq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c +index d26dd206912..db9355d56dd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vqaddq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c +index de03264b4cc..2804d668da8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vqaddq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c +index cd4efc1dd7c..17e59961c87 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vqaddq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c +index 8b3afb4bd04..ce3a397acd6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vqaddq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c +index da2ff1bb25c..faa881f67f6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vqaddq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vqaddq (a, b); + } + +-/* { dg-final { scan-assembler "vqadd.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c +index 51cdadc9ece..aa9c78c883b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmladhq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmladhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c +index 7e43fed1503..4694a6f9ec5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmladhq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmladhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c +index adf591041e3..c8dc67fdd12 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmladhq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmladhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c +index 2dc453bdd9a..74ebbfa8b97 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmladh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqdmladhq_s16 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmladh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqdmladhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c +index 06f3204e47e..796de4df283 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmladh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqdmladhq_s32 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmladh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqdmladhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c +index 79670b8b153..d585f5fac20 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmladh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqdmladhq_s8 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqdmladh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqdmladhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c +index c2446e69181..19c5ce5a64f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladhxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmladhxq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladhxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladhxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmladhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladhxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c +index 12b45517535..e00162addae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladhxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmladhxq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladhxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladhxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmladhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladhxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c +index 146aa51306b..19767d2cd41 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladhxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmladhxq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladhxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmladhxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmladhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmladhxt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c +index 5a6f4455c20..c6a2fa80670 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmladhx.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqdmladhxq_s16 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladhx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmladhx.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqdmladhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladhx.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c +index 4eafa6f9476..d38bd691243 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmladhx.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqdmladhxq_s32 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladhx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmladhx.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqdmladhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladhx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c +index cc6643574f4..322f702d962 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmladhx.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqdmladhxq_s8 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladhx.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqdmladhx.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqdmladhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmladhx.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c +index d8c4f4bab8e..42b3e25fc3d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlaht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p) + { +- return vqdmlahq_m_n_s16 (a, b, c, p); ++ return vqdmlahq_m_n_s16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlaht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlaht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p) + { +- return vqdmlahq_m (a, b, c, p); ++ return vqdmlahq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlaht.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c +index 361f5d00bdf..03e50f14e00 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlaht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p) + { +- return vqdmlahq_m_n_s32 (a, b, c, p); ++ return vqdmlahq_m_n_s32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlaht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlaht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p) + { +- return vqdmlahq_m (a, b, c, p); ++ return vqdmlahq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlaht.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c +index a9eaea89ba4..d7f8a153c63 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlaht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p) + { +- return vqdmlahq_m_n_s8 (a, b, c, p); ++ return vqdmlahq_m_n_s8 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlaht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlaht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p) + { +- return vqdmlahq_m (a, b, c, p); ++ return vqdmlahq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlaht.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c +index c109dd47444..909631c549d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlah.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c) ++foo (int16x8_t add, int16x8_t m1, int16_t m2) + { +- return vqdmlahq_n_s16 (a, b, c); ++ return vqdmlahq_n_s16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vqdmlah.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlah.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c) ++foo1 (int16x8_t add, int16x8_t m1, int16_t m2) + { +- return vqdmlahq (a, b, c); ++ return vqdmlahq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqdmlah.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c +index 752d9d9e3e0..fb670befeff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlah.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c) ++foo (int32x4_t add, int32x4_t m1, int32_t m2) + { +- return vqdmlahq_n_s32 (a, b, c); ++ return vqdmlahq_n_s32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vqdmlah.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlah.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c) ++foo1 (int32x4_t add, int32x4_t m1, int32_t m2) + { +- return vqdmlahq (a, b, c); ++ return vqdmlahq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqdmlah.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c +index 8dffa0e1852..f66740bee0b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlah.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c) ++foo (int8x16_t add, int8x16_t m1, int8_t m2) + { +- return vqdmlahq_n_s8 (a, b, c); ++ return vqdmlahq_n_s8 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vqdmlah.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlah.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c) ++foo1 (int8x16_t add, int8x16_t m1, int8_t m2) + { +- return vqdmlahq (a, b, c); ++ return vqdmlahq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqdmlah.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c +index 7c2e5cf89dd..918de9572e8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlasht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p) + { +- return vqdmlashq_m_n_s16 (a, b, c, p); ++ return vqdmlashq_m_n_s16 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlasht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlasht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p) + { +- return vqdmlashq_m (a, b, c, p); ++ return vqdmlashq_m (m1, m2, add, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlasht.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c +index cea9d9b683f..b25b66057bd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlasht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p) + { +- return vqdmlashq_m_n_s32 (a, b, c, p); ++ return vqdmlashq_m_n_s32 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlasht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlasht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p) + { +- return vqdmlashq_m (a, b, c, p); ++ return vqdmlashq_m (m1, m2, add, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlasht.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c +index 83ee258876a..b796f205e5d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlasht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p) + { +- return vqdmlashq_m_n_s8 (a, b, c, p); ++ return vqdmlashq_m_n_s8 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlasht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlasht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p) + { +- return vqdmlashq_m (a, b, c, p); ++ return vqdmlashq_m (m1, m2, add, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlasht.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c +index c71a61c54f6..9a2549464c5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlash.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c) ++foo (int16x8_t m1, int16x8_t m2, int16_t add) + { +- return vqdmlashq_n_s16 (a, b, c); ++ return vqdmlashq_n_s16 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vqdmlash.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlash.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c) ++foo1 (int16x8_t m1, int16x8_t m2, int16_t add) + { +- return vqdmlashq (a, b, c); ++ return vqdmlashq (m1, m2, add); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqdmlash.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c +index 61f6c6671cc..36fc7b066a1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlash.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c) ++foo (int32x4_t m1, int32x4_t m2, int32_t add) + { +- return vqdmlashq_n_s32 (a, b, c); ++ return vqdmlashq_n_s32 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vqdmlash.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlash.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c) ++foo1 (int32x4_t m1, int32x4_t m2, int32_t add) + { +- return vqdmlashq (a, b, c); ++ return vqdmlashq (m1, m2, add); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqdmlash.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c +index a07892863c1..1e7cd44d4f5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlash.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c) ++foo (int8x16_t m1, int8x16_t m2, int8_t add) + { +- return vqdmlashq_n_s8 (a, b, c); ++ return vqdmlashq_n_s8 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vqdmlash.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlash.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c) ++foo1 (int8x16_t m1, int8x16_t m2, int8_t add) + { +- return vqdmlashq (a, b, c); ++ return vqdmlashq (m1, m2, add); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqdmlash.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c +index d1e66864d10..f87287ab8cd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmlsdhq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmlsdhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c +index cc80f211ec8..8155aaf843c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmlsdhq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmlsdhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c +index 5c9d81a6526..d39badc7707 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmlsdhq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmlsdhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c +index eb058fb9789..a4fa1d5024b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlsdh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqdmlsdhq_s16 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlsdh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqdmlsdhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c +index 27b93d6b76c..0c6ba426ded 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlsdh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqdmlsdhq_s32 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlsdh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqdmlsdhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c +index 1dd2a59ee4b..089c4cdcc39 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlsdh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqdmlsdhq_s8 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlsdh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqdmlsdhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c +index 6ab9743054c..1742d47291c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdhxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmlsdhxq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdhxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdhxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmlsdhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdhxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c +index a34618e97fd..1c1b73a2251 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdhxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmlsdhxq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdhxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdhxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmlsdhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdhxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c +index fdbe89ab6b8..0a980a081a1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdhxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmlsdhxq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdhxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmlsdhxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmlsdhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmlsdhxt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c +index 786decc6238..713ce9732d2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlsdhx.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqdmlsdhxq_s16 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdhx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlsdhx.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqdmlsdhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdhx.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c +index c0244c44067..02f0a3cd6b4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlsdhx.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqdmlsdhxq_s32 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdhx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlsdhx.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqdmlsdhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdhx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c +index 12b43c8edd8..c1792879138 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmlsdhx.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqdmlsdhxq_s8 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdhx.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqdmlsdhx.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqdmlsdhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqdmlsdhx.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c +index 57ab85eaf52..17c43c4e4b4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqdmulhq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c +index 256353a0a21..62e7988f107 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqdmulhq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c +index c24be9ed5ad..3bd8b4f9632 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vqdmulhq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vqdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c +index 49efeefcf63..b1efee53278 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmulhq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c +index a5614830622..3492c17c3fd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmulhq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c +index 2e016f57e35..41118e0dcda 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmulhq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c +index 19534b60b27..dfff38bf59b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmulh.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b) + { + return vqdmulhq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmulh.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b) + { + return vqdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c +index eff9f6ecc4b..ac0812b438d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmulh.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vqdmulhq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmulh.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vqdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c +index 188cf7c616f..db8db5cb855 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmulh.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b) + { + return vqdmulhq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqdmulh.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b) + { + return vqdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c +index 513a30f67e6..e8927845ab4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vqdmulhq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c +index 9cf147dc7c5..c15c8e29273 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vqdmulhq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c +index 87211ad054a..1f7a556e1fb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vqdmulhq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqdmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vqdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmulh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c +index f0a4ad5b9f4..57ad651188c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmullbt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqdmullbq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmullbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmullbt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqdmullbq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmullbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c +index 1c7b2e4a1fc..c7153b35cef 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmullbt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqdmullbq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmullbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmullbt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqdmullbq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmullbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c +index 6a056cf86a1..d7abff0b3f4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmullbt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmullbq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmullbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmullbt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmullbq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmullbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c +index 019c536e7f2..503cd27735a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmullbt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmullbq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmullbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmullbt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmullbq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmullbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c +index ec501c34539..31a3a244355 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmullb.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, int16_t b) + { + return vqdmullbq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmullb.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, int16_t b) + { + return vqdmullbq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c +index 78fe3d6b289..dbc07187165 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmullb.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int32x4_t a, int32_t b) + { + return vqdmullbq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmullb.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int32x4_t a, int32_t b) + { + return vqdmullbq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c +index 9a423d3cc66..7d5fd25a1e1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmullb.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, int16x8_t b) + { + return vqdmullbq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmullb.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqdmullbq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c +index f0278cd8a86..503b1751250 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmullb.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int32x4_t a, int32x4_t b) + { + return vqdmullbq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmullb.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqdmullbq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c +index 85f03149da4..a36afd8a3a5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulltt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqdmulltq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulltt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqdmulltq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulltt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c +index 6bb5004e201..fdbbfee27ef 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulltt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqdmulltq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulltt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulltt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqdmulltq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulltt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c +index a85393b5bc1..f5d5c6ce04e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulltt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmulltq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulltt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqdmulltq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulltt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c +index 82f25b2ebbe..91dad0e506d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulltt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmulltq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulltt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqdmulltt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqdmulltq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqdmulltt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c +index f9ad32a8411..e4f09d0f45c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmullt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, int16_t b) + { + return vqdmulltq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmullt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, int16_t b) + { + return vqdmulltq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c +index 311b023431e..80694b686c9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmullt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int32x4_t a, int32_t b) + { + return vqdmulltq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmullt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int32x4_t a, int32_t b) + { + return vqdmulltq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c +index 851f27a63b6..4f8b1eef4bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmullt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, int16x8_t b) + { + return vqdmulltq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqdmullt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqdmulltq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c +index 1e81cc3dea5..e3ebacc4f36 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqdmullt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int32x4_t a, int32x4_t b) + { + return vqdmulltq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqdmullt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64x2_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqdmulltq (a, b); + } + +-/* { dg-final { scan-assembler "vqdmullt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c +index bf5520ed1ff..dd6c0300c32 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovnbq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovnbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c +index f07612a47d5..eb340ebe520 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovnbq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovnbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c +index 79f082fefab..673f453e7af 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqmovnbq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovnbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c +index 5d242dc497f..84f7f9bf897 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqmovnbq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovnbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovnbt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqmovnbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c +index 18df48f5084..ed17eb81884 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqmovnbq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c +index 37f9e817805..065ce9b246c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnb.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqmovnbq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnb.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c +index 130dcb06944..29df4636e3d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnb.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqmovnbq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnb.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c +index 8bf735294e5..422c33560d3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnb.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqmovnbq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnb.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqmovnbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnb.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c +index bc624bcd877..b50964bd4f7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovntq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c +index 429f25cdb0f..5d4947abb9f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovntq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c +index a453a9fc36a..8cfd62831eb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqmovntq_m_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovntt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c +index 3f9ae8a5ee4..b9d3b7e75ac 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqmovntq_m_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovntt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovntt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqmovntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c +index 5de956cbac4..8838a242fd9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqmovntq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c +index 30db31c47ee..1d8b0dc17ef 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqmovntq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c +index 312ce4f865f..10badd5feb4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqmovntq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnt.u16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c +index 20623384858..80460393001 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovnt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqmovntq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovnt.u32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqmovntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovnt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c +index 8e46de63b84..d295b3f9155 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovunbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovunbq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovunbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovunbt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovunbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c +index d0ec95192f9..84b94db682f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovunbt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovunbq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovunbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovunbt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovunbq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c +index 9b3b80d024f..070bb90bf12 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovunb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqmovunbq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovunb.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqmovunbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c +index 9cc43d987de..659e703a558 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovunb.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqmovunbq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovunb.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqmovunbq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c +index a81fb8863af..fb3b36c451e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovuntt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovuntq_m_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovuntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovuntt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqmovuntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c +index e76ca2b5f48..f6fce6d4473 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovuntt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovuntq_m_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqmovuntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqmovuntt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqmovuntq_m (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c +index 324d2e56f3c..3230f25998b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovunt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqmovuntq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqmovunt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqmovuntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c +index 80fee05b642..5333897a34a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqmovunt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqmovuntq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqmovunt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqmovuntq (a, b); + } + +-/* { dg-final { scan-assembler "vqmovunt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c +index 4f0145d2ebd..f3799a35b12 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vqnegq_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqnegt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vqnegq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c +index da4f90bad53..bbe64ff4d52 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vqnegq_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqnegt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vqnegq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c +index ac1250b2fac..71fcdd7cba7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vqnegq_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqnegt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vqnegq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c +index f9210cd70f4..d5fb4a19854 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqneg.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vqnegq_s16 (a); + } + +-/* { dg-final { scan-assembler "vqneg.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqneg.s16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vqnegq (a); + } + +-/* { dg-final { scan-assembler "vqneg.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c +index c2ded7fe659..2c8e709f491 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqneg.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vqnegq_s32 (a); + } + +-/* { dg-final { scan-assembler "vqneg.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqneg.s32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vqnegq (a); + } + +-/* { dg-final { scan-assembler "vqneg.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c +index d1cc83a6cd0..2f7f7619ef6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqneg.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vqnegq_s8 (a); + } + +-/* { dg-final { scan-assembler "vqneg.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqneg.s8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vqnegq (a); + } + +-/* { dg-final { scan-assembler "vqneg.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c +index fce4f5a35ef..1140c25c4a2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmladhq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmladhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c +index e550b6a7995..b3e6dac19a9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmladhq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmladhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c +index b07b28e5bcd..5ae74e1dd2d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmladhq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmladhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c +index 5bdac923b20..f515c3926da 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmladh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqrdmladhq_s16 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmladh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqrdmladhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c +index aade9bb0ea1..4693d01eeb4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmladh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqrdmladhq_s32 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmladh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqrdmladhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c +index bde80fa5279..cea58e4f80a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmladh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqrdmladhq_s8 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmladh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqrdmladhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c +index 677efdcd1e4..3b8ea613f1d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladhxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmladhxq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladhxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladhxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmladhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladhxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c +index 8ee8bbb420b..6ef932672bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladhxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmladhxq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladhxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladhxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmladhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladhxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c +index 7cfa88fee28..5b9dc5cadac 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladhxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmladhxq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladhxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmladhxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmladhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmladhxt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c +index 2410ef12b38..745c70b84f7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmladhx.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqrdmladhxq_s16 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladhx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmladhx.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqrdmladhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladhx.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c +index 716028cadfd..94e976f724c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmladhx.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqrdmladhxq_s32 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladhx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmladhx.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqrdmladhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladhx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c +index 8f9bed5fdb7..f8c9f487068 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmladhx.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqrdmladhxq_s8 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladhx.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmladhx.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqrdmladhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmladhx.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c +index 70c3fa0e9b1..f8400ac63d7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlaht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p) + { +- return vqrdmlahq_m_n_s16 (a, b, c, p); ++ return vqrdmlahq_m_n_s16 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlaht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlaht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p) + { +- return vqrdmlahq_m (a, b, c, p); ++ return vqrdmlahq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlaht.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c +index 75ed9911276..fa1131de6b5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlaht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p) + { +- return vqrdmlahq_m_n_s32 (a, b, c, p); ++ return vqrdmlahq_m_n_s32 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlaht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlaht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p) + { +- return vqrdmlahq_m (a, b, c, p); ++ return vqrdmlahq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlaht.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c +index ddaea545f40..a7ce97cc2f6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlaht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p) + { +- return vqrdmlahq_m_n_s8 (a, b, c, p); ++ return vqrdmlahq_m_n_s8 (add, m1, m2, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlaht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlaht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p) + { +- return vqrdmlahq_m (a, b, c, p); ++ return vqrdmlahq_m (add, m1, m2, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlaht.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c +index 45e74971838..175a2f74416 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlah.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c) ++foo (int16x8_t add, int16x8_t m1, int16_t m2) + { +- return vqrdmlahq_n_s16 (a, b, c); ++ return vqrdmlahq_n_s16 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vqrdmlah.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlah.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c) ++foo1 (int16x8_t add, int16x8_t m1, int16_t m2) + { +- return vqrdmlahq (a, b, c); ++ return vqrdmlahq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqrdmlah.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c +index 79bb9c98b12..56d5423bd3f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlah.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c) ++foo (int32x4_t add, int32x4_t m1, int32_t m2) + { +- return vqrdmlahq_n_s32 (a, b, c); ++ return vqrdmlahq_n_s32 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vqrdmlah.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlah.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c) ++foo1 (int32x4_t add, int32x4_t m1, int32_t m2) + { +- return vqrdmlahq (a, b, c); ++ return vqrdmlahq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqrdmlah.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c +index 220518ae698..992be758837 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlah.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c) ++foo (int8x16_t add, int8x16_t m1, int8_t m2) + { +- return vqrdmlahq_n_s8 (a, b, c); ++ return vqrdmlahq_n_s8 (add, m1, m2); + } + +-/* { dg-final { scan-assembler "vqrdmlah.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlah.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c) ++foo1 (int8x16_t add, int8x16_t m1, int8_t m2) + { +- return vqrdmlahq (a, b, c); ++ return vqrdmlahq (add, m1, m2); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqrdmlah.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c +index 35b9618ca47..d713c224b30 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlasht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p) + { +- return vqrdmlashq_m_n_s16 (a, b, c, p); ++ return vqrdmlashq_m_n_s16 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlasht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlasht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) ++foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p) + { +- return vqrdmlashq_m (a, b, c, p); ++ return vqrdmlashq_m (m1, m2, add, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlasht.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c +index 8517835eb61..8af4928f833 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlasht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p) + { +- return vqrdmlashq_m_n_s32 (a, b, c, p); ++ return vqrdmlashq_m_n_s32 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlasht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlasht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) ++foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p) + { +- return vqrdmlashq_m (a, b, c, p); ++ return vqrdmlashq_m (m1, m2, add, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlasht.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c +index e42cc63fa74..9f30b7d0e13 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlasht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p) + { +- return vqrdmlashq_m_n_s8 (a, b, c, p); ++ return vqrdmlashq_m_n_s8 (m1, m2, add, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlasht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlasht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) ++foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p) + { +- return vqrdmlashq_m (a, b, c, p); ++ return vqrdmlashq_m (m1, m2, add, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlasht.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c +index 8ff8c34d529..83caaab8926 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlash.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, int16x8_t b, int16_t c) ++foo (int16x8_t m1, int16x8_t m2, int16_t add) + { +- return vqrdmlashq_n_s16 (a, b, c); ++ return vqrdmlashq_n_s16 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vqrdmlash.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlash.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, int16x8_t b, int16_t c) ++foo1 (int16x8_t m1, int16x8_t m2, int16_t add) + { +- return vqrdmlashq (a, b, c); ++ return vqrdmlashq (m1, m2, add); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqrdmlash.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c +index 02583f0627b..337f33c51c8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlash.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, int32_t c) ++foo (int32x4_t m1, int32x4_t m2, int32_t add) + { +- return vqrdmlashq_n_s32 (a, b, c); ++ return vqrdmlashq_n_s32 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vqrdmlash.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlash.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, int32_t c) ++foo1 (int32x4_t m1, int32x4_t m2, int32_t add) + { +- return vqrdmlashq (a, b, c); ++ return vqrdmlashq (m1, m2, add); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqrdmlash.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c +index 0bd5bcac71f..df005ee9b03 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlash.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, int8x16_t b, int8_t c) ++foo (int8x16_t m1, int8x16_t m2, int8_t add) + { +- return vqrdmlashq_n_s8 (a, b, c); ++ return vqrdmlashq_n_s8 (m1, m2, add); + } + +-/* { dg-final { scan-assembler "vqrdmlash.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlash.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, int8x16_t b, int8_t c) ++foo1 (int8x16_t m1, int8x16_t m2, int8_t add) + { +- return vqrdmlashq (a, b, c); ++ return vqrdmlashq (m1, m2, add); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqrdmlash.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c +index d0054b8ea97..52c7f16df12 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmlsdhq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmlsdhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c +index 7d3fe45eb4d..574809dde9b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmlsdhq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmlsdhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c +index c33f8ea903b..9b509687ed9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmlsdhq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmlsdhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c +index 3bd760d38aa..19fdc151550 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlsdh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqrdmlsdhq_s16 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlsdh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqrdmlsdhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c +index e23dc94a9ed..d50bd8500bd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlsdh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqrdmlsdhq_s32 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlsdh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqrdmlsdhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c +index 836e04af566..c3f6b3e462b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlsdh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqrdmlsdhq_s8 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlsdh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqrdmlsdhq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c +index 2fbd351f3b4..35fc3bde975 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdhxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmlsdhxq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdhxt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdhxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmlsdhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdhxt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c +index 324a6e63398..7b5ee71194c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdhxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmlsdhxq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdhxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdhxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmlsdhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdhxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c +index 287868b1190..0ceb9c55aa3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdhxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmlsdhxq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdhxt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmlsdhxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmlsdhxq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmlsdhxt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c +index 9d8ea9b2694..b94e4cca8b2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlsdhx.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqrdmlsdhxq_s16 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdhx.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlsdhx.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b) + { + return vqrdmlsdhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdhx.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c +index aca0b358ea9..0f508d9bca1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlsdhx.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqrdmlsdhxq_s32 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdhx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlsdhx.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b) + { + return vqrdmlsdhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdhx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c +index 18f95317b4c..92607fe0265 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmlsdhx.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqrdmlsdhxq_s8 (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdhx.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmlsdhx.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b) + { + return vqrdmlsdhxq (inactive, a, b); + } + +-/* { dg-final { scan-assembler "vqrdmlsdhx.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c +index c4b6b7e22f8..ae38058cc62 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqrdmulhq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqrdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c +index 6de3eb1cb9a..e923495f4b5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrdmulhq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c +index df3dfa87fbf..a6ce3b2ca01 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vqrdmulhq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vqrdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c +index 24831e8a5f8..a8a749d07cb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmulhq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c +index 70257c3c0a0..ad6130dfbdc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmulhq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c +index 7cd39d2a0d4..da29228e5f3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmulhq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrdmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrdmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrdmulht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c +index 42fe9cbaa2b..342ef427bc9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmulh.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b) + { + return vqrdmulhq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmulh.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b) + { + return vqrdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c +index 5f014fae9fb..7ae72b75689 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmulh.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vqrdmulhq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmulh.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vqrdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c +index 887e294661b..8acb72a2245 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmulh.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b) + { + return vqrdmulhq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmulh.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b) + { + return vqrdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c +index 409fc29c0d0..5e93d7758c0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vqrdmulhq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqrdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c +index 18e11b1248c..d2812c0aa05 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vqrdmulhq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqrdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c +index 3f1441d5d6b..5c188a6d91f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrdmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vqrdmulhq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrdmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vqrdmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vqrdmulh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c +index 8d5abfd7588..d9baa378fac 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c +index 734f67ae251..ce4140a6fb8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c +index 3c6724f285b..ce576b01d65 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c +index 3e39599df8a..e861a7b1f6a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c +index 41f5945daf9..d4cb581c623 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c +index 9aad2599476..f170f225d95 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vqrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c +index 80045c5b583..7c5449fb168 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshlq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c +index 9b4cf1663cd..53a421cf830 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshlq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c +index 55e0dd57023..52ad4372916 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrshlq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c +index cd5605444a1..e7ca4786363 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshlq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c +index 02c94d0a51f..3785bbea0dc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshlq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c +index e6058dfc4c5..c736abeceab 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrshlq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshlt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c +index 46fd917d2d9..231ce85f1a3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b) + { + return vqrshlq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c +index 373de10b89c..05589eb86cc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vqrshlq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c +index d05d2fc722f..182e7cf260a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b) + { + return vqrshlq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c +index 8a74d61e75d..1b5214623c6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b) + { + return vqrshlq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c +index ccb0db7bb32..50d09bac3a9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b) + { + return vqrshlq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c +index c3319ea29d2..846d90a2470 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b) + { + return vqrshlq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c +index c5645cee518..2a4a0feb5e6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vqrshlq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c +index b773ccf9245..94665928299 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vqrshlq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c +index 1a61cb6de10..2836a6e4dc8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vqrshlq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c +index 8de05a290b7..2ea554253c1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b) + { + return vqrshlq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c +index 0ceee291bab..fef01d926b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b) + { + return vqrshlq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c +index 7779871c097..6ceafa0f473 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b) + { + return vqrshlq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b) + { + return vqrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqrshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c +index 16a4827e50d..76c38e07faa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrnbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c +index bb054bcf5a1..3af0ad96493 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrnbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c +index 45119720ed5..f81dd96efde 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqrshrnbq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c +index a3a7a7eac3e..ad52c378a07 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqrshrnbq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c +index d1b2ea58dd5..3f82f86029e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqrshrnbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c +index da5db1b8951..02f303052a3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqrshrnbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c +index 360999e3785..cda56ce3c48 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqrshrnbq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c +index f276f24a1dd..5202e6249a4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqrshrnbq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnb.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c +index fb21072bfa0..39c0eff56f6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c +index 77c4cb7e0b0..5fb6983237c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c +index 1749f4866a4..91ec5795566 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqrshrntq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c +index e243319e256..986437e49ca 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqrshrntq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrntt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c +index c7cdc394c35..5dfed5dcbaa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqrshrntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c +index 68dfccccc66..7df82962342 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqrshrntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c +index bc0572a454b..e76d98ee3f4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqrshrntq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c +index 20bfdbf515a..bc0e39baeae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqrshrntq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrnt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c +index ea12f346b0e..299dd80a887 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrunbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshrunbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c +index d127e5381bf..5c87efe4be9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrunbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshrunbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c +index 88cb39970d4..3bbf72d4def 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqrshrunbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqrshrunbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c +index 46f96127b1b..4dfd8f60e72 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqrshrunbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqrshrunbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c +index 5ff25eb2d32..48c17e5e5b6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshruntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshruntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqrshruntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshruntt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c +index 4876414e308..46912882ff1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshruntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshruntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqrshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqrshruntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqrshruntt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c +index 0f6258b3524..9dc8d3b8f5a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqrshruntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqrshruntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c +index d307f38ec6c..8071367fa2f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqrshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqrshruntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqrshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqrshruntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqrshrunt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c +index a33856f17a5..6eb7443d45e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vqshlq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c +index bcfe4fc2874..d10829c90c8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vqshlq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c +index fba2f0fe859..49886009d74 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vqshlq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c +index 1383f6a9ab4..7eb330e6c18 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vqshlq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c +index 7cff29f5a28..86ecdc6d563 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vqshlq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c +index cbadcbeb77e..f3886e7bae6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vqshlq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vqshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c +index a3057fec343..e89298c570b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c +index 6973b49a476..35e2552728a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c +index 282d4b45c59..366b45699a9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c +index 111d7fa23d9..86774962f0f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c +index 96de168dd23..92a61fe4a2e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c +index 24e388824cc..bace3656143 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vqshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c +index ebae8beecb4..2df2ee5c836 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqshlq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c +index 80e4d860fb9..e0b2de339f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqshlq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c +index e8f88113003..b65df1998fe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqshlq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c +index 692ff54981d..bced90d13b9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqshlq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c +index 1ece80681a7..409ef8524cb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqshlq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c +index 7302669fe26..ce9a426ccc9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqshlq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c +index b827993198d..859da655409 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vqshlq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c +index dbc22df551e..1d61e880890 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vqshlq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c +index e4e1d193c55..737c1bd3764 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vqshlq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c +index 8227890fc4b..9ddb83e4287 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { + return vqshlq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c +index b91dc3b91d3..642060f2225 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { + return vqshlq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c +index ab4903ae407..bd8b9341007 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { + return vqshlq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { + return vqshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c +index 4413d447b71..285f398b35a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b) + { + return vqshlq_r_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c +index 6df14afb48d..af594003c06 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vqshlq_r_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c +index c1b93793c8f..ef39f0c3924 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b) + { + return vqshlq_r_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c +index 20fa0263de4..e6cc0007a2b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b) + { + return vqshlq_r_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c +index 7d56784b3d5..b30ecdf4052 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b) + { + return vqshlq_r_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c +index 199249bf604..69b0a8d0b90 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b) + { + return vqshlq_r_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b) + { + return vqshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c +index 2b01d3e3d31..e7877019200 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vqshlq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c +index b9b66223ae9..a7787cabb62 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vqshlq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c +index 8096205cf28..73af1790b47 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vqshlq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c +index 61b6c18bd8a..26119eff397 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b) + { + return vqshlq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c +index 06b50442d30..01b66d5dfbc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b) + { + return vqshlq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c +index 0cc6a1dac4b..d4727de5de9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b) + { + return vqshlq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b) + { + return vqshlq (a, b); + } + +-/* { dg-final { scan-assembler "vqshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c +index 885874d13fb..ada03b165c5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vqshluq_m_n_s16 (inactive, a, 7, p); ++ return vqshluq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlut.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vqshluq_m (inactive, a, 7, p); ++ return vqshluq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c +index bb2a3294727..6ae38f1ca84 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vqshluq_m_n_s32 (inactive, a, 7, p); ++ return vqshluq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlut.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vqshluq_m (inactive, a, 7, p); ++ return vqshluq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c +index 7f9a42f8027..8d536a7b0f7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vqshluq_m_n_s8 (inactive, a, 7, p); ++ return vqshluq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshlut.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshlut.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vqshluq_m (inactive, a, 7, p); ++ return vqshluq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c +index 481a4465834..33ba80cbf97 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshlu.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (int16x8_t a) + { +- return vqshluq_n_s16 (a, 7); ++ return vqshluq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshlu.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshlu.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (int16x8_t a) + { +- return vqshluq (a, 7); ++ return vqshluq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshlu.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c +index 68298963824..0d5a35f1ed3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshlu.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (int32x4_t a) + { +- return vqshluq_n_s32 (a, 7); ++ return vqshluq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshlu.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshlu.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (int32x4_t a) + { +- return vqshluq (a, 7); ++ return vqshluq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshlu.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c +index 5d52c340667..1e2d9e044b9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshlu.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (int8x16_t a) + { +- return vqshluq_n_s8 (a, 7); ++ return vqshluq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vqshlu.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqshlu.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (int8x16_t a) + { +- return vqshluq (a, 7); ++ return vqshluq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshlu.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c +index 9ea58e95d37..0266640a3ff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vqshrnbq_m_n_s16 (a, b, 7, p); ++ return vqshrnbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vqshrnbq_m (a, b, 7, p); ++ return vqshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c +index b44f41b3699..59be6de392b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vqshrnbq_m_n_s32 (a, b, 11, p); ++ return vqshrnbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vqshrnbq_m (a, b, 11, p); ++ return vqshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c +index f761d14ecec..f227a285ea9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqshrnbq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c +index 3073a5b223c..9711c2f9019 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqshrnbq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrnbt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c +index 24133b57660..e7e9f974bd4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqshrnbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c +index 34c11e156c3..b5e2b8af577 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { +- return vqshrnbq_n_s32 (a, b, 2); ++ return vqshrnbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { +- return vqshrnbq (a, b, 2); ++ return vqshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshrnb.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c +index 23a7596e0ab..708cf3e8d74 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqshrnbq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c +index 4cb7ceaf66b..07fbbaada67 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { +- return vqshrnbq_n_u32 (a, b, 15); ++ return vqshrnbq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnb.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { +- return vqshrnbq (a, b, 15); ++ return vqshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vqshrnb.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c +index d2ff2d359e0..c25619df048 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshrntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c +index 50dde4047d4..1b1d435e282 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshrntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c +index 07949569581..f151a277cd1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqshrntq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vqshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c +index 17f0205c880..c336001c945 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqshrntq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vqshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrntt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c +index 9e8d5e88619..15b010d2c84 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vqshrntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vqshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c +index 0661cefa783..974e4a060ce 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vqshrntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vqshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c +index cda26142559..3172a330f6b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vqshrntq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vqshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c +index f242353f6b4..e9e31d63e98 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vqshrntq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vqshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrnt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c +index 73c480646e7..b7fe0e51e82 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshrunbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrunbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshrunbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrunbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c +index f8887b1cecb..fb78dd44c5d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshrunbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrunbt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshrunbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshrunbt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c +index 2c64d7d0873..3c286e77a40 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqshrunbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqshrunbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c +index 17cb0aa5da1..e22fb2b2b36 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqshrunbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunb.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqshrunbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunb.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c +index 4b9758df7ec..22ca346d98b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshruntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshruntt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vqshruntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshruntt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c +index 18b9f117fb2..2f6adf26e5e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshruntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshruntt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vqshruntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqshruntt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c +index f6247751c44..96a377e13b9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int16x8_t b) + { + return vqshruntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int16x8_t b) + { + return vqshruntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c +index 076fd29c69f..2e2eb93a0d6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32x4_t b) + { + return vqshruntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32x4_t b) + { + return vqshruntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vqshrunt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c +index abcff4f0e3c..f69649b58af 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqsubq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c +index 23e59ff12a2..a7843d07933 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqsubq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c +index d783ab55f65..f1fb5ad2a05 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vqsubq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c +index 5244efb340c..7e7d2c07267 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vqsubq_m_n_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) ++{ ++ return vqsubq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c +index 4427f87f456..13e54be06c1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vqsubq_m_n_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) ++{ ++ return vqsubq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c +index 0abfa5dc132..ae6baaba661 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vqsubq_m_n_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) ++{ ++ return vqsubq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c +index faa189f8466..fd52022fc26 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqsubq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c +index 62a4dd0979f..4225ec29c06 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqsubq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c +index 71fb6f5632e..27496305ee8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqsubq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c +index 68d642dfef5..d840e51d350 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vqsubq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c +index 8f76c5f47da..242903f9dc8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vqsubq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c +index af335ae9752..e5a6b7aa0e4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vqsubq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vqsubt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vqsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vqsubt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c +index 33a79180289..7a286add743 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b) + { + return vqsubq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c +index a2b338839fa..2532b216a34 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vqsubq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c +index e8d7e99d19d..9e0a233baa0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b) + { + return vqsubq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c +index f7b48c546a6..20d3267e583 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b) + { + return vqsubq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u16" } } */ ++/* ++**foo2: ++** ... ++** vqsub.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a) ++{ ++ return vqsubq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c +index f74a968f5a7..4805e4cd969 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b) + { + return vqsubq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u32" } } */ ++/* ++**foo2: ++** ... ++** vqsub.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a) ++{ ++ return vqsubq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c +index ce7b4ce0151..db475615bbc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b) + { + return vqsubq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u8" } } */ ++/* ++**foo2: ++** ... ++** vqsub.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a) ++{ ++ return vqsubq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c +index 85bf265eeb0..76def1b340d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vqsubq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s16" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c +index 35d17e8bc4e..989ad501659 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vqsubq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s32" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c +index 50cfccff7a5..4cf804b4c99 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vqsubq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s8" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c +index 15f0b7244b7..4d937a35269 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vqsubq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u16" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c +index 7d695e23474..5ee2c2d9cc2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vqsubq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u32" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c +index c0552d100d4..14cfb55644c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vqsub.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vqsubq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u8" } } */ + ++/* ++**foo1: ++** ... ++** vqsub.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vqsubq (a, b); + } + +-/* { dg-final { scan-assembler "vqsub.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c +index 7b06f0b3644..b366057dfde 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev16q_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev16t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev16q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c +index 8cf374d97c1..7baad3ba72f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev16q_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev16t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev16q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c +index 52688402437..23fcd61a464 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vrev16q_s8 (a); + } + +-/* { dg-final { scan-assembler "vrev16.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vrev16q (a); + } + +-/* { dg-final { scan-assembler "vrev16.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c +index 56c05c523f3..e08b4b6cda2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vrev16q_u8 (a); ++ return vrev16q_u8 (a); + } + +-/* { dg-final { scan-assembler "vrev16.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vrev16q (a); ++ return vrev16q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev16.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c +index 700a6774e2e..6496bf89931 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vrev16q_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev16t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vrev16q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c +index 3b424061f0e..e03f6f177ff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vrev16q_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev16t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vrev16q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c +index 946fd8ddf5b..6e4c5691760 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrev32q_f16 (a); + } + +-/* { dg-final { scan-assembler "vrev32.16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrev32q (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c +index 623b48a92c4..3b25f0314c7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrev32q_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c +index 4040707d02c..36f671924b3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vrev32q_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c +index ad15e9d2bca..13960569138 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev32q_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c +index 8cd61e6bb1f..7683397030b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vrev32q_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c +index 44600e2d1e7..72fc03bff2d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev32q_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev32q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c +index 503616e2a29..cd02518fd9d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c +@@ -1,21 +1,41 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vrev32q_s16 (a); + } + +-/* { dg-final { scan-assembler "vrev32.16" } } */ + ++/* ++**foo1: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vrev32q (a); + } + +-/* { dg-final { scan-assembler "vrev32.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c +index aa98f965713..3a156b7014f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vrev32q_s8 (a); + } + +-/* { dg-final { scan-assembler "vrev32.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vrev32q (a); + } + +-/* { dg-final { scan-assembler "vrev32.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c +index 6a441ed0edb..299f015bb04 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vrev32q_u16 (a); ++ return vrev32q_u16 (a); + } + +-/* { dg-final { scan-assembler "vrev32.16" } } */ + ++/* ++**foo1: ++** ... ++** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vrev32q (a); ++ return vrev32q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev32.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c +index 787f236411d..fb65d0a3821 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vrev32q_u8 (a); ++ return vrev32q_u8 (a); + } + +-/* { dg-final { scan-assembler "vrev32.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vrev32q (a); ++ return vrev32q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev32.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c +index f7dc8fb14ec..d1c22aa72f4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrev32q_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c +index 81ec83dec4b..0f0c19b1483 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vrev32q_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c +index 8d3bac1e82c..2457dde2a58 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vrev32q_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c +index 36ba71752a8..b1b1237344e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vrev32q_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c +index 9d15c9df43c..21d39274577 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vrev32q_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev32t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vrev32q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c +index 7ec0962a95e..a2dc8957467 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrev64q_f16 (a); + } + +-/* { dg-final { scan-assembler "vrev64.16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c +index 01c342496da..78add56a4da 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrev64q_f32 (a); + } + +-/* { dg-final { scan-assembler "vrev64.32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c +index ef47bab0314..0fb44077ec4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrev64q_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c +index 6df0ba62eff..ff62ea7d021 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrev64q_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c +similarity index 53% +rename from gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c +rename to gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c +index b3a67bb43eb..6464c96181d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c +@@ -3,11 +3,15 @@ + /* { dg-additional-options "-O2" } */ + + #include "arm_mve.h" +-float16x8_t +-foo (float16x8_t a, float16_t b, mve_pred16_t p) ++ ++int16x8_t ++foo (int16x8_t a, mve_pred16_t p) + { +- return vsubq_x_n_f16 (a, 23.23, p); ++ return vrev64q_m_s16 (a, a, p); + } + +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ ++float16x8_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vrev64q_m_f16 (a, a, p); ++} +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c +index 9f9bbe0e666..b30ce76c68f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vrev64q_m_s16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c +index 132628b5a80..b44d363a712 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vrev64q_m_s32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c +index eb6e560ac3c..4804b8acaf3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev64q_m_s8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c +index 4534a64ee84..12c26144cd2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vrev64q_m_u16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c +index 3f1ab24527c..ff90d92fff3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vrev64q_m_u32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c +index 4adb70963dd..267c3b6bee2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev64q_m_u8 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vrev64q_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c +index a886b0b0c6a..b6083f9d69c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vrev64q_s16 (a); + } + +-/* { dg-final { scan-assembler "vrev64.16" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vrev64q (a); + } + +-/* { dg-final { scan-assembler "vrev64.16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c +index b0ba64b186b..81fc7d1bdd0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { + return vrev64q_s32 (a); + } + +-/* { dg-final { scan-assembler "vrev64.32" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { + return vrev64q (a); + } + +-/* { dg-final { scan-assembler "vrev64.32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c +index 12f9f1ac389..3fced739681 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vrev64q_s8 (a); + } + +-/* { dg-final { scan-assembler "vrev64.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vrev64q (a); + } + +-/* { dg-final { scan-assembler "vrev64.8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c +index ee3813428c9..b25fccc6c2a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vrev64q_u16 (a); ++ return vrev64q_u16 (a); + } + +-/* { dg-final { scan-assembler "vrev64.16" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vrev64q (a); ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev64.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c +index c4a551dcc15..9d203b1f6bf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vrev64q_u32 (a); ++ return vrev64q_u32 (a); + } + +-/* { dg-final { scan-assembler "vrev64.32" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { +- return vrev64q (a); ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev64.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c +index 578d538f019..9acd52439e5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vrev64q_u8 (a); ++ return vrev64q_u8 (a); + } + +-/* { dg-final { scan-assembler "vrev64.8" } } */ + ++/* ++**foo1: ++** ... ++** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vrev64q (a); ++ return vrev64q (a); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrev64.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c +index 467da7fe9ef..9c949028d8b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrev64q_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c +index 1a3cd17ebd6..445834a55f8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrev64q_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c +index b9932eddf38..66daa3d9131 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { + return vrev64q_x_s16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c +index 4eb3d4d09b1..2c5a5ee1a0c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { + return vrev64q_x_s32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c +index 5c22c387586..a24f17d5797 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { + return vrev64q_x_s8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c +index bbf42931d92..4c11e79254b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { + return vrev64q_x_u16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c +index 1b595c3ad2f..14f676e0cff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { + return vrev64q_x_u32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c +index abff81e40b9..542dcaa782c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { + return vrev64q_x_u8 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrev64t.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { + return vrev64q_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c +index 01d72efc34b..0deef794352 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrhaddq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c +index dfe8d7334a8..e584987fb3e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrhaddq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c +index 9eceda2b115..40e3472bbf0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrhaddq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c +index ec11b660a4e..bd53871cc58 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrhaddq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c +index 25c6208ec06..30037083a01 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrhaddq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c +index 7b25bf8faa8..3208ac1589b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrhaddq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrhaddq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c +index 36f36f77233..bafb1dc5795 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vrhaddq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s16" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c +index 813cf91649e..bbee81fffd6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vrhaddq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c +index 5ce1109d676..3fad58d4e0d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vrhaddq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s8" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c +index 9d9bf18ec70..91273571ec8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vrhaddq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u16" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c +index e465197505b..79a21051b0b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vrhaddq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c +index cbede385f20..4bdd23419a3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vrhaddq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u8" } } */ + ++/* ++**foo1: ++** ... ++** vrhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vrhaddq (a, b); + } + +-/* { dg-final { scan-assembler "vrhadd.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c +index 8507b436dc8..363dedd3304 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrhaddq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c +index 756c52f8f1e..f1df6749f33 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrhaddq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c +index 9b580782098..107cf2daa58 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrhaddq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c +index ec534c8262e..5837437d33c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrhaddq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c +index c79f406439e..0d8d118987e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrhaddq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c +index c4c16f8a753..37711710ee8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrhaddq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrhaddt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrhaddq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c +index 263d3509771..c18ff82f8f5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlaldavhaq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlaldavhaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhat.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c +index 83ab68c001b..ba0a9587e3f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c +@@ -1,21 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) + { + return vrmlaldavhaq_p_u32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhat.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) + { + return vrmlaldavhaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhat.u32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p) ++{ ++ return vrmlaldavhaq_p (1, b, c, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c +index 09cd9ee99ff..b2ced4b41c7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlaldavhaq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlaldavha.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlaldavhaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlaldavha.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c +index 1d6f64e0879..96f1ab72e92 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavha.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint64_t a, uint32x4_t b, uint32x4_t c) + { + return vrmlaldavhaq_u32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlaldavha.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavha.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint64_t a, uint32x4_t b, uint32x4_t c) + { + return vrmlaldavhaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlaldavha.u32" } } */ ++/* ++**foo2: ++** ... ++** vrmlaldavha.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint64_t ++foo2 (uint32x4_t b, uint32x4_t c) ++{ ++ return vrmlaldavhaq (1, b, c); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c +index 0e29e886ce1..a0164ed2bb7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlaldavhaxq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlaldavhaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c +index 063c94d8c5b..4e71fd72e35 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlaldavhaxq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlaldavhaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c +index 1d7a5e3d690..b8f346f9740 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlaldavhq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlaldavhq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c +index 539b04254cd..d6c6d503a9b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavht.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmlaldavhq_p_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavht.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmlaldavhq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c +index 566b85d1721..22c1164b6a9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vrmlaldavhq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmlaldavhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c +index 352cd58c8e8..6517ee8cd60 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavh.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo (uint32x4_t a, uint32x4_t b) + { + return vrmlaldavhq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavh.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint64_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vrmlaldavhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c +index d99ebffbea0..ebe1012f53f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlaldavhxq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlaldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlaldavhxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c +index 64f02971eb3..56a2071d61c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlaldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vrmlaldavhxq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlaldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmlaldavhxq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c +index 83d5a8ce251..aad2f009ba3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlsldavhaq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlsldavhaq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c +index a8a320c6a43..f30870181b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlsldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlsldavhaq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlsldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlsldavhaq (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c +index aa20ba1a7eb..2a3f441e429 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlsldavhaxq_p_s32 (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) + { + return vrmlsldavhaxq_p (a, b, c, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c +index 78932840dfe..06afa309bfa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlsldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlsldavhaxq_s32 (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlsldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int64_t a, int32x4_t b, int32x4_t c) + { + return vrmlsldavhaxq (a, b, c); + } + +-/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c +index 1e2127a17be..9f1f82a7c62 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlsldavhq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlsldavhq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c +index 2a7844fa370..ff867d5c208 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlsldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vrmlsldavhq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlsldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmlsldavhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c +index ecbc9737d8f..2a127c76df8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlsldavhxq_p_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmlsldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmlsldavhxq_p (a, b, p); + } + +-/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c +index 0cea55724aa..41539059d7f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmlsldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo (int32x4_t a, int32x4_t b) + { + return vrmlsldavhxq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmlsldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int64_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmlsldavhxq (a, b); + } + +-/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c +index 6adaf3f6431..e5c70a0a323 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrmulhq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c +index a90a67971c8..6b373e1739a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmulhq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c +index d0dd99aa4c3..961ba71ccb7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrmulhq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c +index 50d05c1de11..3a782c295e1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrmulhq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c +index a7da7330266..818fb631ff7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmulhq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c +index 42b0b9f0f2f..3d1eb365c63 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrmulhq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrmulhq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c +index ac77b9f13ba..34c3f182628 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vrmulhq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s16" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c +index a7bbd19c393..fe4d11c5acd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vrmulhq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c +index b0d1a856794..4b5a2e656ed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vrmulhq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s8" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c +index b43cb07b1bf..478d5885edd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vrmulhq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u16" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c +index f37eeb606f2..e3dc75d10aa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vrmulhq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c +index ab5d7597a43..108357b6d35 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vrmulhq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u8" } } */ + ++/* ++**foo1: ++** ... ++** vrmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vrmulhq (a, b); + } + +-/* { dg-final { scan-assembler "vrmulh.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c +index 3ef89bd686b..00f728bdaf2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrmulhq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c +index 2a4b9d0d147..49a739d9a95 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmulhq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c +index d3ef8713dba..7d97cbc5f8e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrmulhq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c +index 5ce4d01a235..31622dce8df 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrmulhq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c +index 4a965976c2d..f6d2582bac8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmulhq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c +index 015530c08b2..15e947618f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrmulhq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrmulht.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vrmulhq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c +index ba8426fdff3..17b11972e84 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrinta.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndaq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrinta.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrinta.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndaq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c +index a8c9c28422f..dc3689a66d1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrinta.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndaq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrinta.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrinta.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndaq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c +index 3617d796351..ffbdf3dad94 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndaq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c +index fdb9ddb3551..d20f8050c45 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndaq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndaq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c +index f398e86b689..141f612ddcb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndaq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintat.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndaq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c +index f5f21808528..277d2a7b668 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndaq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintat.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndaq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c +index 911a2b1cb29..a51878645da 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintm.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndmq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintm.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintm.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndmq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c +index 496a2e55d55..4b79490cc21 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintm.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndmq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintm.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintm.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndmq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c +index 86f58e2eb88..e6eb2a1015d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndmq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintmt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c +index 247595df56a..99f3f206823 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndmq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintmt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndmq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c +index accc79579ec..cdef684f381 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndmq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintmt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndmq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c +index 0e4200dc2f5..94da7738d16 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndmq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintmt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndmq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c +index 23299c2a06f..b1b31bebb11 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintn.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndnq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintn.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintn.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndnq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c +index ce445f2249f..e2fec8a87e2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintn.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndnq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintn.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintn.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndnq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c +index c41e38070bf..04d828bde24 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndnq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintnt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c +index 09b9b95d67d..b32eacd9b20 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndnq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintnt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndnq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c +index beeb23cf364..093aaa04d57 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndnq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintnt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c +index d09e55d53b3..8428800d503 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndnq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintnt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndnq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c +index 25dcbd5f3bf..3145faf9f70 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintp.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndpq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintp.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintp.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndpq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c +index 5ab6f7ae9c3..2754af48612 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintp.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndpq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintp.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintp.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndpq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c +index 2cf8220c789..e62883c1edb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndpq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c +index 7ed26e8d926..b8370b85373 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndpq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndpq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c +index 233a6e843e8..57465385173 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndpq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintpt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndpq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c +index f689ce6510b..86a94c0dfe5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndpq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintpt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndpq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c +index 6fe3b2eae48..4b2ee2c3da2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintz.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintz.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintz.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c +index a27b5c99b3a..301e9e4c25e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintz.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintz.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintz.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c +index 3a9edafc772..d7ba6d4f11f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintzt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c +index 0ae4b92d235..6bfe1d49941 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintzt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c +index eb6c3c37876..13ba05011e4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintzt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c +index 8b4c8c1e289..162d199420d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintzt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c +index e6f2028de30..9df65c5473d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintx.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a) + { + return vrndxq_f16 (a); + } + +-/* { dg-final { scan-assembler "vrintx.f16" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintx.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a) ++{ ++ return vrndxq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c +index 32e6c90e60e..92bc6df1361 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c +@@ -1,13 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrintx.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a) + { + return vrndxq_f32 (a); + } + +-/* { dg-final { scan-assembler "vrintx.f32" } } */ ++ ++/* ++**foo1: ++** ... ++** vrintx.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a) ++{ ++ return vrndxq (a); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c +index 0e6a6119f08..9d92566b08d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndxq_m_f16 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintxt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) + { + return vrndxq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c +index 3b09769814b..7a216050fb1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndxq_m_f32 (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintxt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) + { + return vrndxq_m (inactive, a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c +index c160800023f..537506cd5be 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, mve_pred16_t p) + { + return vrndxq_x_f16 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintxt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, mve_pred16_t p) + { + return vrndxq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c +index 48b76161032..e19ba0c0a3c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, mve_pred16_t p) + { + return vrndxq_x_f32 (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrintxt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, mve_pred16_t p) + { + return vrndxq_x (a, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c +index cf51de6aa9c..4c064515f0b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c +index dcfd99773e3..2c9c15b13b0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c +index cc1b746dc0d..48c394e21e3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c +index 93a95ba9065..2fe162b7051 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c +index 4b8c82aba21..49ccaf81c0c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c +index f1ff9dd33b7..df2f38f9cd2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vrshlq_m_n (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c +index 57f343cd3b9..0cb1511f778 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrshlq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c +index 2598b1719fd..52872e30d8d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrshlq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c +index 6e4f1bdddf4..887f3fd8ef8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrshlq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c +index d4d98913b75..9f55d180efb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrshlq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c +index 5d60f1fe799..f52e9d474c3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrshlq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c +index 913ba36c925..7241e3174c7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrshlq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c +index 713c6a218b2..feceb6dae9f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b) + { + return vrshlq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c +index 18906fe44d1..4fe4e4fe209 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vrshlq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c +index d5b1286d943..fc8fd2d3bee 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b) + { + return vrshlq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c +index 49bb21663d7..7d3a77a1928 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b) + { + return vrshlq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c +index 8ed67395b42..e5d688a67c1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b) + { + return vrshlq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c +index ccc6a00b98a..9f594e9cbce 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b) + { + return vrshlq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c +index c28ad31c6f9..facb0c957a5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vrshlq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c +index 2e279b6fb0a..d30d987eeb0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vrshlq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c +index 4d18419d1bf..52d1f41e5fc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vrshlq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c +index e0a9ea9cebc..b729151774c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b) + { + return vrshlq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c +index 788a4b1b6fa..12b46421e69 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b) + { + return vrshlq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c +index d860e9cccb9..37b9194a6a7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b) + { + return vrshlq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b) + { + return vrshlq (a, b); + } + +-/* { dg-final { scan-assembler "vrshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c +index 800a1e8e48f..b813647839c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrshlq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrshlq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c +index 921072a44c9..d06d0f93b10 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrshlq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrshlq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c +index 217b257ed24..0d1d8858e54 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrshlq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrshlq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c +index 5c0cad9ec89..ae050e4cda3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrshlq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vrshlq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c +index 2754d20841c..00a2edc55d4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrshlq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vrshlq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c +index 46dada44559..1172a62d0b5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrshlq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vrshlq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c +index 9e7f22ccad9..e30cfe16fdf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vrshrnbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c +index 6b6a98c3da4..acb89bd462a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vrshrnbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c +index e54893d2abc..4d0c6048971 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vrshrnbq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c +index ecb41a2c444..1b768a13061 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vrshrnbq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vrshrnbq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c +index f09db27adee..6350e3c4cca 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vrshrnbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c +index 2bc4170b07f..8ae96d8a2b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vrshrnbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c +index 990871f5b9e..2918cb05e43 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vrshrnbq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c +index 875fed28fe7..c615d8083d7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vrshrnbq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vrshrnbq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnb.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c +index 72206c36fda..639f25ed719 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vrshrntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { + return vrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c +index e964af2e8b5..07a53e364f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vrshrntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { + return vrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c +index ad98b7677f0..f00d62bcb7a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vrshrntq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { + return vrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c +index adee8b28b88..bb809acfe6e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vrshrntq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { + return vrshrntq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrntt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c +index 4c2f133b605..926a897d50e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { + return vrshrntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { + return vrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c +index 26508ba7961..7e931355751 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { + return vrshrntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { + return vrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c +index eea3d4974db..61636d301f7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { + return vrshrntq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { + return vrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c +index 49afdf0c61e..b82dad525f4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { + return vrshrntq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { + return vrshrntq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vrshrnt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c +index ee48f8c2733..b1a2f813320 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vrshrq_m_n_s16 (inactive, a, 16, p); ++ return vrshrq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 16, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c +index 4330dcfaaa6..fb229273b86 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vrshrq_m_n_s32 (inactive, a, 32, p); ++ return vrshrq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 32, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c +index 4b35c597a13..b9136b8dd69 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vrshrq_m_n_s8 (inactive, a, 8, p); ++ return vrshrq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 8, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c +index 2e83c60ad95..9dbc3fed62a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { +- return vrshrq_m_n_u16 (inactive, a, 16, p); ++ return vrshrq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 16, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c +index 5d2a9d8f4f4..0e0cb10b476 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vrshrq_m_n_u32 (inactive, a, 32, p); ++ return vrshrq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 32, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c +index f5b43708689..010a7915c56 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { +- return vrshrq_m_n_u8 (inactive, a, 8, p); ++ return vrshrq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { +- return vrshrq_m (inactive, a, 8, p); ++ return vrshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c +index 2cd934774ce..ff3d552bd78 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { +- return vrshrq_n_s16 (a, 16); ++ return vrshrq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.s16" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { +- return vrshrq (a, 16); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c +index 3cc21f2b277..db161f7d009 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { +- return vrshrq_n_s32 (a, 32); ++ return vrshrq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.s32" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { +- return vrshrq (a, 32); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c +index 251d5324f5c..86a0294f8a8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { +- return vrshrq_n_s8 (a, 8); ++ return vrshrq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.s8" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { +- return vrshrq (a, 8); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c +index 6934597f844..897247fce6c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vrshrq_n_u16 (a, 16); ++ return vrshrq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.u16" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vrshrq (a, 16); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c +index 52b287b8f3b..e8f7f1c33e0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vrshrq_n_u32 (a, 32); ++ return vrshrq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.u32" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { +- return vrshrq (a, 32); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c +index ac595a9ac95..a22521b14ae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vrshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vrshrq_n_u8 (a, 8); ++ return vrshrq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vrshr.u8" } } */ + ++/* ++**foo1: ++** ... ++** vrshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vrshrq (a, 8); ++ return vrshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vrshr.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c +index 14b5c1884f4..37f364cfc39 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vrshrq_x_n_s16 (a, 16, p); ++ return vrshrq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 16, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c +index 846ddb96782..0da2fd75056 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { +- return vrshrq_x_n_s32 (a, 32, p); ++ return vrshrq_x_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 32, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c +index 06f75e56db6..90c814b20c5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vrshrq_x_n_s8 (a, 8, p); ++ return vrshrq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 8, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c +index bc946497cfc..135b9e7e90f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vrshrq_x_n_u16 (a, 16, p); ++ return vrshrq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 16, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c +index 55002cd196d..dd656f49aa7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { +- return vrshrq_x_n_u32 (a, 32, p); ++ return vrshrq_x_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 32, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c +index e3130657711..e41abc450a0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vrshrq_x_n_u8 (a, 8, p); ++ return vrshrq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, mve_pred16_t p) + { +- return vrshrq_x (a, 8, p); ++ return vrshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vrshrt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c +index 21f4219faa3..dcbaef1a571 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c +@@ -1,23 +1,57 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vsbciq_m_s32 (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbcit.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vsbciq_m (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbcit.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c +index ef9eed92d33..08f67f665c1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c +@@ -1,23 +1,57 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vsbciq_m_u32 (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbcit.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p) ++foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) + { + return vsbciq_m (inactive, a, b, carry_out, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbcit.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c +index 2181a3a2879..803246c3235 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, unsigned * carry_out) ++foo (int32x4_t a, int32x4_t b, unsigned *carry_out) + { + return vsbciq_s32 (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vsbci.i32" } } */ + ++/* ++**foo1: ++** ... ++** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out) ++foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out) + { +- return vsbciq_s32 (a, b, carry_out); ++ return vsbciq (a, b, carry_out); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsbci.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c +index df0487f3b88..22d2b4355bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out) ++foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out) + { + return vsbciq_u32 (a, b, carry_out); + } + +-/* { dg-final { scan-assembler "vsbci.i32" } } */ + ++/* ++**foo1: ++** ... ++** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out) ++foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out) + { +- return vsbciq_u32 (a, b, carry_out); ++ return vsbciq (a, b, carry_out); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsbci.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c +index 73be46a8459..0c62778d482 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c +@@ -1,23 +1,77 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) ++foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) + { +- return vsbcq_m_s32 (inactive, a, b, carry, p); ++ return vsbcq_m_s32 (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbct.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p) ++foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) + { +- return vsbcq_m (inactive, a, b, carry, p); ++ return vsbcq_m (inactive, a, b, carry, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbct.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c +index 80cf70584e5..2532a23fac8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c +@@ -1,22 +1,77 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) ++foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) + { +- return vsbcq_m_u32 (inactive, a, b, carry, p); ++ return vsbcq_m_u32 (inactive, a, b, carry, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbct.i32" } } */ ++ ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p) ++foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) + { +- return vsbcq_m (inactive, a, b, carry, p); ++ return vsbcq_m (inactive, a, b, carry, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsbct.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c +index 23e42575bd7..5deff8c4018 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c +@@ -1,21 +1,69 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, int32x4_t b, unsigned * carry) ++foo (int32x4_t a, int32x4_t b, unsigned *carry) + { + return vsbcq_s32 (a, b, carry); + } + +-/* { dg-final { scan-assembler "vsbc.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, int32x4_t b, unsigned * carry) ++foo1 (int32x4_t a, int32x4_t b, unsigned *carry) + { + return vsbcq (a, b, carry); + } + +-/* { dg-final { scan-assembler "vsbc.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c +index d3aa66f6134..bd0ea2df127 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c +@@ -1,21 +1,69 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32x4_t b, unsigned * carry) ++foo (uint32x4_t a, uint32x4_t b, unsigned *carry) + { + return vsbcq_u32 (a, b, carry); + } + +-/* { dg-final { scan-assembler "vsbc.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** lsls (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?: @.*|) ++** ... ++** and (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?: @.*|) ++** ... ++** orrs (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ++** ... ++** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry) ++foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry) + { + return vsbcq (a, b, carry); + } + +-/* { dg-final { scan-assembler "vsbc.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c +deleted file mode 100644 +index 608dd30788e..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo (float16_t a, float16x8_t b) +-{ +- return vsetq_lane (23.26, b, 0); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c +index e03e9620528..5b1731f7332 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c +@@ -1,15 +1,53 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov.16 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16_t a, float16x8_t b) + { +- return vsetq_lane_f16 (a, b, 0); ++ return vsetq_lane_f16 (a, b, 1); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmov.16 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16_t a, float16x8_t b) ++{ ++ return vsetq_lane (a, b, 1); + } + +-/* { dg-final { scan-assembler "vmov.16" } } */ ++/* ++**foo2: ++** ... ++** vmov.16 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t b) ++{ ++ return vsetq_lane (1.1, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c +deleted file mode 100644 +index c5f5db7f28d..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo (float32_t a, float32x4_t b) +-{ +- return vsetq_lane (23.34, b, 0); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c +index 2b9f1a7e627..34b403d0601 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c +@@ -1,15 +1,53 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov.32 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32_t a, float32x4_t b) + { +- return vsetq_lane_f32 (a, b, 0); ++ return vsetq_lane_f32 (a, b, 1); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmov.32 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32_t a, float32x4_t b) ++{ ++ return vsetq_lane (a, b, 1); + } + +-/* { dg-final { scan-assembler "vmov.32" } } */ ++/* ++**foo2: ++** ... ++** vmov.32 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t b) ++{ ++ return vsetq_lane (1.1, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c +index 92ad0dd16a8..458fd5e6f26 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c +@@ -1,15 +1,41 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov.16 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16_t a, int16x8_t b) + { +- return vsetq_lane_s16 (a, b, 0); ++ return vsetq_lane_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vmov.16" } } */ + ++/* ++**foo1: ++** ... ++** vmov.16 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16_t a, int16x8_t b) ++{ ++ return vsetq_lane (a, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c +index e60c8f26700..44672f6c264 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c +@@ -1,15 +1,41 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov.32 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32_t a, int32x4_t b) + { +- return vsetq_lane_s32 (a, b, 0); ++ return vsetq_lane_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vmov.32" } } */ + ++/* ++**foo1: ++** ... ++** vmov.32 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32_t a, int32x4_t b) ++{ ++ return vsetq_lane (a, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c +index 430df669f2a..62e8ee50929 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c +@@ -1,16 +1,41 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +-/* { dg-require-effective-target arm_hard_ok } */ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-mfloat-abi=hard -O2" } */ ++/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int64x2_t + foo (int64_t a, int64x2_t b) + { +- return vsetq_lane_s64 (a, b, 0); ++ return vsetq_lane_s64 (a, b, 1); + } + +-/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]} } } */ + ++/* ++**foo1: ++** ... ++** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++int64x2_t ++foo1 (int64_t a, int64x2_t b) ++{ ++ return vsetq_lane (a, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c +index d8ccbb524fd..3a79ab1759b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c +@@ -1,15 +1,41 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov.8 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8_t a, int8x16_t b) + { +- return vsetq_lane_s8 (a, b, 0); ++ return vsetq_lane_s8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vmov.8" } } */ + ++/* ++**foo1: ++** ... ++** vmov.8 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++int8x16_t ++foo1 (int8_t a, int8x16_t b) ++{ ++ return vsetq_lane (a, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c +index 156a5d1de1b..8a42773e01f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c +@@ -1,15 +1,53 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov.16 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16_t a, uint16x8_t b) + { +- return vsetq_lane_u16 (a, b, 0); ++ return vsetq_lane_u16 (a, b, 1); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmov.16 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16_t a, uint16x8_t b) ++{ ++ return vsetq_lane (a, b, 1); + } + +-/* { dg-final { scan-assembler "vmov.16" } } */ ++/* ++**foo2: ++** ... ++** vmov.16 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t b) ++{ ++ return vsetq_lane (1, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c +index e9575483cc9..43778e6103d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c +@@ -1,15 +1,53 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov.32 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32_t a, uint32x4_t b) + { +- return vsetq_lane_u32 (a, b, 0); ++ return vsetq_lane_u32 (a, b, 1); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmov.32 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint32_t a, uint32x4_t b) ++{ ++ return vsetq_lane (a, b, 1); + } + +-/* { dg-final { scan-assembler "vmov.32" } } */ ++/* ++**foo2: ++** ... ++** vmov.32 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t b) ++{ ++ return vsetq_lane (1, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c +index 0e040121cf0..c75bfa448f0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c +@@ -1,16 +1,53 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +-/* { dg-require-effective-target arm_hard_ok } */ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ +-/* { dg-additional-options "-mfloat-abi=hard -O2" } */ ++/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint64x2_t + foo (uint64_t a, uint64x2_t b) + { +- return vsetq_lane_u64 (a, b, 0); ++ return vsetq_lane_u64 (a, b, 1); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint64x2_t ++foo1 (uint64_t a, uint64x2_t b) ++{ ++ return vsetq_lane (a, b, 1); + } + +-/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]} } } */ ++/* ++**foo2: ++** ... ++** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint64x2_t ++foo2 (uint64x2_t b) ++{ ++ return vsetq_lane (1, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c +index 668b3fea953..5fb20161259 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c +@@ -1,15 +1,53 @@ +-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmov.8 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8_t a, uint8x16_t b) + { +- return vsetq_lane_u8 (a, b, 0); ++ return vsetq_lane_u8 (a, b, 1); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmov.8 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (uint8_t a, uint8x16_t b) ++{ ++ return vsetq_lane (a, b, 1); + } + +-/* { dg-final { scan-assembler "vmov.8" } } */ ++/* ++**foo2: ++** ... ++** vmov.8 q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t b) ++{ ++ return vsetq_lane (1, b, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c +index c4c77f2559c..c603a89117f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, uint32_t * b, mve_pred16_t p) ++foo (int16x8_t a, uint32_t *b, mve_pred16_t p) + { +- return vshlcq_m_s16 (a, b, 32, p); ++ return vshlcq_m_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, uint32_t * b, mve_pred16_t p) ++foo1 (int16x8_t a, uint32_t *b, mve_pred16_t p) + { +- return vshlcq_m (a, b, 32, p); ++ return vshlcq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c +index 20cfd09c82d..46e75033ae6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, uint32_t * b, mve_pred16_t p) ++foo (int32x4_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, uint32_t * b, mve_pred16_t p) ++foo1 (int32x4_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c +index 33dde10e4a8..868de5df80b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, uint32_t * b, mve_pred16_t p) ++foo (int8x16_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_s8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, uint32_t * b, mve_pred16_t p) ++foo1 (int8x16_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c +index 2bf69f0c465..a1e1c3f9bc4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint32_t * b, mve_pred16_t p) ++foo (uint16x8_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint32_t * b, mve_pred16_t p) ++foo1 (uint16x8_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c +index e6650302ea7..bcb0bebd969 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32_t * b, mve_pred16_t p) ++foo (uint32x4_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32_t * b, mve_pred16_t p) ++foo1 (uint32x4_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c +index 95857f09371..98936447451 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint32_t * b, mve_pred16_t p) ++foo (uint8x16_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint32_t * b, mve_pred16_t p) ++foo1 (uint8x16_t a, uint32_t *b, mve_pred16_t p) + { + return vshlcq_m (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlct" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c +index ecd4fce5de3..e6c5069af21 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t +-foo (int16x8_t a, uint32_t * b) ++foo (int16x8_t a, uint32_t *b) + { + return vshlcq_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t +-foo1 (int16x8_t a, uint32_t * b) ++foo1 (int16x8_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c +index 2956b93138e..2c17845fd7e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t +-foo (int32x4_t a, uint32_t * b) ++foo (int32x4_t a, uint32_t *b) + { + return vshlcq_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t +-foo1 (int32x4_t a, uint32_t * b) ++foo1 (int32x4_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c +index cc22b1b1bd9..ab55f3a29ba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t +-foo (int8x16_t a, uint32_t * b) ++foo (int8x16_t a, uint32_t *b) + { + return vshlcq_s8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t +-foo1 (int8x16_t a, uint32_t * b) ++foo1 (int8x16_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c +index bbf6c531573..e1862be0249 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo (uint16x8_t a, uint32_t * b) ++foo (uint16x8_t a, uint32_t *b) + { + return vshlcq_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t +-foo1 (uint16x8_t a, uint32_t * b) ++foo1 (uint16x8_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c +index c42d9c10afe..dc1030fbedf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo (uint32x4_t a, uint32_t * b) ++foo (uint32x4_t a, uint32_t *b) + { + return vshlcq_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t +-foo1 (uint32x4_t a, uint32_t * b) ++foo1 (uint32x4_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c +index f24b22797c2..cb24651a294 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo (uint8x16_t a, uint32_t * b) ++foo (uint8x16_t a, uint32_t *b) + { + return vshlcq_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ + ++/* ++**foo1: ++** ... ++** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t +-foo1 (uint8x16_t a, uint32_t * b) ++foo1 (uint8x16_t a, uint32_t *b) + { + return vshlcq (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshlc" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c +index 6d6c4b2d737..1ee641d8d68 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshllbq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshllbq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c +index 5d7b9623f1a..93a06cb2676 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshllbq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshllbq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c +index 3697775ea0f..67039260cd5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshllbq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshllbq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c +index 39a10e21b0b..f02293bb874 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshllbq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshllbq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c +index 7d3a4d811cb..906f7fb75d1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a) + { + return vshllbq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshllb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a) + { + return vshllbq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c +index 63b406978c1..f63ff4b7556 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllb.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a) + { + return vshllbq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshllb.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a) + { + return vshllbq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c +index 9306d244645..883d2979f32 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a) + { + return vshllbq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshllb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a) + { + return vshllbq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c +index 0b24160216e..bbdec7ba321 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllb.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a) + { + return vshllbq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshllb.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a) + { + return vshllbq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllb.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c +index 689fc749b00..239c536f4a4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vshllbq_x_n_s16 (a, 1, p); ++ return vshllbq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int16x8_t a, mve_pred16_t p) ++{ ++ return vshllbq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c +index 82f684d1cd5..9371b523c3f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vshllbq_x_n_s8 (a, 1, p); ++ return vshllbq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int8x16_t a, mve_pred16_t p) ++{ ++ return vshllbq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c +index 5c51a4e4011..72f9aed343e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vshllbq_x_n_u16 (a, 1, p); ++ return vshllbq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vshllbq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c +index 5a713befb27..bd209428300 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vshllbq_x_n_u8 (a, 1, p); ++ return vshllbq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshllbt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vshllbq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c +index 8153a570a9a..80035011527 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshlltq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshlltq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c +index 3f47337c9b6..19e2f3c7469 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshlltq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshlltq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c +index f5af1b31087..46af8731146 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshlltq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshlltq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c +index 92154d25387..ed7814c39dc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshlltq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshlltq_m (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c +index ced2aa64217..b2987300406 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a) + { + return vshlltq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshllt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int16x8_t a) + { + return vshlltq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c +index 9fc0cd7ced9..c5b84aa5e2e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a) + { + return vshlltq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshllt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int8x16_t a) + { + return vshlltq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c +index 47b948e2468..358a5b4a3e7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a) + { + return vshlltq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshllt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint16x8_t a) + { + return vshlltq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c +index eac7422a1f1..223649215a6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshllt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a) + { + return vshlltq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshllt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint8x16_t a) + { + return vshlltq (a, 1); + } + +-/* { dg-final { scan-assembler "vshllt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c +index 0e9e789c1e0..12d55e49aed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vshlltq_x_n_s16 (a, 1, p); ++ return vshlltq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int16x8_t a, mve_pred16_t p) ++{ ++ return vshlltq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c +index 67966bed12c..dfad54a5eae 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vshlltq_x_n_s8 (a, 1, p); ++ return vshlltq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int8x16_t a, mve_pred16_t p) ++{ ++ return vshlltq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c +index dedc795797e..e9077d26918 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vshlltq_x_n_u16 (a, 1, p); ++ return vshlltq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vshlltq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c +index a93c69d8d98..1d4d2795fa9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vshlltq_x_n_u8 (a, 1, p); ++ return vshlltq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlltt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vshlltq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c +index 6c0342da0cc..754d412c81d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshlq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c +index 0e472801de5..5805f90a105 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vshlq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c +index 0f9efacc749..b69b52cf099 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshlq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c +index 0c4d9e9b7b5..152844bf318 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshlq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c +index cf247f879aa..9acfd9b8c6e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vshlq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c +index 64bda13216d..d2e7fe59f3f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshlq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { + return vshlq_m_n (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c +index abd747e9008..ce72e8c408b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c +index 001a8d170fc..219c7d2ca73 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c +index 890dd359e65..22fdee6bd6c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c +index 91574c5db26..25eca63907d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c +index f6ec8797a83..9d24eda6e60 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c +index 37f0f488801..2421e0b72ec 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b, mve_pred16_t p) + { + return vshlq_m_r (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c +index 759379c9fc5..c28996ad2cc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vshlq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c +index 4878f0b0e4f..ca4801df9ba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vshlq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c +index f4ed7f5aaeb..782eedbc774 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vshlq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c +index 99ae7ed9a53..941a6cc3578 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vshlq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c +index 7094ba2ccd7..75e10801ae7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vshlq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c +index e7c481a3b8c..dbabcd55900 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vshlq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vshlq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c +index e24bb9acd75..83dee27238a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { + return vshlq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { + return vshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c +index f537879249f..6b390c8b333 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { +- return vshlq_n_s32 (a, 16); ++ return vshlq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { +- return vshlq_n (a, 16); ++ return vshlq_n (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshl.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c +index ba6ddf3f8a1..e4fd7121bff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { + return vshlq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { + return vshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c +index 730c7af40c6..6c37303a9fe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vshlq_n_u16 (a, 11); ++ return vshlq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vshlq_n (a, 11); ++ return vshlq_n (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshl.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c +index 36caf5a9032..408f756408f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { + return vshlq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { + return vshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c +index a5ba9805d9b..5ecdddccadf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { + return vshlq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { + return vshlq_n (a, 1); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c +index b6d3e858d7c..f9a8257729e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32_t b) + { + return vshlq_r_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c +index e04e2a7bcf3..f4f8e363059 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vshlq_r_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c +index d5e54c0a79a..c14d012a1e2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int32_t b) + { + return vshlq_r_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c +index 813bea0575d..71634680deb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int32_t b) + { + return vshlq_r_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c +index 84a61e47ca7..0d47f85bc82 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32_t b) + { + return vshlq_r_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c +index 01f9a7d8f19..2d64908eeca 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int32_t b) + { + return vshlq_r_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int32_t b) + { + return vshlq_r (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c +index 5d3e1e5fdf9..6158fafcdb5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vshlq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c +index cecd050888f..b0b18470dea 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vshlq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c +index d44610f4f5b..70b2d806131 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vshlq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.s8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c +index 210fa905d3d..3ab782fa734 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b) + { + return vshlq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, int16x8_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c +index 8fc59620016..f104235caee 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b) + { + return vshlq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, int32x4_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c +index 8332d501640..1a93abfefb1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b) + { + return vshlq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, int8x16_t b) + { + return vshlq (a, b); + } + +-/* { dg-final { scan-assembler "vshl.u8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c +index 4bdbc848bb7..5ac725187e8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vshlq_x_n_s16 (a, 1, p); ++ return vshlq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c +index 7648d2e2c66..e5e3ab03f01 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { +- return vshlq_x_n_s32 (a, 1, p); ++ return vshlq_x_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c +index 4b303e92e81..7618d83b85b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vshlq_x_n_s8 (a, 1, p); ++ return vshlq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int8x16_t ++foo1 (int8x16_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c +index a2b6ac2d4c0..b4f937ae8f4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vshlq_x_n_u16 (a, 1, p); ++ return vshlq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c +index 59aa9dbe182..e42270ba293 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, mve_pred16_t p) + { +- return vshlq_x_n_u32 (a, 1, p); ++ return vshlq_x_n_u32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c +index 64069bb1728..7e01f8b2ab5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vshlq_x_n_u8 (a, 1, p); ++ return vshlq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vshlq_x_n (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c +index 61a643d64bd..a6eeff654e3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vshlq_x_s16 (a, b, p); ++ return vshlq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c +index 71424456f7d..cc3c434708a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vshlq_x_s32 (a, b, p); ++ return vshlq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c +index 0d4825a03ad..430a3ab43ed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vshlq_x_s8 (a, b, p); ++ return vshlq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++int8x16_t ++foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c +index 7ce18722444..9f5d0903588 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vshlq_x_u16 (a, b, p); ++ return vshlq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c +index fe02cc694a2..32d729f6954 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vshlq_x_u32 (a, b, p); ++ return vshlq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c +index 9611b268ca5..45e72c9dffa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vshlq_x_u8 (a, b, p); ++ return vshlq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshlt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) ++{ ++ return vshlq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c +index d069cb0db44..ab37f2605e0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vshrnbq_m_n_s16 (a, b, 8, p); ++ return vshrnbq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vshrnbq_m (a, b, 8, p); ++ return vshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c +index 50a450f5b52..9fd9f8a7804 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vshrnbq_m_n_s32 (a, b, 16, p); ++ return vshrnbq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vshrnbq_m (a, b, 16, p); ++ return vshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c +index e5762145e64..e9408eeb1bf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { +- return vshrnbq_m_n_u16 (a, b, 8, p); ++ return vshrnbq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { +- return vshrnbq_m (a, b, 8, p); ++ return vshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c +index 88da8e6f341..69699fd15ab 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { +- return vshrnbq_m_n_u32 (a, b, 16, p); ++ return vshrnbq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { +- return vshrnbq_m (a, b, 16, p); ++ return vshrnbq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrnbt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c +index 7fcd9e479dc..0320d690627 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { +- return vshrnbq_n_s16 (a, b, 8); ++ return vshrnbq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { +- return vshrnbq (a, b, 8); ++ return vshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnb.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c +index 38d4fdfc05f..aa7b107f7f9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { +- return vshrnbq_n_s32 (a, b, 16); ++ return vshrnbq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { +- return vshrnbq (a, b, 16); ++ return vshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnb.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c +index ff341a9f202..4f896469eb4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { +- return vshrnbq_n_u16 (a, b, 8); ++ return vshrnbq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnb.i16" } } */ + ++/* ++**foo1: ++** ... ++** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { +- return vshrnbq (a, b, 8); ++ return vshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnb.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c +index b891c036d36..d3d22978542 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { +- return vshrnbq_n_u32 (a, b, 16); ++ return vshrnbq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnb.i32" } } */ + ++/* ++**foo1: ++** ... ++** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { +- return vshrnbq (a, b, 16); ++ return vshrnbq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnb.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c +index 30535470961..77f39ac10c7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vshrntq_m_n_s16 (a, b, 8, p); ++ return vshrntq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p) + { +- return vshrntq_m (a, b, 8, p); ++ return vshrntq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c +index 2d52f5b6bb1..462d5f446f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vshrntq_m_n_s32 (a, b, 16, p); ++ return vshrntq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p) + { +- return vshrntq_m (a, b, 16, p); ++ return vshrntq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c +index ed774e0b31a..0328cc3ef93 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { +- return vshrntq_m_n_u16 (a, b, 8, p); ++ return vshrntq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p) + { +- return vshrntq_m (a, b, 8, p); ++ return vshrntq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c +index e592e96a5f9..d4882dc2d6d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { +- return vshrntq_m_n_u32 (a, b, 16, p); ++ return vshrntq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p) + { +- return vshrntq_m (a, b, 16, p); ++ return vshrntq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrntt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c +index ddd9d5c0507..c9016ac124f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int16x8_t b) + { +- return vshrntq_n_s16 (a, b, 8); ++ return vshrntq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int16x8_t b) + { +- return vshrntq (a, b, 8); ++ return vshrntq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c +index e35dbf07fac..6150f28d872 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int32x4_t b) + { +- return vshrntq_n_s32 (a, b, 16); ++ return vshrntq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int32x4_t b) + { +- return vshrntq (a, b, 16); ++ return vshrntq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c +index 58a6eea561a..75be307feaa 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint16x8_t b) + { +- return vshrntq_n_u16 (a, b, 8); ++ return vshrntq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint16x8_t b) + { +- return vshrntq (a, b, 8); ++ return vshrntq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnt.i16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c +index ec0c10007ff..9b9e534e3d2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint32x4_t b) + { +- return vshrntq_n_u32 (a, b, 16); ++ return vshrntq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vshrnt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint32x4_t b) + { +- return vshrntq (a, b, 16); ++ return vshrntq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshrnt.i32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c +index 00f236c6d74..ed1833b8673 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vshrq_m_n_s16 (inactive, a, 16, p); ++ return vshrq_m_n_s16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 16, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c +index 1d1be501e16..880cd9e3545 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vshrq_m_n_s32 (inactive, a, 32, p); ++ return vshrq_m_n_s32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 32, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c +index 7410ba9c8e9..53fc84857b7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vshrq_m_n_s8 (inactive, a, 8, p); ++ return vshrq_m_n_s8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 8, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c +index 4b0dd59eefa..c3e311454b6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { +- return vshrq_m_n_u16 (inactive, a, 16, p); ++ return vshrq_m_n_u16 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 16, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c +index 47ccc1b7499..6c0471f0120 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vshrq_m_n_u32 (inactive, a, 32, p); ++ return vshrq_m_n_u32 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 32, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c +index 44f96027a04..5621608a2eb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { +- return vshrq_m_n_u8 (inactive, a, 8, p); ++ return vshrq_m_n_u8 (inactive, a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) + { +- return vshrq_m (inactive, a, 8, p); ++ return vshrq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c +index 051fa4a14a1..59a589b21a1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a) + { +- return vshrq_n_s16 (a, 16); ++ return vshrq_n_s16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.s16" } } */ + ++/* ++**foo1: ++** ... ++** vshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a) + { +- return vshrq (a, 16); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.s16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c +index 65a0b2e6224..1666b6657f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a) + { +- return vshrq_n_s32 (a, 32); ++ return vshrq_n_s32 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.s32" } } */ + ++/* ++**foo1: ++** ... ++** vshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a) + { +- return vshrq (a, 32); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.s32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c +index c5adcc1a465..1ce29185bcf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a) + { +- return vshrq_n_s8 (a, 8); ++ return vshrq_n_s8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.s8" } } */ + ++/* ++**foo1: ++** ... ++** vshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a) + { +- return vshrq (a, 8); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.s8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c +index 1b68fafea8a..c2dbe6e5041 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a) + { +- return vshrq_n_u16 (a, 16); ++ return vshrq_n_u16 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.u16" } } */ + ++/* ++**foo1: ++** ... ++** vshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a) + { +- return vshrq (a, 16); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.u16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c +index 8b798b793c0..15d231c217f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a) + { +- return vshrq_n_u32 (a, 32); ++ return vshrq_n_u32 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.u32" } } */ + ++/* ++**foo1: ++** ... ++** vshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a) + { +- return vshrq (a, 32); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c +index 14cdf5917e2..19924e0fcdb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a) + { +- return vshrq_n_u8 (a, 8); ++ return vshrq_n_u8 (a, 1); + } + +-/* { dg-final { scan-assembler "vshr.u8" } } */ + ++/* ++**foo1: ++** ... ++** vshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a) + { +- return vshrq (a, 8); ++ return vshrq (a, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vshr.u8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c +index 4652693d75c..fc26fd8fd3b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, mve_pred16_t p) + { +- return vshrq_x_n_s16 (a, 16, p); ++ return vshrq_x_n_s16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c +index 43fa28a1f8d..bc9ae54faad 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, mve_pred16_t p) + { +- return vshrq_x_n_s32 (a, 32, p); ++ return vshrq_x_n_s32 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c +index 042bf488284..391ced24079 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, mve_pred16_t p) + { +- return vshrq_x_n_s8 (a, 8, p); ++ return vshrq_x_n_s8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.s8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++int8x16_t ++foo1 (int8x16_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c +index d627565fe84..eddb977fa83 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, mve_pred16_t p) + { +- return vshrq_x_n_u16 (a, 16, p); ++ return vshrq_x_n_u16 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c +index 0f26e7b9efc..6867668d1ce 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, mve_pred16_t p) + { +- return vshrq_x_n_u8 (a, 8, p); ++ return vshrq_x_n_u8 (a, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vshrt.u8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vshrq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c +index 49d342e7c17..23b346b1cab 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vsliq_m_n_s16 (a, b, 15, p); ++ return vsliq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 15, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c +index f0f7619dd0a..d640e1f8df4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vsliq_m_n_s32 (a, b, 31, p); ++ return vsliq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 31, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c +index 12d295e70f6..14b1afa1d01 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vsliq_m_n_s8 (a, b, 7, p); ++ return vsliq_m_n_s8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 7, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c +index 78cdbdf3950..521abbf4694 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { +- return vsliq_m_n_u16 (a, b, 15, p); ++ return vsliq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 15, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c +index 62e9cfd9f31..951204a31a0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { +- return vsliq_m_n_u32 (a, b, 31, p); ++ return vsliq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 31, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c +index f86fea32a90..8b893a8c4d2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { +- return vsliq_m_n_u8 (a, b, 7, p); ++ return vsliq_m_n_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { +- return vsliq_m (a, b, 7, p); ++ return vsliq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vslit.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c +index 2c5f82bb317..a6c86764eab 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { +- return vsliq_n_s16 (a, b, 15); ++ return vsliq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.16" } } */ + ++/* ++**foo1: ++** ... ++** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { +- return vsliq (a, b, 15); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c +index 0738fd61203..301cdd463b5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { +- return vsliq_n_s32 (a, b, 31); ++ return vsliq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.32" } } */ + ++/* ++**foo1: ++** ... ++** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { +- return vsliq (a, b, 31); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c +index 25f2f761c3c..2a26f7f444b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { +- return vsliq_n_s8 (a, b, 7); ++ return vsliq_n_s8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.8" } } */ + ++/* ++**foo1: ++** ... ++** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { +- return vsliq (a, b, 7); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c +index 25bbcd8f3fa..b71572a232e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { +- return vsliq_n_u16 (a, b, 15); ++ return vsliq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.16" } } */ + ++/* ++**foo1: ++** ... ++** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { +- return vsliq (a, b, 15); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c +index 970e069cabf..ecafb61b487 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { +- return vsliq_n_u32 (a, b, 31); ++ return vsliq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.32" } } */ + ++/* ++**foo1: ++** ... ++** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { +- return vsliq (a, b, 31); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c +index c24e354a957..e20ec7e030e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { +- return vsliq_n_u8 (a, b, 7); ++ return vsliq_n_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsli.8" } } */ + ++/* ++**foo1: ++** ... ++** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { +- return vsliq (a, b, 7); ++ return vsliq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsli.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c +index 799232a8dc1..086f5f86fc1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vsriq_m_n_s16 (a, b, 4, p); ++ return vsriq_m_n_s16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c +index 7e019782c88..90267f67e54 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vsriq_m_n_s32 (a, b, 2, p); ++ return vsriq_m_n_s32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 2, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c +index 8fa3e757f6d..6c7552905b4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vsriq_m_n_s8 (a, b, 4, p); ++ return vsriq_m_n_s8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c +index 5e2c4a3deb3..624732b0c91 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { +- return vsriq_m_n_u16 (a, b, 4, p); ++ return vsriq_m_n_u16 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c +index 368115e27b2..48abe8b9c0d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { +- return vsriq_m_n_u32 (a, b, 4, p); ++ return vsriq_m_n_u32 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c +index 54db7d78836..b1f9ecd0c9f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { +- return vsriq_m_n_u8 (a, b, 4, p); ++ return vsriq_m_n_u8 (a, b, 1, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsrit.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { +- return vsriq_m (a, b, 4, p); ++ return vsriq_m (a, b, 1, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vpst" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c +index 75f57ae76a7..2f8bde64ff5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { +- return vsriq_n_s16 (a, b, 4); ++ return vsriq_n_s16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.16" } } */ + ++/* ++**foo1: ++** ... ++** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c +index 46d9ead1e9a..a95e6dae8f7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { +- return vsriq_n_s32 (a, b, 4); ++ return vsriq_n_s32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.32" } } */ + ++/* ++**foo1: ++** ... ++** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c +index 3dcc5a34f90..7726a7ed934 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { +- return vsriq_n_s8 (a, b, 4); ++ return vsriq_n_s8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.8" } } */ + ++/* ++**foo1: ++** ... ++** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c +index ff6c4f0c277..4d8d5930b49 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { +- return vsriq_n_u16 (a, b, 4); ++ return vsriq_n_u16 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.16" } } */ + ++/* ++**foo1: ++** ... ++** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c +index f6b79b26235..83a6b13ef40 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { +- return vsriq_n_u32 (a, b, 4); ++ return vsriq_n_u32 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.32" } } */ + ++/* ++**foo1: ++** ... ++** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c +index 4c56b3ab00d..0bd9ac5ddfd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { +- return vsriq_n_u8 (a, b, 4); ++ return vsriq_n_u8 (a, b, 1); + } + +-/* { dg-final { scan-assembler "vsri.8" } } */ + ++/* ++**foo1: ++** ... ++** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { +- return vsriq (a, b, 4); ++ return vsriq (a, b, 1); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vsri.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c +index 312b7464f17..1fa02f00f53 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (float16_t * addr, float16x8_t value) +-{ +- vst1q_f16 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8_t value) ++foo (float16_t *base, float16x8_t value) + { +- vst1q (addr, value); ++ return vst1q_f16 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (float16_t a, float16x8_t x) ++foo1 (float16_t *base, float16x8_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c +index a6ae1cef2d4..67cc3ae3b47 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4_t value) ++foo (float32_t *base, float32x4_t value) + { +- vst1q_f32 (addr, value); ++ return vst1q_f32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4_t value) ++foo1 (float32_t *base, float32x4_t value) + { +- vst1q (addr, value); ++ return vst1q (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c +index f6db22d481a..06b2bd3910d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * addr, float16x8_t value, mve_pred16_t p) ++foo (float16_t *base, float16x8_t value, mve_pred16_t p) + { +- vst1q_p_f16 (addr, value, p); ++ return vst1q_p_f16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p) ++foo1 (float16_t *base, float16x8_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c +index 17e7f9c5dfd..e492a705ea0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4_t value, mve_pred16_t p) ++foo (float32_t *base, float32x4_t value, mve_pred16_t p) + { +- vst1q_p_f32 (addr, value, p); ++ return vst1q_p_f32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) ++foo1 (float32_t *base, float32x4_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c +index b142fc3b021..7b76d1d7687 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int16x8_t value, mve_pred16_t p) ++foo (int16_t *base, int16x8_t value, mve_pred16_t p) + { +- vst1q_p_s16 (addr, value, p); ++ return vst1q_p_s16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p) ++foo1 (int16_t *base, int16x8_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c +index 6334462e230..4ad32a68a96 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4_t value, mve_pred16_t p) ++foo (int32_t *base, int32x4_t value, mve_pred16_t p) + { +- vst1q_p_s32 (addr, value, p); ++ return vst1q_p_s32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) ++foo1 (int32_t *base, int32x4_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c +index 1f3f0343820..2425b9cec00 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int8x16_t value, mve_pred16_t p) ++foo (int8_t *base, int8x16_t value, mve_pred16_t p) + { +- vst1q_p_s8 (addr, value, p); ++ return vst1q_p_s8 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p) ++foo1 (int8_t *base, int8x16_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c +index 331cd34cdce..c0065ef6ff5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p) ++foo (uint16_t *base, uint16x8_t value, mve_pred16_t p) + { +- vst1q_p_u16 (addr, value, p); ++ return vst1q_p_u16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c +index 27836c32451..c41c4184b9b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) ++foo (uint32_t *base, uint32x4_t value, mve_pred16_t p) + { +- vst1q_p_u32 (addr, value, p); ++ return vst1q_p_u32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c +index bfbc542dc35..1cd3a781357 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p) ++foo (uint8_t *base, uint8x16_t value, mve_pred16_t p) + { +- vst1q_p_u8 (addr, value, p); ++ return vst1q_p_u8 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p) + { +- vst1q_p (addr, value, p); ++ return vst1q_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c +index cd14e2c408f..052959b2083 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (int16_t * addr, int16x8_t value) +-{ +- vst1q_s16 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8_t value) ++foo (int16_t *base, int16x8_t value) + { +- vst1q (addr, value); ++ return vst1q_s16 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (int16_t a, int16x8_t x) ++foo1 (int16_t *base, int16x8_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c +index e07e8a30f9d..444ad07f4ef 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4_t value) ++foo (int32_t *base, int32x4_t value) + { +- vst1q_s32 (addr, value); ++ return vst1q_s32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4_t value) ++foo1 (int32_t *base, int32x4_t value) + { +- vst1q (addr, value); ++ return vst1q (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c +index 0004c80963e..684ff0aca5b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (int8_t * addr, int8x16_t value) +-{ +- vst1q_s8 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16_t value) ++foo (int8_t *base, int8x16_t value) + { +- vst1q (addr, value); ++ return vst1q_s8 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (int8_t a, int8x16_t x) ++foo1 (int8_t *base, int8x16_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c +index 248e7ce82b0..1fea2de1e76 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (uint16_t * addr, uint16x8_t value) +-{ +- vst1q_u16 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8_t value) ++foo (uint16_t *base, uint16x8_t value) + { +- vst1q (addr, value); ++ return vst1q_u16 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (uint16_t a, uint16x8_t x) ++foo1 (uint16_t *base, uint16x8_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c +index d1fdf8897b5..64c43c59d47 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4_t value) ++foo (uint32_t *base, uint32x4_t value) + { +- vst1q_u32 (addr, value); ++ return vst1q_u32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4_t value) ++foo1 (uint32_t *base, uint32x4_t value) + { +- vst1q (addr, value); ++ return vst1q (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c +index f8b48a69903..5517611bba6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c +@@ -1,25 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + +-void +-foo (uint8_t * addr, uint8x16_t value) +-{ +- vst1q_u8 (addr, value); +-} ++#ifdef __cplusplus ++extern "C" { ++#endif + ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16_t value) ++foo (uint8_t *base, uint8x16_t value) + { +- vst1q (addr, value); ++ return vst1q_u8 (base, value); + } + +-/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo2 (uint8_t a, uint8x16_t x) ++foo1 (uint8_t *base, uint8x16_t value) + { +- vst1q (&a, x); ++ return vst1q (base, value); + } ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c +index 64650e26bcb..5180667658e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * addr, float16x8x2_t value) ++foo (float16_t *addr, float16x8x2_t value) + { +- vst2q_f16 (addr, value); ++ return vst2q_f16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.16" } } */ +-/* { dg-final { scan-assembler "vst21.16" } } */ + ++/* ++**foo1: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8x2_t value) ++foo1 (float16_t *addr, float16x8x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c +index 8840afb867d..3e6f5b0ed75 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4x2_t value) ++foo (float32_t *addr, float32x4x2_t value) + { +- vst2q_f32 (addr, value); ++ return vst2q_f32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.32" } } */ +-/* { dg-final { scan-assembler "vst21.32" } } */ + ++/* ++**foo1: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4x2_t value) ++foo1 (float32_t *addr, float32x4x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c +index 15182c5eee0..1c939317779 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int16x8x2_t value) ++foo (int16_t *addr, int16x8x2_t value) + { +- vst2q_s16 (addr, value); ++ return vst2q_s16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.16" } } */ +-/* { dg-final { scan-assembler "vst21.16" } } */ + ++/* ++**foo1: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8x2_t value) ++foo1 (int16_t *addr, int16x8x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c +index 11c92463ae4..28c8e078942 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4x2_t value) ++foo (int32_t *addr, int32x4x2_t value) + { +- vst2q_s32 (addr, value); ++ return vst2q_s32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.32" } } */ +-/* { dg-final { scan-assembler "vst21.32" } } */ + ++/* ++**foo1: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4x2_t value) ++foo1 (int32_t *addr, int32x4x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c +index 90257ae5dae..e882c01bd63 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int8x16x2_t value) ++foo (int8_t *addr, int8x16x2_t value) + { +- vst2q_s8 (addr, value); ++ return vst2q_s8 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.8" } } */ +-/* { dg-final { scan-assembler "vst21.8" } } */ + ++/* ++**foo1: ++** ... ++** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16x2_t value) ++foo1 (int8_t *addr, int8x16x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c +index a8a7c49757a..0cfbd6b9902 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8x2_t value) ++foo (uint16_t *addr, uint16x8x2_t value) + { +- vst2q_u16 (addr, value); ++ return vst2q_u16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.16" } } */ +-/* { dg-final { scan-assembler "vst21.16" } } */ + ++/* ++**foo1: ++** ... ++** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8x2_t value) ++foo1 (uint16_t *addr, uint16x8x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c +index b5d78180995..ea46a5969d0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4x2_t value) ++foo (uint32_t *addr, uint32x4x2_t value) + { +- vst2q_u32 (addr, value); ++ return vst2q_u32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.32" } } */ +-/* { dg-final { scan-assembler "vst21.32" } } */ + ++/* ++**foo1: ++** ... ++** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4x2_t value) ++foo1 (uint32_t *addr, uint32x4x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c +index 4e7d6fea7ed..895c2ccf425 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c +@@ -1,22 +1,45 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16x2_t value) ++foo (uint8_t *addr, uint8x16x2_t value) + { +- vst2q_u8 (addr, value); ++ return vst2q_u8 (addr, value); + } + +-/* { dg-final { scan-assembler "vst20.8" } } */ +-/* { dg-final { scan-assembler "vst21.8" } } */ + ++/* ++**foo1: ++** ... ++** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16x2_t value) ++foo1 (uint8_t *addr, uint8x16x2_t value) + { +- vst2q (addr, value); ++ return vst2q (addr, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vst20.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c +index 0da66894e2c..94066089f58 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (float16_t * addr, float16x8x4_t value) ++foo (float16_t *addr, float16x8x4_t value) + { +- vst4q_f16 (addr, value); ++ return vst4q_f16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ + ++/* ++**foo1: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8x4_t value) ++foo1 (float16_t *addr, float16x8x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ +- +-void +-foo2 (float16_t * addr, float16x8x4_t value) +-{ +- vst4q_f16 (addr, value); +- addr += 32; +- vst4q_f16 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c +index c1614bd10fc..0150ba7ca56 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (float32_t * addr, float32x4x4_t value) ++foo (float32_t *addr, float32x4x4_t value) + { +- vst4q_f32 (addr, value); ++ return vst4q_f32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ + ++/* ++**foo1: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4x4_t value) ++foo1 (float32_t *addr, float32x4x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ +- +-void +-foo2 (float32_t * addr, float32x4x4_t value) +-{ +- vst4q_f32 (addr, value); +- addr += 16; +- vst4q_f32 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c +index e1250449bee..8c9df15b3c7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (int16_t * addr, int16x8x4_t value) ++foo (int16_t *addr, int16x8x4_t value) + { +- vst4q_s16 (addr, value); ++ return vst4q_s16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ + ++/* ++**foo1: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8x4_t value) ++foo1 (int16_t *addr, int16x8x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ +- +-void +-foo2 (int16_t * addr, int16x8x4_t value) +-{ +- vst4q_s16 (addr, value); +- addr += 32; +- vst4q_s16 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c +index e6e1272744e..1a1a9797360 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (int32_t * addr, int32x4x4_t value) ++foo (int32_t *addr, int32x4x4_t value) + { +- vst4q_s32 (addr, value); ++ return vst4q_s32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ + ++/* ++**foo1: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4x4_t value) ++foo1 (int32_t *addr, int32x4x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ +- +-void +-foo2 (int32_t * addr, int32x4x4_t value) +-{ +- vst4q_s32 (addr, value); +- addr += 16; +- vst4q_s32 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c +index 16eb488ff99..d23032a73bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (int8_t * addr, int8x16x4_t value) ++foo (int8_t *addr, int8x16x4_t value) + { +- vst4q_s8 (addr, value); ++ return vst4q_s8 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.8" } } */ +-/* { dg-final { scan-assembler "vst41.8" } } */ +-/* { dg-final { scan-assembler "vst42.8" } } */ +-/* { dg-final { scan-assembler "vst43.8" } } */ + ++/* ++**foo1: ++** ... ++** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16x4_t value) ++foo1 (int8_t *addr, int8x16x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.8" } } */ +-/* { dg-final { scan-assembler "vst41.8" } } */ +-/* { dg-final { scan-assembler "vst42.8" } } */ +-/* { dg-final { scan-assembler "vst43.8" } } */ +- +-void +-foo2 (int8_t * addr, int8x16x4_t value) +-{ +- vst4q_s8 (addr, value); +- addr += 16*4; +- vst4q_s8 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c +index afd60306d0d..76cc4311e1b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8x4_t value) ++foo (uint16_t *addr, uint16x8x4_t value) + { +- vst4q_u16 (addr, value); ++ return vst4q_u16 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ + ++/* ++**foo1: ++** ... ++** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8x4_t value) ++foo1 (uint16_t *addr, uint16x8x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.16" } } */ +-/* { dg-final { scan-assembler "vst41.16" } } */ +-/* { dg-final { scan-assembler "vst42.16" } } */ +-/* { dg-final { scan-assembler "vst43.16" } } */ +- +-void +-foo2 (uint16_t * addr, uint16x8x4_t value) +-{ +- vst4q_u16 (addr, value); +- addr += 32; +- vst4q_u16 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c +index 755dd689dff..e5f62858eee 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4x4_t value) ++foo (uint32_t *addr, uint32x4x4_t value) + { +- vst4q_u32 (addr, value); ++ return vst4q_u32 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ + ++/* ++**foo1: ++** ... ++** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4x4_t value) ++foo1 (uint32_t *addr, uint32x4x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.32" } } */ +-/* { dg-final { scan-assembler "vst41.32" } } */ +-/* { dg-final { scan-assembler "vst42.32" } } */ +-/* { dg-final { scan-assembler "vst43.32" } } */ +- +-void +-foo2 (uint32_t * addr, uint32x4x4_t value) +-{ +- vst4q_u32 (addr, value); +- addr += 16; +- vst4q_u32 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c +index 0b28451df55..923cd0d3b10 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c +@@ -1,37 +1,47 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16x4_t value) ++foo (uint8_t *addr, uint8x16x4_t value) + { +- vst4q_u8 (addr, value); ++ return vst4q_u8 (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.8" } } */ +-/* { dg-final { scan-assembler "vst41.8" } } */ +-/* { dg-final { scan-assembler "vst42.8" } } */ +-/* { dg-final { scan-assembler "vst43.8" } } */ + ++/* ++**foo1: ++** ... ++** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\] ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16x4_t value) ++foo1 (uint8_t *addr, uint8x16x4_t value) + { +- vst4q (addr, value); ++ return vst4q (addr, value); + } + +-/* { dg-final { scan-assembler "vst40.8" } } */ +-/* { dg-final { scan-assembler "vst41.8" } } */ +-/* { dg-final { scan-assembler "vst42.8" } } */ +-/* { dg-final { scan-assembler "vst43.8" } } */ +- +-void +-foo2 (uint8_t * addr, uint8x16x4_t value) +-{ +- vst4q_u8 (addr, value); +- addr += 16*4; +- vst4q_u8 (addr, value); ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c +index ad74d8aa2e9..19804443e01 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int16x8_t value, mve_pred16_t p) ++foo (int8_t *base, int16x8_t value, mve_pred16_t p) + { +- vstrbq_p_s16 (addr, value, p); ++ return vstrbq_p_s16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int16x8_t value, mve_pred16_t p) ++foo1 (int8_t *base, int16x8_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c +index 46fd4549ffb..26be212770b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int32x4_t value, mve_pred16_t p) ++foo (int8_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrbq_p_s32 (addr, value, p); ++ return vstrbq_p_s32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int32x4_t value, mve_pred16_t p) ++foo1 (int8_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c +index 8e70b9eb098..a0d08772a50 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int8x16_t value, mve_pred16_t p) ++foo (int8_t *base, int8x16_t value, mve_pred16_t p) + { +- vstrbq_p_s8 (addr, value, p); ++ return vstrbq_p_s8 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p) ++foo1 (int8_t *base, int8x16_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c +index 180f9033edd..bc02c59887a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint16x8_t value, mve_pred16_t p) ++foo (uint8_t *base, uint16x8_t value, mve_pred16_t p) + { +- vstrbq_p_u16 (addr, value, p); ++ return vstrbq_p_u16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint16x8_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint16x8_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c +index 1b944fc9ffc..1215d5f0978 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint32x4_t value, mve_pred16_t p) ++foo (uint8_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrbq_p_u32 (addr, value, p); ++ return vstrbq_p_u32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint32x4_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c +index 7e73cbff84e..a88234e411d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p) ++foo (uint8_t *base, uint8x16_t value, mve_pred16_t p) + { +- vstrbq_p_u8 (addr, value, p); ++ return vstrbq_p_u8 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p) + { +- vstrbq_p (addr, value, p); ++ return vstrbq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c +index 4d12bc2cd19..1e88d3aa600 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int16x8_t value) ++foo (int8_t *base, int16x8_t value) + { +- vstrbq_s16 (addr, value); ++ return vstrbq_s16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int16x8_t value) ++foo1 (int8_t *base, int16x8_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c +index 750413f35ae..12764bf3041 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int32x4_t value) ++foo (int8_t *base, int32x4_t value) + { +- vstrbq_s32 (addr, value); ++ return vstrbq_s32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int32x4_t value) ++foo1 (int8_t *base, int32x4_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c +index 7ffb2c51976..05a9e5c42ce 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * addr, int8x16_t value) ++foo (int8_t *base, int8x16_t value) + { +- vstrbq_s8 (addr, value); ++ return vstrbq_s8 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.8" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * addr, int8x16_t value) ++foo1 (int8_t *base, int8x16_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c +index f59fa349cc0..052c3f85b75 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_s16 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_s16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo1 (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c +index 737c1008976..57410e46a8a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_s32 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c +index 8b2d06807b4..c3cdefdf078 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) ++foo (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_s8 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_s8 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) ++foo1 (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c +index 0adccaac39c..0868cc2248b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_u16 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_u16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c +index 308119294df..9d769941569 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_u32 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c +index 28b2ca4b83a..4586535d600 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) ++foo (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p_u8 (base, offset, value, p); ++ return vstrbq_scatter_offset_p_u8 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) ++foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p) + { +- vstrbq_scatter_offset_p (base, offset, value, p); ++ return vstrbq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrbt.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c +index e6cf1828b33..179b96f4973 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint16x8_t offset, int16x8_t value) ++foo (int8_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrbq_scatter_offset_s16 (base, offset, value); ++ return vstrbq_scatter_offset_s16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value) ++foo1 (int8_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c +index 052e02a7cf9..e7b7767c9f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint32x4_t offset, int32x4_t value) ++foo (int8_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrbq_scatter_offset_s32 (base, offset, value); ++ return vstrbq_scatter_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int8_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c +index 523f318e73c..f47bdd1a630 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int8_t * base, uint8x16_t offset, int8x16_t value) ++foo (int8_t *base, uint8x16_t offset, int8x16_t value) + { +- vstrbq_scatter_offset_s8 (base, offset, value); ++ return vstrbq_scatter_offset_s8 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.8" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value) ++foo1 (int8_t *base, uint8x16_t offset, int8x16_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c +index 49d4d31ad21..90e8cf351f9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value) ++foo (uint8_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrbq_scatter_offset_u16 (base, offset, value); ++ return vstrbq_scatter_offset_u16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value) ++foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c +index 0012852298c..e5449aa0942 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint8_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrbq_scatter_offset_u32 (base, offset, value); ++ return vstrbq_scatter_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c +index e54422a1afe..06c8c45e877 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value) ++foo (uint8_t *base, uint8x16_t offset, uint8x16_t value) + { +- vstrbq_scatter_offset_u8 (base, offset, value); ++ return vstrbq_scatter_offset_u8 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrb.8" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value) ++foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value) + { +- vstrbq_scatter_offset (base, offset, value); ++ return vstrbq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c +index 9fa9d18c6a1..0b350e2491b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint16x8_t value) ++foo (uint8_t *base, uint16x8_t value) + { +- vstrbq_u16 (addr, value); ++ return vstrbq_u16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint16x8_t value) ++foo1 (uint8_t *base, uint16x8_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c +index e535aa275ef..2f809356420 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint32x4_t value) ++foo (uint8_t *base, uint32x4_t value) + { +- vstrbq_u32 (addr, value); ++ return vstrbq_u32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint32x4_t value) ++foo1 (uint8_t *base, uint32x4_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c +index 93771aabcbd..deeea98dda5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint8_t * addr, uint8x16_t value) ++foo (uint8_t *base, uint8x16_t value) + { +- vstrbq_u8 (addr, value); ++ return vstrbq_u8 (base, value); + } + +-/* { dg-final { scan-assembler "vstrb.8" } } */ + ++/* ++**foo1: ++** ... ++** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint8_t * addr, uint8x16_t value) ++foo1 (uint8_t *base, uint8x16_t value) + { +- vstrbq (addr, value); ++ return vstrbq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrb.8" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c +index c694e2b6ad3..25a889dd1f0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p) ++foo (uint64x2_t addr, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_p_s64 (addr, 8, value, p); ++ return vstrdq_scatter_base_p_s64 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p) ++foo1 (uint64x2_t addr, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_p (addr, 8, value, p); ++ return vstrdq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c +index 6e8507c81d9..f0731f69a09 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p) ++foo (uint64x2_t addr, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_p_u64 (addr, 8, value, p); ++ return vstrdq_scatter_base_p_u64 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.u64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p) ++foo1 (uint64x2_t addr, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_p (addr, 8, value, p); ++ return vstrdq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c +index b9aac8036d4..31cdec9ba0a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t addr, const int offset, int64x2_t value) ++foo (uint64x2_t addr, int64x2_t value) + { +- vstrdq_scatter_base_s64 (addr, 1016, value); ++ return vstrdq_scatter_base_s64 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t addr, const int offset, int64x2_t value) ++foo1 (uint64x2_t addr, int64x2_t value) + { +- vstrdq_scatter_base (addr, 1016, value); ++ return vstrdq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c +index 888d4e0c031..8f0195c9e8f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t addr, const int offset, uint64x2_t value) ++foo (uint64x2_t addr, uint64x2_t value) + { +- vstrdq_scatter_base_u64 (addr, 8, value); ++ return vstrdq_scatter_base_u64 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrd.u64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t addr, const int offset, uint64x2_t value) ++foo1 (uint64x2_t addr, uint64x2_t value) + { +- vstrdq_scatter_base (addr, 8, value); ++ return vstrdq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.u64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c +index 319188b706f..8f19ede4e1a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p) ++foo (uint64x2_t *addr, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_wb_p_s64 (addr, 8, value, p); ++ return vstrdq_scatter_base_wb_p_s64 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p) ++foo1 (uint64x2_t *addr, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrdq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c +index 940b5421c84..41958c961f4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p) ++foo (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_wb_p_u64 (addr, 8, value, p); ++ return vstrdq_scatter_base_wb_p_u64 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p) ++foo1 (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrdq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c +index 33926d5c9e2..fc06db1c202 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t * addr, const int offset, int64x2_t value) ++foo (uint64x2_t *addr, int64x2_t value) + { +- vstrdq_scatter_base_wb_s64 (addr, 8, value); ++ return vstrdq_scatter_base_wb_s64 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t * addr, const int offset, int64x2_t value) ++foo1 (uint64x2_t *addr, int64x2_t value) + { +- vstrdq_scatter_base_wb (addr, 8, value); ++ return vstrdq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c +index b7ffcf9b5dd..c6529e617e3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint64x2_t * addr, const int offset, uint64x2_t value) ++foo (uint64x2_t *addr, uint64x2_t value) + { +- vstrdq_scatter_base_wb_u64 (addr, 8, value); ++ return vstrdq_scatter_base_wb_u64 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value) ++foo1 (uint64x2_t *addr, uint64x2_t value) + { +- vstrdq_scatter_base_wb (addr, 8, value); ++ return vstrdq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c +index 7ebf858f816..754fb59df4c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) ++foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_offset_p_s64 (base, offset, value, p); ++ return vstrdq_scatter_offset_p_s64 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) ++foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_offset_p (base, offset, value, p); ++ return vstrdq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c +index 4829bada1a9..046f29a6621 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) ++foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_offset_p_u64 (base, offset, value, p); ++ return vstrdq_scatter_offset_p_u64 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) ++foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_offset_p (base, offset, value, p); ++ return vstrdq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c +index fb7317bc4d7..73e25cdf0ed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int64_t * base, uint64x2_t offset, int64x2_t value) ++foo (int64_t *base, uint64x2_t offset, int64x2_t value) + { +- vstrdq_scatter_offset_s64 (base, offset, value); ++ return vstrdq_scatter_offset_s64 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrd.64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value) ++foo1 (int64_t *base, uint64x2_t offset, int64x2_t value) + { +- vstrdq_scatter_offset (base, offset, value); ++ return vstrdq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c +index e8b3a0210b4..d49adde0b94 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value) ++foo (uint64_t *base, uint64x2_t offset, uint64x2_t value) + { +- vstrdq_scatter_offset_u64 (base, offset, value); ++ return vstrdq_scatter_offset_u64 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrd.64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value) ++foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value) + { +- vstrdq_scatter_offset (base, offset, value); ++ return vstrdq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c +index 9ca83e0f3fd..8acfba1f55e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) ++foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p); ++ return vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) ++foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrdq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c +index 1c33df18e84..630c627d604 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) ++foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p); ++ return vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) ++foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p) + { +- vstrdq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrdq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrdt.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c +index 8af348ddbe2..ec73bca4869 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo (int64_t * base, uint64x2_t offset, int64x2_t value) ++foo (int64_t *base, uint64x2_t offset, int64x2_t value) + { +- vstrdq_scatter_shifted_offset_s64 (base, offset, value); ++ return vstrdq_scatter_shifted_offset_s64 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrd.64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value) ++foo1 (int64_t *base, uint64x2_t offset, int64x2_t value) + { +- vstrdq_scatter_shifted_offset (base, offset, value); ++ return vstrdq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c +index bc153a07192..9bdf8003961 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value) ++foo (uint64_t *base, uint64x2_t offset, uint64x2_t value) + { +- vstrdq_scatter_shifted_offset_u64 (base, offset, value); ++ return vstrdq_scatter_shifted_offset_u64 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrd.64" } } */ + ++/* ++**foo1: ++** ... ++** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value) ++foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value) + { +- vstrdq_scatter_shifted_offset (base, offset, value); ++ return vstrdq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrd.64" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c +index 74e2617c380..a41217b24f2 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * addr, float16x8_t value) ++foo (float16_t *base, float16x8_t value) + { +- vstrhq_f16 (addr, value); ++ return vstrhq_f16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8_t value) ++foo1 (float16_t *base, float16x8_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c +index 227da4f10aa..8398a60023d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * addr, float16x8_t value, mve_pred16_t p) ++foo (float16_t *base, float16x8_t value, mve_pred16_t p) + { +- vstrhq_p_f16 (addr, value, p); ++ return vstrhq_p_f16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p) ++foo1 (float16_t *base, float16x8_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c +index f3ba71f0ce1..ee1026801be 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int16x8_t value, mve_pred16_t p) ++foo (int16_t *base, int16x8_t value, mve_pred16_t p) + { +- vstrhq_p_s16 (addr, value, p); ++ return vstrhq_p_s16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p) ++foo1 (int16_t *base, int16x8_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c +index dab646706ce..b8490209644 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int32x4_t value, mve_pred16_t p) ++foo (int16_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrhq_p_s32 (addr, value, p); ++ return vstrhq_p_s32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int32x4_t value, mve_pred16_t p) ++foo1 (int16_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c +index e575c70cc44..59fb73cef19 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p) ++foo (uint16_t *base, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_p_u16 (addr, value, p); ++ return vstrhq_p_u16 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c +index e863e284c3c..ed66db7f8ce 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint32x4_t value, mve_pred16_t p) ++foo (uint16_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_p_u32 (addr, value, p); ++ return vstrhq_p_u32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint32x4_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_p (addr, value, p); ++ return vstrhq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c +index 5e47fb4e1a6..972d733c5bd 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int16x8_t value) ++foo (int16_t *base, int16x8_t value) + { +- vstrhq_s16 (addr, value); ++ return vstrhq_s16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int16x8_t value) ++foo1 (int16_t *base, int16x8_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c +index 73e01c9acfb..f260c61c3a8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * addr, int32x4_t value) ++foo (int16_t *base, int32x4_t value) + { +- vstrhq_s32 (addr, value); ++ return vstrhq_s32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * addr, int32x4_t value) ++foo1 (int16_t *base, int32x4_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c +index d29bd08ad0a..794d75e76ac 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * base, uint16x8_t offset, float16x8_t value) ++foo (float16_t *base, uint16x8_t offset, float16x8_t value) + { +- vstrhq_scatter_offset_f16 (base, offset, value); ++ return vstrhq_scatter_offset_f16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value) ++foo1 (float16_t *base, uint16x8_t offset, float16x8_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c +index 79d9827b378..1fd5a0773dc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) ++foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_f16 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_f16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) ++foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c +index 1b401d4c5b7..34c44a90541 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_s16 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_s16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c +index afb325b9789..2a84b28a3f5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_s32 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c +index 73bee831282..f1c875657ce 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_u16 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_u16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c +index bae7c2d14c2..913fd8d5591 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p_u32 (base, offset, value, p); ++ return vstrhq_scatter_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_offset_p (base, offset, value, p); ++ return vstrhq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c +index bf3c03a85c6..b322d0fa02e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint16x8_t offset, int16x8_t value) ++foo (int16_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrhq_scatter_offset_s16 (base, offset, value); ++ return vstrhq_scatter_offset_s16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value) ++foo1 (int16_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c +index 0591ab55c07..49fcc3a382b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint32x4_t offset, int32x4_t value) ++foo (int16_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrhq_scatter_offset_s32 (base, offset, value); ++ return vstrhq_scatter_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int16_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c +index 0a2fa1f410e..b5de540a74c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value) ++foo (uint16_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrhq_scatter_offset_u16 (base, offset, value); ++ return vstrhq_scatter_offset_u16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value) ++foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c +index 809a44dee16..7808f25d4a4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint16_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrhq_scatter_offset_u32 (base, offset, value); ++ return vstrhq_scatter_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrhq_scatter_offset (base, offset, value); ++ return vstrhq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c +index 1dcb1f7692d..6d57a22fe41 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * base, uint16x8_t offset, float16x8_t value) ++foo (float16_t *base, uint16x8_t offset, float16x8_t value) + { +- vstrhq_scatter_shifted_offset_f16 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_f16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value) ++foo1 (float16_t *base, uint16x8_t offset, float16x8_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c +index c46eec95adf..2e77dd492a1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) ++foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) ++foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c +index 7e9a549e8c2..1c83a13ffdf 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) ++foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c +index 502b4b00e2a..6d786de4379 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c +index 151145ce174..fd73168ddbb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c +index 14efd952593..689195ce603 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrht.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrhq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrht.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c +index e5142ed85f7..0edacd938f6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint16x8_t offset, int16x8_t value) ++foo (int16_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrhq_scatter_shifted_offset_s16 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_s16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value) ++foo1 (int16_t *base, uint16x8_t offset, int16x8_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c +index 431808f9008..ebda2faec92 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (int16_t * base, uint32x4_t offset, int32x4_t value) ++foo (int16_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrhq_scatter_shifted_offset_s32 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int16_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c +index f93e5d51913..abe8bbf8045 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value) ++foo (uint16_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrhq_scatter_shifted_offset_u16 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_u16 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value) ++foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c +index fc250706fa8..a01b04bd940 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint16_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrhq_scatter_shifted_offset_u32 (base, offset, value); ++ return vstrhq_scatter_shifted_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrhq_scatter_shifted_offset (base, offset, value); ++ return vstrhq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c +index f7b3ef1012b..85f5790ff49 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint16x8_t value) ++foo (uint16_t *base, uint16x8_t value) + { +- vstrhq_u16 (addr, value); ++ return vstrhq_u16 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.16" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint16x8_t value) ++foo1 (uint16_t *base, uint16x8_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.16" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c +index 8e01fd10032..d0958e22222 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint16_t * addr, uint32x4_t value) ++foo (uint16_t *base, uint32x4_t value) + { +- vstrhq_u32 (addr, value); ++ return vstrhq_u32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrh.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint16_t * addr, uint32x4_t value) ++foo1 (uint16_t *base, uint32x4_t value) + { +- vstrhq (addr, value); ++ return vstrhq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrh.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c +index 8aa04fcbdee..e92ecb0f6bc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4_t value) ++foo (float32_t *base, float32x4_t value) + { +- vstrwq_f32 (addr, value); ++ return vstrwq_f32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4_t value) ++foo1 (float32_t *base, float32x4_t value) + { +- vstrwq (addr, value); ++ return vstrwq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c +index 411de6414f7..f1992a67736 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * addr, float32x4_t value, mve_pred16_t p) ++foo (float32_t *base, float32x4_t value, mve_pred16_t p) + { +- vstrwq_p_f32 (addr, value, p); ++ return vstrwq_p_f32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) ++foo1 (float32_t *base, float32x4_t value, mve_pred16_t p) + { +- vstrwq_p (addr, value, p); ++ return vstrwq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c +index 3b042814d27..a00aeabb9fe 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4_t value, mve_pred16_t p) ++foo (int32_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrwq_p_s32 (addr, value, p); ++ return vstrwq_p_s32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) ++foo1 (int32_t *base, int32x4_t value, mve_pred16_t p) + { +- vstrwq_p (addr, value, p); ++ return vstrwq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c +index b9e92204c88..05fded8aac8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) ++foo (uint32_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_p_u32 (addr, value, p); ++ return vstrwq_p_u32 (base, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_p (addr, value, p); ++ return vstrwq_p (base, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c +index c7b3d91a972..b2a184f3c66 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * addr, int32x4_t value) ++foo (int32_t *base, int32x4_t value) + { +- vstrwq_s32 (addr, value); ++ return vstrwq_s32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * addr, int32x4_t value) ++foo1 (int32_t *base, int32x4_t value) + { +- vstrwq (addr, value); ++ return vstrwq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c +index f8b56917295..c80e8d9cdc5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, float32x4_t value) + { +- vstrwq_scatter_base_f32 (addr, 8, value); ++ return vstrwq_scatter_base_f32 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, float32x4_t value) + { +- vstrwq_scatter_base (addr, 8, value); ++ return vstrwq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c +index 4a75e6503e1..237843c0661 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p_f32 (addr, 8, value, p); ++ return vstrwq_scatter_base_p_f32 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p (addr, 8, value, p); ++ return vstrwq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c +index 5ac4f300a7d..5f4f4a09664 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p_s32 (addr, 8, value, p); ++ return vstrwq_scatter_base_p_s32 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p (addr, 8, value, p); ++ return vstrwq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c +index e564f26b9c7..8c5cf63f861 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p_u32 (addr, 8, value, p); ++ return vstrwq_scatter_base_p_u32 (addr, 0, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_p (addr, 8, value, p); ++ return vstrwq_scatter_base_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c +index 5bba36db5cb..5208cf4f808 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, int32x4_t value) + { +- vstrwq_scatter_base_s32 (addr, 8, value); ++ return vstrwq_scatter_base_s32 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, int32x4_t value) + { +- vstrwq_scatter_base (addr, 8, value); ++ return vstrwq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c +index 1dcbb5a739c..e728db2b9f1 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo (uint32x4_t addr, uint32x4_t value) + { +- vstrwq_scatter_base_u32 (addr, 8, value); ++ return vstrwq_scatter_base_u32 (addr, 0, value); + } + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) ++** ... ++*/ + void + foo1 (uint32x4_t addr, uint32x4_t value) + { +- vstrwq_scatter_base (addr, 8, value); ++ return vstrwq_scatter_base (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.u32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c +index b2cc6e555ae..e481191aa57 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, float32x4_t value) ++foo (uint32x4_t *addr, float32x4_t value) + { +- vstrwq_scatter_base_wb_f32 (addr, 8, value); ++ return vstrwq_scatter_base_wb_f32 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, float32x4_t value) ++foo1 (uint32x4_t *addr, float32x4_t value) + { +- vstrwq_scatter_base_wb (addr, 8, value); ++ return vstrwq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c +index 4befd49d7b9..8d217d46230 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) ++foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) ++foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c +index dfb1827c4f0..afc47adcd7f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) ++foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) ++foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c +index 4eb78c600be..65191c2f1ed 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c +@@ -1,19 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) ++foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p); + } + ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_base_wb_p (addr, 8, value, p); ++ return vstrwq_scatter_base_wb_p (addr, 0, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c +index 618dbaf5aa6..b6a9f6cd1f4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, const int offset, int32x4_t value) ++foo (uint32x4_t *addr, int32x4_t value) + { +- vstrwq_scatter_base_wb_s32 (addr, 8, value); ++ return vstrwq_scatter_base_wb_s32 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, const int offset, int32x4_t value) ++foo1 (uint32x4_t *addr, int32x4_t value) + { +- vstrwq_scatter_base_wb (addr, 8, value); ++ return vstrwq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c +index 912a4590cf5..81a278f4e2b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c +@@ -1,19 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo (uint32x4_t * addr, uint32x4_t value) ++foo (uint32x4_t *addr, uint32x4_t value) + { +- vstrwq_scatter_base_wb_u32 (addr, 8, value); ++ return vstrwq_scatter_base_wb_u32 (addr, 0, value); + } + ++ ++/* ++**foo1: ++** ... ++** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) ++** ... ++*/ + void +-foo1 (uint32x4_t * addr, uint32x4_t value) ++foo1 (uint32x4_t *addr, uint32x4_t value) + { +- vstrwq_scatter_base_wb (addr, 8, value); ++ return vstrwq_scatter_base_wb (addr, 0, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c +index c14d3ce607b..b81df68aa21 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * base, uint32x4_t offset, float32x4_t value) ++foo (float32_t *base, uint32x4_t offset, float32x4_t value) + { +- vstrwq_scatter_offset_f32 (base, offset, value); ++ return vstrwq_scatter_offset_f32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) ++foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) + { +- vstrwq_scatter_offset (base, offset, value); ++ return vstrwq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c +index 115be56ec00..8aee42f76a3 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) ++foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p_f32 (base, offset, value, p); ++ return vstrwq_scatter_offset_p_f32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) ++foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p (base, offset, value, p); ++ return vstrwq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c +index 48652af3cff..9c74ae7a8d8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p_s32 (base, offset, value, p); ++ return vstrwq_scatter_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p (base, offset, value, p); ++ return vstrwq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c +index dcd42ec453f..015a202b548 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p_u32 (base, offset, value, p); ++ return vstrwq_scatter_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_offset_p (base, offset, value, p); ++ return vstrwq_scatter_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c +index 04672e5a4aa..df373111b78 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * base, uint32x4_t offset, int32x4_t value) ++foo (int32_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrwq_scatter_offset_s32 (base, offset, value); ++ return vstrwq_scatter_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrwq_scatter_offset (base, offset, value); ++ return vstrwq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c +index e3d312550c6..a74696ca273 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrwq_scatter_offset_u32 (base, offset, value); ++ return vstrwq_scatter_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrwq_scatter_offset (base, offset, value); ++ return vstrwq_scatter_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c +index b20c4c7ed3a..1c9b29a57b8 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * base, uint32x4_t offset, float32x4_t value) ++foo (float32_t *base, uint32x4_t offset, float32x4_t value) + { +- vstrwq_scatter_shifted_offset_f32 (base, offset, value); ++ return vstrwq_scatter_shifted_offset_f32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) ++foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) + { +- vstrwq_scatter_shifted_offset (base, offset, value); ++ return vstrwq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c +index 1682f702dc6..08e1572854e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) ++foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) ++foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c +index eef6ea6e196..2b8f8a7d61f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) ++foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c +index b11e7e04dc4..3e4e87bf79a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c +@@ -1,21 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); + } + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) ++foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) + { +- vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++ return vstrwq_scatter_shifted_offset_p (base, offset, value, p); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrwt.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c +index 8ac25c47554..7f25490a69a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (int32_t * base, uint32x4_t offset, int32x4_t value) ++foo (int32_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrwq_scatter_shifted_offset_s32 (base, offset, value); ++ return vstrwq_scatter_shifted_offset_s32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) ++foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) + { +- vstrwq_scatter_shifted_offset (base, offset, value); ++ return vstrwq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c +index 1ce0ddacc7a..a96220c4f6e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) ++foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrwq_scatter_shifted_offset_u32 (base, offset, value); ++ return vstrwq_scatter_shifted_offset_u32 (base, offset, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) ++foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) + { +- vstrwq_scatter_shifted_offset (base, offset, value); ++ return vstrwq_scatter_shifted_offset (base, offset, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c +index 4aec9935b84..df554af79a6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo (uint32_t * addr, uint32x4_t value) ++foo (uint32_t *base, uint32x4_t value) + { +- vstrwq_u32 (addr, value); ++ return vstrwq_u32 (base, value); + } + +-/* { dg-final { scan-assembler "vstrw.32" } } */ + ++/* ++**foo1: ++** ... ++** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) ++** ... ++*/ + void +-foo1 (uint32_t * addr, uint32x4_t value) ++foo1 (uint32_t *base, uint32x4_t value) + { +- vstrwq (addr, value); ++ return vstrwq (base, value); ++} ++ ++#ifdef __cplusplus + } ++#endif + +-/* { dg-final { scan-assembler "vstrw.32" } } */ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c +index 8e3ce24fa49..5114f9f6e85 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b) + { + return vsubq_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.f16" } } */ + ++/* ++**foo1: ++** ... ++** vsub.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16x8_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c +index 5cb239d70fa..d0524ba6196 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b) + { + return vsubq_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.f32" } } */ + ++/* ++**foo1: ++** ... ++** vsub.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32x4_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c +index f4b3f806822..e8536dc51f9 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vsubq_m_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c +index 75dbf9335c9..eca850b63b5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vsubq_m_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c +deleted file mode 100644 +index f3e19613e7e..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) +-{ +- return vsubq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c +index 556a0845087..1753d6c8045 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) + { + return vsubq_m_n_f16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) ++{ ++ return vsubq_m (inactive, a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c +deleted file mode 100644 +index 4b5cd90c9ed..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vsubq_m (inactive, a, 23.23, p); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c +index e53f5f1966a..056810f4b06 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) + { + return vsubq_m_n_f32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) ++{ ++ return vsubq_m (inactive, a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c +index 73443d500ba..a55ed63d635 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vsubq_m_n_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c +index b4031111678..480fed3a112 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vsubq_m_n_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c +index 5c4e1019225..9aaa540a990 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c +@@ -1,23 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vsubq_m_n_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c +index 04a3036ede8..5d033129356 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vsubq_m_n_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) ++{ ++ return vsubq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c +index a21f9366373..3f9494005cb 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vsubq_m_n_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) ++{ ++ return vsubq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c +index 18f635f1e1a..c6ee8887e62 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c +@@ -1,23 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vsubq_m_n_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) ++{ ++ return vsubq_m (inactive, a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c +index 598d648887b..cfd43b07258 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vsubq_m_s16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c +index af6750278f1..6c382ba6f45 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vsubq_m_s32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c +index 5effbe2e017..0408dd0e2c4 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vsubq_m_s8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c +index 12218ae6791..9d860e9b224 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vsubq_m_u16 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c +index 3a63eeb2b3d..c409b0a9d58 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vsubq_m_u32 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c +index a17a2741a47..7d568c17173 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c +@@ -1,22 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vsubq_m_u8 (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { + return vsubq_m (inactive, a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c +deleted file mode 100644 +index f8832546f54..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float16x8_t +-foo1 (float16x8_t a, float16_t b) +-{ +- return vsubq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c +index 10e27dae907..3c31189e52e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16_t b) + { + return vsubq_n_f16 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.f16" } } */ + ++/* ++**foo1: ++** ... ++** vsub.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo1 (float16x8_t a, float16_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.f16" } } */ ++/* ++**foo2: ++** ... ++** vsub.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t a) ++{ ++ return vsubq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c +deleted file mode 100644 +index 88d9675540d..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo1 (float32x4_t a, float32_t b) +-{ +- return vsubq (a, 23.23); +-} +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c +index 9e16d6c075c..041266b3b7d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c +@@ -1,21 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32_t b) + { + return vsubq_n_f32 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.f32" } } */ + ++/* ++**foo1: ++** ... ++** vsub.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo1 (float32x4_t a, float32_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.f32" } } */ ++/* ++**foo2: ++** ... ++** vsub.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t a) ++{ ++ return vsubq (a, 1.1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c +index 7f2af8691c0..78a2b911c97 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ +-/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b) + { + return vsubq_n_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i16" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c +index a5e6bf486fd..98ab34e89d5 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ +-/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b) + { + return vsubq_n_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i32" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c +index 5754379358d..07173eaa1ec 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c +@@ -1,22 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ +-/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b) + { + return vsubq_n_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i8" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c +index ea0a3f9260c..f0744f5c501 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ +-/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b) + { + return vsubq_n_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i16" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i16" } } */ ++/* ++**foo2: ++** ... ++** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a) ++{ ++ return vsubq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c +index cc409b59438..600d6290cde 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ +-/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b) + { + return vsubq_n_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i32" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i32" } } */ ++/* ++**foo2: ++** ... ++** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a) ++{ ++ return vsubq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c +index 8a18a89b353..34d4725b27b 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c +@@ -1,22 +1,53 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ +-/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b) + { + return vsubq_n_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i8" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i8" } } */ ++/* ++**foo2: ++** ... ++** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a) ++{ ++ return vsubq (a, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c +index 15e732f1f66..80213e828e6 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b) + { + return vsubq_s16 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i16" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo1 (int16x8_t a, int16x8_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c +index 5b4ee855711..262ec5ce5c7 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b) + { + return vsubq_s32 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i32" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo1 (int32x4_t a, int32x4_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c +index b23893af605..9a2d55f1307 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b) + { + return vsubq_s8 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i8" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo1 (int8x16_t a, int8x16_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c +index edb5e354411..62a5942396d 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b) + { + return vsubq_u16 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i16" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo1 (uint16x8_t a, uint16x8_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i16" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c +index 68040afd52b..3c824b0fb75 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b) + { + return vsubq_u32 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i32" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo1 (uint32x4_t a, uint32x4_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i32" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c +index 92c4f059b0e..c9c7f6ca085 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c +@@ -1,21 +1,41 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b) + { + return vsubq_u8 (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i8" } } */ + ++/* ++**foo1: ++** ... ++** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo1 (uint8x16_t a, uint8x16_t b) + { + return vsubq (a, b); + } + +-/* { dg-final { scan-assembler "vsub.i8" } } */ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c +index 4cb8be0ea7f..cb233e9897c 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16x8_t b, mve_pred16_t p) + { +- return vsubq_x_f16 (a, b, p); ++ return vsubq_x_f16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c +index f6711d7f207..227e9349206 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32x4_t b, mve_pred16_t p) + { +- return vsubq_x_f32 (a, b, p); ++ return vsubq_x_f32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c +index c4adacbf5be..14574d5074e 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c +@@ -1,15 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float16x8_t + foo (float16x8_t a, float16_t b, mve_pred16_t p) + { +- return vsubq_x_n_f16 (a, b, p); ++ return vsubq_x_n_f16 (a, b, p); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo1 (float16x8_t a, float16_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float16x8_t ++foo2 (float16x8_t a, mve_pred16_t p) ++{ ++ return vsubq_x (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c +deleted file mode 100644 +index dcb2425397b..00000000000 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +-/* { dg-add-options arm_v8_1m_mve_fp } */ +-/* { dg-additional-options "-O2" } */ +- +-#include "arm_mve.h" +-float32x4_t +-foo (float32x4_t a, float32_t b, mve_pred16_t p) +-{ +- return vsubq_x_n_f32 (a, 23.23, p); +-} +- +- +-/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c +index a4affa0a3a9..864f6fee264 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c +@@ -1,15 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ + /* { dg-add-options arm_v8_1m_mve_fp } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + float32x4_t + foo (float32x4_t a, float32_t b, mve_pred16_t p) + { +- return vsubq_x_n_f32 (a, b, p); ++ return vsubq_x_n_f32 (a, b, p); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo1 (float32x4_t a, float32_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.f32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++float32x4_t ++foo2 (float32x4_t a, mve_pred16_t p) ++{ ++ return vsubq_x (a, 1.1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c +index 99c59b1a6c1..ee9e7bcb45f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16_t b, mve_pred16_t p) + { +- return vsubq_x_n_s16 (a, b, p); ++ return vsubq_x_n_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a, int16_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c +index 6c29ebec05c..551f46c92ff 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32_t b, mve_pred16_t p) + { +- return vsubq_x_n_s32 (a, b, p); ++ return vsubq_x_n_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a, int32_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c +index 0f83c305473..04a9d7285c0 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8_t b, mve_pred16_t p) + { +- return vsubq_x_n_s8 (a, b, p); ++ return vsubq_x_n_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++int8x16_t ++foo1 (int8x16_t a, int8_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c +index 9a372d762d1..a07d4955224 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c +@@ -1,15 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16_t b, mve_pred16_t p) + { +- return vsubq_x_n_u16 (a, b, p); ++ return vsubq_x_n_u16 (a, b, p); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo2 (uint16x8_t a, mve_pred16_t p) ++{ ++ return vsubq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c +index 5219f154fa9..1055769ee1f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c +@@ -1,15 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32_t b, mve_pred16_t p) + { +- return vsubq_x_n_u32 (a, b, p); ++ return vsubq_x_n_u32 (a, b, p); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo2 (uint32x4_t a, mve_pred16_t p) ++{ ++ return vsubq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c +index 0a0bcf8623a..a67d303107a 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c +@@ -1,15 +1,65 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8_t b, mve_pred16_t p) + { +- return vsubq_x_n_u8 (a, b, p); ++ return vsubq_x_n_u8 (a, b, p); ++} ++ ++ ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ ++/* ++**foo2: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo2 (uint8x16_t a, mve_pred16_t p) ++{ ++ return vsubq_x (a, 1, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif + ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c +index 37936a6d647..9bf363275cc 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int16x8_t + foo (int16x8_t a, int16x8_t b, mve_pred16_t p) + { +- return vsubq_x_s16 (a, b, p); ++ return vsubq_x_s16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++int16x8_t ++foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c +index c085f59c6a2..19707f684ba 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int32x4_t + foo (int32x4_t a, int32x4_t b, mve_pred16_t p) + { +- return vsubq_x_s32 (a, b, p); ++ return vsubq_x_s32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++int32x4_t ++foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c +index 361507821ea..ef4d831a117 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + int8x16_t + foo (int8x16_t a, int8x16_t b, mve_pred16_t p) + { +- return vsubq_x_s8 (a, b, p); ++ return vsubq_x_s8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++int8x16_t ++foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c +index 21423dc4f80..6c3d6697c92 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint16x8_t + foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) + { +- return vsubq_x_u16 (a, b, p); ++ return vsubq_x_u16 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i16" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint16x8_t ++foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c +index 38dd09ad8f7..97f9f744f2f 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint32x4_t + foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) + { +- return vsubq_x_u32 (a, b, p); ++ return vsubq_x_u32 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i32" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint32x4_t ++foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c +index 406cbf760fd..75e75e5d028 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c ++++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c +@@ -1,15 +1,49 @@ + /* { dg-require-effective-target arm_v8_1m_mve_ok } */ + /* { dg-add-options arm_v8_1m_mve } */ + /* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ + + #include "arm_mve.h" + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ + uint8x16_t + foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) + { +- return vsubq_x_u8 (a, b, p); ++ return vsubq_x_u8 (a, b, p); + } + +-/* { dg-final { scan-assembler "vpst" } } */ +-/* { dg-final { scan-assembler "vsubt.i8" } } */ + ++/* ++**foo1: ++** ... ++** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) ++** ... ++** vpst(?: @.*|) ++** ... ++** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) ++** ... ++*/ ++uint8x16_t ++foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) ++{ ++ return vsubq_x (a, b, p); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c +new file mode 100644 +index 00000000000..b17f9f36057 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c +@@ -0,0 +1,41 @@ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-additional-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++#include "arm_mve.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++**foo11: ++** ... ++** movs r0, #2 ++** ... ++*/ ++uint32_t ++foo11 () ++{ ++ return uqshl (1, 1); ++} ++ ++/* ++**foo12: ++** ... ++** movs r0, #2 ++** movs r1, #0 ++** ... ++*/ ++uint64_t ++foo12 () ++{ ++ return uqshll (1, 1); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c b/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c +index e35eb1108aa..816980d1203 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c ++++ b/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c +@@ -7,7 +7,7 @@ + /* + **off_load8_0: + ** ... +-** vldrb.8 q0, \[r0, #16\] ++** vldrb.8 q[0-7], \[r0, #16\] + ** ... + */ + int8x16_t off_load8_0 (int8_t * a) +@@ -18,7 +18,7 @@ int8x16_t off_load8_0 (int8_t * a) + /* + **off_load8_1: + ** ... +-** vldrb.u16 q0, \[r0, #1\] ++** vldrb.u16 q[0-7], \[r0, #1\] + ** ... + */ + uint16x8_t off_load8_1 (uint8_t * a) +@@ -29,7 +29,7 @@ uint16x8_t off_load8_1 (uint8_t * a) + /* + **off_load8_2: + ** ... +-** vldrb.s32 q0, \[r0, #127\] ++** vldrb.s32 q[0-7], \[r0, #127\] + ** ... + */ + int32x4_t off_load8_2 (int8_t * a) +@@ -40,7 +40,7 @@ int32x4_t off_load8_2 (int8_t * a) + /* + **off_load8_3: + ** ... +-** vldrb.8 q0, \[r0, #-127\] ++** vldrb.8 q[0-7], \[r0, #-127\] + ** ... + */ + uint8x16_t off_load8_3 (uint8_t * a) +@@ -51,7 +51,7 @@ uint8x16_t off_load8_3 (uint8_t * a) + /* + **not_off_load8_0: + ** ... +-** vldrb.8 q0, \[r[0-9]+\] ++** vldrb.8 q[0-7], \[r[0-7]+\] + ** ... + */ + int8x16_t not_off_load8_0 (int8_t * a) +@@ -62,7 +62,7 @@ int8x16_t not_off_load8_0 (int8_t * a) + /* + **off_loadfp16_0: + ** ... +-** vldrh.16 q0, \[r0, #-244\] ++** vldrh.16 q[0-7], \[r0, #-244\] + ** ... + */ + float16x8_t off_loadfp16_0 (float16_t *a) +@@ -73,7 +73,7 @@ float16x8_t off_loadfp16_0 (float16_t *a) + /* + **off_load16_0: + ** ... +-** vldrh.16 q0, \[r0, #-2\] ++** vldrh.16 q[0-7], \[r0, #-2\] + ** ... + */ + uint16x8_t off_load16_0 (uint16_t * a) +@@ -84,7 +84,7 @@ uint16x8_t off_load16_0 (uint16_t * a) + /* + **off_load16_1: + ** ... +-** vldrh.u32 q0, \[r0, #254\] ++** vldrh.u32 q[0-7], \[r0, #254\] + ** ... + */ + uint32x4_t off_load16_1 (uint16_t * a) +@@ -95,7 +95,7 @@ uint32x4_t off_load16_1 (uint16_t * a) + /* + **not_off_load16_0: + ** ... +-** vldrh.16 q0, \[r[0-9]+\] ++** vldrh.16 q[0-7], \[r[0-7]+\] + ** ... + */ + int16x8_t not_off_load16_0 (int8_t * a) +@@ -106,7 +106,7 @@ int16x8_t not_off_load16_0 (int8_t * a) + /* + **not_off_load16_1: + ** ... +-** vldrh.u32 q0, \[r[0-9]+\] ++** vldrh.u32 q[0-7], \[r[0-7]+\] + ** ... + */ + uint32x4_t not_off_load16_1 (uint16_t * a) +@@ -117,7 +117,7 @@ uint32x4_t not_off_load16_1 (uint16_t * a) + /* + **off_loadfp32_0: + ** ... +-** vldrw.32 q0, \[r0, #24\] ++** vldrw.32 q[0-7], \[r0, #24\] + ** ... + */ + float32x4_t off_loadfp32_0 (float32_t *a) +@@ -128,7 +128,7 @@ float32x4_t off_loadfp32_0 (float32_t *a) + /* + **off_load32_0: + ** ... +-** vldrw.32 q0, \[r0, #4\] ++** vldrw.32 q[0-7], \[r0, #4\] + ** ... + */ + uint32x4_t off_load32_0 (uint32_t * a) +@@ -139,7 +139,7 @@ uint32x4_t off_load32_0 (uint32_t * a) + /* + **off_load32_1: + ** ... +-** vldrw.32 q0, \[r0, #-508\] ++** vldrw.32 q[0-7], \[r0, #-508\] + ** ... + */ + int32x4_t off_load32_1 (int32_t * a) +@@ -149,7 +149,7 @@ int32x4_t off_load32_1 (int32_t * a) + /* + **pre_load8_0: + ** ... +-** vldrb.8 q[0-9]+, \[r0, #16\]! ++** vldrb.8 q[0-7], \[r0, #16\]! + ** ... + */ + int8_t* pre_load8_0 (int8_t * a, int8x16_t *v) +@@ -162,7 +162,7 @@ int8_t* pre_load8_0 (int8_t * a, int8x16_t *v) + /* + **pre_load8_1: + ** ... +-** vldrb.u16 q[0-9]+, \[r0, #4\]! ++** vldrb.u16 q[0-7], \[r0, #4\]! + ** ... + */ + uint8_t* pre_load8_1 (uint8_t * a, uint16x8_t *v) +@@ -175,7 +175,7 @@ uint8_t* pre_load8_1 (uint8_t * a, uint16x8_t *v) + /* + **pre_loadfp16_0: + ** ... +-** vldrh.16 q[0-9]+, \[r0, #128\]! ++** vldrh.16 q[0-7], \[r0, #128\]! + ** ... + */ + float16_t* pre_loadfp16_0 (float16_t *a, float16x8_t *v) +@@ -188,7 +188,7 @@ float16_t* pre_loadfp16_0 (float16_t *a, float16x8_t *v) + /* + **pre_load16_0: + ** ... +-** vldrh.16 q[0-9]+, \[r0, #-254\]! ++** vldrh.16 q[0-7], \[r0, #-254\]! + ** ... + */ + int16_t* pre_load16_0 (int16_t * a, int16x8_t *v) +@@ -201,7 +201,7 @@ int16_t* pre_load16_0 (int16_t * a, int16x8_t *v) + /* + **pre_load16_1: + ** ... +-** vldrh.s32 q[0-9]+, \[r0, #52\]! ++** vldrh.s32 q[0-7], \[r0, #52\]! + ** ... + */ + int16_t* pre_load16_1 (int16_t * a, int32x4_t *v) +@@ -214,7 +214,7 @@ int16_t* pre_load16_1 (int16_t * a, int32x4_t *v) + /* + **pre_loadfp32_0: + ** ... +-** vldrw.32 q[0-9]+, \[r0, #-72\]! ++** vldrw.32 q[0-7], \[r0, #-72\]! + ** ... + */ + float32_t* pre_loadfp32_0 (float32_t *a, float32x4_t *v) +@@ -228,7 +228,7 @@ float32_t* pre_loadfp32_0 (float32_t *a, float32x4_t *v) + /* + **pre_load32_0: + ** ... +-** vldrw.32 q[0-9]+, \[r0, #-4\]! ++** vldrw.32 q[0-7], \[r0, #-4\]! + ** ... + */ + uint32_t* pre_load32_0 (uint32_t * a, uint32x4_t *v) +@@ -242,7 +242,7 @@ uint32_t* pre_load32_0 (uint32_t * a, uint32x4_t *v) + /* + **post_load8_0: + ** ... +-** vldrb.8 q[0-9]+, \[r0\], #26 ++** vldrb.8 q[0-7], \[r0\], #26 + ** ... + */ + uint8_t* post_load8_0 (uint8_t * a, uint8x16_t *v) +@@ -255,7 +255,7 @@ uint8_t* post_load8_0 (uint8_t * a, uint8x16_t *v) + /* + **post_load8_1: + ** ... +-** vldrb.s16 q[0-9]+, \[r0\], #-1 ++** vldrb.s16 q[0-7], \[r0\], #-1 + ** ... + */ + int8_t* post_load8_1 (int8_t * a, int16x8_t *v) +@@ -268,7 +268,7 @@ int8_t* post_load8_1 (int8_t * a, int16x8_t *v) + /* + **post_load8_2: + ** ... +-** vldrb.8 q[0-9]+, \[r0\], #26 ++** vldrb.8 q[0-7], \[r0\], #26 + ** ... + */ + uint8_t* post_load8_2 (uint8_t * a, uint8x16_t *v) +@@ -281,7 +281,7 @@ uint8_t* post_load8_2 (uint8_t * a, uint8x16_t *v) + /* + **post_load8_3: + ** ... +-** vldrb.s16 q[0-9]+, \[r0\], #-1 ++** vldrb.s16 q[0-7], \[r0\], #-1 + ** ... + */ + int8_t* post_load8_3 (int8_t * a, int16x8_t *v) +@@ -294,7 +294,7 @@ int8_t* post_load8_3 (int8_t * a, int16x8_t *v) + /* + **post_loadfp16_0: + ** ... +-** vldrh.16 q[0-9]+, \[r0\], #-24 ++** vldrh.16 q[0-7], \[r0\], #-24 + ** ... + */ + float16_t* post_loadfp16_0 (float16_t *a, float16x8_t *v) +@@ -307,7 +307,7 @@ float16_t* post_loadfp16_0 (float16_t *a, float16x8_t *v) + /* + **post_load16_0: + ** ... +-** vldrh.16 q[0-9]+, \[r0\], #-126 ++** vldrh.16 q[0-7], \[r0\], #-126 + ** ... + */ + uint16_t* post_load16_0 (uint16_t * a, uint16x8_t *v) +@@ -320,7 +320,7 @@ uint16_t* post_load16_0 (uint16_t * a, uint16x8_t *v) + /* + **post_load16_1: + ** ... +-** vldrh.u32 q[0-9]+, \[r0\], #16 ++** vldrh.u32 q[0-7], \[r0\], #16 + ** ... + */ + uint16_t* post_load16_1 (uint16_t * a, uint32x4_t *v) +@@ -333,7 +333,7 @@ uint16_t* post_load16_1 (uint16_t * a, uint32x4_t *v) + /* + **post_loadfp32_0: + ** ... +-** vldrw.32 q[0-9]+, \[r0\], #4 ++** vldrw.32 q[0-7], \[r0\], #4 + ** ... + */ + float32_t* post_loadfp32_0 (float32_t *a, float32x4_t *v) +@@ -346,7 +346,7 @@ float32_t* post_loadfp32_0 (float32_t *a, float32x4_t *v) + /* + **post_load32_0: + ** ... +-** vldrw.32 q[0-9]+, \[r0\], #-16 ++** vldrw.32 q[0-7], \[r0\], #-16 + ** ... + */ + int32_t* post_load32_0 (int32_t * a, int32x4_t *v) +diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c b/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c +index 632f5b44f0b..11df1144064 100644 +--- a/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c ++++ b/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c +@@ -7,7 +7,7 @@ + /* + **off_store8_0: + ** ... +-** vstrb.8 q0, \[r0, #16\] ++** vstrb.8 q[0-7], \[r0, #16\] + ** ... + */ + uint8_t *off_store8_0 (uint8_t * a, uint8x16_t v) +@@ -19,7 +19,7 @@ uint8_t *off_store8_0 (uint8_t * a, uint8x16_t v) + /* + **off_store8_1: + ** ... +-** vstrb.16 q0, \[r0, #-1\] ++** vstrb.16 q[0-7], \[r0, #-1\] + ** ... + */ + int8_t *off_store8_1 (int8_t * a, int16x8_t v) +@@ -31,7 +31,7 @@ int8_t *off_store8_1 (int8_t * a, int16x8_t v) + /* + **off_store8_2: + ** ... +-** vstrb.32 q0, \[r0, #-127\] ++** vstrb.32 q[0-7], \[r0, #-127\] + ** ... + */ + uint8_t *off_store8_2 (uint8_t * a, uint32x4_t v) +@@ -43,7 +43,7 @@ uint8_t *off_store8_2 (uint8_t * a, uint32x4_t v) + /* + **off_store8_3: + ** ... +-** vstrb.8 q0, \[r0, #127\] ++** vstrb.8 q[0-7], \[r0, #127\] + ** ... + */ + int8_t *off_store8_3 (int8_t * a, int8x16_t v) +@@ -55,7 +55,7 @@ int8_t *off_store8_3 (int8_t * a, int8x16_t v) + /* + **not_off_store8_0: + ** ... +-** vstrb.8 q0, \[r[0-9]+\] ++** vstrb.8 q[0-7], \[r[0-7]+\] + ** ... + */ + uint8_t *not_off_store8_0 (uint8_t * a, uint8x16_t v) +@@ -67,7 +67,7 @@ uint8_t *not_off_store8_0 (uint8_t * a, uint8x16_t v) + /* + **off_storefp16_0: + ** ... +-** vstrh.16 q0, \[r0, #250\] ++** vstrh.16 q[0-7], \[r0, #250\] + ** ... + */ + float16_t *off_storefp16_0 (float16_t *a, float16x8_t v) +@@ -79,7 +79,7 @@ float16_t *off_storefp16_0 (float16_t *a, float16x8_t v) + /* + **off_store16_0: + ** ... +-** vstrh.16 q0, \[r0, #4\] ++** vstrh.16 q[0-7], \[r0, #4\] + ** ... + */ + int16_t *off_store16_0 (int16_t * a, int16x8_t v) +@@ -91,7 +91,7 @@ int16_t *off_store16_0 (int16_t * a, int16x8_t v) + /* + **off_store16_1: + ** ... +-** vstrh.32 q0, \[r0, #-254\] ++** vstrh.32 q[0-7], \[r0, #-254\] + ** ... + */ + int16_t *off_store16_1 (int16_t * a, int32x4_t v) +@@ -103,7 +103,7 @@ int16_t *off_store16_1 (int16_t * a, int32x4_t v) + /* + **not_off_store16_0: + ** ... +-** vstrh.16 q0, \[r[0-9]+\] ++** vstrh.16 q[0-7], \[r[0-7]+\] + ** ... + */ + uint8_t *not_off_store16_0 (uint8_t * a, uint16x8_t v) +@@ -115,7 +115,7 @@ uint8_t *not_off_store16_0 (uint8_t * a, uint16x8_t v) + /* + **not_off_store16_1: + ** ... +-** vstrh.32 q0, \[r[0-9]+\] ++** vstrh.32 q[0-7], \[r[0-7]+\] + ** ... + */ + int16_t *not_off_store16_1 (int16_t * a, int32x4_t v) +@@ -127,7 +127,7 @@ int16_t *not_off_store16_1 (int16_t * a, int32x4_t v) + /* + **off_storefp32_0: + ** ... +-** vstrw.32 q0, \[r0, #-412\] ++** vstrw.32 q[0-7], \[r0, #-412\] + ** ... + */ + float32_t *off_storefp32_0 (float32_t *a, float32x4_t v) +@@ -139,7 +139,7 @@ float32_t *off_storefp32_0 (float32_t *a, float32x4_t v) + /* + **off_store32_0: + ** ... +-** vstrw.32 q0, \[r0, #-4\] ++** vstrw.32 q[0-7], \[r0, #-4\] + ** ... + */ + int32_t *off_store32_0 (int32_t * a, int32x4_t v) +@@ -151,7 +151,7 @@ int32_t *off_store32_0 (int32_t * a, int32x4_t v) + /* + **off_store32_1: + ** ... +-** vstrw.32 q0, \[r0, #508\] ++** vstrw.32 q[0-7], \[r0, #508\] + ** ... + */ + uint32_t *off_store32_1 (uint32_t * a, uint32x4_t v) +@@ -163,7 +163,7 @@ uint32_t *off_store32_1 (uint32_t * a, uint32x4_t v) + /* + **pre_store8_0: + ** ... +-** vstrb.8 q[0-9]+, \[r0, #-16\]! ++** vstrb.8 q[0-7], \[r0, #-16\]! + ** ... + */ + uint8_t* pre_store8_0 (uint8_t * a, uint8x16_t v) +@@ -176,7 +176,7 @@ uint8_t* pre_store8_0 (uint8_t * a, uint8x16_t v) + /* + **pre_store8_1: + ** ... +-** vstrb.16 q[0-9]+, \[r0, #4\]! ++** vstrb.16 q[0-7], \[r0, #4\]! + ** ... + */ + int8_t* pre_store8_1 (int8_t * a, int16x8_t v) +@@ -189,7 +189,7 @@ int8_t* pre_store8_1 (int8_t * a, int16x8_t v) + /* + **pre_storefp16_0: + ** ... +-** vstrh.16 q0, \[r0, #8\]! ++** vstrh.16 q[0-7], \[r0, #8\]! + ** ... + */ + float16_t *pre_storefp16_0 (float16_t *a, float16x8_t v) +@@ -202,7 +202,7 @@ float16_t *pre_storefp16_0 (float16_t *a, float16x8_t v) + /* + **pre_store16_0: + ** ... +-** vstrh.16 q[0-9]+, \[r0, #254\]! ++** vstrh.16 q[0-7], \[r0, #254\]! + ** ... + */ + uint16_t* pre_store16_0 (uint16_t * a, uint16x8_t v) +@@ -215,7 +215,7 @@ uint16_t* pre_store16_0 (uint16_t * a, uint16x8_t v) + /* + **pre_store16_1: + ** ... +-** vstrh.32 q[0-9]+, \[r0, #-52\]! ++** vstrh.32 q[0-7], \[r0, #-52\]! + ** ... + */ + int16_t* pre_store16_1 (int16_t * a, int32x4_t v) +@@ -228,7 +228,7 @@ int16_t* pre_store16_1 (int16_t * a, int32x4_t v) + /* + **pre_storefp32_0: + ** ... +-** vstrw.32 q0, \[r0, #-4\]! ++** vstrw.32 q[0-7], \[r0, #-4\]! + ** ... + */ + float32_t *pre_storefp32_0 (float32_t *a, float32x4_t v) +@@ -241,7 +241,7 @@ float32_t *pre_storefp32_0 (float32_t *a, float32x4_t v) + /* + **pre_store32_0: + ** ... +-** vstrw.32 q[0-9]+, \[r0, #4\]! ++** vstrw.32 q[0-7], \[r0, #4\]! + ** ... + */ + int32_t* pre_store32_0 (int32_t * a, int32x4_t v) +@@ -255,7 +255,7 @@ int32_t* pre_store32_0 (int32_t * a, int32x4_t v) + /* + **post_store8_0: + ** ... +-** vstrb.8 q[0-9]+, \[r0\], #-26 ++** vstrb.8 q[0-7], \[r0\], #-26 + ** ... + */ + int8_t* post_store8_0 (int8_t * a, int8x16_t v) +@@ -268,7 +268,7 @@ int8_t* post_store8_0 (int8_t * a, int8x16_t v) + /* + **post_store8_1: + ** ... +-** vstrb.16 q[0-9]+, \[r0\], #1 ++** vstrb.16 q[0-7], \[r0\], #1 + ** ... + */ + uint8_t* post_store8_1 (uint8_t * a, uint16x8_t v) +@@ -281,7 +281,7 @@ uint8_t* post_store8_1 (uint8_t * a, uint16x8_t v) + /* + **post_store8_2: + ** ... +-** vstrb.8 q[0-9]+, \[r0\], #-26 ++** vstrb.8 q[0-7], \[r0\], #-26 + ** ... + */ + int8_t* post_store8_2 (int8_t * a, int8x16_t v) +@@ -294,7 +294,7 @@ int8_t* post_store8_2 (int8_t * a, int8x16_t v) + /* + **post_store8_3: + ** ... +-** vstrb.16 q[0-9]+, \[r0\], #7 ++** vstrb.16 q[0-7], \[r0\], #7 + ** ... + */ + uint8_t* post_store8_3 (uint8_t * a, uint16x8_t v) +@@ -307,7 +307,7 @@ uint8_t* post_store8_3 (uint8_t * a, uint16x8_t v) + /* + **post_storefp16_0: + ** ... +-** vstrh.16 q[0-9]+, \[r0\], #-16 ++** vstrh.16 q[0-7], \[r0\], #-16 + ** ... + */ + float16_t *post_storefp16_0 (float16_t *a, float16x8_t v) +@@ -320,7 +320,7 @@ float16_t *post_storefp16_0 (float16_t *a, float16x8_t v) + /* + **post_store16_0: + ** ... +-** vstrh.16 q[0-9]+, \[r0\], #126 ++** vstrh.16 q[0-7], \[r0\], #126 + ** ... + */ + int16_t* post_store16_0 (int16_t * a, int16x8_t v) +@@ -333,7 +333,7 @@ int16_t* post_store16_0 (int16_t * a, int16x8_t v) + /* + **post_store16_1: + ** ... +-** vstrh.32 q[0-9]+, \[r0\], #-16 ++** vstrh.32 q[0-7], \[r0\], #-16 + ** ... + */ + uint16_t* post_store16_1 (uint16_t * a, uint32x4_t v) +@@ -346,7 +346,7 @@ uint16_t* post_store16_1 (uint16_t * a, uint32x4_t v) + /* + **post_storefp32_0: + ** ... +-** vstrw.32 q[0-9]+, \[r0\], #-16 ++** vstrw.32 q[0-7], \[r0\], #-16 + ** ... + */ + float32_t* post_storefp32_0 (float32_t * a, float32x4_t v) +@@ -359,7 +359,7 @@ float32_t* post_storefp32_0 (float32_t * a, float32x4_t v) + /* + **post_store32_0: + ** ... +-** vstrw.32 q[0-9]+, \[r0\], #16 ++** vstrw.32 q[0-7], \[r0\], #16 + ** ... + */ + int32_t* post_store32_0 (int32_t * a, int32x4_t v) +diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c +new file mode 100644 +index 00000000000..a8c6cce67c8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c +@@ -0,0 +1,67 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include ++ ++volatile int32x4_t c1; ++volatile uint32x4_t c2; ++int *carry; ++ ++int ++main () ++{ ++ int32x4_t a1 = vcreateq_s32 (0, 0); ++ int32x4_t b1 = vcreateq_s32 (0, 0); ++ int32x4_t inactive1 = vcreateq_s32 (0, 0); ++ ++ uint32x4_t a2 = vcreateq_u32 (0, 0); ++ uint32x4_t b2 = vcreateq_u32 (0, 0); ++ uint32x4_t inactive2 = vcreateq_u32 (0, 0); ++ ++ mve_pred16_t p = 0xFFFF; ++ (*carry) = 0xFFFFFFFF; ++ ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c1 = vadcq (a1, b1, carry); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c2 = vadcq (a2, b2, carry); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c1 = vsbcq (a1, b1, carry); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c2 = vsbcq (a2, b2, carry); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c1 = vadcq_m (inactive1, a1, b1, carry, p); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c2 = vadcq_m (inactive2, a2, b2, carry, p); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c1 = vsbcq_m (inactive1, a1, b1, carry, p); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ (*carry) = 0xFFFFFFFF; ++ __builtin_arm_set_fpscr_nzcvqc (0); ++ c2 = vsbcq_m (inactive2, a2, b2, carry, p); ++ if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000) ++ __builtin_abort (); ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c +new file mode 100644 +index 00000000000..ca092df9802 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2 --save-temps" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-1.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c +new file mode 100644 +index 00000000000..8383b4d9e3a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE uint8x16_t ++#define INTRINSIC vstrbq_u8 ++#define INTRINSIC_P vstrbq_p_u8 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c +new file mode 100644 +index 00000000000..0a58b8f7fdf +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-10.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c +new file mode 100644 +index 00000000000..7b1cd3711d8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE int32x4_t ++#define INTRINSIC vstrhq_s32 ++#define INTRINSIC_P vstrhq_p_s32 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c +new file mode 100644 +index 00000000000..9f568eacf34 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-11.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c +new file mode 100644 +index 00000000000..e6ae8524052 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE uint32x4_t ++#define INTRINSIC vstrwq_u32 ++#define INTRINSIC_P vstrwq_p_u32 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c +new file mode 100644 +index 00000000000..8e946a29795 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-12.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c +new file mode 100644 +index 00000000000..e352508e07e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE int32x4_t ++#define INTRINSIC vstrwq_s32 ++#define INTRINSIC_P vstrwq_p_s32 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c +new file mode 100644 +index 00000000000..34a5e7d35e7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve_fp } */ ++ ++#include "pr108177-13.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c +new file mode 100644 +index 00000000000..13afa92771d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE float16x8_t ++#define INTRINSIC vstrhq_f16 ++#define INTRINSIC_P vstrhq_p_f16 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c +new file mode 100644 +index 00000000000..a2dc3338dd3 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve_fp } */ ++ ++#include "pr108177-14.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c +new file mode 100644 +index 00000000000..a093cd4b708 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve_fp } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE float32x4_t ++#define INTRINSIC vstrwq_f32 ++#define INTRINSIC_P vstrwq_p_f32 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c +new file mode 100644 +index 00000000000..03750c9c7a1 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-2.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c +new file mode 100644 +index 00000000000..da4181ff0b7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE int8x16_t ++#define INTRINSIC vstrbq_s8 ++#define INTRINSIC_P vstrbq_p_s8 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c +new file mode 100644 +index 00000000000..bab08e042d4 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-3.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c +new file mode 100644 +index 00000000000..9604fd100e6 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE uint16x8_t ++#define INTRINSIC vstrbq_u16 ++#define INTRINSIC_P vstrbq_p_u16 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c +new file mode 100644 +index 00000000000..cff62c75dd5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-4.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c +new file mode 100644 +index 00000000000..07ba37b466c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE int16x8_t ++#define INTRINSIC vstrbq_s16 ++#define INTRINSIC_P vstrbq_p_s16 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c +new file mode 100644 +index 00000000000..7211828ceeb +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-5.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c +new file mode 100644 +index 00000000000..72c1dd5a4d6 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE uint32x4_t ++#define INTRINSIC vstrbq_u32 ++#define INTRINSIC_P vstrbq_p_u32 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c +new file mode 100644 +index 00000000000..4e7d108cd81 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-6.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c +new file mode 100644 +index 00000000000..3fedc9b98c8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE int32x4_t ++#define INTRINSIC vstrbq_s32 ++#define INTRINSIC_P vstrbq_p_s32 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c +new file mode 100644 +index 00000000000..94c492ed96b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-7.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c +new file mode 100644 +index 00000000000..c3b440c3b6c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE uint16x8_t ++#define INTRINSIC vstrhq_u16 ++#define INTRINSIC_P vstrhq_p_u16 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c +new file mode 100644 +index 00000000000..3c34045f31d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-8.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c +new file mode 100644 +index 00000000000..5c450b81d1c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE int16x8_t ++#define INTRINSIC vstrhq_s16 ++#define INTRINSIC_P vstrhq_p_s16 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c +new file mode 100644 +index 00000000000..967cf7f1992 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c +@@ -0,0 +1,6 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_mve_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++ ++#include "pr108177-9.c" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c +new file mode 100644 +index 00000000000..b5084efcc00 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_1m_mve_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_1m_mve } */ ++/* { dg-final { check-function-bodies "**" "" "" } } */ ++ ++/* ++** test: ++**... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\] ++**... ++*/ ++ ++#define TYPE uint32x4_t ++#define INTRINSIC vstrhq_u32 ++#define INTRINSIC_P vstrhq_p_u32 ++ ++#include "pr108177.x" +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x +new file mode 100644 +index 00000000000..f5f965fb698 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x +@@ -0,0 +1,31 @@ ++#include ++extern void abort (void); ++ ++__attribute__ ((noipa)) void ++write_expected (uint32x4_t v, void *a) ++{ ++ TYPE _v = (TYPE) v; ++ INTRINSIC (a, _v); ++} ++ ++void test (uint32x4_t, void *, mve_pred16_t, mve_pred16_t); ++ ++int main(void) ++{ ++ uint32x4_t v = {0, 1, 2, 3}; ++ uint32_t actual[] = {0, 0, 0, 0}; ++ uint32_t expected[] = {0, 0, 0, 0}; ++ ++ write_expected (v, &(expected[0])); ++ ++ mve_pred16_t p1 = 0xff00; ++ mve_pred16_t p2 = 0x00ff; ++ ++ test (v, (void *)&actual[0], p1, p2); ++ ++ if (__builtin_memcmp (&actual[0], &expected[0], 16) != 0) ++ abort (); ++ ++ return 0; ++} ++ +diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177.x b/gcc/testsuite/gcc.target/arm/mve/pr108177.x +new file mode 100644 +index 00000000000..019ef54eae7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/mve/pr108177.x +@@ -0,0 +1,9 @@ ++#include "pr108177-main.x" ++ ++__attribute__ ((noipa)) void ++test (uint32x4_t v, void *a, mve_pred16_t p1, mve_pred16_t p2) ++{ ++ TYPE _v = (TYPE) v; ++ INTRINSIC_P (a, _v, p1); ++ INTRINSIC_P (a, _v, p2); ++} +diff --git a/gcc/testsuite/gcc.target/arm/pr109939.c b/gcc/testsuite/gcc.target/arm/pr109939.c +new file mode 100644 +index 00000000000..aafda7cd3cd +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/pr109939.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_sat_ok } */ ++/* { dg-add-options arm_sat } */ ++/* { dg-additional-options "-O -Wall -Wconversion" } */ ++ ++#include ++ ++int dbg_ssat_out; ++int dbg_ssat_in; ++ ++void test_arm_ssat(void) ++{ ++ dbg_ssat_out = __ssat(dbg_ssat_in, 16); ++} +diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c +new file mode 100644 +index 00000000000..d797b790232 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c +@@ -0,0 +1,4 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_hard_ok } */ ++/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mbig-endian -mpure-code" } */ ++double f() { return 5.0; } +diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c +index 029c931f47f..887f8dbddd9 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c ++++ b/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c +@@ -50,31 +50,31 @@ TEST_TYPE (vs32, __INT32_TYPE__, COMPARE_REG_AND_ZERO, 16) + TEST_TYPE (vu32, __UINT32_TYPE__, COMPARE_REG, 16) + + /* { 8 bits } x { eq, ne, lt, le, gt, ge, hi, cs }. +-/* { dg-final { scan-assembler-times {\tvcmp.i8 eq, q[0-9]+, q[0-9]+\n} 4 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.i8 ne, q[0-9]+, q[0-9]+\n} 4 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s8 lt, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s8 le, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s8 gt, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s8 ge, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u8 hi, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u8 cs, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i8\teq, q[0-9]+, q[0-9]+\n} 4 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i8\tne, q[0-9]+, q[0-9]+\n} 4 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s8\tlt, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s8\tle, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s8\tgt, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s8\tge, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u8\thi, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u8\tcs, q[0-9]+, q[0-9]+\n} 2 } } */ + + /* { 16 bits } x { eq, ne, lt, le, gt, ge, hi, cs }. +-/* { dg-final { scan-assembler-times {\tvcmp.i16 eq, q[0-9]+, q[0-9]+\n} 4 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.i16 ne, q[0-9]+, q[0-9]+\n} 4 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s16 lt, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s16 le, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s16 gt, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s16 ge, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u16 hi, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u16 cs, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i16\teq, q[0-9]+, q[0-9]+\n} 4 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i16\tne, q[0-9]+, q[0-9]+\n} 4 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s16\tlt, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s16\tle, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s16\tgt, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s16\tge, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u16\thi, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u16\tcs, q[0-9]+, q[0-9]+\n} 2 } } */ + + /* { 32 bits } x { eq, ne, lt, le, gt, ge, hi, cs }. +-/* { dg-final { scan-assembler-times {\tvcmp.i32 eq, q[0-9]+, q[0-9]+\n} 4 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.i32 ne, q[0-9]+, q[0-9]+\n} 4 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s32 lt, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s32 le, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s32 gt, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s32 ge, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u32 hi, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u32 cs, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i32\teq, q[0-9]+, q[0-9]+\n} 4 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i32\tne, q[0-9]+, q[0-9]+\n} 4 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s32\tlt, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s32\tle, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s32\tgt, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s32\tge, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u32\thi, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u32\tcs, q[0-9]+, q[0-9]+\n} 2 } } */ +diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c +index 77749723693..20ab0a2f040 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c ++++ b/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c +@@ -39,31 +39,31 @@ TEST_TYPE (vs32, __INT32_TYPE__, 16) + TEST_TYPE (vu32, __UINT32_TYPE__, 16) + + /* { 8 bits } x { eq, ne, lt, le, gt, ge, hi, cs }. +-/* { dg-final { scan-assembler-times {\tvcmp.i8 eq, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.i8 ne, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s8 lt, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s8 le, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s8 gt, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s8 ge, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u8 hi, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u8 cs, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i8\teq, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i8\tne, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s8\tlt, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s8\tle, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s8\tgt, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s8\tge, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u8\thi, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u8\tcs, q[0-9]+, q[0-9]+\n} 2 } } */ + + /* { 16 bits } x { eq, ne, lt, le, gt, ge, hi, cs }. +-/* { dg-final { scan-assembler-times {\tvcmp.i16 eq, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.i16 ne, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s16 lt, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s16 le, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s16 gt, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s16 ge, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u16 hi, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u16 cs, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i16\teq, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i16\tne, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s16\tlt, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s16\tle, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s16\tgt, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s16\tge, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u16\thi, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u16\tcs, q[0-9]+, q[0-9]+\n} 2 } } */ + + /* { 32 bits } x { eq, ne, lt, le, gt, ge, hi, cs }. +-/* { dg-final { scan-assembler-times {\tvcmp.i32 eq, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.i32 ne, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s32 lt, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s32 le, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s32 gt, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s32 ge, q[0-9]+, q[0-9]+\n} 1 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u32 hi, q[0-9]+, q[0-9]+\n} 2 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u32 cs, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i32\teq, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i32\tne, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s32\tlt, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s32\tle, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s32\tgt, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s32\tge, q[0-9]+, q[0-9]+\n} 1 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u32\thi, q[0-9]+, q[0-9]+\n} 2 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u32\tcs, q[0-9]+, q[0-9]+\n} 2 } } */ +diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c b/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c +index 64cd1c2eb4a..f2f9ee34990 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c ++++ b/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c +@@ -38,7 +38,7 @@ FUNC(f, float, 16, 8, vabs) + integer optimizations actually generate a call to memmove, the other ones a + 'vabs'. */ + /* { dg-final { scan-assembler-times {vabs.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */ +-/* { dg-final { scan-assembler-times {vabs.f[0-9]+ q[0-9]+, q[0-9]+} 2 } } */ ++/* { dg-final { scan-assembler-times {vabs.f[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */ + /* { dg-final { scan-assembler-times {vldr[bhw].[0-9]+\tq[0-9]+} 5 } } */ + /* { dg-final { scan-assembler-times {vstr[bhw].[0-9]+\tq[0-9]+} 5 } } */ + /* { dg-final { scan-assembler-times {memmove} 3 } } */ +diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c +index 15a9daacecf..f31d1cc7f42 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c ++++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c +@@ -22,9 +22,9 @@ FUNC(u, uint, 16, 8, +, vadd) + FUNC(s, int, 8, 16, +, vadd) + FUNC(u, uint, 8, 16, +, vadd) + +-/* { dg-final { scan-assembler-times {vadd\.i32 q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */ +-/* { dg-final { scan-assembler-times {vadd\.i16 q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */ +-/* { dg-final { scan-assembler-times {vadd\.i8 q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */ ++/* { dg-final { scan-assembler-times {vadd\.i32\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */ ++/* { dg-final { scan-assembler-times {vadd\.i16\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */ ++/* { dg-final { scan-assembler-times {vadd\.i8\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */ + + void test_vadd_f32 (float * dest, float * a, float * b) { + int i; +@@ -32,7 +32,7 @@ void test_vadd_f32 (float * dest, float * a, float * b) { + dest[i] = a[i] + b[i]; + } + } +-/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */ ++/* { dg-final { scan-assembler-times {vadd\.f32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */ + + void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) { + int i; +@@ -40,4 +40,4 @@ void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) { + dest[i] = a[i] + b[i]; + } + } +-/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */ ++/* { dg-final { scan-assembler-times {vadd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */ +diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c +index bbf70e14146..7eec2346faa 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c ++++ b/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c +@@ -24,9 +24,9 @@ FUNC_IMM(u, uint, 8, 16, +, vaddimm) + + /* For the moment we do not select the T2 vadd variant operating on a scalar + final argument. */ +-/* { dg-final { scan-assembler-times {vadd\.i32 q[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */ +-/* { dg-final { scan-assembler-times {vadd\.i16 q[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */ +-/* { dg-final { scan-assembler-times {vadd\.i8 q[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {vadd\.i32\tq[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {vadd\.i16\tq[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {vadd\.i8\tq[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */ + + void test_vaddimm_f32 (float * dest, float * a) { + int i; +@@ -34,7 +34,7 @@ void test_vaddimm_f32 (float * dest, float * a) { + dest[i] = a[i] + 5.0; + } + } +-/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {vadd\.f32\tq[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */ + + /* Note that dest[i] = a[i] + 5.0f16 is not vectorized. */ + void test_vaddimm_f16 (__fp16 * dest, __fp16 * a) { +@@ -44,4 +44,4 @@ void test_vaddimm_f16 (__fp16 * dest, __fp16 * a) { + dest[i] = a[i] + b; + } + } +-/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {vadd\.f16\tq[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */ +diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c b/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c +index 7068736bc28..38e91fc5bce 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c ++++ b/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c +@@ -23,6 +23,6 @@ FUNC(u, uint, 8, clz) + + /* 16 and 8-bit versions are not vectorized because they need pack/unpack + patterns since __builtin_clz uses 32-bit parameter and return value. */ +-/* { dg-final { scan-assembler-times {vclz\.i32 q[0-9]+, q[0-9]+} 2 } } */ +-/* { dg-final { scan-assembler-times {vclz\.i16 q[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */ +-/* { dg-final { scan-assembler-times {vclz\.i8 q[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {vclz\.i32\tq[0-9]+, q[0-9]+} 2 } } */ ++/* { dg-final { scan-assembler-times {vclz\.i16\tq[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {vclz\.i8\tq[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */ +diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c +index 8da15e762eb..806b1458cf3 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c ++++ b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c +@@ -36,15 +36,15 @@ ALL_FUNCS(>=, vcmpge) + + /* MVE has only 128-bit vectors, so we can vectorize only half of the + functions above. */ +-/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+ eq, q[0-9]+, q[0-9]+\n} 6 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+ ne, q[0-9]+, q[0-9]+\n} 6 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+\teq, q[0-9]+, q[0-9]+\n} 6 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+\tne, q[0-9]+, q[0-9]+\n} 6 } } */ + + /* lt, le, gt, ge apply to signed types, cs and hi to unsigned types. */ + /* lt and le with unsigned types are replaced with the opposite condition, hence + the double number of matches for cs and hi. */ +-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+ lt, q[0-9]+, q[0-9]+\n} 3 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+ le, q[0-9]+, q[0-9]+\n} 3 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+ gt, q[0-9]+, q[0-9]+\n} 3 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+ ge, q[0-9]+, q[0-9]+\n} 3 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+ cs, q[0-9]+, q[0-9]+\n} 6 } } */ +-/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+ hi, q[0-9]+, q[0-9]+\n} 6 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tlt, q[0-9]+, q[0-9]+\n} 3 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tle, q[0-9]+, q[0-9]+\n} 3 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tgt, q[0-9]+, q[0-9]+\n} 3 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tge, q[0-9]+, q[0-9]+\n} 3 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+\tcs, q[0-9]+, q[0-9]+\n} 6 } } */ ++/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+\thi, q[0-9]+, q[0-9]+\n} 6 } } */ +diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c +index 7945a060e25..1379cae579f 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c ++++ b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c +@@ -45,8 +45,8 @@ FUNC(f, float, 16, 8, -, vneg) + + /* MVE has only 128-bit vectors, so we can vectorize only half of the + functions above. */ +-/* { dg-final { scan-assembler-times {vneg.s[0-9]+ q[0-9]+, q[0-9]+} 6 } } */ +-/* { dg-final { scan-assembler-times {vneg.f[0-9]+ q[0-9]+, q[0-9]+} 2 } } */ ++/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */ ++/* { dg-final { scan-assembler-times {vneg.f[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */ + /* { dg-final { scan-assembler-times {vldr[bhw].[0-9]+\tq[0-9]+} 8 } } */ + /* { dg-final { scan-assembler-times {vstr[bhw].[0-9]+\tq[0-9]+} 8 } } */ + /* { dg-final { scan-assembler-not {orr\tr[0-9]+, r[0-9]+, r[0-9]+} } } */ +diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c +index d4258e9fefe..8c7adef9ed8 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c ++++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c +@@ -58,7 +58,7 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm) + /* Vector right shifts use vneg and left shifts. */ + /* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */ + /* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */ +-/* { dg-final { scan-assembler-times {vneg.s[0-9]+ q[0-9]+, q[0-9]+} 6 } } */ ++/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */ + + + /* Shift by immediate. */ +diff --git a/gcc/testsuite/gcc.target/arm/simd/pr101325.c b/gcc/testsuite/gcc.target/arm/simd/pr101325.c +index 4cb2513da87..ce9ce3a8c19 100644 +--- a/gcc/testsuite/gcc.target/arm/simd/pr101325.c ++++ b/gcc/testsuite/gcc.target/arm/simd/pr101325.c +@@ -9,6 +9,6 @@ unsigned foo(int8x16_t v, int8x16_t w) + { + return vcmpeqq (v, w); + } +-/* { dg-final { scan-assembler {\tvcmp.i8 eq} } } */ +-/* { dg-final { scan-assembler {\tvmrs\tr[0-9]+, P0} } } */ ++/* { dg-final { scan-assembler {\tvcmp.i8\teq} } } */ ++/* { dg-final { scan-assembler {\tvmrs\tr[0-9]+, p0} } } */ + /* { dg-final { scan-assembler {\tuxth} } } */ +diff --git a/gcc/testsuite/gcc.target/avr/pr82931.c b/gcc/testsuite/gcc.target/avr/pr82931.c +new file mode 100644 +index 00000000000..477284fa127 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/avr/pr82931.c +@@ -0,0 +1,29 @@ ++/* { dg-options "-Os" } */ ++/* { dg-final { scan-assembler-times "bst" 4 } } */ ++/* { dg-final { scan-assembler-times "bld" 4 } } */ ++ ++typedef __UINT8_TYPE__ uint8_t; ++typedef __UINT16_TYPE__ uint16_t; ++ ++#define BitMask (1u << 14) ++#define Bit8Mask ((uint8_t) (1u << 4)) ++ ++void merge1_8 (uint8_t *dst, const uint8_t *src) ++{ ++ *dst = (*src & Bit8Mask) | (*dst & ~ Bit8Mask); ++} ++ ++void merge2_8 (uint8_t *dst, const uint8_t *src) ++{ ++ *dst ^= (*dst ^ *src) & Bit8Mask; ++} ++ ++void merge1_16 (uint16_t *dst, const uint16_t *src) ++{ ++ *dst = (*src & BitMask) | (*dst & ~ BitMask); ++} ++ ++void merge2_16 (uint16_t *dst, const uint16_t *src) ++{ ++ *dst ^= (*dst ^ *src) & BitMask; ++} +diff --git a/gcc/testsuite/gcc.target/avr/torture/pr105753.c b/gcc/testsuite/gcc.target/avr/torture/pr105753.c +new file mode 100644 +index 00000000000..7d7cea1de7a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/avr/torture/pr105753.c +@@ -0,0 +1,13 @@ ++int digit_sum (unsigned long n) ++{ ++ int sum = 0; ++ ++ do ++ { ++ int x = n % 10; ++ n /= 10; ++ sum += x; ++ } while(n); ++ ++ return sum; ++} +diff --git a/gcc/testsuite/gcc.target/avr/torture/pr109650-1.c b/gcc/testsuite/gcc.target/avr/torture/pr109650-1.c +new file mode 100644 +index 00000000000..9030db00fde +--- /dev/null ++++ b/gcc/testsuite/gcc.target/avr/torture/pr109650-1.c +@@ -0,0 +1,63 @@ ++/* { dg-do run } */ ++/* { dg-options { -std=c99 } } */ ++ ++typedef _Bool bool; ++typedef __UINT8_TYPE__ uint8_t; ++ ++static inline __attribute__((__always_inline__)) ++bool func1a (bool p1, uint8_t p2) ++{ ++ if (p1) ++ return p2 <= 8; ++ return p2 <= 2; ++} ++ ++__attribute__((__noinline__, __noclone__)) ++bool func1b (bool p1, uint8_t p2) ++{ ++ return func1a (p1, p2); ++} ++ ++static inline __attribute__((__always_inline__)) ++bool func2a (bool p1, unsigned p2) ++{ ++ if (p1) ++ return p2 <= 8; ++ return p2 <= 2; ++} ++ ++__attribute__((__noinline__, __noclone__)) ++bool func2b (bool p1, unsigned p2) ++{ ++ return func2a (p1, p2); ++} ++ ++void test1 (void) ++{ ++ if (func1a (0, 1) != func1b (0, 1)) __builtin_abort(); ++ if (func1a (0, 2) != func1b (0, 2)) __builtin_abort(); ++ if (func1a (0, 3) != func1b (0, 3)) __builtin_abort(); ++ ++ if (func1a (1, 7) != func1b (1, 7)) __builtin_abort(); ++ if (func1a (1, 8) != func1b (1, 8)) __builtin_abort(); ++ if (func1a (1, 9) != func1b (1, 9)) __builtin_abort(); ++} ++ ++void test2 (void) ++{ ++ if (func2a (0, 1) != func2b (0, 1)) __builtin_abort(); ++ if (func2a (0, 2) != func2b (0, 2)) __builtin_abort(); ++ if (func2a (0, 3) != func2b (0, 3)) __builtin_abort(); ++ ++ if (func2a (1, 7) != func2b (1, 7)) __builtin_abort(); ++ if (func2a (1, 8) != func2b (1, 8)) __builtin_abort(); ++ if (func2a (1, 9) != func2b (1, 9)) __builtin_abort(); ++} ++ ++int main (void) ++{ ++ test1(); ++ test2(); ++ ++ __builtin_exit (0); ++} +diff --git a/gcc/testsuite/gcc.target/avr/torture/pr109650-2.c b/gcc/testsuite/gcc.target/avr/torture/pr109650-2.c +new file mode 100644 +index 00000000000..386dc322afa +--- /dev/null ++++ b/gcc/testsuite/gcc.target/avr/torture/pr109650-2.c +@@ -0,0 +1,79 @@ ++/* { dg-do run } */ ++ ++typedef __UINT8_TYPE__ uint8_t; ++ ++#define AI static __inline__ __attribute__((__always_inline__)) ++#define NI __attribute__((__noinline__,__noclone__)) ++ ++AI uint8_t func1_eq (uint8_t c, unsigned x) ++{ ++ if (x == c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_ne (uint8_t c, unsigned x) ++{ ++ if (x != c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_ltu (uint8_t c, unsigned x) ++{ ++ if (x < c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_leu (uint8_t c, unsigned x) ++{ ++ if (x <= c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_gtu (uint8_t c, unsigned x) ++{ ++ if (x > c) ++ return 1; ++ return 0; ++} ++ ++AI uint8_t func1_geu (uint8_t c, unsigned x) ++{ ++ if (x >= c) ++ return 1; ++ return 0; ++} ++ ++NI uint8_t func2_eq (uint8_t c, unsigned x) { return func1_eq (c, x); } ++NI uint8_t func2_ne (uint8_t c, unsigned x) { return func1_ne (c, x); } ++NI uint8_t func2_ltu (uint8_t c, unsigned x) { return func1_ltu (c, x); } ++NI uint8_t func2_leu (uint8_t c, unsigned x) { return func1_leu (c, x); } ++NI uint8_t func2_gtu (uint8_t c, unsigned x) { return func1_gtu (c, x); } ++NI uint8_t func2_geu (uint8_t c, unsigned x) { return func1_geu (c, x); } ++ ++AI void test4 (uint8_t c, unsigned x) ++{ ++ if (func2_eq (c, x) != func1_eq (c, x)) __builtin_abort(); ++ if (func2_ne (c, x) != func1_ne (c, x)) __builtin_abort(); ++ if (func2_ltu (c, x) != func1_ltu (c, x)) __builtin_abort(); ++ if (func2_leu (c, x) != func1_leu (c, x)) __builtin_abort(); ++ if (func2_gtu (c, x) != func1_gtu (c, x)) __builtin_abort(); ++ if (func2_geu (c, x) != func1_geu (c, x)) __builtin_abort(); ++} ++ ++int main (void) ++{ ++ test4 (127, 127); ++ test4 (127, 128); ++ test4 (128, 127); ++ ++ test4 (0x42, 0x142); ++ test4 (0x0, 0x100); ++ test4 (0x0, 0x0); ++ test4 (0x0, 0x1); ++ ++ __builtin_exit (0); ++} +diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c +index e694d4048bd..5a40e87832c 100644 +--- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c ++++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c +@@ -16,5 +16,6 @@ foo () + _mm256_zeroupper (); + } + +-/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 { target ia32 } } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 5 { target { ! ia32 } } } } */ + /* { dg-final { scan-assembler-times "\\*avx_vzeroall" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-29.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-29.c +new file mode 100644 +index 00000000000..4af637757f7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-29.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O0 -mavx -mtune=generic -mvzeroupper -dp" } */ ++ ++#include ++ ++extern __m256 x, y; ++ ++void ++foo () ++{ ++ x = y; ++} ++ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c +index ab6d68779b3..75fe5889783 100644 +--- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c ++++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c +@@ -12,4 +12,5 @@ foo () + _mm256_zeroupper (); + } + +-/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 { target ia32 } } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 2 { target { ! ia32 } } } } */ +diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c +index 974e1626a6d..fa0a6dfcaac 100644 +--- a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c ++++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c +@@ -15,4 +15,5 @@ foo () + _mm256_zeroupper (); + } + +-/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 { target ia32 } } } */ ++/* { dg-final { scan-assembler-times "avx_vzeroupper" 5 { target { ! ia32 } } } } */ +diff --git a/gcc/testsuite/gcc.target/i386/avx2-gather-2.c b/gcc/testsuite/gcc.target/i386/avx2-gather-2.c +index ad5ef73107c..978924b0f57 100644 +--- a/gcc/testsuite/gcc.target/i386/avx2-gather-2.c ++++ b/gcc/testsuite/gcc.target/i386/avx2-gather-2.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O3 -fdump-tree-vect-details -march=skylake" } */ ++/* { dg-options "-O3 -fdump-tree-vect-details -march=skylake -mtune=haswell" } */ + + #include "avx2-gather-1.c" + +diff --git a/gcc/testsuite/gcc.target/i386/avx2-gather-6.c b/gcc/testsuite/gcc.target/i386/avx2-gather-6.c +index b9119581ae2..067b251e393 100644 +--- a/gcc/testsuite/gcc.target/i386/avx2-gather-6.c ++++ b/gcc/testsuite/gcc.target/i386/avx2-gather-6.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O3 -mavx2 -fno-common -fdump-tree-vect-details -mtune=skylake" } */ ++/* { dg-options "-O3 -mavx2 -fno-common -fdump-tree-vect-details -mtune=haswell" } */ + + #include "avx2-gather-5.c" + +diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr88464-1.c b/gcc/testsuite/gcc.target/i386/avx512f-pr88464-1.c +index 06d21bb0129..d1a2298618e 100644 +--- a/gcc/testsuite/gcc.target/i386/avx512f-pr88464-1.c ++++ b/gcc/testsuite/gcc.target/i386/avx512f-pr88464-1.c +@@ -1,6 +1,6 @@ + /* PR tree-optimization/88464 */ + /* { dg-do compile } */ +-/* { dg-options "-O3 -mavx512f -mprefer-vector-width=512 -mtune=skylake-avx512 -fdump-tree-vect-details" } */ ++/* { dg-options "-O3 -mavx512f -mprefer-vector-width=512 -mtune=haswell -fdump-tree-vect-details" } */ + /* { dg-final { scan-tree-dump-times "loop vectorized using 64 byte vectors" 4 "vect" } } */ + /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ + +diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr88464-5.c b/gcc/testsuite/gcc.target/i386/avx512f-pr88464-5.c +index 462e951fdc1..d7b0b2b28cb 100644 +--- a/gcc/testsuite/gcc.target/i386/avx512f-pr88464-5.c ++++ b/gcc/testsuite/gcc.target/i386/avx512f-pr88464-5.c +@@ -1,6 +1,6 @@ + /* PR tree-optimization/88464 */ + /* { dg-do compile } */ +-/* { dg-options "-O3 -mavx512f -mprefer-vector-width=512 -mtune=skylake-avx512 -fdump-tree-vect-details" } */ ++/* { dg-options "-O3 -mavx512f -mprefer-vector-width=512 -mtune=haswell -fdump-tree-vect-details" } */ + /* { dg-final { scan-tree-dump-times "loop vectorized using 64 byte vectors" 4 "vect" } } */ + /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ + +diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-1.c +index 55a28dddbf8..07439185ec1 100644 +--- a/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-1.c ++++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-1.c +@@ -1,6 +1,6 @@ + /* PR tree-optimization/88464 */ + /* { dg-do compile } */ +-/* { dg-options "-O3 -mavx512vl -mprefer-vector-width=256 -mtune=skylake-avx512 -fdump-tree-vect-details" } */ ++/* { dg-options "-O3 -mavx512vl -mprefer-vector-width=256 -mtune=haswell -fdump-tree-vect-details" } */ + /* { dg-final { scan-tree-dump-times "loop vectorized using 32 byte vectors" 4 "vect" } } */ + /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ + +diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-11.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-11.c +index 9696008855d..3a98108279a 100644 +--- a/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-11.c ++++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-11.c +@@ -1,6 +1,6 @@ + /* PR tree-optimization/88464 */ + /* { dg-do compile } */ +-/* { dg-options "-O3 -mavx512vl -mprefer-vector-width=128 -mtune=skylake-avx512 -fdump-tree-vect-details" } */ ++/* { dg-options "-O3 -mavx512vl -mprefer-vector-width=128 -mtune=haswell -fdump-tree-vect-details" } */ + /* { dg-final { scan-tree-dump-times "loop vectorized using 16 byte vectors" 4 "vect" } } */ + /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ + +diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-3.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-3.c +index 6b0c8a85957..ac669e04812 100644 +--- a/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-3.c ++++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-3.c +@@ -1,6 +1,6 @@ + /* PR tree-optimization/88464 */ + /* { dg-do compile } */ +-/* { dg-options "-O3 -mavx512vl -mprefer-vector-width=128 -mtune=skylake-avx512 -fdump-tree-vect-details" } */ ++/* { dg-options "-O3 -mavx512vl -mprefer-vector-width=128 -mtune=haswell -fdump-tree-vect-details" } */ + /* { dg-final { scan-tree-dump-times "loop vectorized using 16 byte vectors" 4 "vect" } } */ + /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ + +diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-9.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-9.c +index 3af568ab323..14a1083b6d1 100644 +--- a/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-9.c ++++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr88464-9.c +@@ -1,6 +1,6 @@ + /* PR tree-optimization/88464 */ + /* { dg-do compile } */ +-/* { dg-options "-O3 -mavx512vl -mprefer-vector-width=256 -mtune=skylake-avx512 -fdump-tree-vect-details" } */ ++/* { dg-options "-O3 -mavx512vl -mprefer-vector-width=256 -mtune=haswell -fdump-tree-vect-details" } */ + /* { dg-final { scan-tree-dump-times "loop vectorized using 32 byte vectors" 4 "vect" } } */ + /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ + +diff --git a/gcc/testsuite/gcc.target/i386/mvc17.c b/gcc/testsuite/gcc.target/i386/mvc17.c +new file mode 100644 +index 00000000000..8b83c1aecb3 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/mvc17.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-require-ifunc "" } */ ++/* { dg-options "-O2 -march=x86-64" } */ ++/* { dg-final { scan-assembler-times "rep mov" 1 } } */ ++ ++__attribute__((target_clones("default","arch=icelake-server"))) ++void ++foo (char *a, char *b, int size) ++{ ++ __builtin_memcpy (a, b, size & 0x7F); ++} +diff --git a/gcc/testsuite/gcc.target/i386/pr110108-2.c b/gcc/testsuite/gcc.target/i386/pr110108-2.c +new file mode 100644 +index 00000000000..2d1d2fd4991 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr110108-2.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mavx2 -O2 -funsigned-char" } */ ++/* { dg-final { scan-assembler-times "vpblendvb" 2 } } */ ++ ++#include ++__m128i do_stuff_128(__m128i X0, __m128i X1, __m128i X2) { ++ __m128i Result = _mm_blendv_epi8(X0, X1, X2); ++ return Result; ++} ++ ++__m256i do_stuff_256(__m256i X0, __m256i X1, __m256i X2) { ++ __m256i Result = _mm256_blendv_epi8(X0, X1, X2); ++ return Result; ++} +diff --git a/gcc/testsuite/gcc.target/i386/pr110170-3.c b/gcc/testsuite/gcc.target/i386/pr110170-3.c +new file mode 100644 +index 00000000000..70daa89e9aa +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr110170-3.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile { target { ! ia32 } } } */ ++/* { dg-options "-O2 -fno-if-conversion -fno-if-conversion2" } */ ++/* { dg-final { scan-assembler-not {(?n)movq.*r} } } */ ++ ++void __cond_swap(double* __x, double* __y) { ++ _Bool __r = (*__x < *__y); ++ double __tmp = __r ? *__x : *__y; ++ *__y = __r ? *__y : *__x; ++ *__x = __tmp; ++} ++ +diff --git a/gcc/testsuite/gcc.target/i386/pr110206.c b/gcc/testsuite/gcc.target/i386/pr110206.c +new file mode 100644 +index 00000000000..af1455c5aa9 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr110206.c +@@ -0,0 +1,39 @@ ++/* PR target/110206 */ ++/* { dg-do run } */ ++/* { dg-options "-Os -mavx512bw -mavx512vl" } */ ++/* { dg-require-effective-target avx512bw } */ ++/* { dg-require-effective-target avx512vl } */ ++ ++#define AVX512BW ++#define AVX512VL ++ ++#include "avx512f-check.h" ++ ++typedef unsigned char __attribute__((__vector_size__ (4))) U; ++typedef unsigned char __attribute__((__vector_size__ (8))) V; ++typedef unsigned short u16; ++ ++V g; ++ ++void ++__attribute__((noinline)) ++foo (U u, u16 c, V *r) ++{ ++ if (!c) ++ abort (); ++ V x = __builtin_shufflevector (u, (204 >> u), 7, 0, 5, 1, 3, 5, 0, 2); ++ V y = __builtin_shufflevector (g, (V) { }, 7, 6, 6, 7, 2, 6, 3, 5); ++ V z = __builtin_shufflevector (y, 204 * x, 3, 9, 8, 1, 4, 6, 14, 5); ++ *r = z; ++} ++ ++static void test_256 (void) { }; ++ ++static void ++test_128 (void) ++{ ++ V r; ++ foo ((U){4}, 5, &r); ++ if (r[6] != 0x30) ++ abort(); ++} +diff --git a/gcc/testsuite/gcc.target/i386/pr110309.c b/gcc/testsuite/gcc.target/i386/pr110309.c +new file mode 100644 +index 00000000000..f6e9e9c3c61 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr110309.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O3 --param vect-partial-vector-usage=1 -march=znver4 -mprefer-vector-width=256" } */ ++/* { dg-final { scan-assembler-not {(?n)vpblendd.*ymm} } } */ ++ ++ ++void foo (int * __restrict a, int *b) ++{ ++ for (int i = 0; i < 6; ++i) ++ a[i] = b[i] + 42; ++} +diff --git a/gcc/testsuite/gcc.target/i386/pr111306.c b/gcc/testsuite/gcc.target/i386/pr111306.c +new file mode 100644 +index 00000000000..541725ebdad +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr111306.c +@@ -0,0 +1,36 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 -mavx512fp16 -mavx512vl" } */ ++/* { dg-require-effective-target avx512fp16 } */ ++ ++#define AVX512FP16 ++#include "avx512f-helper.h" ++ ++__attribute__((optimize("O2"),noipa)) ++void func1(_Float16 *a, _Float16 *b, int n, _Float16 *c) { ++ __m512h rA = _mm512_loadu_ph(a); ++ for (int i = 0; i < n; i += 32) { ++ __m512h rB = _mm512_loadu_ph(b + i); ++ _mm512_storeu_ph(c + i, _mm512_fcmul_pch(rB, rA)); ++ } ++} ++ ++void ++test_512 (void) ++{ ++ int n = 32; ++ _Float16 a[n], b[n], c[n]; ++ _Float16 exp[n]; ++ for (int i = 1; i <= n; i++) { ++ a[i - 1] = i & 1 ? -i : i; ++ b[i - 1] = i; ++ } ++ ++ func1(a, b, n, c); ++ for (int i = 0; i < n / 32; i += 2) { ++ if (c[i] != a[i] * b[i] + a[i+1] * b[i+1] ++ || c[i+1] != a[i] * b[i+1] - a[i+1]*b[i]) ++ __builtin_abort (); ++ } ++} ++ ++ +diff --git a/gcc/testsuite/gcc.target/i386/pr111340.c b/gcc/testsuite/gcc.target/i386/pr111340.c +new file mode 100644 +index 00000000000..6539ae566c0 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr111340.c +@@ -0,0 +1,9 @@ ++/* PR target/111340 */ ++/* { dg-do compile { target { fpic && int128 } } } */ ++/* { dg-options "-O2 -fpic" } */ ++ ++void ++bar (void) ++{ ++ __asm ("# %0" : : "g" ((((unsigned __int128) 0x123456789abcdef0ULL) << 64) | 0x0fedcba987654321ULL)); ++} +diff --git a/gcc/testsuite/gcc.target/i386/pr112672.c b/gcc/testsuite/gcc.target/i386/pr112672.c +new file mode 100644 +index 00000000000..583e9fdfb8b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr112672.c +@@ -0,0 +1,23 @@ ++/* PR target/112672 */ ++/* { dg-do run } */ ++/* { dg-options "-O2" } */ ++ ++typedef unsigned short u16; ++ ++u16 g = 254; ++ ++static inline u16 ++foo (u16 u) ++{ ++ u *= g; ++ return u + __builtin_parityl (u); ++} ++ ++int ++main (void) ++{ ++ u16 x = foo (4); ++ if (x != 4 * 254 + 1) ++ __builtin_abort (); ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/i386/pr112891-2.c b/gcc/testsuite/gcc.target/i386/pr112891-2.c +new file mode 100644 +index 00000000000..164c3985d50 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr112891-2.c +@@ -0,0 +1,30 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mavx2 -O3" } */ ++/* { dg-final { scan-assembler-times "vzeroupper" 1 } } */ ++ ++void ++__attribute__((noinline)) ++bar (double* a) ++{ ++ a[0] = 1.0; ++ a[1] = 2.0; ++} ++ ++double ++__attribute__((noinline)) ++foo (double* __restrict a, double* b) ++{ ++ a[0] += b[0]; ++ a[1] += b[1]; ++ a[2] += b[2]; ++ a[3] += b[3]; ++ bar (b); ++ return a[5] + b[5]; ++} ++ ++double ++foo1 (double* __restrict a, double* b) ++{ ++ double c = foo (a, b); ++ return __builtin_exp (c); ++} +diff --git a/gcc/testsuite/gcc.target/i386/pr112891.c b/gcc/testsuite/gcc.target/i386/pr112891.c +new file mode 100644 +index 00000000000..dbf6c67948a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr112891.c +@@ -0,0 +1,29 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mavx2 -O3" } */ ++/* { dg-final { scan-assembler-times "vzeroupper" 1 } } */ ++ ++void ++__attribute__((noinline)) ++bar (double* a) ++{ ++ a[0] = 1.0; ++ a[1] = 2.0; ++} ++ ++void ++__attribute__((noinline)) ++foo (double* __restrict a, double* b) ++{ ++ a[0] += b[0]; ++ a[1] += b[1]; ++ a[2] += b[2]; ++ a[3] += b[3]; ++ bar (b); ++} ++ ++double ++foo1 (double* __restrict a, double* b) ++{ ++ foo (a, b); ++ return __builtin_exp (b[1]); ++} +diff --git a/gcc/testsuite/gcc.target/i386/pr88531-1b.c b/gcc/testsuite/gcc.target/i386/pr88531-1b.c +index 812c8a10fab..e6df789de90 100644 +--- a/gcc/testsuite/gcc.target/i386/pr88531-1b.c ++++ b/gcc/testsuite/gcc.target/i386/pr88531-1b.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O3 -march=skylake -mfpmath=sse" } */ ++/* { dg-options "-O3 -march=skylake -mfpmath=sse -mtune=haswell" } */ + + #include "pr88531-1a.c" + +diff --git a/gcc/testsuite/gcc.target/i386/pr88531-1c.c b/gcc/testsuite/gcc.target/i386/pr88531-1c.c +index 43fc5913ed3..a093c87c01f 100644 +--- a/gcc/testsuite/gcc.target/i386/pr88531-1c.c ++++ b/gcc/testsuite/gcc.target/i386/pr88531-1c.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O3 -march=skylake-avx512 -mfpmath=sse" } */ ++/* { dg-options "-O3 -march=skylake-avx512 -mfpmath=sse -mtune=haswell" } */ + + #include "pr88531-1a.c" + +diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr112816-2.c b/gcc/testsuite/gcc.target/i386/sse2-pr112816-2.c +new file mode 100644 +index 00000000000..2bfae8fa58e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/sse2-pr112816-2.c +@@ -0,0 +1,16 @@ ++/* PR target/112816 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -msse2" } */ ++ ++#define N 2 ++struct S { float x[N]; }; ++struct T { int x[N]; }; ++ ++struct T ++foo (struct S x) ++{ ++ struct T res; ++ for (int i = 0; i < N; ++i) ++ res.x[i] = __builtin_signbit (x.x[i]) ? -1 : 0; ++ return res; ++} +diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr112816.c b/gcc/testsuite/gcc.target/i386/sse2-pr112816.c +new file mode 100644 +index 00000000000..0701f3cdff8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/sse2-pr112816.c +@@ -0,0 +1,16 @@ ++/* PR target/112816 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -msse2" } */ ++ ++#define N 4 ++struct S { float x[N]; }; ++struct T { int x[N]; }; ++ ++struct T ++foo (struct S x) ++{ ++ struct T res; ++ for (int i = 0; i < N; ++i) ++ res.x[i] = __builtin_signbit (x.x[i]) ? -1 : 0; ++ return res; ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/builtin_thread_pointer.c b/gcc/testsuite/gcc.target/loongarch/builtin_thread_pointer.c +new file mode 100644 +index 00000000000..541e3b143bd +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/builtin_thread_pointer.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target tls_native } */ ++/* { dg-options "-O2" } */ ++/* { dg-final { scan-assembler "or\t\\\$r4,\\\$r2,\\\$r0" } } */ ++ ++void * ++get_tp () ++{ ++ return __builtin_thread_pointer (); ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/cas-acquire.c b/gcc/testsuite/gcc.target/loongarch/cas-acquire.c +new file mode 100644 +index 00000000000..ff7ba866f32 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/cas-acquire.c +@@ -0,0 +1,82 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target c99_runtime } */ ++/* { dg-require-effective-target pthread } */ ++/* { dg-options "-std=c99 -pthread" } */ ++ ++/* https://github.com/llvm/llvm-project/pull/67391#issuecomment-1752403934 ++ reported that this had failed with GCC and 3A6000. */ ++ ++#include ++#include ++#include ++#include ++ ++static unsigned int tags[32]; ++static unsigned int vals[32]; ++ ++static void * ++writer_entry (void *data) ++{ ++ atomic_uint *pt = (atomic_uint *)tags; ++ atomic_uint *pv = (atomic_uint *)vals; ++ ++ for (unsigned int n = 1; n < 10000; n++) ++ { ++ atomic_store_explicit (&pv[n & 31], n, memory_order_release); ++ atomic_store_explicit (&pt[n & 31], n, memory_order_release); ++ } ++ ++ return NULL; ++} ++ ++static void * ++reader_entry (void *data) ++{ ++ atomic_uint *pt = (atomic_uint *)tags; ++ atomic_uint *pv = (atomic_uint *)vals; ++ int i; ++ ++ for (;;) ++ { ++ for (i = 0; i < 32; i++) ++ { ++ unsigned int tag = 0; ++ bool res; ++ ++ res = atomic_compare_exchange_weak_explicit ( ++ &pt[i], &tag, 0, memory_order_acquire, memory_order_acquire); ++ if (!res) ++ { ++ unsigned int val; ++ ++ val = atomic_load_explicit (&pv[i], memory_order_relaxed); ++ if (val < tag) ++ __builtin_trap (); ++ } ++ } ++ } ++ ++ return NULL; ++} ++ ++int ++main (int argc, char *argv[]) ++{ ++ pthread_t writer; ++ pthread_t reader; ++ int res; ++ ++ res = pthread_create (&writer, NULL, writer_entry, NULL); ++ if (res < 0) ++ __builtin_trap (); ++ ++ res = pthread_create (&reader, NULL, reader_entry, NULL); ++ if (res < 0) ++ __builtin_trap (); ++ ++ res = pthread_join (writer, NULL); ++ if (res < 0) ++ __builtin_trap (); ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/powerpc/clone1.c b/gcc/testsuite/gcc.target/powerpc/clone1.c +index c69fd2aa1b8..74323ca0e8c 100644 +--- a/gcc/testsuite/gcc.target/powerpc/clone1.c ++++ b/gcc/testsuite/gcc.target/powerpc/clone1.c +@@ -21,6 +21,7 @@ long mod_func_or (long a, long b, long c) + return mod_func (a, b) | c; + } + +-/* { dg-final { scan-assembler-times {\mdivd\M} 1 } } */ +-/* { dg-final { scan-assembler-times {\mmulld\M} 1 } } */ +-/* { dg-final { scan-assembler-times {\mmodsd\M} 1 } } */ ++/* { Fail due to RS6000_DISABLE_SCALAR_MODULO. */ ++/* { dg-final { scan-assembler-times {\mdivd\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {\mmulld\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {\mmodsd\M} 1 { xfail *-*-* } } } */ +diff --git a/gcc/testsuite/gcc.target/powerpc/clone3.c b/gcc/testsuite/gcc.target/powerpc/clone3.c +index 911b88b781d..d3eb4dd2378 100644 +--- a/gcc/testsuite/gcc.target/powerpc/clone3.c ++++ b/gcc/testsuite/gcc.target/powerpc/clone3.c +@@ -27,7 +27,8 @@ long mod_func_or (long a, long b, long c) + return mod_func (a, b) | c; + } + +-/* { dg-final { scan-assembler-times {\mdivd\M} 1 } } */ +-/* { dg-final { scan-assembler-times {\mmulld\M} 1 } } */ +-/* { dg-final { scan-assembler-times {\mmodsd\M} 2 } } */ ++/* { Fail due to RS6000_DISABLE_SCALAR_MODULO. */ ++/* { dg-final { scan-assembler-times {\mdivd\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {\mmulld\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {\mmodsd\M} 2 { xfail *-*-* } } } */ + /* { dg-final { scan-assembler-times {\mpld\M} 1 } } */ +diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-0.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-0.c +new file mode 100644 +index 00000000000..d8d3c63a083 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-0.c +@@ -0,0 +1,23 @@ ++/* { dg-do compile { target powerpc*-*-darwin* } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-Wno-long-long" } */ ++ ++#include "darwin-structs-0.h" ++ ++int tcd[sizeof(cd) != 12 ? -1 : 1]; ++int acd[__alignof__(cd) != 4 ? -1 : 1]; ++ ++int sdc[sizeof(dc) != 16 ? -1 : 1]; ++int adc[__alignof__(dc) != 8 ? -1 : 1]; ++ ++int scL[sizeof(cL) != 12 ? -1 : 1]; ++int acL[__alignof__(cL) != 4 ? -1 : 1]; ++ ++int sLc[sizeof(Lc) != 16 ? -1 : 1]; ++int aLc[__alignof__(Lc) != 8 ? -1 : 1]; ++ ++int scD[sizeof(cD) != 32 ? -1 : 1]; ++int acD[__alignof__(cD) != 16 ? -1 : 1]; ++ ++int sDc[sizeof(Dc) != 32 ? -1 : 1]; ++int aDc[__alignof__(Dc) != 16 ? -1 : 1]; +diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-1.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-1.c +new file mode 100644 +index 00000000000..4d888d383fa +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-1.c +@@ -0,0 +1,27 @@ ++/* { dg-do compile { target powerpc*-*-darwin* } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-Wno-long-long" } */ ++ ++#pragma pack(push, 1) ++ ++#include "darwin-structs-0.h" ++ ++int tcd[sizeof(cd) != 9 ? -1 : 1]; ++int acd[__alignof__(cd) != 1 ? -1 : 1]; ++ ++int sdc[sizeof(dc) != 9 ? -1 : 1]; ++int adc[__alignof__(dc) != 1 ? -1 : 1]; ++ ++int scL[sizeof(cL) != 9 ? -1 : 1]; ++int acL[__alignof__(cL) != 1 ? -1 : 1]; ++ ++int sLc[sizeof(Lc) != 9 ? -1 : 1]; ++int aLc[__alignof__(Lc) != 1 ? -1 : 1]; ++ ++int scD[sizeof(cD) != 17 ? -1 : 1]; ++int acD[__alignof__(cD) != 1 ? -1 : 1]; ++ ++int sDc[sizeof(Dc) != 17 ? -1 : 1]; ++int aDc[__alignof__(Dc) != 1 ? -1 : 1]; ++ ++#pragma pack(pop) +diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-2.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-2.c +new file mode 100644 +index 00000000000..3bd52c0a8f8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-2.c +@@ -0,0 +1,27 @@ ++/* { dg-do compile { target powerpc*-*-darwin* } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-Wno-long-long" } */ ++ ++#pragma pack(push, 2) ++ ++#include "darwin-structs-0.h" ++ ++int tcd[sizeof(cd) != 10 ? -1 : 1]; ++int acd[__alignof__(cd) != 2 ? -1 : 1]; ++ ++int sdc[sizeof(dc) != 10 ? -1 : 1]; ++int adc[__alignof__(dc) != 2 ? -1 : 1]; ++ ++int scL[sizeof(cL) != 10 ? -1 : 1]; ++int acL[__alignof__(cL) != 2 ? -1 : 1]; ++ ++int sLc[sizeof(Lc) != 10 ? -1 : 1]; ++int aLc[__alignof__(Lc) != 2 ? -1 : 1]; ++ ++int scD[sizeof(cD) != 18 ? -1 : 1]; ++int acD[__alignof__(cD) != 2 ? -1 : 1]; ++ ++int sDc[sizeof(Dc) != 18 ? -1 : 1]; ++int aDc[__alignof__(Dc) != 2 ? -1 : 1]; ++ ++#pragma pack(pop) +diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-structs-0.h b/gcc/testsuite/gcc.target/powerpc/darwin-structs-0.h +new file mode 100644 +index 00000000000..1db44f7a808 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/darwin-structs-0.h +@@ -0,0 +1,29 @@ ++typedef struct _cd { ++ char c; ++ double d; ++} cd; ++ ++typedef struct _dc { ++ double d; ++ char c; ++} dc; ++ ++typedef struct _cL { ++ char c; ++ long long L; ++} cL; ++ ++typedef struct _Lc { ++ long long L; ++ char c; ++} Lc; ++ ++typedef struct _cD { ++ char c; ++ long double D; ++} cD; ++ ++typedef struct _Dc { ++ long double D; ++ char c; ++} Dc; +diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c +index 526a026d874..165bd9a07ad 100644 +--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c ++++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c +@@ -54,15 +54,17 @@ TEST(uint8_t) + TEST(int8_t) + + /* { dg-final { scan-assembler-times "lbz_cmpldi_cr0_QI_clobber_CCUNS_zero" 4 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_DI_CC_none" 4 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_clobber_CC_none" 4 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_DI_CCUNS_none" 1 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_clobber_CCUNS_none" 1 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_DI_CC_none" 24 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_clobber_CC_none" 8 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_DI_CCUNS_none" 2 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_clobber_CCUNS_none" 2 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */ +-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_SI_CC_none" 8 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_SI_CCUNS_none" 2 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */ + + /* { dg-final { scan-assembler-times "lbz_cmpldi_cr0_QI_clobber_CCUNS_zero" 2 { target ilp32 } } } */ +@@ -73,6 +75,8 @@ TEST(int8_t) + /* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */ + /* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */ + /* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */ +-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_SI_CC_none" 36 { target ilp32 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpwi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */ + /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */ + /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */ ++/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_SI_CCUNS_none" 2 { target ilp32 } } } */ +diff --git a/gcc/testsuite/gcc.target/powerpc/mod-1.c b/gcc/testsuite/gcc.target/powerpc/mod-1.c +index 861ba670af4..8720ffb3346 100644 +--- a/gcc/testsuite/gcc.target/powerpc/mod-1.c ++++ b/gcc/testsuite/gcc.target/powerpc/mod-1.c +@@ -7,13 +7,14 @@ long lsmod (long a, long b) { return a%b; } + unsigned int iumod (unsigned int a, unsigned int b) { return a%b; } + unsigned long lumod (unsigned long a, unsigned long b) { return a%b; } + +-/* { dg-final { scan-assembler-times "modsw " 1 } } */ +-/* { dg-final { scan-assembler-times "modsd " 1 } } */ +-/* { dg-final { scan-assembler-times "moduw " 1 } } */ +-/* { dg-final { scan-assembler-times "modud " 1 } } */ +-/* { dg-final { scan-assembler-not "mullw " } } */ +-/* { dg-final { scan-assembler-not "mulld " } } */ +-/* { dg-final { scan-assembler-not "divw " } } */ +-/* { dg-final { scan-assembler-not "divd " } } */ +-/* { dg-final { scan-assembler-not "divwu " } } */ +-/* { dg-final { scan-assembler-not "divdu " } } */ ++/* { Fail due to RS6000_DISABLE_SCALAR_MODULO. */ ++/* { dg-final { scan-assembler-times {\mmodsw\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {\mmodsd\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {\mmoduw\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {\mmodud\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-not {\mmullw\M} { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-not {\mmulld\M} { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-not {\mdivw\M} { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-not {\mdivd\M} { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-not {\mdivwu\M} { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-not {\mdivdu\M} { xfail *-*-* } } } */ +diff --git a/gcc/testsuite/gcc.target/powerpc/mod-2.c b/gcc/testsuite/gcc.target/powerpc/mod-2.c +index 441ec5878f1..54bdca88607 100644 +--- a/gcc/testsuite/gcc.target/powerpc/mod-2.c ++++ b/gcc/testsuite/gcc.target/powerpc/mod-2.c +@@ -5,8 +5,9 @@ + int ismod (int a, int b) { return a%b; } + unsigned int iumod (unsigned int a, unsigned int b) { return a%b; } + +-/* { dg-final { scan-assembler-times "modsw " 1 } } */ +-/* { dg-final { scan-assembler-times "moduw " 1 } } */ +-/* { dg-final { scan-assembler-not "mullw " } } */ +-/* { dg-final { scan-assembler-not "divw " } } */ +-/* { dg-final { scan-assembler-not "divwu " } } */ ++/* { Fail due to RS6000_DISABLE_SCALAR_MODULO. */ ++/* { dg-final { scan-assembler-times {\mmodsw\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-times {\mmoduw\M} 1 { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-not {\mmullw\M} { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-not {\mdivw\M} { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler-not {\mdivwu\M} { xfail *-*-* } } } */ +diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c b/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c +index 84685e5ff43..148998c8c9d 100644 +--- a/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c ++++ b/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c +@@ -23,5 +23,6 @@ __int128 s_mod(__int128 a, __int128 b) + + /* { dg-final { scan-assembler {\mvdivsq\M} } } */ + /* { dg-final { scan-assembler {\mvdivuq\M} } } */ +-/* { dg-final { scan-assembler {\mvmodsq\M} } } */ +-/* { dg-final { scan-assembler {\mvmoduq\M} } } */ ++/* { Fail due to RS6000_DISABLE_SCALAR_MODULO. */ ++/* { dg-final { scan-assembler {\mvmodsq\M} { xfail *-*-* } } } */ ++/* { dg-final { scan-assembler {\mvmoduq\M} { xfail *-*-* } } } */ +diff --git a/gcc/testsuite/gcc.target/powerpc/pr109069-1.c b/gcc/testsuite/gcc.target/powerpc/pr109069-1.c +new file mode 100644 +index 00000000000..eb4d73a1e66 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr109069-1.c +@@ -0,0 +1,25 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target vmx_hw } */ ++/* { dg-options "-O2 -maltivec" } */ ++ ++/* Verify it run successfully. */ ++ ++#include ++ ++__attribute__ ((noipa)) ++vector signed int ++test () ++{ ++ vector signed int v = {-16, -16, -16, -16}; ++ vector signed int res = vec_sld (v, v, 3); ++ return res; ++} ++ ++int ++main () ++{ ++ vector signed int res = test (); ++ if (res[0] != 0xf0ffffff) ++ __builtin_abort (); ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/powerpc/pr109069-2-run.c b/gcc/testsuite/gcc.target/powerpc/pr109069-2-run.c +new file mode 100644 +index 00000000000..fad9fa5df73 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr109069-2-run.c +@@ -0,0 +1,50 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target vsx_hw } */ ++/* { dg-options "-O2 -mvsx" } */ ++ ++/* Verify it doesn't generate wrong code. */ ++ ++#include "pr109069-2.h" ++ ++int ++main () ++{ ++ vector unsigned char res1 = test1 (); ++ for (int i = 0; i < 16; i++) ++ if (res1[i] != 0xd) ++ __builtin_abort (); ++ ++ vector signed short res2 = test2 (); ++ for (int i = 0; i < 8; i++) ++ if (res2[i] != 0x7777) ++ __builtin_abort (); ++ ++ vector signed int res3 = test3 (); ++ vector unsigned int res4 = test4 (); ++ vector float res6 = test6 (); ++ for (int i = 0; i < 4; i++) ++ { ++ if (res3[i] != 0xbbbbbbbb) ++ __builtin_abort (); ++ if (res4[i] != 0x7070707) ++ __builtin_abort (); ++ U32b u; ++ u.f = res6[i]; ++ if (u.i != 0x17171717) ++ __builtin_abort (); ++ } ++ ++ vector unsigned long long res5 = test5 (); ++ vector double res7 = test7 (); ++ for (int i = 0; i < 2; i++) ++ { ++ if (res5[i] != 0x4545454545454545ll) ++ __builtin_abort (); ++ U64b u; ++ u.f = res7[i]; ++ if (u.i != 0x5454545454545454ll) ++ __builtin_abort (); ++ } ++ return 0; ++} ++ +diff --git a/gcc/testsuite/gcc.target/powerpc/pr109069-2.c b/gcc/testsuite/gcc.target/powerpc/pr109069-2.c +new file mode 100644 +index 00000000000..e71bbeb5df5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr109069-2.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* Disable rs6000 optimize_swaps as it drops some REG_EQUAL ++ notes on const vector and affects test point here. */ ++/* { dg-options "-O2 -mvsx -mno-optimize-swaps" } */ ++ ++/* Verify we can optimize away vector shifting if every byte ++ of vector is the same. */ ++ ++#include "pr109069-2.h" ++ ++/* { dg-final { scan-assembler-not {\mvsldoi\M} } } */ +diff --git a/gcc/testsuite/gcc.target/powerpc/pr109069-2.h b/gcc/testsuite/gcc.target/powerpc/pr109069-2.h +new file mode 100644 +index 00000000000..8b03bfb65fa +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr109069-2.h +@@ -0,0 +1,83 @@ ++#include ++ ++typedef union ++{ ++ unsigned int i; ++ float f; ++} U32b; ++ ++typedef union ++{ ++ unsigned long long i; ++ double f; ++} U64b; ++ ++__attribute__ ((noipa)) ++vector unsigned char ++test1 () ++{ ++ vector unsigned char v = {0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, ++ 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd}; ++ vector unsigned char res = vec_sld (v, v, 3); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector signed short ++test2 () ++{ ++ vector signed short v ++ = {0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777}; ++ vector signed short res = vec_sld (v, v, 5); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector signed int ++test3 () ++{ ++ vector signed int v = {0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb}; ++ vector signed int res = vec_sld (v, v, 7); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector unsigned int ++test4 () ++{ ++ vector unsigned int v = {0x07070707, 0x07070707, 0x07070707, 0x07070707}; ++ vector unsigned int res = vec_sld (v, v, 9); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector unsigned long long ++test5 () ++{ ++ vector unsigned long long v = {0x4545454545454545ll, 0x4545454545454545ll}; ++ vector unsigned long long res = vec_sld (v, v, 10); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector float ++test6 () ++{ ++ U32b u; ++ u.i = 0x17171717; ++ vector float vf = {u.f, u.f, u.f, u.f}; ++ vector float res = vec_sld (vf, vf, 11); ++ return res; ++} ++ ++__attribute__ ((noipa)) ++vector double ++test7 () ++{ ++ U64b u; ++ u.i = 0x5454545454545454ll; ++ vector double vf = {u.f, u.f}; ++ vector double res = vec_sld (vf, vf, 13); ++ return res; ++} ++ +diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c +new file mode 100644 +index 00000000000..374d9f60618 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c +@@ -0,0 +1,17 @@ ++/* { dg-require-effective-target int128 } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-maltivec -mno-vsx" } */ ++ ++/* Verify there is no ICE but one expected error message instead. */ ++ ++#include ++ ++extern vector signed __int128 res_vslll; ++extern unsigned long long aull[2]; ++ ++void ++testVectorInt128Pack () ++{ ++ res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */ ++} ++ +diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c +new file mode 100644 +index 00000000000..374d9f60618 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c +@@ -0,0 +1,17 @@ ++/* { dg-require-effective-target int128 } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-maltivec -mno-vsx" } */ ++ ++/* Verify there is no ICE but one expected error message instead. */ ++ ++#include ++ ++extern vector signed __int128 res_vslll; ++extern unsigned long long aull[2]; ++ ++void ++testVectorInt128Pack () ++{ ++ res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */ ++} ++ +diff --git a/gcc/testsuite/gcc.target/powerpc/pr110011.c b/gcc/testsuite/gcc.target/powerpc/pr110011.c +new file mode 100644 +index 00000000000..5b04d3e298a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr110011.c +@@ -0,0 +1,42 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target float128_runtime } */ ++/* Force long double to be with IBM format here, to verify ++ _Float128 constant still uses its own format (IEEE) for ++ encoding rather than IBM format. */ ++/* { dg-options "-mfp-in-toc -mabi=ibmlongdouble" } */ ++/* { dg-add-options float128 } */ ++ ++#define MPFR_FLOAT128_MAX 0x1.ffffffffffffffffffffffffffffp+16383f128 ++ ++__attribute__ ((noipa)) ++_Float128 f128_max () ++{ ++ return MPFR_FLOAT128_MAX; ++} ++ ++typedef union ++{ ++ int w[4]; ++ _Float128 f128; ++} U; ++ ++int main () ++{ ++ ++ U umax; ++ umax.f128 = f128_max (); ++ /* ieee float128 max: ++ 7ffeffff ffffffff ffffffff ffffffff. */ ++ if (umax.w[1] != 0xffffffff || umax.w[2] != 0xffffffff) ++ __builtin_abort (); ++#ifdef __LITTLE_ENDIAN__ ++ if (umax.w[0] != 0xffffffff || umax.w[3] != 0x7ffeffff) ++ __builtin_abort (); ++#else ++ if (umax.w[3] != 0xffffffff || umax.w[0] != 0x7ffeffff) ++ __builtin_abort (); ++#endif ++ ++ return 0; ++} ++ +diff --git a/gcc/testsuite/gcc.target/powerpc/pr111380-1.c b/gcc/testsuite/gcc.target/powerpc/pr111380-1.c +new file mode 100644 +index 00000000000..57ae75ef73a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr111380-1.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target vect_int } */ ++/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ ++ ++/* Verify it emits error message on inlining even without LTO. */ ++ ++vector int c, a, b; ++ ++static inline void __attribute__ ((__always_inline__)) ++foo () /* { dg-error "inlining failed in call to .* target specific option mismatch" } */ ++{ ++ c = a + b; ++} ++ ++__attribute__ ((target ("cpu=power8"))) ++int main () ++{ ++ foo (); /* { dg-message "called from here" } */ ++ c = a + b; ++} +diff --git a/gcc/testsuite/gcc.target/powerpc/pr111380-2.c b/gcc/testsuite/gcc.target/powerpc/pr111380-2.c +new file mode 100644 +index 00000000000..7b363940643 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr111380-2.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target vect_int } */ ++/* { dg-options "-O2 -mno-vsx" } */ ++ ++/* Verify it emits error message on inlining even without LTO. */ ++ ++vector int c, a, b; ++ ++static inline void __attribute__ ((__always_inline__)) ++foo () /* { dg-error "inlining failed in call to .* target specific option mismatch" } */ ++{ ++ c = a + b; ++} ++ ++__attribute__ ((target ("vsx"))) ++int main () ++{ ++ foo (); /* { dg-message "called from here" } */ ++ c = a + b; ++} +diff --git a/gcc/testsuite/gcc.target/powerpc/pr70243.c b/gcc/testsuite/gcc.target/powerpc/pr70243.c +new file mode 100644 +index 00000000000..18a5ce78792 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr70243.c +@@ -0,0 +1,41 @@ ++/* { dg-do compile */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mvsx" } */ ++ ++/* PR 70423, Make sure we don't generate vmaddfp or vnmsubfp. These ++ instructions have different rounding modes than the VSX instructions ++ xvmaddsp and xvnmsubsp. These tests are written where the 3 inputs and ++ target are all separate registers. Because vmaddfp and vnmsubfp are no ++ longer generated the compiler will have to generate an xsmaddsp or xsnmsubsp ++ instruction followed by a move operation. */ ++ ++#include ++ ++vector float ++do_add1 (vector float dummy, vector float a, vector float b, vector float c) ++{ ++ return (a * b) + c; ++} ++ ++vector float ++do_nsub1 (vector float dummy, vector float a, vector float b, vector float c) ++{ ++ return -((a * b) - c); ++} ++ ++vector float ++do_add2 (vector float dummy, vector float a, vector float b, vector float c) ++{ ++ return vec_madd (a, b, c); ++} ++ ++vector float ++do_nsub2 (vector float dummy, vector float a, vector float b, vector float c) ++{ ++ return vec_nmsub (a, b, c); ++} ++ ++/* { dg-final { scan-assembler {\mxvmadd[am]sp\M} } } */ ++/* { dg-final { scan-assembler {\mxvnmsub[am]sp\M} } } */ ++/* { dg-final { scan-assembler-not {\mvmaddfp\M} } } */ ++/* { dg-final { scan-assembler-not {\mvnmsubfp\M} } } */ +diff --git a/gcc/testsuite/gcc.target/powerpc/pr96762.c b/gcc/testsuite/gcc.target/powerpc/pr96762.c +new file mode 100644 +index 00000000000..a59deb42738 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr96762.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ ++ ++/* Verify there is no ICE on ilp32 env. */ ++ ++extern void foo (char *); ++ ++void ++bar (void) ++{ ++ char zj[] = "XXXXXXXXXXXXXXXX"; ++ foo (zj); ++} +diff --git a/gcc/testsuite/gdc.dg/pr108842.d b/gcc/testsuite/gdc.dg/pr108842.d +new file mode 100644 +index 00000000000..5aae9e5000d +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/pr108842.d +@@ -0,0 +1,4 @@ ++// { dg-do compile } ++// { dg-options "-fno-rtti" } ++module object; ++enum int[] x = [0, 1, 2]; +diff --git a/gcc/testsuite/gdc.dg/pr110359.d b/gcc/testsuite/gdc.dg/pr110359.d +new file mode 100644 +index 00000000000..bf69201d9a5 +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/pr110359.d +@@ -0,0 +1,22 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110359 ++// { dg-do compile } ++// { dg-options "-fdump-tree-original" } ++double pow(in double x, in ulong p) ++{ ++ import gcc.builtins : __builtin_expect; ++ if (__builtin_expect(p == 0, false)) ++ return 1; ++ if (__builtin_expect(p == 1, false)) ++ return x; ++ ++ double s = x; ++ double v = 1; ++ for (ulong i = p; i > 1; i >>= 1) ++ { ++ v = (i & 0x1) ? s * v : v; ++ s = s * s; ++ } ++ return v * s; ++} ++// { dg-final { scan-tree-dump "if \\(__builtin_expect \\(p == 0, 0\\) != 0\\)" "original" } } ++// { dg-final { scan-tree-dump "if \\(__builtin_expect \\(p == 1, 0\\) != 0\\)" "original" } } +diff --git a/gcc/testsuite/gdc.dg/pr110514a.d b/gcc/testsuite/gdc.dg/pr110514a.d +new file mode 100644 +index 00000000000..46e370527d3 +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/pr110514a.d +@@ -0,0 +1,9 @@ ++// { dg-do "compile" } ++// { dg-options "-O -fdump-tree-optimized" } ++immutable uint[] imm_arr = [1,2,3]; ++int test_imm(immutable uint[] ptr) ++{ ++ return imm_arr[2] == 3 ? 123 : 456; ++} ++// { dg-final { scan-assembler-not "_d_arraybounds_indexp" } } ++// { dg-final { scan-tree-dump "return 123;" optimized } } +diff --git a/gcc/testsuite/gdc.dg/pr110514b.d b/gcc/testsuite/gdc.dg/pr110514b.d +new file mode 100644 +index 00000000000..86aeb485c34 +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/pr110514b.d +@@ -0,0 +1,8 @@ ++// { dg-do "compile" } ++// { dg-options "-O" } ++immutable uint[] imm_ctor_arr; ++int test_imm_ctor(immutable uint[] ptr) ++{ ++ return imm_ctor_arr[2] == 3; ++} ++// { dg-final { scan-assembler "_d_arraybounds_indexp" } } +diff --git a/gcc/testsuite/gdc.dg/pr110514c.d b/gcc/testsuite/gdc.dg/pr110514c.d +new file mode 100644 +index 00000000000..94779e123a4 +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/pr110514c.d +@@ -0,0 +1,8 @@ ++// { dg-do "compile" } ++// { dg-options "-O" } ++const uint[] cst_arr = [1,2,3]; ++int test_cst(const uint[] ptr) ++{ ++ return cst_arr[2] == 3; ++} ++// { dg-final { scan-assembler "_d_arraybounds_indexp" } } +diff --git a/gcc/testsuite/gdc.dg/pr110514d.d b/gcc/testsuite/gdc.dg/pr110514d.d +new file mode 100644 +index 00000000000..56e9a3139ea +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/pr110514d.d +@@ -0,0 +1,8 @@ ++// { dg-do "compile" } ++// { dg-options "-O" } ++const uint[] cst_ctor_arr; ++int test_cst_ctor(const uint[] ptr) ++{ ++ return cst_ctor_arr[2] == 3; ++} ++// { dg-final { scan-assembler "_d_arraybounds_indexp" } } +diff --git a/gcc/testsuite/gdc.dg/pr110712.d b/gcc/testsuite/gdc.dg/pr110712.d +new file mode 100644 +index 00000000000..ed24b6c90cc +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/pr110712.d +@@ -0,0 +1,23 @@ ++// { dg-do compile { target { { i?86-*-* x86_64-*-* } && lp64 } } } ++import gcc.builtins : va_list = __builtin_va_list; ++ ++void argpass(va_list *ap); ++ ++void pr110712a(va_list ap) ++{ ++ argpass(&ap); // { dg-error "cannot convert parameter" } ++} ++ ++void pr110712b(va_list ap) ++{ ++ va_list ap2 = ap; // { dg-error "cannot convert parameter" } ++} ++ ++struct pr110712c ++{ ++ this(va_list ap) ++ { ++ this.ap = ap; // { dg-error "cannot convert parameter" } ++ } ++ va_list ap; ++} +diff --git a/gcc/testsuite/gdc.dg/pr110959.d b/gcc/testsuite/gdc.dg/pr110959.d +new file mode 100644 +index 00000000000..b1da90fad83 +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/pr110959.d +@@ -0,0 +1,32 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110959 ++// { dg-do compile } ++class ArsdExceptionBase : object.Exception { ++ this(string operation, string file = __FILE__, size_t line = __LINE__, Throwable next = null) { ++ super(operation, file, line, next); ++ } ++} ++ ++template ArsdException(alias Type, DataTuple...) { ++ static if(DataTuple.length) ++ alias Parent = ArsdException!(Type, DataTuple[0 .. $-1]); ++ else ++ alias Parent = ArsdExceptionBase; ++ ++ class ArsdException : Parent { ++ DataTuple data; ++ ++ this(DataTuple data, string file = __FILE__, size_t line = __LINE__) { ++ this.data = data; ++ static if(is(Parent == ArsdExceptionBase)) ++ super(null, file, line); ++ else ++ super(data[0 .. $-1], file, line); ++ } ++ ++ static opCall(R...)(R r, string file = __FILE__, size_t line = __LINE__) { ++ return new ArsdException!(Type, DataTuple, R)(r, file, line); ++ } ++ } ++} ++ ++__gshared pr110959 = ArsdException!"Test"(4, "four"); +diff --git a/gcc/testsuite/gdc.dg/pr112270.d b/gcc/testsuite/gdc.dg/pr112270.d +new file mode 100644 +index 00000000000..591c798fddd +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/pr112270.d +@@ -0,0 +1,7 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112270 ++// { dg-do compile } ++class CPPNamespaceDeclaration { } ++bool isNamespaceEqual (CPPNamespaceDeclaration a) ++{ ++ return a ? true : isNamespaceEqual(a); ++} +diff --git a/gcc/testsuite/gdc.dg/pr98277.d b/gcc/testsuite/gdc.dg/pr98277.d +index 0dff142a6ef..c88c735dec8 100644 +--- a/gcc/testsuite/gdc.dg/pr98277.d ++++ b/gcc/testsuite/gdc.dg/pr98277.d +@@ -11,3 +11,14 @@ ref int getSide(Side side, return ref int left, return ref int right) + { + return side == Side.left ? left : right; + } ++ ++enum SideA : int[] ++{ ++ left = [0], ++ right = [1], ++} ++ ++int getSideA(SideA side, ref int left, ref int right) ++{ ++ return side == SideA.left ? left : right; ++} +diff --git a/gcc/testsuite/gdc.dg/torture/pr110516a.d b/gcc/testsuite/gdc.dg/torture/pr110516a.d +new file mode 100644 +index 00000000000..276455ae408 +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/torture/pr110516a.d +@@ -0,0 +1,12 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110516 ++// { dg-do compile } ++// { dg-options "-fno-moduleinfo -fdump-tree-optimized" } ++void fn110516(ubyte* ptr) ++{ ++ import core.volatile : volatileLoad; ++ volatileLoad(ptr); ++ volatileLoad(ptr); ++ volatileLoad(ptr); ++ volatileLoad(ptr); ++} ++// { dg-final { scan-tree-dump-times " ={v} " 4 "optimized" } } +diff --git a/gcc/testsuite/gdc.dg/torture/pr110516b.d b/gcc/testsuite/gdc.dg/torture/pr110516b.d +new file mode 100644 +index 00000000000..b7a67e716a5 +--- /dev/null ++++ b/gcc/testsuite/gdc.dg/torture/pr110516b.d +@@ -0,0 +1,12 @@ ++// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110516 ++// { dg-do compile } ++// { dg-options "-fno-moduleinfo -fdump-tree-optimized" } ++void fn110516(ubyte* ptr) ++{ ++ import core.volatile : volatileStore; ++ volatileStore(ptr, 0); ++ volatileStore(ptr, 0); ++ volatileStore(ptr, 0); ++ volatileStore(ptr, 0); ++} ++// { dg-final { scan-tree-dump-times " ={v} " 4 "optimized" } } +diff --git a/gcc/testsuite/gdc.test/compilable/test23978.d b/gcc/testsuite/gdc.test/compilable/test23978.d +new file mode 100644 +index 00000000000..cc30f728dee +--- /dev/null ++++ b/gcc/testsuite/gdc.test/compilable/test23978.d +@@ -0,0 +1,30 @@ ++// REQUIRED_ARGS: -preview=dip1021 -lowmem ++// https://issues.dlang.org/show_bug.cgi?id=23978 ++ ++// Note: this is a memory corruption bug. ++// Memory returned by `GC.realloc` retains references to old memory in it, ++// mostly because of the smallarray optimization for `Array(T)`. ++// If this fails again, it might not be consistent, so try running it multiple times. ++ ++class LUBench { } ++void lup(ulong , ulong , int , int = 1) ++{ ++ new LUBench; ++} ++void lup_3200(ulong iters, ulong flops) ++{ ++ lup(iters, flops, 3200); ++} ++void raytrace() ++{ ++ struct V ++ { ++ float x, y, z; ++ auto normalize() { } ++ struct Tid { } ++ auto spawnLinked() { } ++ string[] namesByTid; ++ class MessageBox { } ++ auto cross() { } ++ } ++} +diff --git a/gcc/testsuite/gdc.test/runnable/test23010.d b/gcc/testsuite/gdc.test/runnable/test23010.d +new file mode 100644 +index 00000000000..1cbacfc9279 +--- /dev/null ++++ b/gcc/testsuite/gdc.test/runnable/test23010.d +@@ -0,0 +1,43 @@ ++// https://issues.dlang.org/show_bug.cgi?id=23010 ++ ++alias AliasSeq(T...) = T; ++ ++mixin template faz() { ++ alias T = AliasSeq!(int); ++ T bar = 12345; ++ ++ void write1() { ++ assert(bar[0] == 12345); ++ } ++ ++ AliasSeq!(string, float) foo = AliasSeq!("qwerty", 1.25f); ++ ++ void write2() { ++ assert(foo == AliasSeq!("qwerty", 1.25f)); ++ foo = AliasSeq!("asdfg", 2.5f); // this even crashed before ++ assert(foo == AliasSeq!("asdfg", 2.5f)); ++ } ++} ++ ++void main() { ++ mixin faz!(); ++ write1; ++ write2; ++ fun; ++} ++ ++// Testing static symbol generation ('toobj.d' changes) ++ ++static AliasSeq!(int, string) tup; ++ ++void fun() ++{ ++ auto v = tup; ++ ++ struct S(T...) { ++ static T b; ++ } ++ ++ alias T = S!(int, float); ++ auto p = T.b; ++} +diff --git a/gcc/testsuite/gfortran.dg/deferred_character_37.f90 b/gcc/testsuite/gfortran.dg/deferred_character_37.f90 +new file mode 100644 +index 00000000000..8a5a8c5daf8 +--- /dev/null ++++ b/gcc/testsuite/gfortran.dg/deferred_character_37.f90 +@@ -0,0 +1,88 @@ ++! { dg-do run } ++! PR fortran/95947 ++! PR fortran/110658 ++! ++! Test deferred-length character arguments to selected intrinsics ++! that may return a character result of same length as first argument: ++! CSHIFT, EOSHIFT, MAXVAL, MERGE, MINVAL, PACK, SPREAD, TRANSPOSE, UNPACK ++ ++program p ++ implicit none ++ call pr95947 () ++ call pr110658 () ++ call s () ++ ++contains ++ ++ subroutine pr95947 ++ character(len=:), allocatable :: m(:) ++ ++ m = [ character(len=10) :: 'ape','bat','cat','dog','eel','fly','gnu'] ++ m = pack (m, mask=(m(:)(2:2) == 'a')) ++ ++! print *, "m = '", m,"' ", "; expected is ['bat','cat']" ++ if (.not. all (m == ['bat','cat'])) stop 1 ++ ++! print *, "size(m) = ", size(m), "; expected is 2" ++ if (size (m) /= 2) stop 2 ++ ++! print *, "len(m) = ", len(m), "; expected is 10" ++ if (len (m) /= 10) stop 3 ++ ++! print *, "len_trim(m) = ", len_trim(m), "; expected is 3 3" ++ if (.not. all (len_trim(m) == [3,3])) stop 4 ++ end ++ ++ subroutine pr110658 ++ character(len=:), allocatable :: array(:), array2(:,:) ++ character(len=:), allocatable :: res, res1(:), res2(:) ++ ++ array = ["bb", "aa", "cc"] ++ ++ res = minval (array) ++ if (res /= "aa") stop 11 ++ ++ res = maxval (array, mask=[.true.,.true.,.false.]) ++ if (res /= "bb") stop 12 ++ ++ res1 = cshift (array, 1) ++ if (any (res1 /= ["aa","cc","bb"])) stop 13 ++ ++ res2 = eoshift (res1, -1) ++ if (any (res2 /= [" ", "aa", "cc"])) stop 14 ++ ++ res2 = pack (array, mask=[.true.,.false.,.true.]) ++ if (any (res2 /= ["bb","cc"])) stop 15 ++ ++ res2 = unpack (res2, mask=[.true.,.false.,.true.], field="aa") ++ if (any (res2 /= array)) stop 16 ++ ++ res2 = merge (res2, array, [.true.,.false.,.true.]) ++ if (any (res2 /= array)) stop 17 ++ ++ array2 = spread (array, dim=2, ncopies=2) ++ array2 = transpose (array2) ++ if (any (shape (array2) /= [2,3])) stop 18 ++ if (any (array2(2,:) /= array)) stop 19 ++ end ++ ++ subroutine s ++ character(:), allocatable :: array1(:), array2(:) ++ array1 = ["aa","cc","bb"] ++ array2 = copy (array1) ++ if (any (array1 /= array2)) stop 20 ++ end ++ ++ function copy (arg) result (res) ++ character(:), allocatable :: res(:) ++ character(*), intent(in) :: arg(:) ++ integer :: i, k, n ++ k = len (arg) ++ n = size (arg) ++ allocate (character(k) :: res(n)) ++ do i = 1, n ++ res(i) = arg(i) ++ end do ++ end ++ ++end +diff --git a/gcc/testsuite/gfortran.dg/findloc_10.f90 b/gcc/testsuite/gfortran.dg/findloc_10.f90 +new file mode 100644 +index 00000000000..4d5ecd2306a +--- /dev/null ++++ b/gcc/testsuite/gfortran.dg/findloc_10.f90 +@@ -0,0 +1,13 @@ ++! { dg-do run } ++! { dg-options "-fdump-tree-original" } ++! PR fortran/110288 - FINDLOC and deferred-length character arguments ++ ++program test ++ character(len=:), allocatable :: array(:) ++ character(len=:), allocatable :: value ++ array = ["bb", "aa"] ++ value = "aa" ++ if (findloc (array, value, dim=1) /= 2) stop 1 ++end program test ++ ++! { dg-final { scan-tree-dump "_gfortran_findloc2_s1 \\(.*, \\.array, \\.value\\)" "original" } } +diff --git a/gcc/testsuite/gfortran.dg/findloc_9.f90 b/gcc/testsuite/gfortran.dg/findloc_9.f90 +new file mode 100644 +index 00000000000..05974476cb3 +--- /dev/null ++++ b/gcc/testsuite/gfortran.dg/findloc_9.f90 +@@ -0,0 +1,19 @@ ++! { dg-do compile } ++! { dg-options "-fdump-tree-original" } ++! PR fortran/110585 - simplification of FINDLOC for constant complex arguments ++ ++program mvce ++ implicit none ++ integer, parameter :: a(*) = findloc([(1.,0.),(2.,1.)], (2.,0.)) ++ integer, parameter :: b(*) = findloc([(1.,0.),(2.,1.)], (2.,0.), back=.true.) ++ integer, parameter :: c(*) = findloc([(1.,0.),(2.,1.)], (2.,1.)) ++ integer, parameter :: d(*) = findloc([(1.,0.),(2.,1.)], (2.,1.), back=.true.) ++ integer, parameter :: e = findloc([(1.,0.),(2.,1.)], (2.,1.), dim=1) ++ if (a(1) /= 0) stop 1 ++ if (b(1) /= 0) stop 2 ++ if (c(1) /= 2) stop 3 ++ if (d(1) /= 2) stop 4 ++ if (e /= 2) stop 5 ++end ++ ++! { dg-final { scan-tree-dump-not "_gfortran_stop_numeric" "original" } } +diff --git a/gcc/testsuite/gfortran.dg/implied_do_io_8.f90 b/gcc/testsuite/gfortran.dg/implied_do_io_8.f90 +new file mode 100644 +index 00000000000..c66a0f6fde6 +--- /dev/null ++++ b/gcc/testsuite/gfortran.dg/implied_do_io_8.f90 +@@ -0,0 +1,18 @@ ++! { dg-do run } ++! { dg-additional-options "-fcheck=bounds" } ++! PR fortran/111837 - out of bounds access with front-end optimization ++ ++program implied_do_bug ++ implicit none ++ integer :: i,j,k ++ real :: arr(1,1,1) ++ integer :: ni(1) ++ ni(1) = 1 ++ arr = 1 ++ write(*,*) (((arr(i,j,k), i=1,ni(k)), k=1,1), j=1,1) ++ write(*,*) (((arr(i,j,k), i=1,ni(k)), j=1,1), k=1,1) ++ write(*,*) (((arr(k,i,j), i=1,ni(k)), k=1,1), j=1,1) ++ write(*,*) (((arr(k,i,j), i=1,ni(k)), j=1,1), k=1,1) ++ write(*,*) (((arr(j,k,i), i=1,ni(k)), k=1,1), j=1,1) ++ write(*,*) (((arr(j,k,i), i=1,ni(k)), j=1,1), k=1,1) ++end +diff --git a/gcc/testsuite/gfortran.dg/pr107397.f90 b/gcc/testsuite/gfortran.dg/pr107397.f90 +new file mode 100644 +index 00000000000..fd59bf16007 +--- /dev/null ++++ b/gcc/testsuite/gfortran.dg/pr107397.f90 +@@ -0,0 +1,9 @@ ++!{ dg-do compile } ++! ++program p ++ type t ++ real :: a = 1.0 ++ end type ++ type(t), parameter :: x = z'1' ! { dg-error "incompatible with a BOZ" } ++ x%a = x%a + 2 ! { dg-error "has no IMPLICIT type" } ++end +diff --git a/gcc/testsuite/gfortran.dg/pr111880.f90 b/gcc/testsuite/gfortran.dg/pr111880.f90 +new file mode 100644 +index 00000000000..c0cd98a93d4 +--- /dev/null ++++ b/gcc/testsuite/gfortran.dg/pr111880.f90 +@@ -0,0 +1,22 @@ ++! { dg-do compile } ++! { dg-options "-std=f2018" } ++! PR fortran/111880 - redundant warning of obsolescent COMMON with submodule ++ ++module third_party_module ++ integer :: some_param ++ common /not_my_code/ some_param ! { dg-warning "COMMON block" } ++end module third_party_module ++ ++module foo ++ use third_party_module ++ interface ++ module subroutine bar() ++ end subroutine bar ++ end interface ++end module foo ++ ++submodule (foo) foo_submod ! We do not need a warning here! ++contains ++ module procedure bar ++ end procedure bar ++end submodule foo_submod +diff --git a/gcc/testsuite/gfortran.dg/ptr-func-5.f90 b/gcc/testsuite/gfortran.dg/ptr-func-5.f90 +new file mode 100644 +index 00000000000..05fd56703ca +--- /dev/null ++++ b/gcc/testsuite/gfortran.dg/ptr-func-5.f90 +@@ -0,0 +1,39 @@ ++! { dg-do compile } ++! PR fortran/109846 ++! CLASS pointer function result in variable definition context ++ ++module foo ++ implicit none ++ type :: parameter_list ++ contains ++ procedure :: sublist, sublist_nores ++ end type ++contains ++ function sublist (this) result (slist) ++ class(parameter_list), intent(inout) :: this ++ class(parameter_list), pointer :: slist ++ allocate (slist) ++ end function ++ function sublist_nores (this) ++ class(parameter_list), intent(inout) :: this ++ class(parameter_list), pointer :: sublist_nores ++ allocate (sublist_nores) ++ end function ++end module ++ ++program example ++ use foo ++ implicit none ++ type(parameter_list) :: plist ++ call sub1 (plist%sublist()) ++ call sub1 (plist%sublist_nores()) ++ call sub2 (plist%sublist()) ++ call sub2 (plist%sublist_nores()) ++contains ++ subroutine sub1 (plist) ++ type(parameter_list), intent(inout) :: plist ++ end subroutine ++ subroutine sub2 (plist) ++ type(parameter_list) :: plist ++ end subroutine ++end program +diff --git a/gcc/testsuite/gfortran.dg/select_rank_6.f90 b/gcc/testsuite/gfortran.dg/select_rank_6.f90 +new file mode 100644 +index 00000000000..d0121777bb5 +--- /dev/null ++++ b/gcc/testsuite/gfortran.dg/select_rank_6.f90 +@@ -0,0 +1,48 @@ ++! { dg-do compile } ++! PR fortran/100607 - fix diagnostics for SELECT RANK ++! Contributed by T.Burnus ++ ++program p ++ implicit none ++ integer, allocatable :: A(:,:,:) ++ ++ allocate(a(5:6,-2:2, 99:100)) ++ call foo(a) ++ call bar(a) ++ ++contains ++ ++ subroutine foo(x) ++ integer, allocatable :: x(..) ++ if (rank(x) /= 3) stop 1 ++ if (any (lbound(x) /= [5, -2, 99])) stop 2 ++ ++ select rank (x) ++ rank(3) ++ if (any (lbound(x) /= [5, -2, 99])) stop 3 ++ end select ++ ++ select rank (x) ! { dg-error "pointer or allocatable selector at .2." } ++ rank(*) ! { dg-error "pointer or allocatable selector at .2." } ++ if (rank(x) /= 1) stop 4 ++ if (lbound(x, 1) /= 1) stop 5 ++ end select ++ end ++ ++ subroutine bar(x) ++ integer :: x(..) ++ if (rank(x) /= 3) stop 6 ++ if (any (lbound(x) /= 1)) stop 7 ++ ++ select rank (x) ++ rank(3) ++ if (any (lbound(x) /= 1)) stop 8 ++ end select ++ ++ select rank (x) ++ rank(*) ++ if (rank(x) /= 1) stop 9 ++ if (lbound(x, 1) /= 1) stop 10 ++ end select ++ end ++end +diff --git a/gcc/testsuite/gnat.dg/opt102.adb b/gcc/testsuite/gnat.dg/opt102.adb +new file mode 100644 +index 00000000000..2b5bec54c3d +--- /dev/null ++++ b/gcc/testsuite/gnat.dg/opt102.adb +@@ -0,0 +1,10 @@ ++-- { dg-do run } ++-- { dg-options "-O2 -gnata" } ++ ++with Opt102_Pkg; use Opt102_Pkg; ++ ++procedure Opt102 is ++ I, F : aliased Integer; ++begin ++ I := Get (Two, F'Access, null); ++end; +diff --git a/gcc/testsuite/gnat.dg/opt102_pkg.adb b/gcc/testsuite/gnat.dg/opt102_pkg.adb +new file mode 100644 +index 00000000000..09c338d0517 +--- /dev/null ++++ b/gcc/testsuite/gnat.dg/opt102_pkg.adb +@@ -0,0 +1,12 @@ ++package body Opt102_Pkg is ++ ++ function Get (E : Enum; F, M : access Integer) return Integer is ++ begin ++ case E is ++ when One => return 0; ++ when Two => return F.all; ++ when Three => return M.all; ++ end case; ++ end; ++ ++end Opt102_Pkg; +diff --git a/gcc/testsuite/gnat.dg/opt102_pkg.ads b/gcc/testsuite/gnat.dg/opt102_pkg.ads +new file mode 100644 +index 00000000000..7afc3fe6ac7 +--- /dev/null ++++ b/gcc/testsuite/gnat.dg/opt102_pkg.ads +@@ -0,0 +1,10 @@ ++package Opt102_Pkg is ++ ++ type Enum is (One, Two, Three); ++ ++ function Get (E : Enum; F, M : access Integer) return Integer ++ with Pre => (E = One) = (F = null and M = null) and ++ (E = Two) = (F /= null) and ++ (E = Three) = (M /= null); ++ ++end Opt102_Pkg; +diff --git a/gcc/testsuite/gnat.dg/varsize4.adb b/gcc/testsuite/gnat.dg/varsize4.adb +new file mode 100644 +index 00000000000..0ea5135b7fc +--- /dev/null ++++ b/gcc/testsuite/gnat.dg/varsize4.adb +@@ -0,0 +1,20 @@ ++-- { dg-do compile } ++ ++package body Varsize4 is ++ ++ function Func (Bytes_Read : out Natural) return Arr is ++ Ret : Arr := (others => False); ++ begin ++ Bytes_Read := 0; ++ return Ret; ++ end; ++ ++ function Get return Natural is ++ Data : Arr; ++ Bytes : Natural; ++ begin ++ Data := Func (Bytes); ++ return Bytes; ++ end; ++ ++end Varsize4; +diff --git a/gcc/testsuite/gnat.dg/varsize4.ads b/gcc/testsuite/gnat.dg/varsize4.ads +new file mode 100644 +index 00000000000..62b673fc16b +--- /dev/null ++++ b/gcc/testsuite/gnat.dg/varsize4.ads +@@ -0,0 +1,9 @@ ++with Varsize4_Pkg; ++ ++package Varsize4 is ++ ++ type Arr is array (1 .. Varsize4_Pkg.F) of Boolean; ++ ++ function Get return Natural; ++ ++end Varsize4; +diff --git a/gcc/testsuite/gnat.dg/varsize4_pkg.ads b/gcc/testsuite/gnat.dg/varsize4_pkg.ads +new file mode 100644 +index 00000000000..e07a6b002dc +--- /dev/null ++++ b/gcc/testsuite/gnat.dg/varsize4_pkg.ads +@@ -0,0 +1,5 @@ ++package Varsize4_Pkg is ++ ++ function F return Natural; ++ ++end Varsize4_Pkg; +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index c858bd93b8e..1eaa034f5f4 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -10597,7 +10597,7 @@ proc check_effective_target_aarch64_tiny { } { + # various architecture extensions via the .arch_extension pseudo-op. + + foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve" +- "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" } { ++ "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64" } { + eval [string map [list FUNC $aarch64_ext] { + proc check_effective_target_aarch64_asm_FUNC_ok { } { + if { [istarget aarch64*-*-*] } { +@@ -11819,6 +11819,46 @@ proc check_effective_target_o_flag_in_section { } { + }] + } + ++# Return 1 if the given assembler supports hardware transactional memory ++# instructions with machine type Power10, 0 otherwise. Cache the result. ++ ++proc check_effective_target_powerpc_as_p10_htm { } { ++ global tool ++ global GCC_UNDER_TEST ++ ++ # Need auto-host.h to check linker support. ++ if { ![file exists ../../auto-host.h ] } { ++ return 0 ++ } ++ ++ return [check_cached_effective_target powerpc_as_p10_htm { ++ ++ set src pie[pid].c ++ set obj pie[pid].o ++ ++ set f [open $src "w"] ++ puts $f "#include \"../../auto-host.h\"" ++ puts $f "#if HAVE_AS_POWER10_HTM == 0" ++ puts $f "# error Assembler does not support htm insns with power10." ++ puts $f "#endif" ++ close $f ++ ++ verbose "check_effective_target_powerpc_as_p10_htm compiling testfile $src" 2 ++ set lines [${tool}_target_compile $src $obj object ""] ++ ++ file delete $src ++ file delete $obj ++ ++ if [string match "" $lines] then { ++ verbose "check_effective_target_powerpc_as_p10_htm testfile compilation passed" 2 ++ return 1 ++ } else { ++ verbose "check_effective_target_powerpc_as_p10_htm testfile compilation failed" 2 ++ return 0 ++ } ++ }] ++} ++ + # return 1 if LRA is supported. + + proc check_effective_target_lra { } { +diff --git a/gcc/tree-object-size.cc b/gcc/tree-object-size.cc +index 91db1238f50..31a82d6ac6e 100644 +--- a/gcc/tree-object-size.cc ++++ b/gcc/tree-object-size.cc +@@ -771,21 +771,33 @@ alloc_object_size (const gcall *call, int object_size_type) + arg2 = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (p)))-1; + } + else if (gimple_call_builtin_p (call, BUILT_IN_NORMAL) +- && callfn && ALLOCA_FUNCTION_CODE_P (DECL_FUNCTION_CODE (callfn))) +- arg1 = 0; ++ && callfn ++ && ALLOCA_FUNCTION_CODE_P (DECL_FUNCTION_CODE (callfn))) ++ arg1 = 0; + + /* Non-const arguments are OK here, let the caller handle constness. */ +- if (arg1 < 0 || arg1 >= (int) gimple_call_num_args (call) +- || arg2 >= (int) gimple_call_num_args (call)) ++ if (arg1 < 0 ++ || (unsigned) arg1 >= gimple_call_num_args (call) ++ || (arg2 >= 0 && (unsigned) arg2 >= gimple_call_num_args (call))) + return size_unknown (object_size_type); + ++ tree targ1 = gimple_call_arg (call, arg1); ++ if (!INTEGRAL_TYPE_P (TREE_TYPE (targ1)) ++ || TYPE_PRECISION (TREE_TYPE (targ1)) > TYPE_PRECISION (sizetype)) ++ return size_unknown (object_size_type); ++ targ1 = fold_convert (sizetype, targ1); + tree bytes = NULL_TREE; + if (arg2 >= 0) +- bytes = size_binop (MULT_EXPR, +- fold_convert (sizetype, gimple_call_arg (call, arg1)), +- fold_convert (sizetype, gimple_call_arg (call, arg2))); +- else if (arg1 >= 0) +- bytes = fold_convert (sizetype, gimple_call_arg (call, arg1)); ++ { ++ tree targ2 = gimple_call_arg (call, arg2); ++ if (!INTEGRAL_TYPE_P (TREE_TYPE (targ2)) ++ || TYPE_PRECISION (TREE_TYPE (targ2)) > TYPE_PRECISION (sizetype)) ++ return size_unknown (object_size_type); ++ targ2 = fold_convert (sizetype, targ2); ++ bytes = size_binop (MULT_EXPR, targ1, targ2); ++ } ++ else ++ bytes = targ1; + + return bytes ? bytes : size_unknown (object_size_type); + } +diff --git a/gcc/tree-scalar-evolution.cc b/gcc/tree-scalar-evolution.cc +index 44157265ce8..25d6b346396 100644 +--- a/gcc/tree-scalar-evolution.cc ++++ b/gcc/tree-scalar-evolution.cc +@@ -3282,7 +3282,8 @@ simple_iv_with_niters (class loop *wrto_loop, class loop *use_loop, + + type = TREE_TYPE (iv->base); + e = TREE_OPERAND (iv->base, 0); +- if (TREE_CODE (e) != PLUS_EXPR ++ if (!tree_nop_conversion_p (type, TREE_TYPE (e)) ++ || TREE_CODE (e) != PLUS_EXPR + || TREE_CODE (TREE_OPERAND (e, 1)) != INTEGER_CST + || !tree_int_cst_equal (iv->step, + fold_convert (type, TREE_OPERAND (e, 1)))) +diff --git a/gcc/tree-ssa-ccp.cc b/gcc/tree-ssa-ccp.cc +index 29661884b92..42a02dccaeb 100644 +--- a/gcc/tree-ssa-ccp.cc ++++ b/gcc/tree-ssa-ccp.cc +@@ -1552,6 +1552,8 @@ bit_value_binop (enum tree_code code, signop sgn, int width, + *mask = wi::lrotate (r1mask, shift, width); + *val = wi::lrotate (r1val, shift, width); + } ++ *mask = wi::ext (*mask, width, sgn); ++ *val = wi::ext (*val, width, sgn); + } + } + else if (wi::ltu_p (r2val | r2mask, width) +@@ -1593,8 +1595,8 @@ bit_value_binop (enum tree_code code, signop sgn, int width, + /* Accumulate the result. */ + res_mask |= tmp_mask | (res_val ^ tmp_val); + } +- *val = wi::bit_and_not (res_val, res_mask); +- *mask = res_mask; ++ *val = wi::ext (wi::bit_and_not (res_val, res_mask), width, sgn); ++ *mask = wi::ext (res_mask, width, sgn); + } + break; + +diff --git a/gcc/tree-ssa-loop-im.cc b/gcc/tree-ssa-loop-im.cc +index 162186cc481..831ede23bcf 100644 +--- a/gcc/tree-ssa-loop-im.cc ++++ b/gcc/tree-ssa-loop-im.cc +@@ -1648,11 +1648,21 @@ gather_mem_refs_stmt (class loop *loop, gimple *stmt) + unshare_expr (mem_base)); + if (TYPE_ALIGN (ref_type) != ref_align) + ref_type = build_aligned_type (ref_type, ref_align); +- (*slot)->mem.ref ++ tree new_ref + = fold_build2 (MEM_REF, ref_type, tmp, + build_int_cst (ref_alias_type, mem_off)); + if ((*slot)->mem.volatile_p) +- TREE_THIS_VOLATILE ((*slot)->mem.ref) = 1; ++ TREE_THIS_VOLATILE (new_ref) = 1; ++ (*slot)->mem.ref = new_ref; ++ /* Make sure the recorded base and offset are consistent ++ with the newly built ref. */ ++ if (TREE_CODE (TREE_OPERAND (new_ref, 0)) == ADDR_EXPR) ++ ; ++ else ++ { ++ (*slot)->mem.base = new_ref; ++ (*slot)->mem.offset = 0; ++ } + gcc_checking_assert (TREE_CODE ((*slot)->mem.ref) == MEM_REF + && is_gimple_mem_ref_addr + (TREE_OPERAND ((*slot)->mem.ref, +diff --git a/gcc/tree-ssa-loop-ivcanon.cc b/gcc/tree-ssa-loop-ivcanon.cc +index e2ac2044741..408916c7de0 100644 +--- a/gcc/tree-ssa-loop-ivcanon.cc ++++ b/gcc/tree-ssa-loop-ivcanon.cc +@@ -1487,15 +1487,16 @@ tree_unroll_loops_completely (bool may_increase_size, bool unroll_outer) + } + BITMAP_FREE (fathers); + ++ /* Clean up the information about numbers of iterations, since ++ complete unrolling might have invalidated it. */ ++ scev_reset (); ++ + /* This will take care of removing completely unrolled loops + from the loop structures so we can continue unrolling now + innermost loops. */ + if (cleanup_tree_cfg ()) + update_ssa (TODO_update_ssa_only_virtuals); + +- /* Clean up the information about numbers of iterations, since +- complete unrolling might have invalidated it. */ +- scev_reset (); + if (flag_checking && loops_state_satisfies_p (LOOP_CLOSED_SSA)) + verify_loop_closed_ssa (true); + } +diff --git a/gcc/tree-ssa-loop-ivopts.cc b/gcc/tree-ssa-loop-ivopts.cc +index 59e8df1b5a9..eb4d8388906 100644 +--- a/gcc/tree-ssa-loop-ivopts.cc ++++ b/gcc/tree-ssa-loop-ivopts.cc +@@ -7616,7 +7616,22 @@ rewrite_use_address (struct ivopts_data *data, + true, GSI_SAME_STMT); + } + else +- copy_ref_info (ref, *use->op_p); ++ { ++ /* When we end up confused enough and have no suitable base but ++ stuffed everything to index2 use a LEA for the address and ++ create a plain MEM_REF to avoid basing a memory reference ++ on address zero which create_mem_ref_raw does as fallback. */ ++ if (TREE_CODE (ref) == TARGET_MEM_REF ++ && TMR_INDEX2 (ref) != NULL_TREE ++ && integer_zerop (TREE_OPERAND (ref, 0))) ++ { ++ ref = fold_build1 (ADDR_EXPR, TREE_TYPE (TREE_OPERAND (ref, 0)), ref); ++ ref = force_gimple_operand_gsi (&bsi, ref, true, NULL_TREE, ++ true, GSI_SAME_STMT); ++ ref = build2 (MEM_REF, type, ref, build_zero_cst (alias_ptr_type)); ++ } ++ copy_ref_info (ref, *use->op_p); ++ } + + *use->op_p = ref; + } +diff --git a/gcc/tree-ssa-loop-unswitch.cc b/gcc/tree-ssa-loop-unswitch.cc +index 2927f308234..a9be87c2330 100644 +--- a/gcc/tree-ssa-loop-unswitch.cc ++++ b/gcc/tree-ssa-loop-unswitch.cc +@@ -839,10 +839,7 @@ hoist_guard (class loop *loop, edge guard) + cond_stmt = as_a (stmt); + extract_true_false_edges_from_block (guard_bb, &te, &fe); + /* Insert guard to PRE_HEADER. */ +- if (!empty_block_p (pre_header)) +- gsi = gsi_last_bb (pre_header); +- else +- gsi = gsi_start_bb (pre_header); ++ gsi = gsi_last_bb (pre_header); + /* Create copy of COND_STMT. */ + new_cond_stmt = gimple_build_cond (gimple_cond_code (cond_stmt), + gimple_cond_lhs (cond_stmt), +diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc +index 98134b5d3ad..e2ceba8819e 100644 +--- a/gcc/tree-ssa-pre.cc ++++ b/gcc/tree-ssa-pre.cc +@@ -4216,6 +4216,7 @@ compute_avail (function *fun) + else + { + ref->set = 0; ++ ref->base_set = 0; + if (ref1->opcode == MEM_REF) + ref1->op0 + = wide_int_to_tree (ptr_type_node, +diff --git a/gcc/tree-ssa-reassoc.cc b/gcc/tree-ssa-reassoc.cc +index e3d521e3267..1863d4e361a 100644 +--- a/gcc/tree-ssa-reassoc.cc ++++ b/gcc/tree-ssa-reassoc.cc +@@ -2101,12 +2101,24 @@ undistribute_bitref_for_vector (enum tree_code opcode, + { + sum = build_and_add_sum (vec_type, sum_vec, + valid_vecs[i + 1], opcode); ++ /* Update the operands only after build_and_add_sum, ++ so that we don't have to repeat the placement algorithm ++ of build_and_add_sum. */ ++ if (sum_vec == tvec ++ && !useless_type_conversion_p (vec_type, TREE_TYPE (sum_vec))) ++ { ++ gimple_stmt_iterator gsi = gsi_for_stmt (sum); ++ tree vce = build1 (VIEW_CONVERT_EXPR, vec_type, sum_vec); ++ tree lhs = make_ssa_name (vec_type); ++ gimple *g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, vce); ++ gimple_set_uid (g, gimple_uid (sum)); ++ gsi_insert_before (&gsi, g, GSI_NEW_STMT); ++ gimple_assign_set_rhs1 (sum, lhs); ++ update_stmt (sum); ++ } + if (!useless_type_conversion_p (vec_type, + TREE_TYPE (valid_vecs[i + 1]))) + { +- /* Update the operands only after build_and_add_sum, +- so that we don't have to repeat the placement algorithm +- of build_and_add_sum. */ + gimple_stmt_iterator gsi = gsi_for_stmt (sum); + tree vce = build1 (VIEW_CONVERT_EXPR, vec_type, + valid_vecs[i + 1]); +@@ -2115,15 +2127,6 @@ undistribute_bitref_for_vector (enum tree_code opcode, + gimple_set_uid (g, gimple_uid (sum)); + gsi_insert_before (&gsi, g, GSI_NEW_STMT); + gimple_assign_set_rhs2 (sum, lhs); +- if (sum_vec == tvec) +- { +- vce = build1 (VIEW_CONVERT_EXPR, vec_type, sum_vec); +- lhs = make_ssa_name (vec_type); +- g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, vce); +- gimple_set_uid (g, gimple_uid (sum)); +- gsi_insert_before (&gsi, g, GSI_NEW_STMT); +- gimple_assign_set_rhs1 (sum, lhs); +- } + update_stmt (sum); + } + sum_vec = gimple_get_lhs (sum); +diff --git a/gcc/tree-ssa-strlen.cc b/gcc/tree-ssa-strlen.cc +index cb7ccb41d73..c6415c52060 100644 +--- a/gcc/tree-ssa-strlen.cc ++++ b/gcc/tree-ssa-strlen.cc +@@ -3361,7 +3361,8 @@ strlen_pass::handle_builtin_memcpy (built_in_function bcode) + && !integer_zerop (len)) + { + maybe_warn_overflow (stmt, false, len, olddsi, false, true); +- adjust_last_stmt (olddsi, stmt, false); ++ if (tree_fits_uhwi_p (len)) ++ adjust_last_stmt (olddsi, stmt, false); + } + + int idx = get_stridx (src, stmt); +diff --git a/gcc/tree-ssa-structalias.cc b/gcc/tree-ssa-structalias.cc +index 581bdcf5652..d6e664c5727 100644 +--- a/gcc/tree-ssa-structalias.cc ++++ b/gcc/tree-ssa-structalias.cc +@@ -1581,64 +1581,6 @@ unify_nodes (constraint_graph_t graph, unsigned int to, unsigned int from, + bitmap_clear_bit (graph->succs[to], to); + } + +-/* Information needed to compute the topological ordering of a graph. */ +- +-struct topo_info +-{ +- /* sbitmap of visited nodes. */ +- sbitmap visited; +- /* Array that stores the topological order of the graph, *in +- reverse*. */ +- vec topo_order; +-}; +- +- +-/* Initialize and return a topological info structure. */ +- +-static struct topo_info * +-init_topo_info (void) +-{ +- size_t size = graph->size; +- struct topo_info *ti = XNEW (struct topo_info); +- ti->visited = sbitmap_alloc (size); +- bitmap_clear (ti->visited); +- ti->topo_order.create (1); +- return ti; +-} +- +- +-/* Free the topological sort info pointed to by TI. */ +- +-static void +-free_topo_info (struct topo_info *ti) +-{ +- sbitmap_free (ti->visited); +- ti->topo_order.release (); +- free (ti); +-} +- +-/* Visit the graph in topological order, and store the order in the +- topo_info structure. */ +- +-static void +-topo_visit (constraint_graph_t graph, struct topo_info *ti, +- unsigned int n) +-{ +- bitmap_iterator bi; +- unsigned int j; +- +- bitmap_set_bit (ti->visited, n); +- +- if (graph->succs[n]) +- EXECUTE_IF_SET_IN_BITMAP (graph->succs[n], 0, j, bi) +- { +- if (!bitmap_bit_p (ti->visited, j)) +- topo_visit (graph, ti, j); +- } +- +- ti->topo_order.safe_push (n); +-} +- + /* Process a constraint C that represents x = *(y + off), using DELTA as the + starting solution for y. */ + +@@ -1913,19 +1855,56 @@ find_indirect_cycles (constraint_graph_t graph) + scc_visit (graph, &si, i); + } + +-/* Compute a topological ordering for GRAPH, and store the result in the +- topo_info structure TI. */ ++/* Visit the graph in topological order starting at node N, and store the ++ order in TOPO_ORDER using VISITED to indicate visited nodes. */ + + static void +-compute_topo_order (constraint_graph_t graph, +- struct topo_info *ti) ++topo_visit (constraint_graph_t graph, vec &topo_order, ++ sbitmap visited, unsigned int n) ++{ ++ bitmap_iterator bi; ++ unsigned int j; ++ ++ bitmap_set_bit (visited, n); ++ ++ if (graph->succs[n]) ++ EXECUTE_IF_SET_IN_BITMAP (graph->succs[n], 0, j, bi) ++ { ++ unsigned k = find (j); ++ if (!bitmap_bit_p (visited, k)) ++ topo_visit (graph, topo_order, visited, k); ++ } ++ ++ topo_order.quick_push (n); ++} ++ ++/* Compute a topological ordering for GRAPH, and return the result. */ ++ ++static auto_vec ++compute_topo_order (constraint_graph_t graph) + { + unsigned int i; + unsigned int size = graph->size; + ++ auto_sbitmap visited (size); ++ bitmap_clear (visited); ++ ++ /* For the heuristic in add_graph_edge to work optimally make sure to ++ first visit the connected component of the graph containing ++ ESCAPED. Do this by extracting the connected component ++ with ESCAPED and append that to all other components as solve_graph ++ pops from the order. */ ++ auto_vec tail (size); ++ topo_visit (graph, tail, visited, find (escaped_id)); ++ ++ auto_vec topo_order (size); ++ + for (i = 0; i != size; ++i) +- if (!bitmap_bit_p (ti->visited, i) && find (i) == i) +- topo_visit (graph, ti, i); ++ if (!bitmap_bit_p (visited, i) && find (i) == i) ++ topo_visit (graph, topo_order, visited, i); ++ ++ topo_order.splice (tail); ++ return topo_order; + } + + /* Structure used to for hash value numbering of pointer equivalence +@@ -2753,17 +2732,14 @@ solve_graph (constraint_graph_t graph) + while (!bitmap_empty_p (changed)) + { + unsigned int i; +- struct topo_info *ti = init_topo_info (); + stats.iterations++; + + bitmap_obstack_initialize (&iteration_obstack); + +- compute_topo_order (graph, ti); +- +- while (ti->topo_order.length () != 0) ++ auto_vec topo_order = compute_topo_order (graph); ++ while (topo_order.length () != 0) + { +- +- i = ti->topo_order.pop (); ++ i = topo_order.pop (); + + /* If this variable is not a representative, skip it. */ + if (find (i) != i) +@@ -2888,7 +2864,6 @@ solve_graph (constraint_graph_t graph) + } + } + } +- free_topo_info (ti); + bitmap_obstack_release (&iteration_obstack); + } + +diff --git a/gcc/tree-ssa-tail-merge.cc b/gcc/tree-ssa-tail-merge.cc +index 9721fdade61..72fe0e2d4ed 100644 +--- a/gcc/tree-ssa-tail-merge.cc ++++ b/gcc/tree-ssa-tail-merge.cc +@@ -1165,6 +1165,9 @@ gimple_equal_p (same_succ *same_succ, gimple *s1, gimple *s2) + return operand_equal_p (lhs1, lhs2, 0); + + case GIMPLE_ASSIGN: ++ if (gimple_assign_rhs_code (s1) != gimple_assign_rhs_code (s2)) ++ return false; ++ + lhs1 = gimple_get_lhs (s1); + lhs2 = gimple_get_lhs (s2); + if (TREE_CODE (lhs1) != SSA_NAME +@@ -1172,11 +1175,20 @@ gimple_equal_p (same_succ *same_succ, gimple *s1, gimple *s2) + return (operand_equal_p (lhs1, lhs2, 0) + && gimple_operand_equal_value_p (gimple_assign_rhs1 (s1), + gimple_assign_rhs1 (s2))); +- else if (TREE_CODE (lhs1) == SSA_NAME +- && TREE_CODE (lhs2) == SSA_NAME) +- return operand_equal_p (gimple_assign_rhs1 (s1), +- gimple_assign_rhs1 (s2), 0); +- return false; ++ ++ if (TREE_CODE (lhs1) != SSA_NAME ++ || TREE_CODE (lhs2) != SSA_NAME) ++ return false; ++ ++ gcc_checking_assert (gimple_num_args (s1) == gimple_num_args (s2)); ++ for (i = 0; i < gimple_num_args (s1); ++i) ++ { ++ t1 = gimple_arg (s1, i); ++ t2 = gimple_arg (s2, i); ++ if (!gimple_operand_equal_value_p (t1, t2)) ++ return false; ++ } ++ return true; + + case GIMPLE_COND: + t1 = gimple_cond_lhs (s1); +diff --git a/gcc/tree-ssa.cc b/gcc/tree-ssa.cc +index d36d2273f9d..491a5fa9565 100644 +--- a/gcc/tree-ssa.cc ++++ b/gcc/tree-ssa.cc +@@ -1790,15 +1790,20 @@ maybe_optimize_var (tree var, bitmap addresses_taken, bitmap not_reg_needs, + maybe_reg = true; + DECL_NOT_GIMPLE_REG_P (var) = 0; + } +- if (maybe_reg && is_gimple_reg (var)) ++ if (maybe_reg) + { +- if (dump_file) ++ if (is_gimple_reg (var)) + { +- fprintf (dump_file, "Now a gimple register: "); +- print_generic_expr (dump_file, var); +- fprintf (dump_file, "\n"); ++ if (dump_file) ++ { ++ fprintf (dump_file, "Now a gimple register: "); ++ print_generic_expr (dump_file, var); ++ fprintf (dump_file, "\n"); ++ } ++ bitmap_set_bit (suitable_for_renaming, DECL_UID (var)); + } +- bitmap_set_bit (suitable_for_renaming, DECL_UID (var)); ++ else ++ DECL_NOT_GIMPLE_REG_P (var) = 1; + } + } + } +diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc +index 4e615b80b3a..b47d0122aec 100644 +--- a/gcc/tree-vect-data-refs.cc ++++ b/gcc/tree-vect-data-refs.cc +@@ -672,158 +672,166 @@ vect_slp_analyze_data_ref_dependence (vec_info *vinfo, + } + + +-/* Analyze dependences involved in the transform of SLP NODE. STORES +- contain the vector of scalar stores of this instance if we are +- disambiguating the loads. */ ++/* Analyze dependences involved in the transform of a store SLP NODE. */ + + static bool +-vect_slp_analyze_node_dependences (vec_info *vinfo, slp_tree node, +- vec stores, +- stmt_vec_info last_store_info) ++vect_slp_analyze_store_dependences (vec_info *vinfo, slp_tree node) + { +- /* This walks over all stmts involved in the SLP load/store done ++ /* This walks over all stmts involved in the SLP store done + in NODE verifying we can sink them up to the last stmt in the + group. */ +- if (DR_IS_WRITE (STMT_VINFO_DATA_REF (SLP_TREE_REPRESENTATIVE (node)))) ++ stmt_vec_info last_access_info = vect_find_last_scalar_stmt_in_slp (node); ++ gcc_assert (DR_IS_WRITE (STMT_VINFO_DATA_REF (last_access_info))); ++ ++ for (unsigned k = 0; k < SLP_TREE_SCALAR_STMTS (node).length (); ++k) + { +- stmt_vec_info last_access_info = vect_find_last_scalar_stmt_in_slp (node); +- for (unsigned k = 0; k < SLP_TREE_SCALAR_STMTS (node).length (); ++k) ++ stmt_vec_info access_info ++ = vect_orig_stmt (SLP_TREE_SCALAR_STMTS (node)[k]); ++ if (access_info == last_access_info) ++ continue; ++ data_reference *dr_a = STMT_VINFO_DATA_REF (access_info); ++ ao_ref ref; ++ bool ref_initialized_p = false; ++ for (gimple_stmt_iterator gsi = gsi_for_stmt (access_info->stmt); ++ gsi_stmt (gsi) != last_access_info->stmt; gsi_next (&gsi)) + { +- stmt_vec_info access_info +- = vect_orig_stmt (SLP_TREE_SCALAR_STMTS (node)[k]); +- if (access_info == last_access_info) ++ gimple *stmt = gsi_stmt (gsi); ++ if (! gimple_vuse (stmt)) + continue; +- data_reference *dr_a = STMT_VINFO_DATA_REF (access_info); +- ao_ref ref; +- bool ref_initialized_p = false; +- for (gimple_stmt_iterator gsi = gsi_for_stmt (access_info->stmt); +- gsi_stmt (gsi) != last_access_info->stmt; gsi_next (&gsi)) +- { +- gimple *stmt = gsi_stmt (gsi); +- if (! gimple_vuse (stmt)) +- continue; + +- /* If we couldn't record a (single) data reference for this +- stmt we have to resort to the alias oracle. */ +- stmt_vec_info stmt_info = vinfo->lookup_stmt (stmt); +- data_reference *dr_b = STMT_VINFO_DATA_REF (stmt_info); +- if (!dr_b) +- { +- /* We are moving a store - this means +- we cannot use TBAA for disambiguation. */ +- if (!ref_initialized_p) +- ao_ref_init (&ref, DR_REF (dr_a)); +- if (stmt_may_clobber_ref_p_1 (stmt, &ref, false) +- || ref_maybe_used_by_stmt_p (stmt, &ref, false)) +- return false; +- continue; +- } +- +- bool dependent = false; +- /* If we run into a store of this same instance (we've just +- marked those) then delay dependence checking until we run +- into the last store because this is where it will have +- been sunk to (and we verify if we can do that as well). */ +- if (gimple_visited_p (stmt)) +- { +- if (stmt_info != last_store_info) +- continue; +- +- for (stmt_vec_info &store_info : stores) +- { +- data_reference *store_dr +- = STMT_VINFO_DATA_REF (store_info); +- ddr_p ddr = initialize_data_dependence_relation +- (dr_a, store_dr, vNULL); +- dependent +- = vect_slp_analyze_data_ref_dependence (vinfo, ddr); +- free_dependence_relation (ddr); +- if (dependent) +- break; +- } +- } +- else +- { +- ddr_p ddr = initialize_data_dependence_relation (dr_a, +- dr_b, vNULL); +- dependent = vect_slp_analyze_data_ref_dependence (vinfo, ddr); +- free_dependence_relation (ddr); +- } +- if (dependent) ++ /* If we couldn't record a (single) data reference for this ++ stmt we have to resort to the alias oracle. */ ++ stmt_vec_info stmt_info = vinfo->lookup_stmt (stmt); ++ data_reference *dr_b = STMT_VINFO_DATA_REF (stmt_info); ++ if (!dr_b) ++ { ++ /* We are moving a store - this means ++ we cannot use TBAA for disambiguation. */ ++ if (!ref_initialized_p) ++ ao_ref_init (&ref, DR_REF (dr_a)); ++ if (stmt_may_clobber_ref_p_1 (stmt, &ref, false) ++ || ref_maybe_used_by_stmt_p (stmt, &ref, false)) + return false; ++ continue; + } ++ ++ gcc_assert (!gimple_visited_p (stmt)); ++ ++ ddr_p ddr = initialize_data_dependence_relation (dr_a, ++ dr_b, vNULL); ++ bool dependent = vect_slp_analyze_data_ref_dependence (vinfo, ddr); ++ free_dependence_relation (ddr); ++ if (dependent) ++ return false; + } + } +- else /* DR_IS_READ */ ++ return true; ++} ++ ++/* Analyze dependences involved in the transform of a load SLP NODE. STORES ++ contain the vector of scalar stores of this instance if we are ++ disambiguating the loads. */ ++ ++static bool ++vect_slp_analyze_load_dependences (vec_info *vinfo, slp_tree node, ++ vec stores, ++ stmt_vec_info last_store_info) ++{ ++ /* This walks over all stmts involved in the SLP load done ++ in NODE verifying we can hoist them up to the first stmt in the ++ group. */ ++ stmt_vec_info first_access_info = vect_find_first_scalar_stmt_in_slp (node); ++ gcc_assert (DR_IS_READ (STMT_VINFO_DATA_REF (first_access_info))); ++ ++ for (unsigned k = 0; k < SLP_TREE_SCALAR_STMTS (node).length (); ++k) + { +- stmt_vec_info first_access_info +- = vect_find_first_scalar_stmt_in_slp (node); +- for (unsigned k = 0; k < SLP_TREE_SCALAR_STMTS (node).length (); ++k) ++ stmt_vec_info access_info ++ = vect_orig_stmt (SLP_TREE_SCALAR_STMTS (node)[k]); ++ if (access_info == first_access_info) ++ continue; ++ data_reference *dr_a = STMT_VINFO_DATA_REF (access_info); ++ ao_ref ref; ++ bool ref_initialized_p = false; ++ hash_set grp_visited; ++ for (gimple_stmt_iterator gsi = gsi_for_stmt (access_info->stmt); ++ gsi_stmt (gsi) != first_access_info->stmt; gsi_prev (&gsi)) + { +- stmt_vec_info access_info +- = vect_orig_stmt (SLP_TREE_SCALAR_STMTS (node)[k]); +- if (access_info == first_access_info) ++ gimple *stmt = gsi_stmt (gsi); ++ if (! gimple_vdef (stmt)) + continue; +- data_reference *dr_a = STMT_VINFO_DATA_REF (access_info); +- ao_ref ref; +- bool ref_initialized_p = false; +- for (gimple_stmt_iterator gsi = gsi_for_stmt (access_info->stmt); +- gsi_stmt (gsi) != first_access_info->stmt; gsi_prev (&gsi)) ++ ++ stmt_vec_info stmt_info = vinfo->lookup_stmt (stmt); ++ ++ /* If we run into a store of this same instance (we've just ++ marked those) then delay dependence checking until we run ++ into the last store because this is where it will have ++ been sunk to (and we verified that we can do that already). */ ++ if (gimple_visited_p (stmt)) + { +- gimple *stmt = gsi_stmt (gsi); +- if (! gimple_vdef (stmt)) ++ if (stmt_info != last_store_info) + continue; + +- /* If we couldn't record a (single) data reference for this +- stmt we have to resort to the alias oracle. */ +- stmt_vec_info stmt_info = vinfo->lookup_stmt (stmt); +- data_reference *dr_b = STMT_VINFO_DATA_REF (stmt_info); ++ for (stmt_vec_info &store_info : stores) ++ { ++ data_reference *store_dr = STMT_VINFO_DATA_REF (store_info); ++ ddr_p ddr = initialize_data_dependence_relation ++ (dr_a, store_dr, vNULL); ++ bool dependent ++ = vect_slp_analyze_data_ref_dependence (vinfo, ddr); ++ free_dependence_relation (ddr); ++ if (dependent) ++ return false; ++ } ++ continue; ++ } + +- /* We are hoisting a load - this means we can use +- TBAA for disambiguation. */ ++ auto check_hoist = [&] (stmt_vec_info stmt_info) -> bool ++ { ++ /* We are hoisting a load - this means we can use TBAA for ++ disambiguation. */ + if (!ref_initialized_p) + ao_ref_init (&ref, DR_REF (dr_a)); +- if (stmt_may_clobber_ref_p_1 (stmt, &ref, true)) ++ if (stmt_may_clobber_ref_p_1 (stmt_info->stmt, &ref, true)) + { ++ /* If we couldn't record a (single) data reference for this ++ stmt we have to give up now. */ ++ data_reference *dr_b = STMT_VINFO_DATA_REF (stmt_info); + if (!dr_b) + return false; +- /* Resort to dependence checking below. */ +- } +- else +- /* No dependence. */ +- continue; +- +- bool dependent = false; +- /* If we run into a store of this same instance (we've just +- marked those) then delay dependence checking until we run +- into the last store because this is where it will have +- been sunk to (and we verify if we can do that as well). */ +- if (gimple_visited_p (stmt)) +- { +- if (stmt_info != last_store_info) +- continue; +- +- for (stmt_vec_info &store_info : stores) +- { +- data_reference *store_dr +- = STMT_VINFO_DATA_REF (store_info); +- ddr_p ddr = initialize_data_dependence_relation +- (dr_a, store_dr, vNULL); +- dependent +- = vect_slp_analyze_data_ref_dependence (vinfo, ddr); +- free_dependence_relation (ddr); +- if (dependent) +- break; +- } +- } +- else +- { + ddr_p ddr = initialize_data_dependence_relation (dr_a, + dr_b, vNULL); +- dependent = vect_slp_analyze_data_ref_dependence (vinfo, ddr); ++ bool dependent ++ = vect_slp_analyze_data_ref_dependence (vinfo, ddr); + free_dependence_relation (ddr); ++ if (dependent) ++ return false; + } +- if (dependent) ++ /* No dependence. */ ++ return true; ++ }; ++ if (STMT_VINFO_GROUPED_ACCESS (stmt_info)) ++ { ++ /* When we run into a store group we have to honor ++ that earlier stores might be moved here. We don't ++ know exactly which and where to since we lack a ++ back-mapping from DR to SLP node, so assume all ++ earlier stores are sunk here. It's enough to ++ consider the last stmt of a group for this. ++ ??? Both this and the fact that we disregard that ++ the conflicting instance might be removed later ++ is overly conservative. */ ++ if (!grp_visited.add (DR_GROUP_FIRST_ELEMENT (stmt_info))) ++ for (auto store_info = DR_GROUP_FIRST_ELEMENT (stmt_info); ++ store_info != NULL; ++ store_info = DR_GROUP_NEXT_ELEMENT (store_info)) ++ if ((store_info == stmt_info ++ || get_later_stmt (store_info, stmt_info) == stmt_info) ++ && !check_hoist (store_info)) ++ return false; ++ } ++ else ++ { ++ if (!check_hoist (stmt_info)) + return false; + } + } +@@ -852,7 +860,7 @@ vect_slp_analyze_instance_dependence (vec_info *vinfo, slp_instance instance) + stmt_vec_info last_store_info = NULL; + if (store) + { +- if (! vect_slp_analyze_node_dependences (vinfo, store, vNULL, NULL)) ++ if (! vect_slp_analyze_store_dependences (vinfo, store)) + return false; + + /* Mark stores in this instance and remember the last one. */ +@@ -866,7 +874,7 @@ vect_slp_analyze_instance_dependence (vec_info *vinfo, slp_instance instance) + /* Verify we can sink loads to the vectorized stmt insert location, + special-casing stores of this instance. */ + for (slp_tree &load : SLP_INSTANCE_LOADS (instance)) +- if (! vect_slp_analyze_node_dependences (vinfo, load, ++ if (! vect_slp_analyze_load_dependences (vinfo, load, + store + ? SLP_TREE_SCALAR_STMTS (store) + : vNULL, last_store_info)) +diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc +index 3435f9378da..e1681047d9d 100644 +--- a/gcc/tree-vect-loop.cc ++++ b/gcc/tree-vect-loop.cc +@@ -2874,7 +2874,7 @@ vect_analyze_loop_1 (class loop *loop, vec_info_shared *shared, + res ? "succeeded" : " failed", + GET_MODE_NAME (loop_vinfo->vector_mode)); + +- if (!main_loop_vinfo && suggested_unroll_factor > 1) ++ if (res && !main_loop_vinfo && suggested_unroll_factor > 1) + { + if (dump_enabled_p ()) + dump_printf_loc (MSG_NOTE, vect_location, +@@ -3513,24 +3513,15 @@ pop: + ??? We could relax this and handle arbitrary live stmts by + forcing a scalar epilogue for example. */ + imm_use_iterator imm_iter; ++ use_operand_p use_p; + gimple *op_use_stmt; + unsigned cnt = 0; + FOR_EACH_IMM_USE_STMT (op_use_stmt, imm_iter, op.ops[opi]) + if (!is_gimple_debug (op_use_stmt) + && (*code != ERROR_MARK + || flow_bb_inside_loop_p (loop, gimple_bb (op_use_stmt)))) +- { +- /* We want to allow x + x but not x < 1 ? x : 2. */ +- if (is_gimple_assign (op_use_stmt) +- && gimple_assign_rhs_code (op_use_stmt) == COND_EXPR) +- { +- use_operand_p use_p; +- FOR_EACH_IMM_USE_ON_STMT (use_p, imm_iter) +- cnt++; +- } +- else +- cnt++; +- } ++ FOR_EACH_IMM_USE_ON_STMT (use_p, imm_iter) ++ cnt++; + if (cnt != 1) + { + fail = true; +diff --git a/gcc/wide-int.cc b/gcc/wide-int.cc +index 1fee0788554..6fb66e4721b 100644 +--- a/gcc/wide-int.cc ++++ b/gcc/wide-int.cc +@@ -1888,9 +1888,9 @@ wi::divmod_internal (HOST_WIDE_INT *quotient, unsigned int *remainder_len, + } + + wi_unpack (b_dividend, dividend.get_val (), dividend.get_len (), +- dividend_blocks_needed, dividend_prec, sgn); ++ dividend_blocks_needed, dividend_prec, UNSIGNED); + wi_unpack (b_divisor, divisor.get_val (), divisor.get_len (), +- divisor_blocks_needed, divisor_prec, sgn); ++ divisor_blocks_needed, divisor_prec, UNSIGNED); + + m = dividend_blocks_needed; + b_dividend[m] = 0; +diff --git a/gcc/wide-int.h b/gcc/wide-int.h +index bd0d9a2d4d5..93f293ce841 100644 +--- a/gcc/wide-int.h ++++ b/gcc/wide-int.h +@@ -3169,9 +3169,11 @@ wi::lrotate (const T1 &x, const T2 &y, unsigned int width) + width = precision; + WI_UNARY_RESULT (T2) ymod = umod_trunc (y, width); + WI_UNARY_RESULT (T1) left = wi::lshift (x, ymod); +- WI_UNARY_RESULT (T1) right = wi::lrshift (x, wi::sub (width, ymod)); ++ WI_UNARY_RESULT (T1) right ++ = wi::lrshift (width != precision ? wi::zext (x, width) : x, ++ wi::sub (width, ymod)); + if (width != precision) +- return wi::zext (left, width) | wi::zext (right, width); ++ return wi::zext (left, width) | right; + return left | right; + } + +@@ -3186,10 +3188,11 @@ wi::rrotate (const T1 &x, const T2 &y, unsigned int width) + if (width == 0) + width = precision; + WI_UNARY_RESULT (T2) ymod = umod_trunc (y, width); +- WI_UNARY_RESULT (T1) right = wi::lrshift (x, ymod); ++ WI_UNARY_RESULT (T1) right ++ = wi::lrshift (width != precision ? wi::zext (x, width) : x, ymod); + WI_UNARY_RESULT (T1) left = wi::lshift (x, wi::sub (width, ymod)); + if (width != precision) +- return wi::zext (left, width) | wi::zext (right, width); ++ return wi::zext (left, width) | right; + return left | right; + } + +diff --git a/libffi/ChangeLog b/libffi/ChangeLog +index f9668c45954..3e2b500db22 100644 +--- a/libffi/ChangeLog ++++ b/libffi/ChangeLog +@@ -1,3 +1,11 @@ ++2023-05-09 Dan Horák ++ ++ Backported from master: ++ 2023-05-06 Dan Horák ++ ++ PR libffi/109447 ++ * src/powerpc/ffi_linux64.c (ffi_prep_args64): Update arg.f128 pointer. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/libffi/src/powerpc/ffi_linux64.c b/libffi/src/powerpc/ffi_linux64.c +index 4d50878e402..3454dacd3d6 100644 +--- a/libffi/src/powerpc/ffi_linux64.c ++++ b/libffi/src/powerpc/ffi_linux64.c +@@ -680,7 +680,7 @@ ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack) + { + if (vecarg_count < NUM_VEC_ARG_REGISTERS64 + && i < nfixedargs) +- memcpy (vec_base.f128++, arg.f128, sizeof (float128)); ++ memcpy (vec_base.f128++, arg.f128++, sizeof (float128)); + else + memcpy (next_arg.f128, arg.f128++, sizeof (float128)); + if (++next_arg.f128 == gpr_end.f128) +diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog +index 673c62f12dc..a45d5185770 100644 +--- a/libgcc/ChangeLog ++++ b/libgcc/ChangeLog +@@ -1,3 +1,19 @@ ++2023-05-21 Iain Sandoe ++ ++ Backported from master: ++ 2023-05-19 Iain Sandoe ++ ++ * config.host: Arrange to set min Darwin OS versions from ++ the configured host version. ++ * config/darwin10-unwind-find-enc-func.c: Do not use current ++ headers, but declare the nexessary structures locally to the ++ versions in use for Mac OSX 10.6. ++ * config/t-darwin: Amend to handle configured min OS ++ versions. ++ * config/t-darwin-min-1: New. ++ * config/t-darwin-min-5: New. ++ * config/t-darwin-min-8: New. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/libgcc/config.host b/libgcc/config.host +index 8c56fcae5d2..89e3dbc7c8a 100644 +--- a/libgcc/config.host ++++ b/libgcc/config.host +@@ -241,6 +241,24 @@ case ${host} in + ;; + esac + tmake_file="$tmake_file t-slibgcc-darwin" ++ # newer toolsets produce warnings when building for unsupported versions. ++ case ${host} in ++ *-*-darwin1[89]* | *-*-darwin2* ) ++ tmake_file="t-darwin-min-8 $tmake_file" ++ ;; ++ *-*-darwin9* | *-*-darwin1[0-7]*) ++ tmake_file="t-darwin-min-5 $tmake_file" ++ ;; ++ *-*-darwin[4-8]*) ++ tmake_file="t-darwin-min-1 $tmake_file" ++ ;; ++ *) ++ # Fall back to configuring for the oldest system known to work with ++ # all archs and the current sources. ++ tmake_file="t-darwin-min-5 $tmake_file" ++ echo "Warning: libgcc configured to support macOS 10.5" 1>&2 ++ ;; ++ esac + extra_parts="crt3.o libd10-uwfef.a crttms.o crttme.o libemutls_w.a" + ;; + *-*-dragonfly*) +diff --git a/libgcc/config/darwin10-unwind-find-enc-func.c b/libgcc/config/darwin10-unwind-find-enc-func.c +index 882ec3a2372..b08396c5f1b 100644 +--- a/libgcc/config/darwin10-unwind-find-enc-func.c ++++ b/libgcc/config/darwin10-unwind-find-enc-func.c +@@ -1,8 +1,34 @@ +-#include "tconfig.h" +-#include "tsystem.h" +-#include "unwind-dw2-fde.h" + #include "libgcc_tm.h" + ++/* This shim is special, it needs to be built for Mac OSX 10.6 ++ regardless of the current system version. ++ We must also build it to use the unwinder layout that was ++ present for 10.6 (and not update that). ++ So we copy the referenced structures from unwind-dw2-fde.h ++ to avoid pulling in newer system headers and/or changed ++ layouts. */ ++struct dwarf_eh_bases ++{ ++ void *tbase; ++ void *dbase; ++ void *func; ++}; ++ ++typedef int sword __attribute__ ((mode (SI))); ++typedef unsigned int uword __attribute__ ((mode (SI))); ++ ++/* The first few fields of an FDE. */ ++struct dwarf_fde ++{ ++ uword length; ++ sword CIE_delta; ++ unsigned char pc_begin[]; ++} __attribute__ ((packed, aligned (__alignof__ (void *)))); ++ ++typedef struct dwarf_fde fde; ++ ++extern const fde * _Unwind_Find_FDE (void *, struct dwarf_eh_bases *); ++ + void * + _darwin10_Unwind_FindEnclosingFunction (void *pc) + { +@@ -10,5 +36,5 @@ _darwin10_Unwind_FindEnclosingFunction (void *pc) + const struct dwarf_fde *fde = _Unwind_Find_FDE (pc-1, &bases); + if (fde) + return bases.func; +- return NULL; ++ return (void *) 0; + } +diff --git a/libgcc/config/t-darwin b/libgcc/config/t-darwin +index 299d26c2c96..a3bb70c6a0a 100644 +--- a/libgcc/config/t-darwin ++++ b/libgcc/config/t-darwin +@@ -1,15 +1,15 @@ + # Set this as a minimum (unless overriden by arch t-files) since it's a + # reasonable lowest common denominator that works for all our archs. +-HOST_LIBGCC2_CFLAGS += -mmacosx-version-min=10.4 ++HOST_LIBGCC2_CFLAGS += $(DARWIN_MIN_LIB_VERSION) + + crt3.o: $(srcdir)/config/darwin-crt3.c +- $(crt_compile) -mmacosx-version-min=10.4 -c $< ++ $(crt_compile) $(DARWIN_MIN_CRT_VERSION) -c $< + + crttms.o: $(srcdir)/config/darwin-crt-tm.c +- $(crt_compile) -mmacosx-version-min=10.4 -DSTART -c $< ++ $(crt_compile) $(DARWIN_MIN_CRT_VERSION) -DSTART -c $< + + crttme.o: $(srcdir)/config/darwin-crt-tm.c +- $(crt_compile) -mmacosx-version-min=10.4 -DEND -c $< ++ $(crt_compile) $(DARWIN_MIN_CRT_VERSION) -DEND -c $< + + # Make emutls weak so that we can deal with -static-libgcc, override the + # hidden visibility when this is present in libgcc_eh. +@@ -25,6 +25,8 @@ libemutls_w.a: emutls_s.o + $(RANLIB_FOR_TARGET) $@ + + # Patch to __Unwind_Find_Enclosing_Function for Darwin10. ++# This needs to be built for darwin10, regardless of the current platform ++# version. + d10-uwfef.o: $(srcdir)/config/darwin10-unwind-find-enc-func.c libgcc_tm.h + $(crt_compile) -mmacosx-version-min=10.6 -c $< + +diff --git a/libgcc/config/t-darwin-min-1 b/libgcc/config/t-darwin-min-1 +new file mode 100644 +index 00000000000..8c2cf8acd39 +--- /dev/null ++++ b/libgcc/config/t-darwin-min-1 +@@ -0,0 +1,3 @@ ++# Support building with -mmacosx-version-min back to 10.1. ++DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.4 ++DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.1 +diff --git a/libgcc/config/t-darwin-min-5 b/libgcc/config/t-darwin-min-5 +new file mode 100644 +index 00000000000..138193151e7 +--- /dev/null ++++ b/libgcc/config/t-darwin-min-5 +@@ -0,0 +1,3 @@ ++# Support building with -mmacosx-version-min back to 10.5. ++DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.5 ++DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.5 +diff --git a/libgcc/config/t-darwin-min-8 b/libgcc/config/t-darwin-min-8 +new file mode 100644 +index 00000000000..9efc9dc0257 +--- /dev/null ++++ b/libgcc/config/t-darwin-min-8 +@@ -0,0 +1,3 @@ ++# Support building with -mmacosx-version-min back to 10.8. ++DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.8 ++DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.8 +diff --git a/libgo/Makefile.am b/libgo/Makefile.am +index b03e6553e90..c273d94d111 100644 +--- a/libgo/Makefile.am ++++ b/libgo/Makefile.am +@@ -417,6 +417,7 @@ toolexeclibgounicode_DATA = \ + # Some internal packages are needed to bootstrap the gc toolchain. + toolexeclibgointernaldir = $(toolexeclibgodir)/internal + toolexeclibgointernal_DATA = \ ++ internal/lazyregexp.gox \ + internal/reflectlite.gox \ + internal/unsafeheader.gox + +diff --git a/libgo/Makefile.in b/libgo/Makefile.in +index 16ed62a82ed..04fdb60d497 100644 +--- a/libgo/Makefile.in ++++ b/libgo/Makefile.in +@@ -885,6 +885,7 @@ toolexeclibgounicode_DATA = \ + # Some internal packages are needed to bootstrap the gc toolchain. + toolexeclibgointernaldir = $(toolexeclibgodir)/internal + toolexeclibgointernal_DATA = \ ++ internal/lazyregexp.gox \ + internal/reflectlite.gox \ + internal/unsafeheader.gox + +diff --git a/libgo/go/internal/abi/abi.go b/libgo/go/internal/abi/abi.go +index c4a108847ca..66251274d97 100644 +--- a/libgo/go/internal/abi/abi.go ++++ b/libgo/go/internal/abi/abi.go +@@ -17,10 +17,7 @@ package abi + // compile-time error. + // + // Implemented as a compile intrinsic. +-func FuncPCABI0(f any) uintptr { +- // The compiler should remove all calls. +- panic("FuncPCABI0") +-} ++func FuncPCABI0(f any) uintptr + + // FuncPCABIInternal returns the entry PC of the function f. If f is a + // direct reference of a function, it must be defined as ABIInternal. +@@ -29,7 +26,4 @@ func FuncPCABI0(f any) uintptr { + // the behavior is undefined. + // + // Implemented as a compile intrinsic. +-func FuncPCABIInternal(f any) uintptr { +- // The compiler should remove all calls. +- panic("FuncPCABIInternal") +-} ++func FuncPCABIInternal(f any) uintptr +diff --git a/libgo/go/syscall/libcall_linux.go b/libgo/go/syscall/libcall_linux.go +index 96974bd3269..a39f408151a 100644 +--- a/libgo/go/syscall/libcall_linux.go ++++ b/libgo/go/syscall/libcall_linux.go +@@ -188,6 +188,14 @@ func Gettid() (tid int) { + //sys PivotRoot(newroot string, putold string) (err error) + //pivot_root(newroot *byte, putold *byte) _C_int + ++// Used by golang.org/x/sys/unix. ++//sys prlimit(pid int, resource int, newlimit *Rlimit, oldlimit *Rlimit) (err error) ++//prlimit(pid Pid_t, resource _C_int, newlimit *Rlimit, oldlimit *Rlimit) _C_int ++ ++func Prlimit(pid int, resource int, newlimit *Rlimit, oldlimit *Rlimit) error { ++ return prlimit(pid, resource, newlimit, oldlimit) ++} ++ + //sys Removexattr(path string, attr string) (err error) + //removexattr(path *byte, name *byte) _C_int + +diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog +index 8962addec63..0b2eb559829 100644 +--- a/libgomp/ChangeLog ++++ b/libgomp/ChangeLog +@@ -1,3 +1,69 @@ ++2023-09-01 Tobias Burnus ++ ++ Backported from master: ++ 2023-08-19 Tobias Burnus ++ ++ PR middle-end/111017 ++ * testsuite/libgomp.c-c++-common/non-rect-loop-1.c: New test. ++ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-06-02 Thomas Schwinge ++ ++ PR testsuite/66005 ++ * testsuite/lib/libgomp.exp: 'flock' through stdout. ++ * testsuite/flock: New. ++ * configure.ac (FLOCK): Point to that if no 'flock' available, but ++ 'perl' is. ++ * configure: Regenerate. ++ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-05-15 Thomas Schwinge ++ ++ PR testsuite/66005 ++ * configure.ac: Look for 'flock'. ++ * testsuite/Makefile.am (gcc_test_parallel_slots): Enable parallel testing. ++ * testsuite/config/default.exp: Don't 'load_lib "standard.exp"' here... ++ * testsuite/lib/libgomp.exp: ... but here, instead. ++ (libgomp_load): Override for parallel testing. ++ * testsuite/libgomp-site-extra.exp.in (FLOCK): Set. ++ * configure: Regenerate. ++ * Makefile.in: Regenerate. ++ * testsuite/Makefile.in: Regenerate. ++ ++2023-06-28 Rainer Orth ++ ++ Backported from master: ++ 2023-05-15 Rainer Orth ++ Thomas Schwinge ++ ++ PR testsuite/66005 ++ * testsuite/Makefile.am (PWD_COMMAND): New variable. ++ (%/site.exp): New target. ++ (check_p_numbers0, check_p_numbers1, check_p_numbers2) ++ (check_p_numbers3, check_p_numbers4, check_p_numbers5) ++ (check_p_numbers6, check_p_numbers, gcc_test_parallel_slots) ++ (check_p_subdirs) ++ (check_DEJAGNU_libgomp_targets): New variables. ++ ($(check_DEJAGNU_libgomp_targets)): New target. ++ ($(check_DEJAGNU_libgomp_targets)): New dependency. ++ (check-DEJAGNU $(check_DEJAGNU_libgomp_targets)): New targets. ++ * testsuite/Makefile.in: Regenerate. ++ * testsuite/lib/libgomp.exp: For parallel testing, ++ 'load_file ../libgomp-test-support.exp'. ++ ++2023-06-28 Thomas Schwinge ++ ++ Backported from master: ++ 2023-05-08 Thomas Schwinge ++ ++ * testsuite/libgomp.c++/c++.exp: Use 'lang_include_flags' instead ++ of 'libstdcxx_includes'. ++ * testsuite/libgomp.oacc-c++/c++.exp: Likewise. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/libgomp/Makefile.in b/libgomp/Makefile.in +index 6f0cb716135..31ad7aa4b48 100644 +--- a/libgomp/Makefile.in ++++ b/libgomp/Makefile.in +@@ -384,6 +384,7 @@ EXEEXT = @EXEEXT@ + FC = @FC@ + FCFLAGS = @FCFLAGS@ + FGREP = @FGREP@ ++FLOCK = @FLOCK@ + GREP = @GREP@ + HSA_RUNTIME_INCLUDE = @HSA_RUNTIME_INCLUDE@ + HSA_RUNTIME_LIB = @HSA_RUNTIME_LIB@ +diff --git a/libgomp/configure b/libgomp/configure +index 85fdb4d3f48..be2c5a63d69 100755 +--- a/libgomp/configure ++++ b/libgomp/configure +@@ -656,6 +656,7 @@ tmake_file + XLDFLAGS + XCFLAGS + config_path ++FLOCK + CPU_COUNT + LIBGOMP_BUILD_VERSIONED_SHLIB_SUN_FALSE + LIBGOMP_BUILD_VERSIONED_SHLIB_SUN_TRUE +@@ -11431,7 +11432,7 @@ else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11434 "configure" ++#line 11435 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11537,7 +11538,7 @@ else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11540 "configure" ++#line 11541 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -16663,6 +16664,91 @@ $as_echo "unable to detect (assuming 1)" >&6; } + fi + + ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for flock implementation" >&5 ++$as_echo "$as_me: checking for flock implementation" >&6;} ++for ac_prog in flock ++do ++ # Extract the first word of "$ac_prog", so it can be a program name with args. ++set dummy $ac_prog; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_FLOCK+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$FLOCK"; then ++ ac_cv_prog_FLOCK="$FLOCK" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ++ ac_cv_prog_FLOCK="$ac_prog" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++FLOCK=$ac_cv_prog_FLOCK ++if test -n "$FLOCK"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $FLOCK" >&5 ++$as_echo "$FLOCK" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++ test -n "$FLOCK" && break ++done ++ ++# Fallback if 'perl' is available. ++if test -z "$FLOCK"; then ++ # Extract the first word of "perl", so it can be a program name with args. ++set dummy perl; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_FLOCK+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$FLOCK"; then ++ ac_cv_prog_FLOCK="$FLOCK" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then ++ ac_cv_prog_FLOCK="$srcdir/testsuite/flock" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++FLOCK=$ac_cv_prog_FLOCK ++if test -n "$FLOCK"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $FLOCK" >&5 ++$as_echo "$FLOCK" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++ + # Get target configury. + . ${srcdir}/configure.tgt + CFLAGS="$save_CFLAGS $XCFLAGS" +diff --git a/libgomp/configure.ac b/libgomp/configure.ac +index a9b1f3973f7..cc96e5b753b 100644 +--- a/libgomp/configure.ac ++++ b/libgomp/configure.ac +@@ -339,6 +339,13 @@ fi + AX_COUNT_CPUS + AC_SUBST(CPU_COUNT) + ++AC_MSG_NOTICE([checking for flock implementation]) ++AC_CHECK_PROGS(FLOCK, flock) ++# Fallback if 'perl' is available. ++if test -z "$FLOCK"; then ++ AC_CHECK_PROG(FLOCK, perl, $srcdir/testsuite/flock) ++fi ++ + # Get target configury. + . ${srcdir}/configure.tgt + CFLAGS="$save_CFLAGS $XCFLAGS" +diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am +index 655a413c160..0cc91ccc4d1 100644 +--- a/libgomp/testsuite/Makefile.am ++++ b/libgomp/testsuite/Makefile.am +@@ -12,6 +12,8 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir + ++PWD_COMMAND = $${PWDCMD-pwd} ++ + EXTRA_DEJAGNU_SITE_CONFIG = libgomp-site-extra.exp + + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the +@@ -25,17 +27,6 @@ libgomp-test-support.exp: libgomp-test-support.pt.exp Makefile + 'set offload_additional_lib_paths "$(offload_additional_lib_paths)"' + mv $@.tmp $@ + +-check-DEJAGNU: site.exp +- srcdir='$(srcdir)'; export srcdir; \ +- EXPECT=$(EXPECT); export EXPECT; \ +- if $(SHELL) -c "$(_RUNTEST) --version" > /dev/null 2>&1; then \ +- exit_status=0; l='$(PACKAGE)'; for tool in $$l; do \ +- if $(_RUNTEST) $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $(RUNTESTFLAGS); \ +- then :; else exit_status=1; fi; \ +- done; \ +- else echo "WARNING: could not find '$(_RUNTEST)'" 1>&2; :;\ +- fi; \ +- exit $$exit_status + site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG) + @echo 'Making a new site.exp file ...' + @echo '## these variables are automatically generated by make ##' >site.tmp +@@ -63,6 +54,72 @@ site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG) + @test ! -f site.exp || mv site.exp site.bak + @mv site.tmp site.exp + ++%/site.exp: site.exp ++ -@test -d $* || mkdir $* ++ @srcdir=`cd $(srcdir); ${PWD_COMMAND}`; ++ @objdir=`${PWD_COMMAND}`/$*; \ ++ sed -e "s|^set srcdir .*$$|set srcdir $$srcdir|" \ ++ -e "s|^set objdir .*$$|set objdir $$objdir|" \ ++ site.exp > $*/site.exp.tmp ++ @-rm -f $*/site.bak ++ @test ! -f $*/site.exp || mv $*/site.exp $*/site.bak ++ @mv $*/site.exp.tmp $*/site.exp ++ ++check_p_numbers0:=1 2 3 4 5 6 7 8 9 ++check_p_numbers1:=0 $(check_p_numbers0) ++check_p_numbers2:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers1))) ++check_p_numbers3:=$(addprefix 0,$(check_p_numbers1)) $(check_p_numbers2) ++check_p_numbers4:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers3))) ++check_p_numbers5:=$(addprefix 0,$(check_p_numbers3)) $(check_p_numbers4) ++check_p_numbers6:=$(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers5))) ++check_p_numbers:=$(check_p_numbers0) $(check_p_numbers2) $(check_p_numbers4) $(check_p_numbers6) ++# If unable to serialize execution testing, use just one parallel slot. ++gcc_test_parallel_slots:=$(if $(FLOCK),$(if $(GCC_TEST_PARALLEL_SLOTS),$(GCC_TEST_PARALLEL_SLOTS),19),1) ++check_p_subdirs=$(wordlist 1,$(gcc_test_parallel_slots),$(check_p_numbers)) ++check_DEJAGNU_libgomp_targets = $(addprefix check-DEJAGNUlibgomp,$(check_p_subdirs)) ++$(check_DEJAGNU_libgomp_targets): check-DEJAGNUlibgomp%: libgomp%/site.exp ++ ++check-DEJAGNU $(check_DEJAGNU_libgomp_targets): check-DEJAGNU%: site.exp ++ $(if $*,@)AR="$(AR)"; export AR; \ ++ RANLIB="$(RANLIB)"; export RANLIB; \ ++ if [ -z "$*" ] && [ -n "$(filter -j%, $(MFLAGS))" ]; then \ ++ rm -rf libgomp-parallel || true; \ ++ mkdir libgomp-parallel; \ ++ $(MAKE) $(AM_MAKEFLAGS) $(check_DEJAGNU_libgomp_targets); \ ++ rm -rf libgomp-parallel || true; \ ++ for idx in $(check_p_subdirs); do \ ++ if [ -d libgomp$$idx ]; then \ ++ mv -f libgomp$$idx/libgomp.sum libgomp$$idx/libgomp.sum.sep; \ ++ mv -f libgomp$$idx/libgomp.log libgomp$$idx/libgomp.log.sep; \ ++ fi; \ ++ done; \ ++ $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh \ ++ libgomp[0-9]*/libgomp.sum.sep > libgomp.sum; \ ++ $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh -L \ ++ libgomp[0-9]*/libgomp.log.sep > libgomp.log; \ ++ exit 0; \ ++ fi; \ ++ srcdir=`$(am__cd) $(srcdir) && pwd`; export srcdir; \ ++ EXPECT=$(EXPECT); export EXPECT; \ ++ runtest=$(_RUNTEST); \ ++ if [ -z "$$runtest" ]; then runtest=runtest; fi; \ ++ tool=libgomp; \ ++ if [ -n "$*" ]; then \ ++ if [ -f libgomp-parallel/finished ]; then rm -rf "$*"; exit 0; fi; \ ++ GCC_RUNTEST_PARALLELIZE_DIR=`${PWD_COMMAND}`/libgomp-parallel; \ ++ export GCC_RUNTEST_PARALLELIZE_DIR; \ ++ cd "$*"; \ ++ fi; \ ++ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ ++ $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \ ++ $(RUNTESTFLAGS); \ ++ if [ -n "$*" ]; then \ ++ touch $$GCC_RUNTEST_PARALLELIZE_DIR/finished; \ ++ fi; \ ++ else \ ++ echo "WARNING: could not find \`runtest'" 1>&2; :;\ ++ fi ++ + distclean-DEJAGNU: + -rm -f site.exp site.bak + -l='$(PACKAGE)'; for tool in $$l; do \ +diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in +index e48c3f2f9b0..cd318e3c392 100644 +--- a/libgomp/testsuite/Makefile.in ++++ b/libgomp/testsuite/Makefile.in +@@ -162,6 +162,7 @@ EXEEXT = @EXEEXT@ + FC = @FC@ + FCFLAGS = @FCFLAGS@ + FGREP = @FGREP@ ++FLOCK = @FLOCK@ + GREP = @GREP@ + HSA_RUNTIME_INCLUDE = @HSA_RUNTIME_INCLUDE@ + HSA_RUNTIME_LIB = @HSA_RUNTIME_LIB@ +@@ -310,7 +311,20 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir ++PWD_COMMAND = $${PWDCMD-pwd} + EXTRA_DEJAGNU_SITE_CONFIG = libgomp-site-extra.exp ++check_p_numbers0 := 1 2 3 4 5 6 7 8 9 ++check_p_numbers1 := 0 $(check_p_numbers0) ++check_p_numbers2 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers1))) ++check_p_numbers3 := $(addprefix 0,$(check_p_numbers1)) $(check_p_numbers2) ++check_p_numbers4 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers3))) ++check_p_numbers5 := $(addprefix 0,$(check_p_numbers3)) $(check_p_numbers4) ++check_p_numbers6 := $(foreach i,$(check_p_numbers0),$(addprefix $(i),$(check_p_numbers5))) ++check_p_numbers := $(check_p_numbers0) $(check_p_numbers2) $(check_p_numbers4) $(check_p_numbers6) ++# If unable to serialize execution testing, use just one parallel slot. ++gcc_test_parallel_slots := $(if $(FLOCK),$(if $(GCC_TEST_PARALLEL_SLOTS),$(GCC_TEST_PARALLEL_SLOTS),19),1) ++check_p_subdirs = $(wordlist 1,$(gcc_test_parallel_slots),$(check_p_numbers)) ++check_DEJAGNU_libgomp_targets = $(addprefix check-DEJAGNUlibgomp,$(check_p_subdirs)) + all: all-am + + .SUFFIXES: +@@ -485,17 +499,6 @@ libgomp-test-support.exp: libgomp-test-support.pt.exp Makefile + 'set offload_additional_lib_paths "$(offload_additional_lib_paths)"' + mv $@.tmp $@ + +-check-DEJAGNU: site.exp +- srcdir='$(srcdir)'; export srcdir; \ +- EXPECT=$(EXPECT); export EXPECT; \ +- if $(SHELL) -c "$(_RUNTEST) --version" > /dev/null 2>&1; then \ +- exit_status=0; l='$(PACKAGE)'; for tool in $$l; do \ +- if $(_RUNTEST) $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $(RUNTESTFLAGS); \ +- then :; else exit_status=1; fi; \ +- done; \ +- else echo "WARNING: could not find '$(_RUNTEST)'" 1>&2; :;\ +- fi; \ +- exit $$exit_status + site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG) + @echo 'Making a new site.exp file ...' + @echo '## these variables are automatically generated by make ##' >site.tmp +@@ -523,6 +526,59 @@ site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG) + @test ! -f site.exp || mv site.exp site.bak + @mv site.tmp site.exp + ++%/site.exp: site.exp ++ -@test -d $* || mkdir $* ++ @srcdir=`cd $(srcdir); ${PWD_COMMAND}`; ++ @objdir=`${PWD_COMMAND}`/$*; \ ++ sed -e "s|^set srcdir .*$$|set srcdir $$srcdir|" \ ++ -e "s|^set objdir .*$$|set objdir $$objdir|" \ ++ site.exp > $*/site.exp.tmp ++ @-rm -f $*/site.bak ++ @test ! -f $*/site.exp || mv $*/site.exp $*/site.bak ++ @mv $*/site.exp.tmp $*/site.exp ++$(check_DEJAGNU_libgomp_targets): check-DEJAGNUlibgomp%: libgomp%/site.exp ++ ++check-DEJAGNU $(check_DEJAGNU_libgomp_targets): check-DEJAGNU%: site.exp ++ $(if $*,@)AR="$(AR)"; export AR; \ ++ RANLIB="$(RANLIB)"; export RANLIB; \ ++ if [ -z "$*" ] && [ -n "$(filter -j%, $(MFLAGS))" ]; then \ ++ rm -rf libgomp-parallel || true; \ ++ mkdir libgomp-parallel; \ ++ $(MAKE) $(AM_MAKEFLAGS) $(check_DEJAGNU_libgomp_targets); \ ++ rm -rf libgomp-parallel || true; \ ++ for idx in $(check_p_subdirs); do \ ++ if [ -d libgomp$$idx ]; then \ ++ mv -f libgomp$$idx/libgomp.sum libgomp$$idx/libgomp.sum.sep; \ ++ mv -f libgomp$$idx/libgomp.log libgomp$$idx/libgomp.log.sep; \ ++ fi; \ ++ done; \ ++ $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh \ ++ libgomp[0-9]*/libgomp.sum.sep > libgomp.sum; \ ++ $(SHELL) $(srcdir)/../../contrib/dg-extract-results.sh -L \ ++ libgomp[0-9]*/libgomp.log.sep > libgomp.log; \ ++ exit 0; \ ++ fi; \ ++ srcdir=`$(am__cd) $(srcdir) && pwd`; export srcdir; \ ++ EXPECT=$(EXPECT); export EXPECT; \ ++ runtest=$(_RUNTEST); \ ++ if [ -z "$$runtest" ]; then runtest=runtest; fi; \ ++ tool=libgomp; \ ++ if [ -n "$*" ]; then \ ++ if [ -f libgomp-parallel/finished ]; then rm -rf "$*"; exit 0; fi; \ ++ GCC_RUNTEST_PARALLELIZE_DIR=`${PWD_COMMAND}`/libgomp-parallel; \ ++ export GCC_RUNTEST_PARALLELIZE_DIR; \ ++ cd "$*"; \ ++ fi; \ ++ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ ++ $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \ ++ $(RUNTESTFLAGS); \ ++ if [ -n "$*" ]; then \ ++ touch $$GCC_RUNTEST_PARALLELIZE_DIR/finished; \ ++ fi; \ ++ else \ ++ echo "WARNING: could not find \`runtest'" 1>&2; :;\ ++ fi ++ + distclean-DEJAGNU: + -rm -f site.exp site.bak + -l='$(PACKAGE)'; for tool in $$l; do \ +diff --git a/libgomp/testsuite/config/default.exp b/libgomp/testsuite/config/default.exp +index 7ac3f31d1a2..1c8c47bf13d 100644 +--- a/libgomp/testsuite/config/default.exp ++++ b/libgomp/testsuite/config/default.exp +@@ -13,5 +13,3 @@ + # You should have received a copy of the GNU General Public License + # along with this program; see the file COPYING3. If not see + # . +- +-load_lib "standard.exp" +diff --git a/libgomp/testsuite/flock b/libgomp/testsuite/flock +new file mode 100755 +index 00000000000..71878b104f1 +--- /dev/null ++++ b/libgomp/testsuite/flock +@@ -0,0 +1,17 @@ ++#!/usr/bin/env perl ++ ++use strict; ++use warnings; ++ ++# Only arguments '--exclusive 1' exactly are supported. ++(@ARGV == 2) or die; ++my $mode = shift; ++($mode eq "--exclusive") or die; ++my $fd = shift; ++($fd eq "1") or die; ++ ++use Fcntl ':flock'; ++ ++open(my $fh, '>&=', 1) or die "open: $!"; ++ ++flock($fh, LOCK_EX) or die "flock: $!"; +diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp +index 8c5ecfff0ac..17d173ac8d7 100644 +--- a/libgomp/testsuite/lib/libgomp.exp ++++ b/libgomp/testsuite/lib/libgomp.exp +@@ -9,6 +9,7 @@ proc load_gcc_lib { filename } { + } + + load_lib dg.exp ++load_lib standard.exp + + # Required to use gcc-dg.exp - however, the latter should NOT be + # loaded until ${tool}_target_compile is defined since it uses that +@@ -40,7 +41,12 @@ load_gcc_lib torture-options.exp + load_gcc_lib fortran-modules.exp + + # Try to load a test support file, built during libgomp configuration. +-load_file libgomp-test-support.exp ++# Search in '..' vs. '.' to support parallel vs. sequential testing. ++if [info exists ::env(GCC_RUNTEST_PARALLELIZE_DIR)] { ++ load_file ../libgomp-test-support.exp ++} else { ++ load_file libgomp-test-support.exp ++} + + set dg-do-what-default run + +@@ -319,6 +325,36 @@ proc libgomp_option_proc { option } { + } + } + ++if ![info exists ::env(GCC_RUNTEST_PARALLELIZE_DIR)] { ++ # No parallel testing. ++} elseif { $FLOCK == "" } { ++ # Using just one parallel slot. ++} else { ++ # Using several parallel slots. Override DejaGnu ++ # 'standard.exp:${tool}_load'... ++ rename libgomp_load standard_libgomp_load ++ proc libgomp_load { program args } { ++ # ... in order to serialize execution testing via an exclusive lock. ++ # We use stdout, as per ++ # "[...] FILEHANDLE [...] be open with write intent to use LOCK_EX". ++ set lock_file ../lock ++ set lock_kind --exclusive ++ set lock_fd [open $lock_file a+] ++ set lock_clock_begin [clock seconds] ++ global FLOCK ++ exec $FLOCK $lock_kind 1 >@ $lock_fd ++ set lock_clock_end [clock seconds] ++ verbose -log "Got ${FLOCK}('$lock_file', '$lock_kind') at [clock format $lock_clock_end] after [expr $lock_clock_end - $lock_clock_begin] s" 2 ++ ++ set result [standard_libgomp_load $program $args] ++ ++ # Unlock (implicit with 'close'). ++ close $lock_fd ++ ++ return $result ++ } ++} ++ + # Translate offload target to OpenACC device type. Return the empty string if + # not supported, and 'host' for offload target 'disable'. + proc offload_target_to_openacc_device_type { offload_target } { +diff --git a/libgomp/testsuite/libgomp-site-extra.exp.in b/libgomp/testsuite/libgomp-site-extra.exp.in +index c0d26660bad..0a3ba059c21 100644 +--- a/libgomp/testsuite/libgomp-site-extra.exp.in ++++ b/libgomp/testsuite/libgomp-site-extra.exp.in +@@ -1 +1,2 @@ ++set FLOCK {@FLOCK@} + set GCC_UNDER_TEST {@CC@} +diff --git a/libgomp/testsuite/libgomp.c++/c++.exp b/libgomp/testsuite/libgomp.c++/c++.exp +index f4884e2ffa7..5b9a5924ff3 100644 +--- a/libgomp/testsuite/libgomp.c++/c++.exp ++++ b/libgomp/testsuite/libgomp.c++/c++.exp +@@ -66,13 +66,12 @@ if { $lang_test_file_found } { + + set flags_file "${blddir}/../libstdc++-v3/scripts/testsuite_flags" + if { [file exists $flags_file] } { +- set libstdcxx_includes [exec sh $flags_file --build-includes] +- } else { +- set libstdcxx_includes "" ++ set lang_source_re {^.*\.[cC]$} ++ set lang_include_flags [exec sh $flags_file --build-includes] + } + + # Main loop. +- dg-runtest $tests "" "$libstdcxx_includes $DEFAULT_CFLAGS" ++ dg-runtest $tests "" $DEFAULT_CFLAGS + } + + # See above. +diff --git a/libgomp/testsuite/libgomp.c-c++-common/non-rect-loop-1.c b/libgomp/testsuite/libgomp.c-c++-common/non-rect-loop-1.c +new file mode 100644 +index 00000000000..fbd462b3683 +--- /dev/null ++++ b/libgomp/testsuite/libgomp.c-c++-common/non-rect-loop-1.c +@@ -0,0 +1,72 @@ ++/* PR middle-end/111017 */ ++ ++#include ++ ++#define DIM 32 ++#define N (DIM*DIM) ++ ++int ++main () ++{ ++ int a[N], b[N], c[N]; ++ int dim = DIM; ++ ++ for (int i = 0; i < N; i++) ++ { ++ a[i] = 3*i; ++ b[i] = 7*i; ++ c[i] = 42; ++ } ++ ++ #pragma omp parallel for collapse(2) ++ for (int i = 0; i < DIM; i++) ++ for (int j = (i*DIM); j < (i*DIM + DIM); j++) ++ c[j] = a[j] + b[j]; ++ ++ for (int i = 0; i < DIM; i++) ++ for (int j = (i*DIM); j < (i*DIM + DIM); j++) ++ if (c[j] != a[j] + b[j] || c[j] != 3*j +7*j) ++ __builtin_abort (); ++ for (int i = 0; i < N; i++) ++ c[i] = 42; ++ ++ #pragma omp parallel for collapse(2) ++ for (int i = 0; i < dim; i++) ++ for (int j = (i*dim); j < (i*dim + dim); j++) ++ c[j] = a[j] + b[j]; ++ ++ for (int i = 0; i < DIM; i++) ++ for (int j = (i*DIM); j < (i*DIM + DIM); j++) ++ if (c[j] != a[j] + b[j] || c[j] != 3*j +7*j) ++ __builtin_abort (); ++ for (int i = 0; i < N; i++) ++ c[i] = 42; ++ ++ for (int dev = 0; dev <= omp_get_num_devices(); dev++) ++ { ++ #pragma omp target teams loop device(dev) map(to:a,b) map(from:c) ++ for (int i = 0; i < DIM; i++) ++ for (int j = (i*DIM); j < (i*DIM + DIM); j++) ++ c[j] = a[j] + b[j]; ++ ++ for (int i = 0; i < DIM; i++) ++ for (int j = (i*DIM); j < (i*DIM + DIM); j++) ++ if (c[j] != a[j] + b[j] || c[j] != 3*j +7*j) ++ __builtin_abort (); ++ for (int i = 0; i < N; i++) ++ c[i] = 42; ++ ++ #pragma omp target teams loop device(dev) map(to:a,b) map(from:c) ++ for (int i = 0; i < dim; i++) ++ for (int j = (i*dim); j < (i*dim + dim); j++) ++ c[j] = a[j] + b[j]; ++ ++ for (int i = 0; i < DIM; i++) ++ for (int j = (i*DIM); j < (i*DIM + DIM); j++) ++ if (c[j] != a[j] + b[j] || c[j] != 3*j +7*j) ++ __builtin_abort (); ++ for (int i = 0; i < N; i++) ++ c[i] = 42; ++ } ++ return 0; ++} +diff --git a/libgomp/testsuite/libgomp.oacc-c++/c++.exp b/libgomp/testsuite/libgomp.oacc-c++/c++.exp +index 42e0395f9a5..0b235ba47f3 100644 +--- a/libgomp/testsuite/libgomp.oacc-c++/c++.exp ++++ b/libgomp/testsuite/libgomp.oacc-c++/c++.exp +@@ -72,9 +72,8 @@ if { $lang_test_file_found } { + + set flags_file "${blddir}/../libstdc++-v3/scripts/testsuite_flags" + if { [file exists $flags_file] } { +- set libstdcxx_includes [exec sh $flags_file --build-includes] +- } else { +- set libstdcxx_includes "" ++ set lang_source_re {^.*\.[cC]$} ++ set lang_include_flags [exec sh $flags_file --build-includes] + } + + # Test with all available offload targets, and with offloading disabled. +@@ -147,7 +146,7 @@ if { $lang_test_file_found } { + } + } + +- gcc-dg-runtest $tests "$tagopt" "$libstdcxx_includes" ++ gcc-dg-runtest $tests "$tagopt" "" + } + unset offload_target + } else { +diff --git a/libphobos/ChangeLog b/libphobos/ChangeLog +index 953e1dbfca4..e375c284e2c 100644 +--- a/libphobos/ChangeLog ++++ b/libphobos/ChangeLog +@@ -1,3 +1,15 @@ ++2023-11-07 Iain Buclaw ++ ++ Backported from master: ++ 2023-11-07 Iain Buclaw ++ ++ * libdruntime/core/cpuid.d (getCpuInfo0B): Limit number of times loop ++ runs. ++ ++2023-06-06 Iain Buclaw ++ ++ * src/MERGE: Merge upstream phobos 8e8aaae50. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/libphobos/libdruntime/core/cpuid.d b/libphobos/libdruntime/core/cpuid.d +index e31f776d7ee..b05db248b81 100644 +--- a/libphobos/libdruntime/core/cpuid.d ++++ b/libphobos/libdruntime/core/cpuid.d +@@ -651,10 +651,12 @@ void getAMDcacheinfo() + // to determine number of processors. + void getCpuInfo0B() + { +- int level=0; + int threadsPerCore; + uint a, b, c, d; +- do { ++ // I'm not sure about this. The docs state that there ++ // are 2 hyperthreads per core if HT is factory enabled. ++ for (int level = 0; level < 2; level++) ++ { + version (GNU_OR_LDC) asm pure nothrow @nogc { + "cpuid" : "=a" (a), "=b" (b), "=c" (c), "=d" (d) : "a" (0x0B), "c" (level); + } else asm pure nothrow @nogc { +@@ -666,19 +668,20 @@ void getCpuInfo0B() + mov c, ECX; + mov d, EDX; + } +- if (b!=0) { +- // I'm not sure about this. The docs state that there +- // are 2 hyperthreads per core if HT is factory enabled. +- if (level==0) ++ if (b != 0) ++ { ++ if (level == 0) + threadsPerCore = b & 0xFFFF; +- else if (level==1) { ++ else if (level == 1) ++ { + cpuFeatures.maxThreads = b & 0xFFFF; + cpuFeatures.maxCores = cpuFeatures.maxThreads / threadsPerCore; + } +- + } +- ++level; +- } while (a!=0 || b!=0); ++ // Got "invalid domain" returned from cpuid ++ if (a == 0 && b == 0) ++ break; ++ } + } + + void cpuidX86() +diff --git a/libphobos/src/MERGE b/libphobos/src/MERGE +index f2678185f39..8c570369602 100644 +--- a/libphobos/src/MERGE ++++ b/libphobos/src/MERGE +@@ -1,4 +1,4 @@ +-5fef0d28fc873fb5a0dbfb9149759d76a7b9f1b7 ++8e8aaae5080ccc2e0a2202cbe9778dca96496a95 + + The first line of this file holds the git revision number of the last + merge done from the dlang/phobos repository. +diff --git a/libphobos/src/std/container/array.d b/libphobos/src/std/container/array.d +index 08f9ead196e..ecc45996925 100644 +--- a/libphobos/src/std/container/array.d ++++ b/libphobos/src/std/container/array.d +@@ -412,9 +412,9 @@ if (!is(immutable T == immutable bool)) + .destroy(e); + + static if (hasIndirections!T) +- GC.removeRange(_payload.ptr); ++ GC.removeRange(cast(void*) _payload.ptr); + +- free(_payload.ptr); ++ free(cast(void*) _payload.ptr); + } + + this(this) @disable; +@@ -489,14 +489,14 @@ if (!is(immutable T == immutable bool)) + auto newPayload = newPayloadPtr[0 .. oldLength]; + + // copy old data over to new array +- memcpy(newPayload.ptr, _payload.ptr, T.sizeof * oldLength); ++ memcpy(cast(void*) newPayload.ptr, cast(void*) _payload.ptr, T.sizeof * oldLength); + // Zero out unused capacity to prevent gc from seeing false pointers +- memset(newPayload.ptr + oldLength, ++ memset( cast(void*) (newPayload.ptr + oldLength), + 0, + (elements - oldLength) * T.sizeof); +- GC.addRange(newPayload.ptr, sz); +- GC.removeRange(_payload.ptr); +- free(_payload.ptr); ++ GC.addRange(cast(void*) newPayload.ptr, sz); ++ GC.removeRange(cast(void*) _payload.ptr); ++ free(cast(void*) _payload.ptr); + _payload = newPayload; + } + else +@@ -611,12 +611,17 @@ if (!is(immutable T == immutable bool)) + return opEquals(rhs); + } + ++ // fix https://issues.dlang.org/show_bug.cgi?23140 ++ private alias Unshared(T) = T; ++ private alias Unshared(T: shared U, U) = U; ++ + /// ditto + bool opEquals(ref const Array rhs) const + { + if (empty) return rhs.empty; + if (rhs.empty) return false; +- return _data._payload == rhs._data._payload; ++ ++ return cast(Unshared!(T)[]) _data._payload == cast(Unshared!(T)[]) rhs._data._payload; + } + + /** +@@ -1740,6 +1745,16 @@ if (!is(immutable T == immutable bool)) + assertThrown!AssertError(array.length = 5); + } + ++// https://issues.dlang.org/show_bug.cgi?id=23140 ++@system unittest ++{ ++ shared class C ++ { ++ } ++ ++ Array!C ac; ++ ac = Array!C([new C]); ++} + //////////////////////////////////////////////////////////////////////////////// + // Array!bool + //////////////////////////////////////////////////////////////////////////////// +diff --git a/libphobos/src/std/typecons.d b/libphobos/src/std/typecons.d +index fb15001233a..34e884cac8a 100644 +--- a/libphobos/src/std/typecons.d ++++ b/libphobos/src/std/typecons.d +@@ -3793,8 +3793,28 @@ Params: + sink.formatValue(_value, fmt); + } + } ++ ++ void toString()(scope void delegate(const(char)[]) sink, scope const ref FormatSpec!char fmt) const ++ { ++ if (isNull) ++ { ++ sink.formatValue("Nullable.null", fmt); ++ } ++ else ++ { ++ sink.formatValue(_value, fmt); ++ } ++ } + } + ++@system unittest ++{ ++ import std.conv : to; ++ ++ const Nullable!(ulong, 0) x = 1; ++ assert(x.to!string == "1"); ++} ++ + /** + Check if `this` is in the null state. + +@@ -4320,8 +4340,28 @@ Params: + sink.formatValue(*_value, fmt); + } + } ++ ++ void toString()(scope void delegate(const(char)[]) sink, scope const ref FormatSpec!char fmt) const ++ { ++ if (isNull) ++ { ++ sink.formatValue("Nullable.null", fmt); ++ } ++ else ++ { ++ sink.formatValue(*_value, fmt); ++ } ++ } + } + ++@system unittest ++{ ++ import std.conv : to; ++ ++ const NullableRef!(ulong) x = new ulong(1); ++ assert(x.to!string == "1"); ++} ++ + /** + Binds the internal state to `value`. + +diff --git a/libsanitizer/ChangeLog b/libsanitizer/ChangeLog +index 2f85d1dbdfb..77752060f6f 100644 +--- a/libsanitizer/ChangeLog ++++ b/libsanitizer/ChangeLog +@@ -1,3 +1,11 @@ ++2023-05-21 Iain Sandoe ++ ++ Backported from master: ++ 2023-04-18 Iain Sandoe ++ ++ * configure.tgt: Unsupport Darwin22+ until a mechanism can be found ++ to locate dyld in the shared cache. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/libsanitizer/configure.tgt b/libsanitizer/configure.tgt +index fb89df4935c..bc169c365f2 100644 +--- a/libsanitizer/configure.tgt ++++ b/libsanitizer/configure.tgt +@@ -64,7 +64,7 @@ case "${target}" in + HWASAN_SUPPORTED=yes + fi + ;; +- x86_64-*-darwin2* | x86_64-*-darwin1[2-9]* | i?86-*-darwin1[2-9]*) ++ x86_64-*-darwin2[01]* | x86_64-*-darwin1[2-9]* | i?86-*-darwin1[2-9]*) + TSAN_SUPPORTED=no + EXTRA_CXXFLAGS="${EXTRA_CXXFLAGS} -Wl,-undefined,dynamic_lookup" + ;; +diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog +index 3b6da1e57dd..afe7fa6b936 100644 +--- a/libstdc++-v3/ChangeLog ++++ b/libstdc++-v3/ChangeLog +@@ -1,3 +1,636 @@ ++2023-12-16 Jakub Jelinek ++ ++ Backported from master: ++ 2023-10-13 Jakub Jelinek ++ ++ * testsuite/tr1/8_c_compatibility/cstdio/functions.cc (test01): ++ Initialize stream to va_arg(ap, FILE*) rather than 0. ++ * testsuite/tr1/8_c_compatibility/cwchar/functions.cc (test01): ++ Likewise. ++ ++2023-12-06 Jonathan Wakely ++ ++ Backported from master: ++ 2023-11-02 Jonathan Wakely ++ ++ PR libstdc++/112314 ++ * include/std/string_view (string_view::remove_suffix): Add ++ debug assertion. ++ * testsuite/21_strings/basic_string_view/modifiers/remove_prefix/debug.cc: ++ New test. ++ * testsuite/21_strings/basic_string_view/modifiers/remove_suffix/debug.cc: ++ New test. ++ ++2023-12-06 Jonathan Wakely ++ ++ Backported from master: ++ 2023-11-17 Jonathan Wakely ++ ++ * include/std/utility (in_range): Rename _Up parameter to _Res. ++ ++2023-11-15 Jonathan Wakely ++ ++ Backported from master: ++ 2023-11-15 Jonathan Wakely ++ ++ PR libstdc++/112491 ++ * python/libstdcxx/v6/xmethods.py (DequeWorkerBase.index): ++ Correctly handle unused capacity at the start of the first node. ++ * testsuite/libstdc++-xmethods/deque.cc: Check index operator ++ when elements have been removed from the front. ++ ++2023-11-15 Jonathan Wakely ++ ++ Backported from master: ++ 2023-11-15 Jonathan Wakely ++ ++ * include/std/stacktrace (basic_stacktrace::at): Fix class name ++ in exception message. ++ * testsuite/19_diagnostics/stacktrace/hash.cc: Do not fail if ++ current() returns a non-empty stacktrace. ++ ++2023-11-14 Jonathan Wakely ++ ++ Backported from master: ++ 2023-11-14 Jonathan Wakely ++ ++ PR libstdc++/112348 ++ * include/std/stacktrace (hash>): Fix ++ type of hash function for entries. ++ * testsuite/19_diagnostics/stacktrace/hash.cc: New test. ++ ++2023-11-14 Jonathan Wakely ++ ++ Backported from master: ++ 2023-11-14 Jonathan Wakely ++ ++ PR libstdc++/112491 ++ * python/libstdcxx/v6/xmethods.py (DequeWorkerBase.size): Fix ++ calculation to use _M_start._M_cur. ++ * testsuite/libstdc++-xmethods/deque.cc: Check failing cases. ++ ++2023-11-13 Tom Tromey ++ ++ Backported from master: ++ 2023-10-04 Tom Tromey ++ ++ * python/libstdcxx/v6/printers.py ++ (StdExpAnyPrinter.__init__): Qualify call to ++ _string_types. ++ ++2023-11-13 Tom Tromey ++ ++ Backported from master: ++ 2023-10-04 Tom Tromey ++ ++ * python/libstdcxx/v6/printers.py: Assume that ++ _versioned_namespace is non-None. ++ * python/libstdcxx/v6/xmethods.py (is_specialization_of): ++ Assume that _versioned_namespace is non-None. ++ ++2023-11-13 Tom Tromey ++ ++ Backported from master: ++ 2023-09-28 Tom Tromey ++ ++ * python/libstdcxx/v6/printers.py (Printer.add_version) ++ (add_one_template_type_printer) ++ (FilteringTypePrinter.add_one_type_printer): Use Python ++ "not in" operator. ++ ++2023-11-13 Tom Tromey ++ ++ Backported from master: ++ 2023-10-04 Tom Tromey ++ ++ * python/libstdcxx/v6/xmethods.py (_versioned_namespace): ++ Define. ++ ++2023-11-13 Jonathan Wakely ++ ++ Backported from master: ++ 2023-09-28 Jonathan Wakely ++ ++ * python/libstdcxx/v6/xmethods.py (is_specialization_of): Define ++ new function. ++ (ArrayMethodsMatcher, DequeMethodsMatcher) ++ (ForwardListMethodsMatcher, ListMethodsMatcher) ++ (VectorMethodsMatcher, AssociativeContainerMethodsMatcher) ++ (UniquePtrGetWorker, UniquePtrMethodsMatcher) ++ (SharedPtrSubscriptWorker, SharedPtrMethodsMatcher): Use ++ is_specialization_of instead of re.match. ++ ++2023-11-13 Jonathan Wakely ++ ++ Backported from master: ++ 2023-09-28 Jonathan Wakely ++ ++ * python/libstdcxx/v6/printers.py: Break long lines. Use raw ++ strings for regular expressions. Add whitespace around ++ operators. ++ (is_member_of_namespace): Use isinstance to check type. ++ (is_specialization_of): Likewise. Adjust template_name ++ for versioned namespace instead of duplicating the re.match ++ call. ++ (StdExpAnyPrinter._string_types): New static method. ++ (StdExpAnyPrinter.to_string): Use _string_types. ++ ++2023-11-13 Jonathan Wakely ++ ++ Backported from master: ++ 2023-09-28 Jonathan Wakely ++ ++ * python/libstdcxx/v6/printers.py: Format docstrings according ++ to PEP 257. ++ * python/libstdcxx/v6/xmethods.py: Likewise. ++ ++2023-11-13 Jonathan Wakely ++ ++ Backported from master: ++ 2023-09-12 Jonathan Wakely ++ ++ * python/libstdcxx/v6/printers.py: Reformat. ++ * python/libstdcxx/v6/xmethods.py: Likewise. ++ ++2023-11-06 Ian Lance Taylor ++ ++ PR libbacktrace/111315 ++ PR libbacktrace/112263 ++ * acinclude.m4: Set -D_GNU_SOURCE in BACKTRACE_CPPFLAGS and when ++ grepping link.h for dl_iterate_phdr. ++ * configure: Regenerate. ++ ++2023-10-25 Jonathan Wakely ++ ++ Backported from master: ++ 2023-10-25 Jonathan Wakely ++ ++ PR libstdc++/111936 ++ * src/libbacktrace/Makefile.am: Add -prefer-pic to libtool ++ compile commands. ++ * src/libbacktrace/Makefile.in: Regenerate. ++ ++2023-10-23 François Dumont ++ ++ * include/bits/hashtable_policy.h ++ (_Hash_code_base::_M_hash_code(const _Hash&, const _Hash_node_value<>&)): Remove. ++ (_Hash_code_base::_M_hash_code<_H2>(const _H2&, const _Hash_node_value<>&)): Remove. ++ * include/bits/hashtable.h ++ (_M_src_hash_code<_H2>(const _H2&, const key_type&, const __node_value_type&)): New. ++ (_M_merge_unique<>, _M_merge_multi<>): Use latter. ++ * testsuite/23_containers/unordered_map/modifiers/merge.cc ++ (test04, test05, test06): New test cases. ++ ++2023-10-03 Jonathan Wakely ++ ++ * include/bits/fs_dir.h (directory_iterator::operator==): ++ Define without using a non-exported shared_ptr symbol. ++ (recursive_directory_iterator::operator==): Likewise. ++ ++2023-10-03 Jonathan Wakely ++ ++ Backported from master: ++ 2023-09-01 Jonathan Wakely ++ ++ * testsuite/27_io/filesystem/path/108636.cc: Add dg-require for ++ filesystem support. ++ ++2023-10-03 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-06 Jonathan Wakely ++ ++ PR libstdc++/108178 ++ * src/filesystem/ops-common.h (do_copy_file): Check for empty ++ files by trying to read a character. ++ * testsuite/27_io/filesystem/operations/copy_file_108178.cc: ++ New test. ++ ++2023-10-03 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-06 Jonathan Wakely ++ ++ * src/filesystem/ops-common.h (do_copy_file) [O_CLOEXEC]: Set ++ close-on-exec flag on file descriptors. ++ ++2023-10-03 Jonathan Wakely ++ ++ Backported from master: ++ 2023-03-20 Jonathan Wakely ++ ++ * src/filesystem/ops-common.h (get_temp_directory_from_env): Fix ++ formatting. ++ ++2023-10-03 Jonathan Wakely ++ ++ Backported from master: ++ 2023-02-02 Jonathan Wakely ++ ++ * src/filesystem/ops-common.h [AVR] (__unsupported): Always use ++ errc::function_not_supported instead of errc::not_supported. ++ ++2023-10-02 Tim Song ++ ++ Backported from master: ++ 2023-09-28 Tim Song ++ ++ PR libstdc++/111050 ++ * include/bits/hashtable_policy.h ++ (_Hash_node_value_base<>::_M_valptr(), _Hash_node_value_base<>::_M_v()) ++ Add [[__gnu__::__always_inline__]]. ++ ++2023-09-27 Jonathan Wakely ++ ++ Backported from master: ++ 2023-08-09 Jonathan Wakely ++ ++ * include/experimental/bits/fs_path.h (path::string): Use ++ _GLIBCXX17_CONSTEXPR not _GLIBCXX_CONSTEXPR for 'if constexpr'. ++ * include/std/charconv (__to_chars_8): Initialize variable for ++ C++17 constexpr rules. ++ ++2023-09-26 Jonathan Wakely ++ ++ Backported from master: ++ 2023-09-25 Jonathan Wakely ++ ++ PR libstdc++/111511 ++ PR c++/111512 ++ * include/std/array (to_array): Qualify calls to __to_array. ++ * testsuite/23_containers/array/creation/111512.cc: New test. ++ ++2023-09-18 Jonathan Wakely ++ ++ Backported from master: ++ 2023-09-18 Jonathan Wakely ++ ++ * doc/xml/manual/configure.xml: Use conventional option name. ++ * doc/xml/manual/status_cxx2020.xml: Update. ++ * doc/html/*: Regenerate. ++ ++2023-09-14 Jonathan Wakely ++ ++ Backported from master: ++ 2023-09-14 Jonathan Wakely ++ ++ PR c++/111357 ++ * include/bits/utility.h (make_integer_sequence): Add cast. ++ * testsuite/20_util/integer_sequence/pr111357.cc: New test. ++ ++2023-07-12 Jonathan Wakely ++ ++ Backported from master: ++ 2023-07-12 Jonathan Wakely ++ ++ PR libstdc++/95048 ++ * testsuite/27_io/filesystem/path/construct/95048.cc: Check ++ conversions to wide strings. ++ * testsuite/experimental/filesystem/path/construct/95048.cc: ++ Likewise. ++ ++2023-07-06 Jonathan Wakely ++ ++ Backported from master: ++ 2023-07-06 Jonathan Wakely ++ ++ PR libstdc++/104299 ++ * doc/xml/manual/configure.xml: Describe stdio_pure argument to ++ --enable-cstdio. ++ * doc/html/manual/configure.html: Regenerate. ++ ++2023-06-23 Jonathan Wakely ++ ++ Backported from master: ++ 2023-06-01 Jonathan Wakely ++ ++ * doc/xml/manual/evolution.xml: Document removal of implicit ++ allocator rebinding extensions in strict mode and for C++20. ++ * doc/html/*: Regenerate. ++ ++2023-06-21 Jason Merrill ++ ++ PR tree-optimization/105651 ++ * include/bits/basic_string.tcc (_M_replace): Add an assert ++ to avoid -Wrestrict false positive. ++ ++2023-05-30 Alexandre Oliva ++ ++ Backported from master: ++ 2023-05-30 Alexandre Oliva ++ ++ * testsuite/20_util/from_chars/4.cc: Skip long double test06 ++ on x86_64-vxworks. ++ * testsuite/20_util/to_chars/long_double.cc: Xfail run on ++ x86_64-vxworks. ++ ++2023-05-30 Alexandre Oliva ++ ++ Backported from master: ++ 2023-05-25 Alexandre Oliva ++ ++ * testsuite/20_util/to_chars/long_double.cc: Expect execution ++ fail on x86-vxworks. ++ ++2023-05-30 Alexandre Oliva ++ ++ Backported from master: ++ 2023-05-05 Alexandre Oliva ++ ++ * testsuite/20_util/from_chars/4.cc: Skip long double test06 ++ on aarch64-vxworks. ++ * testsuite/20_util/to_chars/long_double.cc: Xfail run on ++ aarch64-vxworks. ++ ++2023-05-30 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-30 Matthias Kretz ++ ++ PR libstdc++/109822 ++ * include/experimental/bits/simd.h (to_native): Use int NTTP ++ as specified in PTS2. ++ (to_compatible): Likewise. Add missing tag to call mask ++ generator ctor. ++ * testsuite/experimental/simd/pr109822_cast_functions.cc: New ++ test. ++ ++2023-05-30 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-30 Matthias Kretz ++ ++ * testsuite/experimental/simd/tests/integer_operators.cc: ++ Compute expected value differently to avoid getting turned into ++ a vector shift. ++ ++2023-05-30 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-30 Matthias Kretz ++ ++ * testsuite/experimental/simd/tests/operator_cvt.cc: Make long ++ double <-> (u)long conversion tests conditional on sizeof(long ++ double) and sizeof(long). ++ ++2023-05-30 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-26 Matthias Kretz ++ ++ * include/experimental/bits/simd_ppc.h (_S_bit_shift_left): ++ Negative __y is UB, so prefer signed compare. ++ ++2023-05-24 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-24 Matthias Kretz ++ ++ PR libstdc++/109949 ++ * include/experimental/bits/simd.h (__intrinsic_type): If ++ __ALTIVEC__ is defined, map gnu::vector_size types to their ++ corresponding __vector T types without losing unsignedness of ++ integer types. Also prefer long long over long. ++ * include/experimental/bits/simd_ppc.h (_S_popcount): Cast mask ++ object to the expected unsigned vector type. ++ ++2023-05-24 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-24 Matthias Kretz ++ ++ PR libstdc++/109261 ++ * include/experimental/bits/simd.h (__intrinsic_type): ++ Specialize __intrinsic_type and ++ __intrinsic_type in any case, but provide the member ++ type only with __aarch64__. ++ ++2023-05-24 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-24 Matthias Kretz ++ ++ PR libstdc++/109261 ++ * include/experimental/bits/simd_neon.h (_S_reduce): Add ++ constexpr and make NEON implementation conditional on ++ not __builtin_is_constant_evaluated. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-23 Matthias Kretz ++ ++ PR libstdc++/109261 ++ * include/experimental/bits/simd.h (_SimdWrapper::_M_set): ++ Avoid vector builtin subscripting in constant expressions. ++ (resizing_simd_cast): Avoid memcpy if constant_evaluated. ++ (const_where_expression, where_expression, where) ++ (__extract_part, simd_mask, _SimdIntOperators, simd): Add either ++ _GLIBCXX_SIMD_CONSTEXPR (on public APIs), or constexpr (on ++ internal APIs). ++ * include/experimental/bits/simd_builtin.h (__vector_permute) ++ (__vector_shuffle, __extract_part, _GnuTraits::_SimdCastType1) ++ (_GnuTraits::_SimdCastType2, _SimdImplBuiltin) ++ (_MaskImplBuiltin::_S_store): Add constexpr. ++ (_CommonImplBuiltin::_S_store_bool_array) ++ (_SimdImplBuiltin::_S_load, _SimdImplBuiltin::_S_store) ++ (_SimdImplBuiltin::_S_reduce, _MaskImplBuiltin::_S_load): Add ++ constant_evaluated case. ++ * include/experimental/bits/simd_fixed_size.h ++ (_S_masked_load): Reword comment. ++ (__tuple_element_meta, __make_meta, _SimdTuple::_M_apply_r) ++ (_SimdTuple::_M_subscript_read, _SimdTuple::_M_subscript_write) ++ (__make_simd_tuple, __optimize_simd_tuple, __extract_part) ++ (__autocvt_to_simd, _Fixed::__traits::_SimdBase) ++ (_Fixed::__traits::_SimdCastType, _SimdImplFixedSize): Add ++ constexpr. ++ (_SimdTuple::operator[], _M_set): Add constexpr and add ++ constant_evaluated case. ++ (_MaskImplFixedSize::_S_load): Add constant_evaluated case. ++ * include/experimental/bits/simd_scalar.h: Add constexpr. ++ * include/experimental/bits/simd_x86.h (_CommonImplX86): Add ++ constexpr and add constant_evaluated case. ++ (_SimdImplX86::_S_equal_to, _S_not_equal_to, _S_less) ++ (_S_less_equal): Value-initialize to satisfy constexpr ++ evaluation. ++ (_MaskImplX86::_S_load): Add constant_evaluated case. ++ (_MaskImplX86::_S_store): Add constexpr and constant_evaluated ++ case. Value-initialize local variables. ++ (_MaskImplX86::_S_logical_and, _S_logical_or, _S_bit_not) ++ (_S_bit_and, _S_bit_or, _S_bit_xor): Add constant_evaluated ++ case. ++ * testsuite/experimental/simd/pr109261_constexpr_simd.cc: New ++ test. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-05-22 Matthias Kretz ++ ++ * include/experimental/bits/simd_builtin.h (_S_fpclassify): Move ++ __infn into #ifdef'ed block. ++ * testsuite/experimental/simd/tests/fpclassify.cc: Declare ++ constants only when used. ++ * testsuite/experimental/simd/tests/frexp.cc: Likewise. ++ * testsuite/experimental/simd/tests/logarithm.cc: Likewise. ++ * testsuite/experimental/simd/tests/trunc_ceil_floor.cc: ++ Likewise. ++ * testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc: ++ Move totest and expect1 into #ifdef'ed block. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-03-28 Matthias Kretz ++ ++ * include/experimental/bits/simd.h (is_simd_flag_type): New. ++ (_IsSimdFlagType): New. ++ (copy_from, copy_to, load ctors): Constrain _Flags using ++ _IsSimdFlagType. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-03-28 Matthias Kretz ++ ++ * include/experimental/bits/simd_x86.h (_SimdImplX86): Use ++ _Base::_S_divides if the optimized _S_divides function is hidden ++ via the preprocessor. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-03-21 Matthias Kretz ++ ++ * include/experimental/bits/simd_detail.h: Don't declare the ++ simd API as constexpr with Clang. ++ * include/experimental/bits/simd_x86.h (__movm): New. ++ (_S_blend_avx512): Resolve FIXME. Implement blend using __movm ++ and ?:. ++ (_SimdImplX86::_S_masked_unary): Clang does not implement the ++ same builtins. Implement the function using __movm, ?:, and - ++ operators on vector_size types instead. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-02-24 Matthias Kretz ++ ++ * include/experimental/bits/simd.h: Line breaks and indenting ++ fixed to follow the libstdc++ standard. ++ * include/experimental/bits/simd_builtin.h: Likewise. ++ * include/experimental/bits/simd_fixed_size.h: Likewise. ++ * include/experimental/bits/simd_neon.h: Likewise. ++ * include/experimental/bits/simd_ppc.h: Likewise. ++ * include/experimental/bits/simd_scalar.h: Likewise. ++ * include/experimental/bits/simd_x86.h: Likewise. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-02-24 Matthias Kretz ++ ++ PR libstdc++/108030 ++ * include/experimental/bits/simd_fixed_size.h ++ (_SimdImplFixedSize::_S_broadcast): Replace inline with ++ _GLIBCXX_SIMD_INTRINSIC. ++ (_SimdImplFixedSize::_S_generate): Likewise. ++ (_SimdImplFixedSize::_S_load): Likewise. ++ (_SimdImplFixedSize::_S_masked_load): Likewise. ++ (_SimdImplFixedSize::_S_store): Likewise. ++ (_SimdImplFixedSize::_S_masked_store): Likewise. ++ (_SimdImplFixedSize::_S_min): Likewise. ++ (_SimdImplFixedSize::_S_max): Likewise. ++ (_SimdImplFixedSize::_S_complement): Likewise. ++ (_SimdImplFixedSize::_S_unary_minus): Likewise. ++ (_SimdImplFixedSize::_S_plus): Likewise. ++ (_SimdImplFixedSize::_S_minus): Likewise. ++ (_SimdImplFixedSize::_S_multiplies): Likewise. ++ (_SimdImplFixedSize::_S_divides): Likewise. ++ (_SimdImplFixedSize::_S_modulus): Likewise. ++ (_SimdImplFixedSize::_S_bit_and): Likewise. ++ (_SimdImplFixedSize::_S_bit_or): Likewise. ++ (_SimdImplFixedSize::_S_bit_xor): Likewise. ++ (_SimdImplFixedSize::_S_bit_shift_left): Likewise. ++ (_SimdImplFixedSize::_S_bit_shift_right): Likewise. ++ (_SimdImplFixedSize::_S_remquo): Add inline keyword (to be ++ explicit about not always-inline, yet). ++ (_SimdImplFixedSize::_S_isinf): Likewise. ++ (_SimdImplFixedSize::_S_isfinite): Likewise. ++ (_SimdImplFixedSize::_S_isnan): Likewise. ++ (_SimdImplFixedSize::_S_isnormal): Likewise. ++ (_SimdImplFixedSize::_S_signbit): Likewise. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-02-24 Matthias Kretz ++ ++ PR libstdc++/108856 ++ * include/experimental/bits/simd_builtin.h ++ (_SimdImplBuiltin::_S_masked_unary): More efficient ++ implementation of masked inc-/decrement for integers and floats ++ without AVX2. ++ * include/experimental/bits/simd_x86.h ++ (_SimdImplX86::_S_masked_unary): New. Use AVX512 masked subtract ++ builtins for masked inc-/decrement. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-02-23 Matthias Kretz ++ ++ * testsuite/experimental/simd/tests/reductions.cc: Introduce ++ max_distance as the type-dependent max error. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-02-23 Matthias Kretz ++ ++ PR libstdc++/108030 ++ * include/experimental/bits/simd_detail.h ++ (_GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA): Define as empty for ++ __clang__. ++ ++2023-05-23 Matthias Kretz ++ ++ Backported from master: ++ 2023-02-16 Matthias Kretz ++ ++ PR libstdc++/108030 ++ * include/experimental/bits/simd_detail.h: Define ++ _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA. ++ * include/experimental/bits/simd.h: Annotate lambdas with ++ _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA. ++ * include/experimental/bits/simd_builtin.h: Ditto. ++ * include/experimental/bits/simd_converter.h: Ditto. ++ * include/experimental/bits/simd_fixed_size.h: Ditto. ++ * include/experimental/bits/simd_math.h: Ditto. ++ * include/experimental/bits/simd_neon.h: Ditto. ++ * include/experimental/bits/simd_x86.h: Ditto. ++ ++2023-05-16 Jonathan Wakely ++ ++ Backported from master: ++ 2022-11-28 Jonathan Wakely ++ ++ PR libstdc++/107801 ++ * src/c++17/memory_resource.cc (chunk::_M_bytes): Change type ++ from uint32_t to bitset::size_type. Adjust static assertion. ++ (__pool_resource::_Pool::replenish): Cast to size_t after ++ multiplication instead of before. ++ (__pool_resource::_M_alloc_pools): Ensure both arguments to ++ std::max have type size_t. ++ ++2023-05-11 Jonathan Wakely ++ ++ Backported from master: ++ 2022-11-16 Jonathan Wakely ++ ++ * python/libstdcxx/v6/printers.py (StdExpAnyPrinter): Make ++ expansion of std::string in manager name more robust. ++ + 2023-05-08 Release Manager + + * GCC 12.3.0 released. +diff --git a/libstdc++-v3/acinclude.m4 b/libstdc++-v3/acinclude.m4 +index 04f2153fce3..321065aff72 100644 +--- a/libstdc++-v3/acinclude.m4 ++++ b/libstdc++-v3/acinclude.m4 +@@ -4924,7 +4924,7 @@ AC_DEFUN([GLIBCXX_ENABLE_BACKTRACE], [ + + # Most of this is adapted from libsanitizer/configure.ac + +- BACKTRACE_CPPFLAGS= ++ BACKTRACE_CPPFLAGS="-D_GNU_SOURCE" + + # libbacktrace only needs atomics for int, which we've already tested + if test "$glibcxx_cv_atomic_int" = "yes"; then +@@ -4952,8 +4952,11 @@ AC_DEFUN([GLIBCXX_ENABLE_BACKTRACE], [ + have_dl_iterate_phdr=no + else + # When built as a GCC target library, we can't do a link test. ++ ac_save_CPPFLAGS="$CPPFLAGS" ++ CPPFLAGS="$CPPFLAGS -D_GNU_SOURCE" + AC_EGREP_HEADER([dl_iterate_phdr], [link.h], [have_dl_iterate_phdr=yes], + [have_dl_iterate_phdr=no]) ++ CPPFLAGS="$ac_save_CPPFLAGS" + fi + if test "$have_dl_iterate_phdr" = "yes"; then + BACKTRACE_CPPFLAGS="$BACKTRACE_CPPFLAGS -DHAVE_DL_ITERATE_PHDR=1" +diff --git a/libstdc++-v3/configure b/libstdc++-v3/configure +index c07e2756974..b371f422ff3 100755 +--- a/libstdc++-v3/configure ++++ b/libstdc++-v3/configure +@@ -77316,7 +77316,7 @@ fi + + # Most of this is adapted from libsanitizer/configure.ac + +- BACKTRACE_CPPFLAGS= ++ BACKTRACE_CPPFLAGS="-D_GNU_SOURCE" + + # libbacktrace only needs atomics for int, which we've already tested + if test "$glibcxx_cv_atomic_int" = "yes"; then +@@ -77399,6 +77399,8 @@ done + have_dl_iterate_phdr=no + else + # When built as a GCC target library, we can't do a link test. ++ ac_save_CPPFLAGS="$CPPFLAGS" ++ CPPFLAGS="$CPPFLAGS -D_GNU_SOURCE" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext + /* end confdefs.h. */ + #include +@@ -77412,6 +77414,7 @@ else + fi + rm -f conftest* + ++ CPPFLAGS="$ac_save_CPPFLAGS" + fi + if test "$have_dl_iterate_phdr" = "yes"; then + BACKTRACE_CPPFLAGS="$BACKTRACE_CPPFLAGS -DHAVE_DL_ITERATE_PHDR=1" +diff --git a/libstdc++-v3/doc/html/manual/api.html b/libstdc++-v3/doc/html/manual/api.html +index 604380e0136..fd6420a9e2c 100644 +--- a/libstdc++-v3/doc/html/manual/api.html ++++ b/libstdc++-v3/doc/html/manual/api.html +@@ -370,6 +370,11 @@ Calling a std::bind result as volatile was deprecated + For the non-default --enable-symvers=gnu-versioned-namespace + configuration, the shared library SONAME has been changed to + libstdc++.so.8. ++

++ The extension allowing containers to be instantiated with an allocator ++ that doesn't match the container's value type is no longer allowed in ++ strict (-std=c++NN) modes, only in ++ -std=gnu++NN modes. +

9

+ C++17 header + <memory_resource> +@@ -425,6 +430,10 @@ Calling a std::bind result as volatile was deprecated + and + <stop_token> + added. ++

++ The extension allowing containers to be instantiated with an allocator ++ that doesn't match the container's value type is no longer allowed in ++ C++20 mode, even in non-strict -std=gnu++20 mode. +

11

+ The --enable-cheaders=c_std configuration + was deprecated. +diff --git a/libstdc++-v3/doc/html/manual/configure.html b/libstdc++-v3/doc/html/manual/configure.html +index 31c4da8a5e3..dfd7ad63bca 100644 +--- a/libstdc++-v3/doc/html/manual/configure.html ++++ b/libstdc++-v3/doc/html/manual/configure.html +@@ -38,9 +38,14 @@ + 

+    --with-gxx-include-dir=/foo/H-x86-gcc-3-c-gxx-inc/include/4.4-20090404
--enable-cstdio

This is an abbreviated form of '--enable-cstdio=stdio' + (described next). +-

--enable-cstdio=OPTION

Select a target-specific I/O package. At the moment, the only +- choice is to use 'stdio', a generic "C" abstraction. +- The default is 'stdio'. This option can change the library ABI. ++

--enable-cstdio=OPTION

Select a target-specific I/O package. The choices are 'stdio' ++ which is a generic abstraction using POSIX file I/O APIs ++ (read, write, ++ lseek, etc.), and 'stdio_pure' which is similar ++ but only uses standard C file I/O APIs (fread, ++ fwrite, fseek, etc.). ++ The 'stdio_posix' choice is a synonym for 'stdio'. ++ The default is 'stdio'. This option can change the library ABI. +

--enable-clocale

This is an abbreviated form of '--enable-clocale=generic' + (described next). +

--enable-clocale=OPTION

Select a target-specific underlying locale package. The +@@ -203,8 +208,8 @@ + C++ includes. If enabled (as by default), and the compiler + seems capable of passing the simple sanity checks thrown at + it, try to build stdc++.h.gch as part of the make process. +- In addition, this generated file is used later on (by appending +- --include bits/stdc++.h to CXXFLAGS) when running the ++ In addition, this generated file is used later on (by appending ++ -include bits/stdc++.h to CXXFLAGS) when running the + testsuite. +

--enable-extern-template[default]

Use extern template to pre-instantiate all required + specializations for certain types defined in the standard libraries. +diff --git a/libstdc++-v3/doc/html/manual/status.html b/libstdc++-v3/doc/html/manual/status.html +index e8da941038d..76d7d58a831 100644 +--- a/libstdc++-v3/doc/html/manual/status.html ++++ b/libstdc++-v3/doc/html/manual/status.html +@@ -1325,10 +1325,10 @@ or any notes about the implementation. + 9.1 __cpp_lib_type_identity >= 201806L (since 9.4, see Note 1) unwrap_ref_decay and unwrap_reference + + P0318R1 +- 9.1 __cpp_lib_unwrap_ref >= 201811L (since 9.4, see Note 1) Improving Completeness Requirements for Type Traits ++ 9.1 __cpp_lib_unwrap_ref >= 201811L (since 9.4, see Note 1) Improving Completeness Requirements for Type Traits + + P1285R0 +- Partial   Missing feature test macros ++ — Most misuses are diagnosed, but not all. Missing feature test macros + + P1353R0 + 9.1   Making std::underlying_type SFINAE-friendly +@@ -1411,18 +1411,18 @@ or any notes about the implementation. + 10.1   Ranges Design Cleanup + + P1252R2 +- 10.1   Avoid template bloat for safe_ranges in combination with ‘subrange-y’ view adaptors. ++ 10.1   Avoid template bloat for safe_ranges in combination with ‘subrange-y’ view adaptors. + + P1739R4 +-   ++ 12.1   + Time, dates, calendars, time zones +- Extending chrono to Calendars and Time Zones ++ Extending chrono to Calendars and Time Zones + + P0355R7 +-   __cpp_lib_chrono >= 201803L Miscellaneous minor fixes for chrono ++ (see Note 2) __cpp_lib_chrono >= 201803L Miscellaneous minor fixes for chrono + + P1466R3 +-   __cpp_lib_chrono >= 201907L <chrono> zero(), min(), and max() should be noexcept ++ (see Note 2) __cpp_lib_chrono >= 201907L <chrono> zero(), min(), and max() should be noexcept + + P0972R0 + 9.1   +@@ -1467,10 +1467,10 @@ or any notes about the implementation. + String Prefix and Suffix Checking + + P0457R2 +- 9.1 __cpp_lib_starts_ends_with >= 201711L (since 9.4, see Note 1) Update The Reference To The Unicode Standard ++ 9.1 __cpp_lib_starts_ends_with >= 201711L (since 9.4, see Note 1) Update The Reference To The Unicode Standard + + P1025R1 +-   ++ —  + Containers + span: bounds-safe views for sequences of objects + +@@ -1492,10 +1492,10 @@ or any notes about the implementation. + 10.1 __cpp_lib_to_array >= 201907L Checking for Existence of an Element in Associative Containers + + P0458R2 +- 9.1   Comparing Unordered Containers ++ 9.1   Comparing Unordered Containers + + P0809R0 +-   Heterogeneous lookup for unordered containers ++ —   Heterogeneous lookup for unordered containers + + P0919R3 + 11.1 __cpp_lib_generic_unordered_lookup >= 201811 Refinement Proposal for P0919 +@@ -1567,7 +1567,7 @@ or any notes about the implementation. + 9.1   Thou Shalt Not Specialize std Function Templates! + + P0551R3 +-   Bit-casting object representations ++ These changes will not be implemented. Bit-casting object representations + + P0476R2 + 11.1 __cpp_lib_bit_cast >= 201806L Integral power-of-2 operations +@@ -1588,10 +1588,10 @@ or any notes about the implementation. + —   Add shift to <algorithm> + + P0769R2 +- 10.1 __cpp_lib_shift >= 201806L Standard Library Specification in a Concepts and Contracts World ++ 10.1 __cpp_lib_shift >= 201806L Standard Library Specification in a Concepts and Contracts World + + P0788R3 +-   explicit(bool) ++ —   explicit(bool) + + P0892R2 + —   Eradicating unnecessarily explicit default constructors from the standard library +@@ -1627,10 +1627,10 @@ or any notes about the implementation. + 7.1   Editorial Guidance for merging P0019r8 and P0528r3 + + P1123R0 +- —   Cleaning up Clause 20 ++ —   Cleaning up Clause 20 + + P1148R0 +-   Completing the Rebase of Library Fundamentals, Version 3, Working Draft ++ —   Completing the Rebase of Library Fundamentals, Version 3, Working Draft + + P1210R0 +   Alternative Wording for P0907R4 Signed Integers are Two's Complement +@@ -1666,13 +1666,13 @@ or any notes about the implementation. + + + P1463R1 +- 10.1   ++ 10.1   + Mandating the Standard Library: + Clause 22 - Iterators library + + + P1464R1 +-   Make create_directory() Intuitive ++ —   Make create_directory() Intuitive + + P1164R1 + +@@ -1708,6 +1708,9 @@ or any notes about the implementation. + Note 1: This feature is supported in older releases but the + __cpp_lib macro is not defined to the right value + (or not defined at all) until the version shown in parentheses. ++

++Note 2: The C++20 calendar types are supported since 11.1, ++time zones, UTC, formatting and parsing are not supported. +

C++ 2023

+ In this implementation the -std=gnu++23 or + -std=c++23 flag must be used to enable language +diff --git a/libstdc++-v3/doc/xml/manual/configure.xml b/libstdc++-v3/doc/xml/manual/configure.xml +index 8c26acc95a7..d2a866c4fc2 100644 +--- a/libstdc++-v3/doc/xml/manual/configure.xml ++++ b/libstdc++-v3/doc/xml/manual/configure.xml +@@ -74,9 +74,14 @@ + + + --enable-cstdio=OPTION +- Select a target-specific I/O package. At the moment, the only +- choice is to use 'stdio', a generic "C" abstraction. +- The default is 'stdio'. This option can change the library ABI. ++ Select a target-specific I/O package. The choices are 'stdio' ++ which is a generic abstraction using POSIX file I/O APIs ++ (read, write, ++ lseek, etc.), and 'stdio_pure' which is similar ++ but only uses standard C file I/O APIs (fread, ++ fwrite, fseek, etc.). ++ The 'stdio_posix' choice is a synonym for 'stdio'. ++ The default is 'stdio'. This option can change the library ABI. + + + +@@ -336,8 +341,8 @@ + C++ includes. If enabled (as by default), and the compiler + seems capable of passing the simple sanity checks thrown at + it, try to build stdc++.h.gch as part of the make process. +- In addition, this generated file is used later on (by appending +- --include bits/stdc++.h to CXXFLAGS) when running the ++ In addition, this generated file is used later on (by appending ++ -include bits/stdc++.h to CXXFLAGS) when running the + testsuite. + + +diff --git a/libstdc++-v3/doc/xml/manual/evolution.xml b/libstdc++-v3/doc/xml/manual/evolution.xml +index 82936189179..9259c43fb19 100644 +--- a/libstdc++-v3/doc/xml/manual/evolution.xml ++++ b/libstdc++-v3/doc/xml/manual/evolution.xml +@@ -915,6 +915,13 @@ Calling a std::bind result as volatile was deprecated for C++17. + libstdc++.so.8. + + ++ ++ The extension allowing containers to be instantiated with an allocator ++ that doesn't match the container's value type is no longer allowed in ++ strict () modes, only in ++ modes. ++ ++ + + +

<constant>9</constant> +@@ -998,6 +1005,12 @@ Calling a std::bind result as volatile was deprecated for C++17. + added. + + ++ ++ The extension allowing containers to be instantiated with an allocator ++ that doesn't match the container's value type is no longer allowed in ++ C++20 mode, even in non-strict mode. ++ ++ +
+ +
<constant>11</constant> +diff --git a/libstdc++-v3/doc/xml/manual/status_cxx2020.xml b/libstdc++-v3/doc/xml/manual/status_cxx2020.xml +index a13445f2246..d85fa59ae59 100644 +--- a/libstdc++-v3/doc/xml/manual/status_cxx2020.xml ++++ b/libstdc++-v3/doc/xml/manual/status_cxx2020.xml +@@ -251,14 +251,13 @@ or any notes about the implementation. + + + +- + Improving Completeness Requirements for Type Traits + + + P1285R0 + +- Partial +- ++ — ++ Most misuses are diagnosed, but not all. + + + +@@ -542,13 +541,12 @@ or any notes about the implementation. + + + +- + Avoid template bloat for safe_ranges in combination with ‘subrange-y’ view adaptors. + + + P1739R4 + +- ++ 12.1 + + + +@@ -560,24 +558,23 @@ or any notes about the implementation. + + + +- ++ + Extending chrono to Calendars and Time Zones + + + P0355R7 + +- ++ (see Note 2) + __cpp_lib_chrono >= 201803L + + + +- + Miscellaneous minor fixes for chrono + + + P1466R3 + +- ++ (see Note 2) + __cpp_lib_chrono >= 201907L + + +@@ -717,13 +714,12 @@ or any notes about the implementation. + + + +- + Update The Reference To The Unicode Standard + + + P1025R1 + +- ++ — + + + +@@ -797,13 +793,12 @@ or any notes about the implementation. + + + +- + Comparing Unordered Containers + + + P0809R0 + +- ++ — + + + +@@ -1030,7 +1025,7 @@ or any notes about the implementation. + P0551R3 + + +- ++ These changes will not be implemented. + + + +@@ -1104,13 +1099,12 @@ or any notes about the implementation. + + + +- + Standard Library Specification in a Concepts and Contracts World + + + P0788R3 + +- ++ — + + + +@@ -1235,13 +1229,12 @@ or any notes about the implementation. + + + +- + Cleaning up Clause 20 + + + P1148R0 + +- ++ — + + + +@@ -1332,7 +1325,6 @@ or any notes about the implementation. + + + +- + + Mandating the Standard Library: + Clause 22 - Iterators library +@@ -1341,7 +1333,7 @@ or any notes about the implementation. + + P1464R1 + +- ++ — + + + +@@ -1450,4 +1442,9 @@ Note 1: This feature is supported in older releases but the + (or not defined at all) until the version shown in parentheses. + + ++ ++Note 2: The C++20 calendar types are supported since 11.1, ++time zones, UTC, formatting and parsing are not supported. ++ ++ +
+diff --git a/libstdc++-v3/include/bits/basic_string.tcc b/libstdc++-v3/include/bits/basic_string.tcc +index 0696b96604c..48fa28e6466 100644 +--- a/libstdc++-v3/include/bits/basic_string.tcc ++++ b/libstdc++-v3/include/bits/basic_string.tcc +@@ -529,6 +529,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + { + const size_type __nleft = (__p + __len1) - __s; + this->_S_move(__p, __s, __nleft); ++ // Tell the middle-end that the copy can't overlap ++ // (PR105651). ++ if (__len2 < __nleft) ++ __builtin_unreachable(); + this->_S_copy(__p + __nleft, __p + __len2, + __len2 - __nleft); + } +diff --git a/libstdc++-v3/include/bits/fs_dir.h b/libstdc++-v3/include/bits/fs_dir.h +index bec2b7674ef..84e8e8984e8 100644 +--- a/libstdc++-v3/include/bits/fs_dir.h ++++ b/libstdc++-v3/include/bits/fs_dir.h +@@ -433,7 +433,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11 + // _GLIBCXX_RESOLVE_LIB_DEFECTS + // 3719. Directory iterators should be usable with default sentinel + bool operator==(default_sentinel_t) const noexcept +- { return !_M_dir; } ++ { return *this == directory_iterator(); } + #endif + + #if __cpp_impl_three_way_comparison < 201907L +@@ -541,7 +541,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11 + // _GLIBCXX_RESOLVE_LIB_DEFECTS + // 3719. Directory iterators should be usable with default sentinel + bool operator==(default_sentinel_t) const noexcept +- { return !_M_dirs; } ++ { return *this == recursive_directory_iterator(); } + #endif + + #if __cpp_impl_three_way_comparison < 201907L +diff --git a/libstdc++-v3/include/bits/hashtable.h b/libstdc++-v3/include/bits/hashtable.h +index edc151ef15b..1a505fff089 100644 +--- a/libstdc++-v3/include/bits/hashtable.h ++++ b/libstdc++-v3/include/bits/hashtable.h +@@ -1055,6 +1055,20 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + return { __n, this->_M_node_allocator() }; + } + ++ // Only use the possibly cached node's hash code if its hash function ++ // _H2 matches _Hash and is stateless. Otherwise recompute it using _Hash. ++ template ++ __hash_code ++ _M_src_hash_code(const _H2&, const key_type& __k, ++ const __node_value_type& __src_n) const ++ { ++ if constexpr (std::is_same_v<_H2, _Hash>) ++ if constexpr (std::is_empty_v<_Hash>) ++ return this->_M_hash_code(__src_n); ++ ++ return this->_M_hash_code(__k); ++ } ++ + public: + // Extract a node. + node_type +@@ -1092,7 +1106,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + auto __pos = __i++; + const key_type& __k = _ExtractKey{}(*__pos); + __hash_code __code +- = this->_M_hash_code(__src.hash_function(), *__pos._M_cur); ++ = _M_src_hash_code(__src.hash_function(), __k, *__pos._M_cur); + size_type __bkt = _M_bucket_index(__code); + if (_M_find_node(__bkt, __k, __code) == nullptr) + { +@@ -1120,8 +1134,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + for (auto __i = __src.cbegin(), __end = __src.cend(); __i != __end;) + { + auto __pos = __i++; ++ const key_type& __k = _ExtractKey{}(*__pos); + __hash_code __code +- = this->_M_hash_code(__src.hash_function(), *__pos._M_cur); ++ = _M_src_hash_code(__src.hash_function(), __k, *__pos._M_cur); + auto __nh = __src.extract(__pos); + __hint = _M_insert_multi_node(__hint, __code, __nh._M_ptr)._M_cur; + __nh._M_ptr = nullptr; +diff --git a/libstdc++-v3/include/bits/hashtable_policy.h b/libstdc++-v3/include/bits/hashtable_policy.h +index 799c3e986b4..f692804782c 100644 +--- a/libstdc++-v3/include/bits/hashtable_policy.h ++++ b/libstdc++-v3/include/bits/hashtable_policy.h +@@ -291,18 +291,22 @@ namespace __detail + + __gnu_cxx::__aligned_buffer<_Value> _M_storage; + ++ [[__gnu__::__always_inline__]] + _Value* + _M_valptr() noexcept + { return _M_storage._M_ptr(); } + ++ [[__gnu__::__always_inline__]] + const _Value* + _M_valptr() const noexcept + { return _M_storage._M_ptr(); } + ++ [[__gnu__::__always_inline__]] + _Value& + _M_v() noexcept + { return *_M_valptr(); } + ++ [[__gnu__::__always_inline__]] + const _Value& + _M_v() const noexcept + { return *_M_valptr(); } +@@ -1279,19 +1283,6 @@ namespace __detail + return _M_hash()(__k); + } + +- __hash_code +- _M_hash_code(const _Hash&, +- const _Hash_node_value<_Value, true>& __n) const +- { return __n._M_hash_code; } +- +- // Compute hash code using _Hash as __n _M_hash_code, if present, was +- // computed using _H2. +- template +- __hash_code +- _M_hash_code(const _H2&, +- const _Hash_node_value<_Value, __cache_hash_code>& __n) const +- { return _M_hash_code(_ExtractKey{}(__n._M_v())); } +- + __hash_code + _M_hash_code(const _Hash_node_value<_Value, false>& __n) const + { return _M_hash_code(_ExtractKey{}(__n._M_v())); } +diff --git a/libstdc++-v3/include/bits/utility.h b/libstdc++-v3/include/bits/utility.h +index e0e40309a6d..180866e3581 100644 +--- a/libstdc++-v3/include/bits/utility.h ++++ b/libstdc++-v3/include/bits/utility.h +@@ -173,7 +173,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + #if __has_builtin(__make_integer_seq) + = __make_integer_seq; + #else +- = integer_sequence<_Tp, __integer_pack(_Num)...>; ++ = integer_sequence<_Tp, __integer_pack(_Tp(_Num))...>; + #endif + + /// Alias template index_sequence +diff --git a/libstdc++-v3/include/experimental/bits/fs_path.h b/libstdc++-v3/include/experimental/bits/fs_path.h +index ba6acb2158d..c13195a6ba9 100644 +--- a/libstdc++-v3/include/experimental/bits/fs_path.h ++++ b/libstdc++-v3/include/experimental/bits/fs_path.h +@@ -1049,7 +1049,7 @@ namespace __detail + inline std::basic_string<_CharT, _Traits, _Allocator> + path::string(const _Allocator& __a) const + { +- if _GLIBCXX_CONSTEXPR (is_same<_CharT, value_type>::value) ++ if _GLIBCXX17_CONSTEXPR (is_same<_CharT, value_type>::value) + return { _M_pathname.begin(), _M_pathname.end(), __a }; + + using _WString = basic_string<_CharT, _Traits, _Allocator>; +diff --git a/libstdc++-v3/include/experimental/bits/simd.h b/libstdc++-v3/include/experimental/bits/simd.h +index 7c5a32f6e95..b18ce9d34a2 100644 +--- a/libstdc++-v3/include/experimental/bits/simd.h ++++ b/libstdc++-v3/include/experimental/bits/simd.h +@@ -180,10 +180,7 @@ struct vector_aligned_tag + template + _GLIBCXX_SIMD_INTRINSIC static constexpr _Up* + _S_apply(_Up* __ptr) +- { +- return static_cast<_Up*>( +- __builtin_assume_aligned(__ptr, _S_alignment<_Tp, _Up>)); +- } ++ { return static_cast<_Up*>(__builtin_assume_aligned(__ptr, _S_alignment<_Tp, _Up>)); } + }; + + template struct overaligned_tag +@@ -288,13 +285,15 @@ namespace __detail + // expression. math_errhandling may expand to an extern symbol, in which case a constexpr value + // must be guessed. + template +- constexpr bool __handle_fpexcept_impl(int) ++ constexpr bool ++ __handle_fpexcept_impl(int) + { return math_errhandling & MATH_ERREXCEPT; } + #endif + + // Fallback if math_errhandling doesn't work: with fast-math assume floating-point exceptions are + // ignored, otherwise implement correct exception behavior. +- constexpr bool __handle_fpexcept_impl(float) ++ constexpr bool ++ __handle_fpexcept_impl(float) + { + #if defined __FAST_MATH__ + return false; +@@ -609,28 +608,34 @@ template + operator&(_Ip __rhs) const + { + return __generate_from_n_evaluations<_Np, _Ip>( +- [&](auto __i) { return __rhs._M_data[__i] & _M_data[__i]; }); ++ [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ return __rhs._M_data[__i] & _M_data[__i]; ++ }); + } + + _GLIBCXX_SIMD_INTRINSIC constexpr _Ip + operator|(_Ip __rhs) const + { + return __generate_from_n_evaluations<_Np, _Ip>( +- [&](auto __i) { return __rhs._M_data[__i] | _M_data[__i]; }); ++ [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ return __rhs._M_data[__i] | _M_data[__i]; ++ }); + } + + _GLIBCXX_SIMD_INTRINSIC constexpr _Ip + operator^(_Ip __rhs) const + { + return __generate_from_n_evaluations<_Np, _Ip>( +- [&](auto __i) { return __rhs._M_data[__i] ^ _M_data[__i]; }); ++ [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ return __rhs._M_data[__i] ^ _M_data[__i]; ++ }); + } + + _GLIBCXX_SIMD_INTRINSIC constexpr _Ip + operator~() const + { + return __generate_from_n_evaluations<_Np, _Ip>( +- [&](auto __i) { return ~_M_data[__i]; }); ++ [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return ~_M_data[__i]; }); + } + }; + return _Ip{}; +@@ -743,8 +748,7 @@ template + // __invoke_ub{{{ + template + [[noreturn]] _GLIBCXX_SIMD_ALWAYS_INLINE void +- __invoke_ub([[maybe_unused]] const char* __msg, +- [[maybe_unused]] const _Args&... __args) ++ __invoke_ub([[maybe_unused]] const char* __msg, [[maybe_unused]] const _Args&... __args) + { + #ifdef _GLIBCXX_DEBUG_UB + __builtin_fprintf(stderr, __msg, __args...); +@@ -789,11 +793,14 @@ class _ExactBool + const bool _M_data; + + public: +- _GLIBCXX_SIMD_INTRINSIC constexpr _ExactBool(bool __b) : _M_data(__b) {} ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _ExactBool(bool __b) : _M_data(__b) {} + + _ExactBool(int) = delete; + +- _GLIBCXX_SIMD_INTRINSIC constexpr operator bool() const { return _M_data; } ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ operator bool() const ++ { return _M_data; } + }; + + // }}} +@@ -1391,7 +1398,7 @@ template + operator^=(const _BitMask& __b) & noexcept + { + __execute_n_times<_S_array_size>( +- [&](auto __i) { _M_bits[__i] ^= __b._M_bits[__i]; }); ++ [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { _M_bits[__i] ^= __b._M_bits[__i]; }); + return *this; + } + +@@ -1399,7 +1406,7 @@ template + operator|=(const _BitMask& __b) & noexcept + { + __execute_n_times<_S_array_size>( +- [&](auto __i) { _M_bits[__i] |= __b._M_bits[__i]; }); ++ [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { _M_bits[__i] |= __b._M_bits[__i]; }); + return *this; + } + +@@ -1407,7 +1414,7 @@ template + operator&=(const _BitMask& __b) & noexcept + { + __execute_n_times<_S_array_size>( +- [&](auto __i) { _M_bits[__i] &= __b._M_bits[__i]; }); ++ [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { _M_bits[__i] &= __b._M_bits[__i]; }); + return *this; + } + +@@ -1482,8 +1489,7 @@ template + + // else, use GNU-style builtin vector types + template +- struct __vector_type_n<_Tp, _Np, +- enable_if_t<__is_vectorizable_v<_Tp> && _Np >= 2>> ++ struct __vector_type_n<_Tp, _Np, enable_if_t<__is_vectorizable_v<_Tp> && _Np >= 2>> + { + static constexpr size_t _S_Np2 = std::__bit_ceil(_Np * sizeof(_Tp)); + +@@ -1764,8 +1770,7 @@ template + // }}} + // __to_intrin {{{ + template , +- typename _R +- = __intrinsic_type_t> ++ typename _R = __intrinsic_type_t> + _GLIBCXX_SIMD_INTRINSIC constexpr _R + __to_intrin(_Tp __x) + { +@@ -1786,9 +1791,7 @@ template , + template + _GLIBCXX_SIMD_INTRINSIC constexpr __vector_type_t<_Tp, sizeof...(_Args)> + __make_vector(const _Args&... __args) +- { +- return __vector_type_t<_Tp, sizeof...(_Args)>{static_cast<_Tp>(__args)...}; +- } ++ { return __vector_type_t<_Tp, sizeof...(_Args)>{static_cast<_Tp>(__args)...}; } + + // }}} + // __vector_broadcast{{{ +@@ -1807,10 +1810,7 @@ template + template + _GLIBCXX_SIMD_INTRINSIC constexpr __vector_type_t<_Tp, _Np> + __generate_vector_impl(_Gp&& __gen, index_sequence<_I...>) +- { +- return __vector_type_t<_Tp, _Np>{ +- static_cast<_Tp>(__gen(_SizeConstant<_I>()))...}; +- } ++ { return __vector_type_t<_Tp, _Np>{ static_cast<_Tp>(__gen(_SizeConstant<_I>()))...}; } + + template , typename _Gp> + _GLIBCXX_SIMD_INTRINSIC constexpr _V +@@ -2023,8 +2023,7 @@ template > + // }}} + // __concat{{{ + template , +- typename _R = __vector_type_t> ++ typename _R = __vector_type_t> + constexpr _R + __concat(_Tp a_, _Tp b_) + { +@@ -2168,8 +2167,7 @@ template , +- typename _R = __vector_type_t> ++ typename _R = __vector_type_t> + _GLIBCXX_SIMD_INTRINSIC constexpr _R + __extract(_Tp __in) + { +@@ -2206,7 +2204,7 @@ template ( +- __x, [](auto... __entries) { ++ __x, [](auto... __entries) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { + return reinterpret_cast<_R>(_Up{__entries...}); + }); + } +@@ -2215,8 +2213,7 @@ template ::value_type>> ++ typename _R = __vector_type8_t::value_type>> + _GLIBCXX_SIMD_INTRINSIC constexpr _R + __lo64(_Tp __x) + { +@@ -2226,8 +2223,7 @@ template ::value_type>> ++ typename _R = __vector_type8_t::value_type>> + _GLIBCXX_SIMD_INTRINSIC constexpr _R + __hi64(_Tp __x) + { +@@ -2238,8 +2234,7 @@ template ::value_type>> ++ typename _R = __vector_type8_t::value_type>> + _GLIBCXX_SIMD_INTRINSIC constexpr _R + __hi64z([[maybe_unused]] _Tp __x) + { +@@ -2350,18 +2345,15 @@ template <> + // the following excludes bool via __is_vectorizable + #if _GLIBCXX_SIMD_HAVE_SSE + template +- struct __intrinsic_type<_Tp, _Bytes, +- enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 64>> ++ struct __intrinsic_type<_Tp, _Bytes, enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 64>> + { + static_assert(!is_same_v<_Tp, long double>, + "no __intrinsic_type support for long double on x86"); + +- static constexpr size_t _S_VBytes = _Bytes <= 16 ? 16 +- : _Bytes <= 32 ? 32 +- : 64; ++ static constexpr size_t _S_VBytes = _Bytes <= 16 ? 16 : _Bytes <= 32 ? 32 : 64; + + using type [[__gnu__::__vector_size__(_S_VBytes)]] +- = conditional_t, long long int, _Tp>; ++ = conditional_t, long long int, _Tp>; + }; + #endif // _GLIBCXX_SIMD_HAVE_SSE + +@@ -2377,15 +2369,21 @@ template <> + struct __intrinsic_type + { using type = float32x4_t; }; + +-#if _GLIBCXX_SIMD_HAVE_NEON_A64 + template <> + struct __intrinsic_type +- { using type = float64x1_t; }; ++ { ++#if _GLIBCXX_SIMD_HAVE_NEON_A64 ++ using type = float64x1_t; ++#endif ++ }; + + template <> + struct __intrinsic_type +- { using type = float64x2_t; }; ++ { ++#if _GLIBCXX_SIMD_HAVE_NEON_A64 ++ using type = float64x2_t; + #endif ++ }; + + #define _GLIBCXX_SIMD_ARM_INTRIN(_Bits, _Np) \ + template <> \ +@@ -2407,16 +2405,19 @@ _GLIBCXX_SIMD_ARM_INTRIN(64, 2); + #undef _GLIBCXX_SIMD_ARM_INTRIN + + template +- struct __intrinsic_type<_Tp, _Bytes, +- enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>> ++ struct __intrinsic_type<_Tp, _Bytes, enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>> + { + static constexpr int _SVecBytes = _Bytes <= 8 ? 8 : 16; ++ + using _Ip = __int_for_sizeof_t<_Tp>; ++ + using _Up = conditional_t< + is_floating_point_v<_Tp>, _Tp, + conditional_t, make_unsigned_t<_Ip>, _Ip>>; ++ + static_assert(!is_same_v<_Tp, _Up> || _SVecBytes != _Bytes, + "should use explicit specialization above"); ++ + using type = typename __intrinsic_type<_Up, _SVecBytes>::type; + }; + #endif // _GLIBCXX_SIMD_HAVE_NEON +@@ -2451,23 +2452,54 @@ _GLIBCXX_SIMD_PPC_INTRIN(unsigned long long); + #undef _GLIBCXX_SIMD_PPC_INTRIN + + template +- struct __intrinsic_type<_Tp, _Bytes, +- enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>> ++ struct __intrinsic_type<_Tp, _Bytes, enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>> + { + static constexpr bool _S_is_ldouble = is_same_v<_Tp, long double>; ++ + // allow _Tp == long double with -mlong-double-64 + static_assert(!(_S_is_ldouble && sizeof(long double) > sizeof(double)), + "no __intrinsic_type support for 128-bit floating point on PowerPC"); ++ + #ifndef __VSX__ + static_assert(!(is_same_v<_Tp, double> + || (_S_is_ldouble && sizeof(long double) == sizeof(double))), + "no __intrinsic_type support for 64-bit floating point on PowerPC w/o VSX"); + #endif +- using type = +- typename __intrinsic_type_impl< +- conditional_t, +- conditional_t<_S_is_ldouble, double, _Tp>, +- __int_for_sizeof_t<_Tp>>>::type; ++ ++ static constexpr auto __element_type() ++ { ++ if constexpr (is_floating_point_v<_Tp>) ++ { ++ if constexpr (_S_is_ldouble) ++ return double {}; ++ else ++ return _Tp {}; ++ } ++ else if constexpr (is_signed_v<_Tp>) ++ { ++ if constexpr (sizeof(_Tp) == sizeof(_SChar)) ++ return _SChar {}; ++ else if constexpr (sizeof(_Tp) == sizeof(short)) ++ return short {}; ++ else if constexpr (sizeof(_Tp) == sizeof(int)) ++ return int {}; ++ else if constexpr (sizeof(_Tp) == sizeof(_LLong)) ++ return _LLong {}; ++ } ++ else ++ { ++ if constexpr (sizeof(_Tp) == sizeof(_UChar)) ++ return _UChar {}; ++ else if constexpr (sizeof(_Tp) == sizeof(_UShort)) ++ return _UShort {}; ++ else if constexpr (sizeof(_Tp) == sizeof(_UInt)) ++ return _UInt {}; ++ else if constexpr (sizeof(_Tp) == sizeof(_ULLong)) ++ return _ULLong {}; ++ } ++ } ++ ++ using type = typename __intrinsic_type_impl::type; + }; + #endif // __ALTIVEC__ + +@@ -2483,22 +2515,29 @@ template + static constexpr size_t _S_full_size = sizeof(_BuiltinType) * __CHAR_BIT__; + + _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper +- __as_full_vector() const { return _M_data; } ++ __as_full_vector() const ++ { return _M_data; } + +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper() = default; +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(_BuiltinType __k) +- : _M_data(__k) {}; ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapper() = default; ++ ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapper(_BuiltinType __k) : _M_data(__k) {}; + +- _GLIBCXX_SIMD_INTRINSIC operator const _BuiltinType&() const ++ _GLIBCXX_SIMD_INTRINSIC ++ operator const _BuiltinType&() const + { return _M_data; } + +- _GLIBCXX_SIMD_INTRINSIC operator _BuiltinType&() ++ _GLIBCXX_SIMD_INTRINSIC ++ operator _BuiltinType&() + { return _M_data; } + +- _GLIBCXX_SIMD_INTRINSIC _BuiltinType __intrin() const ++ _GLIBCXX_SIMD_INTRINSIC _BuiltinType ++ __intrin() const + { return _M_data; } + +- _GLIBCXX_SIMD_INTRINSIC constexpr value_type operator[](size_t __i) const ++ _GLIBCXX_SIMD_INTRINSIC constexpr value_type ++ operator[](size_t __i) const + { return _M_data & (_BuiltinType(1) << __i); } + + template +@@ -2506,7 +2545,8 @@ template + operator[](_SizeConstant<__i>) const + { return _M_data & (_BuiltinType(1) << __i); } + +- _GLIBCXX_SIMD_INTRINSIC constexpr void _M_set(size_t __i, value_type __x) ++ _GLIBCXX_SIMD_INTRINSIC constexpr void ++ _M_set(size_t __i, value_type __x) + { + if (__x) + _M_data |= (_BuiltinType(1) << __i); +@@ -2514,11 +2554,12 @@ template + _M_data &= ~(_BuiltinType(1) << __i); + } + +- _GLIBCXX_SIMD_INTRINSIC +- constexpr bool _M_is_constprop() const ++ _GLIBCXX_SIMD_INTRINSIC constexpr bool ++ _M_is_constprop() const + { return __builtin_constant_p(_M_data); } + +- _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_none_of() const ++ _GLIBCXX_SIMD_INTRINSIC constexpr bool ++ _M_is_constprop_none_of() const + { + if (__builtin_constant_p(_M_data)) + { +@@ -2530,7 +2571,8 @@ template + return false; + } + +- _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_all_of() const ++ _GLIBCXX_SIMD_INTRINSIC constexpr bool ++ _M_is_constprop_all_of() const + { + if (__builtin_constant_p(_M_data)) + { +@@ -2552,10 +2594,11 @@ template + template + struct _SimdWrapperBase // no padding or no SNaNs + { +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase() = default; +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase(_BuiltinType __init) +- : _M_data(__init) +- {} ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapperBase() = default; ++ ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapperBase(_BuiltinType __init) : _M_data(__init) {} + + _BuiltinType _M_data; + }; +@@ -2564,10 +2607,11 @@ template + struct _SimdWrapperBase // with padding that needs to + // never become SNaN + { +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase() : _M_data() {} +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase(_BuiltinType __init) +- : _M_data(__init) +- {} ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapperBase() : _M_data() {} ++ ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapperBase(_BuiltinType __init) : _M_data(__init) {} + + _BuiltinType _M_data; + }; +@@ -2606,24 +2650,33 @@ template + __as_full_vector() const + { return _M_data; } + +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(initializer_list<_Tp> __init) +- : _Base(__generate_from_n_evaluations<_Width, _BuiltinType>( +- [&](auto __i) { return __init.begin()[__i.value]; })) {} ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapper(initializer_list<_Tp> __init) ++ : _Base(__generate_from_n_evaluations<_Width, _BuiltinType>( ++ [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ return __init.begin()[__i.value]; ++ })) {} + +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper() = default; +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(const _SimdWrapper&) +- = default; +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(_SimdWrapper&&) = default; ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapper() = default; ++ ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapper(const _SimdWrapper&) = default; ++ ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapper(_SimdWrapper&&) = default; + + _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper& + operator=(const _SimdWrapper&) = default; ++ + _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper& + operator=(_SimdWrapper&&) = default; + + template >, + is_same<_V, __intrinsic_type_t<_Tp, _Width>>>>> +- _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(_V __x) ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ _SimdWrapper(_V __x) + // __vector_bitcast can convert e.g. __m128 to __vector(2) float + : _Base(__vector_bitcast<_Tp, _Width>(__x)) {} + +@@ -2633,33 +2686,46 @@ template + _GLIBCXX_SIMD_INTRINSIC constexpr + operator _SimdTuple<_Tp, _As...>() const + { +- const auto& dd = _M_data; // workaround for GCC7 ICE +- return __generate_from_n_evaluations>([&]( +- auto __i) constexpr { return dd[int(__i)]; }); ++ return __generate_from_n_evaluations>( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA ++ { return _M_data[int(__i)]; }); + } + +- _GLIBCXX_SIMD_INTRINSIC constexpr operator const _BuiltinType&() const ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ operator const _BuiltinType&() const + { return _M_data; } + +- _GLIBCXX_SIMD_INTRINSIC constexpr operator _BuiltinType&() ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ operator _BuiltinType&() + { return _M_data; } + +- _GLIBCXX_SIMD_INTRINSIC constexpr _Tp operator[](size_t __i) const ++ _GLIBCXX_SIMD_INTRINSIC constexpr _Tp ++ operator[](size_t __i) const + { return _M_data[__i]; } + + template +- _GLIBCXX_SIMD_INTRINSIC constexpr _Tp operator[](_SizeConstant<__i>) const ++ _GLIBCXX_SIMD_INTRINSIC constexpr _Tp ++ operator[](_SizeConstant<__i>) const + { return _M_data[__i]; } + +- _GLIBCXX_SIMD_INTRINSIC constexpr void _M_set(size_t __i, _Tp __x) +- { _M_data[__i] = __x; } ++ _GLIBCXX_SIMD_INTRINSIC constexpr void ++ _M_set(size_t __i, _Tp __x) ++ { ++ if (__builtin_is_constant_evaluated()) ++ _M_data = __generate_from_n_evaluations<_Width, _BuiltinType>([&](auto __j) { ++ return __j == __i ? __x : _M_data[__j()]; ++ }); ++ else ++ _M_data[__i] = __x; ++ } + + _GLIBCXX_SIMD_INTRINSIC +- constexpr bool _M_is_constprop() const ++ constexpr bool ++ _M_is_constprop() const + { return __builtin_constant_p(_M_data); } + +- _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_none_of() const ++ _GLIBCXX_SIMD_INTRINSIC constexpr bool ++ _M_is_constprop_none_of() const + { + if (__builtin_constant_p(_M_data)) + { +@@ -2680,7 +2746,8 @@ template + return false; + } + +- _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_all_of() const ++ _GLIBCXX_SIMD_INTRINSIC constexpr bool ++ _M_is_constprop_all_of() const + { + if (__builtin_constant_p(_M_data)) + { +@@ -2812,6 +2879,32 @@ template + } // namespace simd_abi + + // traits {{{1 ++template ++ struct is_simd_flag_type ++ : false_type ++ {}; ++ ++template <> ++ struct is_simd_flag_type ++ : true_type ++ {}; ++ ++template <> ++ struct is_simd_flag_type ++ : true_type ++ {}; ++ ++template ++ struct is_simd_flag_type> ++ : __bool_constant<(_Np > 0) and __has_single_bit(_Np)> ++ {}; ++ ++template ++ inline constexpr bool is_simd_flag_type_v = is_simd_flag_type<_Tp>::value; ++ ++template >> ++ using _IsSimdFlagType = _Tp; ++ + // is_abi_tag {{{2 + template > + struct is_abi_tag : false_type {}; +@@ -2878,22 +2971,14 @@ template + struct rebind_simd; + + template +- struct rebind_simd< +- _Tp, simd<_Up, _Abi>, +- void_t, _Abi>>> +- { +- using type +- = simd<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>; +- }; ++ struct rebind_simd<_Tp, simd<_Up, _Abi>, ++ void_t, _Abi>>> ++ { using type = simd<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>; }; + + template +- struct rebind_simd< +- _Tp, simd_mask<_Up, _Abi>, +- void_t, _Abi>>> +- { +- using type +- = simd_mask<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>; +- }; ++ struct rebind_simd<_Tp, simd_mask<_Up, _Abi>, ++ void_t, _Abi>>> ++ { using type = simd_mask<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>; }; + + template + using rebind_simd_t = typename rebind_simd<_Tp, _V>::type; +@@ -2903,13 +2988,11 @@ template + struct resize_simd; + + template +- struct resize_simd<_Np, simd<_Tp, _Abi>, +- void_t>> ++ struct resize_simd<_Np, simd<_Tp, _Abi>, void_t>> + { using type = simd<_Tp, simd_abi::deduce_t<_Tp, _Np, _Abi>>; }; + + template +- struct resize_simd<_Np, simd_mask<_Tp, _Abi>, +- void_t>> ++ struct resize_simd<_Np, simd_mask<_Tp, _Abi>, void_t>> + { using type = simd_mask<_Tp, simd_abi::deduce_t<_Tp, _Np, _Abi>>; }; + + template +@@ -2958,13 +3041,11 @@ template + + // casts [simd.casts] {{{1 + // static_simd_cast {{{2 +-template , +- typename = void> ++template , typename = void> + struct __static_simd_cast_return_type; + + template +- struct __static_simd_cast_return_type, _Up, _Ap, false, +- void> ++ struct __static_simd_cast_return_type, _Up, _Ap, false, void> + : __static_simd_cast_return_type, _Up, _Ap> {}; + + template +@@ -3147,6 +3228,10 @@ template + { + if constexpr (is_same_v) + return __x; ++ else if (__builtin_is_constant_evaluated()) ++ return _Tp([&](auto __i) constexpr { ++ return __i < simd_size_v<_Up, _Ap> ? __x[__i] : _Up(); ++ }); + else if constexpr (simd_size_v<_Up, _Ap> == 1) + { + _Tp __r{}; +@@ -3193,21 +3278,19 @@ template + { return __x; } + + template +- _GLIBCXX_SIMD_INTRINSIC auto ++ _GLIBCXX_SIMD_INTRINSIC fixed_size_simd<_Tp, simd_size_v<_Tp, _Ap>> + to_fixed_size(const simd<_Tp, _Ap>& __x) + { +- return simd<_Tp, simd_abi::fixed_size>>([&__x]( +- auto __i) constexpr { return __x[__i]; }); ++ using _Rp = fixed_size_simd<_Tp, simd_size_v<_Tp, _Ap>>; ++ return _Rp([&__x](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }); + } + + template +- _GLIBCXX_SIMD_INTRINSIC auto ++ _GLIBCXX_SIMD_INTRINSIC fixed_size_simd_mask<_Tp, simd_size_v<_Tp, _Ap>> + to_fixed_size(const simd_mask<_Tp, _Ap>& __x) + { +- constexpr int _Np = simd_mask<_Tp, _Ap>::size(); +- fixed_size_simd_mask<_Tp, _Np> __r; +- __execute_n_times<_Np>([&](auto __i) constexpr { __r[__i] = __x[__i]; }); +- return __r; ++ return {__private_init, ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }}; + } + + // to_native {{{2 +@@ -3221,16 +3304,18 @@ template + return {__mem, vector_aligned}; + } + +-template ++template + _GLIBCXX_SIMD_INTRINSIC + enable_if_t<(_Np == native_simd_mask<_Tp>::size()), native_simd_mask<_Tp>> + to_native(const fixed_size_simd_mask<_Tp, _Np>& __x) + { +- return native_simd_mask<_Tp>([&](auto __i) constexpr { return __x[__i]; }); ++ return native_simd_mask<_Tp>( ++ __private_init, ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }); + } + + // to_compatible {{{2 +-template ++template + _GLIBCXX_SIMD_INTRINSIC enable_if_t<(_Np == simd<_Tp>::size()), simd<_Tp>> + to_compatible(const simd<_Tp, simd_abi::fixed_size<_Np>>& __x) + { +@@ -3239,11 +3324,15 @@ template + return {__mem, vector_aligned}; + } + +-template ++template + _GLIBCXX_SIMD_INTRINSIC + enable_if_t<(_Np == simd_mask<_Tp>::size()), simd_mask<_Tp>> + to_compatible(const simd_mask<_Tp, simd_abi::fixed_size<_Np>>& __x) +- { return simd_mask<_Tp>([&](auto __i) constexpr { return __x[__i]; }); } ++ { ++ return simd_mask<_Tp>( ++ __private_init, ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }); ++ } + + // masked assignment [simd_mask.where] {{{1 + +@@ -3276,12 +3365,14 @@ template + + public: + const_where_expression(const const_where_expression&) = delete; ++ + const_where_expression& operator=(const const_where_expression&) = delete; + +- _GLIBCXX_SIMD_INTRINSIC const_where_expression(const _M& __kk, const _Tp& dd) +- : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {} ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ const_where_expression(const _M& __kk, const _Tp& dd) ++ : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {} + +- _GLIBCXX_SIMD_INTRINSIC _V ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V + operator-() const&& + { + return {__private_init, +@@ -3290,8 +3381,8 @@ template + } + + template +- [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V +- copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) const&& ++ [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V ++ copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&& + { + return {__private_init, + _Impl::_S_masked_load(__data(_M_value), __data(_M_k), +@@ -3299,8 +3390,8 @@ template + } + + template +- _GLIBCXX_SIMD_INTRINSIC void +- copy_to(_LoadStorePtr<_Up, value_type>* __mem, _Flags) const&& ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&& + { + _Impl::_S_masked_store(__data(_M_value), + _Flags::template _S_apply<_V>(__mem), +@@ -3320,8 +3411,8 @@ template + struct _Wrapper { using value_type = _V; }; + + protected: +- using value_type = +- typename conditional_t, _Wrapper, _V>::value_type; ++ using value_type ++ = typename conditional_t, _Wrapper, _V>::value_type; + + _GLIBCXX_SIMD_INTRINSIC friend const _M& + __get_mask(const const_where_expression& __x) +@@ -3338,20 +3429,22 @@ template + const_where_expression(const const_where_expression&) = delete; + const_where_expression& operator=(const const_where_expression&) = delete; + +- _GLIBCXX_SIMD_INTRINSIC const_where_expression(const bool __kk, const _Tp& dd) +- : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {} ++ _GLIBCXX_SIMD_INTRINSIC constexpr ++ const_where_expression(const bool __kk, const _Tp& dd) ++ : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {} + +- _GLIBCXX_SIMD_INTRINSIC _V operator-() const&& ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V ++ operator-() const&& + { return _M_k ? -_M_value : _M_value; } + + template +- [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V +- copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) const&& ++ [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V ++ copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&& + { return _M_k ? static_cast<_V>(__mem[0]) : _M_value; } + + template +- _GLIBCXX_SIMD_INTRINSIC void +- copy_to(_LoadStorePtr<_Up, value_type>* __mem, _Flags) const&& ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&& + { + if (_M_k) + __mem[0] = _M_value; +@@ -3376,18 +3469,21 @@ template + is_same::value, ""); + static_assert(_M::size() == _Tp::size(), ""); + +- _GLIBCXX_SIMD_INTRINSIC friend _Tp& __get_lvalue(where_expression& __x) ++ _GLIBCXX_SIMD_INTRINSIC friend constexpr _Tp& ++ __get_lvalue(where_expression& __x) + { return __x._M_value; } + + public: + where_expression(const where_expression&) = delete; + where_expression& operator=(const where_expression&) = delete; + +- _GLIBCXX_SIMD_INTRINSIC where_expression(const _M& __kk, _Tp& dd) +- : const_where_expression<_M, _Tp>(__kk, dd) {} ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR ++ where_expression(const _M& __kk, _Tp& dd) ++ : const_where_expression<_M, _Tp>(__kk, dd) {} + + template +- _GLIBCXX_SIMD_INTRINSIC void operator=(_Up&& __x) && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator=(_Up&& __x) && + { + _Impl::_S_masked_assign(__data(_M_k), __data(_M_value), + __to_value_type_or_member_type<_Tp>( +@@ -3396,14 +3492,15 @@ template + + #define _GLIBCXX_SIMD_OP_(__op, __name) \ + template \ +- _GLIBCXX_SIMD_INTRINSIC void operator __op##=(_Up&& __x)&& \ ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void \ ++ operator __op##=(_Up&& __x)&& \ + { \ + _Impl::template _S_masked_cassign( \ + __data(_M_k), __data(_M_value), \ + __to_value_type_or_member_type<_Tp>(static_cast<_Up&&>(__x)), \ +- [](auto __impl, auto __lhs, auto __rhs) constexpr { \ +- return __impl.__name(__lhs, __rhs); \ +- }); \ ++ [](auto __impl, auto __lhs, auto __rhs) \ ++ constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA \ ++ { return __impl.__name(__lhs, __rhs); }); \ + } \ + static_assert(true) + _GLIBCXX_SIMD_OP_(+, _S_plus); +@@ -3418,48 +3515,48 @@ template + _GLIBCXX_SIMD_OP_(>>, _S_shift_right); + #undef _GLIBCXX_SIMD_OP_ + +- _GLIBCXX_SIMD_INTRINSIC void operator++() && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator++() && + { + __data(_M_value) +- = _Impl::template _S_masked_unary<__increment>(__data(_M_k), +- __data(_M_value)); ++ = _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value)); + } + +- _GLIBCXX_SIMD_INTRINSIC void operator++(int) && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator++(int) && + { + __data(_M_value) +- = _Impl::template _S_masked_unary<__increment>(__data(_M_k), +- __data(_M_value)); ++ = _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value)); + } + +- _GLIBCXX_SIMD_INTRINSIC void operator--() && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator--() && + { + __data(_M_value) +- = _Impl::template _S_masked_unary<__decrement>(__data(_M_k), +- __data(_M_value)); ++ = _Impl::template _S_masked_unary<__decrement>(__data(_M_k), __data(_M_value)); + } + +- _GLIBCXX_SIMD_INTRINSIC void operator--(int) && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator--(int) && + { + __data(_M_value) +- = _Impl::template _S_masked_unary<__decrement>(__data(_M_k), +- __data(_M_value)); ++ = _Impl::template _S_masked_unary<__decrement>(__data(_M_k), __data(_M_value)); + } + + // intentionally hides const_where_expression::copy_from + template +- _GLIBCXX_SIMD_INTRINSIC void +- copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) && + { +- __data(_M_value) +- = _Impl::_S_masked_load(__data(_M_value), __data(_M_k), +- _Flags::template _S_apply<_Tp>(__mem)); ++ __data(_M_value) = _Impl::_S_masked_load(__data(_M_value), __data(_M_k), ++ _Flags::template _S_apply<_Tp>(__mem)); + } + }; + + // where_expression {{{2 + template +- class where_expression : public const_where_expression ++ class where_expression ++ : public const_where_expression + { + using _M = bool; + using typename const_where_expression<_M, _Tp>::value_type; +@@ -3470,12 +3567,14 @@ template + where_expression(const where_expression&) = delete; + where_expression& operator=(const where_expression&) = delete; + +- _GLIBCXX_SIMD_INTRINSIC where_expression(const _M& __kk, _Tp& dd) +- : const_where_expression<_M, _Tp>(__kk, dd) {} ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR ++ where_expression(const _M& __kk, _Tp& dd) ++ : const_where_expression<_M, _Tp>(__kk, dd) {} + + #define _GLIBCXX_SIMD_OP_(__op) \ + template \ +- _GLIBCXX_SIMD_INTRINSIC void operator __op(_Up&& __x)&& \ ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void \ ++ operator __op(_Up&& __x)&& \ + { if (_M_k) _M_value __op static_cast<_Up&&>(__x); } + + _GLIBCXX_SIMD_OP_(=) +@@ -3491,67 +3590,71 @@ template + _GLIBCXX_SIMD_OP_(>>=) + #undef _GLIBCXX_SIMD_OP_ + +- _GLIBCXX_SIMD_INTRINSIC void operator++() && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator++() && + { if (_M_k) ++_M_value; } + +- _GLIBCXX_SIMD_INTRINSIC void operator++(int) && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator++(int) && + { if (_M_k) ++_M_value; } + +- _GLIBCXX_SIMD_INTRINSIC void operator--() && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator--() && + { if (_M_k) --_M_value; } + +- _GLIBCXX_SIMD_INTRINSIC void operator--(int) && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ operator--(int) && + { if (_M_k) --_M_value; } + + // intentionally hides const_where_expression::copy_from + template +- _GLIBCXX_SIMD_INTRINSIC void +- copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) && ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void ++ copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) && + { if (_M_k) _M_value = __mem[0]; } + }; + + // where {{{1 + template +- _GLIBCXX_SIMD_INTRINSIC where_expression, simd<_Tp, _Ap>> ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR ++ where_expression, simd<_Tp, _Ap>> + where(const typename simd<_Tp, _Ap>::mask_type& __k, simd<_Tp, _Ap>& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC +- const_where_expression, simd<_Tp, _Ap>> +- where(const typename simd<_Tp, _Ap>::mask_type& __k, +- const simd<_Tp, _Ap>& __value) ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR ++ const_where_expression, simd<_Tp, _Ap>> ++ where(const typename simd<_Tp, _Ap>::mask_type& __k, const simd<_Tp, _Ap>& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC +- where_expression, simd_mask<_Tp, _Ap>> +- where(const remove_const_t>& __k, +- simd_mask<_Tp, _Ap>& __value) ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR ++ where_expression, simd_mask<_Tp, _Ap>> ++ where(const remove_const_t>& __k, simd_mask<_Tp, _Ap>& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC +- const_where_expression, simd_mask<_Tp, _Ap>> +- where(const remove_const_t>& __k, +- const simd_mask<_Tp, _Ap>& __value) ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR ++ const_where_expression, simd_mask<_Tp, _Ap>> ++ where(const remove_const_t>& __k, const simd_mask<_Tp, _Ap>& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC where_expression ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR where_expression + where(_ExactBool __k, _Tp& __value) + { return {__k, __value}; } + + template +- _GLIBCXX_SIMD_INTRINSIC const_where_expression ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR const_where_expression + where(_ExactBool __k, const _Tp& __value) + { return {__k, __value}; } + +- template +- void where(bool __k, simd<_Tp, _Ap>& __value) = delete; ++template ++ _GLIBCXX_SIMD_CONSTEXPR void ++ where(bool __k, simd<_Tp, _Ap>& __value) = delete; + +- template +- void where(bool __k, const simd<_Tp, _Ap>& __value) = delete; ++template ++ _GLIBCXX_SIMD_CONSTEXPR void ++ where(bool __k, const simd<_Tp, _Ap>& __value) = delete; + + // proposed mask iterations {{{1 + namespace __proposed { +@@ -3568,10 +3671,12 @@ template + size_t __mask; + size_t __bit; + +- _GLIBCXX_SIMD_INTRINSIC void __next_bit() ++ _GLIBCXX_SIMD_INTRINSIC void ++ __next_bit() + { __bit = __builtin_ctzl(__mask); } + +- _GLIBCXX_SIMD_INTRINSIC void __reset_lsb() ++ _GLIBCXX_SIMD_INTRINSIC void ++ __reset_lsb() + { + // 01100100 - 1 = 01100011 + __mask &= (__mask - 1); +@@ -3583,20 +3688,24 @@ template + iterator(const iterator&) = default; + iterator(iterator&&) = default; + +- _GLIBCXX_SIMD_ALWAYS_INLINE size_t operator->() const ++ _GLIBCXX_SIMD_ALWAYS_INLINE size_t ++ operator->() const + { return __bit; } + +- _GLIBCXX_SIMD_ALWAYS_INLINE size_t operator*() const ++ _GLIBCXX_SIMD_ALWAYS_INLINE size_t ++ operator*() const + { return __bit; } + +- _GLIBCXX_SIMD_ALWAYS_INLINE iterator& operator++() ++ _GLIBCXX_SIMD_ALWAYS_INLINE iterator& ++ operator++() + { + __reset_lsb(); + __next_bit(); + return *this; + } + +- _GLIBCXX_SIMD_ALWAYS_INLINE iterator operator++(int) ++ _GLIBCXX_SIMD_ALWAYS_INLINE iterator ++ operator++(int) + { + iterator __tmp = *this; + __reset_lsb(); +@@ -3604,17 +3713,21 @@ template + return __tmp; + } + +- _GLIBCXX_SIMD_ALWAYS_INLINE bool operator==(const iterator& __rhs) const ++ _GLIBCXX_SIMD_ALWAYS_INLINE bool ++ operator==(const iterator& __rhs) const + { return __mask == __rhs.__mask; } + +- _GLIBCXX_SIMD_ALWAYS_INLINE bool operator!=(const iterator& __rhs) const ++ _GLIBCXX_SIMD_ALWAYS_INLINE bool ++ operator!=(const iterator& __rhs) const + { return __mask != __rhs.__mask; } + }; + +- iterator begin() const ++ iterator ++ begin() const + { return __bits.to_ullong(); } + +- iterator end() const ++ iterator ++ end() const + { return 0; } + }; + +@@ -3629,15 +3742,13 @@ template + // reductions [simd.reductions] {{{1 + template > + _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _Tp +- reduce(const simd<_Tp, _Abi>& __v, +- _BinaryOperation __binary_op = _BinaryOperation()) ++ reduce(const simd<_Tp, _Abi>& __v, _BinaryOperation __binary_op = _BinaryOperation()) + { return _Abi::_SimdImpl::_S_reduce(__v, __binary_op); } + + template > + _GLIBCXX_SIMD_INTRINSIC typename _V::value_type + reduce(const const_where_expression<_M, _V>& __x, +- typename _V::value_type __identity_element, +- _BinaryOperation __binary_op) ++ typename _V::value_type __identity_element, _BinaryOperation __binary_op) + { + if (__builtin_expect(none_of(__get_mask(__x)), false)) + return __identity_element; +@@ -3676,16 +3787,12 @@ template + template + _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _Tp + hmin(const simd<_Tp, _Abi>& __v) noexcept +- { +- return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Minimum()); +- } ++ { return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Minimum()); } + + template + _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _Tp + hmax(const simd<_Tp, _Abi>& __v) noexcept +- { +- return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Maximum()); +- } ++ { return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Maximum()); } + + template + _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR +@@ -3753,8 +3860,7 @@ template + + template + _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR simd<_Tp, _Ap> +- clamp(const simd<_Tp, _Ap>& __v, const simd<_Tp, _Ap>& __lo, +- const simd<_Tp, _Ap>& __hi) ++ clamp(const simd<_Tp, _Ap>& __v, const simd<_Tp, _Ap>& __lo, const simd<_Tp, _Ap>& __hi) + { + using _Impl = typename _Ap::_SimdImpl; + return {__private_init, +@@ -3771,13 +3877,12 @@ template +- _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST ++ _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST constexpr + _SimdWrapper<_Tp, _Np / _Total * _Combine> + __extract_part(const _SimdWrapper<_Tp, _Np> __x); + +-template +- _GLIBCXX_SIMD_INTRINSIC auto ++template ++ _GLIBCXX_SIMD_INTRINSIC constexpr auto + __extract_part(const _SimdTuple<_Tp, _A0, _As...>& __x); + + // }}} +@@ -3786,7 +3891,8 @@ template + struct _SizeList + { + template +- static constexpr size_t _S_at(_SizeConstant<_I> = {}) ++ static constexpr size_t ++ _S_at(_SizeConstant<_I> = {}) + { + if constexpr (_I == 0) + return _V0; +@@ -3795,7 +3901,8 @@ template + } + + template +- static constexpr auto _S_before(_SizeConstant<_I> = {}) ++ static constexpr auto ++ _S_before(_SizeConstant<_I> = {}) + { + if constexpr (_I == 0) + return _SizeConstant<0>(); +@@ -3805,7 +3912,8 @@ template + } + + template +- static constexpr auto _S_pop_front(_SizeConstant<_Np> = {}) ++ static constexpr auto ++ _S_pop_front(_SizeConstant<_Np> = {}) + { + if constexpr (_Np == 0) + return _SizeList(); +@@ -3900,12 +4008,11 @@ template >([&]( +- auto __i) constexpr { +- return _V([&](auto __j) constexpr { +- return __x[__i * _V::size() + __j]; +- }); +- }); ++ return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ return _V([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA ++ { return __x[__i * _V::size() + __j]; }); ++ }); + } + else if constexpr ( + __is_fixed_size_abi_v<_Ap> +@@ -3918,49 +4025,47 @@ template * const __element_ptr + = reinterpret_cast*>(&__data(__x)); +- return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&]( +- auto __i) constexpr { +- return _V(__element_ptr + __i * _V::size(), vector_aligned); +- }); ++ return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA ++ { return _V(__element_ptr + __i * _V::size(), vector_aligned); }); + #else + const auto& __xx = __data(__x); +- return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&]( +- auto __i) constexpr { +- [[maybe_unused]] constexpr size_t __offset +- = decltype(__i)::value * _V::size(); +- return _V([&](auto __j) constexpr { +- constexpr _SizeConstant<__j + __offset> __k; +- return __xx[__k]; +- }); +- }); ++ return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ [[maybe_unused]] constexpr size_t __offset ++ = decltype(__i)::value * _V::size(); ++ return _V([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ constexpr _SizeConstant<__j + __offset> __k; ++ return __xx[__k]; ++ }); ++ }); + #endif + } + else if constexpr (is_same_v) + { + // normally memcpy should work here as well +- return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&]( +- auto __i) constexpr { return __x[__i]; }); ++ return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }); + } + else + { +- return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&]( +- auto __i) constexpr { +- if constexpr (__is_fixed_size_abi_v) +- return _V([&](auto __j) constexpr { +- return __x[__i * _V::size() + __j]; +- }); +- else +- return _V(__private_init, +- __extract_part(__data(__x))); +- }); ++ return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ if constexpr (__is_fixed_size_abi_v) ++ return _V([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ return __x[__i * _V::size() + __j]; ++ }); ++ else ++ return _V(__private_init, ++ __extract_part(__data(__x))); ++ }); + } + } + + // }}} + // split(simd_mask) {{{ + template / _V::size()> ++ size_t _Parts = simd_size_v / _V::size()> + enable_if_t && simd_size_v == _Parts * _V::size(), array<_V, _Parts>> + split(const simd_mask& __x) +@@ -3976,22 +4081,22 @@ template >([&]( +- auto __i) constexpr { +- constexpr size_t __offset = __i * _V::size(); +- return _V(__bitset_init, (__bits >> __offset).to_ullong()); +- }); ++ return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ constexpr size_t __offset = __i * _V::size(); ++ return _V(__bitset_init, (__bits >> __offset).to_ullong()); ++ }); + } + else + { +- return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&]( +- auto __i) constexpr { +- constexpr size_t __offset = __i * _V::size(); +- return _V( +- __private_init, [&](auto __j) constexpr { +- return __x[__j + __offset]; +- }); +- }); ++ return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ constexpr size_t __offset = __i * _V::size(); ++ return _V(__private_init, ++ [&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ return __x[__j + __offset]; ++ }); ++ }); + } + } + +@@ -4009,12 +4114,14 @@ template + using _V = __deduced_simd<_Tp, _N0>; + + if (__x._M_is_constprop()) +- return __generate_from_n_evaluations([&]( +- auto __i) constexpr { +- using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>; +- constexpr size_t __offset = _SL::_S_before(__i); +- return _Vi([&](auto __j) constexpr { return __x[__offset + __j]; }); +- }); ++ return __generate_from_n_evaluations( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>; ++ constexpr size_t __offset = _SL::_S_before(__i); ++ return _Vi([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ return __x[__offset + __j]; ++ }); ++ }); + else if constexpr (_Np == _N0) + { + static_assert(sizeof...(_Sizes) == 1); +@@ -4081,28 +4188,28 @@ template + #ifdef _GLIBCXX_SIMD_USE_ALIASING_LOADS + const __may_alias<_Tp>* const __element_ptr + = reinterpret_cast*>(&__x); +- return __generate_from_n_evaluations([&]( +- auto __i) constexpr { +- using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>; +- constexpr size_t __offset = _SL::_S_before(__i); +- constexpr size_t __base_align = alignof(simd<_Tp, _Ap>); +- constexpr size_t __a +- = __base_align - ((__offset * sizeof(_Tp)) % __base_align); +- constexpr size_t __b = ((__a - 1) & __a) ^ __a; +- constexpr size_t __alignment = __b == 0 ? __a : __b; +- return _Vi(__element_ptr + __offset, overaligned<__alignment>); +- }); ++ return __generate_from_n_evaluations( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>; ++ constexpr size_t __offset = _SL::_S_before(__i); ++ constexpr size_t __base_align = alignof(simd<_Tp, _Ap>); ++ constexpr size_t __a ++ = __base_align - ((__offset * sizeof(_Tp)) % __base_align); ++ constexpr size_t __b = ((__a - 1) & __a) ^ __a; ++ constexpr size_t __alignment = __b == 0 ? __a : __b; ++ return _Vi(__element_ptr + __offset, overaligned<__alignment>); ++ }); + #else +- return __generate_from_n_evaluations([&]( +- auto __i) constexpr { +- using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>; +- const auto& __xx = __data(__x); +- using _Offset = decltype(_SL::_S_before(__i)); +- return _Vi([&](auto __j) constexpr { +- constexpr _SizeConstant<_Offset::value + __j> __k; +- return __xx[__k]; +- }); +- }); ++ return __generate_from_n_evaluations( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>; ++ const auto& __xx = __data(__x); ++ using _Offset = decltype(_SL::_S_before(__i)); ++ return _Vi([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ constexpr _SizeConstant<_Offset::value + __j> __k; ++ return __xx[__k]; ++ }); ++ }); + #endif + } + +@@ -4123,8 +4230,7 @@ template + // __store_pack_of_simd {{{ + template + _GLIBCXX_SIMD_INTRINSIC void +- __store_pack_of_simd(char* __mem, const simd<_Tp, _A0>& __x0, +- const simd<_Tp, _As>&... __xs) ++ __store_pack_of_simd(char* __mem, const simd<_Tp, _A0>& __x0, const simd<_Tp, _As>&... __xs) + { + constexpr size_t __n_bytes = sizeof(_Tp) * simd_size_v<_Tp, _A0>; + __builtin_memcpy(__mem, &__data(__x0), __n_bytes); +@@ -4144,8 +4250,9 @@ template + return simd_cast<_Rp>(__xs...); + else if ((... && __xs._M_is_constprop())) + return simd<_Tp, +- simd_abi::deduce_t<_Tp, (simd_size_v<_Tp, _As> + ...)>>([&]( +- auto __i) constexpr { return __subscript_in_pack<__i>(__xs...); }); ++ simd_abi::deduce_t<_Tp, (simd_size_v<_Tp, _As> + ...)>>( ++ [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA ++ { return __subscript_in_pack<__i>(__xs...); }); + else + { + _Rp __r{}; +@@ -4161,9 +4268,10 @@ template + _GLIBCXX_SIMD_CONSTEXPR __deduced_simd<_Tp, simd_size_v<_Tp, _Abi> * _Np> + concat(const array, _Np>& __x) + { +- return __call_with_subscripts<_Np>(__x, [](const auto&... __xs) { +- return concat(__xs...); +- }); ++ return __call_with_subscripts<_Np>( ++ __x, [](const auto&... __xs) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { ++ return concat(__xs...); ++ }); + } + + // }}} +@@ -4178,7 +4286,8 @@ template ) + return _M_obj; +@@ -4187,7 +4296,8 @@ template +- _GLIBCXX_SIMD_INTRINSIC constexpr void _M_write(_Tp&& __x) const ++ _GLIBCXX_SIMD_INTRINSIC constexpr void ++ _M_write(_Tp&& __x) const + { _Accessor::_S_set(_M_obj, _M_index, static_cast<_Tp&&>(__x)); } + + public: +@@ -4197,32 +4307,32 @@ template , value_type>> +- _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference operator=(_Tp&& __x) && ++ template , value_type>> ++ _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference ++ operator=(_Tp&& __x) && + { + _M_write(static_cast<_Tp&&>(__x)); + return {_M_obj, _M_index}; + } + +-#define _GLIBCXX_SIMD_OP_(__op) \ +- template () __op declval<_Tp>()), \ +- typename = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, _TT>, \ +- typename = _ValuePreservingOrInt<_TT, value_type>> \ +- _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference \ +- operator __op##=(_Tp&& __x) && \ +- { \ +- const value_type& __lhs = _M_read(); \ +- _M_write(__lhs __op __x); \ +- return {_M_obj, _M_index}; \ ++#define _GLIBCXX_SIMD_OP_(__op) \ ++ template () __op declval<_Tp>()), \ ++ typename = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, _TT>, \ ++ typename = _ValuePreservingOrInt<_TT, value_type>> \ ++ _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference \ ++ operator __op##=(_Tp&& __x) && \ ++ { \ ++ const value_type& __lhs = _M_read(); \ ++ _M_write(__lhs __op __x); \ ++ return {_M_obj, _M_index}; \ + } + _GLIBCXX_SIMD_ALL_ARITHMETICS(_GLIBCXX_SIMD_OP_); + _GLIBCXX_SIMD_ALL_SHIFTS(_GLIBCXX_SIMD_OP_); +@@ -4230,9 +4340,9 @@ template &>())> +- _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference operator++() && ++ typename = decltype(++declval&>())> ++ _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference ++ operator++() && + { + value_type __x = _M_read(); + _M_write(++__x); +@@ -4240,9 +4350,9 @@ template &>()++)> +- _GLIBCXX_SIMD_INTRINSIC constexpr value_type operator++(int) && ++ typename = decltype(declval&>()++)> ++ _GLIBCXX_SIMD_INTRINSIC constexpr value_type ++ operator++(int) && + { + const value_type __r = _M_read(); + value_type __x = __r; +@@ -4251,9 +4361,9 @@ template &>())> +- _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference operator--() && ++ typename = decltype(--declval&>())> ++ _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference ++ operator--() && + { + value_type __x = _M_read(); + _M_write(--__x); +@@ -4261,9 +4371,9 @@ template &>()--)> +- _GLIBCXX_SIMD_INTRINSIC constexpr value_type operator--(int) && ++ typename = decltype(declval&>()--)> ++ _GLIBCXX_SIMD_INTRINSIC constexpr value_type ++ operator--(int) && + { + const value_type __r = _M_read(); + value_type __x = __r; +@@ -4339,7 +4449,8 @@ template + template