Replies: 6 comments 19 replies
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Hey there @bartokon ! thanks for reaching out How does this sound, I just checked in a little example pipeline examples/pipeline.c. Pull the repo. It has a synthesis/ The default behavior of the tool Supplying the There is no Does any of this help? What would you like a potential new Happy Friday! Take care, |
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Hello Julian, Let me tell about what I would like to experiment on. Now let's see what would happen if we ran this thread like 10 times We would have some samples to work on.
This would be fun to do as an extra "overlay" application for PipelineC. What do you think about it? I know it is not optimal calculation wise, as you need some samples to work on. Take care, |
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OK cool - I believe I understand what you are getting at. Predicting how freq and latency scales sounds very useful. Anything to have the tool do better guesses / i.e. fewer synthesis/pnr runs would be great to have. And interesting to think about the genetic and GAN approaches with the tool. I think it makes sense to have a I dont have any experience with the machine learning side - but happy to get |
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Righto @bartokon. Pull the repo again. I implemented a Running You will see something like I think you definitely want Also, this was using Vivado for an Artix 7 35T. You can see logs an mentioned in the output Let me know if this is helpful eh! Take care! |
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Hi Julian, I have a few simple requests :)
Do you think that I could use another synthesis tool for faster architecture estimation than Vivado? Just to find optimal starting point for algorithms? Maybe Yosys? Take care! |
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Okay, I will wait for that "output" CSV (or other) implementation and I will try that Yosysy flow. There could be also input CSV file that contains parameters for pipelineC. That way, the interface between tools should be pretty easy to do. PipelineC could read some (or all) parameters like slice factor, cycles for operation, io regs etc. the more variables to tune for ML the funnier it gets :D |
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Hmm these are great points regarding both taking in some, ex. csv file pipeline description I suppose both will be necessary when you come back to me with the bunch of params the NN churned out to try and run synthesis on to see if it worked :) |
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I suppose I can dump entire configuration, that is Something like |
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Haha, can be even thousands parameters! The one and only thing is that it needs to be easy to manipulate from the "top". For example, we could have some hidden function that describes Frequency. Julian, just don't overwork yourself, start with what is easiest for you to implement, just in proper easy to manipulate format ;D |
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Csv is indeed seeming reasonable 👍 |
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I have some errors on Yosys GHDL, and |
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@bartokon this was a dumb issue with GHDL not being passed its 'use VHDL 2008' flag. It has been fixed. Pull repo. |
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Thanks, probably with Yosys I will iterate much faster than before. |
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Hey Julian, For now I have created simple decision tree and these are results...
This is full auto -> How does it works? It probes "0" and "MAX_LATENCY" that is for now 1024 and do rest on it's own. It guesses max freq in range(1, MAX_LATENCY) and output is rounded and passed to Vivado synth. This is output for 10 iterations I need to test it on more programs... but it seems to work on this example >:3 |
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Ooo neat work doing binary search to look for fmax.
Typically I am not trying to find the fmax for a given pipeline but just setting the tool to try and make a pipeline meet timing near my device's fmax. The fmax for pipelined designs is generally determined/limited by the FPGA technology (ex. Artix 7 FPGA clock tree limits all designs to like ~400MHz at max in practice). So all maximally pipelined pipelines (if the pipelinec tool can produce such designs) have an FMAX around ~400MHz for this device. However, it also important to note that targeting the absolute FMAX of your FPGA device for all modules will likely not work/is wasteful. In a real-world design you can probably expect 300-400MHz on an Artix 7 to be 'pretty good'. (having deeper pipeline that could reach fmax but isnt being used at fmax is just wasted latency/clock cycles). That said - it depends on the size of the design. I mentioned some hand crafted heuristic type stuff I have setup, its easier to get that right for smaller designs. Larger designs take longer-per-iteration of synthesis/pnr and more iterations because the timing feedback I get reflects smaller and smaller parts of the entire design. Its a slow incremental process. It can be anywhere from a handful of synthesis runs, taking a few mins, to hundreds, taking multiple days. Lots of variables to consider. What cha think eh? |
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Also the tool does two rounds of synthesis/pnr |
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Generally getting at what you want to Are you planning to use the C code as input to algorithm? otherwise I suppose you are starting from something like the Just a big list of function names/hierarchy structure - and params (not visible the original C code) So some kind of map of learning instance params = f(target freq, instance names) After being trained with fmax = f(instance names, instance params) ? |
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I'm aiming to get better quality of results. For example if we set target for example 300+-10Mhz tool should find the lowest amount of pipeline stages (to limit resource usage) for given frequency, and that means "guide" pipelineC for optimal architecture, for example by changing CSV parameters. I don't want to dig deep into inner workings of PipelineC just try to guide it to be a better tool with some ML models. TL;DR |
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This is not a problem for ML model to evolve if you change a number of input parameters after some git commit in CSV, so I think this is a more flexible solution than hard-coded parameters. |
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OK getting at your So you want run the PipelinecC tool+syn+pnr, etc to evaluate+learn The parameters I was planning to put into a csv are the Thinking that it doesnt seem like there is anything stopping you from doing that^ experiment as is right now? Thinking about how you mentioned wanting to wait for csv before proceeding? Let me know whats up Take care! |
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"deep into inner workings" I thought about parsing C into Verilog and adding pipeline regs manually. I want pipelineC to do it (with pipeline parameters generated by ML). Do not, don't reinvent the wheel twice! "Thinking that it doesn't seem like there is anything stopping you from doing that^ experiment as is right now? " yea I'm working with latency only at this moment, but in the future I would like to test it with more control about code generation, that is control "inst_name, slices, in_reg, out_reg". So I want to "trying out its guesses pipeline params and getting feedback from syn+pnr tool" Take care, I will have some more fun with PipelineC today as well 👍 |
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Hi, is it possible to run compilation of some file for given pipeline stages? (not main_mhz pragma just one time run)
for example ./pipelineC blink.c -start 10 -stop 10 (10 pipeline stages) and return frequency to some file.
I would like to try some machine learning algorithms and see if they could do some magic with pipelining :)
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