diff --git a/src/frontend/frontend.sv b/src/frontend/frontend.sv
index a61e3ed37f..2713d85e0f 100644
--- a/src/frontend/frontend.sv
+++ b/src/frontend/frontend.sv
@@ -418,6 +418,7 @@ module frontend import ariane_pkg::*; #(
       .instr_i             ( instr                ), // from re-aligner
       .addr_i              ( addr                 ), // from re-aligner
       .exception_i         ( icache_ex_valid_q    ), // from I$
+      .exception_addr_i    ( icache_vaddr_q       ),
       .predict_address_i   ( predict_address      ),
       .cf_type_i           ( cf_type              ),
       .valid_i             ( instruction_valid    ), // from re-aligner
diff --git a/src/frontend/instr_queue.sv b/src/frontend/instr_queue.sv
index 62b649d821..37c81a9e01 100644
--- a/src/frontend/instr_queue.sv
+++ b/src/frontend/instr_queue.sv
@@ -54,6 +54,7 @@ module instr_queue (
   output logic [ariane_pkg::INSTR_PER_FETCH-1:0]             consumed_o,
   // we've encountered an exception, at this point the only possible exceptions are page-table faults
   input  ariane_pkg::frontend_exception_t                    exception_i,
+  input  logic [riscv::VLEN-1:0]                             exception_addr_i,
   // branch predict
   input  logic [riscv::VLEN-1:0]                             predict_address_i,
   input  ariane_pkg::cf_t  [ariane_pkg::INSTR_PER_FETCH-1:0] cf_type_i,
@@ -70,6 +71,7 @@ module instr_queue (
     logic [31:0]     instr; // instruction word
     ariane_pkg::cf_t cf;    // branch was taken
     ariane_pkg::frontend_exception_t ex;    // exception happened
+    logic [riscv::VLEN-1:0] ex_vaddr;       // lower VLEN bits of tval for exception
   } instr_data_t;
 
   logic [$clog2(ariane_pkg::INSTR_PER_FETCH)-1:0] branch_index;
@@ -180,6 +182,7 @@ module instr_queue (
     assign instr_data_in[i].instr = instr[i + idx_is_q];
     assign instr_data_in[i].cf = cf[i + idx_is_q];
     assign instr_data_in[i].ex = exception_i; // exceptions hold for the whole fetch packet
+    assign instr_data_in[i].ex_vaddr = exception_addr_i;
     /* verilator lint_on WIDTH */
   end
 
@@ -230,8 +233,7 @@ module instr_queue (
         end
         fetch_entry_o.instruction = instr_data_out[i].instr;
         fetch_entry_o.ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE;
-        // TODO(zarubaf,moschn): Might need some fixes with illegal access exceptions
-        fetch_entry_o.ex.tval  = {{64-riscv::VLEN{1'b0}}, pc_q};
+        fetch_entry_o.ex.tval  = {{64-riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr};
         fetch_entry_o.branch_predict.cf = instr_data_out[i].cf;
         pop_instr[i] = fetch_entry_valid_o & fetch_entry_ready_i;
       end