This repository has been archived by the owner on Mar 28, 2019. It is now read-only.

Digit Lock for FPGA

Capable with ISE Design Suite.
File DigitLock.v is the main code written in Verilog.
Report of the experiment is attached also, as DigitLock.pdf.
Folder DigitLocker holds the whole ISE project, but be aware that *.ucf might vary from the FPGA boards.