General discussion & key points

[WojciechPtas]

ideas / solutions to be discussed:

• should all kinds of tables (numeric, id, comments) be shared among compilation units? if not, how should we determine that they refer to the same name
• do we allow multiple package declaration in the same line (based on previous disccusions, we should not)

[Jacajack]

• C-like variable shadowing, handled by codegen
• do not allow comb(clk) unless clk already defined
• const non-generic signal values don't need to be stored for evaluation (at least for now)
• recurrent modules instantiation
• HIRN errors are to be avoided by semantic analyzer but should not cause Rust panic

[Jacajack]

New discussion topics:

• Generic sensitivity in HIRN API. Useful for distinguishing what is an interface signal and what is a parameter.
• Our expression width evaluation rules are a nightmare when translated to System Verilog

[Jacajack]

const bus<4> x = 5;
auto y;
x = y;

----------------------------

const bus<5> x;
sync bus<4> y;
sync bus<4> w;
auto z;

x = z;
z = y + w;

-----------------------------

auto x; // const bus<4> lub lepszy
comb bus<4> y;
const bus<4> z;

// 1.
z = x; // x (L->R const)
x = y; // x (L->R const, L<-R comb)

// 2.
x = y; // x (L<-R comb)
z = x; // x (L<-R comb, L->R const)

// 1. x = const bus<4> przez co x = y jest nielegalne bo const = comb
// 2. x = comb bus<4> przez co z = x jest nielegalne bo const = comb 

// 3. preferowany typ z dedukcji L<-R
// 4. typ z deklaracji jest niepodważalny

------------------------------
sync auto x;
comb bus<4> y;
const bus<4> z;

//        x (decl sync)
z = x; // x (decl sync, L->R const)
x = y; // x (decl sync, L->R const, L<-R comb)

-------------------------------

auto x;
comb bus<4> y;
const bus<4> z;

y = x;
x = z;

-------------------------------

auto x; // comb bus<4> lub lepszy
auto y; // const bus<4> lub lepszy
comb bus<4> x2;
const bus<4> y2;

x2 = x;
y2 = y;
x = y;
// (comb) = (const)

// sensitivity po prawej musi być lepsze niż po lewej
// 

-------------------------------

x + 3 ---<|--- y;

-----------------------------

auto x; // const bus<4> lub lepszy
comb bus<4> y;
const bus<4> z;

// 1.
z = x; // x (L->R const)
x = y; // x (L->R const, L<-R comb)

// 2.
x = y; // x (L<-R comb)
z = x; // x (L<-R comb, L->R const)

// 1. x = const bus<4> przez co x = y jest nielegalne bo const = comb
// 2. x = comb bus<4> przez co z = x jest nielegalne bo const = comb 

// 3. preferowany typ z dedukcji L<-R
// 4. typ z deklaracji jest niepodważalny

------------------------------
sync auto x;
comb bus<4> y;
const bus<4> z;

//        x (decl sync)
z = x; // x (decl sync, L->R const)
x = y; // x (decl sync, L->R const, L<-R comb)

-------------------------------

auto x;
comb bus<4> y;
const bus<4> z;

y = x;
x = z;

-------------------------------

auto x; // comb bus<4> lub lepszy
auto y; // const bus<4> lub lepszy
comb bus<4> x2;
const bus<4> y2;

x2 = x;
y2 = y;
x = y;
// (comb) = (const)

// sensitivity po prawej musi być lepsze niż po lewej
// 

-------------------------------

x + 3 ---<|--- y;

-------------------------------

signed auto x;
const auto y;
bus<4> z;

x = y; // (x decl signed, x L<-R const, y decl const, y L->R signed, z decl w4)
y = z; // (x decl signed, x L<-R const, y decl const, y L->R signed, z decl w4, y L<-R w4, z L->R const)

|var|decl|L<-R|L->R|result|
|---|--------|---------|--------|
|x  |signed|const| |const signed|
|y  |const|w4|signed| const signed<4>|
|z  |w4| |const|const bus<4>|


--------------------------------


auto x0, x7;

x0 = x1;
x1 = x2;
// ...
x6 = x7;

const auto y;
bus<4> z;
//y = x0;
//x7 = z;

x7 = y;

[Jacajack]

• Distant future: assertions! Two types - statements and expressions (generating statements).
• Prefer .expect(...) when .unwrap() is unavoidable

[Jacajack]

Considering that generic constants should be emitted as localparam in SV, how do we codegen crap like this:

module XXX {
  int param;
};

impl XXX {
  int n;
  const unsigned bus<n> b = 0;
  for (i in [0:10]) {
    if (i == param) {
      n = 143;
    }
  }
}

[Jacajack]

Sounds like a legitimate reason to ban generic assignments in conditional/loop scopes.

[Jacajack]

or we could generate functions for that (non strategical right now): https://stackoverflow.com/questions/41222417/systemverilog-localparam-array-with-configurable-size

[Jacajack]

Another builtin ideas:

• ones(n) - $2^n - 1$ on $n$ bits
• zeros(n) - equivalent to 0u<n>

[Jacajack]

HIRL / HIRN parameter binding issue

impl X {
  int a  = 7;
  generic_module m{
    param: a + 1 // this will have 65-bit width and will cause HIRL elab error (everything is a bus)
  };
}

Generic constants as macros issue

nvm this was stupid, should've used auto FSM_IDLE = 0u2

impl X {
  int FSM_IDLE = 0;
  int FSM_WORKING = 1;
  int FSM_DONE = 2;

  // clk and all that...
  unsigned comb(clk) bus<2> fsm_next = match (fsm_state) {
    FSM_IDLE => FSM_WORKING, // will this work without two casts?
    // ...
  };
}

[Jacajack]

Can we enforce generic assigment in declaration scope?