From 7f58ad80533e2dac02bc242fa1efd410c673cdb2 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Wed, 19 Feb 2014 10:03:22 +0000 Subject: [PATCH 001/718] start experimental implementation of revised new_specification Based on Rob Arthan's "HOL Constant Definition Done Right". The tricky part is deciding how and where to implement the existing definitional rules that are theoretically subsumed by the new one. --- src/0/Thm.sml | 46 +++++++++++++++++++++++++--------- src/postkernel/Theory.sig | 1 + src/postkernel/Theory.sml | 13 ++++++++++ src/prekernel/FinalThm-sig.sml | 3 +-- 4 files changed, 49 insertions(+), 14 deletions(-) diff --git a/src/0/Thm.sml b/src/0/Thm.sml index 6742a9b439..a441192e48 100644 --- a/src/0/Thm.sml +++ b/src/0/Thm.sml @@ -1143,6 +1143,14 @@ fun check_free_vars tm f = ("Free variables in rhs of definition: " :: commafy (map (Lib.quote o fst o dest_var) V))); +fun check_vars tm vars f = + case Lib.set_diff (free_vars tm) vars + of [] => () + | extras => + raise f (String.concat + ("Unbound variable(s) in definition: " + :: commafy (map (Lib.quote o fst o dest_var) extras))); + fun check_tyvars body_tyvars ty f = case Lib.set_diff body_tyvars (Type.type_vars ty) of [] => () @@ -1174,6 +1182,7 @@ in mk_defn_thm(tag thm, mk_exists(rep, list_mk_comb(TYDEF,[P,rep]))) end +(* subsumed by prim_specification fun prim_constant_definition Thy M = let val (lhs, rhs) = with_exn dest_eq M DEF_FORM_ERR val {Name, Thy, Ty} = @@ -1196,25 +1205,38 @@ fun prim_constant_definition Thy M = let in mk_defn_thm(empty_tag, mk_eq(new_lhs, rhs)) end +*) fun bind thy s ty = Term.prim_new_const {Name = s, Thy = thy} ty -fun prim_specification thyname cnames th = let - val con = concl th - val checked = check_null_hyp th SPEC_ERR - val checked = check_free_vars con SPEC_ERR - val checked = +fun prim_specification thyname th = let + val hyps = hypset th + val stys = + let + fun foldthis (tm,stys) = + let + val (l,r) = + with_exn dest_eq tm (SPEC_ERR "non-equational hypothesis") + val (s,ty) = + with_exn dest_var l (SPEC_ERR "lhs of hyp not a variable") + val checked = check_free_vars r SPEC_ERR + val checked = check_tyvars (type_vars_in_term r) ty SPEC_ERR + in + (s,ty)::stys + end + in + HOLset.foldl foldthis [] hyps + end + val cnames = List.map fst stys + val checked = assert_exn (op=) (length(mk_set cnames),length cnames) (SPEC_ERR "duplicate constant names in specification") - val (V,body) = - with_exn (nstrip_exists (length cnames)) con - (SPEC_ERR "too few existentially quantified variables") - fun vOK V v = check_tyvars V (type_of v) SPEC_ERR - val checked = List.app (vOK (type_vars_in_term body)) V - fun addc v s = v |-> bind thyname s (snd(dest_var v)) + val body = concl th + val checked = check_vars body (List.map mk_var stys) SPEC_ERR + fun addc (s,ty) = (mk_var (s,ty)) |-> bind thyname s ty in - mk_defn_thm (tag th, subst (map2 addc V cnames) body) + (cnames, mk_defn_thm (tag th, subst (List.map addc stys) body)) end diff --git a/src/postkernel/Theory.sig b/src/postkernel/Theory.sig index 37f324903b..63dc08b72e 100644 --- a/src/postkernel/Theory.sig +++ b/src/postkernel/Theory.sig @@ -75,6 +75,7 @@ sig (* Extensions by definition *) structure Definition : sig val new_type_definition : string * thm -> thm + val loose_specification : string * thm -> thm val new_definition : string * term -> thm val new_specification : string * string list * thm -> thm diff --git a/src/postkernel/Theory.sml b/src/postkernel/Theory.sml index 81c6d8194e..cae2e2cada 100644 --- a/src/postkernel/Theory.sml +++ b/src/postkernel/Theory.sml @@ -1071,6 +1071,17 @@ fun new_type_definition (name,thm) = let end handle e => raise (wrap_exn "Theory.Definition" "new_type_definition" e); +fun loose_specification(name, th) = let + val thy = current_theory() + val (cnames,def) = Thm.prim_specification thy th + in + store_definition (name, def) before + List.app (fn s => call_hooks (TheoryDelta.NewConstant{Name=s, Thy=thy})) + cnames + end + handle e => raise (wrap_exn "Definition" "loose_specification" e); + +(* TODO: implement these two in terms of the above fun new_definition(name,M) = let val (dest,post) = !new_definition_hook @@ -1094,6 +1105,8 @@ fun new_specification (name, cnames, th) = let end handle e => raise (wrap_exn "Definition" "new_specification" e); +*) + end (* Definition struct *) end (* Theory *) diff --git a/src/prekernel/FinalThm-sig.sml b/src/prekernel/FinalThm-sig.sml index 898b4a9633..03f1071cfa 100644 --- a/src/prekernel/FinalThm-sig.sml +++ b/src/prekernel/FinalThm-sig.sml @@ -110,8 +110,7 @@ sig (* definitional rules of inference *) val prim_type_definition : {Thy : string, Tyop : string} * thm -> thm - val prim_constant_definition : string -> term -> thm - val prim_specification : string -> string list -> thm -> thm + val prim_specification : string -> thm -> string list * thm (* Fetching theorems from disk *) From eae01bc342a860415ad8a859f79bec370b75a99d Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Fri, 21 Feb 2014 16:51:32 +0000 Subject: [PATCH 002/718] remove Theory.new_specification and reimplement new_definition in terms of the revised Thm.prim_specification. obviously this breaks anything that depended on Theory.new_specification, so the next job is to rework those things (and write a backwards-compatible version, but later in the build sequence because it needs pairs.) --- src/0/Thm.sml | 6 +++--- src/postkernel/Theory.sig | 2 +- src/postkernel/Theory.sml | 21 +++------------------ 3 files changed, 7 insertions(+), 22 deletions(-) diff --git a/src/0/Thm.sml b/src/0/Thm.sml index a441192e48..004d964c4c 100644 --- a/src/0/Thm.sml +++ b/src/0/Thm.sml @@ -1099,11 +1099,9 @@ fun mk_defn_thm (witness_tag, c) = fun ERR f msg = HOL_ERR {origin_structure = "Thm", origin_function = f, message = msg} val TYDEF_ERR = ERR "prim_type_definition" -val DEF_ERR = ERR "new_definition" -val SPEC_ERR = ERR "new_specification" +val SPEC_ERR = ERR "prim_specification" val TYDEF_FORM_ERR = TYDEF_ERR "expected a theorem of the form \"?x. P x\"" -val DEF_FORM_ERR = DEF_ERR "expected a term of the form \"v = M\"" (* some simple term manipulation functions *) fun mk_exists (absrec as (Bvar,_)) = @@ -1183,6 +1181,8 @@ in end (* subsumed by prim_specification +val DEF_ERR = ERR "new_definition" +val DEF_FORM_ERR = DEF_ERR "expected a term of the form \"v = M\"" fun prim_constant_definition Thy M = let val (lhs, rhs) = with_exn dest_eq M DEF_FORM_ERR val {Name, Thy, Ty} = diff --git a/src/postkernel/Theory.sig b/src/postkernel/Theory.sig index 63dc08b72e..bcbebc27b0 100644 --- a/src/postkernel/Theory.sig +++ b/src/postkernel/Theory.sig @@ -76,8 +76,8 @@ sig structure Definition : sig val new_type_definition : string * thm -> thm val loose_specification : string * thm -> thm + val new_definition : string * term -> thm - val new_specification : string * string list * thm -> thm val new_definition_hook : ((term -> term list * term) * (term list * thm -> thm)) ref diff --git a/src/postkernel/Theory.sml b/src/postkernel/Theory.sml index cae2e2cada..f17f38a41b 100644 --- a/src/postkernel/Theory.sml +++ b/src/postkernel/Theory.sml @@ -1081,32 +1081,17 @@ fun loose_specification(name, th) = let end handle e => raise (wrap_exn "Definition" "loose_specification" e); -(* TODO: implement these two in terms of the above - fun new_definition(name,M) = let val (dest,post) = !new_definition_hook - val (V,eq) = dest M - val def_th = Thm.prim_constant_definition (current_theory()) eq - val {Name,Thy,...} = dest_thy_const (rand (rator (concl def_th))) + val (V,eq) = dest M + val Thy = current_theory() + val ([Name],def_th) = Thm.prim_specification Thy (Thm.ASSUME eq) in store_definition (name, post(V,def_th)) before call_hooks (TheoryDelta.NewConstant{Name=Name, Thy=Thy}) end handle e => raise (wrap_exn "Definition" "new_definition" e); -fun new_specification (name, cnames, th) = let - val thy = current_theory() - val def = Thm.prim_specification thy cnames th - val final = store_definition (name, def) - in - List.app (fn s => call_hooks (TheoryDelta.NewConstant{Name=s, Thy = thy})) - cnames - ; final - end - handle e => raise (wrap_exn "Definition" "new_specification" e); - -*) - end (* Definition struct *) end (* Theory *) From c07a105b4e916e1eae4ad6a3845fac24de77c0f0 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Fri, 21 Feb 2014 17:54:58 +0000 Subject: [PATCH 003/718] replace calls to new_specification in boolScript.sml --- src/bool/boolScript.sml | 33 +++++++++++++++------------------ src/postkernel/Theory.sml | 5 ++++- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/bool/boolScript.sml b/src/bool/boolScript.sml index a26efc14a3..e592fd3910 100644 --- a/src/bool/boolScript.sml +++ b/src/bool/boolScript.sml @@ -292,8 +292,6 @@ val RES_SELECT_DEF = val _ = (add_const "RES_SELECT"; associate_restriction ("@", "RES_SELECT")); -(* Note: RES_ABSTRACT comes later, defined by new_specification *) - (*---------------------------------------------------------------------------*) (* Experimental rewriting directives *) (*---------------------------------------------------------------------------*) @@ -3948,19 +3946,19 @@ val RES_ABSTRACT_EXISTS = val B22 = GENL [p, m1, m2] B21 (* Cleaning up *) val C1 = CONJ A9 B22 - val C2 = EXISTS - (Term `?f. - (!p (m : 'a -> 'b) x. x IN p ==> (f p m x = m x)) /\ - (!p m1 m2. - (!x. x IN p ==> (m1 x = m2 x)) ==> (f p m1 = f p m2))`, - Term `\p (m : 'a -> 'b) x. (if x IN p then m x else ARB x)`) C1 + val C2 = ASSUME (Term `RES_ABSTRACT = ^witness`) + val C3 = SUBST [lhs (concl C2) |-> SYM C2] + (Term `(!p (m : 'a -> 'b) x. x IN p ==> (RES_ABSTRACT p m x = m x)) /\ + (!p m1 m2. + (!x. x IN p ==> (m1 x = m2 x)) ==> + (RES_ABSTRACT p m1 = RES_ABSTRACT p m2))`) C1 in - C2 + C3 end; val RES_ABSTRACT_DEF = - Definition.new_specification - ("RES_ABSTRACT_DEF", ["RES_ABSTRACT"], RES_ABSTRACT_EXISTS); + Definition.loose_specification + ("RES_ABSTRACT_DEF", RES_ABSTRACT_EXISTS); val _ = add_const "RES_ABSTRACT"; val _ = associate_restriction ("\\", "RES_ABSTRACT"); @@ -4435,14 +4433,13 @@ end (* define case operator *) val itself_case_thm = let val witness = ``\(i:'a itself) (b:'b). b`` - val witness_applied1 = BETA_CONV (mk_comb(witness, ``(:'a)``)) - val witness_applied2 = RIGHT_BETA (AP_THM witness_applied1 ``b:'b``) + val a = ``(:'a)`` val b = ``b:'b`` + val witness_applied1 = BETA_CONV (mk_comb(witness, a)) + val witness_applied2 = RIGHT_BETA (AP_THM witness_applied1 b) + val th1 = AP_THM (AP_THM (ASSUME ``itself_case = ^witness``) a) b + val th2 = TRANS th1 witness_applied2 in - new_specification("itself_case_thm", - ["itself_case"], - EXISTS (``?f:'a itself -> 'b -> 'b. !b. f (:'a) b = b``, - witness) - (GEN_ALL witness_applied2)) + loose_specification ("itself_case_thm", (GEN_ALL th2)) end diff --git a/src/postkernel/Theory.sml b/src/postkernel/Theory.sml index f17f38a41b..91675a8353 100644 --- a/src/postkernel/Theory.sml +++ b/src/postkernel/Theory.sml @@ -1073,6 +1073,8 @@ fun new_type_definition (name,thm) = let fun loose_specification(name, th) = let val thy = current_theory() + val _ = print("Attempting to specify "^name^" with:\n") + val _ = print((HOLPP.pp_to_string 80 (!pp_thm) th)^"\n") val (cnames,def) = Thm.prim_specification thy th in store_definition (name, def) before @@ -1085,7 +1087,8 @@ fun new_definition(name,M) = let val (dest,post) = !new_definition_hook val (V,eq) = dest M val Thy = current_theory() - val ([Name],def_th) = Thm.prim_specification Thy (Thm.ASSUME eq) + val (cnames,def_th) = Thm.prim_specification Thy (Thm.ASSUME eq) + val Name = case cnames of [Name] => Name | _ => raise Match in store_definition (name, post(V,def_th)) before call_hooks (TheoryDelta.NewConstant{Name=Name, Thy=Thy}) From abce3c6f16cdde3ecfadc5d15a81a0d50c960c11 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Tue, 25 Feb 2014 17:38:53 +0000 Subject: [PATCH 004/718] Revert "start experimental implementation of revised new_specification" This reverts commits 7f58ad8, eae01bc, and c07a105. --- src/0/Thm.sml | 52 ++++++++++------------------------ src/bool/boolScript.sml | 33 +++++++++++---------- src/postkernel/Theory.sig | 3 +- src/postkernel/Theory.sml | 29 +++++++++---------- src/prekernel/FinalThm-sig.sml | 3 +- 5 files changed, 50 insertions(+), 70 deletions(-) diff --git a/src/0/Thm.sml b/src/0/Thm.sml index 004d964c4c..6742a9b439 100644 --- a/src/0/Thm.sml +++ b/src/0/Thm.sml @@ -1099,9 +1099,11 @@ fun mk_defn_thm (witness_tag, c) = fun ERR f msg = HOL_ERR {origin_structure = "Thm", origin_function = f, message = msg} val TYDEF_ERR = ERR "prim_type_definition" -val SPEC_ERR = ERR "prim_specification" +val DEF_ERR = ERR "new_definition" +val SPEC_ERR = ERR "new_specification" val TYDEF_FORM_ERR = TYDEF_ERR "expected a theorem of the form \"?x. P x\"" +val DEF_FORM_ERR = DEF_ERR "expected a term of the form \"v = M\"" (* some simple term manipulation functions *) fun mk_exists (absrec as (Bvar,_)) = @@ -1141,14 +1143,6 @@ fun check_free_vars tm f = ("Free variables in rhs of definition: " :: commafy (map (Lib.quote o fst o dest_var) V))); -fun check_vars tm vars f = - case Lib.set_diff (free_vars tm) vars - of [] => () - | extras => - raise f (String.concat - ("Unbound variable(s) in definition: " - :: commafy (map (Lib.quote o fst o dest_var) extras))); - fun check_tyvars body_tyvars ty f = case Lib.set_diff body_tyvars (Type.type_vars ty) of [] => () @@ -1180,9 +1174,6 @@ in mk_defn_thm(tag thm, mk_exists(rep, list_mk_comb(TYDEF,[P,rep]))) end -(* subsumed by prim_specification -val DEF_ERR = ERR "new_definition" -val DEF_FORM_ERR = DEF_ERR "expected a term of the form \"v = M\"" fun prim_constant_definition Thy M = let val (lhs, rhs) = with_exn dest_eq M DEF_FORM_ERR val {Name, Thy, Ty} = @@ -1205,38 +1196,25 @@ fun prim_constant_definition Thy M = let in mk_defn_thm(empty_tag, mk_eq(new_lhs, rhs)) end -*) fun bind thy s ty = Term.prim_new_const {Name = s, Thy = thy} ty -fun prim_specification thyname th = let - val hyps = hypset th - val stys = - let - fun foldthis (tm,stys) = - let - val (l,r) = - with_exn dest_eq tm (SPEC_ERR "non-equational hypothesis") - val (s,ty) = - with_exn dest_var l (SPEC_ERR "lhs of hyp not a variable") - val checked = check_free_vars r SPEC_ERR - val checked = check_tyvars (type_vars_in_term r) ty SPEC_ERR - in - (s,ty)::stys - end - in - HOLset.foldl foldthis [] hyps - end - val cnames = List.map fst stys - val checked = +fun prim_specification thyname cnames th = let + val con = concl th + val checked = check_null_hyp th SPEC_ERR + val checked = check_free_vars con SPEC_ERR + val checked = assert_exn (op=) (length(mk_set cnames),length cnames) (SPEC_ERR "duplicate constant names in specification") - val body = concl th - val checked = check_vars body (List.map mk_var stys) SPEC_ERR - fun addc (s,ty) = (mk_var (s,ty)) |-> bind thyname s ty + val (V,body) = + with_exn (nstrip_exists (length cnames)) con + (SPEC_ERR "too few existentially quantified variables") + fun vOK V v = check_tyvars V (type_of v) SPEC_ERR + val checked = List.app (vOK (type_vars_in_term body)) V + fun addc v s = v |-> bind thyname s (snd(dest_var v)) in - (cnames, mk_defn_thm (tag th, subst (List.map addc stys) body)) + mk_defn_thm (tag th, subst (map2 addc V cnames) body) end diff --git a/src/bool/boolScript.sml b/src/bool/boolScript.sml index e592fd3910..a26efc14a3 100644 --- a/src/bool/boolScript.sml +++ b/src/bool/boolScript.sml @@ -292,6 +292,8 @@ val RES_SELECT_DEF = val _ = (add_const "RES_SELECT"; associate_restriction ("@", "RES_SELECT")); +(* Note: RES_ABSTRACT comes later, defined by new_specification *) + (*---------------------------------------------------------------------------*) (* Experimental rewriting directives *) (*---------------------------------------------------------------------------*) @@ -3946,19 +3948,19 @@ val RES_ABSTRACT_EXISTS = val B22 = GENL [p, m1, m2] B21 (* Cleaning up *) val C1 = CONJ A9 B22 - val C2 = ASSUME (Term `RES_ABSTRACT = ^witness`) - val C3 = SUBST [lhs (concl C2) |-> SYM C2] - (Term `(!p (m : 'a -> 'b) x. x IN p ==> (RES_ABSTRACT p m x = m x)) /\ - (!p m1 m2. - (!x. x IN p ==> (m1 x = m2 x)) ==> - (RES_ABSTRACT p m1 = RES_ABSTRACT p m2))`) C1 + val C2 = EXISTS + (Term `?f. + (!p (m : 'a -> 'b) x. x IN p ==> (f p m x = m x)) /\ + (!p m1 m2. + (!x. x IN p ==> (m1 x = m2 x)) ==> (f p m1 = f p m2))`, + Term `\p (m : 'a -> 'b) x. (if x IN p then m x else ARB x)`) C1 in - C3 + C2 end; val RES_ABSTRACT_DEF = - Definition.loose_specification - ("RES_ABSTRACT_DEF", RES_ABSTRACT_EXISTS); + Definition.new_specification + ("RES_ABSTRACT_DEF", ["RES_ABSTRACT"], RES_ABSTRACT_EXISTS); val _ = add_const "RES_ABSTRACT"; val _ = associate_restriction ("\\", "RES_ABSTRACT"); @@ -4433,13 +4435,14 @@ end (* define case operator *) val itself_case_thm = let val witness = ``\(i:'a itself) (b:'b). b`` - val a = ``(:'a)`` val b = ``b:'b`` - val witness_applied1 = BETA_CONV (mk_comb(witness, a)) - val witness_applied2 = RIGHT_BETA (AP_THM witness_applied1 b) - val th1 = AP_THM (AP_THM (ASSUME ``itself_case = ^witness``) a) b - val th2 = TRANS th1 witness_applied2 + val witness_applied1 = BETA_CONV (mk_comb(witness, ``(:'a)``)) + val witness_applied2 = RIGHT_BETA (AP_THM witness_applied1 ``b:'b``) in - loose_specification ("itself_case_thm", (GEN_ALL th2)) + new_specification("itself_case_thm", + ["itself_case"], + EXISTS (``?f:'a itself -> 'b -> 'b. !b. f (:'a) b = b``, + witness) + (GEN_ALL witness_applied2)) end diff --git a/src/postkernel/Theory.sig b/src/postkernel/Theory.sig index bcbebc27b0..37f324903b 100644 --- a/src/postkernel/Theory.sig +++ b/src/postkernel/Theory.sig @@ -75,9 +75,8 @@ sig (* Extensions by definition *) structure Definition : sig val new_type_definition : string * thm -> thm - val loose_specification : string * thm -> thm - val new_definition : string * term -> thm + val new_specification : string * string list * thm -> thm val new_definition_hook : ((term -> term list * term) * (term list * thm -> thm)) ref diff --git a/src/postkernel/Theory.sml b/src/postkernel/Theory.sml index 91675a8353..81c6d8194e 100644 --- a/src/postkernel/Theory.sml +++ b/src/postkernel/Theory.sml @@ -1071,30 +1071,29 @@ fun new_type_definition (name,thm) = let end handle e => raise (wrap_exn "Theory.Definition" "new_type_definition" e); -fun loose_specification(name, th) = let - val thy = current_theory() - val _ = print("Attempting to specify "^name^" with:\n") - val _ = print((HOLPP.pp_to_string 80 (!pp_thm) th)^"\n") - val (cnames,def) = Thm.prim_specification thy th - in - store_definition (name, def) before - List.app (fn s => call_hooks (TheoryDelta.NewConstant{Name=s, Thy=thy})) - cnames - end - handle e => raise (wrap_exn "Definition" "loose_specification" e); fun new_definition(name,M) = let val (dest,post) = !new_definition_hook - val (V,eq) = dest M - val Thy = current_theory() - val (cnames,def_th) = Thm.prim_specification Thy (Thm.ASSUME eq) - val Name = case cnames of [Name] => Name | _ => raise Match + val (V,eq) = dest M + val def_th = Thm.prim_constant_definition (current_theory()) eq + val {Name,Thy,...} = dest_thy_const (rand (rator (concl def_th))) in store_definition (name, post(V,def_th)) before call_hooks (TheoryDelta.NewConstant{Name=Name, Thy=Thy}) end handle e => raise (wrap_exn "Definition" "new_definition" e); +fun new_specification (name, cnames, th) = let + val thy = current_theory() + val def = Thm.prim_specification thy cnames th + val final = store_definition (name, def) + in + List.app (fn s => call_hooks (TheoryDelta.NewConstant{Name=s, Thy = thy})) + cnames + ; final + end + handle e => raise (wrap_exn "Definition" "new_specification" e); + end (* Definition struct *) end (* Theory *) diff --git a/src/prekernel/FinalThm-sig.sml b/src/prekernel/FinalThm-sig.sml index 03f1071cfa..898b4a9633 100644 --- a/src/prekernel/FinalThm-sig.sml +++ b/src/prekernel/FinalThm-sig.sml @@ -110,7 +110,8 @@ sig (* definitional rules of inference *) val prim_type_definition : {Thy : string, Tyop : string} * thm -> thm - val prim_specification : string -> thm -> string list * thm + val prim_constant_definition : string -> term -> thm + val prim_specification : string -> string list -> thm -> thm (* Fetching theorems from disk *) From 209347444b414aa3b569d5a97689f5415c87d2fc Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Tue, 25 Feb 2014 20:59:36 +0000 Subject: [PATCH 005/718] Add gen_new_specification and remove prim_constant_definition Implement new_definition in terms of gen_prim_specification. Leave the existing new_specification in place. This plan of attack suggested by RDA. Have only touched the standard kernel, and none of the theories. Next steps would include updating the other kernels, implementing new_specification in terms of gen_new_specification (at some point after pairTheory), and removing uses of new_specification before pairTheory one by one if possible/desired... --- src/0/Thm.sml | 39 ++++++++++++++++++++++++++++++++++ src/postkernel/Theory.sig | 1 + src/postkernel/Theory.sml | 16 +++++++++++--- src/prekernel/FinalThm-sig.sml | 2 +- 4 files changed, 54 insertions(+), 4 deletions(-) diff --git a/src/0/Thm.sml b/src/0/Thm.sml index 6742a9b439..110641f022 100644 --- a/src/0/Thm.sml +++ b/src/0/Thm.sml @@ -1143,6 +1143,14 @@ fun check_free_vars tm f = ("Free variables in rhs of definition: " :: commafy (map (Lib.quote o fst o dest_var) V))); +fun check_vars tm vars f = + case Lib.set_diff (free_vars tm) vars + of [] => () + | extras => + raise f (String.concat + ("Unbound variable(s) in definition: " + :: commafy (map (Lib.quote o fst o dest_var) extras))); + fun check_tyvars body_tyvars ty f = case Lib.set_diff body_tyvars (Type.type_vars ty) of [] => () @@ -1174,6 +1182,7 @@ in mk_defn_thm(tag thm, mk_exists(rep, list_mk_comb(TYDEF,[P,rep]))) end +(* subsumed by gen_prim_specification fun prim_constant_definition Thy M = let val (lhs, rhs) = with_exn dest_eq M DEF_FORM_ERR val {Name, Thy, Ty} = @@ -1196,6 +1205,7 @@ fun prim_constant_definition Thy M = let in mk_defn_thm(empty_tag, mk_eq(new_lhs, rhs)) end +*) fun bind thy s ty = Term.prim_new_const {Name = s, Thy = thy} ty @@ -1217,6 +1227,35 @@ in mk_defn_thm (tag th, subst (map2 addc V cnames) body) end +fun gen_prim_specification thyname th = let + val hyps = hypset th + val stys = + let + fun foldthis (tm,stys) = + let + val (l,r) = + with_exn dest_eq tm (SPEC_ERR "non-equational hypothesis") + val (s,ty) = + with_exn dest_var l (SPEC_ERR "lhs of hyp not a variable") + val checked = check_free_vars r SPEC_ERR + val checked = check_tyvars (type_vars_in_term r) ty SPEC_ERR + in + (s,ty)::stys + end + in + HOLset.foldl foldthis [] hyps + end + val cnames = List.map fst stys + val checked = + assert_exn (op=) (length(mk_set cnames),length cnames) + (SPEC_ERR "duplicate constant names in specification") + val body = concl th + val checked = check_vars body (List.map mk_var stys) SPEC_ERR + fun addc (s,ty) = (mk_var (s,ty)) |-> bind thyname s ty +in + (cnames, mk_defn_thm (tag th, subst (List.map addc stys) body)) +end + diff --git a/src/postkernel/Theory.sig b/src/postkernel/Theory.sig index 37f324903b..ef10629b60 100644 --- a/src/postkernel/Theory.sig +++ b/src/postkernel/Theory.sig @@ -77,6 +77,7 @@ sig val new_type_definition : string * thm -> thm val new_definition : string * term -> thm val new_specification : string * string list * thm -> thm + val gen_new_specification : string * thm -> thm val new_definition_hook : ((term -> term list * term) * (term list * thm -> thm)) ref diff --git a/src/postkernel/Theory.sml b/src/postkernel/Theory.sml index 81c6d8194e..b591eb8fd4 100644 --- a/src/postkernel/Theory.sml +++ b/src/postkernel/Theory.sml @@ -1071,12 +1071,22 @@ fun new_type_definition (name,thm) = let end handle e => raise (wrap_exn "Theory.Definition" "new_type_definition" e); +fun gen_new_specification(name, th) = let + val thy = current_theory() + val (cnames,def) = Thm.gen_prim_specification thy th + in + store_definition (name, def) before + List.app (fn s => call_hooks (TheoryDelta.NewConstant{Name=s, Thy=thy})) + cnames + end + handle e => raise (wrap_exn "Definition" "gen_new_specification" e); fun new_definition(name,M) = let val (dest,post) = !new_definition_hook - val (V,eq) = dest M - val def_th = Thm.prim_constant_definition (current_theory()) eq - val {Name,Thy,...} = dest_thy_const (rand (rator (concl def_th))) + val (V,eq) = dest M + val Thy = current_theory() + val (cnames,def_th) = Thm.gen_prim_specification Thy (Thm.ASSUME eq) + val Name = case cnames of [Name] => Name | _ => raise Match in store_definition (name, post(V,def_th)) before call_hooks (TheoryDelta.NewConstant{Name=Name, Thy=Thy}) diff --git a/src/prekernel/FinalThm-sig.sml b/src/prekernel/FinalThm-sig.sml index 898b4a9633..95c99a5575 100644 --- a/src/prekernel/FinalThm-sig.sml +++ b/src/prekernel/FinalThm-sig.sml @@ -110,8 +110,8 @@ sig (* definitional rules of inference *) val prim_type_definition : {Thy : string, Tyop : string} * thm -> thm - val prim_constant_definition : string -> term -> thm val prim_specification : string -> string list -> thm -> thm + val gen_prim_specification : string -> thm -> string list * thm (* Fetching theorems from disk *) From 9fbd0c16c529c8b1c14db3d354233bd69c55d594 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Tue, 25 Feb 2014 21:36:04 +0000 Subject: [PATCH 006/718] add gen_prim_specification to experimental-kernel --- src/experimental-kernel/Thm.sml | 38 +++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/src/experimental-kernel/Thm.sml b/src/experimental-kernel/Thm.sml index 3b98368d91..d18777fded 100644 --- a/src/experimental-kernel/Thm.sml +++ b/src/experimental-kernel/Thm.sml @@ -1132,6 +1132,14 @@ fun check_free_vars tm f = ("Free variables in rhs of definition: " :: commafy (map (Lib.quote o fst o dest_var) V))); +fun check_vars tm vars f = + case Lib.set_diff (free_vars tm) vars + of [] => () + | extras => + raise f (String.concat + ("Unbound variable(s) in definition: " + :: commafy (map (Lib.quote o fst o dest_var) extras))); + fun check_tyvars body_tyvars ty f = case Lib.set_diff body_tyvars (Type.type_vars ty) of [] => () @@ -1164,6 +1172,7 @@ in mk_defn_thm(tag thm, mk_exists(rep, list_mk_comb(TYDEF,[P,rep]))) end +(* subsumed by gen_prim_specification fun prim_constant_definition Thy M = let val (lhs, rhs) = with_exn dest_eq M DEF_FORM_ERR val {Name, Thy, Ty} = @@ -1186,6 +1195,7 @@ fun prim_constant_definition Thy M = let in mk_defn_thm(empty_tag, mk_eq(new_lhs, rhs)) end +*) fun bind thy s ty = Term.prim_new_const {Name = s, Thy = thy} ty @@ -1207,6 +1217,34 @@ in mk_defn_thm (tag th, subst (map2 addc V cnames) body) end +fun gen_prim_specification thyname th = let + val hyps = hypset th + val stys = + let + fun foldthis (tm,stys) = + let + val (l,r) = + with_exn dest_eq tm (SPEC_ERR "non-equational hypothesis") + val (s,ty) = + with_exn dest_var l (SPEC_ERR "lhs of hyp not a variable") + val checked = check_free_vars r SPEC_ERR + val checked = check_tyvars (type_vars_in_term r) ty SPEC_ERR + in + (s,ty)::stys + end + in + HOLset.foldl foldthis [] hyps + end + val cnames = List.map fst stys + val checked = + assert_exn (op=) (length(mk_set cnames),length cnames) + (SPEC_ERR "duplicate constant names in specification") + val body = concl th + val checked = check_vars body (List.map mk_var stys) SPEC_ERR + fun addc (s,ty) = (mk_var (s,ty)) |-> bind thyname s ty +in + (cnames, mk_defn_thm (tag th, subst (List.map addc stys) body)) +end local val mk_disk_thm = make_thm Count.Disk From f6e9197f5f4ae7a62060bbd03de1173b79fb0d5e Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Thu, 27 Feb 2014 17:58:15 +0000 Subject: [PATCH 007/718] implement new_specification in terms of gen_new_specification in pairLib - should re-export elsewhere. --- src/pair/src/pairLib.sig | 2 ++ src/pair/src/pairLib.sml | 62 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/src/pair/src/pairLib.sig b/src/pair/src/pairLib.sig index 520cd13f73..06b6a95eb4 100644 --- a/src/pair/src/pairLib.sig +++ b/src/pair/src/pairLib.sig @@ -117,4 +117,6 @@ sig val TUPLE_TAC : term -> tactic val LET_INTRO_TAC : tactic + + val new_specification : string * string list * thm -> thm end diff --git a/src/pair/src/pairLib.sml b/src/pair/src/pairLib.sml index a04400595a..6cff9d31d0 100644 --- a/src/pair/src/pairLib.sml +++ b/src/pair/src/pairLib.sml @@ -11,4 +11,66 @@ open boolLib pairSyntax PairedLambda pairTools simpLib; val _ = Rewrite.add_implicit_rewrites pairTheory.pair_rws; +(* Implementation of new_specification as a rule derived from + gen_new_specification. This occurs here because the derivation + depends on pairs. *) + +local + open Term Thm + + (* given a varstruct (possibly nested pairs of variables) vs, return a list + of equations equating each variable to the corresponding projection of tm + e.g. varstruct_to_eqs tm ((p,q),r) = + [r = SND tm, + q = SND (FST tm), + p = FST (FST tm)] *) + fun varstruct_to_eqs tm = + let + fun f tm ac vs = + if is_var vs + then (mk_eq(vs, tm))::ac + else + let + val (a,d) = dest_pair vs + val ac = f (mk_fst tm) ac a + val ac = f (mk_snd tm) ac d + in ac end + in + f tm [] + end + + open Lib PairRules + + in + + fun new_specification (name,cnames,th) = let + val th1 = + (* this is not good enough since it doesn't guarantee the cnames will be used + - primed variants could be used if they clash with existing constant names + CONV_RULE (RENAME_VARS_CONV cnames) th *) + let + val tm1 = concl th + val (vs1,body1) = strip_exists tm1 + val tys = map type_of vs1 + val vs2 = map2 (curry mk_var) cnames tys + val body2 = Term.subst (map2 (curry op |->) vs1 vs2) body1 + val tm2 = list_mk_exists(vs2,body2) + val th2 = ALPHA tm1 tm2 + in EQ_MP th2 th end + (* turn it into a single paired existential *) + val th2 = CONV_RULE (REPEATC UNCURRY_EXISTS_CONV) th1 + val (vs,body) = strip_pexists (concl th2) + val vs = case vs of [vs] => vs | _ => raise Match + val witness = mk_pselect (vs,body) + val eqs = varstruct_to_eqs witness vs + val th3 = CONV_RULE PEXISTS_CONV th2 + val th4 = PURE_REWRITE_RULE (List.map (SYM o ASSUME) eqs) th3 + (* ensure that even totally unconstrained constants get defined *) + val th5 = List.foldl (Lib.uncurry ADD_ASSUM) th4 eqs + in + Theory.Definition.gen_new_specification (name,th5) + end + +end + end From 6aba5baa4c810646e6df06bbbaa2fcbf0276fa02 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Mon, 3 Mar 2014 15:27:38 +0000 Subject: [PATCH 008/718] export derived new_specification from bossLib --- src/boss/bossLib.sig | 4 ++++ src/boss/bossLib.sml | 2 ++ 2 files changed, 6 insertions(+) diff --git a/src/boss/bossLib.sig b/src/boss/bossLib.sig index 35dbfc23ab..465c746138 100644 --- a/src/boss/bossLib.sig +++ b/src/boss/bossLib.sig @@ -22,6 +22,10 @@ sig val xHol_reln : string -> term quotation -> thm * thm * thm val export_mono : string -> unit + (* Derived rule for specifying new constants. + (Should have the same effect as Thm.new_specification.) *) + val new_specification : string * string list * thm -> thm + (* Case-splitting and induction operations *) val Cases : tactic diff --git a/src/boss/bossLib.sml b/src/boss/bossLib.sml index 1efea40450..b7dd4760fd 100644 --- a/src/boss/bossLib.sml +++ b/src/boss/bossLib.sml @@ -29,6 +29,8 @@ in end; val ERR = mk_HOL_ERR "bossLib"; +val new_specification = pairLib.new_specification; + (*---------------------------------------------------------------------------* Datatype definition *---------------------------------------------------------------------------*) From 059e250f621b90e5a05f9f3f3c3305bc7722da0b Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Thu, 16 Oct 2014 00:44:31 +0100 Subject: [PATCH 009/718] rename Ho_Net.empty_net to Ho_Net.empty All similar structures (e.g. Net and Raw) use "empty" not "empty_net"; it seems right to follow a single naming convention. --- src/1/Ho_Net.sig | 2 +- src/1/Ho_Net.sml | 10 +++++----- src/1/Ho_Rewrite.sml | 4 ++-- src/quantHeuristics/quantHeuristicsLibBase.sml | 2 +- src/simp/src/congLib.sml | 2 +- src/simp/src/simpLib.sml | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/1/Ho_Net.sig b/src/1/Ho_Net.sig index 603288d87a..78e62ce40a 100644 --- a/src/1/Ho_Net.sig +++ b/src/1/Ho_Net.sig @@ -11,7 +11,7 @@ sig type 'a net type term = Term.term - val empty_net : 'a net + val empty : 'a net val enter : term list * term * 'a -> 'a net -> 'a net val lookup : term -> 'a net -> 'a list val merge_nets : 'a net * 'a net -> 'a net diff --git a/src/1/Ho_Net.sml b/src/1/Ho_Net.sml index 8b4873e08e..2324833324 100644 --- a/src/1/Ho_Net.sml +++ b/src/1/Ho_Net.sml @@ -83,15 +83,15 @@ fun label_for_lookup tm = end; (* double constructor design may seem redundant but it allows us to avoid - a value polymorphism problem, and have a simple value for empty_net. + a value polymorphism problem, and have a simple value for empty. If you try - val empty_net = NODE(mkDict label_cmp, []) - then empty_net can't be fully polymorphic, thanks to the call to + val empty = NODE(mkDict label_cmp, []) + then empty can't be fully polymorphic, thanks to the call to mkDict. *) datatype 'a net = NODE of (term_label,'a net) dict * 'a list | EMPTY of 'a list -val empty_net = EMPTY [] +val empty = EMPTY [] @@ -114,7 +114,7 @@ fun net_update (elem, tms:(term list * term) list, net) = | tm::rtms => let val (label,ntms) = stored_label tm val child = case check_edge(net, label) of - NONE => empty_net + NONE => empty | SOME n => n val new_child = net_update(elem,ntms @ rtms,child) in diff --git a/src/1/Ho_Rewrite.sml b/src/1/Ho_Rewrite.sml index 8a73de7ac2..3523651bf4 100644 --- a/src/1/Ho_Rewrite.sml +++ b/src/1/Ho_Rewrite.sml @@ -59,7 +59,7 @@ datatype rewrites = RW of {thms :thm list, net :conv Ho_Net.net} fun dest_rewrites(RW{thms, ...}) = thms -val empty_rewrites = RW{thms = [], net = Ho_Net.empty_net} +val empty_rewrites = RW{thms = [], net = Ho_Net.empty} val implicit = ref empty_rewrites; @@ -219,7 +219,7 @@ val HIGHER_REWRITE_CONV = val beta_fns = map2 BETA_VAR preds concs val ass_list = zip pats (zip preds (zip thl beta_fns)) fun insert p = Ho_Net.enter ([],p,p) - val mnet = itlist insert pats Ho_Net.empty_net + val mnet = itlist insert pats Ho_Net.empty fun look_fn t = mapfilter (fn p => if can (ho_match_term [] empty_tmset p) t then p else fail()) diff --git a/src/quantHeuristics/quantHeuristicsLibBase.sml b/src/quantHeuristics/quantHeuristicsLibBase.sml index 0712577a9b..c861e7acc0 100644 --- a/src/quantHeuristics/quantHeuristicsLibBase.sml +++ b/src/quantHeuristics/quantHeuristicsLibBase.sml @@ -1325,7 +1325,7 @@ let group_thmL ((P_t', thm::thmL)::L') thmPL end val guess_net_complex = - foldr (fn ((P_t, thmL), n) => Ho_Net.enter ([],P_t, (P_t, thmL)) n) Ho_Net.empty_net + foldr (fn ((P_t, thmL), n) => Ho_Net.enter ([],P_t, (P_t, thmL)) n) Ho_Net.empty (group_thmL [] cL) diff --git a/src/simp/src/congLib.sml b/src/simp/src/congLib.sml index 57cc8f62fc..4165151181 100644 --- a/src/simp/src/congLib.sml +++ b/src/simp/src/congLib.sml @@ -161,7 +161,7 @@ val cong_reducer = end in REDUCER {name=SOME"cong_reducer", addcontext=addcontext, apply=apply, - initial=CONVNET (Ho_Net.empty_net)} + initial=CONVNET (Ho_Net.empty)} end; diff --git a/src/simp/src/simpLib.sml b/src/simp/src/simpLib.sml index 0562081b67..9afd267ec1 100644 --- a/src/simp/src/simpLib.sml +++ b/src/simp/src/simpLib.sml @@ -185,7 +185,7 @@ datatype simpset = val empty_ss = SS {mk_rewrs=fn x => [x], ssfrags = [], limit = NONE, - initial_net=empty_net, + initial_net=empty, dprocs=[],travrules=EQ_tr}; fun ssfrags_of (SS x) = #ssfrags x; From aab658eacdc426745fd030919bf25aa3afceee2c Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Fri, 17 Oct 2014 22:24:29 +0100 Subject: [PATCH 010/718] use "fn" rather than "\" in SML code samples --- help/Docfiles/Tactical.POP_ASSUM.doc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/help/Docfiles/Tactical.POP_ASSUM.doc b/help/Docfiles/Tactical.POP_ASSUM.doc index ae9a5deed4..bf208d3c4b 100644 --- a/help/Docfiles/Tactical.POP_ASSUM.doc +++ b/help/Docfiles/Tactical.POP_ASSUM.doc @@ -38,7 +38,7 @@ Another point to consider is that if the relevant assumption has been obtained by {DISCH_TAC}, it is often cleaner to use {DISCH_THEN} with a theorem-tactic. For example, instead of: { - DISCH_TAC THEN POP_ASSUM (\th. SUBST1_TAC (SYM th)) + DISCH_TAC THEN POP_ASSUM (fn th => SUBST1_TAC (SYM th)) } one might use { @@ -54,7 +54,7 @@ The goal: can be solved by: { POP_ASSUM - (fn th => REWRITE_TAC[REWRITE_RULE[num_CONV (Term`4`, INV_SUC_EQ] th]]) + (fn th => REWRITE_TAC[REWRITE_RULE[num_CONV (Term`4`), INV_SUC_EQ] th]) } From 0278ba3a94144ea4adcce5f5a79eb01cba886a0f Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Mon, 20 Oct 2014 13:16:33 +0100 Subject: [PATCH 011/718] pair: with T1 encoding one can search for names with underscodes in PDF --- src/pair/Manual/description.tex | 2 +- src/pair/Manual/pair.tex | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/pair/Manual/description.tex b/src/pair/Manual/description.tex index 11a780cf99..25f77cb8ad 100644 --- a/src/pair/Manual/description.tex +++ b/src/pair/Manual/description.tex @@ -232,7 +232,7 @@ \section{The pair Library Philosophy} \section{Bugs and Future Changes} -At the time of release there were no known bugs in the system. +At the time of release there were no known bugs in the library. However, this is more likely to be a result of poor testing than of good coding. If you do find a bug please report it to me, preferably along with a short example that exhibits the bug and the version number of the diff --git a/src/pair/Manual/pair.tex b/src/pair/Manual/pair.tex index c976271c90..9881519a2a 100644 --- a/src/pair/Manual/pair.tex +++ b/src/pair/Manual/pair.tex @@ -7,6 +7,7 @@ \usepackage{fleqn} \usepackage{alltt} \usepackage{../../..//Manual/LaTeX/layout} +\usepackage[T1]{fontenc} % --------------------------------------------------------------------- % Input defined macros and commands From dabaaf6812c7459d7c5d01c4c5dd6a71507e3305 Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Mon, 20 Oct 2014 13:17:18 +0100 Subject: [PATCH 012/718] pair: export pvariant function, as it is already listed in manual --- src/pair/Manual/description.tex | 2 +- src/pair/src/PairRules.sig | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/pair/Manual/description.tex b/src/pair/Manual/description.tex index 25f77cb8ad..ffd7f80289 100644 --- a/src/pair/Manual/description.tex +++ b/src/pair/Manual/description.tex @@ -56,7 +56,7 @@ \chapter{The pair Library} BETA\_CONV & PBETA\_CONV \\ BETA\_RULE & PBETA\_RULE \\ BETA\_TAC & PBETA\_TAC \\ - bndvar & bndpair \\ + bvar & pbvar \\ body & pbody \\ CHOOSE & PCHOOSE \\ CHOOSE\_TAC & PCHOOSE\_TAC \\ diff --git a/src/pair/src/PairRules.sig b/src/pair/src/PairRules.sig index 3f6afcafb8..5fd9b56188 100644 --- a/src/pair/src/PairRules.sig +++ b/src/pair/src/PairRules.sig @@ -114,4 +114,6 @@ sig val PMATCH_MP_TAC : thm_tactic val PMATCH_MP : thm -> thm -> thm + val pvariant : term list -> term -> term + end From 15a21307bac00aa280a5a029a0bcc52f83b367b1 Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Wed, 22 Oct 2014 23:31:42 +0100 Subject: [PATCH 013/718] guide: grammar fix --- Manual/Guide/guide.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Manual/Guide/guide.tex b/Manual/Guide/guide.tex index f628c054f2..1bae719408 100644 --- a/Manual/Guide/guide.tex +++ b/Manual/Guide/guide.tex @@ -427,7 +427,7 @@ \section{Generation of the LaTeX source} Each \id\doc\ file is in a special format (described below), from which the \latex\ source for a manual entry on the \ML\ identifier \id\ can be generated. -The file {\tt bin/doc-to-tex.sed} is the {\tt sed} script used generate \latex\ +The file {\tt bin/doc-to-tex.sed} is the {\tt sed} script used to generate \latex\ source text from \doc\ files. Executing: \begin{itemize} From 08d7a55835eacf88f47be119cf094646b981a0e0 Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Thu, 23 Oct 2014 10:46:09 +0100 Subject: [PATCH 014/718] trailing newlines in *.{sml,sig} files from src/ removed Trailing newlines from SML files in src/ were rendered in HTML documentation. --- src/0/Subst.sig | 3 --- src/0/Type.sig | 3 --- src/1/BoolExtractShared.sig | 1 - src/1/ConseqConv.sig | 1 - src/1/dep_rewrite.sig | 1 - src/1/dep_rewrite.sml | 1 - src/HolSat/HolSatLib.sml | 2 -- src/HolSat/def_cnf.sml | 1 - src/HolSat/minisatProve.sml | 2 -- src/HolSat/minisatResolve.sml | 2 -- src/HolSat/satTools.sml | 1 - src/TeX/mkmkmunge.sml | 4 ---- src/combin/combinScript.sml | 1 - src/compute/examples/MergeSort.sml | 2 -- src/compute/examples/Sort.sml | 1 - src/datatype/DatatypeSimps.sig | 1 - src/datatype/mutrec/ConsThms.sml | 1 - src/datatype/mutrec/MutRecDef.sml | 1 - src/datatype/record/RecordType.sig | 2 -- src/enumfset/tcScript.sml | 1 - src/finite_map/fmaptreeScript.sml | 2 -- src/integer/OmegaMath.sig | 1 - src/integer/OmegaScript.sml | 1 - src/integer/testing/selftest.sml | 1 - src/integer/testing/test_coopers.sml | 1 - src/integer/testing/test_omega.sml | 2 -- src/marker/markerScript.sml | 1 - src/meson/src/Canon_Port.sig | 1 - src/meson/test.sml | 2 -- src/metis/mlibOmega.sig | 1 - src/metis/mlibSubst.sig | 1 - src/monad/parmonadsyntax2.sml | 2 -- src/num/arith/src/GenPolyCanon.sig | 2 -- src/num/extra_theories/numpairScript.sml | 1 - src/num/theories/DecimalFractionPP.sml | 1 - src/num/theories/basicSizeScript.sml | 1 - src/option/optionSimps.sig | 1 - src/parse/CharSet.sml | 1 - src/parse/ProvideUnicode.sig | 1 - src/parse/base_tokens.sig | 1 - src/parse/errormonad.sml | 3 --- src/parse/parse_term.sig | 1 - src/parse/qbuf.sml | 4 ---- src/parse/term_pp.sig | 1 - src/parse/term_pp_utils.sig | 2 -- src/parse/term_tokens.sig | 1 - src/path/pathScript.sml | 1 - src/pfl/index.sml | 1 - src/portableML/Arbnum.sml | 1 - src/portableML/poly/Susp.sml | 1 - src/pred_set/src/gcdsetScript.sml | 1 - src/prekernel/KernelSig.sml | 1 - src/prekernel/Nonce.sig | 2 -- src/quantHeuristics/selftest.sml | 1 - src/quotient/examples/lambda/barendregt.sig | 1 - src/quotient/examples/lambda/more_listScript.sml | 1 - src/quotient/examples/lambda/more_setScript.sml | 1 - src/quotient/examples/sigma/barendregt.sig | 1 - src/quotient/examples/sigma/more_listScript.sml | 1 - src/quotient/examples/sigma/more_setScript.sml | 1 - src/quotient/src/quotientLib.sml | 1 - src/quotient/src/quotientScript.sml | 1 - src/quotient/src/quotient_listScript.sml | 1 - src/quotient/src/quotient_optionScript.sml | 1 - src/quotient/src/quotient_pairScript.sml | 1 - src/quotient/src/quotient_pred_setScript.sml | 1 - src/quotient/src/quotient_sumScript.sml | 1 - src/rational/fracScript.sml | 1 - src/rational/intExtensionScript.sml | 1 - src/real/polyScript.sml | 1 - src/refute/AC.sig | 1 - src/refute/Canon.sig | 1 - src/ring/src/numRingScript.sml | 1 - src/simp/src/Opening.sig | 2 -- src/simp/src/Opening.sml | 1 - src/simp/src/Satisfy.sig | 1 - src/simp/src/Sequence.sig | 2 -- src/simp/src/Sequence.sml | 1 - src/simp/src/Travrules.sig | 3 --- src/simp/src/Unify.sig | 1 - src/simp/src/boolSimps.sig | 1 - src/simp/src/congLib.sig | 1 - src/simp/test.sml | 8 -------- src/string/selftest.sml | 4 ---- src/string/stringSimps.sml | 1 - src/string/stringSyntax.sig | 1 - src/string/theorytesting/otherScript.sml | 1 - src/string/theorytesting/sampleScript.sml | 1 - src/temporal/src/Temporal_LogicScript.sml | 2 -- 89 files changed, 128 deletions(-) diff --git a/src/0/Subst.sig b/src/0/Subst.sig index cc96d7585b..0a866e69e4 100644 --- a/src/0/Subst.sig +++ b/src/0/Subst.sig @@ -11,6 +11,3 @@ sig val comp : ('a subs * 'a -> 'a) -> 'a subs * 'a subs -> 'a subs; end; - - - diff --git a/src/0/Type.sig b/src/0/Type.sig index 3051a6ad20..f873c5ad39 100644 --- a/src/0/Type.sig +++ b/src/0/Type.sig @@ -4,6 +4,3 @@ sig include FinalType where type hol_type = KernelTypes.hol_type end; - - - diff --git a/src/1/BoolExtractShared.sig b/src/1/BoolExtractShared.sig index de48f8fbb1..5f9ded788c 100644 --- a/src/1/BoolExtractShared.sig +++ b/src/1/BoolExtractShared.sig @@ -19,4 +19,3 @@ val BOOL_NEG_PAIR_convdata : simpfrag.convdata; end - diff --git a/src/1/ConseqConv.sig b/src/1/ConseqConv.sig index 5322f97221..60f417c35a 100644 --- a/src/1/ConseqConv.sig +++ b/src/1/ConseqConv.sig @@ -243,4 +243,3 @@ val EXT_CONTEXT_CONSEQ_HO_REWRITE_TAC : CONSEQ_CONV_context -> (thm list -> co end - diff --git a/src/1/dep_rewrite.sig b/src/1/dep_rewrite.sig index 16a3c58e16..49bae15a4a 100644 --- a/src/1/dep_rewrite.sig +++ b/src/1/dep_rewrite.sig @@ -244,4 +244,3 @@ end; (* END OF DEPENDENT REWRITING TACTICS *) (* ================================================================== *) (* ================================================================== *) - diff --git a/src/1/dep_rewrite.sml b/src/1/dep_rewrite.sml index c262725d02..b64b686278 100644 --- a/src/1/dep_rewrite.sml +++ b/src/1/dep_rewrite.sml @@ -813,4 +813,3 @@ e(DEP_ONCE_REWRITE_TAC[RIGHT_FORALL_IMP_THM]); drop(); *) - diff --git a/src/HolSat/HolSatLib.sml b/src/HolSat/HolSatLib.sml index 43a23c813d..3f20aa8fbb 100644 --- a/src/HolSat/HolSatLib.sml +++ b/src/HolSat/HolSatLib.sml @@ -12,5 +12,3 @@ exception SAT_cex = minisatProve.SAT_cex open satTools dimacsTools SatSolvers minisatProve satConfig end; - - diff --git a/src/HolSat/def_cnf.sml b/src/HolSat/def_cnf.sml index 537aaf6649..4abbb297d3 100644 --- a/src/HolSat/def_cnf.sml +++ b/src/HolSat/def_cnf.sml @@ -241,4 +241,3 @@ List.app (fn eq => end end - diff --git a/src/HolSat/minisatProve.sml b/src/HolSat/minisatProve.sml index fd1230492d..14e9f67d76 100644 --- a/src/HolSat/minisatProve.sml +++ b/src/HolSat/minisatProve.sml @@ -138,5 +138,3 @@ fun ZSAT_ORACLE tm = GEN_SAT ((set_term tm o set_flag_is_proved false) zchaff_co end end - - diff --git a/src/HolSat/minisatResolve.sml b/src/HolSat/minisatResolve.sml index 7c4b067389..a30516bf01 100644 --- a/src/HolSat/minisatResolve.sml +++ b/src/HolSat/minisatResolve.sml @@ -107,5 +107,3 @@ fun resolveChain lfn sva cl (nl,lnl) rci = end end - - diff --git a/src/HolSat/satTools.sml b/src/HolSat/satTools.sml index 7a2e718f8a..0ae8d10c3b 100644 --- a/src/HolSat/satTools.sml +++ b/src/HolSat/satTools.sml @@ -132,4 +132,3 @@ fun satCheck model t = end end - diff --git a/src/TeX/mkmkmunge.sml b/src/TeX/mkmkmunge.sml index 4af4475155..94118dbbb3 100644 --- a/src/TeX/mkmkmunge.sml +++ b/src/TeX/mkmkmunge.sml @@ -19,7 +19,3 @@ val _ = systeml "-I", HOLDIR ++ "src" ++ "TeX"] @ toload @ [HOLDIR ++ "src" ++ "TeX" ++ "mosmlmunge.uo"]) - - - - diff --git a/src/combin/combinScript.sml b/src/combin/combinScript.sml index 8810a757d8..b8201a2fec 100644 --- a/src/combin/combinScript.sml +++ b/src/combin/combinScript.sml @@ -312,4 +312,3 @@ val _ = adjoin_to_theory end)}; val _ = export_theory(); - diff --git a/src/compute/examples/MergeSort.sml b/src/compute/examples/MergeSort.sml index c90acc68f8..db09c007fd 100644 --- a/src/compute/examples/MergeSort.sml +++ b/src/compute/examples/MergeSort.sml @@ -159,5 +159,3 @@ val srws = flatten (map BODY_CONJUNCTS (COND_CLAUSES :: sort_thms)); fun simp_norm q = time (SIMP_CONV empty_ss srws) (--q--); simp_norm `merge_sort L12`; (* ~ 5s *) - - diff --git a/src/compute/examples/Sort.sml b/src/compute/examples/Sort.sml index b959fc8305..7d4023cb4a 100644 --- a/src/compute/examples/Sort.sml +++ b/src/compute/examples/Sort.sml @@ -64,4 +64,3 @@ time (funpow 100 (fn() => (tri_heap (L200()); ()))) (); (* ~ 0.36s *) time (funpow 100 (fn() => (tri_heap (L1200()); ()))) (); (* ~ 4.17s *) time (funpow 10 (fn() => (tri_heap (L19200()); ()))) (); (* ~ 15.7s *) time (funpow 10 (fn() => (tri_heap (L38400()); ()))) (); (* ~ 43.3s *) - diff --git a/src/datatype/DatatypeSimps.sig b/src/datatype/DatatypeSimps.sig index 1e3b4b20b3..07123d07c0 100644 --- a/src/datatype/DatatypeSimps.sig +++ b/src/datatype/DatatypeSimps.sig @@ -117,4 +117,3 @@ val expand_type_quants_stateful_ss : unit -> ssfrag val cases_to_top_RULE : rule end - diff --git a/src/datatype/mutrec/ConsThms.sml b/src/datatype/mutrec/ConsThms.sml index 94e84cf38d..f82c941f1f 100644 --- a/src/datatype/mutrec/ConsThms.sml +++ b/src/datatype/mutrec/ConsThms.sml @@ -662,4 +662,3 @@ end; val _ = Parse.temp_set_grammars ambient_grammars end (* ConsThms *) - diff --git a/src/datatype/mutrec/MutRecDef.sml b/src/datatype/mutrec/MutRecDef.sml index 9c1de944b1..cb8d667557 100644 --- a/src/datatype/mutrec/MutRecDef.sml +++ b/src/datatype/mutrec/MutRecDef.sml @@ -1477,4 +1477,3 @@ end val _ = Parse.temp_set_grammars ambient_grammars end (* MutRecDef *) - diff --git a/src/datatype/record/RecordType.sig b/src/datatype/record/RecordType.sig index 222bb280bd..d6f7a8c3c4 100644 --- a/src/datatype/record/RecordType.sig +++ b/src/datatype/record/RecordType.sig @@ -25,5 +25,3 @@ end accessor and update information. *) - - diff --git a/src/enumfset/tcScript.sml b/src/enumfset/tcScript.sml index ac40997441..ad6f007683 100644 --- a/src/enumfset/tcScript.sml +++ b/src/enumfset/tcScript.sml @@ -635,4 +635,3 @@ val _ = export_theory (); val _ = print_theory "-"; end; (* struct *) - diff --git a/src/finite_map/fmaptreeScript.sml b/src/finite_map/fmaptreeScript.sml index 3a4a6ce5ed..908a9e11bf 100644 --- a/src/finite_map/fmaptreeScript.sml +++ b/src/finite_map/fmaptreeScript.sml @@ -247,5 +247,3 @@ val fmtree_Axiom = store_thm( SRW_TAC [][fmtreerec_thm]); val _ = export_theory() - - diff --git a/src/integer/OmegaMath.sig b/src/integer/OmegaMath.sig index 77dec05281..3c3a500a0b 100644 --- a/src/integer/OmegaMath.sig +++ b/src/integer/OmegaMath.sig @@ -148,4 +148,3 @@ end; *) - diff --git a/src/integer/OmegaScript.sml b/src/integer/OmegaScript.sml index b9002e6ba0..c4524515a7 100644 --- a/src/integer/OmegaScript.sml +++ b/src/integer/OmegaScript.sml @@ -1078,4 +1078,3 @@ val calculational_nightmare = store_thm( PROVE_TAC []); val _ = export_theory(); - diff --git a/src/integer/testing/selftest.sml b/src/integer/testing/selftest.sml index 27aa4e44f7..a7132c597e 100644 --- a/src/integer/testing/selftest.sml +++ b/src/integer/testing/selftest.sml @@ -30,4 +30,3 @@ val cooper_result = val _ = Process.exit (if cooper_result andalso omega_result then Process.success else Process.failure) - diff --git a/src/integer/testing/test_coopers.sml b/src/integer/testing/test_coopers.sml index e402f949a6..d2a82f6b02 100644 --- a/src/integer/testing/test_coopers.sml +++ b/src/integer/testing/test_coopers.sml @@ -11,4 +11,3 @@ val _ = | _ => Profile.print_profile_results (Profile.results()) val _ = Process.exit (if result then Process.success else Process.failure) - diff --git a/src/integer/testing/test_omega.sml b/src/integer/testing/test_omega.sml index 5de3892aa4..be6e76e73f 100644 --- a/src/integer/testing/test_omega.sml +++ b/src/integer/testing/test_omega.sml @@ -8,5 +8,3 @@ val _ = case CommandLine.arguments() of [] => () | _ => Profile.print_profile_results (Profile.results()) val _ = Process.exit (if result then Process.success else Process.failure) - - diff --git a/src/marker/markerScript.sml b/src/marker/markerScript.sml index c7737678bc..3b5f10e79c 100644 --- a/src/marker/markerScript.sml +++ b/src/marker/markerScript.sml @@ -126,4 +126,3 @@ val label_def = new_definition( ``((lab:label) :- (argument:bool)) = argument``); val _ = export_theory(); - diff --git a/src/meson/src/Canon_Port.sig b/src/meson/src/Canon_Port.sig index a8e7831681..2a5f1a8d6a 100644 --- a/src/meson/src/Canon_Port.sig +++ b/src/meson/src/Canon_Port.sig @@ -15,4 +15,3 @@ sig val REFUTE_THEN : (thm -> tactic) -> tactic val GEN_FOL_CONV : (term*int)list * (term*int) list -> conv end; - diff --git a/src/meson/test.sml b/src/meson/test.sml index 7d4756168f..a507bb36df 100644 --- a/src/meson/test.sml +++ b/src/meson/test.sml @@ -3418,5 +3418,3 @@ Lib.with_flag(Globals.guessing_tyvars,true) (!X U Y. subset_collections(X,Y) /\ element_of_collection(U,X) ==> element_of_collection(U,Y)) /\ (subset_collections(g,top_of_basis(f))) /\ (~element_of_collection(union_of_members(g),top_of_basis(f))) ==> F`; - - diff --git a/src/metis/mlibOmega.sig b/src/metis/mlibOmega.sig index 7239a3ef0b..dc9720f07a 100644 --- a/src/metis/mlibOmega.sig +++ b/src/metis/mlibOmega.sig @@ -49,4 +49,3 @@ end ---------------------------------------------------------------------- *) (* a derivation represents a proof of a factoid *) - diff --git a/src/metis/mlibSubst.sig b/src/metis/mlibSubst.sig index ce5d84d233..d1b2cb6dd7 100644 --- a/src/metis/mlibSubst.sig +++ b/src/metis/mlibSubst.sig @@ -31,4 +31,3 @@ val foldr : ((string, term) maplet -> 'a -> 'a) -> 'a -> subst -> 'a val pp_subst : subst pp end - diff --git a/src/monad/parmonadsyntax2.sml b/src/monad/parmonadsyntax2.sml index 049358c163..b2e27e4139 100644 --- a/src/monad/parmonadsyntax2.sml +++ b/src/monad/parmonadsyntax2.sml @@ -293,5 +293,3 @@ end val _ = temp_add_user_printer ("parmonadsyntax.print_monads", ``x:'a``, print_monads) - - diff --git a/src/num/arith/src/GenPolyCanon.sig b/src/num/arith/src/GenPolyCanon.sig index 395d1dba30..5ec9dd9b2d 100644 --- a/src/num/arith/src/GenPolyCanon.sig +++ b/src/num/arith/src/GenPolyCanon.sig @@ -87,5 +87,3 @@ end; theorems. *) - - diff --git a/src/num/extra_theories/numpairScript.sml b/src/num/extra_theories/numpairScript.sml index ca54cc1cb5..70fba5a8b5 100644 --- a/src/num/extra_theories/numpairScript.sml +++ b/src/num/extra_theories/numpairScript.sml @@ -304,4 +304,3 @@ val nlist_cases = store_thm( val _ = export_theory() - diff --git a/src/num/theories/DecimalFractionPP.sml b/src/num/theories/DecimalFractionPP.sml index d27a6adf13..8ff8d6f08d 100644 --- a/src/num/theories/DecimalFractionPP.sml +++ b/src/num/theories/DecimalFractionPP.sml @@ -51,4 +51,3 @@ in end end - diff --git a/src/num/theories/basicSizeScript.sml b/src/num/theories/basicSizeScript.sml index 8910174541..f5df8da8f2 100644 --- a/src/num/theories/basicSizeScript.sml +++ b/src/num/theories/basicSizeScript.sml @@ -28,4 +28,3 @@ val option_size_def = rec_axiom = optionTheory.option_Axiom}; val _ = export_theory(); - diff --git a/src/option/optionSimps.sig b/src/option/optionSimps.sig index eb6945004b..541908f89f 100644 --- a/src/option/optionSimps.sig +++ b/src/option/optionSimps.sig @@ -2,4 +2,3 @@ signature optionSimps = sig val OPTION_ss : simpLib.ssfrag end - diff --git a/src/parse/CharSet.sml b/src/parse/CharSet.sml index 499e22487a..2fb65cc1a7 100644 --- a/src/parse/CharSet.sml +++ b/src/parse/CharSet.sml @@ -86,4 +86,3 @@ struct end end; - diff --git a/src/parse/ProvideUnicode.sig b/src/parse/ProvideUnicode.sig index d61e317540..8c0ba87f33 100644 --- a/src/parse/ProvideUnicode.sig +++ b/src/parse/ProvideUnicode.sig @@ -40,4 +40,3 @@ val reader : ThyUpdateInfo Coding.reader end - diff --git a/src/parse/base_tokens.sig b/src/parse/base_tokens.sig index 09c7f22b89..ea9b9896e8 100644 --- a/src/parse/base_tokens.sig +++ b/src/parse/base_tokens.sig @@ -21,4 +21,3 @@ sig val parse_fraction : string * locn.locn -> fracinfo end - diff --git a/src/parse/errormonad.sml b/src/parse/errormonad.sml index 9270f1bdc8..5b22b4c0ea 100644 --- a/src/parse/errormonad.sml +++ b/src/parse/errormonad.sml @@ -49,6 +49,3 @@ end fun repeat p env = ((p >> repeat p) ++ ok) env end - - - diff --git a/src/parse/parse_term.sig b/src/parse/parse_term.sig index 8ab188011d..43e1f0ad02 100644 --- a/src/parse/parse_term.sig +++ b/src/parse/parse_term.sig @@ -28,4 +28,3 @@ sig end - diff --git a/src/parse/qbuf.sml b/src/parse/qbuf.sml index 29578529ea..0be47b5a36 100644 --- a/src/parse/qbuf.sml +++ b/src/parse/qbuf.sml @@ -123,7 +123,3 @@ struct end end; - - - - diff --git a/src/parse/term_pp.sig b/src/parse/term_pp.sig index 092ac4635d..3bdf819f45 100644 --- a/src/parse/term_pp.sig +++ b/src/parse/term_pp.sig @@ -13,4 +13,3 @@ sig val init_casesplit_munger : (term -> term * (term * term) list) -> unit end - diff --git a/src/parse/term_pp_utils.sig b/src/parse/term_pp_utils.sig index 3e4c8fea00..1cc8cffdf3 100644 --- a/src/parse/term_pp_utils.sig +++ b/src/parse/term_pp_utils.sig @@ -16,5 +16,3 @@ sig val get_gspec : (term_pp_types.printing_info,bool) smpp.t end - - diff --git a/src/parse/term_tokens.sig b/src/parse/term_tokens.sig index f80eea5ae7..a650da0607 100644 --- a/src/parse/term_tokens.sig +++ b/src/parse/term_tokens.sig @@ -25,4 +25,3 @@ sig val lextest : string list -> string -> 'a term_token list end - diff --git a/src/path/pathScript.sml b/src/path/pathScript.sml index 4d4220d69f..f00affd313 100644 --- a/src/path/pathScript.sml +++ b/src/path/pathScript.sml @@ -1811,4 +1811,3 @@ SRW_TAC [] [] THENL val _ = export_theory(); - diff --git a/src/pfl/index.sml b/src/pfl/index.sml index 5d6c118310..b1bdae3de2 100644 --- a/src/pfl/index.sml +++ b/src/pfl/index.sml @@ -541,4 +541,3 @@ e (pbase_clause pfn_def idef limspec ifn_def_pos); (* Recursive case *) (* Recursive case *) - diff --git a/src/portableML/Arbnum.sml b/src/portableML/Arbnum.sml index d9a1622601..20fafeaf95 100644 --- a/src/portableML/Arbnum.sml +++ b/src/portableML/Arbnum.sml @@ -20,4 +20,3 @@ in end end - diff --git a/src/portableML/poly/Susp.sml b/src/portableML/poly/Susp.sml index da6e120bd4..308c99b638 100644 --- a/src/portableML/poly/Susp.sml +++ b/src/portableML/poly/Susp.sml @@ -14,4 +14,3 @@ fun force (su : 'a susp) : 'a = | THUNK f => let val v = f () in su := VAL v; v end end (* struct *) - diff --git a/src/pred_set/src/gcdsetScript.sml b/src/pred_set/src/gcdsetScript.sml index b9a4dab846..f7bfcc546c 100644 --- a/src/pred_set/src/gcdsetScript.sml +++ b/src/pred_set/src/gcdsetScript.sml @@ -86,4 +86,3 @@ val _ = export_rewrites ["gcdset_INSERT"] val _ = export_theory() - diff --git a/src/prekernel/KernelSig.sml b/src/prekernel/KernelSig.sml index 498b3a368a..5448ff6683 100644 --- a/src/prekernel/KernelSig.sml +++ b/src/prekernel/KernelSig.sml @@ -92,4 +92,3 @@ struct end - diff --git a/src/prekernel/Nonce.sig b/src/prekernel/Nonce.sig index bf25a08d83..e867e18546 100644 --- a/src/prekernel/Nonce.sig +++ b/src/prekernel/Nonce.sig @@ -6,5 +6,3 @@ sig val dest : 'a t -> 'a end - - diff --git a/src/quantHeuristics/selftest.sml b/src/quantHeuristics/selftest.sml index 9ad009a8a3..3fc3cf62b6 100644 --- a/src/quantHeuristics/selftest.sml +++ b/src/quantHeuristics/selftest.sml @@ -317,4 +317,3 @@ val _ = map (qh_test_context2 hard_fail quiet) qh_testCases_context2; val _ = Process.exit Process.success; - diff --git a/src/quotient/examples/lambda/barendregt.sig b/src/quotient/examples/lambda/barendregt.sig index 4640217aec..6277a234fe 100644 --- a/src/quotient/examples/lambda/barendregt.sig +++ b/src/quotient/examples/lambda/barendregt.sig @@ -25,4 +25,3 @@ val MAKE_SIMPLE_SUBST_TAC : tactic val SIMPLE_SUBST_TAC : tactic end; - diff --git a/src/quotient/examples/lambda/more_listScript.sml b/src/quotient/examples/lambda/more_listScript.sml index b59f4e0cc7..e5391f27bc 100644 --- a/src/quotient/examples/lambda/more_listScript.sml +++ b/src/quotient/examples/lambda/more_listScript.sml @@ -171,4 +171,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "more_list.lst"; val _ = html_theory "more_list"; - diff --git a/src/quotient/examples/lambda/more_setScript.sml b/src/quotient/examples/lambda/more_setScript.sml index fc4950f277..f9f9c39796 100644 --- a/src/quotient/examples/lambda/more_setScript.sml +++ b/src/quotient/examples/lambda/more_setScript.sml @@ -770,4 +770,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "more_set.lst"; val _ = html_theory "more_set"; - diff --git a/src/quotient/examples/sigma/barendregt.sig b/src/quotient/examples/sigma/barendregt.sig index d5a5275bfb..34bc8eace1 100644 --- a/src/quotient/examples/sigma/barendregt.sig +++ b/src/quotient/examples/sigma/barendregt.sig @@ -24,4 +24,3 @@ val MAKE_SIMPLE_SUBST_TAC : tactic val SIMPLE_SUBST_TAC : tactic end; - diff --git a/src/quotient/examples/sigma/more_listScript.sml b/src/quotient/examples/sigma/more_listScript.sml index b59f4e0cc7..e5391f27bc 100644 --- a/src/quotient/examples/sigma/more_listScript.sml +++ b/src/quotient/examples/sigma/more_listScript.sml @@ -171,4 +171,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "more_list.lst"; val _ = html_theory "more_list"; - diff --git a/src/quotient/examples/sigma/more_setScript.sml b/src/quotient/examples/sigma/more_setScript.sml index fc4950f277..f9f9c39796 100644 --- a/src/quotient/examples/sigma/more_setScript.sml +++ b/src/quotient/examples/sigma/more_setScript.sml @@ -770,4 +770,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "more_set.lst"; val _ = html_theory "more_set"; - diff --git a/src/quotient/src/quotientLib.sml b/src/quotient/src/quotientLib.sml index 299c370c89..dc6f993814 100644 --- a/src/quotient/src/quotientLib.sml +++ b/src/quotient/src/quotientLib.sml @@ -8,4 +8,3 @@ struct open quotient_pred_setTheory open quotient end - diff --git a/src/quotient/src/quotientScript.sml b/src/quotient/src/quotientScript.sml index 1da867c2b9..3633f19b73 100644 --- a/src/quotient/src/quotientScript.sml +++ b/src/quotient/src/quotientScript.sml @@ -1832,4 +1832,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "quotient.lst"; val _ = html_theory "quotient"; - diff --git a/src/quotient/src/quotient_listScript.sml b/src/quotient/src/quotient_listScript.sml index 5100bded43..3ffe118b3b 100644 --- a/src/quotient/src/quotient_listScript.sml +++ b/src/quotient/src/quotient_listScript.sml @@ -655,4 +655,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "quotient_list.lst"; val _ = html_theory "quotient_list"; - diff --git a/src/quotient/src/quotient_optionScript.sml b/src/quotient/src/quotient_optionScript.sml index a8dfca7b9b..ce3553fac1 100644 --- a/src/quotient/src/quotient_optionScript.sml +++ b/src/quotient/src/quotient_optionScript.sml @@ -263,4 +263,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "quotient_option.lst"; val _ = html_theory "quotient_option"; - diff --git a/src/quotient/src/quotient_pairScript.sml b/src/quotient/src/quotient_pairScript.sml index 1ff86d6c40..1e2d746932 100644 --- a/src/quotient/src/quotient_pairScript.sml +++ b/src/quotient/src/quotient_pairScript.sml @@ -382,4 +382,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "quotient_pair.lst"; val _ = html_theory "quotient_pair"; - diff --git a/src/quotient/src/quotient_pred_setScript.sml b/src/quotient/src/quotient_pred_setScript.sml index 8f3d3192af..370c5f55d2 100644 --- a/src/quotient/src/quotient_pred_setScript.sml +++ b/src/quotient/src/quotient_pred_setScript.sml @@ -994,4 +994,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "quotient_pred_set.lst"; val _ = html_theory "quotient_pred_set"; - diff --git a/src/quotient/src/quotient_sumScript.sml b/src/quotient/src/quotient_sumScript.sml index eda6b86c5b..d8dbaf432f 100644 --- a/src/quotient/src/quotient_sumScript.sml +++ b/src/quotient/src/quotient_sumScript.sml @@ -291,4 +291,3 @@ val _ = export_theory(); val _ = print_theory_to_file "-" "quotient_sum.lst"; val _ = html_theory "quotient_sum"; - diff --git a/src/rational/fracScript.sml b/src/rational/fracScript.sml index 70655484e9..50edb2f3f5 100644 --- a/src/rational/fracScript.sml +++ b/src/rational/fracScript.sml @@ -1028,4 +1028,3 @@ val FRAC_MUL_SAVE = store_thm( *==========================================================================*) val _ = export_theory(); - diff --git a/src/rational/intExtensionScript.sml b/src/rational/intExtensionScript.sml index 14dc05d386..1b3fe4b006 100644 --- a/src/rational/intExtensionScript.sml +++ b/src/rational/intExtensionScript.sml @@ -336,4 +336,3 @@ val INT_LT_ADD_NEG = store_thm("INT_LT_ADD_NEG", ``!x y. x < 0i /\ y < 0i ==> x val _ = export_theory(); - diff --git a/src/real/polyScript.sml b/src/real/polyScript.sml index 9ead8709dd..2f35e0e84e 100644 --- a/src/real/polyScript.sml +++ b/src/real/polyScript.sml @@ -1430,4 +1430,3 @@ val POLY_NORMALIZE_CONV = val _ = export_theory (); end; - diff --git a/src/refute/AC.sig b/src/refute/AC.sig index 83e6cc6229..ea360eaead 100644 --- a/src/refute/AC.sig +++ b/src/refute/AC.sig @@ -13,4 +13,3 @@ sig val ASSOC_CONV : thm -> conv val DISTRIB_CONV : thm * thm -> conv end - diff --git a/src/refute/Canon.sig b/src/refute/Canon.sig index 1ff5605e28..5766633057 100644 --- a/src/refute/Canon.sig +++ b/src/refute/Canon.sig @@ -35,4 +35,3 @@ sig val latest : (thm * thm * term) option ref; end (* sig *) - diff --git a/src/ring/src/numRingScript.sml b/src/ring/src/numRingScript.sml index 6ac978c706..068135d1f1 100644 --- a/src/ring/src/numRingScript.sml +++ b/src/ring/src/numRingScript.sml @@ -36,4 +36,3 @@ end; val _ = temp_overload_on("mult",--`$* : num->num->num`--); val _ = export_theory(); - diff --git a/src/simp/src/Opening.sig b/src/simp/src/Opening.sig index b050940127..85f0054ef9 100644 --- a/src/simp/src/Opening.sig +++ b/src/simp/src/Opening.sig @@ -92,5 +92,3 @@ signature Opening = sig val EQ_CONGPROC : congproc end (* sig *) - - diff --git a/src/simp/src/Opening.sml b/src/simp/src/Opening.sml index aad7eefbbb..8bfe62b64b 100644 --- a/src/simp/src/Opening.sml +++ b/src/simp/src/Opening.sml @@ -265,4 +265,3 @@ fun EQ_CONGPROC {relation,depther,solver,freevars} tm = end (* struct *) - diff --git a/src/simp/src/Satisfy.sig b/src/simp/src/Satisfy.sig index 360bcbb744..f1d148d60c 100644 --- a/src/simp/src/Satisfy.sig +++ b/src/simp/src/Satisfy.sig @@ -49,4 +49,3 @@ signature Satisfy = sig val SATISFY_TAC : tactic val add_facts : factdb -> thm list -> factdb end (* sig *) - diff --git a/src/simp/src/Sequence.sig b/src/simp/src/Sequence.sig index 0b807bfd07..5ea1686924 100644 --- a/src/simp/src/Sequence.sig +++ b/src/simp/src/Sequence.sig @@ -38,5 +38,3 @@ signature Sequence = sig val seq_diagonalize : 'a seq -> 'b seq -> ('a * 'b) seq val seq_permutations : 'a list -> 'a list seq end (* sig *) - - diff --git a/src/simp/src/Sequence.sml b/src/simp/src/Sequence.sml index c4378fb287..3ca3574863 100644 --- a/src/simp/src/Sequence.sml +++ b/src/simp/src/Sequence.sml @@ -173,4 +173,3 @@ fun seq_permutations l = end (* struct *) - diff --git a/src/simp/src/Travrules.sig b/src/simp/src/Travrules.sig index ecf7c85dd4..e6bf07ce17 100644 --- a/src/simp/src/Travrules.sig +++ b/src/simp/src/Travrules.sig @@ -94,6 +94,3 @@ sig val EQ_tr : travrules end (* sig *) - - - diff --git a/src/simp/src/Unify.sig b/src/simp/src/Unify.sig index 624ae0859e..097e2b8ed5 100644 --- a/src/simp/src/Unify.sig +++ b/src/simp/src/Unify.sig @@ -22,4 +22,3 @@ sig val restrict_tmenv :(term -> bool) -> (term,term)subst -> (term,term)subst end - diff --git a/src/simp/src/boolSimps.sig b/src/simp/src/boolSimps.sig index eea5e93489..a2e87f1a2e 100644 --- a/src/simp/src/boolSimps.sig +++ b/src/simp/src/boolSimps.sig @@ -67,4 +67,3 @@ sig end - diff --git a/src/simp/src/congLib.sig b/src/simp/src/congLib.sig index 0e8fd668aa..8deb93c064 100644 --- a/src/simp/src/congLib.sig +++ b/src/simp/src/congLib.sig @@ -130,4 +130,3 @@ sig end - diff --git a/src/simp/test.sml b/src/simp/test.sml index 46ccd45f08..07782e29a7 100644 --- a/src/simp/test.sml +++ b/src/simp/test.sml @@ -67,11 +67,3 @@ CACHED_ARITH [] (--`3 < 1`--);; (* cache hit, failure *) val CC = SIMP_PROVE bool_ss [] (--`!P:'a->'b. (x = x') ==> (P x = P x')`--); val CC2 = SIMP_PROVE bool_ss [] (--`!P:'a->'b->'c. (x = x') /\ (y = y') ==> (P x y = P x' y')`--); SIMP_PROVE arith_ss [CC,CC2] (--`y >= z ==> z >= y ==> (P y (x + 2):bool = P z (2 + x))`--); - - - - - - - - diff --git a/src/string/selftest.sml b/src/string/selftest.sml index 3d39758756..d7734359a8 100644 --- a/src/string/selftest.sml +++ b/src/string/selftest.sml @@ -109,7 +109,3 @@ val _ = if s = "\"\\042)\"" then print "OK\n" val _ = OS.Process.exit OS.Process.success - - - - diff --git a/src/string/stringSimps.sml b/src/string/stringSimps.sml index 504ab361ae..cc27797fbb 100644 --- a/src/string/stringSimps.sml +++ b/src/string/stringSimps.sml @@ -8,4 +8,3 @@ val STRING_ss = BasicProvers.thy_ssfrag "string" val string_rewrites = frag_rewrites STRING_ss end - diff --git a/src/string/stringSyntax.sig b/src/string/stringSyntax.sig index 4aa9c78eda..453db11f25 100644 --- a/src/string/stringSyntax.sig +++ b/src/string/stringSyntax.sig @@ -184,4 +184,3 @@ sig val lift_string : hol_type -> string -> term end - diff --git a/src/string/theorytesting/otherScript.sml b/src/string/theorytesting/otherScript.sml index e19e0f5f9b..0e9bab2859 100644 --- a/src/string/theorytesting/otherScript.sml +++ b/src/string/theorytesting/otherScript.sml @@ -11,4 +11,3 @@ val _ = print "Successfully opened sampleTheory\n" val _ = export_theory(); - diff --git a/src/string/theorytesting/sampleScript.sml b/src/string/theorytesting/sampleScript.sml index cb7aa61fd0..2f4ed58328 100644 --- a/src/string/theorytesting/sampleScript.sml +++ b/src/string/theorytesting/sampleScript.sml @@ -6,4 +6,3 @@ val _ = Define `badstring = "*)"`; (* val _ = max_print_depth := 0; *) val _ = export_theory(); - diff --git a/src/temporal/src/Temporal_LogicScript.sml b/src/temporal/src/Temporal_LogicScript.sml index 8a8ad11f0b..c0cd112382 100644 --- a/src/temporal/src/Temporal_LogicScript.sml +++ b/src/temporal/src/Temporal_LogicScript.sml @@ -2999,5 +2999,3 @@ val _ = save_thm("NOT_SBEFORE",NOT_SBEFORE); val _ = export_theory(); (* html_theory "-"; *) - - From 82bb4a0ce5934b4446abc84b5d36b55ff20a82f0 Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Thu, 23 Oct 2014 11:09:24 +0100 Subject: [PATCH 015/718] whitespace cleanup: consistent use of tabs and spaces --- tools/mllex/mllex.sml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/mllex/mllex.sml b/tools/mllex/mllex.sml index a2db7db864..28344c5c22 100644 --- a/tools/mllex/mllex.sml +++ b/tools/mllex/mllex.sml @@ -955,7 +955,7 @@ fun maketable (fins:(int * (int list)) list, fun GetEndLeaf t = let fun f ((tl,el)::r) = if (tl=t) then el else f r | f [] = raise Fail "GetEndLeaf" - in f tcpairs + in f tcpairs end fun GetTrConLeaves s = let fun f ((s',l)::r) = if (s = s') then l else f r From e5cccb76f02564042172dfe01b1c382c6ea24c72 Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Fri, 24 Oct 2014 11:30:55 +0100 Subject: [PATCH 016/718] first_tok: error message improved; unused code removed --- src/parse/parse_term.sig | 3 +-- src/parse/parse_term.sml | 2 +- src/parse/term_grammar.sml | 2 +- src/parse/term_pp.sml | 4 ---- 4 files changed, 3 insertions(+), 8 deletions(-) diff --git a/src/parse/parse_term.sig b/src/parse/parse_term.sig index 43e1f0ad02..c72e75a25f 100644 --- a/src/parse/parse_term.sig +++ b/src/parse/parse_term.sig @@ -1,7 +1,7 @@ signature parse_term = sig type 'a PStack - type 'a qbuf= 'a qbuf.qbuf + type 'a qbuf = 'a qbuf.qbuf type stack_terminal = term_grammar.stack_terminal val initial_pstack : 'a PStack val is_final_pstack : 'a PStack -> bool @@ -26,5 +26,4 @@ sig term_grammar.grammar -> ((stack_terminal * bool) * stack_terminal, mx_order) Binarymap.dict ref - end diff --git a/src/parse/parse_term.sml b/src/parse/parse_term.sml index 67a27be9a2..9d8e300927 100644 --- a/src/parse/parse_term.sml +++ b/src/parse/parse_term.sml @@ -82,7 +82,7 @@ exception PrecConflict of stack_terminal * stack_terminal val complained_already = ref false; -fun first_tok [] = raise Fail "Shouldn't happen parse_term 133" +fun first_tok [] = raise Fail "Shouldn't happen: parse_term.first_tok" | first_tok (RE (TOK s)::_) = s | first_tok (_ :: t) = first_tok t diff --git a/src/parse/term_grammar.sml b/src/parse/term_grammar.sml index 94cc6e3298..c44a0b7640 100644 --- a/src/parse/term_grammar.sml +++ b/src/parse/term_grammar.sml @@ -468,7 +468,7 @@ val stdhol : grammar = absyn_postprocessors = [] } -fun first_tok [] = raise Fail "Shouldn't happen parse_term 133" +fun first_tok [] = raise Fail "Shouldn't happen: term_grammar.first_tok" | first_tok (RE (TOK s)::_) = s | first_tok (_ :: t) = first_tok t diff --git a/src/parse/term_pp.sml b/src/parse/term_pp.sml index 5d83f32fa6..4c2cd5f374 100644 --- a/src/parse/term_pp.sml +++ b/src/parse/term_pp.sml @@ -321,10 +321,6 @@ val prettyprint_bigrecs = ref true; val _ = register_btrace ("pp_bigrecs", prettyprint_bigrecs) -fun first_tok [] = raise Fail "Shouldn't happen term_pp 133" - | first_tok (RE (TOK s)::_) = s - | first_tok (_ :: t) = first_tok t - fun decdepth n = if n < 0 then n else n - 1 val unfakeconst = Option.map #fake o GrammarSpecials.dest_fakeconst_name From cf9c1e787bdce76b1a63927d150025b194c934e2 Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Fri, 24 Oct 2014 14:38:52 +0100 Subject: [PATCH 017/718] correct indent (3 spaces) of documentation in .sig files --- src/0/Net-sig.sml | 6 +- src/1/AC_Sort.sig | 44 +++++++------- src/experimental-kernel/Net.sig | 6 +- src/logging-kernel/Net.sig | 6 +- src/num/arith/src/GenPolyCanon.sig | 98 +++++++++++++++--------------- src/parse/parse_term.sig | 1 + src/parse/qbuf.sml | 2 +- 7 files changed, 82 insertions(+), 81 deletions(-) diff --git a/src/0/Net-sig.sml b/src/0/Net-sig.sml index 2e7a85d349..f4dff791f8 100644 --- a/src/0/Net-sig.sml +++ b/src/0/Net-sig.sml @@ -40,16 +40,16 @@ sig operations are not exact. In this sense, term nets are akin to hash tables. - [empty] is the empty term net. + [empty] is the empty term net. - [insert (tm, x) net] + [insert (tm, x) net] The term tm is used as a key to compute a path at which to store x in net. If the path does not already exist in net, it is created. Note that insert merely adds x to the net; if x has already been stored under tm, then it is not overwritten. - [match tm net] + [match tm net] Term nets can be used to cut down on the number of match attempts that a matching function would have to make, say when rewriting diff --git a/src/1/AC_Sort.sig b/src/1/AC_Sort.sig index 141c539de1..b2545fea79 100644 --- a/src/1/AC_Sort.sig +++ b/src/1/AC_Sort.sig @@ -11,36 +11,36 @@ end (* - [sort {assoc,comm,dest,mk,cmp,combine,preprocess}] is a conversion for - sorting terms with respect to an associative and commutative operator. - It uses a merge sort internally, so should be reasonably efficient. + [sort {assoc,comm,dest,mk,cmp,combine,preprocess}] is a conversion for + sorting terms with respect to an associative and commutative operator. + It uses a merge sort internally, so should be reasonably efficient. - The record's fields are: + The record's fields are: - assoc: associativity theorem in standard r-to-l format: - a + (b + c) = (a + b) + c - can be universally quantified + assoc: associativity theorem in standard r-to-l format: + a + (b + c) = (a + b) + c + can be universally quantified - comm: commutativity theorem (can be universally quantified) + comm: commutativity theorem (can be universally quantified) - dest: destructor function for operator + dest: destructor function for operator - mk: constructor function for operator + mk: constructor function for operator - cmp: comparison function for performing sort. Terms identified - as EQUAL will be combined by combine conversion. + cmp: comparison function for performing sort. Terms identified + as EQUAL will be combined by combine conversion. - combine: conv taking terms of the form (t1 op t2) where t1 and t2 - have compared as equal. Should always succeed (can be - ALL_CONV). + combine: conv taking terms of the form (t1 op t2) where t1 and t2 + have compared as equal. Should always succeed (can be + ALL_CONV). - preprocess: applied to all leaf terms as term is first examined. - If it fails or raises UNCHANGED (i.e., both ALL_CONV and - NO_CONV are OK here), nothing further is done. If it - succeeds, further processing is performed on the resulting - term + preprocess: applied to all leaf terms as term is first examined. + If it fails or raises UNCHANGED (i.e., both ALL_CONV and + NO_CONV are OK here), nothing further is done. If it + succeeds, further processing is performed on the resulting + term - E.g., combine can combine numeric literals; preprocess could convert - a - b into a + -b, or -x into -1 * x, or ~~p into p. + E.g., combine can combine numeric literals; preprocess could convert + a - b into a + -b, or -x into -1 * x, or ~~p into p. *) diff --git a/src/experimental-kernel/Net.sig b/src/experimental-kernel/Net.sig index 260f0c30f7..6065a7ec06 100644 --- a/src/experimental-kernel/Net.sig +++ b/src/experimental-kernel/Net.sig @@ -40,16 +40,16 @@ sig operations are not exact. In this sense, term nets are akin to hash tables. - [empty] is the empty term net. + [empty] is the empty term net. - [insert (tm, x) net] + [insert (tm, x) net] The term tm is used as a key to compute a path at which to store x in net. If the path does not already exist in net, it is created. Note that insert merely adds x to the net; if x has already been stored under tm, then it is not overwritten. - [match tm net] + [match tm net] Term nets can be used to cut down on the number of match attempts that a matching function would have to make, say when rewriting diff --git a/src/logging-kernel/Net.sig b/src/logging-kernel/Net.sig index 260f0c30f7..6065a7ec06 100644 --- a/src/logging-kernel/Net.sig +++ b/src/logging-kernel/Net.sig @@ -40,16 +40,16 @@ sig operations are not exact. In this sense, term nets are akin to hash tables. - [empty] is the empty term net. + [empty] is the empty term net. - [insert (tm, x) net] + [insert (tm, x) net] The term tm is used as a key to compute a path at which to store x in net. If the path does not already exist in net, it is created. Note that insert merely adds x to the net; if x has already been stored under tm, then it is not overwritten. - [match tm net] + [match tm net] Term nets can be used to cut down on the number of match attempts that a matching function would have to make, say when rewriting diff --git a/src/num/arith/src/GenPolyCanon.sig b/src/num/arith/src/GenPolyCanon.sig index 5ec9dd9b2d..4de9323488 100644 --- a/src/num/arith/src/GenPolyCanon.sig +++ b/src/num/arith/src/GenPolyCanon.sig @@ -30,60 +30,60 @@ end; (* - The gci type stores sufficient information about a type and operators over - it to allow normalisation of "polynomials" over that type, collecting up - coefficients etc. + The gci type stores sufficient information about a type and operators over + it to allow normalisation of "polynomials" over that type, collecting up + coefficients etc. - The required fields of the record are - dest : pulls apart a term (e.g., x + y -> (x,y)) - is_literal : returns true iff a term is a numeric literal - in L & R - modes literals are shunted to the right end of the term. - In L_Cflipped they appear on the front. - assoc_mode : how the term should be associated when built. - L & R are obvious. L_Cflipped has non-literals - left-associated, but possibly prepended by a literal to - the left. This is appropriate for multiplication, e.g., - c((xy)z) - assoc : associativity theorem (e.g., |- x + (y + z) = (x + y) + z) - symassoc : associativity theorem with equality flipped - comm : commutativity theorem (e.g., |- x + y = y + x) - l_asscomm : right-commutativity theorem (letter 'l' indicates that - terms are left-associated) - (e.g., |- (x + y) + z = (x + z) + y) - r_asscomm : left-commutativity theorem (terms are right-associated) - (e.g., |- x + (y + z) = y + (x + z)) - non_coeff : returns the "base" of a term, ignoring the coefficient. - (e.g., x -> x, 2 * x -> x, ~y -> y, 3 -> 1) - merge : takes a term of the form t1 op t2, where t1 and t2 have - equal base, and merges them into one by summing - coefficients. The result will be subjected to - post-normalisation (see below) - postnorm : conversion to normalise certain coeff-term pairs. Must - include the analogue of - 0 * x -> |- 0 * x = 0 - and might reasonably include - x ** 1 -> |- x ** 1 = x - ~1 * x -> |- ~1 * x = ~x - 3 * 1 -> |- 3 * 1 = 3 - left_id : theorem stating left-identity for the base operator - (e.g., |- 0 + x = x and |- 1 * x = x) - right_id : theorem stating right-identity for the base operator - reducer : conversion for doing ground arithmetic on coefficients + The required fields of the record are + dest : pulls apart a term (e.g., x + y -> (x,y)) + is_literal : returns true iff a term is a numeric literal - in L & R + modes literals are shunted to the right end of the term. + In L_Cflipped they appear on the front. + assoc_mode : how the term should be associated when built. + L & R are obvious. L_Cflipped has non-literals + left-associated, but possibly prepended by a literal to + the left. This is appropriate for multiplication, e.g., + c((xy)z) + assoc : associativity theorem (e.g., |- x + (y + z) = (x + y) + z) + symassoc : associativity theorem with equality flipped + comm : commutativity theorem (e.g., |- x + y = y + x) + l_asscomm : right-commutativity theorem (letter 'l' indicates that + terms are left-associated) + (e.g., |- (x + y) + z = (x + z) + y) + r_asscomm : left-commutativity theorem (terms are right-associated) + (e.g., |- x + (y + z) = y + (x + z)) + non_coeff : returns the "base" of a term, ignoring the coefficient. + (e.g., x -> x, 2 * x -> x, ~y -> y, 3 -> 1) + merge : takes a term of the form t1 op t2, where t1 and t2 have + equal base, and merges them into one by summing + coefficients. The result will be subjected to + post-normalisation (see below) + postnorm : conversion to normalise certain coeff-term pairs. Must + include the analogue of + 0 * x -> |- 0 * x = 0 + and might reasonably include + x ** 1 -> |- x ** 1 = x + ~1 * x -> |- ~1 * x = ~x + 3 * 1 -> |- 3 * 1 = 3 + left_id : theorem stating left-identity for the base operator + (e.g., |- 0 + x = x and |- 1 * x = x) + right_id : theorem stating right-identity for the base operator + reducer : conversion for doing ground arithmetic on coefficients - To handle literals, get non_coeff to return a base of 1 for them, and then - handle their merging separately in the merge function. + To handle literals, get non_coeff to return a base of 1 for them, and then + handle their merging separately in the merge function. - [update_mode m g] returns a g' that is identical to g except that - the assoc_mode field of the record has been updated to have value m. + [update_mode m g] returns a g' that is identical to g except that + the assoc_mode field of the record has been updated to have value m. - [gencanon g t] returns a theorem of the form |- t = t', where t' is a normal - form. The polynomial will be right-associated (for backwards compatibility - reasons). + [gencanon g t] returns a theorem of the form |- t = t', where t' is a normal + form. The polynomial will be right-associated (for backwards compatibility + reasons). - [derive_l_asscomm ass comm] derives an l_asscomm theorem from assoc and comm - theorems. + [derive_l_asscomm ass comm] derives an l_asscomm theorem from assoc and comm + theorems. - [derive_r_asscomm ass comm] derives an r_asscomm theorem from assoc and comm - theorems. + [derive_r_asscomm ass comm] derives an r_asscomm theorem from assoc and comm + theorems. *) diff --git a/src/parse/parse_term.sig b/src/parse/parse_term.sig index c72e75a25f..f3eee4f28e 100644 --- a/src/parse/parse_term.sig +++ b/src/parse/parse_term.sig @@ -3,6 +3,7 @@ sig type 'a PStack type 'a qbuf = 'a qbuf.qbuf type stack_terminal = term_grammar.stack_terminal + val initial_pstack : 'a PStack val is_final_pstack : 'a PStack -> bool val top_nonterminal : Term.term PStack -> Absyn.absyn diff --git a/src/parse/qbuf.sml b/src/parse/qbuf.sml index 0be47b5a36..442238ff60 100644 --- a/src/parse/qbuf.sml +++ b/src/parse/qbuf.sml @@ -10,7 +10,7 @@ struct (* qbufs are references to quadruples: field #1 : the optional lexing function for a current QUOTE part of the quotation - field #2 : the "current token" and its location (advance recalculates this) + field #2 : the "current token" and its location (advance recalculates this) field #3 : the first fragment number of the remainder frag list field #4 : the frag list that we're consuming. From c517f68317bb72fc165ccdd77f1e448f34c7190c Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Fri, 24 Oct 2014 16:05:58 +0100 Subject: [PATCH 018/718] doc: full stop at the end of SYNOPSIS sections --- help/Docfiles/Defn.tgoal.doc | 2 +- help/Docfiles/Feedback.HOL_ERR.doc | 2 +- help/Docfiles/Feedback.Raise.doc | 2 +- help/Docfiles/IndDefRules.doc | 2 +- help/Docfiles/Lib.append.doc | 2 +- help/Docfiles/Lib.cons.doc | 2 +- help/Docfiles/Lib.doc | 2 +- help/Docfiles/Parse.minus2.doc | 2 +- help/Docfiles/Term.list_mk_binder.doc | 2 +- help/Docfiles/TypeBase.doc | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/help/Docfiles/Defn.tgoal.doc b/help/Docfiles/Defn.tgoal.doc index d7c7c9d564..a9994d3249 100644 --- a/help/Docfiles/Defn.tgoal.doc +++ b/help/Docfiles/Defn.tgoal.doc @@ -3,7 +3,7 @@ \TYPE {tgoal : defn -> proofs} \SYNOPSIS -Set up a termination proof +Set up a termination proof. \KEYWORDS termination, goalstack. diff --git a/help/Docfiles/Feedback.HOL_ERR.doc b/help/Docfiles/Feedback.HOL_ERR.doc index 6c301893cf..f86ce7d688 100644 --- a/help/Docfiles/Feedback.HOL_ERR.doc +++ b/help/Docfiles/Feedback.HOL_ERR.doc @@ -6,7 +6,7 @@ HOL_ERR : {message : string, origin_function : string, \ELTYPE \SYNOPSIS -Standard HOL exception +Standard HOL exception. \KEYWORDS exception, error diff --git a/help/Docfiles/Feedback.Raise.doc b/help/Docfiles/Feedback.Raise.doc index 7b8711e1e1..a3431b89cd 100644 --- a/help/Docfiles/Feedback.Raise.doc +++ b/help/Docfiles/Feedback.Raise.doc @@ -3,7 +3,7 @@ \TYPE {Raise : exn -> 'a} \SYNOPSIS -Print an exception before re-raising it +Print an exception before re-raising it. \KEYWORDS I/O, exception diff --git a/help/Docfiles/IndDefRules.doc b/help/Docfiles/IndDefRules.doc index c574b278e6..66ef7d017c 100644 --- a/help/Docfiles/IndDefRules.doc +++ b/help/Docfiles/IndDefRules.doc @@ -3,7 +3,7 @@ \TYPE {structure IndDefRules} \SYNOPSIS -Tom Melham's inference support for inductive definitions +Tom Melham's inference support for inductive definitions. \KEYWORDS inductive diff --git a/help/Docfiles/Lib.append.doc b/help/Docfiles/Lib.append.doc index fb0f1812f3..b80ad6354b 100644 --- a/help/Docfiles/Lib.append.doc +++ b/help/Docfiles/Lib.append.doc @@ -6,7 +6,7 @@ Curry \SYNOPSIS -Curried form of list append +Curried form of list append. \DESCRIBE The function {append} is a curried form of the standard operation for diff --git a/help/Docfiles/Lib.cons.doc b/help/Docfiles/Lib.cons.doc index b0bc03c947..53290cc549 100644 --- a/help/Docfiles/Lib.cons.doc +++ b/help/Docfiles/Lib.cons.doc @@ -3,7 +3,7 @@ \TYPE {cons : 'a -> 'a list -> 'a list} \SYNOPSIS -Curried form of list cons operation +Curried form of list cons operation. \KEYWORDS Curry diff --git a/help/Docfiles/Lib.doc b/help/Docfiles/Lib.doc index ba9701f6d5..d1bd020313 100644 --- a/help/Docfiles/Lib.doc +++ b/help/Docfiles/Lib.doc @@ -3,7 +3,7 @@ \TYPE {structure Lib} \SYNOPSIS -Collection of commonly used functions +Collection of commonly used functions. \DESCRIBE {Lib} is a collection of functions that have been found useful in diff --git a/help/Docfiles/Parse.minus2.doc b/help/Docfiles/Parse.minus2.doc index 67404900bf..b9ef5aa91d 100644 --- a/help/Docfiles/Parse.minus2.doc +++ b/help/Docfiles/Parse.minus2.doc @@ -3,7 +3,7 @@ \TYPE {-- : term quotation -> 'a -> term} \SYNOPSIS -Parses a quotation into a term value +Parses a quotation into a term value. \KEYWORDS Parsing diff --git a/help/Docfiles/Term.list_mk_binder.doc b/help/Docfiles/Term.list_mk_binder.doc index 00018ebd7b..e26b5b19ff 100644 --- a/help/Docfiles/Term.list_mk_binder.doc +++ b/help/Docfiles/Term.list_mk_binder.doc @@ -3,7 +3,7 @@ \TYPE {list_mk_binder : term option -> term list * term -> term} \SYNOPSIS -Performs a sequence of variable binding operations on a term +Performs a sequence of variable binding operations on a term. \KEYWORDS variable, binding, abstraction. diff --git a/help/Docfiles/TypeBase.doc b/help/Docfiles/TypeBase.doc index 3141dfe39e..0d448ecf60 100644 --- a/help/Docfiles/TypeBase.doc +++ b/help/Docfiles/TypeBase.doc @@ -3,7 +3,7 @@ \TYPE {structure TypeBase} \SYNOPSIS -A database of facts stemming from datatype declarations +A database of facts stemming from datatype declarations. \KEYWORDS type, datatype, constructor, induction, primitive recursion. From 162412b0c047309dbc593441a9d805178fdd4f4a Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Wed, 29 Oct 2014 10:05:17 +0000 Subject: [PATCH 019/718] help: rewrite as parallel structures (firstly, secondly, thirdly) --- help/Docfiles/bossLib.srw_ss.doc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/help/Docfiles/bossLib.srw_ss.doc b/help/Docfiles/bossLib.srw_ss.doc index 2d1839fabd..dff6e01932 100644 --- a/help/Docfiles/bossLib.srw_ss.doc +++ b/help/Docfiles/bossLib.srw_ss.doc @@ -17,7 +17,7 @@ enter the {TypeBase}, and as theories are loaded. For this reason, it can't be accessed as a simple value, but is instead hidden behind a function. -The value behind {srw_ss()} can change in three ways. First, whenever +The value behind {srw_ss()} can change in three ways. Firstly, whenever a type enters the {TypeBase}, the type's associated simplification theorems (accessible directly using the function {TypeBase.simpls_of}) are all added to the {simpset}. This ensures that the "obvious" From d92257e501242c792f857e8fc5520257b98cb977 Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Fri, 31 Oct 2014 20:22:22 +0000 Subject: [PATCH 020/718] Prim_rec: whitespace cleanup in both .sig and .doc --- help/Docfiles/Prim_rec.new_recursive_definition.doc | 4 ++-- src/1/Prim_rec.sig | 13 ++++++------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/help/Docfiles/Prim_rec.new_recursive_definition.doc b/help/Docfiles/Prim_rec.new_recursive_definition.doc index dd842a9e2e..09d979cc92 100644 --- a/help/Docfiles/Prim_rec.new_recursive_definition.doc +++ b/help/Docfiles/Prim_rec.new_recursive_definition.doc @@ -41,7 +41,7 @@ variables {vsi}. If {tm} is a conjunction of clauses, as described above, then evaluating: { - new_recursive_definition{name=name, rec_axiom=th,def=tm} + new_recursive_definition{name=name, rec_axiom=th, def=tm} } automatically proves the existence of a function {fn} that satisfies the defining equations supplied as the fourth argument, and then declares a new @@ -116,7 +116,7 @@ of a function {Label} which extracts the label from a leaf node. The value of - val Label = new_recursive_definition {name = "Label", rec_axiom = th, - def = --`Label (LEAF (x:'a)) = x`--}; + def = --`Label (LEAF (x:'a)) = x`--}; > val Label = |- !x. Label (LEAF x) = x : thm } Curried functions can also be defined, and the recursion can be on diff --git a/src/1/Prim_rec.sig b/src/1/Prim_rec.sig index fa9328f9bc..13b5cb489d 100644 --- a/src/1/Prim_rec.sig +++ b/src/1/Prim_rec.sig @@ -3,12 +3,12 @@ sig include Abbrev - (*----------------------------------------------------------------------- - Returns the types defined by an axiom. Does not return type - operators that are applied to other types that are defined in - the axiom. This is a test for detecting nested recursion, where - the operator must already have an axiom elsewhere. - ------------------------------------------------------------------------*) + (*------------------------------------------------------------------------ + Returns the types defined by an axiom. Does not return type + operators that are applied to other types that are defined in + the axiom. This is a test for detecting nested recursion, where + the operator must already have an axiom elsewhere. + -------------------------------------------------------------------------*) val doms_of_tyaxiom : thm -> hol_type list @@ -20,7 +20,6 @@ sig val type_constructors : thm -> string -> term list val type_constructors_with_args : thm -> string -> term list - val new_recursive_definition : {name:string, rec_axiom:thm, def:term} -> thm (*------------------------------------------------------------------------ From b6f807a8cf7167d767506ea05c448376135b604d Mon Sep 17 00:00:00 2001 From: Piotr Trojanek Date: Fri, 7 Nov 2014 10:41:09 +0000 Subject: [PATCH 021/718] SML whitespace cleanup --- src/proofman/goalStack.sig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/proofman/goalStack.sig b/src/proofman/goalStack.sig index a62442cf56..28465da3d9 100644 --- a/src/proofman/goalStack.sig +++ b/src/proofman/goalStack.sig @@ -24,4 +24,4 @@ sig val pp_gstk : ppstream -> gstk -> unit val set_goal_pp : (ppstream -> goal -> unit) -> (ppstream -> goal -> unit) - end +end From d88eb17f25bf2800de5a5c852051092fecd95bb6 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Fri, 7 Nov 2014 11:03:21 +0000 Subject: [PATCH 022/718] TeX notation for monad syntax I thought I had done this before but apparently not. Make do and od keywords (this was already the case for parmonadsyntax, now it also works for monadsyntax). Also, fix (I hope - correct if I'm wrong) parmonadsyntax's length for the left arrow. --- src/monad/monadsyntax.sml | 2 ++ src/monad/parmonadsyntax.sml | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/monad/monadsyntax.sml b/src/monad/monadsyntax.sml index e7b21c2138..bec3689ffc 100644 --- a/src/monad/monadsyntax.sml +++ b/src/monad/monadsyntax.sml @@ -202,5 +202,7 @@ val _ = temp_overload_on ("return", mkc "UNIT") val _ = TexTokenMap.temp_TeX_notation {hol = "<-", TeX = ("\\HOLTokenLeftmap", 1)} +val _ = TexTokenMap.temp_TeX_notation {hol = "do", TeX = (" \\HOLKeyword{do}", 2)} +val _ = TexTokenMap.temp_TeX_notation {hol = "od", TeX = (" \\HOLKeyword{od}", 2)} end (* struct *) diff --git a/src/monad/parmonadsyntax.sml b/src/monad/parmonadsyntax.sml index 01845e348a..51e29bdfb0 100644 --- a/src/monad/parmonadsyntax.sml +++ b/src/monad/parmonadsyntax.sml @@ -259,7 +259,7 @@ end val _ = temp_add_user_printer ("parmonadsyntax.print_monads", ``x:'a``, print_monads) -val _ = TexTokenMap.temp_TeX_notation {hol = " <-", TeX = (" \\HOLTokenLeftmap{}", 2)} +val _ = TexTokenMap.temp_TeX_notation {hol = " <-", TeX = (" \\HOLTokenLeftmap{}", 1)} val _ = TexTokenMap.temp_TeX_notation {hol = "do", TeX = (" \\HOLKeyword{do}", 2)} val _ = TexTokenMap.temp_TeX_notation {hol = "od", TeX = (" \\HOLKeyword{od}", 2)} end (* struct *) From 0c2c180e432ce05eed11f37b53f304fc9e22a266 Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Fri, 7 Nov 2014 13:03:11 +0000 Subject: [PATCH 023/718] Update the MIPS example. The model should detect more instances of branches in the branch delay slot, which is categorised as being unpredictable. --- examples/l3-machine-code/common/Import.sml | 2 - examples/l3-machine-code/mips/model/mips.sig | 222 +- examples/l3-machine-code/mips/model/mips.sml | 3179 +++-------------- .../l3-machine-code/mips/model/mipsScript.sml | 1050 +++--- .../mips/prog/mips_progLib.sml | 75 +- .../mips/step/mips_stepLib.sml | 76 +- .../mips/step/mips_stepScript.sml | 105 +- 7 files changed, 1110 insertions(+), 3599 deletions(-) diff --git a/examples/l3-machine-code/common/Import.sml b/examples/l3-machine-code/common/Import.sml index 54db70e064..368e31e166 100644 --- a/examples/l3-machine-code/common/Import.sml +++ b/examples/l3-machine-code/common/Import.sml @@ -664,8 +664,6 @@ local then wordsSyntax.mk_word_reverse else listSyntax.mk_reverse) tm - val c_mk_comb = Lib.curry Term.mk_comb - fun enum2num ty = Lib.with_exn mk_local_const (typeName ty ^ "2num", Type.--> (ty, numLib.num)) diff --git a/examples/l3-machine-code/mips/model/mips.sig b/examples/l3-machine-code/mips/model/mips.sig index 4b25fc7513..83cffc737c 100644 --- a/examples/l3-machine-code/mips/model/mips.sig +++ b/examples/l3-machine-code/mips/model/mips.sig @@ -1,4 +1,4 @@ -(* mips - generated by L<3> - Wed Oct 15 14:19:50 2014 *) +(* mips - generated by L<3> - Wed Oct 29 16:00:41 2014 *) signature mips = sig @@ -87,40 +87,6 @@ datatype IorD = INSTRUCTION | DATA datatype LorS = LOAD | STORE -type PIC_Config_Reg = - { EN: bool, IRQ: BitsN.nbit, pic_config_reg'rst: BitsN.nbit } - -type PIC = - { base_address: BitsN.nbit, config_regs: PIC_Config_Reg Map.map, - external_intrs: BitsN.nbit, ip_bits: BitsN.nbit, - mips_ip_bits: BitsN.nbit } - -type JTAG_UART_data = - { RAVAIL: BitsN.nbit, RVALID: bool, RW_DATA: BitsN.nbit, - jtag_uart_data'rst: BitsN.nbit } - -type JTAG_UART_control = - { AC: bool, RE: bool, RI: bool, WE: bool, WI: bool, WSPACE: BitsN.nbit, - jtag_uart_control'rst: BitsN.nbit } - -type JTAG_UART = - { base_address: BitsN.nbit, control: JTAG_UART_control, - data: JTAG_UART_data, read_fifo: BitsN.nbit list, - read_threshold: Nat.nat, write_fifo: BitsN.nbit list, - write_threshold: Nat.nat } - -datatype event = - w_c0 of BitsN.nbit * BitsN.nbit - | w_gpr of BitsN.nbit * BitsN.nbit - | w_hi of BitsN.nbit - | w_lo of BitsN.nbit - | w_mem of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) - -type TLBEntry = - { ASID: BitsN.nbit, C0: BitsN.nbit, C1: BitsN.nbit, D0: bool, D1: bool, - G: bool, Mask: BitsN.nbit, PFN0: BitsN.nbit, PFN1: BitsN.nbit, - R: BitsN.nbit, V0: bool, V1: bool, VPN2: BitsN.nbit } - datatype Branch = BEQ of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | BEQL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) @@ -311,23 +277,16 @@ val LorSToString:LorS-> string end -val BranchDelay: (BitsN.nbit option) ref -val BranchTo: (BitsN.nbit option) ref +val BranchDelay: ((BitsN.nbit option) option) ref +val BranchTo: ((bool * BitsN.nbit) option) ref val CP0: CP0 ref -val JTAG_UART: JTAG_UART ref val LLbit: (bool option) ref val MEM: (BitsN.nbit Map.map) ref val PC: BitsN.nbit ref -val PIC: PIC ref -val TLB_assoc: (TLBEntry Map.map) ref -val TLB_direct: (TLBEntry Map.map) ref -val UNPREDICTABLE_HI: (unit -> unit) ref -val UNPREDICTABLE_LO: (unit -> unit) ref val exceptionSignalled: bool ref val gpr: (BitsN.nbit Map.map) ref val hi: (BitsN.nbit option) ref val lo: (BitsN.nbit option) ref -val log: (event list) ref val Index_Index_rupd: Index * BitsN.nbit -> Index val Index_P_rupd: Index * bool -> Index val Index_index'rst_rupd: Index * BitsN.nbit -> Index @@ -471,122 +430,6 @@ val CP0_Status_rupd: CP0 * StatusRegister -> CP0 val CP0_UsrLocal_rupd: CP0 * BitsN.nbit -> CP0 val CP0_Wired_rupd: CP0 * Wired -> CP0 val CP0_XContext_rupd: CP0 * XContext -> CP0 -val PIC_Config_Reg_EN_rupd: PIC_Config_Reg * bool -> PIC_Config_Reg -val PIC_Config_Reg_IRQ_rupd: PIC_Config_Reg * BitsN.nbit -> PIC_Config_Reg -val PIC_Config_Reg_pic_config_reg'rst_rupd: - PIC_Config_Reg * BitsN.nbit -> PIC_Config_Reg -val PIC_base_address_rupd: PIC * BitsN.nbit -> PIC -val PIC_config_regs_rupd: PIC * (PIC_Config_Reg Map.map) -> PIC -val PIC_external_intrs_rupd: PIC * BitsN.nbit -> PIC -val PIC_ip_bits_rupd: PIC * BitsN.nbit -> PIC -val PIC_mips_ip_bits_rupd: PIC * BitsN.nbit -> PIC -val JTAG_UART_data_RAVAIL_rupd: - JTAG_UART_data * BitsN.nbit -> JTAG_UART_data -val JTAG_UART_data_RVALID_rupd: JTAG_UART_data * bool -> JTAG_UART_data -val JTAG_UART_data_RW_DATA_rupd: - JTAG_UART_data * BitsN.nbit -> JTAG_UART_data -val JTAG_UART_data_jtag_uart_data'rst_rupd: - JTAG_UART_data * BitsN.nbit -> JTAG_UART_data -val JTAG_UART_control_AC_rupd: - JTAG_UART_control * bool -> JTAG_UART_control -val JTAG_UART_control_RE_rupd: - JTAG_UART_control * bool -> JTAG_UART_control -val JTAG_UART_control_RI_rupd: - JTAG_UART_control * bool -> JTAG_UART_control -val JTAG_UART_control_WE_rupd: - JTAG_UART_control * bool -> JTAG_UART_control -val JTAG_UART_control_WI_rupd: - JTAG_UART_control * bool -> JTAG_UART_control -val JTAG_UART_control_WSPACE_rupd: - JTAG_UART_control * BitsN.nbit -> JTAG_UART_control -val JTAG_UART_control_jtag_uart_control'rst_rupd: - JTAG_UART_control * BitsN.nbit -> JTAG_UART_control -val JTAG_UART_base_address_rupd: JTAG_UART * BitsN.nbit -> JTAG_UART -val JTAG_UART_control_rupd: JTAG_UART * JTAG_UART_control -> JTAG_UART -val JTAG_UART_data_rupd: JTAG_UART * JTAG_UART_data -> JTAG_UART -val JTAG_UART_read_fifo_rupd: JTAG_UART * (BitsN.nbit list) -> JTAG_UART -val JTAG_UART_read_threshold_rupd: JTAG_UART * Nat.nat -> JTAG_UART -val JTAG_UART_write_fifo_rupd: JTAG_UART * (BitsN.nbit list) -> JTAG_UART -val JTAG_UART_write_threshold_rupd: JTAG_UART * Nat.nat -> JTAG_UART -val TLBEntry_ASID_rupd: TLBEntry * BitsN.nbit -> TLBEntry -val TLBEntry_C0_rupd: TLBEntry * BitsN.nbit -> TLBEntry -val TLBEntry_C1_rupd: TLBEntry * BitsN.nbit -> TLBEntry -val TLBEntry_D0_rupd: TLBEntry * bool -> TLBEntry -val TLBEntry_D1_rupd: TLBEntry * bool -> TLBEntry -val TLBEntry_G_rupd: TLBEntry * bool -> TLBEntry -val TLBEntry_Mask_rupd: TLBEntry * BitsN.nbit -> TLBEntry -val TLBEntry_PFN0_rupd: TLBEntry * BitsN.nbit -> TLBEntry -val TLBEntry_PFN1_rupd: TLBEntry * BitsN.nbit -> TLBEntry -val TLBEntry_R_rupd: TLBEntry * BitsN.nbit -> TLBEntry -val TLBEntry_V0_rupd: TLBEntry * bool -> TLBEntry -val TLBEntry_V1_rupd: TLBEntry * bool -> TLBEntry -val TLBEntry_VPN2_rupd: TLBEntry * BitsN.nbit -> TLBEntry -val boolify'64: - BitsN.nbit -> - bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - (bool * - bool)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) val boolify'32: BitsN.nbit -> bool * @@ -703,38 +546,6 @@ val KernelMode: unit -> bool val BigEndianMem: unit -> bool val ReverseEndian: unit -> BitsN.nbit val BigEndianCPU: unit -> BitsN.nbit -val rec'PIC_Config_Reg: BitsN.nbit -> PIC_Config_Reg -val reg'PIC_Config_Reg: PIC_Config_Reg -> BitsN.nbit -val write'rec'PIC_Config_Reg: (BitsN.nbit * PIC_Config_Reg) -> BitsN.nbit -val write'reg'PIC_Config_Reg: - (PIC_Config_Reg * BitsN.nbit) -> PIC_Config_Reg -val PIC_update: unit -> unit -val PIC_initialise: Nat.nat -> unit -val PIC_load: BitsN.nbit -> BitsN.nbit -val PIC_store: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit -val rec'JTAG_UART_data: BitsN.nbit -> JTAG_UART_data -val reg'JTAG_UART_data: JTAG_UART_data -> BitsN.nbit -val write'rec'JTAG_UART_data: (BitsN.nbit * JTAG_UART_data) -> BitsN.nbit -val write'reg'JTAG_UART_data: - (JTAG_UART_data * BitsN.nbit) -> JTAG_UART_data -val rec'JTAG_UART_control: BitsN.nbit -> JTAG_UART_control -val reg'JTAG_UART_control: JTAG_UART_control -> BitsN.nbit -val write'rec'JTAG_UART_control: - (BitsN.nbit * JTAG_UART_control) -> BitsN.nbit -val write'reg'JTAG_UART_control: - (JTAG_UART_control * BitsN.nbit) -> JTAG_UART_control -val JTAG_UART_update_interrupt_bit: unit -> unit -val JTAG_UART_load: unit -> unit -val JTAG_UART_input: (BitsN.nbit list) -> unit -val JTAG_UART_store: (BitsN.nbit * BitsN.nbit) -> unit -val JTAG_UART_output: unit -> (BitsN.nbit list) -val JTAG_UART_initialise: Nat.nat -> unit -val PSIZE: Nat.nat -val mark: event -> unit -val unmark: unit -> unit -val flip_endian_word: BitsN.nbit -> BitsN.nbit -val flip_endian_dword: BitsN.nbit -> BitsN.nbit -val TLBEntries: Nat.nat val GPR: BitsN.nbit -> BitsN.nbit val write'GPR: (BitsN.nbit * BitsN.nbit) -> unit val HI: unit -> BitsN.nbit @@ -744,35 +555,18 @@ val write'LO: BitsN.nbit -> unit val CPR: (Nat.nat * (BitsN.nbit * BitsN.nbit)) -> BitsN.nbit val write'CPR: (BitsN.nbit * (Nat.nat * (BitsN.nbit * BitsN.nbit))) -> unit -val LookupTLB: (BitsN.nbit * BitsN.nbit) -> ((BitsN.nbit * TLBEntry) list) -val ModifyTLB: TLBEntry -> TLBEntry -val SignalTLBException: - (ExceptionType * (BitsN.nbit * BitsN.nbit)) -> (BitsN.nbit * BitsN.nbit) -val CheckSegment: - BitsN.nbit -> (((BitsN.nbit * BitsN.nbit) option) * bool) +val PSIZE: Nat.nat val AddressTranslation: (BitsN.nbit * (IorD * LorS)) -> (BitsN.nbit * BitsN.nbit) val LoadMemory: (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * IorD)))) -> BitsN.nbit -val loadWord32: BitsN.nbit -> BitsN.nbit val StoreMemory: (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * IorD))))) -> unit -val dfn'TLBP: unit -> unit -val dfn'TLBR: unit -> unit -val dfn'TLBWI: unit -> unit -val dfn'TLBWR: unit -> unit -val dfn'CACHE: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit -val dfn'RDHWR: (BitsN.nbit * BitsN.nbit) -> unit val Fetch: unit -> (BitsN.nbit option) -val initTLB: unit -> TLBEntry -val addTLB: (BitsN.nbit * BitsN.nbit) -> unit -val initMips: (Nat.nat * Nat.nat) -> unit -val done: unit -> bool val NotWordValue: BitsN.nbit -> bool -val CheckBranch: unit -> unit val dfn'ADDI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit val dfn'ADDIU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit val dfn'DADDI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit @@ -886,6 +680,8 @@ val dfn'J: BitsN.nbit -> unit val dfn'JAL: BitsN.nbit -> unit val dfn'JR: BitsN.nbit -> unit val dfn'JALR: (BitsN.nbit * BitsN.nbit) -> unit +val ConditionalBranch: (bool * BitsN.nbit) -> unit +val ConditionalBranchLikely: (bool * BitsN.nbit) -> unit val dfn'BEQ: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit val dfn'BNE: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit val dfn'BLEZ: (BitsN.nbit * BitsN.nbit) -> unit @@ -903,6 +699,12 @@ val dfn'BGEZL: (BitsN.nbit * BitsN.nbit) -> unit val dfn'BLTZALL: (BitsN.nbit * BitsN.nbit) -> unit val dfn'BGEZALL: (BitsN.nbit * BitsN.nbit) -> unit val dfn'WAIT: unit +val dfn'TLBP: unit -> unit +val dfn'TLBR: unit -> unit +val dfn'TLBWI: unit -> unit +val dfn'TLBWR: unit -> unit +val dfn'CACHE: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'RDHWR: (BitsN.nbit * BitsN.nbit) -> unit val dfn'ReservedInstruction: unit -> unit val dfn'Unpredictable: unit -> unit val Run: instruction -> unit diff --git a/examples/l3-machine-code/mips/model/mips.sml b/examples/l3-machine-code/mips/model/mips.sml index 62b7434db3..2f641f8a45 100644 --- a/examples/l3-machine-code/mips/model/mips.sml +++ b/examples/l3-machine-code/mips/model/mips.sml @@ -1,4 +1,4 @@ -(* mips - generated by L<3> - Wed Oct 15 14:19:50 2014 *) +(* mips - generated by L<3> - Wed Oct 29 16:00:41 2014 *) structure mips :> mips = struct @@ -87,40 +87,6 @@ datatype IorD = INSTRUCTION | DATA datatype LorS = LOAD | STORE -type PIC_Config_Reg = - { EN: bool, IRQ: BitsN.nbit, pic_config_reg'rst: BitsN.nbit } - -type PIC = - { base_address: BitsN.nbit, config_regs: PIC_Config_Reg Map.map, - external_intrs: BitsN.nbit, ip_bits: BitsN.nbit, - mips_ip_bits: BitsN.nbit } - -type JTAG_UART_data = - { RAVAIL: BitsN.nbit, RVALID: bool, RW_DATA: BitsN.nbit, - jtag_uart_data'rst: BitsN.nbit } - -type JTAG_UART_control = - { AC: bool, RE: bool, RI: bool, WE: bool, WI: bool, WSPACE: BitsN.nbit, - jtag_uart_control'rst: BitsN.nbit } - -type JTAG_UART = - { base_address: BitsN.nbit, control: JTAG_UART_control, - data: JTAG_UART_data, read_fifo: BitsN.nbit list, - read_threshold: Nat.nat, write_fifo: BitsN.nbit list, - write_threshold: Nat.nat } - -datatype event = - w_c0 of BitsN.nbit * BitsN.nbit - | w_gpr of BitsN.nbit * BitsN.nbit - | w_hi of BitsN.nbit - | w_lo of BitsN.nbit - | w_mem of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) - -type TLBEntry = - { ASID: BitsN.nbit, C0: BitsN.nbit, C1: BitsN.nbit, D0: bool, D1: bool, - G: bool, Mask: BitsN.nbit, PFN0: BitsN.nbit, PFN1: BitsN.nbit, - R: BitsN.nbit, V0: bool, V1: bool, VPN2: BitsN.nbit } - datatype Branch = BEQ of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | BEQL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) @@ -1216,224 +1182,6 @@ fun CP0_XContext_rupd ({BadVAddr, Cause, Compare, Config, Config1, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = x'} : CP0 -fun PIC_Config_Reg_EN_rupd ({EN, IRQ, pic_config_reg'rst} - : PIC_Config_Reg, x') = - {EN = x', IRQ = IRQ, pic_config_reg'rst = pic_config_reg'rst} - : PIC_Config_Reg - -fun PIC_Config_Reg_IRQ_rupd ({EN, IRQ, pic_config_reg'rst} - : PIC_Config_Reg, x') = - {EN = EN, IRQ = x', pic_config_reg'rst = pic_config_reg'rst} - : PIC_Config_Reg - -fun PIC_Config_Reg_pic_config_reg'rst_rupd ({EN, IRQ, pic_config_reg'rst} - : PIC_Config_Reg, x') = {EN = EN, IRQ = IRQ, pic_config_reg'rst = x'} - : PIC_Config_Reg - -fun PIC_base_address_rupd ({base_address, config_regs, external_intrs, - ip_bits, mips_ip_bits}: PIC, x') = - {base_address = x', config_regs = config_regs, - external_intrs = external_intrs, ip_bits = ip_bits, - mips_ip_bits = mips_ip_bits}: PIC - -fun PIC_config_regs_rupd ({base_address, config_regs, external_intrs, - ip_bits, mips_ip_bits}: PIC, x') = - {base_address = base_address, config_regs = x', - external_intrs = external_intrs, ip_bits = ip_bits, - mips_ip_bits = mips_ip_bits}: PIC - -fun PIC_external_intrs_rupd ({base_address, config_regs, external_intrs, - ip_bits, mips_ip_bits}: PIC, x') = - {base_address = base_address, config_regs = config_regs, - external_intrs = x', ip_bits = ip_bits, mips_ip_bits = mips_ip_bits} - : PIC - -fun PIC_ip_bits_rupd ({base_address, config_regs, external_intrs, ip_bits, - mips_ip_bits}: PIC, x') = - {base_address = base_address, config_regs = config_regs, - external_intrs = external_intrs, ip_bits = x', - mips_ip_bits = mips_ip_bits}: PIC - -fun PIC_mips_ip_bits_rupd ({base_address, config_regs, external_intrs, - ip_bits, mips_ip_bits}: PIC, x') = - {base_address = base_address, config_regs = config_regs, - external_intrs = external_intrs, ip_bits = ip_bits, mips_ip_bits = x'} - : PIC - -fun JTAG_UART_data_RAVAIL_rupd ({RAVAIL, RVALID, RW_DATA, - jtag_uart_data'rst}: JTAG_UART_data, x') = - {RAVAIL = x', RVALID = RVALID, RW_DATA = RW_DATA, - jtag_uart_data'rst = jtag_uart_data'rst}: JTAG_UART_data - -fun JTAG_UART_data_RVALID_rupd ({RAVAIL, RVALID, RW_DATA, - jtag_uart_data'rst}: JTAG_UART_data, x') = - {RAVAIL = RAVAIL, RVALID = x', RW_DATA = RW_DATA, - jtag_uart_data'rst = jtag_uart_data'rst}: JTAG_UART_data - -fun JTAG_UART_data_RW_DATA_rupd ({RAVAIL, RVALID, RW_DATA, - jtag_uart_data'rst}: JTAG_UART_data, x') = - {RAVAIL = RAVAIL, RVALID = RVALID, RW_DATA = x', - jtag_uart_data'rst = jtag_uart_data'rst}: JTAG_UART_data - -fun JTAG_UART_data_jtag_uart_data'rst_rupd ({RAVAIL, RVALID, RW_DATA, - jtag_uart_data'rst}: JTAG_UART_data, x') = - {RAVAIL = RAVAIL, RVALID = RVALID, RW_DATA = RW_DATA, - jtag_uart_data'rst = x'}: JTAG_UART_data - -fun JTAG_UART_control_AC_rupd ({AC, RE, RI, WE, WI, WSPACE, - jtag_uart_control'rst}: JTAG_UART_control, x') = - {AC = x', RE = RE, RI = RI, WE = WE, WI = WI, WSPACE = WSPACE, - jtag_uart_control'rst = jtag_uart_control'rst}: JTAG_UART_control - -fun JTAG_UART_control_RE_rupd ({AC, RE, RI, WE, WI, WSPACE, - jtag_uart_control'rst}: JTAG_UART_control, x') = - {AC = AC, RE = x', RI = RI, WE = WE, WI = WI, WSPACE = WSPACE, - jtag_uart_control'rst = jtag_uart_control'rst}: JTAG_UART_control - -fun JTAG_UART_control_RI_rupd ({AC, RE, RI, WE, WI, WSPACE, - jtag_uart_control'rst}: JTAG_UART_control, x') = - {AC = AC, RE = RE, RI = x', WE = WE, WI = WI, WSPACE = WSPACE, - jtag_uart_control'rst = jtag_uart_control'rst}: JTAG_UART_control - -fun JTAG_UART_control_WE_rupd ({AC, RE, RI, WE, WI, WSPACE, - jtag_uart_control'rst}: JTAG_UART_control, x') = - {AC = AC, RE = RE, RI = RI, WE = x', WI = WI, WSPACE = WSPACE, - jtag_uart_control'rst = jtag_uart_control'rst}: JTAG_UART_control - -fun JTAG_UART_control_WI_rupd ({AC, RE, RI, WE, WI, WSPACE, - jtag_uart_control'rst}: JTAG_UART_control, x') = - {AC = AC, RE = RE, RI = RI, WE = WE, WI = x', WSPACE = WSPACE, - jtag_uart_control'rst = jtag_uart_control'rst}: JTAG_UART_control - -fun JTAG_UART_control_WSPACE_rupd ({AC, RE, RI, WE, WI, WSPACE, - jtag_uart_control'rst}: JTAG_UART_control, x') = - {AC = AC, RE = RE, RI = RI, WE = WE, WI = WI, WSPACE = x', - jtag_uart_control'rst = jtag_uart_control'rst}: JTAG_UART_control - -fun JTAG_UART_control_jtag_uart_control'rst_rupd ({AC, RE, RI, WE, WI, - WSPACE, jtag_uart_control'rst}: JTAG_UART_control, x') = - {AC = AC, RE = RE, RI = RI, WE = WE, WI = WI, WSPACE = WSPACE, - jtag_uart_control'rst = x'}: JTAG_UART_control - -fun JTAG_UART_base_address_rupd ({base_address, control, data, read_fifo, - read_threshold, write_fifo, write_threshold}: JTAG_UART, x') = - {base_address = x', control = control, data = data, - read_fifo = read_fifo, read_threshold = read_threshold, - write_fifo = write_fifo, write_threshold = write_threshold}: JTAG_UART - -fun JTAG_UART_control_rupd ({base_address, control, data, read_fifo, - read_threshold, write_fifo, write_threshold}: JTAG_UART, x') = - {base_address = base_address, control = x', data = data, - read_fifo = read_fifo, read_threshold = read_threshold, - write_fifo = write_fifo, write_threshold = write_threshold}: JTAG_UART - -fun JTAG_UART_data_rupd ({base_address, control, data, read_fifo, - read_threshold, write_fifo, write_threshold}: JTAG_UART, x') = - {base_address = base_address, control = control, data = x', - read_fifo = read_fifo, read_threshold = read_threshold, - write_fifo = write_fifo, write_threshold = write_threshold}: JTAG_UART - -fun JTAG_UART_read_fifo_rupd ({base_address, control, data, read_fifo, - read_threshold, write_fifo, write_threshold}: JTAG_UART, x') = - {base_address = base_address, control = control, data = data, - read_fifo = x', read_threshold = read_threshold, - write_fifo = write_fifo, write_threshold = write_threshold}: JTAG_UART - -fun JTAG_UART_read_threshold_rupd ({base_address, control, data, - read_fifo, read_threshold, write_fifo, write_threshold} - : JTAG_UART, x') = - {base_address = base_address, control = control, data = data, - read_fifo = read_fifo, read_threshold = x', write_fifo = write_fifo, - write_threshold = write_threshold}: JTAG_UART - -fun JTAG_UART_write_fifo_rupd ({base_address, control, data, read_fifo, - read_threshold, write_fifo, write_threshold}: JTAG_UART, x') = - {base_address = base_address, control = control, data = data, - read_fifo = read_fifo, read_threshold = read_threshold, - write_fifo = x', write_threshold = write_threshold}: JTAG_UART - -fun JTAG_UART_write_threshold_rupd ({base_address, control, data, - read_fifo, read_threshold, write_fifo, write_threshold} - : JTAG_UART, x') = - {base_address = base_address, control = control, data = data, - read_fifo = read_fifo, read_threshold = read_threshold, - write_fifo = write_fifo, write_threshold = x'}: JTAG_UART - -fun TLBEntry_ASID_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = x', C0 = C0, C1 = C1, D0 = D0, D1 = D1, G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = V0, V1 = V1, VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_C0_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = x', C1 = C1, D0 = D0, D1 = D1, G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = V0, V1 = V1, VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_C1_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = x', D0 = D0, D1 = D1, G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = V0, V1 = V1, VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_D0_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = x', D1 = D1, G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = V0, V1 = V1, VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_D1_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = D0, D1 = x', G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = V0, V1 = V1, VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_G_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = D0, D1 = D1, G = x', Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = V0, V1 = V1, VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_Mask_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = D0, D1 = D1, G = G, Mask = x', - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = V0, V1 = V1, VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_PFN0_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = D0, D1 = D1, G = G, Mask = Mask, - PFN0 = x', PFN1 = PFN1, R = R, V0 = V0, V1 = V1, VPN2 = VPN2}: TLBEntry - -fun TLBEntry_PFN1_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = D0, D1 = D1, G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = x', R = R, V0 = V0, V1 = V1, VPN2 = VPN2}: TLBEntry - -fun TLBEntry_R_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = D0, D1 = D1, G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = x', V0 = V0, V1 = V1, VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_V0_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = D0, D1 = D1, G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = x', V1 = V1, VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_V1_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = D0, D1 = D1, G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = V0, V1 = x', VPN2 = VPN2} - : TLBEntry - -fun TLBEntry_VPN2_rupd ({ASID, C0, C1, D0, D1, G, Mask, PFN0, PFN1, R, V0, - V1, VPN2}: TLBEntry, x') = - {ASID = ASID, C0 = C0, C1 = C1, D0 = D0, D1 = D1, G = G, Mask = Mask, - PFN0 = PFN0, PFN1 = PFN1, R = R, V0 = V0, V1 = V1, VPN2 = x'}: TLBEntry - (* ------------------------------------------------------------------------- Exceptions ------------------------------------------------------------------------- *) @@ -1444,9 +1192,9 @@ exception UNPREDICTABLE of string Global variables (state) ------------------------------------------------------------------------- *) -val BranchDelay = ref (NONE): (BitsN.nbit option) ref +val BranchDelay = ref (NONE): ((BitsN.nbit option) option) ref -val BranchTo = ref (NONE): (BitsN.nbit option) ref +val BranchTo = ref (NONE): ((bool * BitsN.nbit) option) ref val CP0 = ref ({BadVAddr = BitsN.B(0x0,64), @@ -1506,56 +1254,13 @@ val CP0 = ref {BadVPN2 = BitsN.B(0x0,27), PTEBase = BitsN.B(0x0,31), R = BitsN.B(0x0,2), xcontext'rst = BitsN.B(0x0,4)}}): CP0 ref -val JTAG_UART = ref - ({base_address = BitsN.B(0x0,37), - control = - {AC = false, RE = false, RI = false, WE = false, WI = false, - WSPACE = BitsN.B(0x0,16), jtag_uart_control'rst = BitsN.B(0x0,11)}, - data = - {RAVAIL = BitsN.B(0x0,16), RVALID = false, RW_DATA = BitsN.B(0x0,8), - jtag_uart_data'rst = BitsN.B(0x0,7)}, read_fifo = [], - read_threshold = 0, write_fifo = [], write_threshold = 0}) - : JTAG_UART ref - val LLbit = ref (NONE): (bool option) ref -val MEM = ref (Map.mkMap(SOME 137438953472,BitsN.B(0x0,64))) +val MEM = ref (Map.mkMap(SOME 18446744073709551616,BitsN.B(0x0,8))) : (BitsN.nbit Map.map) ref val PC = ref (BitsN.B(0x0,64)): BitsN.nbit ref -val PIC = ref - ({base_address = BitsN.B(0x0,37), - config_regs = - Map.mkMap - (SOME 128, - {EN = false, IRQ = BitsN.B(0x0,3), - pic_config_reg'rst = BitsN.B(0x0,60)}), - external_intrs = BitsN.B(0x0,64), ip_bits = BitsN.B(0x0,128), - mips_ip_bits = BitsN.B(0x0,6)}): PIC ref - -val TLB_assoc = ref - (Map.mkMap - (SOME 16, - {ASID = BitsN.B(0x0,8), C0 = BitsN.B(0x0,3), C1 = BitsN.B(0x0,3), - D0 = false, D1 = false, G = false, Mask = BitsN.B(0x0,12), - PFN0 = BitsN.B(0x0,28), PFN1 = BitsN.B(0x0,28), R = BitsN.B(0x0,2), - V0 = false, V1 = false, VPN2 = BitsN.B(0x0,27)})) - : (TLBEntry Map.map) ref - -val TLB_direct = ref - (Map.mkMap - (SOME 128, - {ASID = BitsN.B(0x0,8), C0 = BitsN.B(0x0,3), C1 = BitsN.B(0x0,3), - D0 = false, D1 = false, G = false, Mask = BitsN.B(0x0,12), - PFN0 = BitsN.B(0x0,28), PFN1 = BitsN.B(0x0,28), R = BitsN.B(0x0,2), - V0 = false, V1 = false, VPN2 = BitsN.B(0x0,27)})) - : (TLBEntry Map.map) ref - -val UNPREDICTABLE_HI = ref (L3.K ()): (unit -> unit) ref - -val UNPREDICTABLE_LO = ref (L3.K ()): (unit -> unit) ref - val exceptionSignalled = ref (false): bool ref val gpr = ref (Map.mkMap(SOME 32,BitsN.B(0x0,64))) @@ -1565,87 +1270,10 @@ val hi = ref (NONE): (BitsN.nbit option) ref val lo = ref (NONE): (BitsN.nbit option) ref -val log = ref ([]): (event list) ref - (* ------------------------------------------------------------------------- Main specification ------------------------------------------------------------------------- *) -local - fun tuple'64 [t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16, - t17,t18,t19,t20,t21,t22,t23,t24,t25,t26,t27,t28,t29,t30, - t31,t32,t33,t34,t35,t36,t37,t38,t39,t40,t41,t42,t43,t44, - t45,t46,t47,t48,t49,t50,t51,t52,t53,t54,t55,t56,t57,t58, - t59,t60,t61,t62,t63] = - (t0, - (t1, - (t2, - (t3, - (t4, - (t5, - (t6, - (t7, - (t8, - (t9, - (t10, - (t11, - (t12, - (t13, - (t14, - (t15, - (t16, - (t17, - (t18, - (t19, - (t20, - (t21, - (t22, - (t23, - (t24, - (t25, - (t26, - (t27, - (t28, - (t29, - (t30, - (t31, - (t32, - (t33, - (t34, - (t35, - (t36, - (t37, - (t38, - (t39, - (t40, - (t41, - (t42, - (t43, - (t44, - (t45, - (t46, - (t47, - (t48, - (t49, - (t50, - (t51, - (t52, - (t53, - (t54, - (t55, - (t56, - (t57, - (t58, - (t59, - (t60, - (t61, - (t62, - t63))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - | tuple'64 (_: bool list) = raise Fail "tuple'64" -in - val boolify'64 = tuple'64 o BitsN.toList -end - local fun tuple'32 [t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16, t17,t18,t19,t20,t21,t22,t23,t24,t25,t26,t27,t28,t29,t30, @@ -3214,26 +2842,26 @@ fun ExceptionCode ExceptionType = fun SignalException ExceptionType = ( if not((#EXL)((#Status) (!CP0))) - then if Option.isSome (!BranchDelay) - then ( CP0 := - (CP0_EPC_rupd((!CP0),BitsN.-((!PC),BitsN.B(0x4,64)))) - ; let - val x0 = (#Cause) (!CP0) - in - CP0 := - (CP0_Cause_rupd - ((!CP0),CauseRegister_BD_rupd(x0,true))) - end - ) - else ( CP0 := (CP0_EPC_rupd((!CP0),(!PC))) - ; let - val x0 = (#Cause) (!CP0) - in - CP0 := - (CP0_Cause_rupd - ((!CP0),CauseRegister_BD_rupd(x0,false))) - end - ) + then case (!BranchDelay) of + Option.SOME(Option.SOME _) => + ( CP0 := + (CP0_EPC_rupd((!CP0),BitsN.-((!PC),BitsN.B(0x4,64)))) + ; let + val x0 = (#Cause) (!CP0) + in + CP0 := + (CP0_Cause_rupd((!CP0),CauseRegister_BD_rupd(x0,true))) + end + ) + | _ => + ( CP0 := (CP0_EPC_rupd((!CP0),(!PC))) + ; let + val x0 = (#Cause) (!CP0) + in + CP0 := + (CP0_Cause_rupd((!CP0),CauseRegister_BD_rupd(x0,false))) + end + ) else () ; let val vectorOffset = @@ -3248,2181 +2876,352 @@ fun SignalException ExceptionType = val x0 = (#Status) (!CP0) in CP0 := - (CP0_Status_rupd((!CP0),StatusRegister_EXL_rupd(x0,true))) - end - ; let - val vectorBase = - if (#BEV)((#Status) (!CP0)) - then BitsN.B(0xFFFFFFFFBFC00200,64) - else BitsN.B(0xFFFFFFFF80000000,64) - in - ( BranchDelay := NONE - ; BranchTo := NONE - ; PC := - (BitsN.@@ - (BitsN.bits(vectorBase,63,30), - BitsN.+(BitsN.bits(vectorBase,29,0),vectorOffset))) - ; exceptionSignalled := true - ) - end - ) - end - ); - -val BYTE = BitsN.B(0x0,3) - -val HALFWORD = BitsN.B(0x1,3) - -val WORD = BitsN.B(0x3,3) - -val DOUBLEWORD = BitsN.B(0x7,3) - -fun UserMode () = - (((#KSU)((#Status) (!CP0))) = (BitsN.B(0x2,2))) andalso - (not(((#EXL)((#Status) (!CP0))) orelse ((#ERL)((#Status) (!CP0))))); - -fun SupervisorMode () = - (((#KSU)((#Status) (!CP0))) = (BitsN.B(0x1,2))) andalso - (not(((#EXL)((#Status) (!CP0))) orelse ((#ERL)((#Status) (!CP0))))); - -fun KernelMode () = - ((((#KSU)((#Status) (!CP0))) = (BitsN.B(0x0,2))) orelse - ((#EXL)((#Status) (!CP0)))) orelse ((#ERL)((#Status) (!CP0))); - -fun BigEndianMem () = (#BE)((#Config) (!CP0)); - -fun ReverseEndian () = - BitsN.fromBit(((#RE)((#Status) (!CP0))) andalso (UserMode ())); - -fun BigEndianCPU () = - BitsN.??(BitsN.fromBit(BigEndianMem ()),ReverseEndian ()); - -fun rec'PIC_Config_Reg x = - {EN = BitsN.bit(x,31), IRQ = BitsN.bits(x,2,0), - pic_config_reg'rst = BitsN.@@(BitsN.bits(x,30,3),BitsN.bits(x,63,32))}; - -fun reg'PIC_Config_Reg x = - case x of - {EN = EN, IRQ = IRQ, pic_config_reg'rst = pic_config_reg'rst} => - BitsN.modify - (fn (i,_) => - if i = 63 - then BitsN.bit(pic_config_reg'rst,31) - else if i = 62 - then BitsN.bit(pic_config_reg'rst,30) - else if i = 61 - then BitsN.bit(pic_config_reg'rst,29) - else if i = 60 - then BitsN.bit(pic_config_reg'rst,28) - else if i = 59 - then BitsN.bit(pic_config_reg'rst,27) - else if i = 58 - then BitsN.bit(pic_config_reg'rst,26) - else if i = 57 - then BitsN.bit(pic_config_reg'rst,25) - else if i = 56 - then BitsN.bit(pic_config_reg'rst,24) - else if i = 55 - then BitsN.bit(pic_config_reg'rst,23) - else if i = 54 - then BitsN.bit(pic_config_reg'rst,22) - else if i = 53 - then BitsN.bit(pic_config_reg'rst,21) - else if i = 52 - then BitsN.bit(pic_config_reg'rst,20) - else if i = 51 - then BitsN.bit(pic_config_reg'rst,19) - else if i = 50 - then BitsN.bit(pic_config_reg'rst,18) - else if i = 49 - then BitsN.bit(pic_config_reg'rst,17) - else if i = 48 - then BitsN.bit(pic_config_reg'rst,16) - else if i = 47 - then BitsN.bit(pic_config_reg'rst,15) - else if i = 46 - then BitsN.bit(pic_config_reg'rst,14) - else if i = 45 - then BitsN.bit(pic_config_reg'rst,13) - else if i = 44 - then BitsN.bit(pic_config_reg'rst,12) - else if i = 43 - then BitsN.bit(pic_config_reg'rst,11) - else if i = 42 - then BitsN.bit(pic_config_reg'rst,10) - else if i = 41 - then BitsN.bit(pic_config_reg'rst,9) - else if i = 40 - then BitsN.bit(pic_config_reg'rst,8) - else if i = 39 - then BitsN.bit(pic_config_reg'rst,7) - else if i = 38 - then BitsN.bit(pic_config_reg'rst,6) - else if i = 37 - then BitsN.bit(pic_config_reg'rst,5) - else if i = 36 - then BitsN.bit(pic_config_reg'rst,4) - else if i = 35 - then BitsN.bit(pic_config_reg'rst,3) - else if i = 34 - then BitsN.bit(pic_config_reg'rst,2) - else if i = 33 - then BitsN.bit(pic_config_reg'rst,1) - else if i = 32 - then BitsN.bit(pic_config_reg'rst,0) - else if i = 31 - then EN - else if i = 30 - then BitsN.bit(pic_config_reg'rst,59) - else if i = 29 - then BitsN.bit(pic_config_reg'rst,58) - else if i = 28 - then BitsN.bit(pic_config_reg'rst,57) - else if i = 27 - then BitsN.bit(pic_config_reg'rst,56) - else if i = 26 - then BitsN.bit(pic_config_reg'rst,55) - else if i = 25 - then BitsN.bit(pic_config_reg'rst,54) - else if i = 24 - then BitsN.bit(pic_config_reg'rst,53) - else if i = 23 - then BitsN.bit(pic_config_reg'rst,52) - else if i = 22 - then BitsN.bit(pic_config_reg'rst,51) - else if i = 21 - then BitsN.bit(pic_config_reg'rst,50) - else if i = 20 - then BitsN.bit(pic_config_reg'rst,49) - else if i = 19 - then BitsN.bit(pic_config_reg'rst,48) - else if i = 18 - then BitsN.bit(pic_config_reg'rst,47) - else if i = 17 - then BitsN.bit(pic_config_reg'rst,46) - else if i = 16 - then BitsN.bit(pic_config_reg'rst,45) - else if i = 15 - then BitsN.bit(pic_config_reg'rst,44) - else if i = 14 - then BitsN.bit(pic_config_reg'rst,43) - else if i = 13 - then BitsN.bit(pic_config_reg'rst,42) - else if i = 12 - then BitsN.bit(pic_config_reg'rst,41) - else if i = 11 - then BitsN.bit(pic_config_reg'rst,40) - else if i = 10 - then BitsN.bit(pic_config_reg'rst,39) - else if i = 9 - then BitsN.bit(pic_config_reg'rst,38) - else if i = 8 - then BitsN.bit(pic_config_reg'rst,37) - else if i = 7 - then BitsN.bit(pic_config_reg'rst,36) - else if i = 6 - then BitsN.bit(pic_config_reg'rst,35) - else if i = 5 - then BitsN.bit(pic_config_reg'rst,34) - else if i = 4 - then BitsN.bit(pic_config_reg'rst,33) - else if i = 3 - then BitsN.bit(pic_config_reg'rst,32) - else if i = 2 - then BitsN.bit(IRQ,2) - else if i = 1 then BitsN.bit(IRQ,1) else BitsN.bit(IRQ,0), - BitsN.B(0x0,64)); - -fun write'rec'PIC_Config_Reg (_,x) = reg'PIC_Config_Reg x; - -fun write'reg'PIC_Config_Reg (_,x) = rec'PIC_Config_Reg x; - -fun PIC_update () = - let - val ext = BitsN.zeroExtend 128 ((#external_intrs) (!PIC)) - in - let - val ip = ref (BitsN.B(0x0,8)) - in - ( ip := (BitsN.B(0x0,8)) - ; if (not(((#ip_bits) (!PIC)) = (BitsN.B(0x0,128)))) orelse - (not(ext = (BitsN.B(0x0,128)))) - then L3.for - (0,127, - fn i => - if (BitsN.bit((#ip_bits) (!PIC),i)) orelse - (BitsN.bit(ext,i)) - then let - val reg = - Map.lookup - ((#config_regs) (!PIC), - BitsN.toNat(BitsN.fromNat(i,7))) - val i = BitsN.toNat((#IRQ) reg) - in - ip := - (BitsN.bitFieldInsert - ((!ip), - BitsN.fromBit - ((BitsN.bit - ((!ip),BitsN.toNat((#IRQ) reg))) orelse - ((#EN) reg)),i,i)) - end - else ()) - else () - ; PIC := (PIC_mips_ip_bits_rupd((!PIC),BitsN.bits((!ip),5,0))) - ) - end - end; - -fun PIC_initialise pic = - ( PIC := - (PIC_base_address_rupd - ((!PIC), - BitsN.fromNat(BitsN.toNat(BitsN.>>+(BitsN.fromNat(pic,40),3)),37))) - ; L3.for - (0,127, - fn i => - let - val f = Map.copy((#config_regs) (!PIC)) - val x0 = BitsN.fromNat(i,7) - val x1 = Map.lookup(f,BitsN.toNat x0) - in - PIC := - (PIC_config_regs_rupd - ((!PIC), - Map.update - (f,BitsN.toNat x0, - write'reg'PIC_Config_Reg(x1,BitsN.B(0x0,64))))) - end) - ; L3.for - (0,4, - fn i => - ( let - val f = Map.copy((#config_regs) (!PIC)) - val x0 = BitsN.fromNat(i,7) - val x1 = Map.lookup(f,BitsN.toNat x0) - in - PIC := - (PIC_config_regs_rupd - ((!PIC), - Map.update - (f,BitsN.toNat x0,PIC_Config_Reg_EN_rupd(x1,true)))) - end - ; let - val f = Map.copy((#config_regs) (!PIC)) - val x0 = BitsN.fromNat(i,7) - val x1 = Map.lookup(f,BitsN.toNat x0) - in - PIC := - (PIC_config_regs_rupd - ((!PIC), - Map.update - (f,BitsN.toNat x0, - PIC_Config_Reg_IRQ_rupd(x1,BitsN.fromNat(i,3))))) - end - )) - ; PIC := (PIC_ip_bits_rupd((!PIC),BitsN.B(0x0,128))) - ; PIC := (PIC_external_intrs_rupd((!PIC),BitsN.B(0x0,64))) - ; PIC_update () - ); - -fun PIC_load addr = - let - val offset = BitsN.-(addr,(#base_address) (!PIC)) - in - let - val ret = ref (BitsN.B(0x0,64)) - in - ( if BitsN.<(offset,BitsN.B(0x80,37)) - then ret := - (reg'PIC_Config_Reg - (Map.lookup - ((#config_regs) (!PIC), - BitsN.toNat(BitsN.fromNat(BitsN.toNat offset,7))))) - else if offset = (BitsN.B(0x400,37)) - then ret := - (BitsN.|| - (BitsN.bits((#ip_bits) (!PIC),63,0), - (#external_intrs) (!PIC))) - else if offset = (BitsN.B(0x401,37)) - then ret := (BitsN.bits((#ip_bits) (!PIC),127,64)) - else ret := (BitsN.B(0x0,64)) - ; (!ret) - ) - end - end; - -fun PIC_store (addr,(mask,data)) = - let - val offset = BitsN.-(addr,(#base_address) (!PIC)) - in - ( if BitsN.<(offset,BitsN.B(0x80,37)) - then let - val f = Map.copy((#config_regs) (!PIC)) - val x0 = BitsN.fromNat(BitsN.toNat offset,7) - val x1 = Map.lookup(f,BitsN.toNat x0) - in - PIC := - (PIC_config_regs_rupd - ((!PIC), - Map.update - (f,BitsN.toNat x0,write'reg'PIC_Config_Reg(x1,data)))) - end - else if BitsN.<(offset,BitsN.B(0x410,37)) - then () - else if offset = (BitsN.B(0x410,37)) - then let - val w = (#ip_bits) (!PIC) - in - PIC := - (PIC_ip_bits_rupd - ((!PIC), - BitsN.bitFieldInsert - (w, - BitsN.|| - (BitsN.bits((#ip_bits) (!PIC),63,0), - BitsN.&&(data,mask)),63,0))) - end - else if offset = (BitsN.B(0x411,37)) - then let - val w = (#ip_bits) (!PIC) - in - PIC := - (PIC_ip_bits_rupd - ((!PIC), - BitsN.bitFieldInsert - (w, - BitsN.|| - (BitsN.bits((#ip_bits) (!PIC),127,64), - BitsN.&&(data,mask)),127,64))) - end - else if offset = (BitsN.B(0x420,37)) - then let - val w = (#ip_bits) (!PIC) - in - PIC := - (PIC_ip_bits_rupd - ((!PIC), - BitsN.bitFieldInsert - (w, - BitsN.&& - (BitsN.bits((#ip_bits) (!PIC),63,0), - BitsN.~(BitsN.&&(data,mask))),63,0))) - end - else if offset = (BitsN.B(0x421,37)) - then let - val w = (#ip_bits) (!PIC) - in - PIC := - (PIC_ip_bits_rupd - ((!PIC), - BitsN.bitFieldInsert - (w, - BitsN.&& - (BitsN.bits((#ip_bits) (!PIC),127,64), - BitsN.~(BitsN.&&(data,mask))),127,64))) - end - else () - ; PIC_update () - ) - end; - -fun rec'JTAG_UART_data x = - {RAVAIL = BitsN.bits(x,31,16), RVALID = BitsN.bit(x,15), - RW_DATA = BitsN.bits(x,7,0), jtag_uart_data'rst = BitsN.bits(x,14,8)}; - -fun reg'JTAG_UART_data x = - case x of - {RAVAIL = RAVAIL, RVALID = RVALID, RW_DATA = RW_DATA, - jtag_uart_data'rst = jtag_uart_data'rst} => - BitsN.modify - (fn (i,_) => - if i = 31 - then BitsN.bit(RAVAIL,15) - else if i = 30 - then BitsN.bit(RAVAIL,14) - else if i = 29 - then BitsN.bit(RAVAIL,13) - else if i = 28 - then BitsN.bit(RAVAIL,12) - else if i = 27 - then BitsN.bit(RAVAIL,11) - else if i = 26 - then BitsN.bit(RAVAIL,10) - else if i = 25 - then BitsN.bit(RAVAIL,9) - else if i = 24 - then BitsN.bit(RAVAIL,8) - else if i = 23 - then BitsN.bit(RAVAIL,7) - else if i = 22 - then BitsN.bit(RAVAIL,6) - else if i = 21 - then BitsN.bit(RAVAIL,5) - else if i = 20 - then BitsN.bit(RAVAIL,4) - else if i = 19 - then BitsN.bit(RAVAIL,3) - else if i = 18 - then BitsN.bit(RAVAIL,2) - else if i = 17 - then BitsN.bit(RAVAIL,1) - else if i = 16 - then BitsN.bit(RAVAIL,0) - else if i = 15 - then RVALID - else if i = 14 - then BitsN.bit(jtag_uart_data'rst,6) - else if i = 13 - then BitsN.bit(jtag_uart_data'rst,5) - else if i = 12 - then BitsN.bit(jtag_uart_data'rst,4) - else if i = 11 - then BitsN.bit(jtag_uart_data'rst,3) - else if i = 10 - then BitsN.bit(jtag_uart_data'rst,2) - else if i = 9 - then BitsN.bit(jtag_uart_data'rst,1) - else if i = 8 - then BitsN.bit(jtag_uart_data'rst,0) - else if i = 7 - then BitsN.bit(RW_DATA,7) - else if i = 6 - then BitsN.bit(RW_DATA,6) - else if i = 5 - then BitsN.bit(RW_DATA,5) - else if i = 4 - then BitsN.bit(RW_DATA,4) - else if i = 3 - then BitsN.bit(RW_DATA,3) - else if i = 2 - then BitsN.bit(RW_DATA,2) - else if i = 1 - then BitsN.bit(RW_DATA,1) - else BitsN.bit(RW_DATA,0),BitsN.B(0x0,32)); - -fun write'rec'JTAG_UART_data (_,x) = reg'JTAG_UART_data x; - -fun write'reg'JTAG_UART_data (_,x) = rec'JTAG_UART_data x; - -fun rec'JTAG_UART_control x = - {AC = BitsN.bit(x,10), RE = BitsN.bit(x,0), RI = BitsN.bit(x,8), - WE = BitsN.bit(x,1), WI = BitsN.bit(x,9), WSPACE = BitsN.bits(x,31,16), - jtag_uart_control'rst = BitsN.@@(BitsN.bits(x,7,2),BitsN.bits(x,15,11))}; - -fun reg'JTAG_UART_control x = - case x of - {AC = AC, RE = RE, RI = RI, WE = WE, WI = WI, WSPACE = WSPACE, - jtag_uart_control'rst = jtag_uart_control'rst} => - BitsN.modify - (fn (i,_) => - if i = 31 - then BitsN.bit(WSPACE,15) - else if i = 30 - then BitsN.bit(WSPACE,14) - else if i = 29 - then BitsN.bit(WSPACE,13) - else if i = 28 - then BitsN.bit(WSPACE,12) - else if i = 27 - then BitsN.bit(WSPACE,11) - else if i = 26 - then BitsN.bit(WSPACE,10) - else if i = 25 - then BitsN.bit(WSPACE,9) - else if i = 24 - then BitsN.bit(WSPACE,8) - else if i = 23 - then BitsN.bit(WSPACE,7) - else if i = 22 - then BitsN.bit(WSPACE,6) - else if i = 21 - then BitsN.bit(WSPACE,5) - else if i = 20 - then BitsN.bit(WSPACE,4) - else if i = 19 - then BitsN.bit(WSPACE,3) - else if i = 18 - then BitsN.bit(WSPACE,2) - else if i = 17 - then BitsN.bit(WSPACE,1) - else if i = 16 - then BitsN.bit(WSPACE,0) - else if i = 15 - then BitsN.bit(jtag_uart_control'rst,4) - else if i = 14 - then BitsN.bit(jtag_uart_control'rst,3) - else if i = 13 - then BitsN.bit(jtag_uart_control'rst,2) - else if i = 12 - then BitsN.bit(jtag_uart_control'rst,1) - else if i = 11 - then BitsN.bit(jtag_uart_control'rst,0) - else if i = 10 - then AC - else if i = 9 - then WI - else if i = 8 - then RI - else if i = 7 - then BitsN.bit(jtag_uart_control'rst,10) - else if i = 6 - then BitsN.bit(jtag_uart_control'rst,9) - else if i = 5 - then BitsN.bit(jtag_uart_control'rst,8) - else if i = 4 - then BitsN.bit(jtag_uart_control'rst,7) - else if i = 3 - then BitsN.bit(jtag_uart_control'rst,6) - else if i = 2 - then BitsN.bit(jtag_uart_control'rst,5) - else if i = 1 then WE else RE,BitsN.B(0x0,32)); - -fun write'rec'JTAG_UART_control (_,x) = reg'JTAG_UART_control x; - -fun write'reg'JTAG_UART_control (_,x) = rec'JTAG_UART_control x; - -fun JTAG_UART_update_interrupt_bit () = - let - val readIntr = - ((#RE)((#control) (!JTAG_UART))) andalso - ((#RVALID)((#data) (!JTAG_UART))) - in - if not(((#RI)((#control) (!JTAG_UART))) = readIntr) - then ( let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_RI_rupd(x0,readIntr))) - end - ; let - val w = (#external_intrs) (!PIC) - in - PIC := - (PIC_external_intrs_rupd - ((!PIC), - BitsN.bitFieldInsert(w,BitsN.fromBit readIntr,0,0))) - end - ; PIC_update () - ) - else () - end; - -fun JTAG_UART_load () = - ( case (#read_fifo) (!JTAG_UART) of - [] => - ( let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART), - JTAG_UART_data_RAVAIL_rupd(x0,BitsN.B(0x0,16)))) - end - ; let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART),JTAG_UART_data_RVALID_rupd(x0,false))) - end - ) - | h :: t => - ( let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART),JTAG_UART_data_RW_DATA_rupd(x0,h))) - end - ; let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART), - JTAG_UART_data_RAVAIL_rupd - (x0,BitsN.fromNat(List.length t,16)))) - end - ; let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART),JTAG_UART_data_RVALID_rupd(x0,true))) - end - ; JTAG_UART := (JTAG_UART_read_fifo_rupd((!JTAG_UART),t)) - ) - ; JTAG_UART_update_interrupt_bit () - ); - -fun JTAG_UART_input l = - ( case ((#read_fifo) (!JTAG_UART)) @ l of - [] => - let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART), - JTAG_UART_data_RAVAIL_rupd(x0,BitsN.B(0x0,16)))) - end - | t => - ( JTAG_UART := (JTAG_UART_read_fifo_rupd((!JTAG_UART),t)) - ; let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART), - JTAG_UART_data_RAVAIL_rupd - (x0,BitsN.fromNat(List.length t,16)))) - end - ; let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_AC_rupd(x0,true))) - end - ; if not((#RVALID)((#data) (!JTAG_UART))) - then JTAG_UART_load () - else () - ) - ; JTAG_UART_update_interrupt_bit () - ); - -fun JTAG_UART_store (mask,MemElem) = - ( if (not((BitsN.bits(mask,63,56)) = (BitsN.B(0x0,8)))) andalso - (not(((#WSPACE)((#control) (!JTAG_UART))) = (BitsN.B(0x0,16)))) - then ( let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART), - JTAG_UART_control_WSPACE_rupd - (x0, - BitsN.- - ((#WSPACE)((#control) (!JTAG_UART)), - BitsN.B(0x1,16))))) - end - ; JTAG_UART := - (JTAG_UART_write_fifo_rupd - ((!JTAG_UART), - (BitsN.bits(MemElem,63,56)) - :: - ((#write_fifo) (!JTAG_UART)))) - ) - else () - ; if BitsN.bit(mask,24) - then let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART), - JTAG_UART_control_RE_rupd(x0,BitsN.bit(MemElem,24)))) - end - else () - ; if BitsN.bit(mask,25) - then let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART), - JTAG_UART_control_WE_rupd(x0,BitsN.bit(MemElem,25)))) - end - else () - ; if (BitsN.bit(mask,18)) andalso (BitsN.bit(MemElem,18)) - then let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_AC_rupd(x0,false))) - end - else () - ; JTAG_UART_update_interrupt_bit () - ); - -fun JTAG_UART_output () = - ( let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_AC_rupd(x0,true))) - end - ; let - val l = List.rev((#write_fifo) (!JTAG_UART)) - in - ( JTAG_UART := (JTAG_UART_write_fifo_rupd((!JTAG_UART),[])) - ; let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART), - JTAG_UART_control_WSPACE_rupd(x0,BitsN.neg(BitsN.B(0x1,16))))) - end - ; let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_WI_rupd(x0,false))) - end - ; JTAG_UART_update_interrupt_bit () - ; l - ) - end - ); - -fun JTAG_UART_initialise uart = - ( JTAG_UART := - (JTAG_UART_base_address_rupd - ((!JTAG_UART), - BitsN.fromNat(BitsN.toNat(BitsN.>>+(BitsN.fromNat(uart,40),3)),37))) - ; JTAG_UART := (JTAG_UART_read_threshold_rupd((!JTAG_UART),65280)) - ; JTAG_UART := (JTAG_UART_write_threshold_rupd((!JTAG_UART),65520)) - ; JTAG_UART := (JTAG_UART_read_fifo_rupd((!JTAG_UART),[])) - ; JTAG_UART := (JTAG_UART_write_fifo_rupd((!JTAG_UART),[])) - ; let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART),JTAG_UART_data_RW_DATA_rupd(x0,BitsN.B(0x0,8)))) - end - ; let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART),JTAG_UART_data_RVALID_rupd(x0,false))) - end - ; let - val x0 = (#data) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_data_rupd - ((!JTAG_UART),JTAG_UART_data_RAVAIL_rupd(x0,BitsN.B(0x0,16)))) - end - ; let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_RE_rupd(x0,true))) - end - ; let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_WE_rupd(x0,false))) - end - ; let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_RI_rupd(x0,false))) - end - ; let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_WI_rupd(x0,false))) - end - ; let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART),JTAG_UART_control_AC_rupd(x0,false))) - end - ; let - val x0 = (#control) (!JTAG_UART) - in - JTAG_UART := - (JTAG_UART_control_rupd - ((!JTAG_UART), - JTAG_UART_control_WSPACE_rupd(x0,BitsN.neg(BitsN.B(0x1,16))))) - end - ); - -val PSIZE = 40 - -fun mark e = log := (e :: (!log)); - -fun unmark () = log := (List.tl (!log)); - -fun flip_endian_word w = - case boolify'32 w of - (a'7, - (a'6, - (a'5, - (a'4, - (a'3, - (a'2, - (a'1, - (a'0, - (b'7, - (b'6, - (b'5, - (b'4, - (b'3, - (b'2, - (b'1, - (b'0, - (c'7, - (c'6, - (c'5, - (c'4, - (c'3, - (c'2, - (c'1, - (c'0, - (d'7,(d'6,(d'5,(d'4,(d'3,(d'2,(d'1,d'0))))))))))))))))))))))))))))))) => - BitsN.concat - [BitsN.fromBitstring([d'7,d'6,d'5,d'4,d'3,d'2,d'1,d'0],8), - BitsN.fromBitstring([c'7,c'6,c'5,c'4,c'3,c'2,c'1,c'0],8), - BitsN.fromBitstring([b'7,b'6,b'5,b'4,b'3,b'2,b'1,b'0],8), - BitsN.fromBitstring([a'7,a'6,a'5,a'4,a'3,a'2,a'1,a'0],8)]; - -fun flip_endian_dword dw = - case boolify'64 dw of - (a'7, - (a'6, - (a'5, - (a'4, - (a'3, - (a'2, - (a'1, - (a'0, - (b'7, - (b'6, - (b'5, - (b'4, - (b'3, - (b'2, - (b'1, - (b'0, - (c'7, - (c'6, - (c'5, - (c'4, - (c'3, - (c'2, - (c'1, - (c'0, - (d'7, - (d'6, - (d'5, - (d'4, - (d'3, - (d'2, - (d'1, - (d'0, - (e'7, - (e'6, - (e'5, - (e'4, - (e'3, - (e'2, - (e'1, - (e'0, - (f'7, - (f'6, - (f'5, - (f'4, - (f'3, - (f'2, - (f'1, - (f'0, - (g'7, - (g'6, - (g'5, - (g'4, - (g'3, - (g'2, - (g'1, - (g'0, - (h'7, - (h'6, - (h'5, - (h'4, - (h'3, - (h'2, - (h'1, - h'0))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) => - BitsN.concat - [BitsN.fromBitstring([h'7,h'6,h'5,h'4,h'3,h'2,h'1,h'0],8), - BitsN.fromBitstring([g'7,g'6,g'5,g'4,g'3,g'2,g'1,g'0],8), - BitsN.fromBitstring([f'7,f'6,f'5,f'4,f'3,f'2,f'1,f'0],8), - BitsN.fromBitstring([e'7,e'6,e'5,e'4,e'3,e'2,e'1,e'0],8), - BitsN.fromBitstring([d'7,d'6,d'5,d'4,d'3,d'2,d'1,d'0],8), - BitsN.fromBitstring([c'7,c'6,c'5,c'4,c'3,c'2,c'1,c'0],8), - BitsN.fromBitstring([b'7,b'6,b'5,b'4,b'3,b'2,b'1,b'0],8), - BitsN.fromBitstring([a'7,a'6,a'5,a'4,a'3,a'2,a'1,a'0],8)]; - -val TLBEntries = 16 - -fun GPR n = - if n = (BitsN.B(0x0,5)) - then BitsN.B(0x0,64) - else Map.lookup((!gpr),BitsN.toNat n); - -fun write'GPR (value,n) = - if not(n = (BitsN.B(0x0,5))) - then ( gpr := (Map.update((!gpr),BitsN.toNat n,value)) - ; mark(w_gpr(n,value)) - ) - else (); - -fun HI () = - case (!hi) of - Option.SOME v => v - | NONE => ( (!UNPREDICTABLE_HI) (); BitsN.B(0x0,64) ); - -fun write'HI value = ( hi := (Option.SOME value); mark(w_hi value) ); - -fun LO () = - case (!lo) of - Option.SOME v => v - | NONE => ( (!UNPREDICTABLE_LO) (); BitsN.B(0x0,64) ); - -fun write'LO value = ( lo := (Option.SOME value); mark(w_lo value) ); - -fun CPR (n,(reg,sel)) = - case (n,(reg,sel)) of - (0,(BitsN.B(0x0,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat(reg'Index((#Index) (!CP0))),64) - | (0,(BitsN.B(0x1,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat(reg'Random((#Random) (!CP0))),64) - | (0,(BitsN.B(0x2,5),BitsN.B(0x0,3))) => - reg'EntryLo((#EntryLo0) (!CP0)) - | (0,(BitsN.B(0x3,5),BitsN.B(0x0,3))) => - reg'EntryLo((#EntryLo1) (!CP0)) - | (0,(BitsN.B(0x4,5),BitsN.B(0x0,3))) => reg'Context((#Context) (!CP0)) - | (0,(BitsN.B(0x4,5),BitsN.B(0x2,3))) => (#UsrLocal) (!CP0) - | (0,(BitsN.B(0x5,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat(reg'PageMask((#PageMask) (!CP0))),64) - | (0,(BitsN.B(0x6,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat(reg'Wired((#Wired) (!CP0))),64) - | (0,(BitsN.B(0x7,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat(reg'HWREna((#HWREna) (!CP0))),64) - | (0,(BitsN.B(0x8,5),BitsN.B(0x0,3))) => (#BadVAddr) (!CP0) - | (0,(BitsN.B(0x9,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat((#Count) (!CP0)),64) - | (0,(BitsN.B(0xA,5),BitsN.B(0x0,3))) => reg'EntryHi((#EntryHi) (!CP0)) - | (0,(BitsN.B(0xB,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat((#Compare) (!CP0)),64) - | (0,(BitsN.B(0xC,5),BitsN.B(0x0,3))) => - BitsN.fromNat - (BitsN.toNat(reg'StatusRegister((#Status) (!CP0))),64) - | (0,(BitsN.B(0xD,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat(reg'CauseRegister((#Cause) (!CP0))),64) - | (0,(BitsN.B(0xE,5),BitsN.B(0x0,3))) => (#EPC) (!CP0) - | (0,(BitsN.B(0xF,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat((#PRId) (!CP0)),64) - | (0,(BitsN.B(0x10,5),BitsN.B(0x0,3))) => - BitsN.fromNat - (BitsN.toNat(reg'ConfigRegister((#Config) (!CP0))),64) - | (0,(BitsN.B(0x10,5),BitsN.B(0x1,3))) => - BitsN.fromNat - (BitsN.toNat(reg'ConfigRegister1((#Config1) (!CP0))),64) - | (0,(BitsN.B(0x10,5),BitsN.B(0x2,3))) => - BitsN.fromNat - (BitsN.toNat(reg'ConfigRegister2((#Config2) (!CP0))),64) - | (0,(BitsN.B(0x10,5),BitsN.B(0x3,3))) => - BitsN.fromNat - (BitsN.toNat(reg'ConfigRegister3((#Config3) (!CP0))),64) - | (0,(BitsN.B(0x10,5),BitsN.B(0x4,3))) => BitsN.B(0x1,64) - | (0,(BitsN.B(0x10,5),BitsN.B(0x5,3))) => BitsN.B(0x1,64) - | (0,(BitsN.B(0x10,5),BitsN.B(0x6,3))) => - BitsN.fromNat - (BitsN.toNat(reg'ConfigRegister6((#Config6) (!CP0))),64) - | (0,(BitsN.B(0x11,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat((#LLAddr) (!CP0)),64) - | (0,(BitsN.B(0x14,5),BitsN.B(0x0,3))) => - reg'XContext((#XContext) (!CP0)) - | (0,(BitsN.B(0x17,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat((#Debug) (!CP0)),64) - | (0,(BitsN.B(0x1A,5),BitsN.B(0x0,3))) => - BitsN.fromNat(BitsN.toNat((#ErrCtl) (!CP0)),64) - | (0,(BitsN.B(0x1E,5),BitsN.B(0x0,3))) => (#ErrorEPC) (!CP0) - | _ => BitsN.B(0x0,64); - -fun write'CPR (value,(n,(reg,sel))) = - ( mark(w_c0(reg,value)) - ; case (n,(reg,sel)) of - (0,(BitsN.B(0x0,5),BitsN.B(0x0,3))) => - let - val x0 = (#Index) (!CP0) - in - CP0 := - (CP0_Index_rupd - ((!CP0),Index_Index_rupd(x0,BitsN.bits(value,7,0)))) - end - | (0,(BitsN.B(0x2,5),BitsN.B(0x0,3))) => - let - val x0 = (#EntryLo0) (!CP0) - in - CP0 := (CP0_EntryLo0_rupd((!CP0),write'reg'EntryLo(x0,value))) - end - | (0,(BitsN.B(0x3,5),BitsN.B(0x0,3))) => - let - val x0 = (#EntryLo1) (!CP0) - in - CP0 := (CP0_EntryLo1_rupd((!CP0),write'reg'EntryLo(x0,value))) - end - | (0,(BitsN.B(0x4,5),BitsN.B(0x0,3))) => - let - val x0 = (#Context) (!CP0) - in - CP0 := - (CP0_Context_rupd - ((!CP0),Context_PTEBase_rupd(x0,BitsN.bits(value,63,23)))) - end - | (0,(BitsN.B(0x4,5),BitsN.B(0x2,3))) => - CP0 := (CP0_UsrLocal_rupd((!CP0),value)) - | (0,(BitsN.B(0x5,5),BitsN.B(0x0,3))) => - let - val x0 = (#PageMask) (!CP0) - in - CP0 := - (CP0_PageMask_rupd - ((!CP0),PageMask_Mask_rupd(x0,BitsN.bits(value,24,13)))) - end - | (0,(BitsN.B(0x6,5),BitsN.B(0x0,3))) => - ( let - val x0 = (#Wired) (!CP0) - in - CP0 := - (CP0_Wired_rupd - ((!CP0),Wired_Wired_rupd(x0,BitsN.bits(value,7,0)))) - end - ; let - val x0 = (#Random) (!CP0) - in - CP0 := - (CP0_Random_rupd - ((!CP0), - Random_Random_rupd - (x0,BitsN.fromNat(Nat.-(TLBEntries,1),8)))) - end - ) - | (0,(BitsN.B(0x7,5),BitsN.B(0x0,3))) => - ( let - val x0 = (#HWREna) (!CP0) - in - CP0 := - (CP0_HWREna_rupd - ((!CP0),HWREna_CPUNum_rupd(x0,BitsN.bit(value,0)))) - end - ; let - val x0 = (#HWREna) (!CP0) - in - CP0 := - (CP0_HWREna_rupd - ((!CP0),HWREna_CC_rupd(x0,BitsN.bit(value,2)))) - end - ; let - val x0 = (#HWREna) (!CP0) - in - CP0 := - (CP0_HWREna_rupd - ((!CP0),HWREna_CCRes_rupd(x0,BitsN.bit(value,3)))) - end - ; let - val x0 = (#HWREna) (!CP0) - in - CP0 := - (CP0_HWREna_rupd - ((!CP0),HWREna_UL_rupd(x0,BitsN.bit(value,29)))) - end - ) - | (0,(BitsN.B(0x9,5),BitsN.B(0x0,3))) => - CP0 := (CP0_Count_rupd((!CP0),BitsN.bits(value,31,0))) - | (0,(BitsN.B(0xA,5),BitsN.B(0x0,3))) => - let - val x0 = (#EntryHi) (!CP0) - in - CP0 := (CP0_EntryHi_rupd((!CP0),write'reg'EntryHi(x0,value))) - end - | (0,(BitsN.B(0xB,5),BitsN.B(0x0,3))) => - ( CP0 := (CP0_Compare_rupd((!CP0),BitsN.bits(value,31,0))) - ; let - val x0 = (#Cause) (!CP0) - val w = (#IP) x0 - in - CP0 := - (CP0_Cause_rupd - ((!CP0), - CauseRegister_IP_rupd - (x0,BitsN.bitFieldInsert(w,BitsN.fromBit false,7,7)))) - end - ; let - val x0 = (#Cause) (!CP0) - in - CP0 := - (CP0_Cause_rupd((!CP0),CauseRegister_TI_rupd(x0,false))) - end - ) - | (0,(BitsN.B(0xC,5),BitsN.B(0x0,3))) => - let - val x0 = (#Status) (!CP0) - in - CP0 := - (CP0_Status_rupd - ((!CP0),write'reg'StatusRegister(x0,BitsN.bits(value,31,0)))) - end - | (0,(BitsN.B(0xD,5),BitsN.B(0x0,3))) => - let - val x0 = (#Cause) (!CP0) - in - CP0 := - (CP0_Cause_rupd - ((!CP0),write'reg'CauseRegister(x0,BitsN.bits(value,31,0)))) - end - | (0,(BitsN.B(0xE,5),BitsN.B(0x0,3))) => - CP0 := (CP0_EPC_rupd((!CP0),value)) - | (0,(BitsN.B(0x10,5),BitsN.B(0x0,3))) => - let - val x0 = (#Config) (!CP0) - in - CP0 := - (CP0_Config_rupd - ((!CP0),ConfigRegister_K0_rupd(x0,BitsN.bits(value,2,0)))) - end - | (0,(BitsN.B(0x10,5),BitsN.B(0x2,3))) => - let - val x0 = (#Config2) (!CP0) - in - CP0 := - (CP0_Config2_rupd - ((!CP0),ConfigRegister2_SU_rupd(x0,BitsN.bits(value,15,12)))) - end - | (0,(BitsN.B(0x10,5),BitsN.B(0x6,3))) => - let - val x0 = (#Config6) (!CP0) - in - CP0 := - (CP0_Config6_rupd - ((!CP0),ConfigRegister6_LTLB_rupd(x0,BitsN.bit(value,2)))) - end - | (0,(BitsN.B(0x14,5),BitsN.B(0x0,3))) => - let - val x0 = (#XContext) (!CP0) - in - CP0 := - (CP0_XContext_rupd - ((!CP0),XContext_PTEBase_rupd(x0,BitsN.bits(value,63,33)))) - end - | (0,(BitsN.B(0x17,5),BitsN.B(0x0,3))) => - CP0 := (CP0_Debug_rupd((!CP0),BitsN.bits(value,31,0))) - | (0,(BitsN.B(0x1A,5),BitsN.B(0x0,3))) => - CP0 := (CP0_ErrCtl_rupd((!CP0),BitsN.bits(value,31,0))) - | (0,(BitsN.B(0x1E,5),BitsN.B(0x0,3))) => - CP0 := (CP0_ErrorEPC_rupd((!CP0),value)) - | _ => unmark () - ); - -fun LookupTLB (r,vpn2) = - let - val e = Map.lookup((!TLB_direct),BitsN.toNat(BitsN.bits(vpn2,6,0))) - val index = - if Nat.>=(BitsN.toNat(BitsN.bits(vpn2,6,0)),TLBEntries) - then BitsN.fromNat(BitsN.toNat(BitsN.bits(vpn2,6,0)),8) - else BitsN.+ - (BitsN.B(0x80,8), - BitsN.fromNat(BitsN.toNat(BitsN.bits(vpn2,6,0)),8)) - val nmask = BitsN.~(BitsN.fromNat(BitsN.toNat((#Mask) e),27)) - in - let - val found = ref [] - in - ( if (#LTLB)((#Config6) (!CP0)) - then found := - (if (((BitsN.&&((#VPN2) e,nmask)) = (BitsN.&&(vpn2,nmask))) andalso - (((#R) e) = r)) andalso - (((#G) e) orelse - (((#ASID) e) = ((#ASID)((#EntryHi) (!CP0))))) - then [(index,e)] - else []) - else () - ; L3.for - (0,Nat.-(TLBEntries,1), - fn i => - let - val e = - Map.lookup((!TLB_assoc),BitsN.toNat(BitsN.fromNat(i,4))) - val nmask = - BitsN.~(BitsN.fromNat(BitsN.toNat((#Mask) e),27)) - in - if (((BitsN.&&((#VPN2) e,nmask)) = (BitsN.&&(vpn2,nmask))) andalso - (((#R) e) = r)) andalso - (((#G) e) orelse - (((#ASID) e) = ((#ASID)((#EntryHi) (!CP0))))) - then found := ((BitsN.fromNat(i,8),e) :: (!found)) - else () - end) - ; (!found) - ) - end - end; - -fun ModifyTLB ie = - let - val eHi = (#EntryHi) (!CP0) - val eLo1 = (#EntryLo1) (!CP0) - val eLo0 = (#EntryLo0) (!CP0) - in - let - val e = ref ie - in - ( e := (TLBEntry_Mask_rupd((!e),(#Mask)((#PageMask) (!CP0)))) - ; e := (TLBEntry_R_rupd((!e),(#R) eHi)) - ; e := (TLBEntry_VPN2_rupd((!e),(#VPN2) eHi)) - ; e := (TLBEntry_ASID_rupd((!e),(#ASID) eHi)) - ; e := (TLBEntry_PFN1_rupd((!e),(#PFN) eLo1)) - ; e := (TLBEntry_C1_rupd((!e),(#C) eLo1)) - ; e := (TLBEntry_D1_rupd((!e),(#D) eLo1)) - ; e := (TLBEntry_V1_rupd((!e),(#V) eLo1)) - ; e := (TLBEntry_G_rupd((!e),((#G) eLo1) andalso ((#G) eLo0))) - ; e := (TLBEntry_PFN0_rupd((!e),(#PFN) eLo0)) - ; e := (TLBEntry_C0_rupd((!e),(#C) eLo0)) - ; e := (TLBEntry_D0_rupd((!e),(#D) eLo0)) - ; e := (TLBEntry_V0_rupd((!e),(#V) eLo0)) - ; (!e) - ) - end - end; - -fun SignalTLBException (e,(asid,vAddr)) = - let - val r = BitsN.bits(vAddr,63,62) - val vpn2 = BitsN.bits(vAddr,39,13) - in - ( SignalException e - ; CP0 := (CP0_BadVAddr_rupd((!CP0),vAddr)) - ; let - val x0 = (#EntryHi) (!CP0) - in - CP0 := (CP0_EntryHi_rupd((!CP0),EntryHi_R_rupd(x0,r))) - end - ; let - val x0 = (#EntryHi) (!CP0) - in - CP0 := (CP0_EntryHi_rupd((!CP0),EntryHi_VPN2_rupd(x0,vpn2))) - end - ; let - val x0 = (#EntryHi) (!CP0) - in - CP0 := (CP0_EntryHi_rupd((!CP0),EntryHi_ASID_rupd(x0,asid))) - end - ; let - val x0 = (#XContext) (!CP0) - in - CP0 := (CP0_XContext_rupd((!CP0),XContext_R_rupd(x0,r))) - end - ; let - val x0 = (#XContext) (!CP0) - in - CP0 := (CP0_XContext_rupd((!CP0),XContext_BadVPN2_rupd(x0,vpn2))) - end - ; let - val x0 = (#Context) (!CP0) - in - CP0 := - (CP0_Context_rupd - ((!CP0),Context_BadVPN2_rupd(x0,BitsN.bits(vAddr,31,13)))) - end - ; (BitsN.B(0x0,40),BitsN.B(0x0,3)) - ) - end; - -fun CheckSegment vAddr = - if UserMode () - then (NONE,BitsN.<+(vAddr,BitsN.B(0x10000000000,64))) - else if SupervisorMode () - then (NONE, - ((BitsN.<+(vAddr,BitsN.B(0x10000000000,64))) orelse - ((BitsN.<=+(vAddr,BitsN.B(0x4000000000000000,64))) andalso - (BitsN.<+(vAddr,BitsN.B(0x4000010000000000,64))))) orelse - ((BitsN.<=+(vAddr,BitsN.B(0xFFFFFFFFC0000000,64))) andalso - (BitsN.<+(vAddr,BitsN.B(0xFFFFFFFFE0000000,64))))) - else if BitsN.<+(vAddr,BitsN.B(0x10000000000,64)) - then (NONE,true) - else if (BitsN.<=+(BitsN.B(0x4000000000000000,64),vAddr)) andalso - (BitsN.<+(vAddr,BitsN.B(0x4000010000000000,64))) - then (NONE,true) - else if (BitsN.<=+(BitsN.B(0x8000000000000000,64),vAddr)) andalso - (BitsN.<+(vAddr,BitsN.B(0xC000000000000000,64))) - then (Option.SOME(BitsN.bits(vAddr,39,0),BitsN.bits(vAddr,61,59)), - (BitsN.bits(vAddr,58,40)) = (BitsN.B(0x0,19))) - else if (BitsN.<=+(BitsN.B(0xC000000000000000,64),vAddr)) andalso - (BitsN.<+(vAddr,BitsN.B(0xC00000FF80000000,64))) - then (NONE,true) - else if (BitsN.<=+(BitsN.B(0xFFFFFFFF80000000,64),vAddr)) andalso - (BitsN.<+(vAddr,BitsN.B(0xFFFFFFFFA0000000,64))) - then (Option.SOME - (BitsN.-(BitsN.bits(vAddr,39,0),BitsN.B(0xFF80000000,40)), - (#K0)((#Config) (!CP0))),true) - else if (BitsN.<=+(BitsN.B(0xFFFFFFFFA0000000,64),vAddr)) andalso - (BitsN.<+(vAddr,BitsN.B(0xFFFFFFFFC0000000,64))) - then (Option.SOME - (BitsN.-(BitsN.bits(vAddr,39,0),BitsN.B(0xFFA0000000,40)), - BitsN.B(0x2,3)),true) - else (NONE,BitsN.<=+(BitsN.B(0xFFFFFFFFC0000000,64),vAddr)); - -fun AddressTranslation (vAddr,(IorD,LorS)) = - let - val (unmapped,valid) = CheckSegment vAddr - in - if valid - then case unmapped of - Option.SOME(pAddr,cca) => (pAddr,cca) - | NONE => - (case LookupTLB - (BitsN.bits(vAddr,63,62),BitsN.bits(vAddr,39,13)) of - [] => - let - val exc = - if LorS = LOAD - then XTLBRefillL - else XTLBRefillS - in - SignalTLBException - (exc,((#ASID)((#EntryHi) (!CP0)),vAddr)) - end - | [(_,e)] => - let - val EvenOddBit = - case (#Mask) e of - BitsN.B(0x0,12) => 12 - | BitsN.B(0x3,12) => 14 - | BitsN.B(0xF,12) => 16 - | BitsN.B(0x3F,12) => 18 - | BitsN.B(0xFF,12) => 20 - | BitsN.B(0x3FF,12) => 22 - | BitsN.B(0xFFF,12) => 24 - | _ => raise UNPREDICTABLE ("TLB: bad mask") - val (PFN,(C,(D,V))) = - if BitsN.bit(vAddr,EvenOddBit) - then ((#PFN1) e,((#C1) e,((#D1) e,(#V1) e))) - else ((#PFN0) e,((#C0) e,((#D0) e,(#V0) e))) - in - if V - then if (not D) andalso (LorS = STORE) - then SignalTLBException - (Mod,((#ASID) e,vAddr)) - else let - val PFN_ = BitsN.toBitstring PFN - val vAddr_ = BitsN.toBitstring vAddr - val pAddr = - (Bitstring.bits - (PFN_,27,Nat.-(EvenOddBit,12))) - @ - (Bitstring.bits - (vAddr_,Nat.-(EvenOddBit,1),0)) - in - (BitsN.fromBitstring(pAddr,40),C) - end - else let - val exc = - if LorS = LOAD then TLBL else TLBS - in - SignalTLBException(exc,((#ASID) e,vAddr)) - end - end - | _ => raise UNPREDICTABLE ("TLB: multiple matches")) - else ( CP0 := (CP0_BadVAddr_rupd((!CP0),vAddr)) - ; SignalException(if LorS = LOAD then AdEL else AdES) - ; (BitsN.B(0x0,40),BitsN.B(0x0,3)) - ) - end; - -fun LoadMemory (CCA,(AccessLength,(pAddr,(vAddr,IorD)))) = - let - val a = BitsN.bits(pAddr,39,3) - in - let - val ret = ref (BitsN.B(0x0,64)) - in - ( if a = ((#base_address) (!JTAG_UART)) - then ( ret := - (BitsN.@@ - (flip_endian_word - (reg'JTAG_UART_data((#data) (!JTAG_UART))), - flip_endian_word - (reg'JTAG_UART_control((#control) (!JTAG_UART))))) - ; if (BitsN.bits(pAddr,2,0)) = (BitsN.B(0x0,3)) - then JTAG_UART_load () - else () - ) - else if (BitsN.>=(a,(#base_address) (!PIC))) andalso - (BitsN.<(a,BitsN.+((#base_address) (!PIC),BitsN.B(0x430,37)))) - then ret := (PIC_load a) - else ret := (Map.lookup((!MEM),BitsN.toNat a)) - ; (!ret) - ) - end - end; - -fun loadWord32 a = - let - val d = Map.lookup((!MEM),BitsN.toNat(BitsN.bits(a,39,3))) - in - if BitsN.bit(a,2) then BitsN.bits(d,31,0) else BitsN.bits(d,63,32) - end; - -fun StoreMemory (CCA,(AccessLength,(MemElem,(pAddr,(vAddr,IorD))))) = - let - val a = BitsN.bits(pAddr,39,3) - val l = - Nat.- - (64, - Nat.* - (Nat.+ - (Nat.+(BitsN.toNat AccessLength,1), - BitsN.toNat(BitsN.bits(pAddr,2,0))),8)) - val mask = - BitsN.fromNat - (Nat.- - (Nat.pow(2,Nat.+(l,Nat.*(Nat.+(BitsN.toNat AccessLength,1),8))), - Nat.pow(2,l)),64) - in - ( mark(w_mem(pAddr,(mask,(AccessLength,MemElem)))) - ; if a = ((#base_address) (!JTAG_UART)) - then JTAG_UART_store(mask,MemElem) - else if (BitsN.>=(a,(#base_address) (!PIC))) andalso - (BitsN.<(a,BitsN.+((#base_address) (!PIC),BitsN.B(0x430,37)))) - then PIC_store(a,(mask,MemElem)) - else MEM := - (Map.update - ((!MEM),BitsN.toNat a, - BitsN.|| - (BitsN.&&(Map.lookup((!MEM),BitsN.toNat a),BitsN.~ mask), - BitsN.&&(MemElem,mask)))) - ) - end; - -fun dfn'TLBP () = - if (not((#CU0)((#Status) (!CP0)))) andalso (not(KernelMode ())) - then SignalException CpU - else case LookupTLB((#R)((#EntryHi) (!CP0)),(#VPN2)((#EntryHi) (!CP0))) of - [] => - ( let - val x0 = (#Index) (!CP0) - in - CP0 := (CP0_Index_rupd((!CP0),Index_P_rupd(x0,true))) - end - ; let - val x0 = (#Index) (!CP0) - in - CP0 := - (CP0_Index_rupd - ((!CP0),Index_Index_rupd(x0,BitsN.B(0x0,8)))) - end - ) - | [(i,e)] => - ( let - val x0 = (#Index) (!CP0) - in - CP0 := (CP0_Index_rupd((!CP0),Index_P_rupd(x0,false))) - end - ; let - val x0 = (#Index) (!CP0) - in - CP0 := (CP0_Index_rupd((!CP0),Index_Index_rupd(x0,i))) - end - ) - | _ => raise UNPREDICTABLE ("TLB: multiple matches"); - -fun dfn'TLBR () = - if (not((#CU0)((#Status) (!CP0)))) andalso (not(KernelMode ())) - then SignalException CpU - else let - val i = (#Index)((#Index) (!CP0)) - val e = - if Nat.>=(BitsN.toNat i,TLBEntries) - then Map.lookup((!TLB_direct),BitsN.toNat(BitsN.bits(i,6,0))) - else Map.lookup - ((!TLB_assoc), - BitsN.toNat(BitsN.fromNat(BitsN.toNat i,4))) - in - ( let - val x0 = (#PageMask) (!CP0) - in - CP0 := - (CP0_PageMask_rupd((!CP0),PageMask_Mask_rupd(x0,(#Mask) e))) - end - ; let - val x0 = (#EntryHi) (!CP0) - in - CP0 := (CP0_EntryHi_rupd((!CP0),EntryHi_R_rupd(x0,(#R) e))) - end - ; let - val x0 = (#EntryHi) (!CP0) - in - CP0 := - (CP0_EntryHi_rupd((!CP0),EntryHi_VPN2_rupd(x0,(#VPN2) e))) - end - ; let - val x0 = (#EntryHi) (!CP0) - in - CP0 := - (CP0_EntryHi_rupd((!CP0),EntryHi_ASID_rupd(x0,(#ASID) e))) - end - ; let - val x0 = (#EntryLo1) (!CP0) - in - CP0 := - (CP0_EntryLo1_rupd((!CP0),EntryLo_PFN_rupd(x0,(#PFN1) e))) - end - ; let - val x0 = (#EntryLo1) (!CP0) - in - CP0 := (CP0_EntryLo1_rupd((!CP0),EntryLo_C_rupd(x0,(#C1) e))) - end - ; let - val x0 = (#EntryLo1) (!CP0) - in - CP0 := (CP0_EntryLo1_rupd((!CP0),EntryLo_D_rupd(x0,(#D1) e))) - end - ; let - val x0 = (#EntryLo1) (!CP0) - in - CP0 := (CP0_EntryLo1_rupd((!CP0),EntryLo_V_rupd(x0,(#V1) e))) - end - ; let - val x0 = (#EntryLo1) (!CP0) - in - CP0 := (CP0_EntryLo1_rupd((!CP0),EntryLo_G_rupd(x0,(#G) e))) - end - ; let - val x0 = (#EntryLo0) (!CP0) - in - CP0 := - (CP0_EntryLo0_rupd((!CP0),EntryLo_PFN_rupd(x0,(#PFN0) e))) - end - ; let - val x0 = (#EntryLo0) (!CP0) - in - CP0 := (CP0_EntryLo0_rupd((!CP0),EntryLo_C_rupd(x0,(#C0) e))) - end - ; let - val x0 = (#EntryLo0) (!CP0) - in - CP0 := (CP0_EntryLo0_rupd((!CP0),EntryLo_D_rupd(x0,(#D0) e))) - end - ; let - val x0 = (#EntryLo0) (!CP0) - in - CP0 := (CP0_EntryLo0_rupd((!CP0),EntryLo_V_rupd(x0,(#V0) e))) - end - ; let - val x0 = (#EntryLo0) (!CP0) - in - CP0 := (CP0_EntryLo0_rupd((!CP0),EntryLo_G_rupd(x0,(#G) e))) - end - ) - end; - -fun dfn'TLBWI () = - if (not((#CU0)((#Status) (!CP0)))) andalso (not(KernelMode ())) - then SignalException CpU - else if Nat.>=(BitsN.toNat((#Index)((#Index) (!CP0))),TLBEntries) - then let - val j = BitsN.bits((#VPN2)((#EntryHi) (!CP0)),6,0) - in - TLB_direct := - (Map.update - ((!TLB_direct),BitsN.toNat j, - ModifyTLB(Map.lookup((!TLB_direct),BitsN.toNat j)))) - end - else let - val i = BitsN.fromNat(BitsN.toNat((#Index)((#Index) (!CP0))),4) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i, - ModifyTLB(Map.lookup((!TLB_assoc),BitsN.toNat i)))) - end; - -fun dfn'TLBWR () = - if (not((#CU0)((#Status) (!CP0)))) andalso (not(KernelMode ())) - then SignalException CpU - else if (#LTLB)((#Config6) (!CP0)) - then let - val j = BitsN.bits((#VPN2)((#EntryHi) (!CP0)),6,0) - val old = Map.lookup((!TLB_direct),BitsN.toNat j) - in - ( TLB_direct := - (Map.update((!TLB_direct),BitsN.toNat j,ModifyTLB old)) - ; if ((#V0) old) andalso ((#V1) old) - then let - val x = - BitsN.fromNat - (BitsN.toNat((#Random)((#Random) (!CP0))),4) - in - TLB_assoc := - (Map.update((!TLB_assoc),BitsN.toNat x,old)) - end - else () - ) - end - else let - val j = (#Random)((#Random) (!CP0)) - val x = BitsN.fromNat(BitsN.toNat j,4) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat x, - ModifyTLB - (Map.lookup - ((!TLB_assoc), - BitsN.toNat(BitsN.fromNat(BitsN.toNat j,4)))))) - end; - -fun dfn'CACHE (base,(opn,offset)) = - if (not((#CU0)((#Status) (!CP0)))) andalso (not(KernelMode ())) - then SignalException CpU - else let - val vAddr = BitsN.+(GPR base,BitsN.signExtend 64 offset) - val x = AddressTranslation(vAddr,(DATA,LOAD)) - in - () - end; - -fun dfn'RDHWR (rt,rd) = - if (((#CU0)((#Status) (!CP0))) orelse (KernelMode ())) orelse - (BitsN.bit(reg'HWREna((#HWREna) (!CP0)),BitsN.toNat rd)) - then case rd of - BitsN.B(0x0,5) => write'GPR(BitsN.B(0x0,64),rt) - | BitsN.B(0x2,5) => - write'GPR(BitsN.signExtend 64 ((#Count) (!CP0)),rt) - | BitsN.B(0x3,5) => write'GPR(BitsN.B(0x1,64),rt) - | BitsN.B(0x1D,5) => write'GPR((#UsrLocal) (!CP0),rt) - | _ => SignalException ResI - else SignalException ResI; - -fun Fetch () = - ( log := [] - ; let - val x0 = (#Random) (!CP0) - in - CP0 := - (CP0_Random_rupd - ((!CP0), - Random_Random_rupd - (x0, - if ((#Random)((#Random) (!CP0))) = - ((#Wired)((#Wired) (!CP0))) - then BitsN.fromNat(Nat.-(TLBEntries,1),8) - else BitsN.-((#Random)((#Random) (!CP0)),BitsN.B(0x1,8))))) - end - ; if ((#Compare) (!CP0)) = ((#Count) (!CP0)) - then ( let - val x0 = (#Cause) (!CP0) - val w = (#IP) x0 - in - CP0 := - (CP0_Cause_rupd - ((!CP0), - CauseRegister_IP_rupd - (x0,BitsN.bitFieldInsert(w,BitsN.fromBit true,7,7)))) - end - ; let - val x0 = (#Cause) (!CP0) - in - CP0 := - (CP0_Cause_rupd((!CP0),CauseRegister_TI_rupd(x0,true))) - end - ) - else () - ; if ((#IE)((#Status) (!CP0))) andalso - (not(((#EXL)((#Status) (!CP0))) orelse ((#ERL)((#Status) (!CP0))))) - then ( let - val x0 = (#Cause) (!CP0) - val w = (#IP) x0 - in - CP0 := - (CP0_Cause_rupd - ((!CP0), - CauseRegister_IP_rupd - (x0, - BitsN.bitFieldInsert - (w,BitsN.bits((#mips_ip_bits) (!PIC),4,0),6,2)))) - end - ; let - val x0 = (#Cause) (!CP0) - val w = (#IP) x0 - in - CP0 := - (CP0_Cause_rupd - ((!CP0), - CauseRegister_IP_rupd - (x0, - BitsN.bitFieldInsert - (w, - BitsN.fromBit - ((BitsN.bit((#IP)((#Cause) (!CP0)),7)) orelse - (BitsN.bit((#mips_ip_bits) (!PIC),5))),7,7)))) - end - ; if not((BitsN.&& - (BitsN.bits((#IM)((#Status) (!CP0)),7,2), - BitsN.bits((#IP)((#Cause) (!CP0)),7,2))) = - (BitsN.B(0x0,6))) - then SignalException Int - else () - ) - else () - ; if (!exceptionSignalled) - then NONE - else if (BitsN.bits((!PC),1,0)) = (BitsN.B(0x0,2)) - then let - val (pc,cca) = AddressTranslation((!PC),(INSTRUCTION,LOAD)) - in - if (!exceptionSignalled) - then NONE - else Option.SOME(loadWord32 pc) - end - else ( CP0 := (CP0_BadVAddr_rupd((!CP0),(!PC))) - ; SignalException AdEL - ; NONE - ) - ); - -fun initTLB () = - let - val e = ref {ASID = BitsN.B(0x0,8), C0 = BitsN.B(0x0,3), - C1 = BitsN.B(0x0,3), D0 = false, D1 = false, G = false, - Mask = BitsN.B(0x0,12), PFN0 = BitsN.B(0x0,28), - PFN1 = BitsN.B(0x0,28), R = BitsN.B(0x0,2), V0 = false, V1 = false, - VPN2 = BitsN.B(0x0,27)} - in - ( e := (TLBEntry_R_rupd((!e),BitsN.B(0x2,2))); (!e) ) - end; - -fun addTLB (a,i) = - let - val pfn = BitsN.bits(a,39,12) - in - ( let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i, - TLBEntry_VPN2_rupd - (x0,BitsN.fromNat(BitsN.toNat(BitsN.>>+(pfn,1)),27)))) - end - ; let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i,TLBEntry_R_rupd(x0,BitsN.B(0x0,2)))) - end - ; let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update((!TLB_assoc),BitsN.toNat i,TLBEntry_G_rupd(x0,true))) - end - ; if BitsN.bit(a,12) - then ( let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i,TLBEntry_PFN1_rupd(x0,pfn))) - end - ; let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i, - TLBEntry_C1_rupd(x0,BitsN.B(0x2,3)))) - end - ; let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i,TLBEntry_D1_rupd(x0,true))) - end - ; let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i,TLBEntry_V1_rupd(x0,true))) - end - ) - else ( let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i,TLBEntry_PFN0_rupd(x0,pfn))) - end - ; let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i, - TLBEntry_C0_rupd(x0,BitsN.B(0x2,3)))) - end - ; let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i,TLBEntry_D0_rupd(x0,true))) - end - ; let - val x0 = Map.lookup((!TLB_assoc),BitsN.toNat i) - in - TLB_assoc := - (Map.update - ((!TLB_assoc),BitsN.toNat i,TLBEntry_V0_rupd(x0,true))) - end - ) - ) - end; - -fun initMips (pc,uart) = - ( let - val x0 = (#Config) (!CP0) - in - CP0 := (CP0_Config_rupd((!CP0),ConfigRegister_M_rupd(x0,true))) - end - ; let - val x0 = (#Config) (!CP0) - in - CP0 := (CP0_Config_rupd((!CP0),ConfigRegister_BE_rupd(x0,true))) - end - ; let - val x0 = (#Config) (!CP0) - in - CP0 := - (CP0_Config_rupd((!CP0),ConfigRegister_MT_rupd(x0,BitsN.B(0x1,3)))) - end - ; let - val x0 = (#Config) (!CP0) - in - CP0 := - (CP0_Config_rupd((!CP0),ConfigRegister_AR_rupd(x0,BitsN.B(0x0,3)))) - end - ; let - val x0 = (#Config) (!CP0) - in - CP0 := - (CP0_Config_rupd((!CP0),ConfigRegister_AT_rupd(x0,BitsN.B(0x2,2)))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := (CP0_Config1_rupd((!CP0),ConfigRegister1_M_rupd(x0,true))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := - (CP0_Config1_rupd - ((!CP0),ConfigRegister1_MMUSize_rupd(x0,BitsN.B(0xF,6)))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := - (CP0_Config1_rupd((!CP0),ConfigRegister1_IS_rupd(x0,BitsN.B(0x3,3)))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := - (CP0_Config1_rupd((!CP0),ConfigRegister1_IL_rupd(x0,BitsN.B(0x4,3)))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := - (CP0_Config1_rupd((!CP0),ConfigRegister1_IA_rupd(x0,BitsN.B(0x0,3)))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := - (CP0_Config1_rupd((!CP0),ConfigRegister1_DS_rupd(x0,BitsN.B(0x3,3)))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := - (CP0_Config1_rupd((!CP0),ConfigRegister1_DL_rupd(x0,BitsN.B(0x4,3)))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := - (CP0_Config1_rupd((!CP0),ConfigRegister1_DA_rupd(x0,BitsN.B(0x0,3)))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := (CP0_Config1_rupd((!CP0),ConfigRegister1_C2_rupd(x0,false))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := (CP0_Config1_rupd((!CP0),ConfigRegister1_MD_rupd(x0,false))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := (CP0_Config1_rupd((!CP0),ConfigRegister1_PC_rupd(x0,false))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := (CP0_Config1_rupd((!CP0),ConfigRegister1_WR_rupd(x0,false))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := (CP0_Config1_rupd((!CP0),ConfigRegister1_CA_rupd(x0,false))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := (CP0_Config1_rupd((!CP0),ConfigRegister1_EP_rupd(x0,false))) - end - ; let - val x0 = (#Config1) (!CP0) - in - CP0 := (CP0_Config1_rupd((!CP0),ConfigRegister1_FP_rupd(x0,false))) - end - ; let - val x0 = (#Config2) (!CP0) - in - CP0 := (CP0_Config2_rupd((!CP0),ConfigRegister2_M_rupd(x0,true))) - end - ; let - val x0 = (#Config2) (!CP0) - in - CP0 := - (CP0_Config2_rupd((!CP0),ConfigRegister2_TU_rupd(x0,BitsN.B(0x0,3)))) - end - ; let - val x0 = (#Config2) (!CP0) - in - CP0 := - (CP0_Config2_rupd((!CP0),ConfigRegister2_TS_rupd(x0,BitsN.B(0x0,4)))) - end - ; let - val x0 = (#Config2) (!CP0) - in - CP0 := - (CP0_Config2_rupd((!CP0),ConfigRegister2_TL_rupd(x0,BitsN.B(0x0,4)))) - end - ; let - val x0 = (#Config2) (!CP0) - in - CP0 := - (CP0_Config2_rupd((!CP0),ConfigRegister2_TA_rupd(x0,BitsN.B(0x0,4)))) - end - ; let - val x0 = (#Config2) (!CP0) - in - CP0 := - (CP0_Config2_rupd((!CP0),ConfigRegister2_SU_rupd(x0,BitsN.B(0x3,4)))) - end - ; let - val x0 = (#Config2) (!CP0) - in - CP0 := - (CP0_Config2_rupd((!CP0),ConfigRegister2_SS_rupd(x0,BitsN.B(0x8,4)))) - end - ; let - val x0 = (#Config2) (!CP0) - in - CP0 := - (CP0_Config2_rupd((!CP0),ConfigRegister2_SL_rupd(x0,BitsN.B(0x4,4)))) - end - ; let - val x0 = (#Config2) (!CP0) - in - CP0 := - (CP0_Config2_rupd((!CP0),ConfigRegister2_SA_rupd(x0,BitsN.B(0x0,4)))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := (CP0_Config3_rupd((!CP0),ConfigRegister3_M_rupd(x0,true))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := (CP0_Config3_rupd((!CP0),ConfigRegister3_ULRI_rupd(x0,true))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := - (CP0_Config3_rupd((!CP0),ConfigRegister3_DSPP_rupd(x0,false))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := (CP0_Config3_rupd((!CP0),ConfigRegister3_LPA_rupd(x0,false))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := - (CP0_Config3_rupd((!CP0),ConfigRegister3_VEIC_rupd(x0,false))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := - (CP0_Config3_rupd((!CP0),ConfigRegister3_VInt_rupd(x0,false))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := (CP0_Config3_rupd((!CP0),ConfigRegister3_SP_rupd(x0,false))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := (CP0_Config3_rupd((!CP0),ConfigRegister3_MT_rupd(x0,false))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := (CP0_Config3_rupd((!CP0),ConfigRegister3_SM_rupd(x0,false))) - end - ; let - val x0 = (#Config3) (!CP0) - in - CP0 := (CP0_Config3_rupd((!CP0),ConfigRegister3_TL_rupd(x0,false))) - end - ; let - val x0 = (#Config6) (!CP0) - in - CP0 := - (CP0_Config6_rupd - ((!CP0),ConfigRegister6_TLBSize_rupd(x0,BitsN.B(0x8F,16)))) - end - ; let - val x0 = (#Config6) (!CP0) - in - CP0 := - (CP0_Config6_rupd((!CP0),ConfigRegister6_LTLB_rupd(x0,false))) - end - ; let - val x0 = (#Status) (!CP0) - in - CP0 := - (CP0_Status_rupd - ((!CP0),write'reg'StatusRegister(x0,BitsN.B(0x0,32)))) - end - ; let - val x0 = (#Status) (!CP0) - in - CP0 := (CP0_Status_rupd((!CP0),StatusRegister_BEV_rupd(x0,true))) - end - ; let - val x0 = (#Status) (!CP0) - in - CP0 := - (CP0_Status_rupd((!CP0),StatusRegister_KSU_rupd(x0,BitsN.B(0x0,2)))) - end - ; let - val x0 = (#Status) (!CP0) - in - CP0 := (CP0_Status_rupd((!CP0),StatusRegister_EXL_rupd(x0,false))) - end - ; let - val x0 = (#Status) (!CP0) - in - CP0 := (CP0_Status_rupd((!CP0),StatusRegister_ERL_rupd(x0,false))) - end - ; let - val x0 = (#Status) (!CP0) - in - CP0 := (CP0_Status_rupd((!CP0),StatusRegister_KX_rupd(x0,true))) - end - ; let - val x0 = (#Status) (!CP0) - in - CP0 := (CP0_Status_rupd((!CP0),StatusRegister_SX_rupd(x0,true))) - end - ; let - val x0 = (#Status) (!CP0) - in - CP0 := (CP0_Status_rupd((!CP0),StatusRegister_UX_rupd(x0,true))) - end - ; CP0 := (CP0_Count_rupd((!CP0),BitsN.B(0x0,32))) - ; CP0 := (CP0_Compare_rupd((!CP0),BitsN.B(0x0,32))) - ; CP0 := (CP0_PRId_rupd((!CP0),BitsN.B(0x400,32))) - ; let - val x0 = (#Index) (!CP0) - in - CP0 := (CP0_Index_rupd((!CP0),Index_P_rupd(x0,false))) - end - ; let - val x0 = (#Index) (!CP0) - in - CP0 := (CP0_Index_rupd((!CP0),Index_Index_rupd(x0,BitsN.B(0x0,8)))) - end - ; let - val x0 = (#Random) (!CP0) - in - CP0 := - (CP0_Random_rupd - ((!CP0), - Random_Random_rupd(x0,BitsN.fromNat(Nat.-(TLBEntries,1),8)))) - end - ; let - val x0 = (#Wired) (!CP0) - in - CP0 := (CP0_Wired_rupd((!CP0),Wired_Wired_rupd(x0,BitsN.B(0x0,8)))) - end - ; let - val x0 = (#HWREna) (!CP0) - in - CP0 := - (CP0_HWREna_rupd((!CP0),write'reg'HWREna(x0,BitsN.B(0x0,32)))) + (CP0_Status_rupd((!CP0),StatusRegister_EXL_rupd(x0,true))) + end + ; let + val vectorBase = + if (#BEV)((#Status) (!CP0)) + then BitsN.B(0xFFFFFFFFBFC00200,64) + else BitsN.B(0xFFFFFFFF80000000,64) + in + ( BranchDelay := NONE + ; BranchTo := + (Option.SOME + (true, + BitsN.@@ + (BitsN.bits(vectorBase,63,30), + BitsN.+(BitsN.bits(vectorBase,29,0),vectorOffset)))) + ; exceptionSignalled := true + ) + end + ) end - ; TLB_assoc := (Map.mkMap(SOME 16,initTLB ())) - ; BranchDelay := NONE - ; BranchTo := NONE - ; LLbit := NONE - ; hi := NONE - ; lo := NONE - ; PC := (BitsN.fromNat(pc,64)) - ; MEM := (Map.mkMap(SOME 137438953472,BitsN.B(0x0,64))) - ; gpr := (Map.mkMap(SOME 32,BitsN.B(0xAAAAAAAAAAAAAAAA,64))) - ; JTAG_UART_initialise uart - ; PIC_initialise 2139111424 ); -fun done () = - case (!log) of [w_c0(BitsN.B(0x17,5),_)] => true | _ => false; +val BYTE = BitsN.B(0x0,3) + +val HALFWORD = BitsN.B(0x1,3) + +val WORD = BitsN.B(0x3,3) + +val DOUBLEWORD = BitsN.B(0x7,3) + +fun UserMode () = + (((#KSU)((#Status) (!CP0))) = (BitsN.B(0x2,2))) andalso + (not(((#EXL)((#Status) (!CP0))) orelse ((#ERL)((#Status) (!CP0))))); + +fun SupervisorMode () = + (((#KSU)((#Status) (!CP0))) = (BitsN.B(0x1,2))) andalso + (not(((#EXL)((#Status) (!CP0))) orelse ((#ERL)((#Status) (!CP0))))); + +fun KernelMode () = + ((((#KSU)((#Status) (!CP0))) = (BitsN.B(0x0,2))) orelse + ((#EXL)((#Status) (!CP0)))) orelse ((#ERL)((#Status) (!CP0))); + +fun BigEndianMem () = (#BE)((#Config) (!CP0)); + +fun ReverseEndian () = + BitsN.fromBit(((#RE)((#Status) (!CP0))) andalso (UserMode ())); + +fun BigEndianCPU () = + BitsN.??(BitsN.fromBit(BigEndianMem ()),ReverseEndian ()); + +fun GPR n = + if n = (BitsN.B(0x0,5)) + then BitsN.B(0x0,64) + else Map.lookup((!gpr),BitsN.toNat n); + +fun write'GPR (value,n) = + if not(n = (BitsN.B(0x0,5))) + then gpr := (Map.update((!gpr),BitsN.toNat n,value)) + else (); + +fun HI () = + case (!hi) of Option.SOME v => v | NONE => raise UNPREDICTABLE ("HI"); + +fun write'HI value = hi := (Option.SOME value); + +fun LO () = + case (!lo) of Option.SOME v => v | NONE => raise UNPREDICTABLE ("LO"); + +fun write'LO value = lo := (Option.SOME value); + +fun CPR (n,(reg,sel)) = + case (n,(reg,sel)) of + (0,(BitsN.B(0x8,5),BitsN.B(0x0,3))) => (#BadVAddr) (!CP0) + | (0,(BitsN.B(0x9,5),BitsN.B(0x0,3))) => + BitsN.fromNat(BitsN.toNat((#Count) (!CP0)),64) + | (0,(BitsN.B(0xB,5),BitsN.B(0x0,3))) => + BitsN.fromNat(BitsN.toNat((#Compare) (!CP0)),64) + | (0,(BitsN.B(0xC,5),BitsN.B(0x0,3))) => + BitsN.fromNat + (BitsN.toNat(reg'StatusRegister((#Status) (!CP0))),64) + | (0,(BitsN.B(0xD,5),BitsN.B(0x0,3))) => + BitsN.fromNat(BitsN.toNat(reg'CauseRegister((#Cause) (!CP0))),64) + | (0,(BitsN.B(0xE,5),BitsN.B(0x0,3))) => (#EPC) (!CP0) + | (0,(BitsN.B(0xF,5),BitsN.B(0x0,3))) => + BitsN.fromNat(BitsN.toNat((#PRId) (!CP0)),64) + | (0,(BitsN.B(0x10,5),BitsN.B(0x0,3))) => + BitsN.fromNat + (BitsN.toNat(reg'ConfigRegister((#Config) (!CP0))),64) + | (0,(BitsN.B(0x11,5),BitsN.B(0x0,3))) => + BitsN.fromNat(BitsN.toNat((#LLAddr) (!CP0)),64) + | (0,(BitsN.B(0x17,5),BitsN.B(0x0,3))) => + BitsN.fromNat(BitsN.toNat((#Debug) (!CP0)),64) + | (0,(BitsN.B(0x1A,5),BitsN.B(0x0,3))) => + BitsN.fromNat(BitsN.toNat((#ErrCtl) (!CP0)),64) + | (0,(BitsN.B(0x1E,5),BitsN.B(0x0,3))) => (#ErrorEPC) (!CP0) + | _ => BitsN.B(0x0,64); + +fun write'CPR (value,(n,(reg,sel))) = + case (n,(reg,sel)) of + (0,(BitsN.B(0x9,5),BitsN.B(0x0,3))) => + CP0 := (CP0_Count_rupd((!CP0),BitsN.bits(value,31,0))) + | (0,(BitsN.B(0xB,5),BitsN.B(0x0,3))) => + CP0 := (CP0_Compare_rupd((!CP0),BitsN.bits(value,31,0))) + | (0,(BitsN.B(0xC,5),BitsN.B(0x0,3))) => + let + val x0 = (#Status) (!CP0) + in + CP0 := + (CP0_Status_rupd + ((!CP0),write'reg'StatusRegister(x0,BitsN.bits(value,31,0)))) + end + | (0,(BitsN.B(0xD,5),BitsN.B(0x0,3))) => + let + val x0 = (#Cause) (!CP0) + in + CP0 := + (CP0_Cause_rupd + ((!CP0),write'reg'CauseRegister(x0,BitsN.bits(value,31,0)))) + end + | (0,(BitsN.B(0xE,5),BitsN.B(0x0,3))) => + CP0 := (CP0_EPC_rupd((!CP0),value)) + | (0,(BitsN.B(0x10,5),BitsN.B(0x0,3))) => + let + val x0 = (#Config) (!CP0) + in + CP0 := + (CP0_Config_rupd + ((!CP0),write'reg'ConfigRegister(x0,BitsN.bits(value,31,0)))) + end + | (0,(BitsN.B(0x17,5),BitsN.B(0x0,3))) => + CP0 := (CP0_Debug_rupd((!CP0),BitsN.bits(value,31,0))) + | (0,(BitsN.B(0x1A,5),BitsN.B(0x0,3))) => + CP0 := (CP0_ErrCtl_rupd((!CP0),BitsN.bits(value,31,0))) + | (0,(BitsN.B(0x1E,5),BitsN.B(0x0,3))) => + CP0 := (CP0_ErrorEPC_rupd((!CP0),value)) + | _ => (); + +val PSIZE = 64 + +fun AddressTranslation (vAddr,(IorD,LorS)) = (vAddr,BitsN.B(0x2,3)); + +fun LoadMemory (CCA,(AccessLength,(pAddr,(vAddr,IorD)))) = + let + val a = BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,64))) + in + if BigEndianMem () + then BitsN.concat + [Map.lookup((!MEM),BitsN.toNat a), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x1,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x2,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x3,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x4,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x5,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x6,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x7,64))))] + else BitsN.concat + [Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x7,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x6,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x5,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x4,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x3,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x2,64)))), + Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x1,64)))), + Map.lookup((!MEM),BitsN.toNat a)] + end; + +fun StoreMemory (CCA,(AccessLength,(MemElem,(pAddr,(vAddr,IorD))))) = + let + val a = BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,64))) + val l = BitsN.bits(pAddr,2,0) + val h = BitsN.+(l,AccessLength) + in + if BigEndianMem () + then ( if l = (BitsN.B(0x0,3)) + then MEM := + (Map.update + ((!MEM),BitsN.toNat a,BitsN.bits(MemElem,63,56))) + else () + ; if (BitsN.<=+(l,BitsN.B(0x1,3))) andalso + (BitsN.<=+(BitsN.B(0x1,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x1,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,55,48))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x2,3))) andalso + (BitsN.<=+(BitsN.B(0x2,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x2,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,47,40))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x3,3))) andalso + (BitsN.<=+(BitsN.B(0x3,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x3,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,39,32))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x4,3))) andalso + (BitsN.<=+(BitsN.B(0x4,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x4,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,31,24))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x5,3))) andalso + (BitsN.<=+(BitsN.B(0x5,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x5,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,23,16))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x6,3))) andalso + (BitsN.<=+(BitsN.B(0x6,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x6,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,15,8))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x7,3))) andalso + (BitsN.<=+(BitsN.B(0x7,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x7,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,7,0))) + end + else () + ) + else ( if (BitsN.<=+(l,BitsN.B(0x7,3))) andalso + (BitsN.<=+(BitsN.B(0x7,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x7,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,63,56))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x6,3))) andalso + (BitsN.<=+(BitsN.B(0x6,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x6,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,55,48))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x5,3))) andalso + (BitsN.<=+(BitsN.B(0x5,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x5,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,47,40))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x4,3))) andalso + (BitsN.<=+(BitsN.B(0x4,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x4,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,39,32))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x3,3))) andalso + (BitsN.<=+(BitsN.B(0x3,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x3,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,31,24))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x2,3))) andalso + (BitsN.<=+(BitsN.B(0x2,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x2,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,23,16))) + end + else () + ; if (BitsN.<=+(l,BitsN.B(0x1,3))) andalso + (BitsN.<=+(BitsN.B(0x1,3),h)) + then let + val x = BitsN.+(a,BitsN.B(0x1,64)) + in + MEM := + (Map.update + ((!MEM),BitsN.toNat x,BitsN.bits(MemElem,15,8))) + end + else () + ; if l = (BitsN.B(0x0,3)) + then MEM := + (Map.update + ((!MEM),BitsN.toNat a,BitsN.bits(MemElem,7,0))) + else () + ) + end; + +fun Fetch () = + if (BitsN.bits((!PC),1,0)) = (BitsN.B(0x0,2)) + then let + val vAddr = (!PC) + val (pAddr,CCA) = AddressTranslation(vAddr,(INSTRUCTION,LOAD)) + val memdoubleword = + LoadMemory(CCA,(WORD,(pAddr,(vAddr,INSTRUCTION)))) + val bytesel = + BitsN.?? + (BitsN.bits(vAddr,2,0), + BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) + val memword = + BitsN.bits + (memdoubleword,Nat.+(31,Nat.*(8,BitsN.toNat bytesel)), + Nat.*(8,BitsN.toNat bytesel)) + in + Option.SOME memword + end + else ( SignalException AdEL; NONE ); fun NotWordValue value = let @@ -5433,11 +3232,6 @@ fun NotWordValue value = else not(top = (BitsN.B(0x0,32))) end; -fun CheckBranch () = - if Option.isSome (!BranchDelay) - then raise UNPREDICTABLE ("Not permitted in delay slot") - else (); - fun dfn'ADDI (rs,(rt,immediate)) = ( if NotWordValue(GPR rs) then raise UNPREDICTABLE ("ADDI: NotWordValue") @@ -6135,7 +3929,7 @@ fun dfn'LWL (base,(rt,offset)) = val pAddr = if BigEndianMem () then pAddr - else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,40))) + else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,64))) val byte = BitsN.?? (BitsN.bits(vAddr,1,0), @@ -6196,7 +3990,7 @@ fun dfn'LWR (base,(rt,offset)) = val pAddr = if BigEndianMem () then pAddr - else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,40))) + else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,64))) val byte = BitsN.?? (BitsN.bits(vAddr,1,0), @@ -6259,7 +4053,7 @@ fun dfn'LDL (base,(rt,offset)) = val pAddr = if BigEndianMem () then pAddr - else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,40))) + else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,64))) val byte = BitsN.?? (BitsN.bits(vAddr,2,0), @@ -6321,7 +4115,7 @@ fun dfn'LDR (base,(rt,offset)) = val pAddr = if BigEndianMem () then pAddr - else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,40))) + else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,64))) val byte = BitsN.?? (BitsN.bits(vAddr,2,0), @@ -6530,7 +4324,7 @@ fun dfn'SWL (base,(rt,offset)) = val pAddr = if BigEndianMem () then pAddr - else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x3,40))) + else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x3,64))) val byte = BitsN.?? (BitsN.bits(vAddr,1,0), @@ -6579,7 +4373,7 @@ fun dfn'SWR (base,(rt,offset)) = BitsN.resize_replicate 3 (ReverseEndian (),3))) val pAddr = if BigEndianMem () - then BitsN.&&(pAddr,BitsN.~(BitsN.B(0x3,40))) + then BitsN.&&(pAddr,BitsN.~(BitsN.B(0x3,64))) else pAddr val byte = BitsN.?? @@ -6644,7 +4438,7 @@ fun dfn'SDL (base,(rt,offset)) = val pAddr = if BigEndianMem () then pAddr - else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,40))) + else BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,64))) val byte = BitsN.?? (BitsN.bits(vAddr,2,0), @@ -6695,7 +4489,7 @@ fun dfn'SDR (base,(rt,offset)) = BitsN.resize_replicate 3 (ReverseEndian (),3))) val pAddr = if BigEndianMem () - then BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,40))) + then BitsN.&&(pAddr,BitsN.~(BitsN.B(0x7,64))) else pAddr val byte = BitsN.?? @@ -6749,31 +4543,33 @@ fun dfn'BREAK () = SignalException Bp; fun dfn'SYSCALL () = SignalException Sys; fun dfn'ERET () = - ( CheckBranch () - ; if ((#CU0)((#Status) (!CP0))) orelse (KernelMode ()) - then ( if (#ERL)((#Status) (!CP0)) - then ( PC := (BitsN.-((#ErrorEPC) (!CP0),BitsN.B(0x4,64))) - ; let - val x0 = (#Status) (!CP0) - in - CP0 := - (CP0_Status_rupd - ((!CP0),StatusRegister_ERL_rupd(x0,false))) - end - ) - else ( PC := (BitsN.-((#EPC) (!CP0),BitsN.B(0x4,64))) + if ((#CU0)((#Status) (!CP0))) orelse (KernelMode ()) + then ( if (#ERL)((#Status) (!CP0)) + then ( BranchTo := + (Option.SOME + (true,BitsN.-((#ErrorEPC) (!CP0),BitsN.B(0x4,64)))) ; let val x0 = (#Status) (!CP0) in CP0 := (CP0_Status_rupd - ((!CP0),StatusRegister_EXL_rupd(x0,false))) + ((!CP0),StatusRegister_ERL_rupd(x0,false))) end ) - ; LLbit := (Option.SOME false) - ) - else SignalException CpU - ); + else ( BranchTo := + (Option.SOME + (true,BitsN.-((#EPC) (!CP0),BitsN.B(0x4,64)))) + ; let + val x0 = (#Status) (!CP0) + in + CP0 := + (CP0_Status_rupd + ((!CP0),StatusRegister_EXL_rupd(x0,false))) + end + ) + ; LLbit := (Option.SOME false) + ) + else SignalException CpU; fun dfn'MTC0 (rt,(rd,sel)) = if ((#CU0)((#Status) (!CP0))) orelse (KernelMode ()) @@ -6799,92 +4595,74 @@ fun dfn'DMFC0 (rt,(rd,sel)) = fun dfn'J instr_index = BranchTo := (Option.SOME - (BitsN.concat[BitsN.bits((!PC),63,28),instr_index,BitsN.B(0x0,2)])); + (false, + BitsN.concat[BitsN.bits((!PC),63,28),instr_index,BitsN.B(0x0,2)])); fun dfn'JAL instr_index = ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) ; BranchTo := (Option.SOME - (BitsN.concat[BitsN.bits((!PC),63,28),instr_index,BitsN.B(0x0,2)])) + (false, + BitsN.concat[BitsN.bits((!PC),63,28),instr_index,BitsN.B(0x0,2)])) ); -fun dfn'JR rs = BranchTo := (Option.SOME(GPR rs)); +fun dfn'JR rs = BranchTo := (Option.SOME(false,GPR rs)); fun dfn'JALR (rs,rd) = let val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),rd) - ; BranchTo := (Option.SOME temp) + ; BranchTo := (Option.SOME(false,temp)) ) end; -fun dfn'BEQ (rs,(rt,offset)) = - if (GPR rs) = (GPR rt) +fun ConditionalBranch (b,offset) = + BranchTo := + (Option.SOME + (if b + then (false, + BitsN.+ + (BitsN.+((!PC),BitsN.B(0x4,64)), + BitsN.<<(BitsN.signExtend 64 offset,2))) + else (true,BitsN.+((!PC),BitsN.B(0x4,64))))); + +fun ConditionalBranchLikely (b,offset) = + if b then BranchTo := (Option.SOME - (BitsN.+ + (false, + BitsN.+ (BitsN.+((!PC),BitsN.B(0x4,64)), BitsN.<<(BitsN.signExtend 64 offset,2)))) - else CheckBranch (); + else if Option.isSome (!BranchDelay) + then BranchTo := (Option.SOME(true,BitsN.+((!PC),BitsN.B(0x8,64)))) + else PC := (BitsN.+((!PC),BitsN.B(0x4,64))); + +fun dfn'BEQ (rs,(rt,offset)) = + ConditionalBranch((GPR rs) = (GPR rt),offset); fun dfn'BNE (rs,(rt,offset)) = - if not((GPR rs) = (GPR rt)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else CheckBranch (); + ConditionalBranch(not((GPR rs) = (GPR rt)),offset); fun dfn'BLEZ (rs,offset) = - if BitsN.<=(GPR rs,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else CheckBranch (); + ConditionalBranch(BitsN.<=(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BGTZ (rs,offset) = - if BitsN.>(GPR rs,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else CheckBranch (); + ConditionalBranch(BitsN.>(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BLTZ (rs,offset) = - if BitsN.<(GPR rs,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else CheckBranch (); + ConditionalBranch(BitsN.<(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BGEZ (rs,offset) = - if BitsN.>=(GPR rs,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else CheckBranch (); + ConditionalBranch(BitsN.>=(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BLTZAL (rs,offset) = let val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) - ; if BitsN.<(temp,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else CheckBranch () + ; ConditionalBranch(BitsN.<(temp,BitsN.B(0x0,64)),offset) ) end; @@ -6893,82 +4671,34 @@ fun dfn'BGEZAL (rs,offset) = val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) - ; if BitsN.>=(temp,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else CheckBranch () + ; ConditionalBranch(BitsN.>=(temp,BitsN.B(0x0,64)),offset) ) end; fun dfn'BEQL (rs,(rt,offset)) = - if (GPR rs) = (GPR rt) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else ( CheckBranch (); PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ); + ConditionalBranchLikely((GPR rs) = (GPR rt),offset); fun dfn'BNEL (rs,(rt,offset)) = - if not((GPR rs) = (GPR rt)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else ( CheckBranch (); PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ); + ConditionalBranchLikely(not((GPR rs) = (GPR rt)),offset); fun dfn'BLEZL (rs,offset) = - if BitsN.<=(GPR rs,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else ( CheckBranch (); PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ); + ConditionalBranchLikely(BitsN.<=(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BGTZL (rs,offset) = - if BitsN.>(GPR rs,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else ( CheckBranch (); PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ); + ConditionalBranchLikely(BitsN.>(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BLTZL (rs,offset) = - if BitsN.<(GPR rs,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else ( CheckBranch (); PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ); + ConditionalBranchLikely(BitsN.<(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BGEZL (rs,offset) = - if BitsN.>=(GPR rs,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else ( CheckBranch (); PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ); + ConditionalBranchLikely(BitsN.>=(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BLTZALL (rs,offset) = let val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) - ; if BitsN.<(temp,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else ( CheckBranch (); PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ) + ; ConditionalBranchLikely(BitsN.<(temp,BitsN.B(0x0,64)),offset) ) end; @@ -6977,18 +4707,24 @@ fun dfn'BGEZALL (rs,offset) = val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) - ; if BitsN.>=(temp,BitsN.B(0x0,64)) - then BranchTo := - (Option.SOME - (BitsN.+ - (BitsN.+((!PC),BitsN.B(0x4,64)), - BitsN.<<(BitsN.signExtend 64 offset,2)))) - else ( CheckBranch (); PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ) + ; ConditionalBranchLikely(BitsN.>=(temp,BitsN.B(0x0,64)),offset) ) end; val dfn'WAIT = () +fun dfn'TLBP () = SignalException ResI; + +fun dfn'TLBR () = SignalException ResI; + +fun dfn'TLBWI () = SignalException ResI; + +fun dfn'TLBWR () = SignalException ResI; + +fun dfn'CACHE (base,(opn,offset)) = SignalException ResI; + +fun dfn'RDHWR (rt,rd) = SignalException ResI; + fun dfn'ReservedInstruction () = SignalException ResI; fun dfn'Unpredictable () = @@ -11553,16 +9289,21 @@ fun Decode w = fun Next () = ( case Fetch () of Option.SOME w => Run(Decode w) | NONE => () ; case ((!BranchDelay),(!BranchTo)) of - (NONE,NONE) => - if not (!exceptionSignalled) - then PC := (BitsN.+((!PC),BitsN.B(0x4,64))) - else () - | (Option.SOME addr,NONE) => ( BranchDelay := NONE; PC := addr ) - | (NONE,Option.SOME addr) => - ( BranchDelay := (Option.SOME addr) + (NONE,NONE) => PC := (BitsN.+((!PC),BitsN.B(0x4,64))) + | (NONE,Option.SOME(true,addr)) => + ( BranchDelay := (Option.SOME NONE) + ; BranchTo := NONE + ; PC := addr + ) + | (NONE,Option.SOME(false,addr)) => + ( BranchDelay := (Option.SOME(Option.SOME addr)) ; BranchTo := NONE ; PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ) + | (Option.SOME NONE,NONE) => + ( BranchDelay := NONE; PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ) + | (Option.SOME(Option.SOME addr),NONE) => + ( BranchDelay := NONE; PC := addr ) | _ => raise UNPREDICTABLE ("Branch follows branch") ; exceptionSignalled := false ; CP0 := diff --git a/examples/l3-machine-code/mips/model/mipsScript.sml b/examples/l3-machine-code/mips/model/mipsScript.sml index a3d404a1ec..6f15881594 100644 --- a/examples/l3-machine-code/mips/model/mipsScript.sml +++ b/examples/l3-machine-code/mips/model/mipsScript.sml @@ -1,4 +1,4 @@ -(* mipsScript.sml - generated by L<3> - Wed Sep 17 11:16:47 2014 *) +(* mipsScript.sml - generated by L<3> - Thu Oct 30 16:32:12 2014 *) open HolKernel boolLib bossLib Import val () = Import.start "mips" @@ -226,8 +226,8 @@ val _ = Construct ; val _ = Record ("mips_state", - [("BranchDelay",OTy F64),("BranchTo",OTy F64),("CP0",CTy"CP0"), - ("LLbit",OTy bTy),("MEM",ATy(F64,F8)),("PC",F64), + [("BranchDelay",OTy(OTy F64)),("BranchTo",OTy(PTy(bTy,F64))), + ("CP0",CTy"CP0"),("LLbit",OTy bTy),("MEM",ATy(F64,F8)),("PC",F64), ("exception",CTy"exception"),("exceptionSignalled",bTy), ("gpr",ATy(FTy 5,F64)),("hi",OTy F64),("lo",OTy F64)]) ; @@ -1683,48 +1683,50 @@ val SignalException_def = Def Dest ("Status",CTy"StatusRegister", Dest("CP0",CTy"CP0",qVar"state")))), - ITE(Mop(IsSome,Dest("BranchDelay",OTy F64,qVar"state")), - Let(qVar"s", - Rupd - ("CP0", - TP[qVar"state", - Rupd - ("EPC", - TP[Dest("CP0",CTy"CP0",qVar"state"), - Bop(Sub,Dest("PC",F64,qVar"state"), - LW(4,64))])]), - Rupd - ("CP0", - TP[qVar"s", - Rupd - ("Cause", - TP[Dest("CP0",CTy"CP0",qVar"s"), - Rupd - ("BD", - TP[Dest - ("Cause",CTy"CauseRegister", - Dest("CP0",CTy"CP0",qVar"s")), - LT])])])), - Let(qVar"s", - Rupd - ("CP0", - TP[qVar"state", - Rupd - ("EPC", - TP[Dest("CP0",CTy"CP0",qVar"state"), - Dest("PC",F64,qVar"state")])]), - Rupd - ("CP0", - TP[qVar"s", - Rupd - ("Cause", - TP[Dest("CP0",CTy"CP0",qVar"s"), - Rupd - ("BD", - TP[Dest - ("Cause",CTy"CauseRegister", - Dest("CP0",CTy"CP0",qVar"s")), - LF])])]))),qVar"state"), + CS(Dest("BranchDelay",OTy(OTy F64),qVar"state"), + [(Mop(Some,Mop(Some,AVar F64)), + Let(qVar"s", + Rupd + ("CP0", + TP[qVar"state", + Rupd + ("EPC", + TP[Dest("CP0",CTy"CP0",qVar"state"), + Bop(Sub,Dest("PC",F64,qVar"state"), + LW(4,64))])]), + Rupd + ("CP0", + TP[qVar"s", + Rupd + ("Cause", + TP[Dest("CP0",CTy"CP0",qVar"s"), + Rupd + ("BD", + TP[Dest + ("Cause",CTy"CauseRegister", + Dest("CP0",CTy"CP0",qVar"s")), + LT])])]))), + (AVar(OTy(OTy F64)), + Let(qVar"s", + Rupd + ("CP0", + TP[qVar"state", + Rupd + ("EPC", + TP[Dest("CP0",CTy"CP0",qVar"state"), + Dest("PC",F64,qVar"state")])]), + Rupd + ("CP0", + TP[qVar"s", + Rupd + ("Cause", + TP[Dest("CP0",CTy"CP0",qVar"s"), + Rupd + ("BD", + TP[Dest + ("Cause",CTy"CauseRegister", + Dest("CP0",CTy"CP0",qVar"s")), + LF])])])))]),qVar"state"), Let(qVar"s0", Mop(Snd, Apply @@ -1757,37 +1759,36 @@ val SignalException_def = Def TP[Rupd ("PC", TP[Rupd - ("BranchTo", - TP[Rupd - ("BranchDelay", - TP[qVar"s0",LO F64]),LO F64]), - CC[EX(Var("v0",F64),LN 63,LN 30, - FTy 34), - Bop(Add, - EX(Var("v0",F64),LN 29,LN 0, - FTy 30), - ITE(Bop(And, - Bop(Or, - EQ(Var("ExceptionType", - CTy"ExceptionType"), - LC("XTLBRefillL", - CTy"ExceptionType")), - EQ(Var("ExceptionType", - CTy"ExceptionType"), - LC("XTLBRefillS", - CTy"ExceptionType"))), - Mop(Not, - Dest - ("EXL",bTy, - Dest - ("Status", - CTy"StatusRegister", - Dest - ("CP0", - CTy"CP0", - qVar"s"))))), - LW(128,30),LW(384,30)))]]), - LT])])))))) + ("BranchDelay", + TP[qVar"s0",LO(OTy F64)]), + Bop(Sub, + CC[EX(Var("v0",F64),LN 63,LN 30, + FTy 34), + Bop(Add, + EX(Var("v0",F64),LN 29, + LN 0,FTy 30), + ITE(Bop(And, + Bop(Or, + EQ(Var("ExceptionType", + CTy"ExceptionType"), + LC("XTLBRefillL", + CTy"ExceptionType")), + EQ(Var("ExceptionType", + CTy"ExceptionType"), + LC("XTLBRefillS", + CTy"ExceptionType"))), + Mop(Not, + Dest + ("EXL",bTy, + Dest + ("Status", + CTy"StatusRegister", + Dest + ("CP0", + CTy"CP0", + qVar"s"))))), + LW(128,30),LW(384,30)))], + LW(4,64))]),LT])])))))) ; val BYTE_def = Def0 ("BYTE",LW(0,3)) ; @@ -2535,52 +2536,6 @@ val Fetch_def = Def ("SignalException",ATy(qTy,PTy(uTy,qTy)), LC("AdEL",CTy"ExceptionType")),qVar"state"))])) ; -val dfn'TLBP_def = Def - ("dfn'TLBP",qVar"state", - Apply - (Call - ("SignalException",ATy(qTy,PTy(uTy,qTy)), - LC("ResI",CTy"ExceptionType")),qVar"state")) -; -val dfn'TLBR_def = Def - ("dfn'TLBR",qVar"state", - Apply - (Call - ("SignalException",ATy(qTy,PTy(uTy,qTy)), - LC("ResI",CTy"ExceptionType")),qVar"state")) -; -val dfn'TLBWI_def = Def - ("dfn'TLBWI",qVar"state", - Apply - (Call - ("SignalException",ATy(qTy,PTy(uTy,qTy)), - LC("ResI",CTy"ExceptionType")),qVar"state")) -; -val dfn'TLBWR_def = Def - ("dfn'TLBWR",qVar"state", - Apply - (Call - ("SignalException",ATy(qTy,PTy(uTy,qTy)), - LC("ResI",CTy"ExceptionType")),qVar"state")) -; -val dfn'CACHE_def = Def - ("dfn'CACHE",TP[Var("base",FTy 5),Var("opn",FTy 5),Var("offset",F16)], - Close - (qVar"state", - Apply - (Call - ("SignalException",ATy(qTy,PTy(uTy,qTy)), - LC("ResI",CTy"ExceptionType")),qVar"state"))) -; -val dfn'RDHWR_def = Def - ("dfn'RDHWR",TP[Var("rt",FTy 5),Var("rd",FTy 5)], - Close - (qVar"state", - Apply - (Call - ("SignalException",ATy(qTy,PTy(uTy,qTy)), - LC("ResI",CTy"ExceptionType")),qVar"state"))) -; val NotWordValue_def = Def ("NotWordValue",Var("value",F64), Let(Var("top",F32),EX(Var("value",F64),LN 63,LN 32,F32), @@ -2588,17 +2543,6 @@ val NotWordValue_def = Def Mop(Not,EQ(Var("top",F32),LW(4294967295,32))), Mop(Not,EQ(Var("top",F32),LW(0,32)))))) ; -val CheckBranch_def = Def - ("CheckBranch",qVar"state", - ITE(Mop(IsSome,Dest("BranchDelay",OTy F64,qVar"state")), - Apply - (Call - ("raise'exception",ATy(qTy,PTy(uTy,qTy)), - Call - ("UNPREDICTABLE",CTy"exception", - LS"Not permitted in delay slot")),qVar"state"), - TP[LU,qVar"state"])) -; val dfn'ADDI_def = Def ("dfn'ADDI",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], Close @@ -6436,76 +6380,80 @@ val dfn'SYSCALL_def = Def ; val dfn'ERET_def = Def ("dfn'ERET",qVar"state", - Let(qVar"s", - Mop(Snd, - Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")), - ITE(Bop(Or, - Dest - ("CU0",bTy, - Dest - ("Status",CTy"StatusRegister", - Dest("CP0",CTy"CP0",qVar"s"))), - Mop(Fst, - Apply - (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))),qVar"s"))), - TP[LU, - Rupd - ("LLbit", - TP[ITE(Dest - ("ERL",bTy, - Dest - ("Status",CTy"StatusRegister", - Dest("CP0",CTy"CP0",qVar"s"))), - Let(qVar"s", - Rupd - ("PC", - TP[qVar"s", - Bop(Sub, - Dest - ("ErrorEPC",F64, - Dest("CP0",CTy"CP0",qVar"s")), - LW(4,64))]), - Rupd - ("CP0", - TP[qVar"s", - Rupd - ("Status", - TP[Dest("CP0",CTy"CP0",qVar"s"), - Rupd - ("ERL", - TP[Dest - ("Status", - CTy"StatusRegister", - Dest - ("CP0",CTy"CP0",qVar"s")), - LF])])])), - Let(qVar"s", - Rupd - ("PC", - TP[qVar"s", - Bop(Sub, - Dest - ("EPC",F64, - Dest("CP0",CTy"CP0",qVar"s")), - LW(4,64))]), - Rupd - ("CP0", - TP[qVar"s", - Rupd - ("Status", - TP[Dest("CP0",CTy"CP0",qVar"s"), - Rupd - ("EXL", - TP[Dest - ("Status", - CTy"StatusRegister", - Dest - ("CP0",CTy"CP0",qVar"s")), - LF])])]))),Mop(Some,LF)])], - Apply - (Call - ("SignalException",ATy(qTy,PTy(uTy,qTy)), - LC("CpU",CTy"ExceptionType")),qVar"s")))) + ITB([(Mop(IsSome,Dest("BranchDelay",OTy(OTy F64),qVar"state")), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception",LS"ERET follows branch")), + qVar"state")), + (Bop(Or, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Dest("CP0",CTy"CP0",qVar"state"))), + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))),qVar"state"))), + TP[LU, + Rupd + ("LLbit", + TP[ITE(Dest + ("ERL",bTy, + Dest + ("Status",CTy"StatusRegister", + Dest("CP0",CTy"CP0",qVar"state"))), + Let(qVar"s", + Rupd + ("PC", + TP[qVar"state", + Bop(Sub, + Dest + ("ErrorEPC",F64, + Dest("CP0",CTy"CP0",qVar"state")), + LW(4,64))]), + Rupd + ("CP0", + TP[qVar"s", + Rupd + ("Status", + TP[Dest("CP0",CTy"CP0",qVar"s"), + Rupd + ("ERL", + TP[Dest + ("Status", + CTy"StatusRegister", + Dest + ("CP0",CTy"CP0",qVar"s")), + LF])])])), + Let(qVar"s", + Rupd + ("PC", + TP[qVar"state", + Bop(Sub, + Dest + ("EPC",F64, + Dest("CP0",CTy"CP0",qVar"state")), + LW(4,64))]), + Rupd + ("CP0", + TP[qVar"s", + Rupd + ("Status", + TP[Dest("CP0",CTy"CP0",qVar"s"), + Rupd + ("EXL", + TP[Dest + ("Status", + CTy"StatusRegister", + Dest + ("CP0",CTy"CP0",qVar"s")), + LF])])]))),Mop(Some,LF)])])], + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state"))) ; val dfn'MTC0_def = Def ("dfn'MTC0",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)], @@ -6626,8 +6574,9 @@ val dfn'J_def = Def ("BranchTo", TP[qVar"state", Mop(Some, - CC[EX(Dest("PC",F64,qVar"state"),LN 63,LN 28,FTy 36), - Var("instr_index",FTy 26),LW(0,2)])])])) + TP[LF, + CC[EX(Dest("PC",F64,qVar"state"),LN 63,LN 28,FTy 36), + Var("instr_index",FTy 26),LW(0,2)]])])])) ; val dfn'JAL_def = Def ("dfn'JAL",Var("instr_index",FTy 26), @@ -6645,8 +6594,9 @@ val dfn'JAL_def = Def ("BranchTo", TP[qVar"s", Mop(Some, - CC[EX(Dest("PC",F64,qVar"s"),LN 63,LN 28,FTy 36), - Var("instr_index",FTy 26),LW(0,2)])])]))) + TP[LF, + CC[EX(Dest("PC",F64,qVar"s"),LN 63,LN 28,FTy 36), + Var("instr_index",FTy 26),LW(0,2)]])])]))) ; val dfn'JR_def = Def ("dfn'JR",Var("rs",FTy 5), @@ -6657,11 +6607,12 @@ val dfn'JR_def = Def ("BranchTo", TP[qVar"state", Mop(Some, - Mop(Fst, - Apply - (Call - ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")))])])) + TP[LF, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state"))])])])) ; val dfn'JALR_def = Def ("dfn'JALR",TP[Var("rs",FTy 5),Var("rd",FTy 5)], @@ -6677,426 +6628,376 @@ val dfn'JALR_def = Def TP[Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64)), Var("rd",FTy 5)]),qVar"state")), Mop(Some, - Mop(Fst, - Apply - (Call - ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")))])])) + TP[LF, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state"))])])])) ; -val dfn'BEQ_def = Def - ("dfn'BEQ",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("offset",F16)], +val ConditionalBranch_def = Def + ("ConditionalBranch",TP[bVar"b",Var("offset",F16)], Close (qVar"state", - ITE(EQ(Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")), - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), - qVar"state"))), - TP[LU, + TP[LU, + Rupd + ("BranchTo", + TP[qVar"state", + Mop(Some, + ITE(bVar"b", + TP[LF, + Bop(Add, + Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2))], + TP[LT,Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64))]))])])) +; +val ConditionalBranchLikely_def = Def + ("ConditionalBranchLikely",TP[bVar"b",Var("offset",F16)], + Close + (qVar"state", + TP[LU, + ITB([(bVar"b", + Rupd + ("BranchTo", + TP[qVar"state", + Mop(Some, + TP[LF, + Bop(Add, + Bop(Add,Dest("PC",F64,qVar"state"), + LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2))])])), + (Mop(IsSome,Dest("BranchDelay",OTy(OTy F64),qVar"state")), + Rupd + ("BranchTo", + TP[qVar"state", + Mop(Some, + TP[LT, + Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64))])]))], Rupd - ("BranchTo", + ("PC", TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) + Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64))]))])) +; +val dfn'BEQ_def = Def + ("dfn'BEQ",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("ConditionalBranch",ATy(qTy,PTy(uTy,qTy)), + TP[EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))),Var("offset",F16)]),qVar"state"))) ; val dfn'BNE_def = Def ("dfn'BNE",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Mop(Not, - EQ(Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")), - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), - qVar"state")))), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) + Apply + (Call + ("ConditionalBranch",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Not, + EQ(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")))), + Var("offset",F16)]),qVar"state"))) ; val dfn'BLEZ_def = Def ("dfn'BLEZ",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Bop(Le, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) + Apply + (Call + ("ConditionalBranch",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Le, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + qVar"state"))) ; val dfn'BGTZ_def = Def ("dfn'BGTZ",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Bop(Gt, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) + Apply + (Call + ("ConditionalBranch",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Gt, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + qVar"state"))) ; val dfn'BLTZ_def = Def ("dfn'BLTZ",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Bop(Lt, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) + Apply + (Call + ("ConditionalBranch",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lt, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + qVar"state"))) ; val dfn'BGEZ_def = Def ("dfn'BGEZ",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Bop(Ge, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) + Apply + (Call + ("ConditionalBranch",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Ge, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + qVar"state"))) ; val dfn'BLTZAL_def = Def ("dfn'BLTZAL",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - Let(qVar"s", - Mop(Snd, - Apply - (Call - ("write'GPR",ATy(qTy,PTy(uTy,qTy)), - TP[Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64)), - LW(31,5)]),qVar"state")), - ITE(Bop(Lt, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"s", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"s"))))) + Apply + (Call + ("ConditionalBranch",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lt, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64)), + LW(31,5)]),qVar"state"))))) ; val dfn'BGEZAL_def = Def ("dfn'BGEZAL",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - Let(qVar"s", - Mop(Snd, - Apply - (Call - ("write'GPR",ATy(qTy,PTy(uTy,qTy)), - TP[Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64)), - LW(31,5)]),qVar"state")), - ITE(Bop(Ge, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"s", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"s"))))) + Apply + (Call + ("ConditionalBranch",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Ge, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64)), + LW(31,5)]),qVar"state"))))) ; val dfn'BEQL_def = Def ("dfn'BEQL",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(EQ(Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")), - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), - qVar"state"))), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Let(qVar"s", - Mop(Snd, - Apply - (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), - qVar"state")), - TP[LU, - Rupd - ("PC", - TP[qVar"s",Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))])])))) + Apply + (Call + ("ConditionalBranchLikely",ATy(qTy,PTy(uTy,qTy)), + TP[EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))),Var("offset",F16)]),qVar"state"))) ; val dfn'BNEL_def = Def ("dfn'BNEL",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Mop(Not, - EQ(Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")), - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), - qVar"state")))), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Let(qVar"s", - Mop(Snd, - Apply - (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), - qVar"state")), - TP[LU, - Rupd - ("PC", - TP[qVar"s",Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))])])))) + Apply + (Call + ("ConditionalBranchLikely",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Not, + EQ(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")))), + Var("offset",F16)]),qVar"state"))) ; val dfn'BLEZL_def = Def ("dfn'BLEZL",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Bop(Le, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Let(qVar"s", - Mop(Snd, - Apply - (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), - qVar"state")), - TP[LU, - Rupd - ("PC", - TP[qVar"s",Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))])])))) + Apply + (Call + ("ConditionalBranchLikely",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Le, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + qVar"state"))) ; val dfn'BGTZL_def = Def ("dfn'BGTZL",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Bop(Gt, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Let(qVar"s", - Mop(Snd, - Apply - (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), - qVar"state")), - TP[LU, - Rupd - ("PC", - TP[qVar"s",Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))])])))) + Apply + (Call + ("ConditionalBranchLikely",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Gt, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + qVar"state"))) ; val dfn'BLTZL_def = Def ("dfn'BLTZL",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Bop(Lt, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Let(qVar"s", - Mop(Snd, - Apply - (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), - qVar"state")), - TP[LU, - Rupd - ("PC", - TP[qVar"s",Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))])])))) + Apply + (Call + ("ConditionalBranchLikely",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lt, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + qVar"state"))) ; val dfn'BGEZL_def = Def ("dfn'BGEZL",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - ITE(Bop(Ge, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"state", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"state"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Let(qVar"s", - Mop(Snd, - Apply - (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), - qVar"state")), - TP[LU, - Rupd - ("PC", - TP[qVar"s",Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))])])))) + Apply + (Call + ("ConditionalBranchLikely",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Ge, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + qVar"state"))) ; val dfn'BLTZALL_def = Def ("dfn'BLTZALL",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - Let(qVar"s", - Mop(Snd, - Apply - (Call - ("write'GPR",ATy(qTy,PTy(uTy,qTy)), - TP[Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64)), - LW(31,5)]),qVar"state")), - ITE(Bop(Lt, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"s", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Let(qVar"s", - Mop(Snd, - Apply - (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), - qVar"s")), - TP[LU, - Rupd - ("PC", - TP[qVar"s", - Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))])]))))) + Apply + (Call + ("ConditionalBranchLikely",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lt, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64)), + LW(31,5)]),qVar"state"))))) ; val dfn'BGEZALL_def = Def ("dfn'BGEZALL",TP[Var("rs",FTy 5),Var("offset",F16)], Close (qVar"state", - Let(qVar"s", - Mop(Snd, - Apply - (Call - ("write'GPR",ATy(qTy,PTy(uTy,qTy)), - TP[Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64)), - LW(31,5)]),qVar"state")), - ITE(Bop(Ge, - Mop(Fst, - Apply - (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), - qVar"state")),LW(0,64)), - TP[LU, - Rupd - ("BranchTo", - TP[qVar"s", - Mop(Some, - Bop(Add, - Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64)), - Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))])], - Let(qVar"s", - Mop(Snd, - Apply - (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), - qVar"s")), - TP[LU, - Rupd - ("PC", - TP[qVar"s", - Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))])]))))) + Apply + (Call + ("ConditionalBranchLikely",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Ge, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)),Var("offset",F16)]), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add,Dest("PC",F64,qVar"state"),LW(8,64)), + LW(31,5)]),qVar"state"))))) ; val dfn'WAIT_def = Def0 ("dfn'WAIT",LU) ; +val dfn'TLBP_def = Def + ("dfn'TLBP",qVar"state", + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state")) +; +val dfn'TLBR_def = Def + ("dfn'TLBR",qVar"state", + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state")) +; +val dfn'TLBWI_def = Def + ("dfn'TLBWI",qVar"state", + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state")) +; +val dfn'TLBWR_def = Def + ("dfn'TLBWR",qVar"state", + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state")) +; +val dfn'CACHE_def = Def + ("dfn'CACHE",TP[Var("base",FTy 5),Var("opn",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state"))) +; +val dfn'RDHWR_def = Def + ("dfn'RDHWR",TP[Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state"))) +; val dfn'ReservedInstruction_def = Def ("dfn'ReservedInstruction",qVar"state", Apply @@ -11596,36 +11497,53 @@ val Next_def = Def Let(qVar"s", Rupd ("exceptionSignalled", - TP[CS(TP[Dest("BranchDelay",OTy F64,qVar"s"), - Dest("BranchTo",OTy F64,qVar"s")], - [(TP[LO F64,LO F64], - ITE(Mop(Not, - Dest("exceptionSignalled",bTy,qVar"s")), - Rupd - ("PC", - TP[qVar"s", - Bop(Add,Dest("PC",F64,qVar"s"), - LW(4,64))]),qVar"s")), - (TP[Mop(Some,Var("addr",F64)),LO F64], + TP[CS(TP[Dest("BranchDelay",OTy(OTy F64),qVar"s"), + Dest("BranchTo",OTy(PTy(bTy,F64)),qVar"s")], + [(TP[LO(OTy F64),LO(PTy(bTy,F64))], Rupd ("PC", - TP[Rupd("BranchDelay",TP[qVar"s",LO F64]), - Var("addr",F64)])), - (TP[LO F64,Mop(Some,Var("addr",F64))], + TP[qVar"s", + Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))])), + (TP[LO(OTy F64),Mop(Some,TP[LT,Var("addr",F64)])], + Rupd + ("PC", + TP[Rupd + ("BranchTo", + TP[Rupd + ("BranchDelay", + TP[qVar"s",Mop(Some,LO F64)]), + LO(PTy(bTy,F64))]),Var("addr",F64)])), + (TP[LO(OTy F64),Mop(Some,TP[LF,Var("addr",F64)])], Let(qVar"s", Rupd ("BranchTo", TP[Rupd ("BranchDelay", TP[qVar"s", - Mop(Some,Var("addr",F64))]), - LO F64]), + Mop(Some, + Mop(Some,Var("addr",F64)))]), + LO(PTy(bTy,F64))]), Rupd ("PC", TP[qVar"s", Bop(Add,Dest("PC",F64,qVar"s"), LW(4,64))]))), - (AVar(PTy(OTy F64,OTy F64)), + (TP[Mop(Some,LO F64),LO(PTy(bTy,F64))], + Let(qVar"s", + Rupd("BranchDelay",TP[qVar"s",LO(OTy F64)]), + Rupd + ("PC", + TP[qVar"s", + Bop(Add,Dest("PC",F64,qVar"s"), + LW(4,64))]))), + (TP[Mop(Some,Mop(Some,Var("addr",F64))), + LO(PTy(bTy,F64))], + Rupd + ("PC", + TP[Rupd + ("BranchDelay",TP[qVar"s",LO(OTy F64)]), + Var("addr",F64)])), + (AVar(PTy(OTy(OTy F64),OTy(PTy(bTy,F64)))), Mop(Snd, Apply (Call diff --git a/examples/l3-machine-code/mips/prog/mips_progLib.sml b/examples/l3-machine-code/mips/prog/mips_progLib.sml index c1feece9ed..43c5ef05c4 100644 --- a/examples/l3-machine-code/mips/prog/mips_progLib.sml +++ b/examples/l3-machine-code/mips/prog/mips_progLib.sml @@ -85,7 +85,9 @@ val state_id = [["CP0", "PC", "gpr"], ["CP0", "PC", "exceptionSignalled", "gpr"], ["CP0", "PC", "exceptionSignalled"], + ["CP0", "PC", "exceptionSignalled", "hi", "lo"], ["CP0", "LLbit", "PC"], + ["CP0", "LLbit", "PC", "exceptionSignalled"], ["CP0", "LLbit", "PC", "gpr"], ["CP0", "PC"], ["CP0", "PC", "lo"], @@ -164,22 +166,23 @@ local case fst (Term.dest_const (boolSyntax.rator tm)) of "cond" => 0 | "mips_exception" => 1 - | "mips_CP0_Status_RE" => 2 - | "mips_CP0_Status_ERL" => 3 - | "mips_CP0_Status_EXL" => 4 - | "mips_CP0_Status_BEV" => 5 - | "mips_CP0_Config_BE" => 6 - | "mips_CP0_Count" => 7 - | "mips_CP0_Cause" => 8 - | "mips_CP0_EPC" => 9 - | "mips_CP0_Debug" => 10 - | "mips_CP0_ErrCtl" => 11 - | "mips_BranchDelay" => 12 - | "mips_BranchTo" => 13 - | "mips_LLbit" => 14 - | "mips_hi" => 15 - | "mips_lo" => 16 - | "mips_PC" => 17 + | "mips_exceptionSignalled" => 2 + | "mips_CP0_Status_RE" => 3 + | "mips_CP0_Status_ERL" => 4 + | "mips_CP0_Status_EXL" => 5 + | "mips_CP0_Status_BEV" => 6 + | "mips_CP0_Config_BE" => 7 + | "mips_CP0_Count" => 8 + | "mips_CP0_Cause" => 9 + | "mips_CP0_EPC" => 10 + | "mips_CP0_Debug" => 11 + | "mips_CP0_ErrCtl" => 12 + | "mips_BranchDelay" => 13 + | "mips_BranchTo" => 14 + | "mips_LLbit" => 15 + | "mips_hi" => 16 + | "mips_lo" => 17 + | "mips_PC" => 18 | _ => ~1 val total_dest_lit = Lib.total wordsSyntax.dest_word_literal fun word_compare (w1, w2) = @@ -406,7 +409,7 @@ in end | _ => [] in - List.map + List.mapPartial (fn (s, ds) => let val sbst = Term.subst s @@ -415,13 +418,17 @@ in val f = utilsLib.rhsc o cnv o sbst val p' = subst_delete f ds pl val q' = subst_delete f ds ql + val th = thm |> Thm.INST s + |> Drule.DISCH_ALL + |> Conv.CONV_RULE cnv + |> Drule.UNDISCH_ALL in - (thm |> Thm.INST s - |> Drule.DISCH_ALL - |> Conv.CONV_RULE cnv - |> Drule.UNDISCH_ALL, - temporal_stateSyntax.mk_spec_or_temporal_next m - (stateLib.generate_temporal()) (p', sbst c, q')) + if utilsLib.vacuous th + then NONE + else SOME + (th, + temporal_stateSyntax.mk_spec_or_temporal_next m + (stateLib.generate_temporal()) (p', sbst c, q')) end) groups end end @@ -467,6 +474,12 @@ in end end +(* +val l = (List.concat thm_ts) +val x as (thm, t) = List.nth (l, 0) +spec x +*) + local val get_opcode = fst o bitstringSyntax.dest_v2w o @@ -533,6 +546,8 @@ end (* Testing... +open mips_progLib + val imp_spec = MIPS_IMP_SPEC val imp_temp = mips_progTheory.MIPS_IMP_TEMPORAL val read_thms = [mips_stepTheory.get_bytes] @@ -559,13 +574,16 @@ in in bitstringSyntax.hexstring_of_term (Term.subst s tm) end + fun hex s = + mips_spec_hex s + handle e as HOL_ERR _ => (print ("\n\n" ^ s ^ "\n\n"); raise e) end val () = mips_config false val be = false val tst = mips_spec -val tst = Count.apply mips_spec_hex o random_hex -val tst = mips_spec_hex o random_hex +val tst = Count.apply hex o random_hex +val tst = hex o random_hex val dec = Conv.CONV_RULE (Conv.DEPTH_CONV bitstringLib.v2w_n2w_CONV) o mips_stepLib.mips_decode_hex @@ -574,7 +592,12 @@ val d = List.filter (fn (s, _) => not (Lib.mem s ["MFC0", "MTC0"])) val l = List.map (I ## tst) d -mips_stepLib.mips_find_opc (mips_stepLib.hex_to_padded_opcode "9FA0AED9") +mips_stepLib.mips_find_opc (mips_stepLib.hex_to_padded_opcode "000C001E") + +val s = random_hex (Redblackmap.find (mips_stepLib.mips_dict, "ERET")) +mips_spec (Redblackmap.find (mips_stepLib.mips_dict, "ERET")) + +mips_spec_hex s dec "9FA0AED9" diff --git a/examples/l3-machine-code/mips/step/mips_stepLib.sml b/examples/l3-machine-code/mips/step/mips_stepLib.sml index 84676b2f7e..619de90f6c 100644 --- a/examples/l3-machine-code/mips/step/mips_stepLib.sml +++ b/examples/l3-machine-code/mips/step/mips_stepLib.sml @@ -40,7 +40,8 @@ val cond_thms = Q.prove( local val state_fns = utilsLib.accessor_fns ``:mips_state`` val other_fns = - [pairSyntax.fst_tm, pairSyntax.snd_tm, bitstringSyntax.v2w_tm] @ + [pairSyntax.fst_tm, pairSyntax.snd_tm, bitstringSyntax.v2w_tm, + optionSyntax.is_some_tm] @ utilsLib.update_fns ``:mips_state`` val extra_fns = [wordsSyntax.sw2sw_tm, wordsSyntax.w2w_tm, @@ -221,7 +222,8 @@ val bEV = dfn'BLTZ_def, dfn'BGEZ_def, dfn'BLTZAL_def, dfn'BGEZAL_def, dfn'BEQL_def, dfn'BNEL_def, dfn'BLEZL_def, dfn'BGTZL_def, dfn'BLTZL_def, dfn'BGEZL_def, dfn'BLTZALL_def, dfn'BGEZALL_def, - CheckBranch_def] [[``^st.BranchDelay = NONE``]] [] + ConditionalBranch_def, ConditionalBranchLikely_def] + [[``^st.BranchDelay = NONE``]] [] (* ------------------------------------------------------------------------- *) @@ -325,7 +327,9 @@ val BGEZALL = bEV ``dfn'BGEZALL (rs, offset)`` (* Assumes EXL is high, which permits return from exception *) val ERET = - EVR COND_UPDATE_RULE [dfn'ERET_def, KernelMode_def, CheckBranch_def] + EVR (SIMP_RULE std_ss [ASSUME ``^st.CP0.Status.EXL``, satTheory.AND_INV] o + COND_UPDATE_RULE) + [dfn'ERET_def, KernelMode_def] [[``^st.CP0.Status.EXL``, ``^st.BranchDelay = NONE``]] [] ``dfn'ERET`` (* ------------------------------------------------------------------------- *) @@ -581,12 +585,16 @@ local val v = fst (bitstringSyntax.dest_v2w (bitstringSyntax.mk_vec 32 0)) val unpredictable_tm = ``mips$Unpredictable`` fun fix_unpredictable thm = - case Lib.total (boolSyntax.dest_cond o utilsLib.rhsc) thm of - SOME (b, t, _) => - if t = unpredictable_tm - then REWRITE_RULE [ASSUME (boolSyntax.mk_neg b)] thm - else thm - | _ => thm + let + val thm = REWRITE_RULE [not31] thm + in + case Lib.total (boolSyntax.dest_cond o utilsLib.rhsc) thm of + SOME (b, t, _) => + if t = unpredictable_tm + then REWRITE_RULE [ASSUME (boolSyntax.mk_neg b)] thm + else thm + | _ => thm + end in fun DecodeMIPS pat = let @@ -875,26 +883,31 @@ local val st_BranchDelay_tm = mk_proj_BranchDelay st val ap_snd = Thm.AP_TERM ``SND:unit # mips_state -> mips_state`` val snd_conv = Conv.REWR_CONV pairTheory.SND - val delay_none_tm = ``^st.BranchDelay = NONE`` - val delay_ok = not o List.exists (Lib.equal delay_none_tm) o Thm.hyp val STATE_CONV = Conv.QCONV (REWRITE_CONV (utilsLib.datatype_rewrites true "mips" ["mips_state", "CP0"] @ [boolTheory.COND_ID, cond_rand_thms, ASSUME ``^st.BranchTo = NONE``])) + THENC REPEATC + (Conv.DEPTH_CONV Thm.BETA_CONV + THENC + REWRITE_CONV + [boolTheory.COND_ID, wordsTheory.WORD_SUB_ADD, branch_delay, + pairTheory.pair_case_def]) val BRANCH_DELAY_RULE = - PURE_REWRITE_RULE [ASSUME ``^st.BranchDelay = SOME a``] + utilsLib.ALL_HYP_CONV_RULE + (REWRITE_CONV [ASSUME ``^st.BranchDelay = SOME d``, + optionTheory.NOT_SOME_NONE]) val NO_BRANCH_DELAY_RULE = PURE_REWRITE_RULE [boolTheory.COND_ID, ASSUME ``^st.BranchDelay = NONE``] val state_rule = Conv.RIGHT_CONV_RULE (Conv.RAND_CONV STATE_CONV) val exc_rule = SIMP_RULE bool_ss [] o COND_UPDATE_RULE o state_rule - val MP_Next = state_rule o Drule.MATCH_MP NextStateMIPS_nodelay - val MP_NextB = state_rule o Drule.MATCH_MP NextStateMIPS_delay - val MP_NextE = exc_rule o Drule.MATCH_MP NextStateMIPS_exception o + val MP_Next = state_rule o Drule.MATCH_MP NextStateMIPS_nodelay o NO_BRANCH_DELAY_RULE - val MP_NextF = exc_rule o Drule.MATCH_MP NextStateMIPS_exception_delay o - BRANCH_DELAY_RULE + val MP_NextB = state_rule o BRANCH_DELAY_RULE o + Drule.MATCH_MP NextStateMIPS_delay + val MP_NextE = state_rule o Drule.MATCH_MP NextStateMIPS_exception val Run_CONV = utilsLib.Run_CONV ("mips", st) o utilsLib.rhsc in fun mips_eval be = @@ -915,18 +928,13 @@ in val tm = rhsc thm3 val thms = List.map (fn f => STATE_CONV (f tm)) [mk_proj_exception, - mk_proj_exceptionSignalled, mk_proj_BranchDelay, mk_proj_BranchTo] val thm = Drule.LIST_CONJ ([thm1, thm2, thm3] @ thms) in - if rhsc (List.nth (thms, 2)) = st_BranchDelay_tm - then MP_Next thm :: - (if delay_ok thm andalso - optionSyntax.is_none (rhsc (Lib.last thms)) - then [MP_NextB thm] - else []) - else [MP_NextE thm, MP_NextF thm] + [MP_Next thm] @ + ([MP_NextB thm] handle HOL_ERR _ => []) @ + ([MP_NextE thm] handle HOL_ERR _ => []) end end end @@ -956,14 +964,16 @@ open mips_stepLib val step = mips_eval false fun test s = step (Redblackmap.find (mips_dict, s)) - -test "ADDI"; -test "ADDU"; -test "J"; -test "BEQ"; -test "BEQL"; -test "BLTZAL"; -test "ERET" +fun test s = (Redblackmap.find (mips_dict, s)) + +val v = test "ADDI"; +val v = test "ADDU"; +val v = test "J"; +val v = test "BEQ"; +val v = test "BEQL"; +val v = test "BLTZAL"; +val v = test "BLTZALL"; +val v = test "ERET" val be = false val v = bitstringSyntax.bitstring_of_hexstring "811BAF37" diff --git a/examples/l3-machine-code/mips/step/mips_stepScript.sml b/examples/l3-machine-code/mips/step/mips_stepScript.sml index 1049c6954b..cc724a826e 100644 --- a/examples/l3-machine-code/mips/step/mips_stepScript.sml +++ b/examples/l3-machine-code/mips/step/mips_stepScript.sml @@ -40,6 +40,7 @@ val tac = exceptionSignalled_id, LoadMemory_ARB_CCA] \\ Cases_on `(SND (Run (Decode w) s)).BranchTo` \\ Cases_on `(SND (Run (Decode w) s)).BranchDelay` + \\ TRY (Cases_on `x`) \\ lrw [] \\ fs [mips_state_component_equality] @@ -51,88 +52,72 @@ val NextStateMIPS_nodelay = utilsLib.ustore_thm("NextStateMIPS_nodelay", (Decode w = i) /\ (SND (Run i s) = next_state) /\ (next_state.exception = s.exception) /\ - (next_state.exceptionSignalled = s.exceptionSignalled) /\ - (next_state.BranchDelay = s.BranchDelay) /\ + (next_state.BranchDelay = NONE) /\ (next_state.BranchTo = b) ==> (NextStateMIPS s = SOME (next_state with - <| PC := next_state.PC + 4w; - BranchDelay := b; + <| PC := case b of SOME (T, a) => a | _ => next_state.PC + 4w; + BranchDelay := case b of SOME (F, a) => SOME (SOME a) + | SOME (T, _) => SOME NONE + | _ => NONE; BranchTo := NONE; + exceptionSignalled := F; CP0 := next_state.CP0 with Count := next_state.CP0.Count + 1w |>))`, - tac) + tac + ) val NextStateMIPS_delay = utilsLib.ustore_thm("NextStateMIPS_delay", `(s.exception = NoException) /\ - (s.BranchDelay = SOME a) /\ + (s.BranchDelay = SOME d) /\ ~s.exceptionSignalled ==> (Fetch s = (SOME w, s)) /\ (Decode w = i) /\ (SND (Run i s) = next_state) /\ (next_state.exception = s.exception) /\ - (next_state.exceptionSignalled = s.exceptionSignalled) /\ (next_state.BranchDelay = s.BranchDelay) /\ (next_state.BranchTo = NONE) ==> (NextStateMIPS s = SOME (next_state with - <| PC := a; + <| PC := case d of SOME a => a | NONE => next_state.PC + 4w; BranchDelay := NONE; + exceptionSignalled := F; CP0 := next_state.CP0 with Count := next_state.CP0.Count + 1w |>))`, - tac) + tac + ) +(* exceptions can occur in the branch delay slot *) val NextStateMIPS_exception = utilsLib.ustore_thm("NextStateMIPS_exception", `(s.exception = NoException) /\ - (s.BranchDelay = NONE) /\ - ~s.exceptionSignalled ==> - (Fetch s = (SOME w, s)) /\ - (Decode w = i) /\ - (SND (Run i s) = next_state) /\ - (next_state.exception = s.exception) /\ - (next_state.exceptionSignalled = e) /\ - (next_state.BranchDelay = NONE) /\ - (next_state.BranchTo = b) ==> - (NextStateMIPS s = - SOME (if e /\ (b = NONE) then - next_state with - <| PC := next_state.PC; - exceptionSignalled := F; - CP0 := next_state.CP0 with - Count := next_state.CP0.Count + 1w |> - else - next_state with - <| PC := next_state.PC + 4w; - BranchDelay := b; - BranchTo := NONE; - exceptionSignalled := F; - CP0 := next_state.CP0 with - Count := next_state.CP0.Count + 1w |>))`, - tac) - -val NextStateMIPS_exception_delay = - utilsLib.ustore_thm("NextStateMIPS_exception_delay", - `(s.exception = NoException) /\ - (s.BranchDelay = SOME a) /\ + (s.BranchDelay = SOME d) /\ ~s.exceptionSignalled ==> (Fetch s = (SOME w, s)) /\ (Decode w = i) /\ (SND (Run i s) = next_state) /\ (next_state.exception = s.exception) /\ - (next_state.exceptionSignalled = e) /\ - (next_state.BranchDelay = if e then NONE else SOME a) /\ + (next_state.BranchDelay = if b then NONE else s.BranchDelay) /\ (next_state.BranchTo = NONE) ==> (NextStateMIPS s = SOME (next_state with - <| PC := if e then next_state.PC else a; + <| PC := if b then + next_state.PC + 4w + else + (case d of SOME a => a | NONE => next_state.PC + 4w); BranchDelay := NONE; exceptionSignalled := F; CP0 := next_state.CP0 with Count := next_state.CP0.Count + 1w |>))`, - tac) + tac + ) (* ------------------------------------------------------------------------ *) +val not31 = Q.store_thm("not31", + `x0 /\ x1 /\ x2 /\ x3 /\ x4 = (v2w [x0; x1; x2; x3; x4] = (31w: word5))`, + blastLib.BBLAST_TAC + ) + val v2w_0_rwts = Q.store_thm("v2w_0_rwts", `((v2w [F; F; F; F; F] = 0w: word5)) /\ ((v2w [T; b3; b2; b1; b0] = 0w: word5) = F) /\ @@ -557,4 +542,38 @@ val StoreMemory_doubleword = Q.store_thm("StoreMemory_doubleword", (* ------------------------------------------------------------------------ *) +val branch_delay = Q.store_thm("branch_delay", + `(!b x y. + (case (if b then (F, x) else (T, y)) of + (T, a) => SOME NONE + | (F, a) => SOME (SOME a)) = + (if b then SOME (SOME x) else SOME NONE)) /\ + (!b x y. + (case (if b then (F, x) else (T, y)) of + (T, a) => a + | (F, a) => y) = y) /\ + (!b x y. + (if b then + (case THE (if b then SOME (F, x) else NONE) of + (T, a) => SOME NONE + | (F, a) => SOME (SOME a)) + else + NONE) = + (if b then SOME (SOME x) else NONE)) /\ + (!b x y. + (if b then + (case THE (if b then SOME (F, x) else NONE) of + (T, a) => a + | (F, a) => y) + else + y) = y) /\ + (!b. (if b then T else F) = b) /\ + (!b x y. + (if b then x else y) + 4w = (if b then x + 4w else y + 4w)) /\ + (!x. x + 4w + 4w = x + 8w)`, + rw [] \\ fs []) + +(* ------------------------------------------------------------------------ *) + + val () = export_theory () From 210a422372a92c66744651b3e99c67a78e72df3a Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Tue, 11 Nov 2014 14:53:11 +1100 Subject: [PATCH 024/718] Tweak generation of Inno Setup file for building Windows installer --- tools/make_iss.sml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/make_iss.sml b/tools/make_iss.sml index 574a69074f..74602dae9c 100644 --- a/tools/make_iss.sml +++ b/tools/make_iss.sml @@ -11,6 +11,8 @@ val holdir = Globals.HOLDIR val systeml = Systeml.systeml val sysname = Globals.release ^ " " ^ Int.toString Globals.version +val sysname_lchyphen = + String.translate (fn #" " => "-" | c => str (Char.toLower c)) sysname val _ = print "Changing to hol directory\n" val _ = FileSys.chDir holdir @@ -56,7 +58,7 @@ val header = "\ \DefaultGroupName = HOL\n\ \Compression = lzma/ultra\n\ \SolidCompression = true\n\ -\OutputBaseFilename = HOL-install\n"; +\OutputBaseFilename = "^sysname_lchyphen^"-install\n"; fun mem s [] = false | mem s (h::t) = s = h orelse mem s t From 229718f6f5ac13765a628450b16d84426008b619 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Tue, 11 Nov 2014 14:54:19 +1100 Subject: [PATCH 025/718] Fix error in K-10 release notes (already fixed on webpages etc) --- doc/kananaskis-10.release.md | 2 -- 1 file changed, 2 deletions(-) diff --git a/doc/kananaskis-10.release.md b/doc/kananaskis-10.release.md index 57be12e12d..7c038ea072 100644 --- a/doc/kananaskis-10.release.md +++ b/doc/kananaskis-10.release.md @@ -63,8 +63,6 @@ Bugs fixed: * The “munging” code for turning HOL into LaTeX now does a better job of rendering data type definition theorems. (This change is independent of the new underlying syntax described earlier.) -* On Windows, the Unicode trace is now off by default. - * Pretty-printers added to the system with `add_user_printer` weren’t having terms-to-be-printed tested against the supplied patterns (except by the gross approximation provided by the built-in term-net structure). Thanks to Ramana Kumar for the [bug report](https://github.com/mn200/HOL/issues/172). * Character literals weren’t pretty-printing to LaTeX. We also improved the handling of string literals. Thanks to Ramana Kumar for the [bug reports](http://github.com/HOL-Theorem-Prover/HOL/issues/190). From 742c71b9b46d2753a2e5403d0e6d27668a255ac0 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Tue, 11 Nov 2014 15:50:49 +1100 Subject: [PATCH 026/718] Some minor fixes to TeX hacking for monad syntax. In short, spaces shouldn't appear in the "hol" field of TeX_notation call because tokens with spaces in them aren't going to get omitted if the grammar rule is remotely sensible (math mode munging gets hard if there are literal spaces around). Putting spaces into the TeX field is wrong (even wronger, really) for the same reason. --- src/monad/monadsyntax.sml | 6 +++--- src/monad/parmonadsyntax.sml | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/monad/monadsyntax.sml b/src/monad/monadsyntax.sml index bec3689ffc..da0a6c76c7 100644 --- a/src/monad/monadsyntax.sml +++ b/src/monad/monadsyntax.sml @@ -201,8 +201,8 @@ val _ = temp_overload_on (monad_unitbind, mkc "IGNORE_BIND") val _ = temp_overload_on ("return", mkc "UNIT") val _ = TexTokenMap.temp_TeX_notation - {hol = "<-", TeX = ("\\HOLTokenLeftmap", 1)} -val _ = TexTokenMap.temp_TeX_notation {hol = "do", TeX = (" \\HOLKeyword{do}", 2)} -val _ = TexTokenMap.temp_TeX_notation {hol = "od", TeX = (" \\HOLKeyword{od}", 2)} + {hol = "<-", TeX = ("\\HOLTokenLeftmap{}", 1)} +val _ = TexTokenMap.temp_TeX_notation {hol = "do", TeX = ("\\HOLKeyword{do}", 2)} +val _ = TexTokenMap.temp_TeX_notation {hol = "od", TeX = ("\\HOLKeyword{od}", 2)} end (* struct *) diff --git a/src/monad/parmonadsyntax.sml b/src/monad/parmonadsyntax.sml index 51e29bdfb0..047c5086ae 100644 --- a/src/monad/parmonadsyntax.sml +++ b/src/monad/parmonadsyntax.sml @@ -259,7 +259,7 @@ end val _ = temp_add_user_printer ("parmonadsyntax.print_monads", ``x:'a``, print_monads) -val _ = TexTokenMap.temp_TeX_notation {hol = " <-", TeX = (" \\HOLTokenLeftmap{}", 1)} -val _ = TexTokenMap.temp_TeX_notation {hol = "do", TeX = (" \\HOLKeyword{do}", 2)} -val _ = TexTokenMap.temp_TeX_notation {hol = "od", TeX = (" \\HOLKeyword{od}", 2)} +val _ = TexTokenMap.temp_TeX_notation {hol = "<-", TeX = ("\\HOLTokenLeftmap{}", 1)} +val _ = TexTokenMap.temp_TeX_notation {hol = "do", TeX = ("\\HOLKeyword{do}", 2)} +val _ = TexTokenMap.temp_TeX_notation {hol = "od", TeX = ("\\HOLKeyword{od}", 2)} end (* struct *) From 7e33637495f0f50b227b08c20d33f96037333729 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Tue, 18 Nov 2014 10:23:15 +1100 Subject: [PATCH 027/718] list_tactic concept introduce list_tactic - works on a list of goals, not a single goal THEN_LT (tac1, ltac2 : list_tactic), A tactical that applies ltac2 to the list of subgoals resulting from tac1 TACS_TO_LT (tac2l: tactic list) : list_tactic ALLGOALS - A list_tactic which applies a given tactic to all goals ALL_LT - always succeeds NTH_GOAL - applies tactic to nth goal of list REVERSE_LT - A list_tactic that reverses a list of subgoals SPLIT_LT - apply two list-tactics, one to first n subgoals, the other to the rest ROTATE_LT - rotate the list of subgoals by n positions --- src/0/Overlay.sml | 2 +- src/1/Abbrev.sig | 2 + src/1/Abbrev.sml | 2 + src/1/Tactical.sig | 15 ++++ src/1/Tactical.sml | 174 ++++++++++++++++++++++++++++++++++++++++++++- 5 files changed, 191 insertions(+), 4 deletions(-) diff --git a/src/0/Overlay.sml b/src/0/Overlay.sml index fa42318c65..d8c453f615 100644 --- a/src/0/Overlay.sml +++ b/src/0/Overlay.sml @@ -22,7 +22,7 @@ open CoreKernel; between the two. ---------------------------------------------------------------------- *) -infix ++ && |-> THEN THEN1 THENL THENC ORELSE ORELSEC THEN_TCL ORELSE_TCL ?> |> +infix ++ && |-> THEN THEN1 THENL THEN_LT THENC ORELSE ORELSEC THEN_TCL ORELSE_TCL ?> |> (* infixes for THEN shorthands *) infix >> >- >| \\ diff --git a/src/1/Abbrev.sig b/src/1/Abbrev.sig index 936397d903..4fce1dae32 100644 --- a/src/1/Abbrev.sig +++ b/src/1/Abbrev.sig @@ -8,6 +8,8 @@ sig type goal = term list * term type validation = thm list -> thm type tactic = goal -> goal list * validation + type list_validation = thm list -> thm list + type list_tactic = goal list -> goal list * list_validation type thm_tactic = thm -> tactic type thm_tactical = thm_tactic -> thm_tactic type ppstream = Portable.ppstream diff --git a/src/1/Abbrev.sml b/src/1/Abbrev.sml index bda92f1627..ea8168a2e4 100644 --- a/src/1/Abbrev.sml +++ b/src/1/Abbrev.sml @@ -8,6 +8,8 @@ struct type goal = term list * term type validation = thm list -> thm type tactic = goal -> goal list * validation + type list_validation = thm list -> thm list + type list_tactic = goal list -> goal list * list_validation type thm_tactic = thm -> tactic type thm_tactical = thm_tactic -> thm_tactic type ppstream = Portable.ppstream diff --git a/src/1/Tactical.sig b/src/1/Tactical.sig index 74fa1313b3..701ce57c9f 100644 --- a/src/1/Tactical.sig +++ b/src/1/Tactical.sig @@ -9,10 +9,25 @@ sig val THENL : tactic * tactic list -> tactic val ORELSE : tactic * tactic -> tactic val THEN1 : tactic * tactic -> tactic + val THEN_LT : ('a -> goal list * (thm list -> 'b)) * list_tactic -> + 'a -> goal list * (thm list -> 'b) + (* could be used as + val THEN_LT : tactic * list_tactic -> tactic + val THEN_LT : list_tactic * list_tactic -> list_tactic + *) + val TACS_TO_LT : tactic list -> list_tactic + val ALLGOALS : tactic -> list_tactic + val NTH_GOAL : tactic -> int -> list_tactic + val LASTGOAL : tactic -> list_tactic + val HEADGOAL : tactic -> list_tactic + val SPLIT_LT : int -> list_tactic * list_tactic -> list_tactic + val ROTATE_LT : int -> list_tactic val REVERSE : tactic -> tactic + val REVERSE_LT : list_tactic val FAIL_TAC : string -> tactic val NO_TAC : tactic val ALL_TAC : tactic + val ALL_LT : list_tactic val TRY : tactic -> tactic val REPEAT : tactic -> tactic val VALID : tactic -> tactic diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index b870acad0b..1bb7376990 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -75,14 +75,14 @@ fun store_thm (name, tm, tac) = (print ("Failed to prove theorem " ^ name ^ ".\n"); Raise e) -infix THEN THENL THEN1 ORELSE +infix THEN THENL THEN1 ORELSE THEN_LT (*--------------------------------------------------------------------------- * fun (tac1:tactic) THEN (tac2:tactic) : tactic = fn g => * let val (gl,p) = tac1 g * val (gll,pl) = unzip(map tac2 gl) * in - * (flatten gll, (p o mapshape(map length gll)pl)) + * (flatten gll, (p o mapshape(map length gll)pl)) * end; *---------------------------------------------------------------------------*) @@ -113,7 +113,7 @@ fun tac1 THEN tac2 = * val tac2gl = zip tac2l gl * val (gll,pl) = unzip (map (fn (tac2,g) => tac2 g) tac2gl) * in - * (flatten gll, p o mapshape(map length gll) pl) + * (flatten gll, p o mapshape(map length gll) pl) * end *---------------------------------------------------------------------------*) @@ -162,6 +162,152 @@ fun op THEN1 (tac1: tactic, tac2: tactic) : tactic = (t_gl, fn thl => jf (h_jf [] :: thl)) end +(*--------------------------------------------------------------------------- + * tac1 THEN_LT ltac2: + * A tactical that applies ltac2 to the list of subgoals resulting from tac1 + * tac1 may be a tactic or a list_tactic + *---------------------------------------------------------------------------*) +fun op THEN_LT (tac1, ltac2 : list_tactic) = + fn g => + let + val (gl1, vf1) = tac1 g + val (gl2, vf2) = ltac2 gl1 ; + in + (gl2, vf1 o vf2) + end + +(* first argument can be a tactic or a list-tactic *) +val _ = op THEN_LT : tactic * list_tactic -> tactic ; +val _ = op THEN_LT : list_tactic * list_tactic -> list_tactic ; + +(*--------------------------------------------------------------------------- + * fun ALLGOALS (tac2:tactic) : list_tactic = fn gl => + * let + * val (gll,pl) = unzip(map tac2 gl) + * in + * (flatten gll, mapshape(map length gll)pl) + * end; + * A list_tactic which applies a given tactic to all goals + *---------------------------------------------------------------------------*) + +fun ALLGOALS tac2 gl = + case itlist + (fn goal => fn (G, V, lengths) => + case tac2 goal of + ([], vfun) => let + val th = vfun [] + in + (G, empty th :: V, 0 :: lengths) + end + | (goals, vfun) => + (goals @ G, vfun :: V, length goals :: lengths)) + gl ([], [], []) of + ([], V, _) => + ([], let val ths = map (fn f => f []) V in empty ths end) + | (G, V, lengths) => (G, mapshape lengths V) + +(*--------------------------------------------------------------------------- + * fun TACS_TO_LT (tac2l: tactic list) : list_tactic = fn gl => + * let + * val tac2gl = zip tac2l gl + * val (gll,pl) = unzip (map (fn (tac2,g) => tac2 g) tac2gl) + * in + * (flatten gll, mapshape(map length gll) pl) + * end + * Converts a list of tactics to a single list_tactic + *---------------------------------------------------------------------------*) + +fun TACS_TO_LT (tacl: tactic list) : list_tactic = + fn gl => + let + val (G, V, lengths) = + itlist2 + (fn goal => fn tac => fn (G, V, lengths) => + case tac goal of + ([], vfun) => let + val th = vfun [] + in + (G, (empty th) :: V, 0 :: lengths) + end + | (goals, vfun) => + (goals @ G, vfun :: V, length goals :: lengths)) + gl tacl ([], [], []) + in + case G of + [] => ([], let val ths = map (fn f => f []) V in empty ths end) + | _ => (G, mapshape lengths V) + end + +fun (tac1 ORELSE tac2) g = tac1 g handle HOL_ERR _ => tac2 g + +(*--------------------------------------------------------------------------- + * tac1 THEN1 tac2: A tactical like THEN that applies tac2 only to the + * first subgoal of tac1 + *---------------------------------------------------------------------------*) + +fun op THEN1 (tac1: tactic, tac2: tactic) : tactic = + fn g => + let + val (gl, jf) = tac1 g + val (h_g, t_gl) = + case gl of + [] => raise ERR "THEN1" "goal completely solved by first tactic" + | h :: t => (h, t) + val (h_gl, h_jf) = tac2 h_g + val _ = + if null h_gl then () + else raise ERR "THEN1" "first subgoal not solved by second tactic" + in + (t_gl, fn thl => jf (h_jf [] :: thl)) + end + +(*--------------------------------------------------------------------------- + * NTH_GOAL tac n: A list_tactic that applies tac to the nth goal + (counting goals from 1) + *---------------------------------------------------------------------------*) +fun NTH_GOAL tac n gl1 = + let val (gl_before, g :: gl_after) = Lib.split_after (n-1) gl1 ; + val (gl2, vf2) = tac g ; + val gl_result = gl_before @ gl2 @ gl_after ; + fun vf thl = + let val (th_before, th_rest) = Lib.split_after (n-1) thl ; + val (th2, th_after) = Lib.split_after (length gl2) th_rest ; + val th_result = th_before @ vf2 th2 :: th_after ; + in th_result end ; + in (gl_result, vf) end + handle _ => raise ERR "NTH_GOAL" "no nth subgoal in list" ; + +fun LASTGOAL tac gl1 = NTH_GOAL tac (length gl1) gl1 ; +fun HEADGOAL tac gl1 = NTH_GOAL tac 1 gl1 ; + +(*--------------------------------------------------------------------------- + * SPLIT_LT n (ltaca, ltacb) : A list_tactic that applies ltaca to the + first n goals, and ltacb to the rest + *---------------------------------------------------------------------------*) +fun SPLIT_LT n (ltaca, ltacb) gl = + let val (gla, glb) = Lib.split_after n gl ; + val (glra, vfa) = ltaca gla ; + val (glrb, vfb) = ltacb glb ; + fun vf ths = + let val (thsa, thsb) = Lib.split_after (length glra) ths ; + in vfa thsa @ vfb thsb end ; + in (glra @ glrb, vf) end ; + +(*--------------------------------------------------------------------------- + * ROTATE_LT n : + * A list_tactic that moves the first n goals to the end of the goal list + * first n goals + *---------------------------------------------------------------------------*) +fun ROTATE_LT n [] = ([], Lib.I) + | ROTATE_LT n gl = + let val lgl = length gl ; + val fixn = Int.mod (n, lgl) ; + val (gla, glb) = Lib.split_after fixn gl ; + fun vf ths = + let val (thsb, thsa) = Lib.split_after (lgl - fixn) ths ; + in thsa @ thsb end ; + in (glb @ gla, vf) end ; + (*--------------------------------------------------------------------------- * REVERSE tac: A tactical that reverses the list of subgoals of tac. * Intended for use with THEN1 to pick the `easy' subgoal, e.g.: @@ -178,6 +324,21 @@ fun REVERSE tac g = (rev gl, jf o rev) end +(*--------------------------------------------------------------------------- + * REVERSE_LT: A list_tactic that reverses a list of subgoals + *---------------------------------------------------------------------------*) + +fun REVERSE_LT gl = (rev gl, rev) ; + +(* for testing, redefine REVERSE +fun REVERSE tac = tac THEN_LT REVERSE_LT ; +*) + +(* for testing, redefine THEN and THENL +fun tac1 THENL tacs2 = tac1 THEN_LT TACS_TO_LT tacs2 ; +fun tac1 THEN tac2 = tac1 THEN_LT ALLGOALS tac2 ; +*) + (*--------------------------------------------------------------------------- * Fail with the given token. Useful in tactic programs to check that a * tactic produces no subgoals. Write @@ -193,11 +354,18 @@ fun FAIL_TAC tok (g: goal) = raise ERR "FAIL_TAC" tok fun NO_TAC g = FAIL_TAC "NO_TAC" g +(* for testing, redefine THEN1 +fun tac1 THEN1 tac2 = tac1 THEN_LT NTH_GOAL (tac2 THEN NO_TAC) 1 ; +fun tac1 THEN1 tac2 = tac1 THEN_LT REVERSE_LT THEN_LT + LASTGOAL (tac2 THEN NO_TAC) THEN_LT REVERSE_LT ; +*) + (*--------------------------------------------------------------------------- * Tactic that succeeds on all goals; identity for THEN *---------------------------------------------------------------------------*) val ALL_TAC: tactic = fn (g: goal) => ([g], hd) +val ALL_LT: list_tactic = fn (gl: goal list) => (gl, Lib.I) fun TRY tac = tac ORELSE ALL_TAC From ccb4b4eb329826ee2f37109fbbaa35b102024e4d Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Tue, 18 Nov 2014 15:59:40 +0000 Subject: [PATCH 028/718] Ensure the bit-string rotate operations is well-defined on empty lists. --- src/n-bit/bitstringScript.sml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/n-bit/bitstringScript.sml b/src/n-bit/bitstringScript.sml index e45cf13b9e..4d8d937a49 100644 --- a/src/n-bit/bitstringScript.sml +++ b/src/n-bit/bitstringScript.sml @@ -74,7 +74,7 @@ val rotate_def = Define` let l = LENGTH v in let x = m MOD l in - if x = 0 then v else field (x - 1) 0 v ++ field (l - 1) x v`; + if (l = 0) \/ (x = 0) then v else field (x - 1) 0 v ++ field (l - 1) x v`; val testbit_def = zDefine` testbit b v = (field b b v = [T])`; @@ -227,6 +227,15 @@ val length_w2v = Q.store_thm("length_w2v", `!w:'a word. LENGTH (w2v w) = dimindex(:'a)`, lrw [w2v_def]); +val length_rotate = Q.store_thm("length_rotate", + `!v n. LENGTH (rotate v n) = LENGTH v`, + simp [rotate_def] + \\ rw [length_field] + \\ fs [DECIDE ``n <> 0n ==> (SUC (n - 1) = n)``, + DECIDE ``n:num < l ==> (n + (l - n) = l)``, + arithmeticTheory.NOT_ZERO_LT_ZERO, arithmeticTheory.MOD_LESS] + ) + val el_rev_count_list = Q.store_thm("el_rev_count_list", `!n i. i < n ==> (EL i (rev_count_list n) = n - 1 - i)`, Induct \\ lrw [rev_count_list_def]); @@ -943,7 +952,7 @@ val ops_to_n2w = Q.store_thm("ops_to_n2w", val () = bossLib.export_rewrites ["length_w2v", "length_fixwidth", "length_field", - "length_bitify", "length_shiftr", + "length_bitify", "length_shiftr", "length_rotate", "v2w_w2v", "v2n_n2v", "v2w_n2v", "fixwidth_fixwidth", "fixwidth_id_imp"] From 06401b706a63de6bcd8a87a07fbdbc963c9749e3 Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Tue, 18 Nov 2014 16:08:27 +0000 Subject: [PATCH 029/718] Update for L3 machine-code examples. Some minor changes come from using the latest version of L3 when generating SML code. The ARMv8 model gains a function for encoding instructions (in the logic). The step tools are updated to support the NOP instruction. --- examples/l3-machine-code/arm/model/arm.sig | 4 +- examples/l3-machine-code/arm/model/arm.sml | 870 ++++++------ examples/l3-machine-code/arm8/model/arm8.sig | 2 +- examples/l3-machine-code/arm8/model/arm8.sml | 99 +- .../l3-machine-code/arm8/model/arm8Script.sml | 1257 ++++++++++++++++- .../arm8/model/arm8_encodeScript.sml | 48 + .../arm8/step/arm8_stepLib.sml | 16 +- examples/l3-machine-code/lib/L3.sig | 20 +- examples/l3-machine-code/lib/L3.sml | 45 +- examples/l3-machine-code/lib/Set.sig | 15 + examples/l3-machine-code/lib/Set.sml | 26 + examples/l3-machine-code/m0/model/m0.sig | 2 +- examples/l3-machine-code/m0/model/m0.sml | 38 +- examples/l3-machine-code/mips/model/mips.sig | 2 +- examples/l3-machine-code/mips/model/mips.sml | 24 +- examples/l3-machine-code/x64/model/x64.sig | 2 +- examples/l3-machine-code/x64/model/x64.sml | 35 +- 17 files changed, 1934 insertions(+), 571 deletions(-) create mode 100644 examples/l3-machine-code/arm8/model/arm8_encodeScript.sml create mode 100644 examples/l3-machine-code/lib/Set.sig create mode 100644 examples/l3-machine-code/lib/Set.sml diff --git a/examples/l3-machine-code/arm/model/arm.sig b/examples/l3-machine-code/arm/model/arm.sig index b6a76afd74..ad1a91f342 100644 --- a/examples/l3-machine-code/arm/model/arm.sig +++ b/examples/l3-machine-code/arm/model/arm.sig @@ -1,4 +1,4 @@ -(* arm - generated by L<3> - Fri May 16 15:32:26 2014 *) +(* arm - generated by L<3> - Tue Nov 18 15:31:11 2014 *) signature arm = sig @@ -1071,7 +1071,7 @@ val dfn'vstr: val dfn'UndefinedVFP: unit -> unit val Run: instruction -> unit val Fetch: unit -> MachineCode -val Take: (BitsN.nbit * bool) -> bool +val Do: (BitsN.nbit * bool) -> bool val Skip: unit -> instruction val UndefinedARM: BitsN.nbit -> instruction val UndefinedThumb: unit -> instruction diff --git a/examples/l3-machine-code/arm/model/arm.sml b/examples/l3-machine-code/arm/model/arm.sml index 7d6dab2323..d79169e2c3 100644 --- a/examples/l3-machine-code/arm/model/arm.sml +++ b/examples/l3-machine-code/arm/model/arm.sml @@ -1,4 +1,4 @@ -(* arm - generated by L<3> - Fri May 16 15:32:26 2014 *) +(* arm - generated by L<3> - Tue Nov 18 15:31:11 2014 *) structure arm :> arm = struct @@ -1735,26 +1735,26 @@ fun ArchVersion () = | ARMv7_R => 7; fun HaveDSPSupport () = - not(L3.mem((!Architecture),[ARMv4,ARMv4T,ARMv5T])); + not(Set.mem((!Architecture),[ARMv4,ARMv4T,ARMv5T])); -fun HaveThumb2 () = L3.mem((!Architecture),[ARMv6T2,ARMv7_A,ARMv7_R]); +fun HaveThumb2 () = Set.mem((!Architecture),[ARMv6T2,ARMv7_A,ARMv7_R]); fun HaveThumbEE () = ((!Architecture) = ARMv7_A) orelse (((!Architecture) = ARMv7_R) andalso - (L3.mem(Extension_ThumbEE,(!Extensions)))); + (Set.mem(Extension_ThumbEE,(!Extensions)))); fun HaveMPExt () = (Nat.>=(ArchVersion (),7)) andalso - (L3.mem(Extension_Multiprocessing,(!Extensions))); + (Set.mem(Extension_Multiprocessing,(!Extensions))); fun HaveSecurityExt () = - (L3.mem((!Architecture),[ARMv6K,ARMv7_A])) andalso - (L3.mem(Extension_Security,(!Extensions))); + (Set.mem((!Architecture),[ARMv6K,ARMv7_A])) andalso + (Set.mem(Extension_Security,(!Extensions))); fun HaveVirtExt () = (Nat.>=(ArchVersion (),7)) andalso - (L3.mem(Extension_Virtualization,(!Extensions))); + (Set.mem(Extension_Virtualization,(!Extensions))); fun rec'PSR x = {A = BitsN.bit(x,8), C = BitsN.bit(x,29), E = BitsN.bit(x,9), @@ -2361,7 +2361,7 @@ fun CurrentModeIsUserOrSystem () = then raise UNPREDICTABLE (("BadMode: ") ^ (BitsN.toHexString((#M) (!CPSR)))) else () - ; L3.mem((#M) (!CPSR),[BitsN.B(0x10,5),BitsN.B(0x1F,5)]) + ; Set.mem((#M) (!CPSR),[BitsN.B(0x10,5),BitsN.B(0x1F,5)]) ); fun CurrentModeIsHyp () = @@ -4058,7 +4058,7 @@ fun BankedRegisterAccessValid (SYSm,mode) = then if (BitsN.bits(SYSm,2,0)) = (BitsN.B(0x7,3)) then raise UNPREDICTABLE ("BankedRegisterAccessValid") else if (BitsN.bits(SYSm,2,0)) = (BitsN.B(0x6,3)) - then if L3.mem(mode,[BitsN.B(0x1A,5),BitsN.B(0x1F,5)]) + then if Set.mem(mode,[BitsN.B(0x1A,5),BitsN.B(0x1F,5)]) then raise UNPREDICTABLE ("BankedRegisterAccessValid") else () else if (BitsN.bits(SYSm,2,0)) = (BitsN.B(0x5,3)) @@ -4249,7 +4249,7 @@ fun DataProcessing (opc,(setflags,(d,(n,(imm32,C))))) = if (opc = (BitsN.B(0xD,4))) orelse ((opc = (BitsN.B(0xF,4))) andalso (n = (BitsN.B(0xF,4)))) then BitsN.B(0x0,32) - else if ((L3.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso + else if ((Set.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso (n = (BitsN.B(0xF,4)))) andalso (not setflags) then Align 32 (PC (),4) else R n @@ -4277,7 +4277,7 @@ fun DataProcessingPC (opc,(setflags,(n,(imm32,C)))) = if (opc = (BitsN.B(0xD,4))) orelse ((opc = (BitsN.B(0xF,4))) andalso (n = (BitsN.B(0xF,4)))) then BitsN.B(0x0,32) - else if ((L3.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso + else if ((Set.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso (n = (BitsN.B(0xF,4)))) andalso (not setflags) then Align 32 (PC (),4) else R n @@ -4921,7 +4921,7 @@ fun dfn'UnsignedAddSub16 (op',(d,(n,m))) = (w, if Int.>= (res1, - if L3.mem(op',[BitsN.B(0x1,2),BitsN.B(0x2,2)]) + if Set.mem(op',[BitsN.B(0x1,2),BitsN.B(0x2,2)]) then 0 else 65536) then BitsN.B(0x3,2) @@ -4937,7 +4937,7 @@ fun dfn'UnsignedAddSub16 (op',(d,(n,m))) = (w, if Int.>= (res2, - if L3.mem(op',[BitsN.B(0x2,2),BitsN.B(0x3,2)]) + if Set.mem(op',[BitsN.B(0x2,2),BitsN.B(0x3,2)]) then 0 else 65536) then BitsN.B(0x3,2) @@ -6738,12 +6738,14 @@ fun VFPExpandImm (imm8,single) = then BitsN.zeroExtend 64 (BitsN.concat [BitsN.bits(imm8,7,7),BitsN.~(BitsN.bits(imm8,6,6)), - BitsN.replicate(BitsN.bits(imm8,6,6),5), - BitsN.bits(imm8,5,0),BitsN.replicate(BitsN.B(0x0,1),19)]) + BitsN.resize_replicate 5 (BitsN.bits(imm8,6,6),5), + BitsN.bits(imm8,5,0), + BitsN.resize_replicate 19 (BitsN.B(0x0,1),19)]) else BitsN.concat [BitsN.bits(imm8,7,7),BitsN.~(BitsN.bits(imm8,6,6)), - BitsN.replicate(BitsN.bits(imm8,6,6),8),BitsN.bits(imm8,5,0), - BitsN.replicate(BitsN.B(0x0,1),48)]; + BitsN.resize_replicate 8 (BitsN.bits(imm8,6,6),8), + BitsN.bits(imm8,5,0), + BitsN.resize_replicate 48 (BitsN.B(0x0,1),48)]; fun FPCompare32 (op1,op2) = if ((fn _ => raise Fail "FP32_IsNan") op1) orelse @@ -7160,7 +7162,7 @@ fun Fetch () = end end; -fun Take (cond,defined) = +fun Do (cond,defined) = ( CurrentCondition := cond ; let val pass = ConditionPassed () @@ -7203,8 +7205,7 @@ fun DecodeHint (cond,op') = ((((BitsN.bits(op',7,4)) = (BitsN.B(0xF,4))) andalso ((!Encoding) = Encoding_ARM)) andalso ((!Architecture) = ARMv6K)) then NoOperation - else if Take - (cond, + else if Do(cond, (Nat.>=(ArchVersion (),7)) orelse (((!Encoding) = Encoding_ARM) andalso ((!Architecture) = ARMv6K))) then case boolify'8 op' of @@ -7585,7 +7586,7 @@ fun DecodeARM w = (_, (_, (E'0,(_,(false,(false,(false,(false,_)))))))))))))))))))))))) => - (if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) + (if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) then System (Setend ((BitsN.fromBitstring([E'0],1)) = @@ -7626,7 +7627,7 @@ fun DecodeARM w = val M = BitsN.fromBitstring([M'0],1) val imod = BitsN.fromBitstring([imod'1,imod'0],2) in - if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) + if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) then ( if ((((not(mode = (BitsN.B(0x0,5)))) andalso (M = (BitsN.B(0x0,1)))) orelse ((BitsN.bit(imod,1)) = @@ -7682,7 +7683,7 @@ fun DecodeARM w = (imm12'5, (imm12'4, (imm12'3,(imm12'2,(imm12'1,imm12'0))))))))))))))))))))))))))) => - (if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) + (if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) then let val add = (BitsN.fromBitstring([U'0],1)) = @@ -7729,7 +7730,7 @@ fun DecodeARM w = let val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) in - if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) + if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) then ( if Rm = (BitsN.B(0xF,4)) then DECODE_UNPREDICTABLE (mc,"PreloadInstruction (register)") @@ -7772,9 +7773,8 @@ fun DecodeARM w = (_, (_, (_,(_,(_,(false,(false,(false,(true,_)))))))))))))))))))))))) => - (if Take - (BitsN.B(0xE,4), - L3.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) + (if Do(BitsN.B(0xE,4), + Set.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) then ClearExclusive else Skip ()) | (false, @@ -7803,7 +7803,7 @@ fun DecodeARM w = (false, (option'3, (option'2,(option'1,option'0))))))))))))))))))))))))))) => - (if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) + (if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) then Hint (DataSynchronizationBarrier (BitsN.fromBitstring @@ -7835,7 +7835,7 @@ fun DecodeARM w = (true, (option'3, (option'2,(option'1,option'0))))))))))))))))))))))))))) => - (if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) + (if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) then Hint (DataMemoryBarrier (BitsN.fromBitstring @@ -7867,7 +7867,7 @@ fun DecodeARM w = (false, (option'3, (option'2,(option'1,option'0))))))))))))))))))))))))))) => - (if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) + (if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),7)) then Hint (InstructionSynchronizationBarrier (BitsN.fromBitstring @@ -7898,7 +7898,7 @@ fun DecodeARM w = (imm12'5, (imm12'4, (imm12'3,(imm12'2,(imm12'1,imm12'0))))))))))))))))))))))))))) => - (if Take(BitsN.B(0xE,4),HaveDSPSupport ()) + (if Do(BitsN.B(0xE,4),HaveDSPSupport ()) then let val add = (BitsN.fromBitstring([U'0],1)) = @@ -7941,11 +7941,10 @@ fun DecodeARM w = let val R = BitsN.fromBitstring([R'0],1) in - if Take - (BitsN.B(0xE,4), + if Do(BitsN.B(0xE,4), (((R = (BitsN.B(0x1,1))) andalso (Nat.>=(ArchVersion (),7))) andalso - (L3.mem(Extension_Multiprocessing,(!Extensions)))) orelse + (Set.mem(Extension_Multiprocessing,(!Extensions)))) orelse ((R = (BitsN.B(0x0,1))) andalso (HaveDSPSupport ()))) then let val add = @@ -7998,11 +7997,10 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val R = BitsN.fromBitstring([R'0],1) in - if Take - (BitsN.B(0xE,4), + if Do(BitsN.B(0xE,4), (((R = (BitsN.B(0x1,1))) andalso (Nat.>=(ArchVersion (),7))) andalso - (L3.mem(Extension_Multiprocessing,(!Extensions)))) orelse + (Set.mem(Extension_Multiprocessing,(!Extensions)))) orelse ((R = (BitsN.B(0x0,1))) andalso (HaveDSPSupport ()))) then let val is_pldw = R = (BitsN.B(0x0,1)) @@ -8058,7 +8056,7 @@ fun DecodeARM w = let val U = BitsN.fromBitstring([U'0],1) in - if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) + if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) then let val wback = (BitsN.fromBitstring([W'0],1)) = @@ -8087,7 +8085,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val U = BitsN.fromBitstring([U'0],1) in - if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) + if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) then ( if Rn = (BitsN.B(0xF,4)) then DECODE_UNPREDICTABLE (mc,"ReturnFromException") @@ -8132,7 +8130,7 @@ fun DecodeARM w = (imm24'5, (imm24'4, (imm24'3,(imm24'2,(imm24'1,imm24'0))))))))))))))))))))))))))) => - (if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),5)) + (if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),5)) then let val imm32 = BitsN.signExtend 32 @@ -8224,7 +8222,7 @@ fun DecodeARM w = let val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,HaveVirtExt ()) + if Do(cond,HaveVirtExt ()) then ( if Rd = (BitsN.B(0xF,4)) then DECODE_UNPREDICTABLE (mc,"MoveToRegisterFromBankedOrSpecial") @@ -8268,7 +8266,7 @@ fun DecodeARM w = let val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,true) + if Do(cond,true) then ( if Rd = (BitsN.B(0xF,4)) then DECODE_UNPREDICTABLE (mc,"MoveToRegisterFromSpecial") @@ -8309,8 +8307,8 @@ fun DecodeARM w = let val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,HaveVirtExt ()) - then ( if L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(cond,HaveVirtExt ()) + then ( if Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE (mc,"MoveToBankedOrSpecialRegister") else () @@ -8359,7 +8357,7 @@ fun DecodeARM w = val mask = BitsN.fromBitstring([mask'3,mask'2,mask'1,mask'0],4) in - if Take(cond,true) + if Do(cond,true) then ( if (Rn = (BitsN.B(0xF,4))) orelse (mask = (BitsN.B(0x0,4))) then DECODE_UNPREDICTABLE @@ -8400,7 +8398,7 @@ fun DecodeARM w = (false, (false, (false,(true,(Rm'3,(Rm'2,(Rm'1,Rm'0))))))))))))))))))))))))))) => - (if Take(cond,not((!Architecture) = ARMv4)) + (if Do(cond,not((!Architecture) = ARMv4)) then Branch (BranchExchange (BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4))) @@ -8432,7 +8430,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),5)) + if Do(cond,Nat.>=(ArchVersion (),5)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rm = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE @@ -8468,7 +8466,7 @@ fun DecodeARM w = let val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) in - if Take(cond,Nat.>=(ArchVersion (),5)) + if Do(cond,Nat.>=(ArchVersion (),5)) then ( if Rm = (BitsN.B(0xF,4)) then DECODE_UNPREDICTABLE (mc,"BranchLinkExchangeRegister") @@ -8505,7 +8503,7 @@ fun DecodeARM w = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,HaveDSPSupport ()) + if Do(cond,HaveDSPSupport ()) then ( if ((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4))) @@ -8562,7 +8560,7 @@ fun DecodeARM w = Hint(Breakpoint imm32) end ) - else if Take(cond,false) + else if Do(cond,false) then Undefined(BitsN.B(0x0,32)) else NoOperation) | (false, @@ -8589,7 +8587,7 @@ fun DecodeARM w = (true, (true, (true,(imm4'3,(imm4'2,(imm4'1,imm4'0))))))))))))))))))))))))))) => - (if Take(cond,HaveVirtExt ()) + (if Do(cond,HaveVirtExt ()) then ( if not(cond = (BitsN.B(0xE,4))) then DECODE_UNPREDICTABLE(mc,"HypervisorCall") else () @@ -8631,7 +8629,7 @@ fun DecodeARM w = (true, (true, (true,(imm4'3,(imm4'2,(imm4'1,imm4'0))))))))))))))))))))))))))) => - (if Take(cond,HaveSecurityExt ()) + (if Do(cond,HaveSecurityExt ()) then System (SecureMonitorCall (BitsN.fromBitstring @@ -8666,7 +8664,7 @@ fun DecodeARM w = val Ra = BitsN.fromBitstring([Ra'3,Ra'2,Ra'1,Ra'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,HaveDSPSupport ()) + if Do(cond,HaveDSPSupport ()) then ( if (((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4)))) orelse @@ -8718,7 +8716,7 @@ fun DecodeARM w = val Ra = BitsN.fromBitstring([Ra'3,Ra'2,Ra'1,Ra'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,HaveDSPSupport ()) + if Do(cond,HaveDSPSupport ()) then ( if (((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4)))) orelse @@ -8766,7 +8764,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,HaveDSPSupport ()) + if Do(cond,HaveDSPSupport ()) then ( if ((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4))) @@ -8816,7 +8814,7 @@ fun DecodeARM w = val RdHi = BitsN.fromBitstring([RdHi'3,RdHi'2,RdHi'1,RdHi'0],4) in - if Take(cond,HaveDSPSupport ()) + if Do(cond,HaveDSPSupport ()) then ( if (((RdLo = (BitsN.B(0xF,4))) orelse (RdHi = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse @@ -8867,7 +8865,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,HaveDSPSupport ()) + if Do(cond,HaveDSPSupport ()) then ( if ((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4))) @@ -8913,7 +8911,7 @@ fun DecodeARM w = (true, (true, (false,(true,(true,(true,false))))))))))))))))))))))))))) => - if Take(cond,HaveVirtExt ()) + if Do(cond,HaveVirtExt ()) then System ExceptionReturn else Skip () | (false, @@ -8956,7 +8954,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val opc = BitsN.fromBitstring([opc'3,opc'2,opc'1,opc'0],4) in - if Take(cond,true) + if Do(cond,true) then let val setflags = (BitsN.fromBitstring([S'0],1)) = @@ -8972,7 +8970,7 @@ fun DecodeARM w = (TestCompareRegister (BitsN.bits(opc,1,0), (Rn,(Rm,(shift_t,shift_n))))) - else if L3.mem + else if Set.mem (opc,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then Data (ShiftImmediate @@ -9016,7 +9014,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val opc = BitsN.fromBitstring([opc'3,opc'2,opc'1,opc'0],4) in - if Take(cond,true) + if Do(cond,true) then ( if ((((Rd = (BitsN.B(0xF,4))) andalso (not((BitsN.bits(opc,3,2)) = (BitsN.B(0x2,2))))) orelse @@ -9078,7 +9076,7 @@ fun DecodeARM w = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val A = BitsN.fromBitstring([A'0],1) in - if Take(cond,true) + if Do(cond,true) then ( if ((((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4)))) orelse @@ -9132,7 +9130,7 @@ fun DecodeARM w = val RdHi = BitsN.fromBitstring([RdHi'3,RdHi'2,RdHi'1,RdHi'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if ((((RdHi = (BitsN.B(0xF,4))) orelse (RdLo = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse @@ -9175,7 +9173,7 @@ fun DecodeARM w = val Ra = BitsN.fromBitstring([Ra'3,Ra'2,Ra'1,Ra'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,HaveThumb2 ()) + if Do(cond,HaveThumb2 ()) then ( if (((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4)))) orelse @@ -9217,7 +9215,7 @@ fun DecodeARM w = val RdHi = BitsN.fromBitstring([RdHi'3,RdHi'2,RdHi'1,RdHi'0],4) in - if Take(cond,true) + if Do(cond,true) then ( if (((((RdLo = (BitsN.B(0xF,4))) orelse (RdHi = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse @@ -9274,7 +9272,7 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,true) + if Do(cond,true) then ( if ((((Rt = (BitsN.B(0xF,4))) orelse (Rt2 = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rn = Rt)) orelse @@ -9319,7 +9317,7 @@ fun DecodeARM w = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if ((((Rd = (BitsN.B(0xF,4))) orelse (Rt = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rd = Rn)) orelse @@ -9352,7 +9350,7 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rt = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE(mc,"LoadExclusive") @@ -9389,8 +9387,8 @@ fun DecodeARM w = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take - (cond,L3.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) + if Do(cond, + Set.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) then let val Rt2 = BitsN.+(Rt,BitsN.B(0x1,4)) in @@ -9429,8 +9427,8 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take - (cond,L3.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) + if Do(cond, + Set.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) then let val Rt2 = BitsN.+(Rt,BitsN.B(0x1,4)) in @@ -9473,8 +9471,8 @@ fun DecodeARM w = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take - (cond,L3.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) + if Do(cond, + Set.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) then ( if ((((Rd = (BitsN.B(0xF,4))) orelse (Rt = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rd = Rn)) orelse @@ -9507,8 +9505,8 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take - (cond,L3.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) + if Do(cond, + Set.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) then ( if (Rt = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE @@ -9546,8 +9544,8 @@ fun DecodeARM w = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take - (cond,L3.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) + if Do(cond, + Set.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) then ( if ((((Rd = (BitsN.B(0xF,4))) orelse (Rt = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rd = Rn)) orelse @@ -9580,8 +9578,8 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take - (cond,L3.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) + if Do(cond, + Set.mem((!Architecture),[ARMv6K,ARMv7_A,ARMv7_R])) then ( if (Rt = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE @@ -9619,7 +9617,7 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,HaveThumb2 ()) + if Do(cond,HaveThumb2 ()) then ( if (((Rt = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rn = Rt)) orelse (Rm = (BitsN.B(0xF,4))) @@ -9669,7 +9667,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val P = BitsN.fromBitstring([P'0],1) in - if Take(cond,true) + if Do(cond,true) then let val wback = (P = (BitsN.B(0x0,1))) orelse @@ -9729,8 +9727,7 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take - (cond, + if Do(cond, ((not(H = (BitsN.B(0x0,1)))) orelse (S = (BitsN.B(0x1,1)))) andalso (HaveThumb2 ())) then ( if (((Rt = (BitsN.B(0xF,4))) orelse @@ -9790,8 +9787,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val P = BitsN.fromBitstring([P'0],1) in - if Take - (cond, + if Do(cond, (not(H = (BitsN.B(0x0,1)))) orelse (S = (BitsN.B(0x1,1)))) then let @@ -9859,7 +9855,7 @@ fun DecodeARM w = val W = BitsN.fromBitstring([W'0],1) val P = BitsN.fromBitstring([P'0],1) in - if Take(cond,HaveDSPSupport ()) + if Do(cond,HaveDSPSupport ()) then let val Rt2 = BitsN.+(Rt,BitsN.B(0x1,4)) val wback = @@ -9930,7 +9926,7 @@ fun DecodeARM w = let val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(cond,HaveDSPSupport ()) + if Do(cond,HaveDSPSupport ()) then let val Rt2 = BitsN.+(Rt,BitsN.B(0x1,4)) in @@ -9989,7 +9985,7 @@ fun DecodeARM w = val W = BitsN.fromBitstring([W'0],1) val P = BitsN.fromBitstring([P'0],1) in - if Take(cond,HaveDSPSupport ()) + if Do(cond,HaveDSPSupport ()) then let val Rt2 = BitsN.+(Rt,BitsN.B(0x1,4)) val wback = @@ -10066,8 +10062,7 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take - (cond, + if Do(cond, ((not(H = (BitsN.B(0x0,1)))) orelse (S = (BitsN.B(0x1,1)))) andalso (HaveThumb2 ())) then ( if ((Rt = (BitsN.B(0xF,4))) orelse @@ -10132,8 +10127,7 @@ fun DecodeARM w = val S = BitsN.fromBitstring([S'0],1) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (cond, + if Do(cond, (not(H = (BitsN.B(0x0,1)))) orelse (S = (BitsN.B(0x1,1)))) then ( if Rt = (BitsN.B(0xF,4)) @@ -10196,8 +10190,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val P = BitsN.fromBitstring([P'0],1) in - if Take - (cond, + if Do(cond, (not(H = (BitsN.B(0x0,1)))) orelse (S = (BitsN.B(0x1,1)))) then let @@ -10270,7 +10263,7 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,HaveThumb2 ()) + if Do(cond,HaveThumb2 ()) then ( if ((Rt = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rn = Rt) then DECODE_UNPREDICTABLE @@ -10327,7 +10320,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val P = BitsN.fromBitstring([P'0],1) in - if Take(cond,true) + if Do(cond,true) then let val wback = (P = (BitsN.B(0x0,1))) orelse @@ -10389,7 +10382,7 @@ fun DecodeARM w = let val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,HaveThumb2 ()) + if Do(cond,HaveThumb2 ()) then ( if Rd = (BitsN.B(0xF,4)) then DECODE_UNPREDICTABLE(mc,"MoveTopHalfword") else () @@ -10467,7 +10460,7 @@ fun DecodeARM w = val mask = BitsN.fromBitstring([mask'3,mask'2,mask'1,mask'0],4) in - if Take(cond,true) + if Do(cond,true) then ( if mask = (BitsN.B(0x0,4)) then DECODE_UNPREDICTABLE (mc,"MoveToSpecialFromImmediate") @@ -10524,7 +10517,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val opc = BitsN.fromBitstring([opc'3,opc'2,opc'1,opc'0],4) in - if Take(cond,true) + if Do(cond,true) then let val setflags = (BitsN.fromBitstring([S'0],1)) = @@ -10580,7 +10573,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val B = BitsN.fromBitstring([B'0],1) in - if Take(cond,true) + if Do(cond,true) then ( if (((B = (BitsN.B(0x1,1))) andalso (Rt = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rn = Rt) @@ -10642,7 +10635,7 @@ fun DecodeARM w = val B = BitsN.fromBitstring([B'0],1) val P = BitsN.fromBitstring([P'0],1) in - if Take(cond,true) + if Do(cond,true) then let val wback = (P = (BitsN.B(0x0,1))) orelse @@ -10710,7 +10703,7 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,true) + if Do(cond,true) then ( if ((Rt = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rn = Rt) then DECODE_UNPREDICTABLE @@ -10770,7 +10763,7 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val B = BitsN.fromBitstring([B'0],1) in - if Take(cond,true) + if Do(cond,true) then ( if (B = (BitsN.B(0x1,1))) andalso (Rt = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE @@ -10826,7 +10819,7 @@ fun DecodeARM w = val B = BitsN.fromBitstring([B'0],1) val P = BitsN.fromBitstring([P'0],1) in - if Take(cond,true) + if Do(cond,true) then let val wback = (P = (BitsN.B(0x0,1))) orelse @@ -10894,7 +10887,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val B = BitsN.fromBitstring([B'0],1) in - if Take(cond,true) + if Do(cond,true) then ( if (((((B = (BitsN.B(0x1,1))) andalso (Rt = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rn = Rt)) orelse @@ -10956,7 +10949,7 @@ fun DecodeARM w = val B = BitsN.fromBitstring([B'0],1) val P = BitsN.fromBitstring([P'0],1) in - if Take(cond,true) + if Do(cond,true) then let val wback = (P = (BitsN.B(0x0,1))) orelse @@ -11025,7 +11018,7 @@ fun DecodeARM w = val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,true) + if Do(cond,true) then ( if ((((Rt = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rn = Rt)) orelse (Rm = (BitsN.B(0xF,4)))) orelse @@ -11087,7 +11080,7 @@ fun DecodeARM w = val B = BitsN.fromBitstring([B'0],1) val P = BitsN.fromBitstring([P'0],1) in - if Take(cond,true) + if Do(cond,true) then let val wback = (P = (BitsN.B(0x0,1))) orelse @@ -11157,7 +11150,7 @@ fun DecodeARM w = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if ((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4))) @@ -11200,7 +11193,7 @@ fun DecodeARM w = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if ((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4))) @@ -11249,7 +11242,7 @@ fun DecodeARM w = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if ((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4))) @@ -11289,7 +11282,7 @@ fun DecodeARM w = BitsN.fromBitstring ([sat_imm'4,sat_imm'3,sat_imm'2,sat_imm'1,sat_imm'0],5) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE(mc,"Saturate") @@ -11348,7 +11341,7 @@ fun DecodeARM w = BitsN.fromBitstring ([sat_imm'3,sat_imm'2,sat_imm'1,sat_imm'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE(mc,"Saturate16") @@ -11395,7 +11388,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rm = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE(mc,"ExtendByte16") @@ -11448,7 +11441,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rm = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE(mc,"ExtendByte") @@ -11501,7 +11494,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rm = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE(mc,"ExtendHalfword") @@ -11554,7 +11547,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rm = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE(mc,"ByteReverse") @@ -11590,7 +11583,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rm = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE @@ -11627,7 +11620,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rm = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE @@ -11664,7 +11657,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (Rd = (BitsN.B(0xF,4))) orelse (Rm = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE(mc,"ReverseBits") @@ -11701,7 +11694,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if ((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4))) @@ -11760,7 +11753,7 @@ fun DecodeARM w = val RdHi = BitsN.fromBitstring([RdHi'3,RdHi'2,RdHi'1,RdHi'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (((RdLo = (BitsN.B(0xF,4))) orelse (RdHi = (BitsN.B(0xF,4)))) orelse (Rn = (BitsN.B(0xF,4)))) orelse @@ -11811,7 +11804,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if ((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4))) @@ -11864,7 +11857,7 @@ fun DecodeARM w = val Ra = BitsN.fromBitstring([Ra'3,Ra'2,Ra'1,Ra'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if (((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4)))) orelse @@ -11913,7 +11906,7 @@ fun DecodeARM w = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then ( if ((Rd = (BitsN.B(0xF,4))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rm = (BitsN.B(0xF,4))) @@ -11957,7 +11950,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then let val lsbit = BitsN.toNat @@ -12014,7 +12007,7 @@ fun DecodeARM w = let val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(cond,Nat.>=(ArchVersion (),6)) + if Do(cond,Nat.>=(ArchVersion (),6)) then let val lsbit = BitsN.toNat @@ -12076,7 +12069,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val U = BitsN.fromBitstring([U'0],1) in - if Take(cond,true) + if Do(cond,true) then ( if (Rn = (BitsN.B(0xF,4))) orelse (Nat.<(BitCount 16 registers,1)) then DECODE_UNPREDICTABLE @@ -12130,7 +12123,7 @@ fun DecodeARM w = registers'3,registers'2,registers'1,registers'0],16) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,true) + if Do(cond,true) then ( if (Rn = (BitsN.B(0xF,4))) orelse (Nat.<(BitCount 16 registers,1)) then DECODE_UNPREDICTABLE(mc,"StoreMultiple") @@ -12190,7 +12183,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val U = BitsN.fromBitstring([U'0],1) in - if Take(cond,true) + if Do(cond,true) then ( if (Rn = (BitsN.B(0xF,4))) orelse (Nat.<(BitCount 15 registers,1)) then DECODE_UNPREDICTABLE @@ -12245,7 +12238,7 @@ fun DecodeARM w = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val U = BitsN.fromBitstring([U'0],1) in - if Take(cond,true) + if Do(cond,true) then let val wback = (BitsN.fromBitstring([W'0],1)) = @@ -12308,7 +12301,7 @@ fun DecodeARM w = registers'3,registers'2,registers'1,registers'0],16) val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(cond,true) + if Do(cond,true) then let val wback = (BitsN.fromBitstring([W'0],1)) = @@ -12362,7 +12355,7 @@ fun DecodeARM w = (imm24'5, (imm24'4, (imm24'3,(imm24'2,(imm24'1,imm24'0))))))))))))))))))))))))))) => - (if Take(cond,true) + (if Do(cond,true) then let val imm32 = BitsN.signExtend 32 @@ -12404,7 +12397,7 @@ fun DecodeARM w = (imm24'5, (imm24'4, (imm24'3,(imm24'2,(imm24'1,imm24'0))))))))))))))))))))))))))) => - (if Take(cond,true) + (if Do(cond,true) then let val imm32 = BitsN.signExtend 32 @@ -12449,7 +12442,7 @@ fun DecodeARM w = (imm24'5, (imm24'4, (imm24'3,(imm24'2,(imm24'1,imm24'0))))))))))))))))))))))))))) => - (if Take(cond,true) + (if Do(cond,true) then let val imm32 = BitsN.signExtend 32 @@ -12473,7 +12466,7 @@ fun DecodeARM w = (_, (_, (_,(_,(_,(_,(_,(_,(_,(_,(true,(false,(true,_))))))))))))))))))) => - (if Take(cond,L3.mem(Extension_VFP,(!Extensions))) + (if Do(cond,Set.mem(Extension_VFP,(!Extensions))) then VFP(DecodeVFP w) else Skip ()) | _ => UndefinedARM cond @@ -12492,7 +12485,7 @@ fun DecodeThumb h = (false, (S'0, (Rm'2,(Rm'1,(Rm'0,(Rn'2,(Rn'1,(Rn'0,(Rd'2,(Rd'1,Rd'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val d = BitsN.fromNat @@ -12527,7 +12520,7 @@ fun DecodeThumb h = (S'0, (imm3'2, (imm3'1,(imm3'0,(Rn'2,(Rn'1,(Rn'0,(Rd'2,(Rd'1,Rd'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val d = BitsN.fromNat @@ -12558,7 +12551,7 @@ fun DecodeThumb h = (imm5'3, (imm5'2, (imm5'1,(imm5'0,(Rm'2,(Rm'1,(Rm'0,(Rd'2,(Rd'1,Rd'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val d = BitsN.fromNat @@ -12591,7 +12584,7 @@ fun DecodeThumb h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val d = BitsN.fromNat @@ -12619,7 +12612,7 @@ fun DecodeThumb h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val n = BitsN.fromNat @@ -12645,7 +12638,7 @@ fun DecodeThumb h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val d = BitsN.fromNat @@ -12680,7 +12673,7 @@ fun DecodeThumb h = val Rx = BitsN.fromBitstring([Rx'2,Rx'1,Rx'0],3) val opc = BitsN.fromBitstring([opc'3,opc'2,opc'1,opc'0],4) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then case opc of BitsN.B(0x0,4) => let @@ -12909,8 +12902,7 @@ fun DecodeThumb h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val DN = BitsN.fromBitstring([DN'0],1) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), ((BitsN.msb Rm) orelse (DN = (BitsN.B(0x1,1)))) orelse (HaveThumb2 ())) then let @@ -12953,7 +12945,7 @@ fun DecodeThumb h = let val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val n = BitsN.@@ @@ -12985,8 +12977,7 @@ fun DecodeThumb h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val D = BitsN.fromBitstring([D'0],1) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), ((BitsN.msb Rm) orelse (D = (BitsN.B(0x1,1)))) orelse (Nat.>=(ArchVersion (),6))) then let @@ -13015,7 +13006,7 @@ fun DecodeThumb h = (false, (false, (true,(true,(true,(false,(Rm'3,(Rm'2,(Rm'1,(Rm'0,_))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then ( if (InITBlock ()) andalso (not(LastInITBlock ())) then DECODE_UNPREDICTABLE(mc,"BranchExchange") else () @@ -13033,7 +13024,7 @@ fun DecodeThumb h = let val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) in - if Take(ThumbCondition (),Nat.>=(ArchVersion (),5)) + if Do(ThumbCondition (),Nat.>=(ArchVersion (),5)) then ( if (Rm = (BitsN.B(0xF,4))) orelse ((InITBlock ()) andalso (not(LastInITBlock ()))) then DECODE_UNPREDICTABLE @@ -13054,7 +13045,7 @@ fun DecodeThumb h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val add = true val imm32 = @@ -13085,7 +13076,7 @@ fun DecodeThumb h = val Rt = BitsN.fromBitstring([Rt'2,Rt'1,Rt'0],3) val Rn = BitsN.fromBitstring([Rn'2,Rn'1,Rn'0],3) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val index = true val add = true @@ -13184,7 +13175,7 @@ fun DecodeThumb h = val Rt = BitsN.fromBitstring([Rt'2,Rt'1,Rt'0],3) val Rn = BitsN.fromBitstring([Rn'2,Rn'1,Rn'0],3) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val index = true val add = true @@ -13228,7 +13219,7 @@ fun DecodeThumb h = val Rt = BitsN.fromBitstring([Rt'2,Rt'1,Rt'0],3) val Rn = BitsN.fromBitstring([Rn'2,Rn'1,Rn'0],3) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val index = true val add = true @@ -13271,7 +13262,7 @@ fun DecodeThumb h = val Rt = BitsN.fromBitstring([Rt'2,Rt'1,Rt'0],3) val Rn = BitsN.fromBitstring([Rn'2,Rn'1,Rn'0],3) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val index = true val add = true @@ -13317,7 +13308,7 @@ fun DecodeThumb h = let val Rt = BitsN.fromBitstring([Rt'2,Rt'1,Rt'0],3) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val index = true val add = true @@ -13359,7 +13350,7 @@ fun DecodeThumb h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val imm12 = BitsN.@@ @@ -13393,7 +13384,7 @@ fun DecodeThumb h = (S'0, (imm7'6, (imm7'5,(imm7'4,(imm7'3,(imm7'2,(imm7'1,imm7'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val imm12 = BitsN.@@ @@ -13422,7 +13413,7 @@ fun DecodeThumb h = (true, (imm5'4, (imm5'3,(imm5'2,(imm5'1,(imm5'0,(Rn'2,(Rn'1,Rn'0))))))))))))))) => - (if Take(BitsN.B(0xE,4),HaveThumb2 ()) + (if Do(BitsN.B(0xE,4),HaveThumb2 ()) then ( if InITBlock () then DECODE_UNPREDICTABLE(mc,"CompareBranch") else () @@ -13455,7 +13446,7 @@ fun DecodeThumb h = (false, (true, (false,(U'0,(false,(Rm'2,(Rm'1,(Rm'0,(Rd'2,(Rd'1,Rd'0))))))))))))))) => - (if Take(ThumbCondition (),Nat.>=(ArchVersion (),6)) + (if Do(ThumbCondition (),Nat.>=(ArchVersion (),6)) then let val unsigned = (BitsN.fromBitstring([U'0],1)) = (BitsN.B(0x1,1)) @@ -13481,7 +13472,7 @@ fun DecodeThumb h = (false, (true, (false,(U'0,(true,(Rm'2,(Rm'1,(Rm'0,(Rd'2,(Rd'1,Rd'0))))))))))))))) => - (if Take(ThumbCondition (),Nat.>=(ArchVersion (),6)) + (if Do(ThumbCondition (),Nat.>=(ArchVersion (),6)) then let val unsigned = (BitsN.fromBitstring([U'0],1)) = (BitsN.B(0x1,1)) @@ -13513,7 +13504,7 @@ fun DecodeThumb h = (register_list'4, (register_list'3, (register_list'2,(register_list'1,register_list'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val registers = BitsN.concat @@ -13546,7 +13537,7 @@ fun DecodeThumb h = (true, (true, (false,(true,(true,(false,(false,(true,(false,(_,(E'0,_))))))))))))) => - (if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) + (if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) then ( if InITBlock () then DECODE_UNPREDICTABLE(mc,"Setend") else () @@ -13571,7 +13562,7 @@ fun DecodeThumb h = val I = BitsN.fromBitstring([I'0],1) val A = BitsN.fromBitstring([A'0],1) in - if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) + if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),6)) then ( if ((BitsN.concat[A,I,F]) = (BitsN.B(0x0,3))) orelse (InITBlock ()) then DECODE_UNPREDICTABLE(mc,"ChangeProcessorState") @@ -13604,7 +13595,7 @@ fun DecodeThumb h = val Rd = BitsN.fromBitstring([Rd'2,Rd'1,Rd'0],3) val Rm = BitsN.fromBitstring([Rm'2,Rm'1,Rm'0],3) in - if Take(ThumbCondition (),Nat.>=(ArchVersion (),6)) + if Do(ThumbCondition (),Nat.>=(ArchVersion (),6)) then case BitsN.fromBitstring([opc'1,opc'0],2) of BitsN.B(0x0,2) => Media @@ -13638,7 +13629,7 @@ fun DecodeThumb h = (register_list'4, (register_list'3, (register_list'2,(register_list'1,register_list'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val registers = BitsN.concat @@ -13678,7 +13669,7 @@ fun DecodeThumb h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0))))))))))))))) => - (if Take(BitsN.B(0xE,4),Nat.>=(ArchVersion (),5)) + (if Do(BitsN.B(0xE,4),Nat.>=(ArchVersion (),5)) then let val imm32 = BitsN.zeroExtend 32 @@ -13720,7 +13711,7 @@ fun DecodeThumb h = BitsN.fromBitstring ([firstcond'3,firstcond'2,firstcond'1,firstcond'0],4) in - if Take(BitsN.B(0xE,4),HaveThumb2 ()) + if Do(BitsN.B(0xE,4),HaveThumb2 ()) then ( if ((firstcond = (BitsN.B(0xF,4))) orelse ((firstcond = (BitsN.B(0xE,4))) andalso (not((BitCount 4 mask) = 1)))) orelse @@ -13745,7 +13736,7 @@ fun DecodeThumb h = (register_list'4, (register_list'3, (register_list'2,(register_list'1,register_list'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val registers = BitsN.fromNat @@ -13794,7 +13785,7 @@ fun DecodeThumb h = let val Rn = BitsN.fromBitstring([Rn'2,Rn'1,Rn'0],3) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val registers = BitsN.fromNat @@ -13836,7 +13827,7 @@ fun DecodeThumb h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val imm32 = BitsN.zeroExtend 32 @@ -13858,7 +13849,7 @@ fun DecodeThumb h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then System (SupervisorCall (BitsN.zeroExtend 32 @@ -13877,8 +13868,7 @@ fun DecodeThumb h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0))))))))))))))) => - (if Take - (BitsN.fromBitstring([cond'3,cond'2,cond'1,cond'0],4),true) + (if Do(BitsN.fromBitstring([cond'3,cond'2,cond'1,cond'0],4),true) then ( if InITBlock () then DECODE_UNPREDICTABLE(mc,"BranchTarget") else () @@ -13905,7 +13895,7 @@ fun DecodeThumb h = (imm11'7, (imm11'6, (imm11'5,(imm11'4,(imm11'3,(imm11'2,(imm11'1,imm11'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then ( if (InITBlock ()) andalso (not(LastInITBlock ())) then DECODE_UNPREDICTABLE(mc,"BranchTarget") else () @@ -13942,7 +13932,7 @@ fun DecodeThumbEE h = val Rt = BitsN.fromBitstring([Rt'2,Rt'1,Rt'0],3) val Rn = BitsN.fromBitstring([Rn'2,Rn'1,Rn'0],3) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val index = true val add = true @@ -14013,7 +14003,7 @@ fun DecodeThumbEE h = (imm3'1, (imm3'0, (handler'4,(handler'3,(handler'2,(handler'1,handler'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then ( if (InITBlock ()) andalso (not(LastInITBlock ())) then DECODE_UNPREDICTABLE(mc,"HandlerBranchParameter") else () @@ -14046,7 +14036,7 @@ fun DecodeThumbEE h = (handler'6, (handler'5, (handler'4,(handler'3,(handler'2,(handler'1,handler'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then ( if (InITBlock ()) andalso (not(LastInITBlock ())) then DECODE_UNPREDICTABLE(mc,"HandlerBranchLink") else () @@ -14078,7 +14068,7 @@ fun DecodeThumbEE h = (imm5'1, (imm5'0, (handler'4,(handler'3,(handler'2,(handler'1,handler'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then ( if (InITBlock ()) andalso (not(LastInITBlock ())) then DECODE_UNPREDICTABLE (mc,"HandlerBranchLinkParameter") @@ -14109,7 +14099,7 @@ fun DecodeThumbEE h = (false, (imm3'2, (imm3'1,(imm3'0,(Rn'2,(Rn'1,(Rn'0,(Rt'2,(Rt'1,Rt'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val index = true val add = false @@ -14147,7 +14137,7 @@ fun DecodeThumbEE h = let val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val n = BitsN.@@ @@ -14155,7 +14145,7 @@ fun DecodeThumbEE h = BitsN.fromBitstring([Rn'2,Rn'1,Rn'0],3)) in ( if (n = (BitsN.B(0xF,4))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"CheckArray") else () ; Branch(CheckArray(Rm,n)) @@ -14173,7 +14163,7 @@ fun DecodeThumbEE h = (true, (imm5'4, (imm5'3,(imm5'2,(imm5'1,(imm5'0,(Rt'2,(Rt'1,Rt'0))))))))))))))) => - (if Take(ThumbCondition (),true) + (if Do(ThumbCondition (),true) then let val index = true val add = true @@ -14210,7 +14200,7 @@ fun DecodeThumbEE h = let val Rt = BitsN.fromBitstring([Rt'2,Rt'1,Rt'0],3) in - if Take(ThumbCondition (),true) + if Do(ThumbCondition (),true) then let val index = true val add = true @@ -14290,7 +14280,7 @@ fun DecodeThumb2 h = let val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then let val registers = BitsN.concat @@ -14351,7 +14341,7 @@ fun DecodeThumb2 h = let val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then let val registers = BitsN.concat @@ -14414,7 +14404,7 @@ fun DecodeThumb2 h = val M = BitsN.fromBitstring([M'0],1) val P = BitsN.fromBitstring([P'0],1) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then let val registers = BitsN.concat @@ -14480,7 +14470,7 @@ fun DecodeThumb2 h = val M = BitsN.fromBitstring([M'0],1) val P = BitsN.fromBitstring([P'0],1) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then let val registers = BitsN.concat @@ -14534,9 +14524,8 @@ fun DecodeThumb2 h = let val op' = BitsN.fromBitstring([op'1,op'0],2) in - if Take - (ThumbCondition (), - (L3.mem(op',[BitsN.B(0x0,2),BitsN.B(0x3,2)])) andalso + if Do(ThumbCondition (), + (Set.mem(op',[BitsN.B(0x0,2),BitsN.B(0x3,2)])) andalso (HaveThumb2 ())) then ( if (CurrentInstrSet ()) = InstrSet_ThumbEE then DECODE_UNPREDICTABLE(mc,"StoreReturnState") @@ -14571,9 +14560,8 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val op' = BitsN.fromBitstring([op'1,op'0],2) in - if Take - (ThumbCondition (), - (L3.mem(op',[BitsN.B(0x0,2),BitsN.B(0x3,2)])) andalso + if Do(ThumbCondition (), + (Set.mem(op',[BitsN.B(0x0,2),BitsN.B(0x3,2)])) andalso (HaveThumb2 ())) then ( if (((CurrentInstrSet ()) = InstrSet_ThumbEE) orelse (Rn = (BitsN.B(0xF,4)))) orelse @@ -14618,9 +14606,9 @@ fun DecodeThumb2 h = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if ((((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if ((((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rd = Rn)) orelse (Rd = Rt) then DECODE_UNPREDICTABLE(mc,"StoreExclusive") @@ -14662,8 +14650,8 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if (L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if (Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse (Rn = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE(mc,"StoreExclusive") else () @@ -14702,9 +14690,9 @@ fun DecodeThumb2 h = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),Nat.>=(ArchVersion (),7)) - then ( if ((((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + if Do(ThumbCondition (),Nat.>=(ArchVersion (),7)) + then ( if ((((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rd = Rn)) orelse (Rd = Rt) then DECODE_UNPREDICTABLE @@ -14740,10 +14728,10 @@ fun DecodeThumb2 h = val Rt2 = BitsN.fromBitstring([Rt2'3,Rt2'2,Rt2'1,Rt2'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),Nat.>=(ArchVersion (),7)) - then ( if (((((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + if Do(ThumbCondition (),Nat.>=(ArchVersion (),7)) + then ( if (((((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse (Rn = (BitsN.B(0xF,4)))) orelse (Rd = Rn)) orelse (Rd = Rt) then DECODE_UNPREDICTABLE @@ -14774,9 +14762,9 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if ((Rn = (BitsN.B(0xD,4))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse ((InITBlock ()) andalso (not(LastInITBlock ()))) then DECODE_UNPREDICTABLE(mc,"TableBranchByte") else () @@ -14810,8 +14798,8 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),Nat.>=(ArchVersion (),7)) - then ( if (L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + if Do(ThumbCondition (),Nat.>=(ArchVersion (),7)) + then ( if (Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse (Rn = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE (mc,"LoadExclusive: Byte or Halfword") @@ -14841,9 +14829,9 @@ fun DecodeThumb2 h = val Rt2 = BitsN.fromBitstring([Rt2'3,Rt2'2,Rt2'1,Rt2'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),Nat.>=(ArchVersion (),7)) - then ( if (((L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + if Do(ThumbCondition (),Nat.>=(ArchVersion (),7)) + then ( if (((Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse (Rt = Rt2)) orelse (Rn = (BitsN.B(0xF,4))) then DECODE_UNPREDICTABLE (mc,"LoadExclusiveDoubleword") @@ -14878,8 +14866,7 @@ fun DecodeThumb2 h = val Rt2 = BitsN.fromBitstring([Rt2'3,Rt2'2,Rt2'1,Rt2'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), ((P = (BitsN.B(0x1,1))) orelse (W = (BitsN.B(0x1,1)))) andalso (HaveThumb2 ())) then let @@ -14887,8 +14874,8 @@ fun DecodeThumb2 h = in ( if (((wback andalso ((Rn = Rt) orelse (Rn = Rt2))) orelse (Rn = (BitsN.B(0xF,4)))) orelse - (L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"StoreDual") else () ; let @@ -14934,12 +14921,11 @@ fun DecodeThumb2 h = val Rt2 = BitsN.fromBitstring([Rt2'3,Rt2'2,Rt2'1,Rt2'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (((BitsN.fromBitstring([P'0],1)) = (BitsN.B(0x1,1))) orelse (W = (BitsN.B(0x1,1)))) andalso (HaveThumb2 ())) - then ( if (((L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + then ( if (((Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse (Rt = Rt2)) orelse (W = (BitsN.B(0x1,1))) then DECODE_UNPREDICTABLE(mc,"LoadDual: literal") else () @@ -14984,16 +14970,15 @@ fun DecodeThumb2 h = val Rt2 = BitsN.fromBitstring([Rt2'3,Rt2'2,Rt2'1,Rt2'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), ((P = (BitsN.B(0x1,1))) orelse (W = (BitsN.B(0x1,1)))) andalso (HaveThumb2 ())) then let val wback = W = (BitsN.B(0x1,1)) in ( if (((wback andalso ((Rn = Rt) orelse (Rn = Rt2))) orelse - (L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rt2,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse (Rt = Rt2) then DECODE_UNPREDICTABLE(mc,"LoadDual") else () @@ -15042,7 +15027,7 @@ fun DecodeThumb2 h = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val imm3 = BitsN.fromBitstring([imm3'2,imm3'1,imm3'0],3) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then let val (shift_t,shift_n) = DecodeImmShift(typ,BitsN.@@(imm3,imm2)) @@ -15051,8 +15036,8 @@ fun DecodeThumb2 h = case (BitsN.fromBitstring([op'3,op'2,op'1,op'0],4), (Rn,(Rd,S))) of (BitsN.B(0x0,4),(_,(BitsN.B(0xF,4),BitsN.B(0x1,1)))) => - ( if (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"TST (register)") else () ; Data @@ -15063,8 +15048,8 @@ fun DecodeThumb2 h = ( if (((Rd = (BitsN.B(0xD,4))) orelse ((Rd = (BitsN.B(0xF,4))) andalso (not setflags))) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"AND (register)") else () ; Data @@ -15073,9 +15058,9 @@ fun DecodeThumb2 h = (setflags,(Rd,(Rn,(Rm,(shift_t,shift_n))))))) ) | (BitsN.B(0x1,4),_) => - ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"BIC (register)") else () ; Data @@ -15088,10 +15073,10 @@ fun DecodeThumb2 h = (imm3 = (BitsN.B(0x0,3)))) andalso (imm2 = (BitsN.B(0x0,2))) then if (setflags andalso - ((L3.mem + ((Set.mem (Rd, [BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem + (Set.mem (Rm, [BitsN.B(0xD,4),BitsN.B(0xF,4)])))) orelse ((not setflags) andalso @@ -15102,9 +15087,9 @@ fun DecodeThumb2 h = then DECODE_UNPREDICTABLE (mc,"MOV (register)") else () - else if (L3.mem + else if (Set.mem (Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE (mc,"SHIFT (register)") else () @@ -15114,9 +15099,9 @@ fun DecodeThumb2 h = (setflags,(Rd,(Rm,(shift_t,shift_n)))))) ) | (BitsN.B(0x2,4),_) => - ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse (Rn = (BitsN.B(0xD,4)))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"ORR (register)") else () ; Data @@ -15125,8 +15110,8 @@ fun DecodeThumb2 h = (setflags,(Rd,(Rn,(Rm,(shift_t,shift_n))))))) ) | (BitsN.B(0x3,4),(BitsN.B(0xF,4),_)) => - ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"MVN (register)") else () ; Data @@ -15134,9 +15119,9 @@ fun DecodeThumb2 h = (true,(setflags,(Rd,(Rm,(shift_t,shift_n)))))) ) | (BitsN.B(0x3,4),_) => - ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse (Rn = (BitsN.B(0xD,4)))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"ORN (register)") else () ; Data @@ -15145,8 +15130,8 @@ fun DecodeThumb2 h = (setflags,(Rd,(Rn,(Rm,(shift_t,shift_n))))))) ) | (BitsN.B(0x4,4),(_,(BitsN.B(0xF,4),BitsN.B(0x1,1)))) => - ( if (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"TEQ (register)") else () ; Data @@ -15157,8 +15142,8 @@ fun DecodeThumb2 h = ( if (((Rd = (BitsN.B(0xD,4))) orelse ((Rd = (BitsN.B(0xF,4))) andalso (not setflags))) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"EOR (register)") else () ; Data @@ -15169,11 +15154,11 @@ fun DecodeThumb2 h = | (BitsN.B(0x6,4),(_,(_,BitsN.B(0x0,1)))) => (if BitsN.bit(typ,0) then Undefined(BitsN.B(0x0,32)) - else ( if ((L3.mem + else ( if ((Set.mem (Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem + (Set.mem (Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem + (Set.mem (Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE (mc,"PackHalfword") @@ -15189,7 +15174,7 @@ fun DecodeThumb2 h = )) | (BitsN.B(0x8,4),(_,(BitsN.B(0xF,4),BitsN.B(0x1,1)))) => ( if (Rn = (BitsN.B(0xF,4))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"CMN (register)") else () ; Data @@ -15201,7 +15186,7 @@ fun DecodeThumb2 h = ((Rd = (BitsN.B(0xF,4))) andalso (not setflags))) orelse (Rn = (BitsN.B(0xF,4)))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"ADD (register)") else () ; let @@ -15216,9 +15201,9 @@ fun DecodeThumb2 h = end ) | (BitsN.B(0xA,4),_) => - ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"ADC (register)") else () ; Data @@ -15227,9 +15212,9 @@ fun DecodeThumb2 h = (setflags,(Rd,(Rn,(Rm,(shift_t,shift_n))))))) ) | (BitsN.B(0xB,4),_) => - ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"SBC (register)") else () ; Data @@ -15239,7 +15224,7 @@ fun DecodeThumb2 h = ) | (BitsN.B(0xD,4),(_,(BitsN.B(0xF,4),BitsN.B(0x1,1)))) => ( if (Rn = (BitsN.B(0xF,4))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"CMP (register)") else () ; Data @@ -15251,7 +15236,7 @@ fun DecodeThumb2 h = ((Rd = (BitsN.B(0xF,4))) andalso (not setflags))) orelse (Rn = (BitsN.B(0xF,4)))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"SUB (register)") else () ; Data @@ -15260,9 +15245,9 @@ fun DecodeThumb2 h = (setflags,(Rd,(Rn,(Rm,(shift_t,shift_n))))))) ) | (BitsN.B(0xE,4),_) => - ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"RSB (register)") else () ; Data @@ -15298,7 +15283,7 @@ fun DecodeThumb2 h = val S = BitsN.fromBitstring([S'0],1) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then let val imm12 = BitsN.concat @@ -15313,7 +15298,7 @@ fun DecodeThumb2 h = case (BitsN.fromBitstring([op'3,op'2,op'1,op'0],4), (Rn,(Rd,S))) of (BitsN.B(0x0,4),(_,(BitsN.B(0xF,4),BitsN.B(0x1,1)))) => - ( if L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + ( if Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"TST (immediate)") else () ; Data @@ -15324,7 +15309,7 @@ fun DecodeThumb2 h = ( if ((Rd = (BitsN.B(0xD,4))) orelse ((Rd = (BitsN.B(0xF,4))) andalso (not setflags))) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"AND (immediate)") else () ; Data @@ -15332,8 +15317,8 @@ fun DecodeThumb2 h = (BitsN.B(0x0,4),(setflags,(Rd,(Rn,imm12))))) ) | (BitsN.B(0x1,4),_) => - ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"BIC (immediate)") else () ; Data @@ -15341,13 +15326,13 @@ fun DecodeThumb2 h = (BitsN.B(0xE,4),(setflags,(Rd,(Rn,imm12))))) ) | (BitsN.B(0x2,4),(BitsN.B(0xF,4),_)) => - ( if L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + ( if Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"MOV (immediate)") else () ; Data(Move(setflags,(false,(Rd,imm12)))) ) | (BitsN.B(0x2,4),_) => - ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse (Rn = (BitsN.B(0xD,4))) then DECODE_UNPREDICTABLE(mc,"ORR (immediate)") else () @@ -15356,13 +15341,13 @@ fun DecodeThumb2 h = (BitsN.B(0xC,4),(setflags,(Rd,(Rn,imm12))))) ) | (BitsN.B(0x3,4),(BitsN.B(0xF,4),_)) => - ( if L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + ( if Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"MVN (immediate)") else () ; Data(Move(setflags,(true,(Rd,imm12)))) ) | (BitsN.B(0x3,4),_) => - ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse (Rn = (BitsN.B(0xD,4))) then DECODE_UNPREDICTABLE(mc,"ORN (immediate)") else () @@ -15371,7 +15356,7 @@ fun DecodeThumb2 h = (BitsN.B(0xF,4),(setflags,(Rd,(Rn,imm12))))) ) | (BitsN.B(0x4,4),(_,(BitsN.B(0xF,4),BitsN.B(0x1,1)))) => - ( if L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + ( if Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"TEQ (immediate)") else () ; Data @@ -15382,7 +15367,7 @@ fun DecodeThumb2 h = ( if ((Rd = (BitsN.B(0xD,4))) orelse ((Rd = (BitsN.B(0xF,4))) andalso (not setflags))) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"EOR (immediate)") else () ; Data @@ -15409,8 +15394,8 @@ fun DecodeThumb2 h = (BitsN.B(0x4,4),(setflags,(Rd,(Rn,imm12))))) ) | (BitsN.B(0xA,4),_) => - ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"ADC (immediate)") else () ; Data @@ -15418,8 +15403,8 @@ fun DecodeThumb2 h = (BitsN.B(0x5,4),(setflags,(Rd,(Rn,imm12))))) ) | (BitsN.B(0xB,4),_) => - ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"SBC (immediate)") else () ; Data @@ -15446,8 +15431,8 @@ fun DecodeThumb2 h = (BitsN.B(0x2,4),(setflags,(Rd,(Rn,imm12))))) ) | (BitsN.B(0xE,4),_) => - ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"RSB (immediate)") else () ; Data @@ -15481,8 +15466,8 @@ fun DecodeThumb2 h = let val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"ADDW (immediate)") else () ; let @@ -15527,8 +15512,8 @@ fun DecodeThumb2 h = let val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"SUBW (immediate)") else () ; let @@ -15574,8 +15559,8 @@ fun DecodeThumb2 h = let val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE (mc,"MOVT or MOVW (immediate)") else () @@ -15624,9 +15609,9 @@ fun DecodeThumb2 h = ([sat_imm'3,sat_imm'2,sat_imm'1,sat_imm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"Saturate16") else () ; let @@ -15671,9 +15656,9 @@ fun DecodeThumb2 h = ([sat_imm'4,sat_imm'3,sat_imm'2,sat_imm'1,sat_imm'0],5) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"Saturate") else () ; let @@ -15725,7 +15710,7 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then let val widthminus1 = BitsN.toNat @@ -15738,8 +15723,8 @@ fun DecodeThumb2 h = (BitsN.fromBitstring([imm3'2,imm3'1,imm3'0],3), BitsN.fromBitstring([imm2'1,imm2'0],2))) in - ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse (Nat.<(31,Nat.+(lsbit,widthminus1))) then DECODE_UNPREDICTABLE(mc,"BitFieldExtract") else () @@ -15777,7 +15762,7 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then let val msbit = BitsN.toNat @@ -15789,7 +15774,7 @@ fun DecodeThumb2 h = (BitsN.fromBitstring([imm3'2,imm3'1,imm3'0],3), BitsN.fromBitstring([imm2'1,imm2'0],2))) in - ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse (Rn = (BitsN.B(0xD,4)))) orelse (Nat.<(msbit,lsbit)) then DECODE_UNPREDICTABLE @@ -15815,8 +15800,8 @@ fun DecodeThumb2 h = let val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) in - if Take(ThumbCondition (),HaveVirtExt ()) - then ( if L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(ThumbCondition (),HaveVirtExt ()) + then ( if Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE (mc,"MoveToBankedOrSpecialRegister") else () @@ -15851,9 +15836,9 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val mask = BitsN.fromBitstring([mask'3,mask'2,mask'1,mask'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if (mask = (BitsN.B(0x0,4))) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE (mc,"MoveToSpecialFromRegister") else () @@ -15909,7 +15894,7 @@ fun DecodeThumb2 h = val M = BitsN.fromBitstring([M'0],1) val imod = BitsN.fromBitstring([imod'1,imod'0],2) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if ((((not(mode = (BitsN.B(0x0,5)))) andalso (M = (BitsN.B(0x0,1)))) orelse ((BitsN.bit(imod,1)) = @@ -15948,7 +15933,7 @@ fun DecodeThumb2 h = let val J = BitsN.fromBitstring([J'0],1) in - if (Take(ThumbCondition (),HaveThumbEE ())) andalso + if (Do(ThumbCondition (),HaveThumbEE ())) andalso (not(((CurrentInstrSet ()) = InstrSet_Thumb) andalso (J = (BitsN.B(0x0,1))))) then ( if InITBlock () @@ -15982,7 +15967,7 @@ fun DecodeThumb2 h = val option = BitsN.fromBitstring([option'3,option'2,option'1,option'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then case BitsN.fromBitstring([op'3,op'2,op'1,op'0],4) of BitsN.B(0x2,4) => ClearExclusive | BitsN.B(0x4,4) => @@ -16020,7 +16005,7 @@ fun DecodeThumb2 h = BitsN.fromBitstring ([imm8'7,imm8'6,imm8'5,imm8'4,imm8'3,imm8'2,imm8'1,imm8'0],8) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then if (HaveVirtExt ()) andalso (imm8 = (BitsN.B(0x0,8))) then System ExceptionReturn else ( if ((CurrentInstrSet ()) = InstrSet_ThumbEE) orelse @@ -16057,8 +16042,8 @@ fun DecodeThumb2 h = let val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveVirtExt ()) - then ( if L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(ThumbCondition (),HaveVirtExt ()) + then ( if Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE (mc,"MoveToRegisterFromBankedOrSpecial") else () @@ -16087,8 +16072,8 @@ fun DecodeThumb2 h = let val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE (mc,"MoveToRegisterFromSpecial") else () @@ -16122,7 +16107,7 @@ fun DecodeThumb2 h = (imm12'7, (imm12'6, (imm12'5,(imm12'4,(imm12'3,(imm12'2,(imm12'1,imm12'0)))))))))))))))) => - (if Take(ThumbCondition (),HaveVirtExt ()) + (if Do(ThumbCondition (),HaveVirtExt ()) then ( if InITBlock () then DECODE_UNPREDICTABLE(mc,"HypervisorCall") else () @@ -16151,8 +16136,7 @@ fun DecodeThumb2 h = (true, (true,(true,(true,(imm4'3,(imm4'2,(imm4'1,imm4'0))))))))))))))), (true,(false,(false,(false,_))))) => - (if Take - (ThumbCondition (), + (if Do(ThumbCondition (), (HaveSecurityExt ()) andalso (not((!Architecture) = ARMv6K))) then ( if (InITBlock ()) andalso (not(LastInITBlock ())) @@ -16185,7 +16169,7 @@ fun DecodeThumb2 h = (imm12'7, (imm12'6, (imm12'5,(imm12'4,(imm12'3,(imm12'2,(imm12'1,imm12'0)))))))))))))))) => - (if Take(ThumbCondition (),HaveThumb2 ()) + (if Do(ThumbCondition (),HaveThumb2 ()) then let val imm32 = BitsN.zeroExtend 32 @@ -16222,8 +16206,7 @@ fun DecodeThumb2 h = (imm11'7, (imm11'6, (imm11'5,(imm11'4,(imm11'3,(imm11'2,(imm11'1,imm11'0)))))))))))))))) => - (if Take - (BitsN.fromBitstring([cond'3,cond'2,cond'1,cond'0],4), + (if Do(BitsN.fromBitstring([cond'3,cond'2,cond'1,cond'0],4), HaveThumb2 ()) then ( if InITBlock () then DECODE_UNPREDICTABLE(mc,"BranchTarget") @@ -16275,8 +16258,7 @@ fun DecodeThumb2 h = val J1 = BitsN.fromBitstring([J1'0],1) val L = BitsN.fromBitstring([L'0],1) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (((L = (BitsN.B(0x1,1))) andalso (J1 = (BitsN.B(0x1,1)))) andalso (J1 = J2)) orelse (HaveThumb2 ())) then ( if (InITBlock ()) andalso (not(LastInITBlock ())) @@ -16339,8 +16321,7 @@ fun DecodeThumb2 h = val J2 = BitsN.fromBitstring([J2'0],1) val J1 = BitsN.fromBitstring([J1'0],1) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (not(((CurrentInstrSet ()) = InstrSet_ThumbEE) orelse ((BitsN.fromBitstring([H'0],1)) = (BitsN.B(0x1,1))))) andalso (if (J1 = (BitsN.B(0x1,1))) andalso (J1 = J2) @@ -16404,7 +16385,7 @@ fun DecodeThumb2 h = (imm12'7, (imm12'6, (imm12'5,(imm12'4,(imm12'3,(imm12'2,(imm12'1,imm12'0)))))))))))))))) => - (if Take(ThumbCondition (),HaveThumb2 ()) + (if Do(ThumbCondition (),HaveThumb2 ()) then let val imm32 = BitsN.zeroExtend 32 @@ -16438,7 +16419,7 @@ fun DecodeThumb2 h = (imm12'7, (imm12'6, (imm12'5,(imm12'4,(imm12'3,(imm12'2,(imm12'1,imm12'0)))))))))))))))) => - (if Take(ThumbCondition (),Nat.>=(ArchVersion (),7)) + (if Do(ThumbCondition (),Nat.>=(ArchVersion (),7)) then let val imm32 = BitsN.zeroExtend 32 @@ -16473,7 +16454,7 @@ fun DecodeThumb2 h = (imm12'7, (imm12'6, (imm12'5,(imm12'4,(imm12'3,(imm12'2,(imm12'1,imm12'0)))))))))))))))) => - (if Take(ThumbCondition (),Nat.>=(ArchVersion (),7)) + (if Do(ThumbCondition (),Nat.>=(ArchVersion (),7)) then let val imm32 = BitsN.zeroExtend 32 @@ -16513,8 +16494,7 @@ fun DecodeThumb2 h = let val W = BitsN.fromBitstring([W'0],1) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), if W = (BitsN.B(0x1,1)) then HaveMPExt () else HaveThumb2 ()) @@ -16568,7 +16548,7 @@ fun DecodeThumb2 h = let val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if Rt = (BitsN.B(0xD,4)) then DECODE_UNPREDICTABLE (mc,"LoadByteLiteral/LoadHalfLiteral") @@ -16616,7 +16596,7 @@ fun DecodeThumb2 h = let val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if ((Rt = (BitsN.B(0xF,4))) andalso (InITBlock ())) andalso (not(LastInITBlock ())) then DECODE_UNPREDICTABLE(mc,"LoadLiteral") @@ -16659,7 +16639,7 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if Rt = (BitsN.B(0xD,4)) then DECODE_UNPREDICTABLE (mc,"LoadByte/LoadHalf (immediate)") @@ -16713,7 +16693,7 @@ fun DecodeThumb2 h = let val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if ((Rt = (BitsN.B(0xF,4))) andalso (InITBlock ())) andalso (not(LastInITBlock ())) then DECODE_UNPREDICTABLE(mc,"LoadWord") @@ -16765,8 +16745,7 @@ fun DecodeThumb2 h = let val W = BitsN.fromBitstring([W'0],1) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), if W = (BitsN.B(0x1,1)) then HaveMPExt () else HaveThumb2 ()) @@ -16808,7 +16787,7 @@ fun DecodeThumb2 h = (imm8'7, (imm8'6, (imm8'5,(imm8'4,(imm8'3,(imm8'2,(imm8'1,imm8'0)))))))))))))))) => - (if Take(ThumbCondition (),Nat.>=(ArchVersion (),7)) + (if Do(ThumbCondition (),Nat.>=(ArchVersion (),7)) then let val imm32 = BitsN.zeroExtend 32 @@ -16853,8 +16832,8 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"LoadUnprivileged") else () ; let @@ -16916,7 +16895,7 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then let val wback = (BitsN.fromBitstring([W'0],1)) = (BitsN.B(0x1,1)) @@ -16978,8 +16957,8 @@ fun DecodeThumb2 h = let val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"LoadUnprivileged") else () ; let @@ -17029,8 +17008,7 @@ fun DecodeThumb2 h = val P = BitsN.fromBitstring([P'0],1) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), ((P = (BitsN.B(0x1,1))) orelse (W = (BitsN.B(0x1,1)))) andalso (HaveThumb2 ())) then let @@ -17080,12 +17058,11 @@ fun DecodeThumb2 h = val W = BitsN.fromBitstring([W'0],1) val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), if W = (BitsN.B(0x1,1)) then HaveMPExt () else HaveThumb2 ()) - then ( if L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + then ( if Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"PreloadData") else () ; let @@ -17128,8 +17105,8 @@ fun DecodeThumb2 h = let val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) in - if Take(ThumbCondition (),Nat.>=(ArchVersion (),7)) - then ( if L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + if Do(ThumbCondition (),Nat.>=(ArchVersion (),7)) + then ( if Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"PreloadInstruction") else () ; let @@ -17179,9 +17156,9 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if (Rt = (BitsN.B(0xD,4))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"Load (register)") else () ; let @@ -17230,10 +17207,10 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if (((Rt = (BitsN.B(0xF,4))) andalso (InITBlock ())) andalso (not(LastInITBlock ()))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"LoadWord") else () ; let @@ -17281,11 +17258,10 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (not(Rn = (BitsN.B(0xF,4)))) andalso (HaveThumb2 ())) then ( if (Rt = (BitsN.B(0xF,4))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"Store (register)") else () ; let @@ -17326,11 +17302,10 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (not(Rn = (BitsN.B(0xF,4)))) andalso (HaveThumb2 ())) - then ( if (L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + then ( if (Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE (mc,"StoreByte/Half (register)") else () @@ -17377,10 +17352,9 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (not(Rn = (BitsN.B(0xF,4)))) andalso (HaveThumb2 ())) - then ( if L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + then ( if Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE(mc,"StoreUnprivileged") else () ; let @@ -17422,10 +17396,9 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (not(Rn = (BitsN.B(0xF,4)))) andalso (HaveThumb2 ())) - then ( if L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + then ( if Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE (mc,"StoreByte/HalfUnprivileged") else () @@ -17477,8 +17450,7 @@ fun DecodeThumb2 h = val P = BitsN.fromBitstring([P'0],1) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), ((not(Rn = (BitsN.B(0xF,4)))) andalso ((P = (BitsN.B(0x1,1))) orelse (W = (BitsN.B(0x1,1))))) andalso (HaveThumb2 ())) @@ -17532,15 +17504,14 @@ fun DecodeThumb2 h = val P = BitsN.fromBitstring([P'0],1) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), ((not(Rn = (BitsN.B(0xF,4)))) andalso ((P = (BitsN.B(0x1,1))) orelse (W = (BitsN.B(0x1,1))))) andalso (HaveThumb2 ())) then let val wback = W = (BitsN.B(0x1,1)) in - ( if (L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + ( if (Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse (wback andalso (Rn = Rt)) then DECODE_UNPREDICTABLE (mc,"StoreByte/Half (immediate)") @@ -17592,8 +17563,7 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (not(Rn = (BitsN.B(0xF,4)))) andalso (HaveThumb2 ())) then ( if Rt = (BitsN.B(0xF,4)) then DECODE_UNPREDICTABLE(mc,"Store (immediate)") @@ -17639,10 +17609,9 @@ fun DecodeThumb2 h = val Rn = BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4) val Rt = BitsN.fromBitstring([Rt'3,Rt'2,Rt'1,Rt'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (not(Rn = (BitsN.B(0xF,4)))) andalso (HaveThumb2 ())) - then ( if L3.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) + then ( if Set.mem(Rt,[BitsN.B(0xD,4),BitsN.B(0xF,4)]) then DECODE_UNPREDICTABLE (mc,"StoreByte/Half (immediate)") else () @@ -17690,10 +17659,10 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"Shift (register)") else () ; let @@ -17732,10 +17701,10 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse (Rn = (BitsN.B(0xD,4)))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"Extend (register)") else () ; let @@ -17781,10 +17750,10 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE (mc,"Parallel addition and subtraction") else () @@ -17831,10 +17800,10 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"SaturatingAddSubtract") else () ; let @@ -17868,11 +17837,11 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if ((not((BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4)) = Rm)) orelse - (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"Reverses") else () ; case BitsN.fromBitstring([op2'1,op2'0],2) of @@ -17909,10 +17878,10 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"SelectBytes") else () ; Media(SelectBytes(Rd,(Rn,Rm))) @@ -17941,11 +17910,11 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) + if Do(ThumbCondition (),HaveThumb2 ()) then ( if ((not((BitsN.fromBitstring([Rn'3,Rn'2,Rn'1,Rn'0],4)) = Rm)) orelse - (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"CountLeadingZeroes") else () ; Data(CountLeadingZeroes(Rd,Rm)) @@ -17975,10 +17944,10 @@ fun DecodeThumb2 h = val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) val Ra = BitsN.fromBitstring([Ra'3,Ra'2,Ra'1,Ra'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if (((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if (((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse (Ra = (BitsN.B(0xD,4))) then DECODE_UNPREDICTABLE (mc,"Multiplies and absolute difference") @@ -18062,12 +18031,11 @@ fun DecodeThumb2 h = val Rm = BitsN.fromBitstring([Rm'3,Rm'2,Rm'1,Rm'0],4) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - if Take - (ThumbCondition (), + if Do(ThumbCondition (), (HaveVirtExt ()) orelse ((!Architecture) = ARMv7_R)) - then ( if ((L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) + then ( if ((Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) then DECODE_UNPREDICTABLE(mc,"Divide") else () ; let @@ -18103,11 +18071,11 @@ fun DecodeThumb2 h = val RdHi = BitsN.fromBitstring([RdHi'3,RdHi'2,RdHi'1,RdHi'0],4) val RdLo = BitsN.fromBitstring([RdLo'3,RdLo'2,RdLo'1,RdLo'0],4) in - if Take(ThumbCondition (),HaveThumb2 ()) - then ( if ((((L3.mem(RdLo,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (L3.mem(RdHi,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse - (L3.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + if Do(ThumbCondition (),HaveThumb2 ()) + then ( if ((((Set.mem(RdLo,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (Set.mem(RdHi,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse + (Set.mem(Rm,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) orelse (RdHi = RdLo) then DECODE_UNPREDICTABLE (mc,"Long multiply, long multiply accumulate") @@ -18303,7 +18271,7 @@ fun EncodeAddSubOpc opc = fun EncodeVFPImmediate (imm64,single_register) = if single_register then if ((((BitsN.bits(imm64,18,0)) = (BitsN.B(0x0,19))) andalso - (L3.mem + (Set.mem (BitsN.bits(imm64,29,25),[BitsN.B(0x0,5),BitsN.B(0x1F,5)]))) andalso (not((BitsN.bit(imm64,25)) = (BitsN.bit(imm64,30))))) andalso ((BitsN.bits(imm64,63,32)) = (BitsN.B(0x0,32))) @@ -18313,7 +18281,7 @@ fun EncodeVFPImmediate (imm64,single_register) = BitsN.bits(imm64,24,19)]) else NONE else if (((BitsN.bits(imm64,47,0)) = (BitsN.B(0x0,48))) andalso - (L3.mem(BitsN.bits(imm64,61,54),[BitsN.B(0x0,8),BitsN.B(0xFF,8)]))) andalso + (Set.mem(BitsN.bits(imm64,61,54),[BitsN.B(0x0,8),BitsN.B(0xFF,8)]))) andalso (not((BitsN.bit(imm64,61)) = (BitsN.bit(imm64,62)))) then Option.SOME (BitsN.concat @@ -18341,7 +18309,7 @@ fun e_branch (c,(ast,e)) = else BadCode("B: bad offset") else if BitsN.bit(imm32,0) then BadCode("BranchTarget: bad offset") - else if L3.mem(c,[BitsN.B(0xE,4),BitsN.B(0xF,4)]) + else if Set.mem(c,[BitsN.B(0xE,4),BitsN.B(0xF,4)]) then if ((BitsN.<=(BitsN.neg(BitsN.B(0x800,32)),imm32)) andalso (BitsN.<=(imm32,BitsN.B(0x7FE,32)))) andalso (not(e = Enc_Wide)) @@ -18470,7 +18438,7 @@ fun e_branch (c,(ast,e)) = | CompareBranch(nonzero,(n,imm32)) => (if ((BitsN.<=+(imm32,BitsN.B(0x7E,32))) andalso (not((BitsN.bit(imm32,0)) orelse (BitsN.bit(n,3))))) andalso - (L3.mem(e,[Enc_Thumb,Enc_Narrow])) + (Set.mem(e,[Enc_Thumb,Enc_Narrow])) then let val op' = BitsN.fromBit nonzero val i = BitsN.bits(imm32,6,6) @@ -18484,7 +18452,7 @@ fun e_branch (c,(ast,e)) = end else BadCode("CBZ")) | TableBranchByte(is_tbh,(Rm,Rn)) => - (if L3.mem(e,[Enc_Thumb,Enc_Wide]) + (if Set.mem(e,[Enc_Thumb,Enc_Wide]) then let val H = BitsN.fromBit is_tbh in @@ -18494,7 +18462,7 @@ fun e_branch (c,(ast,e)) = end else BadCode("CBZ")) | CheckArray(Rm,n) => - (if L3.mem(e,[Enc_Thumb,Enc_Narrow]) + (if Set.mem(e,[Enc_Thumb,Enc_Narrow]) then let val N = BitsN.bits(n,3,3) val Rn = BitsN.bits(n,2,0) @@ -18505,7 +18473,7 @@ fun e_branch (c,(ast,e)) = | HandlerBranchLink(generate_link,handler_offset) => (if ((BitsN.<=+(handler_offset,BitsN.B(0x1FE0,32))) andalso ((BitsN.bits(handler_offset,4,0)) = (BitsN.B(0x0,5)))) andalso - (L3.mem(e,[Enc_Thumb,Enc_Narrow])) + (Set.mem(e,[Enc_Thumb,Enc_Narrow])) then let val L = BitsN.fromBit generate_link val handler = BitsN.bits(handler_offset,12,5) @@ -18517,7 +18485,7 @@ fun e_branch (c,(ast,e)) = (if (((BitsN.<+(imm32,BitsN.B(0x20,32))) andalso (BitsN.<=+(handler_offset,BitsN.B(0x3E0,32)))) andalso ((BitsN.bits(handler_offset,4,0)) = (BitsN.B(0x0,5)))) andalso - (L3.mem(e,[Enc_Thumb,Enc_Narrow])) + (Set.mem(e,[Enc_Thumb,Enc_Narrow])) then let val imm5 = BitsN.bits(imm32,4,0) val handler = BitsN.bits(handler_offset,9,5) @@ -18529,7 +18497,7 @@ fun e_branch (c,(ast,e)) = (if (((BitsN.<+(imm32,BitsN.B(0x8,32))) andalso (BitsN.<=+(handler_offset,BitsN.B(0x3E0,32)))) andalso ((BitsN.bits(handler_offset,4,0)) = (BitsN.B(0x0,5)))) andalso - (L3.mem(e,[Enc_Thumb,Enc_Narrow])) + (Set.mem(e,[Enc_Thumb,Enc_Narrow])) then let val imm3 = BitsN.bits(imm32,2,0) val handler = BitsN.bits(handler_offset,9,5) @@ -18785,7 +18753,7 @@ fun e_data (c,(ast,e)) = end else BadCode("MOV")) | AddSub(sub,(Rd,(Rn,imm12))) => - (if L3.mem(e,[Enc_Thumb,Enc_Wide]) + (if Set.mem(e,[Enc_Thumb,Enc_Wide]) then let val i = BitsN.bits(imm12,11,11) val imm3 = BitsN.bits(imm12,10,8) @@ -18842,7 +18810,7 @@ fun e_data (c,(ast,e)) = in ARM(BitsN.concat[c,BitsN.B(0x1,3),opc,S,Rn,Rd,imm12]) end - else if ((L3.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso + else if ((Set.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso ((BitsN.bits(imm12,11,3)) = (BitsN.B(0x0,9)))) andalso (not((((setflags = (not(c = (BitsN.B(0xE,4))))) orelse (BitsN.bit(d,3))) orelse (BitsN.bit(n,3))) orelse @@ -18855,7 +18823,7 @@ fun e_data (c,(ast,e)) = in Thumb(BitsN.concat[BitsN.B(0x7,6),S,imm3,Rn,Rd]) end - else if (((L3.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso + else if (((Set.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso (d = n)) andalso ((BitsN.bits(imm12,11,8)) = (BitsN.B(0x0,4)))) andalso (not(((setflags = (not(c = (BitsN.B(0xE,4))))) orelse (BitsN.bit(d,3))) orelse (e = Enc_Wide))) @@ -18878,7 +18846,7 @@ fun e_data (c,(ast,e)) = Thumb(BitsN.concat[BitsN.B(0x109,10),Rn,Rd]) end else if ((((opc = (BitsN.B(0x4,4))) andalso (not setflags)) andalso - (L3.mem(n,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) andalso + (Set.mem(n,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) andalso ((BitsN.bits(imm12,11,8)) = (BitsN.B(0xF,4)))) andalso (not((BitsN.bit(d,3)) orelse (e = Enc_Wide))) then let @@ -18888,7 +18856,7 @@ fun e_data (c,(ast,e)) = in Thumb(BitsN.concat[BitsN.B(0xA,4),S,Rd,imm8]) end - else if ((((L3.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso + else if ((((Set.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso (d = (BitsN.B(0xD,4)))) andalso (n = (BitsN.B(0xD,4)))) andalso ((BitsN.bits(imm12,11,7)) = (BitsN.B(0x1E,5)))) andalso (not(setflags orelse (e = Enc_Wide))) @@ -18953,7 +18921,7 @@ fun e_data (c,(ast,e)) = [c,BitsN.B(0x0,3),opc,S,Rn,Rd,imm5,typ, BitsN.B(0x0,1),Rm]) end - else if (((L3.mem(opc,[BitsN.B(0x2,4),BitsN.B(0x4,4)])) andalso + else if (((Set.mem(opc,[BitsN.B(0x2,4),BitsN.B(0x4,4)])) andalso (shift_t = SRType_LSL)) andalso (shift_n = 0)) andalso (not(((((setflags = (not(c = (BitsN.B(0xE,4))))) orelse (BitsN.bit(d,3))) orelse (BitsN.bit(n,3))) orelse @@ -18966,7 +18934,7 @@ fun e_data (c,(ast,e)) = in Thumb(BitsN.concat[BitsN.B(0x6,6),S,Rm,Rn,Rd]) end - else if ((((L3.mem + else if ((((Set.mem (opc, [BitsN.B(0x0,4),BitsN.B(0x1,4),BitsN.B(0x5,4), BitsN.B(0x6,4),BitsN.B(0xC,4),BitsN.B(0xE,4)])) andalso @@ -19096,7 +19064,7 @@ fun e_data (c,(ast,e)) = in Thumb(BitsN.concat[BitsN.B(0x10F,10),Rm,Rd]) end - else if (L3.mem(shift_t,[SRType_LSL,SRType_LSR,SRType_ASR])) andalso + else if (Set.mem(shift_t,[SRType_LSL,SRType_LSR,SRType_ASR])) andalso (not((((negate orelse (setflags = (not(c = (BitsN.B(0xE,4)))))) orelse (BitsN.bit(m,3))) orelse (BitsN.bit(d,3))) orelse (e = Enc_Wide))) @@ -19711,7 +19679,7 @@ fun e_hint (c,(ast,e)) = fun e_system (c,(ast,e)) = case ast of EnterxLeavex is_enterx => - (if L3.mem(e,[Enc_Thumb,Enc_Wide]) + (if Set.mem(e,[Enc_Thumb,Enc_Wide]) then let val J = BitsN.fromBit is_enterx in @@ -20530,7 +20498,7 @@ fun e_load (c,(ast,e)) = ARM(BitsN.concat [c,BitsN.B(0x4,4),U,BitsN.B(0x3,3),Rn,Rt,imm12]) end - else if (((L3.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso + else if (((Set.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso (not postindex)) andalso (BitsN.<=+(imm32,BitsN.B(0xFF,32))) then let val imm8 = BitsN.bits(imm32,7,0) @@ -20728,7 +20696,7 @@ fun e_load (c,(ast,e)) = ARM(BitsN.concat [c,BitsN.B(0x4,4),U,BitsN.B(0x7,3),Rn,Rt,imm12]) end - else if (((L3.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso + else if (((Set.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso (not postindex)) andalso (BitsN.<=+(imm32,BitsN.B(0xFF,32))) then let val imm8 = BitsN.bits(imm32,7,0) @@ -20763,7 +20731,7 @@ fun e_load (c,(ast,e)) = [c,BitsN.B(0x0,4),U,BitsN.B(0x7,3),Rn,Rt,imm4H, BitsN.B(0xD,4),imm4L]) end - else if (((L3.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso + else if (((Set.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso (not postindex)) andalso (BitsN.<=+(imm32,BitsN.B(0xFF,32))) then let val imm8 = BitsN.bits(imm32,7,0) @@ -20943,7 +20911,7 @@ fun e_load (c,(ast,e)) = [c,BitsN.B(0x0,4),U,BitsN.B(0x7,3),Rn,Rt,imm4H, BitsN.B(0x1,1),S,BitsN.B(0x3,2),imm4L]) end - else if ((L3.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso + else if ((Set.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso (not postindex) then let val imm8 = BitsN.bits(imm32,7,0) @@ -21288,7 +21256,7 @@ fun e_store (c,(ast,e)) = ARM(BitsN.concat [c,BitsN.B(0x4,4),U,BitsN.B(0x2,3),Rn,Rt,imm12]) end - else if (((L3.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso + else if (((Set.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso (not postindex)) andalso (BitsN.<=+(imm32,BitsN.B(0xFF,32))) then let val imm8 = BitsN.bits(imm32,7,0) @@ -21420,7 +21388,7 @@ fun e_store (c,(ast,e)) = ARM(BitsN.concat [c,BitsN.B(0x4,4),U,BitsN.B(0x6,3),Rn,Rt,imm12]) end - else if (((L3.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso + else if (((Set.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso (not postindex)) andalso (BitsN.<=+(imm32,BitsN.B(0xFF,32))) then let val imm8 = BitsN.bits(imm32,7,0) @@ -21559,7 +21527,7 @@ fun e_store (c,(ast,e)) = [c,BitsN.B(0x0,4),U,BitsN.B(0x6,3),Rn,Rt,imm4H, BitsN.B(0xB,4),imm4L]) end - else if ((L3.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso + else if ((Set.mem(e,[Enc_Thumb,Enc_Wide])) andalso add) andalso (not postindex) then let val imm8 = BitsN.bits(imm32,7,0) @@ -21739,11 +21707,11 @@ fun instructionEncode (c,(ast,e)) = | Hint h => e_hint(c,(h,e)) | VFP v => e_vfp(c,(v,e)) | IfThen(firstcond,mask) => - (if L3.mem(e,[Enc_Thumb,Enc_Narrow]) + (if Set.mem(e,[Enc_Thumb,Enc_Narrow]) then Thumb(BitsN.concat[BitsN.B(0xBF,8),firstcond,mask]) else BadCode("IfThen")) | Divide(unsigned,(Rd,(Rn,Rm))) => - (if L3.mem(e,[Enc_Thumb,Enc_Wide]) + (if Set.mem(e,[Enc_Thumb,Enc_Wide]) then let val U = BitsN.fromBit unsigned in @@ -22001,7 +21969,7 @@ fun p_label s = let val (l,r) = L3.splitl - (fn c => (Char.isAlphaNum c) orelse (L3.mem(c,[#"_",#"."])),t) + (fn c => (Char.isAlphaNum c) orelse (Set.mem(c,[#"_",#"."])),t) in if ((r = ("")) andalso (not(l = ("")))) andalso (not(Char.isDigit(L3.strHd l))) @@ -22035,7 +22003,7 @@ fun p_cond s = fun p_suffix s = case L3.uncurry String.fields (fn c => c = #".",s) of [cond,s] => - (case (p_cond cond,L3.mem(s,["w","n","f32","f64","32","64"])) of + (case (p_cond cond,Set.mem(s,["w","n","f32","f64","32","64"])) of (Option.SOME c,true) => Option.SOME(c,s) | _ => NONE) | [cond] => @@ -22119,10 +22087,10 @@ fun p_fp_register (single,s) = | _ => NONE; fun p_any_fp_register (s,t) = - case (p_fp_register(true,s),L3.mem(t,["","32"])) of + case (p_fp_register(true,s),Set.mem(t,["","32"])) of (Option.SOME r,true) => Option.SOME(true,r) | _ => - (case (p_fp_register(false,s),L3.mem(t,["","64"])) of + (case (p_fp_register(false,s),Set.mem(t,["","64"])) of (Option.SOME r,true) => Option.SOME(false,r) | _ => NONE); @@ -22141,7 +22109,7 @@ fun p_shift_amount (typ,(h,s)) = then case p_unbounded_immediate s of Option.SOME n => (if (Nat.<(n,32)) orelse - ((n = 32) andalso (L3.mem(typ,[SRType_LSR,SRType_ASR]))) + ((n = 32) andalso (Set.mem(typ,[SRType_LSR,SRType_ASR]))) then ("",(typ,NAT n)) else ("shift amount too large",(SRType_LSL,NAT 0))) | NONE => @@ -22169,7 +22137,7 @@ fun p_rotation s = (if Char.isSpace h then case p_unbounded_immediate(String.implode t) of Option.SOME n => - (if L3.mem(n,[0,8,16,24]) + (if Set.mem(n,[0,8,16,24]) then ("",n) else ("rotation not 0, 8, 16 or 24",0)) | NONE => ("syntax error",0) @@ -22292,7 +22260,7 @@ fun p_shift_full (c,(typ,(setflags,l))) = Option.SOME n => (if (Nat.<(n,32)) orelse ((n = 32) andalso - (L3.mem(typ,[SRType_LSR,SRType_ASR]))) + (Set.mem(typ,[SRType_LSR,SRType_ASR]))) then OK(c, Data (ShiftImmediate @@ -23383,7 +23351,7 @@ fun p_ldm_stm (c,(load,(inc,(index,l)))) = let val (r,wb) = L3.splitr(fn c => c = #"!",stripSpaces h) in - case (p_register r,(p_registers t,L3.mem(wb,["","!"]))) of + case (p_register r,(p_registers t,Set.mem(wb,["","!"]))) of (Option.SOME rn,(Option.SOME(false,w),true)) => let val r = (inc,(index,(wb = ("!"),(rn,w)))) @@ -23687,7 +23655,7 @@ fun p_rfe (c,(increment,(wordhigher,l))) = let val (r,wb) = L3.splitr(fn c => c = #"!",stripSpaces h) in - case (p_register r,L3.mem(wb,["","!"])) of + case (p_register r,Set.mem(wb,["","!"])) of (Option.SOME n,true) => OK(c, System @@ -23703,7 +23671,7 @@ fun p_srs (c,(increment,(wordhigher,l))) = let val (r,wb) = L3.splitr(fn c => c = #"!",stripSpaces h) in - case (p_register r,(L3.mem(wb,["","!"]),p_immediate_number 5 m)) of + case (p_register r,(Set.mem(wb,["","!"]),p_immediate_number 5 m)) of (Option.SOME(BitsN.B(0xD,4)),(true,Option.SOME(ok,mode))) => (if ok then OK(c, @@ -23785,7 +23753,7 @@ fun p_vmov (c,l) = case (p_suffix c,l) of (Option.SOME(c,s),[d,v]) => let - val single = L3.mem(s,["","f32"]) + val single = Set.mem(s,["","f32"]) in if single orelse (s = ("f64")) then case p_fp_register(single,d) of @@ -23808,7 +23776,7 @@ fun p_vcmpe (c,l) = case (p_suffix c,l) of (Option.SOME(c,s),[d,v]) => let - val single = L3.mem(s,["","f32"]) + val single = Set.mem(s,["","f32"]) in if single orelse (s = ("f64")) then case p_fp_register(single,d) of @@ -23838,7 +23806,7 @@ fun p_fp3 (c,(opc,l)) = case p_suffix c of Option.SOME(c,s) => let - val single = L3.mem(s,["","f32"]) + val single = Set.mem(s,["","f32"]) val double = not single in if single orelse (s = ("f64")) diff --git a/examples/l3-machine-code/arm8/model/arm8.sig b/examples/l3-machine-code/arm8/model/arm8.sig index bd0c715b38..83f33a9593 100644 --- a/examples/l3-machine-code/arm8/model/arm8.sig +++ b/examples/l3-machine-code/arm8/model/arm8.sig @@ -1,4 +1,4 @@ -(* arm8 - generated by L<3> - Fri Oct 10 16:45:06 2014 *) +(* arm8 - generated by L<3> - Tue Nov 18 15:32:41 2014 *) signature arm8 = sig diff --git a/examples/l3-machine-code/arm8/model/arm8.sml b/examples/l3-machine-code/arm8/model/arm8.sml index 34804d9f7f..e00993e3b8 100644 --- a/examples/l3-machine-code/arm8/model/arm8.sml +++ b/examples/l3-machine-code/arm8/model/arm8.sml @@ -1,4 +1,4 @@ -(* arm8 - generated by L<3> - Fri Oct 10 16:45:06 2014 *) +(* arm8 - generated by L<3> - Tue Nov 18 15:32:41 2014 *) structure arm8 :> arm8 = struct @@ -6324,28 +6324,32 @@ fun e_data (imm_enc,i) = [e_sf 64 sf,BitsN.fromBit opc,BitsN.fromBit s,BitsN.B(0x59,8), rm,BitsN.fromNat(Cast.ExtendTypeToNat sty,3),imm3,rn,rd]) | AddSubImmediate''32(sf,(opc,(s,(imm,(rn,rd))))) => - (if (BitsN.bits(imm,11,0)) = (BitsN.B(0x0,12)) - then if (BitsN.bits(imm,31,24)) = (BitsN.B(0x0,8)) + (if (BitsN.&&(imm,BitsN.B(0xFFF,32))) = (BitsN.B(0x0,32)) + then if (BitsN.&&(imm,BitsN.~(BitsN.B(0xFFFFFF,32)))) = + (BitsN.B(0x0,32)) then ARM8 (BitsN.concat [e_sf 32 sf,BitsN.fromBit opc,BitsN.fromBit s, BitsN.B(0x45,7),BitsN.bits(imm,23,12),rn,rd]) else BadCode("AddSubImmediate") - else if (BitsN.bits(imm,31,12)) = (BitsN.B(0x0,20)) + else if (BitsN.&&(imm,BitsN.~(BitsN.B(0xFFF,32)))) = + (BitsN.B(0x0,32)) then ARM8 (BitsN.concat [e_sf 32 sf,BitsN.fromBit opc,BitsN.fromBit s, BitsN.B(0x44,7),BitsN.bits(imm,11,0),rn,rd]) else BadCode("AddSubImmediate")) | AddSubImmediate''64(sf,(opc,(s,(imm,(rn,rd))))) => - (if (BitsN.bits(imm,11,0)) = (BitsN.B(0x0,12)) - then if (BitsN.bits(imm,31,24)) = (BitsN.B(0x0,8)) + (if (BitsN.&&(imm,BitsN.B(0xFFF,64))) = (BitsN.B(0x0,64)) + then if (BitsN.&&(imm,BitsN.~(BitsN.B(0xFFFFFF,64)))) = + (BitsN.B(0x0,64)) then ARM8 (BitsN.concat [e_sf 64 sf,BitsN.fromBit opc,BitsN.fromBit s, BitsN.B(0x45,7),BitsN.bits(imm,23,12),rn,rd]) else BadCode("AddSubImmediate") - else if (BitsN.bits(imm,31,12)) = (BitsN.B(0x0,20)) + else if (BitsN.&&(imm,BitsN.~(BitsN.B(0xFFF,64)))) = + (BitsN.B(0x0,64)) then ARM8 (BitsN.concat [e_sf 64 sf,BitsN.fromBit opc,BitsN.fromBit s, @@ -6629,7 +6633,7 @@ fun e_branch i = val imm26 = BitsN.bits(imm,27,2) in if (imm = (BitsN.signExtend 64 (BitsN.@@(imm26,BitsN.B(0x0,2))))) andalso - (L3.mem(btype,[BranchType_CALL,BranchType_JMP])) + (Set.mem(btype,[BranchType_CALL,BranchType_JMP])) then ARM8 (BitsN.concat [BitsN.fromBit(btype = BranchType_CALL), @@ -6731,14 +6735,15 @@ fun e_LoadStoreImmediate (acctype, (signed,(wback,(postindex,(unsigned_offset,(offset,(rn,rt)))))))))) = let + val sz = if memop = MemOp_PREFETCH then BitsN.B(0x3,2) else size val imm9 = BitsN.bits(offset,8,0) + val imm12 = BitsN.bits(LSR 64 (offset,BitsN.toNat sz),11,0) val opc = if memop = MemOp_STORE then BitsN.B(0x0,2) else if (memop = MemOp_LOAD) andalso (not signed) then BitsN.B(0x1,2) else BitsN.@@(BitsN.B(0x1,1),BitsN.fromBit regsize_word) - val sz = if memop = MemOp_PREFETCH then BitsN.B(0x3,2) else size in if wback then if (offset = (BitsN.signExtend 64 imm9)) andalso @@ -6750,16 +6755,10 @@ fun e_LoadStoreImmediate else BadCode("LoadStoreImmediate") else if postindex then BadCode("LoadStoreImmediate") - else if unsigned_offset - then let - val imm12 = BitsN.bits(LSR 64 (offset,BitsN.toNat sz),11,0) - in - if (offset = - (LSL 64 (BitsN.zeroExtend 64 imm12,BitsN.toNat sz))) andalso - (acctype = AccType_NORMAL) - then ARM8(BitsN.concat[sz,BitsN.B(0x39,6),opc,imm12,rn,rt]) - else BadCode("LoadStoreImmediate") - end + else if (unsigned_offset andalso + (offset = (LSL 64 (BitsN.zeroExtend 64 imm12,BitsN.toNat sz)))) andalso + (acctype = AccType_NORMAL) + then ARM8(BitsN.concat[sz,BitsN.B(0x39,6),opc,imm12,rn,rt]) else if offset = (BitsN.signExtend 64 imm9) then ARM8 (BitsN.concat @@ -6912,8 +6911,8 @@ fun e_load_store i = val imm7 = BitsN.bits(LSR 64 (offset,scale),6,0) in if ((((sf = (BitsN.B(0x1,1))) = ((BitsN.size size) = 64)) andalso - (L3.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso - (L3.mem(acctype,[AccType_STREAM,AccType_NORMAL]))) andalso + (Set.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso + (Set.mem(acctype,[AccType_STREAM,AccType_NORMAL]))) andalso (offset = (LSL 64 (BitsN.signExtend 64 imm7,scale))) then ARM8 (BitsN.concat @@ -6935,8 +6934,8 @@ fun e_load_store i = val imm7 = BitsN.bits(LSR 64 (offset,scale),6,0) in if ((((sf = (BitsN.B(0x1,1))) = ((BitsN.size size) = 64)) andalso - (L3.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso - (L3.mem(acctype,[AccType_STREAM,AccType_NORMAL]))) andalso + (Set.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso + (Set.mem(acctype,[AccType_STREAM,AccType_NORMAL]))) andalso (offset = (LSL 64 (BitsN.signExtend 64 imm7,scale))) then ARM8 (BitsN.concat @@ -6956,8 +6955,8 @@ fun e_load_store i = | 32 => size = (BitsN.B(0x2,8)) | _ => size = (BitsN.B(0x3,8)) in - if (sizeok andalso (L3.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso - (L3.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) + if (sizeok andalso (Set.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso + (Set.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) then ARM8 (BitsN.concat [BitsN.fromNat(BitsN.toNat size,2),BitsN.B(0x8,6), @@ -6978,8 +6977,8 @@ fun e_load_store i = | 32 => size = (BitsN.B(0x2,16)) | _ => size = (BitsN.B(0x3,16)) in - if (sizeok andalso (L3.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso - (L3.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) + if (sizeok andalso (Set.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso + (Set.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) then ARM8 (BitsN.concat [BitsN.fromNat(BitsN.toNat size,2),BitsN.B(0x8,6), @@ -7000,8 +6999,8 @@ fun e_load_store i = | 32 => size = (BitsN.B(0x2,32)) | _ => size = (BitsN.B(0x3,32)) in - if (sizeok andalso (L3.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso - (L3.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) + if (sizeok andalso (Set.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso + (Set.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) then ARM8 (BitsN.concat [BitsN.fromNat(BitsN.toNat size,2),BitsN.B(0x8,6), @@ -7022,8 +7021,8 @@ fun e_load_store i = | 32 => size = (BitsN.B(0x2,64)) | _ => size = (BitsN.B(0x3,64)) in - if (sizeok andalso (L3.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso - (L3.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) + if (sizeok andalso (Set.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso + (Set.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) then ARM8 (BitsN.concat [BitsN.fromNat(BitsN.toNat size,2),BitsN.B(0x8,6), @@ -7043,8 +7042,8 @@ fun e_load_store i = then BitsN.B(0x2,64) else BitsN.B(0x3,64)) in - if (sizeok andalso (L3.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso - (L3.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) + if (sizeok andalso (Set.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso + (Set.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) then ARM8 (BitsN.concat [BitsN.fromNat(BitsN.toNat size,2),BitsN.B(0x10,7), @@ -7062,8 +7061,8 @@ fun e_load_store i = then BitsN.B(0x2,128) else BitsN.B(0x3,128)) in - if (sizeok andalso (L3.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso - (L3.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) + if (sizeok andalso (Set.mem(memop,[MemOp_LOAD,MemOp_STORE]))) andalso + (Set.mem(acctype,[AccType_ORDERED,AccType_ATOMIC])) then ARM8 (BitsN.concat [BitsN.fromNat(BitsN.toNat size,2),BitsN.B(0x10,7), @@ -7184,7 +7183,7 @@ fun p_label s = let val (l,r) = L3.splitl - (fn c => (Char.isAlphaNum c) orelse (L3.mem(c,[#"_",#"."])),t) + (fn c => (Char.isAlphaNum c) orelse (Set.mem(c,[#"_",#"."])),t) in if ((r = ("")) andalso (not(l = ("")))) andalso (not(Char.isDigit(L3.strHd l))) @@ -7382,7 +7381,7 @@ fun p_extend2 (size,(wide,s)) = | _ => NONE in case r of - Option.SOME(_,v) => (if L3.mem(v,[0,size]) then r else NONE) + Option.SOME(_,v) => (if Set.mem(v,[0,size]) then r else NONE) | NONE => NONE end; @@ -7919,7 +7918,7 @@ fun p_extend_register (wm,(ext,(BitsN.fromNat(amount,3),(wn,wd))))))))) else FAIL("syntax error: add, sub")) | (Option.SOME(wide,(rd,rn)),NONE) => - (if is_lsl andalso (L3.mem(amount,[0,12])) + (if is_lsl andalso (Set.mem(amount,[0,12])) then case p_immediate 12 m of Option.SOME(true,imm12) => (if wide @@ -8344,7 +8343,7 @@ fun p_call (typ,l) = | Option.SOME _ => FAIL("immediate too large: hint") | _ => FAIL("syntax error: svc, hvc, smc, hlt, brk, dcpsN")) | [] => - if L3.mem(typ,[1,2,3]) + if Set.mem(typ,[1,2,3]) then OK(Debug(DebugSwitch(BitsN.fromNat(typ,2)))) else FAIL("syntax error: svc, hvc, smc, hlt, brk") | _ => FAIL("syntax error: svc, hvc, smc, hlt, brk, dcpsN"); @@ -8425,7 +8424,7 @@ fun p_mov l = val i = (L3.strHd n) = #"#" val orr = (LogicalOp_ORR,(false,(false,[d,wzr_xzr d,n]))) in - if (L3.mem(d,s)) orelse (L3.mem(n,s)) + if (Set.mem(d,s)) orelse (Set.mem(n,s)) then if i then p_and_etc orr else p_add_sub(false,(false,l @ ["#0"])) @@ -9042,7 +9041,7 @@ fun s_data ast = s_regp(wide,n),", ", s_regz (wide andalso - (L3.mem(extend_type,[ExtendType_UXTX,ExtendType_SXTX])),m), + (Set.mem(extend_type,[ExtendType_UXTX,ExtendType_SXTX])),m), if ((n = (BitsN.B(0x1F,5))) orelse ((not setflags) andalso (d = (BitsN.B(0x1F,5))))) andalso ((wide andalso (extend_type = ExtendType_UXTX)) orelse @@ -9066,7 +9065,7 @@ fun s_data ast = s_regp(wide,n),", ", s_regz (wide andalso - (L3.mem(extend_type,[ExtendType_UXTX,ExtendType_SXTX])),m), + (Set.mem(extend_type,[ExtendType_UXTX,ExtendType_SXTX])),m), if ((n = (BitsN.B(0x1F,5))) orelse ((not setflags) andalso (d = (BitsN.B(0x1F,5))))) andalso ((wide andalso (extend_type = ExtendType_UXTX)) orelse @@ -9850,8 +9849,8 @@ fun s_load_store ast = String.concat [s_regz(wide,rt),", [",s_regp(true,rn),", ", s_regz - (L3.mem(extend_type,[ExtendType_UXTX,ExtendType_SXTX]), - rm), + (Set.mem + (extend_type,[ExtendType_UXTX,ExtendType_SXTX]),rm), if extend_type = ExtendType_UXTX then if shift = 0 then "" @@ -9883,8 +9882,8 @@ fun s_load_store ast = String.concat [s_regz(wide,rt),", [",s_regp(true,rn),", ", s_regz - (L3.mem(extend_type,[ExtendType_UXTX,ExtendType_SXTX]), - rm), + (Set.mem + (extend_type,[ExtendType_UXTX,ExtendType_SXTX]),rm), if extend_type = ExtendType_UXTX then if shift = 0 then "" @@ -9916,8 +9915,8 @@ fun s_load_store ast = String.concat [s_regz(wide,rt),", [",s_regp(true,rn),", ", s_regz - (L3.mem(extend_type,[ExtendType_UXTX,ExtendType_SXTX]), - rm), + (Set.mem + (extend_type,[ExtendType_UXTX,ExtendType_SXTX]),rm), if extend_type = ExtendType_UXTX then if shift = 0 then "" @@ -9949,8 +9948,8 @@ fun s_load_store ast = String.concat [s_regz(wide,rt),", [",s_regp(true,rn),", ", s_regz - (L3.mem(extend_type,[ExtendType_UXTX,ExtendType_SXTX]), - rm), + (Set.mem + (extend_type,[ExtendType_UXTX,ExtendType_SXTX]),rm), if extend_type = ExtendType_UXTX then if shift = 0 then "" diff --git a/examples/l3-machine-code/arm8/model/arm8Script.sml b/examples/l3-machine-code/arm8/model/arm8Script.sml index e770c22eef..6b1d8027f8 100644 --- a/examples/l3-machine-code/arm8/model/arm8Script.sml +++ b/examples/l3-machine-code/arm8/model/arm8Script.sml @@ -1,4 +1,4 @@ -(* arm8Script.sml - generated by L<3> - Tue Oct 14 10:39:24 2014 *) +(* arm8Script.sml - generated by L<3> - Thu Nov 06 16:00:59 2014 *) open HolKernel boolLib bossLib Import val () = Import.start "arm8" @@ -355,6 +355,10 @@ val _ = Construct ("MemoryBarrier",[PTy(CTy"MemBarrierOp",F4)]),("Reserved",[]), ("System",[CTy"System"]),("Unallocated",[])])] ; +val _ = Construct [("MachineCode",[("ARM8",[F32]),("BadCode",[sTy])])] +; +val _ = Construct [("imm32_64",[("Imm32",[F32]),("Imm64",[F64])])] +; val _ = Construct [("exception", [("ALIGNMENT_FAULT",[]),("ASSERT",[sTy]),("NoException",[]), @@ -8040,5 +8044,1256 @@ val Next_def = Def ("PC", TP[qVar"s",Bop(Add,Dest("PC",F64,qVar"s"),LW(4,64))]), qVar"s")]))) +; +val e_sf_def = Def + ("e_sf",Var("sf",BTy"N"),Mop(Cast F1,EQ(Mop(Size,LY(0,"N")),LN 64))) +; +val EncodeLogicalOp_def = Def + ("EncodeLogicalOp",TP[Var("opc",CTy"LogicalOp"),bVar"setflags"], + CS(TP[Var("opc",CTy"LogicalOp"),bVar"setflags"], + [(TP[LC("LogicalOp_AND",CTy"LogicalOp"),LF],Mop(Some,LW(0,2))), + (TP[LC("LogicalOp_ORR",CTy"LogicalOp"),LF],Mop(Some,LW(1,2))), + (TP[LC("LogicalOp_EOR",CTy"LogicalOp"),LF],Mop(Some,LW(2,2))), + (TP[LC("LogicalOp_AND",CTy"LogicalOp"),LT],Mop(Some,LW(3,2))), + (AVar(PTy(CTy"LogicalOp",bTy)),LO(FTy 2))])) +; +val e_data_def = Def + ("e_data", + TP[Var("imm_enc",ATy(CTy"imm32_64",OTy(PTy(F1,PTy(FTy 6,FTy 6))))), + Var("i",CTy"Data")], + CS(Var("i",CTy"Data"), + [(Call + ("AddSubShiftedRegister@32",CTy"Data", + TP[AVar F32,bVar"opc",bVar"s",Var("sh",CTy"ShiftType"), + Var("rm",FTy 5),Var("imm6",FTy 6),Var("rn",FTy 5), + Var("rd",FTy 5)]), + ITE(Bop(Bit,Var("imm6",FTy 6),LN 5), + Call("BadCode",CTy"MachineCode",LS"AddSubShiftedRegister32"), + Call + ("ARM8",CTy"MachineCode", + CC[LW(0,1),Mop(Cast F1,bVar"opc"),Mop(Cast F1,bVar"s"), + LW(11,5),Mop(Cast(FTy 2),Var("sh",CTy"ShiftType")), + LW(0,1),Var("rm",FTy 5),Var("imm6",FTy 6), + Var("rn",FTy 5),Var("rd",FTy 5)]))), + (Call + ("AddSubShiftedRegister@64",CTy"Data", + TP[AVar F64,bVar"opc",bVar"s",Var("sh",CTy"ShiftType"), + Var("rm",FTy 5),Var("imm6",FTy 6),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1,1),Mop(Cast F1,bVar"opc"),Mop(Cast F1,bVar"s"), + LW(11,5),Mop(Cast(FTy 2),Var("sh",CTy"ShiftType")),LW(0,1), + Var("rm",FTy 5),Var("imm6",FTy 6),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("AddSubExtendRegister@32",CTy"Data", + TP[Var("sf",F32),bVar"opc",bVar"s",Var("rm",FTy 5), + Var("sty",CTy"ExtendType"),Var("imm3",FTy 3), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F32)),Mop(Cast F1,bVar"opc"), + Mop(Cast F1,bVar"s"),LW(89,8),Var("rm",FTy 5), + Mop(Cast(FTy 3),Var("sty",CTy"ExtendType")), + Var("imm3",FTy 3),Var("rn",FTy 5),Var("rd",FTy 5)])), + (Call + ("AddSubExtendRegister@64",CTy"Data", + TP[Var("sf",F64),bVar"opc",bVar"s",Var("rm",FTy 5), + Var("sty",CTy"ExtendType"),Var("imm3",FTy 3), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F64)),Mop(Cast F1,bVar"opc"), + Mop(Cast F1,bVar"s"),LW(89,8),Var("rm",FTy 5), + Mop(Cast(FTy 3),Var("sty",CTy"ExtendType")), + Var("imm3",FTy 3),Var("rn",FTy 5),Var("rd",FTy 5)])), + (Call + ("AddSubImmediate@32",CTy"Data", + TP[Var("sf",F32),bVar"opc",bVar"s",Var("imm",F32), + Var("rn",FTy 5),Var("rd",FTy 5)]), + ITB([(EQ(Bop(BAnd,Var("imm",F32),LW(4095,32)),LW(0,32)), + ITE(EQ(Bop(BAnd,Var("imm",F32),Mop(BNot,LW(16777215,32))), + LW(0,32)), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F32)), + Mop(Cast F1,bVar"opc"),Mop(Cast F1,bVar"s"), + LW(69,7),EX(Var("imm",F32),LN 23,LN 12,FTy 12), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"AddSubImmediate"))), + (EQ(Bop(BAnd,Var("imm",F32),Mop(BNot,LW(4095,32))),LW(0,32)), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F32)),Mop(Cast F1,bVar"opc"), + Mop(Cast F1,bVar"s"),LW(68,7), + EX(Var("imm",F32),LN 11,LN 0,FTy 12),Var("rn",FTy 5), + Var("rd",FTy 5)]))], + Call("BadCode",CTy"MachineCode",LS"AddSubImmediate"))), + (Call + ("AddSubImmediate@64",CTy"Data", + TP[Var("sf",F64),bVar"opc",bVar"s",Var("imm",F64), + Var("rn",FTy 5),Var("rd",FTy 5)]), + ITB([(EQ(Bop(BAnd,Var("imm",F64),LW(4095,64)),LW(0,64)), + ITE(EQ(Bop(BAnd,Var("imm",F64),Mop(BNot,LW(16777215,64))), + LW(0,64)), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F64)), + Mop(Cast F1,bVar"opc"),Mop(Cast F1,bVar"s"), + LW(69,7),EX(Var("imm",F64),LN 23,LN 12,FTy 12), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"AddSubImmediate"))), + (EQ(Bop(BAnd,Var("imm",F64),Mop(BNot,LW(4095,64))),LW(0,64)), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F64)),Mop(Cast F1,bVar"opc"), + Mop(Cast F1,bVar"s"),LW(68,7), + EX(Var("imm",F64),LN 11,LN 0,FTy 12),Var("rn",FTy 5), + Var("rd",FTy 5)]))], + Call("BadCode",CTy"MachineCode",LS"AddSubImmediate"))), + (Call + ("AddSubCarry@32",CTy"Data", + TP[AVar F32,bVar"opc",bVar"s",Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(0,1),Mop(Cast F1,bVar"opc"),Mop(Cast F1,bVar"s"), + LW(208,8),Var("rm",FTy 5),LW(0,6),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("AddSubCarry@64",CTy"Data", + TP[AVar F64,bVar"opc",bVar"s",Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1,1),Mop(Cast F1,bVar"opc"),Mop(Cast F1,bVar"s"), + LW(208,8),Var("rm",FTy 5),LW(0,6),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("LogicalShiftedRegister@32",CTy"Data", + TP[Var("sf",F32),Var("opc",CTy"LogicalOp"),bVar"invert", + bVar"s",Var("sh",CTy"ShiftType"),nVar"imm",Var("rm",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)]), + CS(Call + ("EncodeLogicalOp",OTy(FTy 2), + TP[Var("opc",CTy"LogicalOp"),bVar"s"]), + [(Mop(Some,Var("opc",FTy 2)), + Let(Var("imm6",FTy 6),Mop(Cast(FTy 6),nVar"imm"), + ITE(EQ(nVar"imm",Mop(Cast nTy,Var("imm6",FTy 6))), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F32)),Var("opc",FTy 2), + LW(10,5), + Mop(Cast(FTy 2),Var("sh",CTy"ShiftType")), + Mop(Cast F1,bVar"invert"),Var("rm",FTy 5), + Var("imm6",FTy 6),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("BadCode",CTy"MachineCode", + LS"LogicalShiftedRegister")))), + (LO(FTy 2), + Call("BadCode",CTy"MachineCode",LS"LogicalShiftedRegister"))])), + (Call + ("LogicalShiftedRegister@64",CTy"Data", + TP[Var("sf",F64),Var("opc",CTy"LogicalOp"),bVar"invert", + bVar"s",Var("sh",CTy"ShiftType"),nVar"imm",Var("rm",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)]), + CS(Call + ("EncodeLogicalOp",OTy(FTy 2), + TP[Var("opc",CTy"LogicalOp"),bVar"s"]), + [(Mop(Some,Var("opc",FTy 2)), + Let(Var("imm6",FTy 6),Mop(Cast(FTy 6),nVar"imm"), + ITE(EQ(nVar"imm",Mop(Cast nTy,Var("imm6",FTy 6))), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F64)),Var("opc",FTy 2), + LW(10,5), + Mop(Cast(FTy 2),Var("sh",CTy"ShiftType")), + Mop(Cast F1,bVar"invert"),Var("rm",FTy 5), + Var("imm6",FTy 6),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("BadCode",CTy"MachineCode", + LS"LogicalShiftedRegister")))), + (LO(FTy 2), + Call("BadCode",CTy"MachineCode",LS"LogicalShiftedRegister"))])), + (Call + ("LogicalImmediate@32",CTy"Data", + TP[AVar F32,Var("opc",CTy"LogicalOp"),bVar"s",Var("imm",F32), + Var("rn",FTy 5),Var("rd",FTy 5)]), + CS(TP[Apply + (Var("imm_enc", + ATy(CTy"imm32_64",OTy(PTy(F1,PTy(FTy 6,FTy 6))))), + Call("Imm32",CTy"imm32_64",Var("imm",F32))), + Call + ("EncodeLogicalOp",OTy(FTy 2), + TP[Var("opc",CTy"LogicalOp"),bVar"s"])], + [(TP[Mop(Some,TP[AVar F1,Var("imms",FTy 6),Var("immr",FTy 6)]), + Mop(Some,Var("opc",FTy 2))], + Call + ("ARM8",CTy"MachineCode", + CC[LW(0,1),Var("opc",FTy 2),LW(72,7),Var("immr",FTy 6), + Var("imms",FTy 6),Var("rn",FTy 5),Var("rd",FTy 5)])), + (AVar(PTy(OTy(PTy(F1,PTy(FTy 6,FTy 6))),OTy(FTy 2))), + Call("BadCode",CTy"MachineCode",LS"LogicalImmediate32"))])), + (Call + ("LogicalImmediate@64",CTy"Data", + TP[AVar F64,Var("opc",CTy"LogicalOp"),bVar"s",Var("imm",F64), + Var("rn",FTy 5),Var("rd",FTy 5)]), + CS(TP[Apply + (Var("imm_enc", + ATy(CTy"imm32_64",OTy(PTy(F1,PTy(FTy 6,FTy 6))))), + Call("Imm64",CTy"imm32_64",Var("imm",F64))), + Call + ("EncodeLogicalOp",OTy(FTy 2), + TP[Var("opc",CTy"LogicalOp"),bVar"s"])], + [(TP[Mop(Some, + TP[Var("N",F1),Var("imms",FTy 6),Var("immr",FTy 6)]), + Mop(Some,Var("opc",FTy 2))], + Call + ("ARM8",CTy"MachineCode", + CC[LW(1,1),Var("opc",FTy 2),LW(36,6),Var("N",F1), + Var("immr",FTy 6),Var("imms",FTy 6),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (AVar(PTy(OTy(PTy(F1,PTy(FTy 6,FTy 6))),OTy(FTy 2))), + Call("BadCode",CTy"MachineCode",LS"LogicalImmediate64"))])), + (Call + ("Shift@32",CTy"Data", + TP[AVar F32,Var("sh",CTy"ShiftType"),Var("rm",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(214,11),Var("rm",FTy 5),LW(2,4), + Mop(Cast(FTy 2),Var("sh",CTy"ShiftType")),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("Shift@64",CTy"Data", + TP[AVar F64,Var("sh",CTy"ShiftType"),Var("rm",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1238,11),Var("rm",FTy 5),LW(2,4), + Mop(Cast(FTy 2),Var("sh",CTy"ShiftType")),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("MoveWide@32",CTy"Data", + TP[AVar F32,Var("opc",CTy"MoveWideOp"),Var("hw",FTy 2), + Var("imm16",F16),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(0,1), + CS(Var("opc",CTy"MoveWideOp"), + [(LC("MoveWideOp_N",CTy"MoveWideOp"),LW(0,2)), + (LC("MoveWideOp_Z",CTy"MoveWideOp"),LW(2,2)), + (LC("MoveWideOp_K",CTy"MoveWideOp"),LW(3,2))]),LW(37,6), + Var("hw",FTy 2),Var("imm16",F16),Var("rd",FTy 5)])), + (Call + ("MoveWide@64",CTy"Data", + TP[AVar F64,Var("opc",CTy"MoveWideOp"),Var("hw",FTy 2), + Var("imm16",F16),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1,1), + CS(Var("opc",CTy"MoveWideOp"), + [(LC("MoveWideOp_N",CTy"MoveWideOp"),LW(0,2)), + (LC("MoveWideOp_Z",CTy"MoveWideOp"),LW(2,2)), + (LC("MoveWideOp_K",CTy"MoveWideOp"),LW(3,2))]),LW(37,6), + Var("hw",FTy 2),Var("imm16",F16),Var("rd",FTy 5)])), + (Call + ("BitfieldMove@32",CTy"Data", + TP[Var("sf",F32),bVar"inzero",bVar"extend",Var("wmask",F32), + Var("tmask",F32),nVar"immr",nVar"imms",Var("rn",FTy 5), + Var("rd",FTy 5)]), + Let(Var("sz",F1),Call("e_sf",F1,Var("sf",F32)), + CS(CS(TP[bVar"inzero",bVar"extend"], + [(TP[LT,LT],Mop(Some,LW(0,2))), + (TP[LF,LF],Mop(Some,LW(1,2))), + (TP[LT,LF],Mop(Some,LW(2,2))), + (AVar(PTy(bTy,bTy)),LO(FTy 2))]), + [(Mop(Some,Var("opc",FTy 2)), + Let(Var("r",FTy 6),Mop(Cast(FTy 6),nVar"immr"), + Let(Var("s",FTy 6),Mop(Cast(FTy 6),nVar"imms"), + ITE(Bop(And, + Bop(And, + EQ(nVar"immr", + Mop(Cast nTy,Var("r",FTy 6))), + EQ(nVar"imms", + Mop(Cast nTy,Var("s",FTy 6)))), + EQ(Call + ("DecodeBitMasks",OTy(PTy(F32,F32)), + TP[Mop(Cast F1,Var("sz",F1)), + Var("s",FTy 6),Var("r",FTy 6),LF]), + Mop(Some, + TP[Var("wmask",F32), + Var("tmask",F32)]))), + Call + ("ARM8",CTy"MachineCode", + CC[Var("sz",F1),Var("opc",FTy 2),LW(38,6), + Var("sz",F1),Var("r",FTy 6), + Var("s",FTy 6),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("BadCode",CTy"MachineCode", + LS"BitfieldMove"))))), + (LO(FTy 2), + Call("BadCode",CTy"MachineCode",LS"BitfieldMove"))]))), + (Call + ("BitfieldMove@64",CTy"Data", + TP[Var("sf",F64),bVar"inzero",bVar"extend",Var("wmask",F64), + Var("tmask",F64),nVar"immr",nVar"imms",Var("rn",FTy 5), + Var("rd",FTy 5)]), + Let(Var("sz",F1),Call("e_sf",F1,Var("sf",F64)), + CS(CS(TP[bVar"inzero",bVar"extend"], + [(TP[LT,LT],Mop(Some,LW(0,2))), + (TP[LF,LF],Mop(Some,LW(1,2))), + (TP[LT,LF],Mop(Some,LW(2,2))), + (AVar(PTy(bTy,bTy)),LO(FTy 2))]), + [(Mop(Some,Var("opc",FTy 2)), + Let(Var("r",FTy 6),Mop(Cast(FTy 6),nVar"immr"), + Let(Var("s",FTy 6),Mop(Cast(FTy 6),nVar"imms"), + ITE(Bop(And, + Bop(And, + EQ(nVar"immr", + Mop(Cast nTy,Var("r",FTy 6))), + EQ(nVar"imms", + Mop(Cast nTy,Var("s",FTy 6)))), + EQ(Call + ("DecodeBitMasks",OTy(PTy(F64,F64)), + TP[Mop(Cast F1,Var("sz",F1)), + Var("s",FTy 6),Var("r",FTy 6),LF]), + Mop(Some, + TP[Var("wmask",F64), + Var("tmask",F64)]))), + Call + ("ARM8",CTy"MachineCode", + CC[Var("sz",F1),Var("opc",FTy 2),LW(38,6), + Var("sz",F1),Var("r",FTy 6), + Var("s",FTy 6),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("BadCode",CTy"MachineCode", + LS"BitfieldMove"))))), + (LO(FTy 2), + Call("BadCode",CTy"MachineCode",LS"BitfieldMove"))]))), + (Call + ("ConditionalCompareImmediate@32",CTy"Data", + TP[Var("sf",F32),bVar"opc",Var("imm",F32),Var("cd",F4), + TP[bVar"n",bVar"z",bVar"c",bVar"v"],Var("rn",FTy 5)]), + Let(Var("imm5",FTy 5),Mop(Cast(FTy 5),Var("imm",F32)), + ITE(EQ(Var("imm",F32),Mop(Cast F32,Var("imm5",FTy 5))), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F32)), + Mop(Cast F1,bVar"opc"),LW(466,9),Var("imm5",FTy 5), + Var("cd",F4),LW(2,2),Var("rn",FTy 5),LW(0,1), + Mop(Cast F1,bVar"n"),Mop(Cast F1,bVar"z"), + Mop(Cast F1,bVar"c"),Mop(Cast F1,bVar"v")]), + Call + ("BadCode",CTy"MachineCode", + LS"ConditionalCompareImmediate")))), + (Call + ("ConditionalCompareImmediate@64",CTy"Data", + TP[Var("sf",F64),bVar"opc",Var("imm",F64),Var("cd",F4), + TP[bVar"n",bVar"z",bVar"c",bVar"v"],Var("rn",FTy 5)]), + Let(Var("imm5",FTy 5),Mop(Cast(FTy 5),Var("imm",F64)), + ITE(EQ(Var("imm",F64),Mop(Cast F64,Var("imm5",FTy 5))), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F64)), + Mop(Cast F1,bVar"opc"),LW(466,9),Var("imm5",FTy 5), + Var("cd",F4),LW(2,2),Var("rn",FTy 5),LW(0,1), + Mop(Cast F1,bVar"n"),Mop(Cast F1,bVar"z"), + Mop(Cast F1,bVar"c"),Mop(Cast F1,bVar"v")]), + Call + ("BadCode",CTy"MachineCode", + LS"ConditionalCompareImmediate")))), + (Call + ("ConditionalCompareRegister@32",CTy"Data", + TP[Var("sf",F32),bVar"opc",Var("cd",F4), + TP[bVar"n",bVar"z",bVar"c",bVar"v"],Var("rm",FTy 5), + Var("rn",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F32)),Mop(Cast F1,bVar"opc"), + LW(466,9),Var("rm",FTy 5),Var("cd",F4),LW(0,2), + Var("rn",FTy 5),LW(0,1),Mop(Cast F1,bVar"n"), + Mop(Cast F1,bVar"z"),Mop(Cast F1,bVar"c"), + Mop(Cast F1,bVar"v")])), + (Call + ("ConditionalCompareRegister@64",CTy"Data", + TP[Var("sf",F64),bVar"opc",Var("cd",F4), + TP[bVar"n",bVar"z",bVar"c",bVar"v"],Var("rm",FTy 5), + Var("rn",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[Call("e_sf",F1,Var("sf",F64)),Mop(Cast F1,bVar"opc"), + LW(466,9),Var("rm",FTy 5),Var("cd",F4),LW(0,2), + Var("rn",FTy 5),LW(0,1),Mop(Cast F1,bVar"n"), + Mop(Cast F1,bVar"z"),Mop(Cast F1,bVar"c"), + Mop(Cast F1,bVar"v")])), + (Call + ("ConditionalSelect@32",CTy"Data", + TP[AVar F32,bVar"op",bVar"o2",Var("cd",F4),Var("rm",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(0,1),Mop(Cast F1,bVar"op"),LW(212,9),Var("rm",FTy 5), + Var("cd",F4),LW(0,1),Mop(Cast F1,bVar"o2"),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("ConditionalSelect@64",CTy"Data", + TP[AVar F64,bVar"op",bVar"o2",Var("cd",F4),Var("rm",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1,1),Mop(Cast F1,bVar"op"),LW(212,9),Var("rm",FTy 5), + Var("cd",F4),LW(0,1),Mop(Cast F1,bVar"o2"),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("CountLeading@32",CTy"Data", + TP[AVar F32,bVar"op",Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(743426,21),Mop(Cast F1,bVar"op"),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("CountLeading@64",CTy"Data", + TP[AVar F64,bVar"op",Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1792002,21),Mop(Cast F1,bVar"op"),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("ExtractRegister@32",CTy"Data", + TP[AVar F32,Var("imms",FTy 6),Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + ITE(Bop(Bit,Var("imms",FTy 6),LN 5), + Call("BadCode",CTy"MachineCode",LS"ExtractRegister32"), + Call + ("ARM8",CTy"MachineCode", + CC[LW(156,11),Var("rm",FTy 5),Var("imms",FTy 6), + Var("rn",FTy 5),Var("rd",FTy 5)]))), + (Call + ("ExtractRegister@64",CTy"Data", + TP[AVar F64,Var("imms",FTy 6),Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1182,11),Var("rm",FTy 5),Var("imms",FTy 6), + Var("rn",FTy 5),Var("rd",FTy 5)])), + (Call + ("Division@32",CTy"Data", + TP[AVar F32,bVar"o1",Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(214,11),Var("rm",FTy 5),LW(1,5), + Mop(Cast F1,Mop(Not,bVar"o1")),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("Division@64",CTy"Data", + TP[AVar F64,bVar"o1",Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1238,11),Var("rm",FTy 5),LW(1,5), + Mop(Cast F1,Mop(Not,bVar"o1")),Var("rn",FTy 5), + Var("rd",FTy 5)])), + (Call + ("MultiplyAddSub@32",CTy"Data", + TP[AVar F32,bVar"o0",Var("rm",FTy 5),Var("ra",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(216,11),Var("rm",FTy 5),Mop(Cast F1,bVar"o0"), + Var("ra",FTy 5),Var("rn",FTy 5),Var("rd",FTy 5)])), + (Call + ("MultiplyAddSub@64",CTy"Data", + TP[AVar F64,bVar"o0",Var("rm",FTy 5),Var("ra",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1240,11),Var("rm",FTy 5),Mop(Cast F1,bVar"o0"), + Var("ra",FTy 5),Var("rn",FTy 5),Var("rd",FTy 5)])), + (Call + ("MultiplyAddSubLong",CTy"Data", + TP[bVar"o0",bVar"u",Var("rm",FTy 5),Var("ra",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(155,8),Mop(Cast F1,Mop(Not,bVar"u")),LW(1,2), + Var("rm",FTy 5),Mop(Cast F1,bVar"o0"),Var("ra",FTy 5), + Var("rn",FTy 5),Var("rd",FTy 5)])), + (Call + ("MultiplyHigh",CTy"Data", + TP[bVar"u",Var("rm",FTy 5),Var("rn",FTy 5),Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(155,8),Mop(Cast F1,Mop(Not,bVar"u")),LW(2,2), + Var("rm",FTy 5),LW(31,6),Var("rn",FTy 5),Var("rd",FTy 5)])), + (Call + ("Reverse@32",CTy"Data", + TP[AVar F32,Var("opc",CTy"RevOp"),Var("rn",FTy 5), + Var("rd",FTy 5)]), + ITE(EQ(Var("opc",CTy"RevOp"),LC("RevOp_REV64",CTy"RevOp")), + Call("BadCode",CTy"MachineCode",LS"Reverse32"), + Call + ("ARM8",CTy"MachineCode", + CC[LW(371712,20),Mop(Cast(FTy 2),Var("opc",CTy"RevOp")), + Var("rn",FTy 5),Var("rd",FTy 5)]))), + (Call + ("Reverse@64",CTy"Data", + TP[AVar F64,Var("opc",CTy"RevOp"),Var("rn",FTy 5), + Var("rd",FTy 5)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(896000,20),Mop(Cast(FTy 2),Var("opc",CTy"RevOp")), + Var("rn",FTy 5),Var("rd",FTy 5)]))])) +; +val e_debug_def = Def + ("e_debug",Var("i",CTy"Debug"), + CS(Var("i",CTy"Debug"), + [(Call("Breakpoint",CTy"Debug",Var("imm16",F16)), + CC[LW(1697,11),Var("imm16",F16),LW(0,5)]), + (Const("DebugRestore",CTy"Debug"),LW(3602842592,32)), + (Call("DebugSwitch",CTy"Debug",Var("LL",FTy 2)), + CC[LW(1701,11),LW(0,16),LW(0,3),Var("LL",FTy 2)]), + (Call("Halt",CTy"Debug",Var("imm16",F16)), + CC[LW(1698,11),Var("imm16",F16),LW(0,5)])])) +; +val e_crc_def = Def + ("e_crc",Var("i",CTy"CRCExt"), + CS(Var("i",CTy"CRCExt"), + [(Call + ("CRC@8",CTy"CRCExt", + TP[AVar F8,bVar"c",Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + CC[LW(214,11),Var("rm",FTy 5),LW(2,3),Mop(Cast F1,bVar"c"), + LW(0,2),Var("rn",FTy 5),Var("rd",FTy 5)]), + (Call + ("CRC@16",CTy"CRCExt", + TP[AVar F16,bVar"c",Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + CC[LW(214,11),Var("rm",FTy 5),LW(2,3),Mop(Cast F1,bVar"c"), + LW(1,2),Var("rn",FTy 5),Var("rd",FTy 5)]), + (Call + ("CRC@32",CTy"CRCExt", + TP[AVar F32,bVar"c",Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + CC[LW(214,11),Var("rm",FTy 5),LW(2,3),Mop(Cast F1,bVar"c"), + LW(2,2),Var("rn",FTy 5),Var("rd",FTy 5)]), + (Call + ("CRC@64",CTy"CRCExt", + TP[AVar F64,bVar"c",Var("rm",FTy 5),Var("rn",FTy 5), + Var("rd",FTy 5)]), + CC[LW(1238,11),Var("rm",FTy 5),LW(2,3),Mop(Cast F1,bVar"c"), + LW(3,2),Var("rn",FTy 5),Var("rd",FTy 5)])])) +; +val e_branch_def = Def + ("e_branch",Var("i",CTy"Branch"), + CS(Var("i",CTy"Branch"), + [(Call + ("BranchConditional",CTy"Branch",TP[Var("imm",F64),Var("cd",F4)]), + Let(Var("imm19",FTy 19),EX(Var("imm",F64),LN 20,LN 2,FTy 19), + ITE(EQ(Var("imm",F64), + Mop(SE F64,CC[Var("imm19",FTy 19),LW(0,2)])), + Call + ("ARM8",CTy"MachineCode", + CC[LW(84,8),Var("imm19",FTy 19),LW(0,1),Var("cd",F4)]), + Call("BadCode",CTy"MachineCode",LS"BranchConditional")))), + (Call + ("BranchImmediate",CTy"Branch", + TP[Var("imm",F64),Var("btype",CTy"BranchType")]), + Let(Var("imm26",FTy 26),EX(Var("imm",F64),LN 27,LN 2,FTy 26), + ITE(Bop(And, + EQ(Var("imm",F64), + Mop(SE F64,CC[Var("imm26",FTy 26),LW(0,2)])), + Bop(In,Var("btype",CTy"BranchType"), + SL[LC("BranchType_CALL",CTy"BranchType"), + LC("BranchType_JMP",CTy"BranchType")])), + Call + ("ARM8",CTy"MachineCode", + CC[Mop(Cast F1, + EQ(Var("btype",CTy"BranchType"), + LC("BranchType_CALL",CTy"BranchType"))), + LW(5,5),Var("imm26",FTy 26)]), + Call("BadCode",CTy"MachineCode",LS"BranchImmediate")))), + (Call + ("BranchRegister",CTy"Branch", + TP[Var("rn",FTy 5),Var("btype",CTy"BranchType")]), + Let(Var("opc",FTy 2), + CS(Var("btype",CTy"BranchType"), + [(LC("BranchType_JMP",CTy"BranchType"),LW(0,2)), + (LC("BranchType_CALL",CTy"BranchType"),LW(1,2)), + (LC("BranchType_RET",CTy"BranchType"),LW(2,2)), + (AVar(CTy"BranchType"),LW(3,2))]), + ITE(EQ(Var("opc",FTy 2),LW(3,2)), + Call("BadCode",CTy"MachineCode",LS"BranchRegister"), + Call + ("ARM8",CTy"MachineCode", + CC[LW(428,9),Var("opc",FTy 2),LW(1984,11), + Var("rn",FTy 5),LW(0,5)])))), + (Call + ("CompareAndBranch@32",CTy"Branch", + TP[AVar F32,bVar"iszero",Var("offset",F64),Var("rt",FTy 5)]), + Let(Var("imm19",FTy 19),EX(Var("offset",F64),LN 20,LN 2,FTy 19), + ITE(EQ(Var("offset",F64), + Mop(SE F64,CC[Var("imm19",FTy 19),LW(0,2)])), + Call + ("ARM8",CTy"MachineCode", + CC[LW(26,7),Mop(Cast F1,Mop(Not,bVar"iszero")), + Var("imm19",FTy 19),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"CompareAndBranch32")))), + (Call + ("CompareAndBranch@64",CTy"Branch", + TP[AVar F64,bVar"iszero",Var("offset",F64),Var("rt",FTy 5)]), + Let(Var("imm19",FTy 19),EX(Var("offset",F64),LN 20,LN 2,FTy 19), + ITE(EQ(Var("offset",F64), + Mop(SE F64,CC[Var("imm19",FTy 19),LW(0,2)])), + Call + ("ARM8",CTy"MachineCode", + CC[LW(90,7),Mop(Cast F1,Mop(Not,bVar"iszero")), + Var("imm19",FTy 19),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"CompareAndBranch64")))), + (Call + ("TestBitAndBranch@32",CTy"Branch", + TP[AVar F32,Var("bit_pos",FTy 6),bVar"bit_val", + Var("offset",F64),Var("rt",FTy 5)]), + Let(Var("imm14",FTy 14),EX(Var("offset",F64),LN 15,LN 2,FTy 14), + ITE(Bop(And, + EQ(Var("offset",F64), + Mop(SE F64,CC[Var("imm14",FTy 14),LW(0,2)])), + Mop(Not,Bop(Bit,Var("bit_pos",FTy 6),LN 5))), + Call + ("ARM8",CTy"MachineCode", + CC[LW(27,7),Mop(Cast F1,bVar"bit_val"), + EX(Var("bit_pos",FTy 6),LN 4,LN 0,FTy 5), + Var("imm14",FTy 14),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"TestBitAndBranch32")))), + (Call + ("TestBitAndBranch@64",CTy"Branch", + TP[AVar F64,Var("bit_pos",FTy 6),bVar"bit_val", + Var("offset",F64),Var("rt",FTy 5)]), + Let(Var("imm14",FTy 14),EX(Var("offset",F64),LN 15,LN 2,FTy 14), + ITE(Bop(And, + EQ(Var("offset",F64), + Mop(SE F64,CC[Var("imm14",FTy 14),LW(0,2)])), + Bop(Bit,Var("bit_pos",FTy 6),LN 5)), + Call + ("ARM8",CTy"MachineCode", + CC[LW(91,7),Mop(Cast F1,bVar"bit_val"), + EX(Var("bit_pos",FTy 6),LN 4,LN 0,FTy 5), + Var("imm14",FTy 14),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"TestBitAndBranch64"))))])) +; +val e_system_def = Def + ("e_system",Var("i",CTy"System"), + CS(Var("i",CTy"System"), + [(Call + ("MoveSystemRegister",CTy"System", + TP[bVar"l",Var("op0",FTy 3),Var("op1",FTy 3),Var("op2",FTy 3), + Var("crn",F4),Var("crm",F4),Var("rt",FTy 5)]), + CC[LW(852,10),Mop(Cast F1,bVar"l"),LW(1,1), + Mop(Cast F1,Bop(Sub,Var("op0",FTy 3),LW(2,3))), + Var("op1",FTy 3),Var("crn",F4),Var("crm",F4),Var("op2",FTy 3), + Var("rt",FTy 5)]), + (Call + ("MoveImmediateProcState",CTy"System", + TP[LC("PSTATEField_SP",CTy"PSTATEField"),Var("crm",F4)]), + CC[LW(872452,20),Var("crm",F4),LW(191,8)]), + (Call + ("MoveImmediateProcState",CTy"System", + TP[LC("PSTATEField_DAIFSet",CTy"PSTATEField"),Var("crm",F4)]), + CC[LW(872500,20),Var("crm",F4),LW(223,8)]), + (Call + ("MoveImmediateProcState",CTy"System", + TP[LC("PSTATEField_DAIFClr",CTy"PSTATEField"),Var("crm",F4)]), + CC[LW(872500,20),Var("crm",F4),LW(255,8)]), + (Const("ExceptionReturn",CTy"System"),LW(3600745440,32)), + (Call("SupervisorCall",CTy"System",Var("imm16",F16)), + CC[LW(1696,11),Var("imm16",F16),LW(1,5)]), + (Call("HypervisorCall",CTy"System",Var("imm16",F16)), + CC[LW(1696,11),Var("imm16",F16),LW(2,5)]), + (Call("SecureMonitorCall",CTy"System",Var("imm16",F16)), + CC[LW(1696,11),Var("imm16",F16),LW(3,5)]), + (Call + ("SystemInstruction",CTy"System", + TP[Var("op1",FTy 3),Var("op2",FTy 3),Var("crn",F4), + Var("crm",F4),bVar"l",Var("rt",FTy 5)]), + CC[LW(852,10),Mop(Cast F1,bVar"l"),LW(1,2),Var("op1",FTy 3), + Var("crn",F4),Var("crm",F4),Var("op2",FTy 3),Var("rt",FTy 5)])])) +; +val e_LoadStoreImmediate_def = Def + ("e_LoadStoreImmediate", + TP[Var("size",FTy 2),bVar"regsize_word",Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"signed",bVar"wback", + bVar"postindex",bVar"unsigned_offset",Var("offset",F64), + Var("rn",FTy 5),Var("rt",FTy 5)], + Let(Var("sz",FTy 2), + ITE(EQ(Var("memop",CTy"MemOp"),LC("MemOp_PREFETCH",CTy"MemOp")), + LW(3,2),Var("size",FTy 2)), + Let(Var("imm9",FTy 9),EX(Var("offset",F64),LN 8,LN 0,FTy 9), + Let(Var("imm12",FTy 12), + EX(Call + ("LSR",F64, + TP[Var("offset",F64),Mop(Cast nTy,Var("sz",FTy 2))]), + LN 11,LN 0,FTy 12), + Let(Var("opc",FTy 2), + ITB([(EQ(Var("memop",CTy"MemOp"), + LC("MemOp_STORE",CTy"MemOp")),LW(0,2)), + (Bop(And, + EQ(Var("memop",CTy"MemOp"), + LC("MemOp_LOAD",CTy"MemOp")), + Mop(Not,bVar"signed")),LW(1,2))], + CC[LW(1,1),Mop(Cast F1,bVar"regsize_word")]), + ITB([(bVar"wback", + ITE(Bop(And, + EQ(Var("offset",F64), + Mop(SE F64,Var("imm9",FTy 9))), + EQ(Var("acctype",CTy"AccType"), + LC("AccType_NORMAL",CTy"AccType"))), + Call + ("ARM8",CTy"MachineCode", + CC[Var("sz",FTy 2),LW(56,6), + Var("opc",FTy 2),LW(0,1), + Var("imm9",FTy 9), + Mop(Cast F1,Mop(Not,bVar"postindex")), + LW(1,1),Var("rn",FTy 5),Var("rt",FTy 5)]), + Call + ("BadCode",CTy"MachineCode", + LS"LoadStoreImmediate"))), + (bVar"postindex", + Call + ("BadCode",CTy"MachineCode", + LS"LoadStoreImmediate")), + (Bop(And, + Bop(And,bVar"unsigned_offset", + EQ(Var("offset",F64), + Call + ("LSL",F64, + TP[Mop(Cast F64,Var("imm12",FTy 12)), + Mop(Cast nTy,Var("sz",FTy 2))]))), + EQ(Var("acctype",CTy"AccType"), + LC("AccType_NORMAL",CTy"AccType"))), + Call + ("ARM8",CTy"MachineCode", + CC[Var("sz",FTy 2),LW(57,6),Var("opc",FTy 2), + Var("imm12",FTy 12),Var("rn",FTy 5), + Var("rt",FTy 5)])), + (EQ(Var("offset",F64), + Mop(SE F64,Var("imm9",FTy 9))), + Call + ("ARM8",CTy"MachineCode", + CC[Var("sz",FTy 2),LW(56,6),Var("opc",FTy 2), + LW(0,1),Var("imm9",FTy 9), + Mop(Cast F1, + EQ(Var("acctype",CTy"AccType"), + LC("AccType_UNPRIV",CTy"AccType"))), + LW(0,1),Var("rn",FTy 5),Var("rt",FTy 5)]))], + Call + ("BadCode",CTy"MachineCode", + LS"LoadStoreImmediate"))))))) +; +val e_LoadStoreRegister_def = Def + ("e_LoadStoreRegister", + TP[Var("size",FTy 2),bVar"regsize_word",Var("memop",CTy"MemOp"), + bVar"signed",Var("rm",FTy 5),Var("extend_type",CTy"ExtendType"), + nVar"shift",Var("rn",FTy 5),Var("rt",FTy 5)], + Call + ("ARM8",CTy"MachineCode", + CC[ITE(EQ(Var("memop",CTy"MemOp"),LC("MemOp_PREFETCH",CTy"MemOp")), + LW(3,2),Var("size",FTy 2)),LW(56,6), + ITB([(EQ(Var("memop",CTy"MemOp"),LC("MemOp_STORE",CTy"MemOp")), + LW(0,2)), + (Bop(And, + EQ(Var("memop",CTy"MemOp"),LC("MemOp_LOAD",CTy"MemOp")), + Mop(Not,bVar"signed")),LW(1,2))], + CC[LW(1,1),Mop(Cast F1,bVar"regsize_word")]),LW(1,1), + Var("rm",FTy 5), + Mop(Cast(FTy 3),Var("extend_type",CTy"ExtendType")), + Mop(Cast F1,Mop(Not,EQ(nVar"shift",LN 0))),LW(2,2), + Var("rn",FTy 5),Var("rt",FTy 5)])) +; +val e_load_store_def = Def + ("e_load_store",Var("i",CTy"LoadStore"), + CS(Var("i",CTy"LoadStore"), + [(Call + ("LoadStoreImmediate@8",CTy"LoadStore", + TP[Var("size",F8),bVar"regsize_word",Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"signed",bVar"wb_unknown", + bVar"rt_unknown",bVar"wback",bVar"postindex", + bVar"unsigned_offset",Var("offset",F64),Var("rn",FTy 5), + Var("rt",FTy 5)]), + Call + ("e_LoadStoreImmediate",CTy"MachineCode", + TP[Mop(Cast(FTy 2),Var("size",F8)),bVar"regsize_word", + Var("memop",CTy"MemOp"),Var("acctype",CTy"AccType"), + bVar"signed",bVar"wback",bVar"postindex", + bVar"unsigned_offset",Var("offset",F64),Var("rn",FTy 5), + Var("rt",FTy 5)])), + (Call + ("LoadStoreImmediate@16",CTy"LoadStore", + TP[Var("size",F16),bVar"regsize_word",Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"signed",bVar"wb_unknown", + bVar"rt_unknown",bVar"wback",bVar"postindex", + bVar"unsigned_offset",Var("offset",F64),Var("rn",FTy 5), + Var("rt",FTy 5)]), + Call + ("e_LoadStoreImmediate",CTy"MachineCode", + TP[Mop(Cast(FTy 2),Var("size",F16)),bVar"regsize_word", + Var("memop",CTy"MemOp"),Var("acctype",CTy"AccType"), + bVar"signed",bVar"wback",bVar"postindex", + bVar"unsigned_offset",Var("offset",F64),Var("rn",FTy 5), + Var("rt",FTy 5)])), + (Call + ("LoadStoreImmediate@32",CTy"LoadStore", + TP[Var("size",F32),bVar"regsize_word",Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"signed",bVar"wb_unknown", + bVar"rt_unknown",bVar"wback",bVar"postindex", + bVar"unsigned_offset",Var("offset",F64),Var("rn",FTy 5), + Var("rt",FTy 5)]), + Call + ("e_LoadStoreImmediate",CTy"MachineCode", + TP[Mop(Cast(FTy 2),Var("size",F32)),bVar"regsize_word", + Var("memop",CTy"MemOp"),Var("acctype",CTy"AccType"), + bVar"signed",bVar"wback",bVar"postindex", + bVar"unsigned_offset",Var("offset",F64),Var("rn",FTy 5), + Var("rt",FTy 5)])), + (Call + ("LoadStoreImmediate@64",CTy"LoadStore", + TP[Var("size",F64),bVar"regsize_word",Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"signed",bVar"wb_unknown", + bVar"rt_unknown",bVar"wback",bVar"postindex", + bVar"unsigned_offset",Var("offset",F64),Var("rn",FTy 5), + Var("rt",FTy 5)]), + Call + ("e_LoadStoreImmediate",CTy"MachineCode", + TP[Mop(Cast(FTy 2),Var("size",F64)),bVar"regsize_word", + Var("memop",CTy"MemOp"),Var("acctype",CTy"AccType"), + bVar"signed",bVar"wback",bVar"postindex", + bVar"unsigned_offset",Var("offset",F64),Var("rn",FTy 5), + Var("rt",FTy 5)])), + (Call + ("LoadStoreRegister@8",CTy"LoadStore", + TP[Var("size",F8),bVar"regsize_word",Var("memop",CTy"MemOp"), + bVar"signed",Var("rm",FTy 5), + Var("extend_type",CTy"ExtendType"),nVar"shift", + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call + ("e_LoadStoreRegister",CTy"MachineCode", + TP[Mop(Cast(FTy 2),Var("size",F8)),bVar"regsize_word", + Var("memop",CTy"MemOp"),bVar"signed",Var("rm",FTy 5), + Var("extend_type",CTy"ExtendType"),nVar"shift", + Var("rn",FTy 5),Var("rt",FTy 5)])), + (Call + ("LoadStoreRegister@16",CTy"LoadStore", + TP[Var("size",F16),bVar"regsize_word",Var("memop",CTy"MemOp"), + bVar"signed",Var("rm",FTy 5), + Var("extend_type",CTy"ExtendType"),nVar"shift", + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call + ("e_LoadStoreRegister",CTy"MachineCode", + TP[Mop(Cast(FTy 2),Var("size",F16)),bVar"regsize_word", + Var("memop",CTy"MemOp"),bVar"signed",Var("rm",FTy 5), + Var("extend_type",CTy"ExtendType"),nVar"shift", + Var("rn",FTy 5),Var("rt",FTy 5)])), + (Call + ("LoadStoreRegister@32",CTy"LoadStore", + TP[Var("size",F32),bVar"regsize_word",Var("memop",CTy"MemOp"), + bVar"signed",Var("rm",FTy 5), + Var("extend_type",CTy"ExtendType"),nVar"shift", + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call + ("e_LoadStoreRegister",CTy"MachineCode", + TP[Mop(Cast(FTy 2),Var("size",F32)),bVar"regsize_word", + Var("memop",CTy"MemOp"),bVar"signed",Var("rm",FTy 5), + Var("extend_type",CTy"ExtendType"),nVar"shift", + Var("rn",FTy 5),Var("rt",FTy 5)])), + (Call + ("LoadStoreRegister@64",CTy"LoadStore", + TP[Var("size",F64),bVar"regsize_word",Var("memop",CTy"MemOp"), + bVar"signed",Var("rm",FTy 5), + Var("extend_type",CTy"ExtendType"),nVar"shift", + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call + ("e_LoadStoreRegister",CTy"MachineCode", + TP[Mop(Cast(FTy 2),Var("size",F64)),bVar"regsize_word", + Var("memop",CTy"MemOp"),bVar"signed",Var("rm",FTy 5), + Var("extend_type",CTy"ExtendType"),nVar"shift", + Var("rn",FTy 5),Var("rt",FTy 5)])), + (Call + ("LoadLiteral@32",CTy"LoadStore", + TP[AVar F32,Var("memop",CTy"MemOp"),bVar"signed", + Var("offset",F64),Var("rt",FTy 5)]), + Let(Var("imm19",FTy 19),EX(Var("offset",F64),LN 20,LN 2,FTy 19), + Let(Var("opc",OTy(FTy 2)), + CS(TP[Var("memop",CTy"MemOp"),bVar"signed"], + [(TP[LC("MemOp_LOAD",CTy"MemOp"),LF],Mop(Some,LW(0,2))), + (TP[LC("MemOp_LOAD",CTy"MemOp"),LT],Mop(Some,LW(2,2))), + (TP[LC("MemOp_PREFETCH",CTy"MemOp"),LF], + Mop(Some,LW(3,2))), + (AVar(PTy(CTy"MemOp",bTy)),LO(FTy 2))]), + ITE(Bop(And,Mop(IsSome,Var("opc",OTy(FTy 2))), + EQ(Var("offset",F64), + Mop(SE F64,CC[Var("imm19",FTy 19),LW(0,2)]))), + Call + ("ARM8",CTy"MachineCode", + CC[Mop(ValOf,Var("opc",OTy(FTy 2))),LW(24,6), + Var("imm19",FTy 19),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadLiteral32"))))), + (Call + ("LoadLiteral@64",CTy"LoadStore", + TP[AVar F64,LC("MemOp_LOAD",CTy"MemOp"),LF,Var("offset",F64), + Var("rt",FTy 5)]), + Let(Var("imm19",FTy 19),EX(Var("offset",F64),LN 20,LN 2,FTy 19), + ITE(EQ(Var("offset",F64), + Mop(SE F64,CC[Var("imm19",FTy 19),LW(0,2)])), + Call + ("ARM8",CTy"MachineCode", + CC[LW(88,8),Var("imm19",FTy 19),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadLiteral64")))), + (Call + ("LoadLiteral@64",CTy"LoadStore", + AVar(PTy(F64,PTy(CTy"MemOp",PTy(bTy,PTy(F64,FTy 5)))))), + Call("BadCode",CTy"MachineCode",LS"LoadLiteral64")), + (Call + ("LoadStorePair@32",CTy"LoadStore", + TP[Var("size",F32),Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"signed",bVar"wb_unknown", + bVar"rt_unknown",bVar"wback",bVar"postindex", + Var("offset",F64),Var("rn",FTy 5),Var("rt",FTy 5), + Var("rt2",FTy 5)]), + Let(Var("sf",F1),Mop(Cast F1,Var("size",F32)), + Let(nVar"scale",Bop(Add,LN 2,Mop(Cast nTy,Var("sf",F1))), + Let(Var("imm7",FTy 7), + EX(Call("LSR",F64,TP[Var("offset",F64),nVar"scale"]), + LN 6,LN 0,FTy 7), + ITE(Bop(And, + Bop(And, + Bop(And, + EQ(EQ(Var("sf",F1),LW(1,1)), + EQ(Mop(Size,Var("size",F32)),LN 64)), + Bop(In,Var("memop",CTy"MemOp"), + SL[LC("MemOp_LOAD",CTy"MemOp"), + LC("MemOp_STORE",CTy"MemOp")])), + Bop(In,Var("acctype",CTy"AccType"), + SL[LC("AccType_STREAM",CTy"AccType"), + LC("AccType_NORMAL",CTy"AccType")])), + EQ(Var("offset",F64), + Call + ("LSL",F64, + TP[Mop(SE F64,Var("imm7",FTy 7)), + nVar"scale"]))), + Call + ("ARM8",CTy"MachineCode", + CC[Var("sf",F1),Mop(Cast F1,bVar"signed"), + LW(20,5), + Mop(Cast F1,Mop(Not,bVar"postindex")), + Mop(Cast F1,bVar"wback"), + Mop(Cast F1, + EQ(Var("memop",CTy"MemOp"), + LC("MemOp_LOAD",CTy"MemOp"))), + Var("imm7",FTy 7),Var("rt2",FTy 5), + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadStorePair")))))), + (Call + ("LoadStorePair@64",CTy"LoadStore", + TP[Var("size",F64),Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"signed",bVar"wb_unknown", + bVar"rt_unknown",bVar"wback",bVar"postindex", + Var("offset",F64),Var("rn",FTy 5),Var("rt",FTy 5), + Var("rt2",FTy 5)]), + Let(Var("sf",F1),Mop(Cast F1,Var("size",F64)), + Let(nVar"scale",Bop(Add,LN 2,Mop(Cast nTy,Var("sf",F1))), + Let(Var("imm7",FTy 7), + EX(Call("LSR",F64,TP[Var("offset",F64),nVar"scale"]), + LN 6,LN 0,FTy 7), + ITE(Bop(And, + Bop(And, + Bop(And, + EQ(EQ(Var("sf",F1),LW(1,1)), + EQ(Mop(Size,Var("size",F64)),LN 64)), + Bop(In,Var("memop",CTy"MemOp"), + SL[LC("MemOp_LOAD",CTy"MemOp"), + LC("MemOp_STORE",CTy"MemOp")])), + Bop(In,Var("acctype",CTy"AccType"), + SL[LC("AccType_STREAM",CTy"AccType"), + LC("AccType_NORMAL",CTy"AccType")])), + EQ(Var("offset",F64), + Call + ("LSL",F64, + TP[Mop(SE F64,Var("imm7",FTy 7)), + nVar"scale"]))), + Call + ("ARM8",CTy"MachineCode", + CC[Var("sf",F1),Mop(Cast F1,bVar"signed"), + LW(20,5), + Mop(Cast F1,Mop(Not,bVar"postindex")), + Mop(Cast F1,bVar"wback"), + Mop(Cast F1, + EQ(Var("memop",CTy"MemOp"), + LC("MemOp_LOAD",CTy"MemOp"))), + Var("imm7",FTy 7),Var("rt2",FTy 5), + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadStorePair")))))), + (Call + ("LoadStoreAcquire@8",CTy"LoadStore", + TP[Var("size",F8),Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"excl",bVar"rn_unknown", + bVar"rt_unknown",Var("rs",FTy 5),Var("rn",FTy 5), + Var("rt",FTy 5)]), + ITE(Bop(And, + Bop(And, + CS(Mop(Size,Var("size",F8)), + [(LN 8,EQ(Var("size",F8),LW(0,8))), + (LN 16,EQ(Var("size",F8),LW(1,8))), + (LN 32,EQ(Var("size",F8),LW(2,8))), + (AVar nTy,EQ(Var("size",F8),LW(3,8)))]), + Bop(In,Var("memop",CTy"MemOp"), + SL[LC("MemOp_LOAD",CTy"MemOp"), + LC("MemOp_STORE",CTy"MemOp")])), + Bop(In,Var("acctype",CTy"AccType"), + SL[LC("AccType_ORDERED",CTy"AccType"), + LC("AccType_ATOMIC",CTy"AccType")])), + Call + ("ARM8",CTy"MachineCode", + CC[Mop(Cast(FTy 2),Var("size",F8)),LW(8,6), + Mop(Cast F1,Mop(Not,bVar"excl")), + Mop(Cast F1, + EQ(Var("memop",CTy"MemOp"), + LC("MemOp_LOAD",CTy"MemOp"))),LW(0,1), + Var("rs",FTy 5), + Mop(Cast F1, + EQ(Var("acctype",CTy"AccType"), + LC("AccType_ORDERED",CTy"AccType"))),LW(31,5), + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadStoreAcquire"))), + (Call + ("LoadStoreAcquire@16",CTy"LoadStore", + TP[Var("size",F16),Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"excl",bVar"rn_unknown", + bVar"rt_unknown",Var("rs",FTy 5),Var("rn",FTy 5), + Var("rt",FTy 5)]), + ITE(Bop(And, + Bop(And, + CS(Mop(Size,Var("size",F16)), + [(LN 8,EQ(Var("size",F16),LW(0,16))), + (LN 16,EQ(Var("size",F16),LW(1,16))), + (LN 32,EQ(Var("size",F16),LW(2,16))), + (AVar nTy,EQ(Var("size",F16),LW(3,16)))]), + Bop(In,Var("memop",CTy"MemOp"), + SL[LC("MemOp_LOAD",CTy"MemOp"), + LC("MemOp_STORE",CTy"MemOp")])), + Bop(In,Var("acctype",CTy"AccType"), + SL[LC("AccType_ORDERED",CTy"AccType"), + LC("AccType_ATOMIC",CTy"AccType")])), + Call + ("ARM8",CTy"MachineCode", + CC[Mop(Cast(FTy 2),Var("size",F16)),LW(8,6), + Mop(Cast F1,Mop(Not,bVar"excl")), + Mop(Cast F1, + EQ(Var("memop",CTy"MemOp"), + LC("MemOp_LOAD",CTy"MemOp"))),LW(0,1), + Var("rs",FTy 5), + Mop(Cast F1, + EQ(Var("acctype",CTy"AccType"), + LC("AccType_ORDERED",CTy"AccType"))),LW(31,5), + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadStoreAcquire"))), + (Call + ("LoadStoreAcquire@32",CTy"LoadStore", + TP[Var("size",F32),Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"excl",bVar"rn_unknown", + bVar"rt_unknown",Var("rs",FTy 5),Var("rn",FTy 5), + Var("rt",FTy 5)]), + ITE(Bop(And, + Bop(And, + CS(Mop(Size,Var("size",F32)), + [(LN 8,EQ(Var("size",F32),LW(0,32))), + (LN 16,EQ(Var("size",F32),LW(1,32))), + (LN 32,EQ(Var("size",F32),LW(2,32))), + (AVar nTy,EQ(Var("size",F32),LW(3,32)))]), + Bop(In,Var("memop",CTy"MemOp"), + SL[LC("MemOp_LOAD",CTy"MemOp"), + LC("MemOp_STORE",CTy"MemOp")])), + Bop(In,Var("acctype",CTy"AccType"), + SL[LC("AccType_ORDERED",CTy"AccType"), + LC("AccType_ATOMIC",CTy"AccType")])), + Call + ("ARM8",CTy"MachineCode", + CC[Mop(Cast(FTy 2),Var("size",F32)),LW(8,6), + Mop(Cast F1,Mop(Not,bVar"excl")), + Mop(Cast F1, + EQ(Var("memop",CTy"MemOp"), + LC("MemOp_LOAD",CTy"MemOp"))),LW(0,1), + Var("rs",FTy 5), + Mop(Cast F1, + EQ(Var("acctype",CTy"AccType"), + LC("AccType_ORDERED",CTy"AccType"))),LW(31,5), + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadStoreAcquire"))), + (Call + ("LoadStoreAcquire@64",CTy"LoadStore", + TP[Var("size",F64),Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"excl",bVar"rn_unknown", + bVar"rt_unknown",Var("rs",FTy 5),Var("rn",FTy 5), + Var("rt",FTy 5)]), + ITE(Bop(And, + Bop(And, + CS(Mop(Size,Var("size",F64)), + [(LN 8,EQ(Var("size",F64),LW(0,64))), + (LN 16,EQ(Var("size",F64),LW(1,64))), + (LN 32,EQ(Var("size",F64),LW(2,64))), + (AVar nTy,EQ(Var("size",F64),LW(3,64)))]), + Bop(In,Var("memop",CTy"MemOp"), + SL[LC("MemOp_LOAD",CTy"MemOp"), + LC("MemOp_STORE",CTy"MemOp")])), + Bop(In,Var("acctype",CTy"AccType"), + SL[LC("AccType_ORDERED",CTy"AccType"), + LC("AccType_ATOMIC",CTy"AccType")])), + Call + ("ARM8",CTy"MachineCode", + CC[Mop(Cast(FTy 2),Var("size",F64)),LW(8,6), + Mop(Cast F1,Mop(Not,bVar"excl")), + Mop(Cast F1, + EQ(Var("memop",CTy"MemOp"), + LC("MemOp_LOAD",CTy"MemOp"))),LW(0,1), + Var("rs",FTy 5), + Mop(Cast F1, + EQ(Var("acctype",CTy"AccType"), + LC("AccType_ORDERED",CTy"AccType"))),LW(31,5), + Var("rn",FTy 5),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadStoreAcquire"))), + (Call + ("LoadStoreAcquirePair@64",CTy"LoadStore", + TP[Var("size",F64),Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"rn_unknown", + bVar"rt_unknown",Var("rs",FTy 5),Var("rn",FTy 5), + Var("rt",FTy 5),Var("rt2",FTy 5)]), + ITE(Bop(And, + Bop(And, + EQ(Var("size",F64), + ITE(EQ(Mop(Size,Var("size",F64)),LN 64),LW(2,64), + LW(3,64))), + Bop(In,Var("memop",CTy"MemOp"), + SL[LC("MemOp_LOAD",CTy"MemOp"), + LC("MemOp_STORE",CTy"MemOp")])), + Bop(In,Var("acctype",CTy"AccType"), + SL[LC("AccType_ORDERED",CTy"AccType"), + LC("AccType_ATOMIC",CTy"AccType")])), + Call + ("ARM8",CTy"MachineCode", + CC[Mop(Cast(FTy 2),Var("size",F64)),LW(16,7), + Mop(Cast F1, + EQ(Var("memop",CTy"MemOp"), + LC("MemOp_LOAD",CTy"MemOp"))),LW(1,1), + Var("rs",FTy 5), + Mop(Cast F1, + EQ(Var("acctype",CTy"AccType"), + LC("AccType_ORDERED",CTy"AccType"))), + Var("rt2",FTy 5),Var("rn",FTy 5),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadStoreAcquirePair"))), + (Call + ("LoadStoreAcquirePair@128",CTy"LoadStore", + TP[Var("size",FTy 128),Var("memop",CTy"MemOp"), + Var("acctype",CTy"AccType"),bVar"rn_unknown", + bVar"rt_unknown",Var("rs",FTy 5),Var("rn",FTy 5), + Var("rt",FTy 5),Var("rt2",FTy 5)]), + ITE(Bop(And, + Bop(And, + EQ(Var("size",FTy 128), + ITE(EQ(Mop(Size,Var("size",FTy 128)),LN 64), + LW(2,128),LW(3,128))), + Bop(In,Var("memop",CTy"MemOp"), + SL[LC("MemOp_LOAD",CTy"MemOp"), + LC("MemOp_STORE",CTy"MemOp")])), + Bop(In,Var("acctype",CTy"AccType"), + SL[LC("AccType_ORDERED",CTy"AccType"), + LC("AccType_ATOMIC",CTy"AccType")])), + Call + ("ARM8",CTy"MachineCode", + CC[Mop(Cast(FTy 2),Var("size",FTy 128)),LW(16,7), + Mop(Cast F1, + EQ(Var("memop",CTy"MemOp"), + LC("MemOp_LOAD",CTy"MemOp"))),LW(1,1), + Var("rs",FTy 5), + Mop(Cast F1, + EQ(Var("acctype",CTy"AccType"), + LC("AccType_ORDERED",CTy"AccType"))), + Var("rt2",FTy 5),Var("rn",FTy 5),Var("rt",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"LoadStoreAcquirePair")))])) +; +val Encode_def = Def + ("Encode", + TP[Var("imm_enc",ATy(CTy"imm32_64",OTy(PTy(F1,PTy(FTy 6,FTy 6))))), + Var("i",CTy"instruction")], + CS(Var("i",CTy"instruction"), + [(Call + ("Address",CTy"instruction", + TP[bVar"page",Var("imm",F64),Var("rd",FTy 5)]), + ITE(bVar"page", + Let(Var("immlo",FTy 2),EX(Var("imm",F64),LN 13,LN 12,FTy 2), + Let(Var("immhi",FTy 19), + EX(Var("imm",F64),LN 32,LN 14,FTy 19), + ITE(EQ(Mop(SE F64, + CC[Var("immhi",FTy 19),Var("immlo",FTy 2), + LW(0,12)]),Var("imm",F64)), + Call + ("ARM8",CTy"MachineCode", + CC[LW(1,1),Var("immlo",FTy 2),LW(16,5), + Var("immhi",FTy 19),Var("rd",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"Address")))), + Let(Var("immlo",FTy 2),EX(Var("imm",F64),LN 1,LN 0,FTy 2), + Let(Var("immhi",FTy 19), + EX(Var("imm",F64),LN 20,LN 2,FTy 19), + ITE(EQ(Mop(SE F64, + CC[Var("immhi",FTy 19),Var("immlo",FTy 2)]), + Var("imm",F64)), + Call + ("ARM8",CTy"MachineCode", + CC[LW(0,1),Var("immlo",FTy 2),LW(16,5), + Var("immhi",FTy 19),Var("rd",FTy 5)]), + Call("BadCode",CTy"MachineCode",LS"Address")))))), + (Call("Data",CTy"instruction",Var("x",CTy"Data")), + Call + ("e_data",CTy"MachineCode", + TP[Var("imm_enc", + ATy(CTy"imm32_64",OTy(PTy(F1,PTy(FTy 6,FTy 6))))), + Var("x",CTy"Data")])), + (Call("Branch",CTy"instruction",Var("x",CTy"Branch")), + Call("e_branch",CTy"MachineCode",Var("x",CTy"Branch"))), + (Call("LoadStore",CTy"instruction",Var("x",CTy"LoadStore")), + Call("e_load_store",CTy"MachineCode",Var("x",CTy"LoadStore"))), + (Call("CRCExt",CTy"instruction",Var("x",CTy"CRCExt")), + Call + ("ARM8",CTy"MachineCode",Call("e_crc",F32,Var("x",CTy"CRCExt")))), + (Call("Debug",CTy"instruction",Var("x",CTy"Debug")), + Call + ("ARM8",CTy"MachineCode",Call("e_debug",F32,Var("x",CTy"Debug")))), + (Call("System",CTy"instruction",Var("x",CTy"System")), + Call + ("ARM8",CTy"MachineCode", + Call("e_system",F32,Var("x",CTy"System")))), + (Call + ("MemoryBarrier",CTy"instruction", + TP[Var("opc",CTy"MemBarrierOp"),Var("crm",F4)]), + Call + ("ARM8",CTy"MachineCode", + CC[LW(872499,20),Var("crm",F4),LW(1,1), + Mop(Cast(FTy 2),Var("opc",CTy"MemBarrierOp")),LW(31,5)])), + (Call("ClearExclusive",CTy"instruction",Var("crm",F4)), + Call + ("ARM8",CTy"MachineCode", + CC[LW(872499,20),Var("crm",F4),LW(95,8)])), + (Call("Hint",CTy"instruction",Var("opc",CTy"SystemHintOp")), + Call + ("ARM8",CTy"MachineCode", + CC[LW(13959968,24), + Mop(Cast(FTy 3),Var("opc",CTy"SystemHintOp")),LW(31,5)])), + (Const("Unallocated",CTy"instruction"), + Call("BadCode",CTy"MachineCode",LS"Unallocated")), + (Const("Reserved",CTy"instruction"), + Call("BadCode",CTy"MachineCode",LS"Reserved"))])) val () = Import.finish 1 \ No newline at end of file diff --git a/examples/l3-machine-code/arm8/model/arm8_encodeScript.sml b/examples/l3-machine-code/arm8/model/arm8_encodeScript.sml new file mode 100644 index 0000000000..ae75092ea7 --- /dev/null +++ b/examples/l3-machine-code/arm8/model/arm8_encodeScript.sml @@ -0,0 +1,48 @@ +open HolKernel boolLib bossLib +open arm8AssemblerLib +open sptreeTheory arm8Theory + +val () = new_theory "arm8_encode" + +(* ----------------------------------------------------------------------- *) + +(* + +val () = Globals.max_print_depth := 10 + +*) + +val () = sptreeSyntax.temp_add_sptree_printer() + +val sptree_mask32_def = zDefine `sptree_mask32 = ^m32` +val sptree_mask64_def = zDefine `sptree_mask64 = ^m64` + +val EncodeBitMask_def = zDefine` + (EncodeBitMask (Imm32 i) = sptree$lookup (w2n i) sptree_mask32) /\ + (EncodeBitMask (Imm64 i) = sptree$lookup (w2n i) sptree_mask64)` + +val InstructionEncode_def = Define` + InstructionEncode ast = arm8$Encode (EncodeBitMask, ast)` + +val () = export_theory () + +(* ----------------------------------------------------------------------- *) + +(* Testing + +open sptreeSyntax wordsLib arm8_encodeTheory + +val EncodeBitMask_CONV = PURE_REWRITE_CONV [EncodeBitMask_def] THENC lookup_CONV +val () = computeLib.add_convs [(``EncodeBitMask``, 1, EncodeBitMask_CONV)] + +Count.apply EVAL ``EncodeBitMask (Imm32 0xFFw)`` +Count.apply EVAL ``EncodeBitMask (Imm64 0xFFw)`` + +val () = Globals.max_print_depth := ~1 + +open MutableMap arm8AssemblerLib + +EVAL ``size ^(arm8AssemblerLib.m32)`` (* 1302 *) +EVAL ``size ^(arm8AssemblerLib.m64)`` (* 5334 *) + +*) diff --git a/examples/l3-machine-code/arm8/step/arm8_stepLib.sml b/examples/l3-machine-code/arm8/step/arm8_stepLib.sml index 4c61099aa8..48c3640f3a 100644 --- a/examples/l3-machine-code/arm8/step/arm8_stepLib.sml +++ b/examples/l3-machine-code/arm8/step/arm8_stepLib.sml @@ -139,6 +139,9 @@ val Address_rwt = (* ---------------------------- *) +val Nop_rwt = + EV [dfn'Hint_def] [] [] ``dfn'Hint SystemHintOp_NOP`` + val AddSubCarry_rwt = EV [dfn'AddSubCarry_def] (SPLIT_31 "d") (TF0 `setflags`) ``dfn'AddSubCarry (sf, sub_op, setflags, m, n, d)`` @@ -485,7 +488,13 @@ local v2w [x2; x3; x4; x5; x6; x7],F)= SOME (imm:word64, x)` ] - val r1 = REWRITE_RULE [] + val r_rwt = + utilsLib.map_conv + (EVAL THENC REWRITE_CONV [arm8Theory.num2SystemHintOp_thm]) + [``v2w [F; F; F] <+ 6w: word3``, + ``arm8$num2SystemHintOp (w2n (v2w [F; F; F]: word3))``] + + val r1 = REWRITE_RULE [r_rwt] val r2 = utilsLib.INST_REWRITE_RULE (LoadStoreImmediate @ LoadStorePair) val r3 = utilsLib.ALL_HYP_CONV_RULE @@ -612,7 +621,8 @@ val ps = (List.concat o List.map decode_rwt) ("LoadStoreRegister", "..TTTFFF..T______T__TF__________"), ("StorePair32", "FFTFTFF_.F______________________"), ("LoadPair32", "F_TFTFF_.T______________________"), - ("LoadStorePair64", "TFTFTFF_..______________________") + ("LoadStorePair64", "TFTFTFF_..______________________"), + ("NoOperation", "TTFTFTFTFFFFFFTTFFTFFFFFFFFTTTTT") ] local @@ -678,7 +688,7 @@ local MultiplyHigh_rwt @ Reverse32_rwt @ Reverse64_rwt @ CRC_rwt @ BranchImmediate_rwt @ BranchRegister_rwt @ BranchConditional_rwt @ CompareAndBranch_rwt @ TestBitAndBranch_rwt @ LoadStoreImmediate_rwt @ - LoadStoreRegister_rwt @ LoadLiteral_rwt @ LoadStorePair_rwt + LoadStoreRegister_rwt @ LoadLiteral_rwt @ LoadStorePair_rwt @ Nop_rwt ) val get_next = Term.rator o utilsLib.lhsc val r = REWRITE_RULE [] diff --git a/examples/l3-machine-code/lib/L3.sig b/examples/l3-machine-code/lib/L3.sig index 1c67836f1e..09a5222d29 100644 --- a/examples/l3-machine-code/lib/L3.sig +++ b/examples/l3-machine-code/lib/L3.sig @@ -5,13 +5,18 @@ signature L3 = sig val K : 'a -> 'b -> 'a + val drop : int * 'a list -> 'a list + val dropString : int * string -> string + val element : int * 'a list -> 'a val equal : ''a -> ''a -> bool - val for : int * int * (int -> 'a) -> unit + val for : int * int * (int -> unit) -> unit + val foreach : 'a list * ('a -> unit) -> unit + val indexOf : ''a * ''a list -> int option + val indexOfString : char * string -> int option val fst : 'a * 'b -> 'a val listCompare : ('a * 'a -> order) -> 'a list * 'a list -> order val lowercase : string -> string - val mem : ''a * ''a list -> bool - val mkSet : ''a list -> ''a list + val memString : char * string -> bool val padLeft : 'a * (int * 'a list) -> 'a list val padLeftString : char * (int * string) -> string val padRight : 'a * (int * 'a list) -> 'a list @@ -19,12 +24,21 @@ sig val pairCompare : ('a * 'a -> order) * ('b * 'b -> order) -> ('a * 'b) * ('a * 'b) -> order val prefix : char * string -> string + val remove : ''a list * ''a list -> ''a list + val removeExceptString : string * string -> string + val removeString : string * string -> string + val removeDuplicatesString : string -> string + val revLookup : ('a -> 'a -> bool) -> 'a * 'a list -> int option val revString : string -> string val snd : 'a * 'b -> 'b val splitl : (char -> bool) * string -> string * string val splitr : (char -> bool) * string -> string * string val strHd : string -> char val strTl : string -> string + val stringToChar : string -> char + val swap : 'a * 'b -> 'b * 'a + val take : int * 'a list -> 'a list + val takeString : int * string -> string val uncurry : ('a -> 'b -> 'c) -> 'a * 'b -> 'c val update : (''a -> 'b) -> ''a -> 'b -> ''a -> 'b val uppercase : string -> string diff --git a/examples/l3-machine-code/lib/L3.sml b/examples/l3-machine-code/lib/L3.sml index 1729806d78..24fd0831eb 100644 --- a/examples/l3-machine-code/lib/L3.sml +++ b/examples/l3-machine-code/lib/L3.sml @@ -27,6 +27,9 @@ struct else for (if Nat.< (i, j) then Nat.suc i else Nat.pred i, j, a) ) + fun foreach ([], _) = () + | foreach (h :: t, a) = (a h; foreach (t, a)) + fun pairCompare (cmp1, cmp2) ((a: 'a, b: 'b), (c: 'a, d :'b)) = case cmp1 (a, c) of General.EQUAL => cmp2 (b, d) @@ -46,15 +49,6 @@ struct ((List.length l1, l1), (List.length l2, l2)) end - fun mem (i, l) = List.exists (fn x => x = i) l - - local - fun insert i l = if mem (i, l) then l else i :: l - in - fun mkSet [] = [] - | mkSet (h :: t) = insert h (mkSet t) - end - local fun liftSubstring (f, s) = let @@ -73,6 +67,39 @@ struct l @ List.tabulate (Nat.- (n, List.length l), fn _ => e) fun padLeftString (e, (n, l)) = StringCvt.padLeft e n l fun padRightString (e, (n, l)) = StringCvt.padRight e n l + fun takeString (n, s) = String.extract (s, 0, SOME n) + fun dropString (n, s) = String.extract (s, n, NONE) + val removeDuplicatesString = String.implode o Set.mk o String.explode val revString = String.implode o List.rev o String.explode + fun stringToChar s = + if String.size s = 1 then String.sub (s, 0) else raise Domain + fun memString (c, s) = String.isSubstring (String.str c) s + + local + fun trans P (s, r) = + String.translate + (fn d => let val x = String.str d in if P x r then "" else x end) s + in + val removeExceptString = + trans (fn x => fn r => not (String.isSubstring x r)) + val removeString = trans String.isSubstring + end + + fun revLookup eq (e, l) = + let + fun loop i = + fn [] => NONE + | h :: t => if eq e h then SOME i else loop (i + 1) t + in + loop 0 l + end + + fun remove (l1, l2) = List.filter (fn x => not (Set.mem (x, l2))) l1 + fun swap (n, l) = (l, n) + fun take (n, l) = List.take (l, n) + fun drop (n, l) = List.drop (l, n) + fun element (n, l) = List.nth (l, n) + fun indexOf x = revLookup equal x + fun indexOfString (c, s) = revLookup equal (c, String.explode s) end (* structure L3 *) diff --git a/examples/l3-machine-code/lib/Set.sig b/examples/l3-machine-code/lib/Set.sig new file mode 100644 index 0000000000..5612362148 --- /dev/null +++ b/examples/l3-machine-code/lib/Set.sig @@ -0,0 +1,15 @@ +(* ------------------------------------------------------------------------- + Set + ------------------------------------------------------------------------- *) + +signature Set = +sig + val diff : ''a list * ''a list -> ''a list + val equal : ''a list * ''a list -> bool + val insert : ''a * ''a list -> ''a list + val intersect : ''a list * ''a list -> ''a list + val isSubset : ''a list * ''a list -> bool + val mem : ''a * ''a list -> bool + val mk : ''a list -> ''a list + val union : ''a list * ''a list -> ''a list +end diff --git a/examples/l3-machine-code/lib/Set.sml b/examples/l3-machine-code/lib/Set.sml new file mode 100644 index 0000000000..8e0aee61d1 --- /dev/null +++ b/examples/l3-machine-code/lib/Set.sml @@ -0,0 +1,26 @@ +(* ------------------------------------------------------------------------- + Set + ------------------------------------------------------------------------- *) + +structure Set :> Set = +struct + + fun mem (i, l) = List.exists (fn x => x = i) l + + fun insert (i, l) = if mem (i, l) then l else i :: l + + fun mk [] = [] + | mk (h :: t) = if mem (h, t) then mk t else h :: mk t + + fun diff (s1, s2) = List.filter (fn x => not (mem (x, s2))) s1 + fun intersect (s1, s2) = List.filter (fn x => mem (x, s2)) s1 + fun isSubset (s1, s2) = List.all (fn x => mem (x, s2)) s1 + + fun equal (s1, s2) = + List.length s1 = List.length s2 andalso intersect (s1, s2) = s1 + + fun union ([], s) = s + | union (s, []) = s + | union (h :: t, s) = union (t, insert (h, s)) + +end (* structure Set *) diff --git a/examples/l3-machine-code/m0/model/m0.sig b/examples/l3-machine-code/m0/model/m0.sig index 455c2b1780..168fac2e3b 100644 --- a/examples/l3-machine-code/m0/model/m0.sig +++ b/examples/l3-machine-code/m0/model/m0.sig @@ -1,4 +1,4 @@ -(* m0 - generated by L<3> - Fri May 16 15:39:31 2014 *) +(* m0 - generated by L<3> - Tue Nov 18 15:29:59 2014 *) signature m0 = sig diff --git a/examples/l3-machine-code/m0/model/m0.sml b/examples/l3-machine-code/m0/model/m0.sml index 4350410ee7..b2d39badd9 100644 --- a/examples/l3-machine-code/m0/model/m0.sml +++ b/examples/l3-machine-code/m0/model/m0.sml @@ -1,4 +1,4 @@ -(* m0 - generated by L<3> - Fri May 16 15:39:31 2014 *) +(* m0 - generated by L<3> - Tue Nov 18 15:29:59 2014 *) structure m0 :> m0 = struct @@ -1848,7 +1848,7 @@ fun DataProcessing (opc,(setflags,(d,(n,(imm32,C))))) = val rn = if (opc = (BitsN.B(0xD,4))) orelse (opc = (BitsN.B(0xF,4))) then BitsN.B(0x0,32) - else if ((L3.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso + else if ((Set.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso (n = (BitsN.B(0xF,4)))) andalso (not setflags) then Align 32 (PC (),4) else R n @@ -3457,8 +3457,8 @@ fun DecodeThumb2 h = BitsN.fromBitstring ([SYSm'7,SYSm'6,SYSm'5,SYSm'4,SYSm'3,SYSm'2,SYSm'1,SYSm'0],8) in - ( if (L3.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (not(L3.mem + ( if (Set.mem(Rn,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (not(Set.mem (SYSm, [BitsN.B(0x0,8),BitsN.B(0x1,8),BitsN.B(0x2,8), BitsN.B(0x3,8),BitsN.B(0x5,8),BitsN.B(0x6,8), @@ -3518,8 +3518,8 @@ fun DecodeThumb2 h = ([SYSm'7,SYSm'6,SYSm'5,SYSm'4,SYSm'3,SYSm'2,SYSm'1,SYSm'0],8) val Rd = BitsN.fromBitstring([Rd'3,Rd'2,Rd'1,Rd'0],4) in - ( if (L3.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse - (not(L3.mem + ( if (Set.mem(Rd,[BitsN.B(0xD,4),BitsN.B(0xF,4)])) orelse + (not(Set.mem (SYSm, [BitsN.B(0x0,8),BitsN.B(0x1,8),BitsN.B(0x2,8), BitsN.B(0x3,8),BitsN.B(0x5,8),BitsN.B(0x6,8), @@ -3628,7 +3628,7 @@ fun EncodeImmShift (shift_t,shift_n) = fun e_branch (c,(ast,e)) = case ast of BranchTarget imm32 => - (if L3.mem(c,[BitsN.B(0xE,4),BitsN.B(0xF,4)]) + (if Set.mem(c,[BitsN.B(0xE,4),BitsN.B(0xF,4)]) then if ((BitsN.<=(BitsN.neg(BitsN.B(0x800,32)),imm32)) andalso (BitsN.<=(imm32,BitsN.B(0x7FE,32)))) andalso (not(e = Enc_Wide)) @@ -3679,7 +3679,7 @@ fun e_data ast = (BitsN.concat [BitsN.B(0x4,5),BitsN.bits(d,2,0),BitsN.bits(imm32,7,0)]) | ArithLogicImmediate(opc,(setflags,(d,(n,imm32)))) => - (if (((L3.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso + (if (((Set.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso (BitsN.<=+(imm32,BitsN.B(0x7,32)))) andalso setflags) andalso (not((BitsN.bit(d,3)) orelse (BitsN.bit(n,3)))) then let @@ -3690,7 +3690,7 @@ fun e_data ast = in Thumb16(BitsN.concat[BitsN.B(0x7,6),S,imm3,Rn,Rd]) end - else if ((((L3.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso + else if ((((Set.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso (d = n)) andalso (BitsN.<=+(imm32,BitsN.B(0xFF,32)))) andalso setflags) andalso (not(BitsN.bit(d,3))) then let @@ -3710,7 +3710,7 @@ fun e_data ast = Thumb16(BitsN.concat[BitsN.B(0x109,10),Rn,Rd]) end else if (((((opc = (BitsN.B(0x4,4))) andalso (not setflags)) andalso - (L3.mem(n,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) andalso + (Set.mem(n,[BitsN.B(0xD,4),BitsN.B(0xF,4)]))) andalso (not setflags)) andalso ((BitsN.&&(imm32,BitsN.B(0xFFFFFC03,32))) = (BitsN.B(0x0,32)))) andalso (not(BitsN.bit(d,3))) @@ -3721,7 +3721,7 @@ fun e_data ast = in Thumb16(BitsN.concat[BitsN.B(0xA,4),S,Rd,imm8]) end - else if (((((L3.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso + else if (((((Set.mem(opc,[BitsN.B(0x4,4),BitsN.B(0x2,4)])) andalso (d = (BitsN.B(0xD,4)))) andalso (n = (BitsN.B(0xD,4)))) andalso (not setflags)) andalso ((BitsN.&&(imm32,BitsN.B(0xFFFFFE03,32))) = (BitsN.B(0x0,32)))) andalso @@ -3734,7 +3734,7 @@ fun e_data ast = end else BadCode("ArithLogicImmediate")) | Register(opc,(setflags,(d,(n,m)))) => - (if ((L3.mem(opc,[BitsN.B(0x2,4),BitsN.B(0x4,4)])) andalso setflags) andalso + (if ((Set.mem(opc,[BitsN.B(0x2,4),BitsN.B(0x4,4)])) andalso setflags) andalso (not(((BitsN.bit(d,3)) orelse (BitsN.bit(n,3))) orelse (BitsN.bit(m,3)))) then let @@ -3745,7 +3745,7 @@ fun e_data ast = in Thumb16(BitsN.concat[BitsN.B(0x6,6),S,Rm,Rn,Rd]) end - else if (((L3.mem + else if (((Set.mem (opc, [BitsN.B(0x0,4),BitsN.B(0x1,4),BitsN.B(0x5,4), BitsN.B(0x6,4),BitsN.B(0xC,4),BitsN.B(0xE,4)])) andalso @@ -3799,7 +3799,7 @@ fun e_data ast = in Thumb16(BitsN.concat[BitsN.B(0x10F,10),Rm,Rd]) end - else if ((L3.mem(shift_t,[SRType_LSL,SRType_LSR,SRType_ASR])) andalso + else if ((Set.mem(shift_t,[SRType_LSL,SRType_LSR,SRType_ASR])) andalso setflags) andalso (not((negate orelse (BitsN.bit(m,3))) orelse (BitsN.bit(d,3)))) then let @@ -4191,7 +4191,7 @@ fun p_label s = let val (l,r) = L3.splitl - (fn c => (Char.isAlphaNum c) orelse (L3.mem(c,[#"_",#"."])),t) + (fn c => (Char.isAlphaNum c) orelse (Set.mem(c,[#"_",#"."])),t) in if ((r = ("")) andalso (not(l = ("")))) andalso (not(Char.isDigit(L3.strHd l))) @@ -4225,7 +4225,7 @@ fun p_cond s = fun p_suffix s = case L3.uncurry String.fields (fn c => c = #".",s) of [cond,s] => - (case (p_cond cond,L3.mem(s,["w","n"])) of + (case (p_cond cond,Set.mem(s,["w","n"])) of (Option.SOME c,true) => Option.SOME(c,s) | _ => NONE) | [cond] => @@ -4304,7 +4304,7 @@ fun p_shift_amount (typ,(h,s)) = then case p_unbounded_immediate s of Option.SOME n => (if (Nat.<(n,32)) orelse - ((n = 32) andalso (L3.mem(typ,[SRType_LSR,SRType_ASR]))) + ((n = 32) andalso (Set.mem(typ,[SRType_LSR,SRType_ASR]))) then ("",(typ,NAT n)) else ("shift amount too large",(SRType_LSL,NAT 0))) | NONE => @@ -4413,7 +4413,7 @@ fun p_shift_full (c,(typ,l)) = Option.SOME n => (if (Nat.<(n,32)) orelse ((n = 32) andalso - (L3.mem(typ,[SRType_LSR,SRType_ASR]))) + (Set.mem(typ,[SRType_LSR,SRType_ASR]))) then OK(c, Data (ShiftImmediate @@ -4762,7 +4762,7 @@ fun p_ldm_stm (c,(load,l)) = let val (r,wb) = L3.splitr(fn c => c = #"!",stripSpaces h) in - case (p_register r,(p_registers t,L3.mem(wb,["","!"]))) of + case (p_register r,(p_registers t,Set.mem(wb,["","!"]))) of (Option.SOME rn,(Option.SOME w,true)) => (if (BitsN.bits(w,15,8)) = (BitsN.B(0x0,8)) then let diff --git a/examples/l3-machine-code/mips/model/mips.sig b/examples/l3-machine-code/mips/model/mips.sig index 83cffc737c..08a09f3d89 100644 --- a/examples/l3-machine-code/mips/model/mips.sig +++ b/examples/l3-machine-code/mips/model/mips.sig @@ -1,4 +1,4 @@ -(* mips - generated by L<3> - Wed Oct 29 16:00:41 2014 *) +(* mips - generated by L<3> - Tue Nov 18 15:34:51 2014 *) signature mips = sig diff --git a/examples/l3-machine-code/mips/model/mips.sml b/examples/l3-machine-code/mips/model/mips.sml index 2f641f8a45..83ac8046b2 100644 --- a/examples/l3-machine-code/mips/model/mips.sml +++ b/examples/l3-machine-code/mips/model/mips.sml @@ -1,4 +1,4 @@ -(* mips - generated by L<3> - Wed Oct 29 16:00:41 2014 *) +(* mips - generated by L<3> - Tue Nov 18 15:34:51 2014 *) structure mips :> mips = struct @@ -2885,12 +2885,12 @@ fun SignalException ExceptionType = else BitsN.B(0xFFFFFFFF80000000,64) in ( BranchDelay := NONE - ; BranchTo := - (Option.SOME - (true, - BitsN.@@ + ; PC := + (BitsN.- + (BitsN.@@ (BitsN.bits(vectorBase,63,30), - BitsN.+(BitsN.bits(vectorBase,29,0),vectorOffset)))) + BitsN.+(BitsN.bits(vectorBase,29,0),vectorOffset)), + BitsN.B(0x4,64))) ; exceptionSignalled := true ) end @@ -4543,11 +4543,11 @@ fun dfn'BREAK () = SignalException Bp; fun dfn'SYSCALL () = SignalException Sys; fun dfn'ERET () = - if ((#CU0)((#Status) (!CP0))) orelse (KernelMode ()) + if Option.isSome (!BranchDelay) + then raise UNPREDICTABLE ("ERET follows branch") + else if ((#CU0)((#Status) (!CP0))) orelse (KernelMode ()) then ( if (#ERL)((#Status) (!CP0)) - then ( BranchTo := - (Option.SOME - (true,BitsN.-((#ErrorEPC) (!CP0),BitsN.B(0x4,64)))) + then ( PC := (BitsN.-((#ErrorEPC) (!CP0),BitsN.B(0x4,64))) ; let val x0 = (#Status) (!CP0) in @@ -4556,9 +4556,7 @@ fun dfn'ERET () = ((!CP0),StatusRegister_ERL_rupd(x0,false))) end ) - else ( BranchTo := - (Option.SOME - (true,BitsN.-((#EPC) (!CP0),BitsN.B(0x4,64)))) + else ( PC := (BitsN.-((#EPC) (!CP0),BitsN.B(0x4,64))) ; let val x0 = (#Status) (!CP0) in diff --git a/examples/l3-machine-code/x64/model/x64.sig b/examples/l3-machine-code/x64/model/x64.sig index 6ff4efedc7..e241d45e14 100644 --- a/examples/l3-machine-code/x64/model/x64.sig +++ b/examples/l3-machine-code/x64/model/x64.sig @@ -1,4 +1,4 @@ -(* x64 - generated by L<3> - Fri Aug 29 10:14:41 2014 *) +(* x64 - generated by L<3> - Tue Nov 18 15:39:44 2014 *) signature x64 = sig diff --git a/examples/l3-machine-code/x64/model/x64.sml b/examples/l3-machine-code/x64/model/x64.sml index a0d72af02f..f34a318271 100644 --- a/examples/l3-machine-code/x64/model/x64.sml +++ b/examples/l3-machine-code/x64/model/x64.sml @@ -1,4 +1,4 @@ -(* x64 - generated by L<3> - Fri Aug 29 10:14:41 2014 *) +(* x64 - generated by L<3> - Tue Nov 18 15:39:44 2014 *) structure x64 :> x64 = struct @@ -562,7 +562,7 @@ fun EA ea = Zea_i i => restrictSize i | Zea_r(Z8 have_rex,r) => BitsN.&& - (if have_rex orelse (not(L3.mem(r,[RSP,RBP,RSI,RDI]))) + (if have_rex orelse (not(Set.mem(r,[RSP,RBP,RSI,RDI]))) then Map.lookup((!REG),Cast.ZregToNat r) else BitsN.>>+ (Map.lookup @@ -580,7 +580,7 @@ fun write'EA (w,ea) = case ea of Zea_i i => raise FAILURE ("write to constant") | Zea_r(Z8 have_rex,r) => - (if have_rex orelse (not(L3.mem(r,[RSP,RBP,RSI,RDI]))) + (if have_rex orelse (not(Set.mem(r,[RSP,RBP,RSI,RDI]))) then let val w0 = Map.lookup((!REG),Cast.ZregToNat r) in @@ -1339,9 +1339,9 @@ fun readPrefix (s,(p,strm)) = then Option.SOME(p,(false,(rec'REX(BitsN.B(0x0,4)),strm))) else if group = 5 then Option.SOME(p,(true,(rec'REX(BitsN.bits(h,3,0)),strm1))) - else if L3.mem(group,s) + else if Set.mem(group,s) then NONE - else readPrefix((op ::) (group,s),(h :: p,strm1)) + else readPrefix(Set.insert(group,s),(h :: p,strm1)) end | [] => Option.SOME @@ -1361,12 +1361,12 @@ fun x64_decode strm = NONE => Zdec_fail("Bad prefix") | Option.SOME(p,(have_rex,(REX,strm1))) => let - val prefixes = L3.mkSet p - val op_size_override = L3.mem(BitsN.B(0x66,8),prefixes) + val prefixes = Set.mk p + val op_size_override = Set.mem(BitsN.B(0x66,8),prefixes) in if ((#W) REX) andalso op_size_override then Zdec_fail("REX.W together with override prefix") - else if L3.mem(BitsN.B(0x67,8),prefixes) + else if Set.mem(BitsN.B(0x67,8),prefixes) then Zdec_fail("address override prefix not supported") else case strm1 of v'0 :: v'1 => @@ -2079,7 +2079,7 @@ fun e_ModRM (r,rm) = then (0,[]) else e_imm_8_32 imm in - if L3.mem(s,[0,1,4]) + if Set.mem(s,[0,1,4]) then (BitsN.concat [BitsN.B(0x0,1),BitsN.bits(r,3,3),BitsN.bits(i,3,3), BitsN.bits(b,3,3)], @@ -2103,7 +2103,7 @@ fun e_ModRM (r,rm) = then (0,[]) else e_imm_8_32 imm in - if L3.mem(s,[0,1,4]) + if Set.mem(s,[0,1,4]) then (BitsN.concat [BitsN.B(0x0,1),BitsN.bits(r,3,3),BitsN.B(0x0,1), BitsN.bits(base,3,3)], @@ -2584,7 +2584,7 @@ fun p_label s = let val (l,r) = L3.splitl - (fn c => (Char.isAlphaNum c) orelse (L3.mem(c,[#"_",#"."])),t) + (fn c => (Char.isAlphaNum c) orelse (Set.mem(c,[#"_",#"."])),t) in if ((r = ("")) andalso (not(l = ("")))) andalso (not(Char.isDigit(L3.strHd l))) @@ -2698,7 +2698,7 @@ fun p_disp (b,s) = fun p_rip_disp s = let val (l,r) = - L3.splitl(fn c => not(L3.mem(c,[#"+",#"-"])),stripLeftSpaces s) + L3.splitl(fn c => not(Set.mem(c,[#"+",#"-"])),stripLeftSpaces s) in if l = ("") then if r = ("") @@ -2731,7 +2731,8 @@ fun p_parts (m,s) = | (#"-" :: t,(si,(b,disp))) => let val (l,r) = - L3.splitl(fn c => not(L3.mem(c,[#"+",#"-"])),String.implode t) + L3.splitl + (fn c => not(Set.mem(c,[#"+",#"-"])),String.implode t) in case (p_imm32(("-") ^ l),disp) of (NONE,_) => (NONE,(NONE,NONE)) @@ -2742,7 +2743,8 @@ fun p_parts (m,s) = | (#"+" :: t,(si,(b,disp))) => let val (l,r) = - L3.splitl(fn c => not(L3.mem(c,[#"+",#"-"])),String.implode t) + L3.splitl + (fn c => not(Set.mem(c,[#"+",#"-"])),String.implode t) in case (p_imm32 l,disp) of (NONE,_) => @@ -2781,7 +2783,8 @@ fun p_parts (m,s) = | (t,(si,(b,disp))) => let val (l,r) = - L3.splitl(fn c => not(L3.mem(c,[#"+",#"-"])),String.implode t) + L3.splitl + (fn c => not(Set.mem(c,[#"+",#"-"])),String.implode t) in case (p_imm32 l,disp) of (NONE,_) => @@ -3167,7 +3170,7 @@ fun instructionFromString s = in case p_cond(String.implode cond) of Option.SOME c => - (if L3.mem(c,[Z_ALWAYS,Z_E,Z_NE]) + (if Set.mem(c,[Z_ALWAYS,Z_E,Z_NE]) then case p_imm8 i of Option.SOME imm => OK(Zloop(c,BitsN.-(imm,BitsN.B(0x2,64)))) From 37c691515f7aa91f8dfa4c6b817656d3de359e8e Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Wed, 19 Nov 2014 15:09:33 +0000 Subject: [PATCH 030/718] The MIPS tools were experiencing problems with NOP instructions. Reported by Brian Campbell. --- examples/l3-machine-code/mips/step/Holmakefile | 2 +- examples/l3-machine-code/mips/step/mips_stepLib.sml | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/examples/l3-machine-code/mips/step/Holmakefile b/examples/l3-machine-code/mips/step/Holmakefile index b85938bbc0..549bde284a 100644 --- a/examples/l3-machine-code/mips/step/Holmakefile +++ b/examples/l3-machine-code/mips/step/Holmakefile @@ -5,7 +5,7 @@ ifdef POLY HOLHEAP = mips-heap EXTRA_CLEANS = $(HOLHEAP) $(HOLHEAP).o -BARE_THYS = ../model/mipsLib ../../Lib/MutableMap ../model/mips +BARE_THYS = ../model/mipsLib ../../lib/MutableMap ../model/mips DEPS = $(patsubst %,%.uo,$(BARE_THYS)) THYFILES = $(patsubst %Script.sml,%Theory.uo,$(wildcard *.sml)) diff --git a/examples/l3-machine-code/mips/step/mips_stepLib.sml b/examples/l3-machine-code/mips/step/mips_stepLib.sml index 619de90f6c..b0713f8515 100644 --- a/examples/l3-machine-code/mips/step/mips_stepLib.sml +++ b/examples/l3-machine-code/mips/step/mips_stepLib.sml @@ -900,7 +900,12 @@ local (REWRITE_CONV [ASSUME ``^st.BranchDelay = SOME d``, optionTheory.NOT_SOME_NONE]) val NO_BRANCH_DELAY_RULE = - PURE_REWRITE_RULE [boolTheory.COND_ID, ASSUME ``^st.BranchDelay = NONE``] + CONV_RULE + (Lib.funpow 4 RAND_CONV + (LAND_CONV + (RAND_CONV + (PURE_REWRITE_CONV + [boolTheory.COND_ID, ASSUME ``^st.BranchDelay = NONE``])))) val state_rule = Conv.RIGHT_CONV_RULE (Conv.RAND_CONV STATE_CONV) val exc_rule = SIMP_RULE bool_ss [] o COND_UPDATE_RULE o state_rule val MP_Next = state_rule o Drule.MATCH_MP NextStateMIPS_nodelay o From dcc2c549beb22b2aa615f1ebee21b04c0fe80056 Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Mon, 24 Nov 2014 11:21:48 +0000 Subject: [PATCH 031/718] Some fixes for the L3 ARM model. A number of bugs were detected when validating the L3 model against the tests used to check the old (monadic) ARM model. These can be found here: http://www.cl.cam.ac.uk/~mom22/arm-tests/ The bugs were as follows: 1. Off by one error in definition of SignExtendFrom. 2. Off by one error in definition of SignedSatQ. 3. Error in setting Q flag for QDADD. 4. Error in setting the GE flags for USAX and USUB16. 5. Error in the top-halfword result for SXTB16, UXTB16, SXTAB16 and UXTAB16. 6. Error in handling the C flag for some data-processing instructions (looks to affect immediate value variants only). 7. Incorrectly identifying some STRD instructions as unpredictable. Note that 1-5 relate to instructions that are not supported by the decompiler, and 7 just prevented some valid code from being decompiled. As such, 6 is the most significant error fixed here. The model now passes all of the tests. --- examples/l3-machine-code/arm/model/arm.sig | 4 +- examples/l3-machine-code/arm/model/arm.sml | 59 +-- .../l3-machine-code/arm/model/armScript.sml | 361 +++++++++--------- .../l3-machine-code/arm/step/arm_stepLib.sml | 13 +- 4 files changed, 230 insertions(+), 207 deletions(-) diff --git a/examples/l3-machine-code/arm/model/arm.sig b/examples/l3-machine-code/arm/model/arm.sig index ad1a91f342..e6360dada0 100644 --- a/examples/l3-machine-code/arm/model/arm.sig +++ b/examples/l3-machine-code/arm/model/arm.sig @@ -1,4 +1,4 @@ -(* arm - generated by L<3> - Tue Nov 18 15:31:11 2014 *) +(* arm - generated by L<3> - Fri Nov 21 16:33:11 2014 *) signature arm = sig @@ -805,7 +805,7 @@ val DataProcessing: (BitsN.nbit * (bool * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * bool))))) -> unit val DataProcessingPC: - (BitsN.nbit * (bool * (BitsN.nbit * (BitsN.nbit * bool)))) -> unit + (BitsN.nbit * (bool * (BitsN.nbit * BitsN.nbit))) -> unit val dfn'Move: (bool * (bool * (BitsN.nbit * BitsN.nbit))) -> unit val dfn'TestCompareImmediate: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit diff --git a/examples/l3-machine-code/arm/model/arm.sml b/examples/l3-machine-code/arm/model/arm.sml index d79169e2c3..4fd59903de 100644 --- a/examples/l3-machine-code/arm/model/arm.sml +++ b/examples/l3-machine-code/arm/model/arm.sml @@ -1,4 +1,4 @@ -(* arm - generated by L<3> - Tue Nov 18 15:31:11 2014 *) +(* arm - generated by L<3> - Fri Nov 21 16:33:11 2014 *) structure arm :> arm = struct @@ -3272,7 +3272,7 @@ fun BitCount N w = fun SignExtendFrom N (w,p) = let - val s = Nat.-(BitsN.size(BitsN.B(0x0,N)),p) + val s = Nat.-(Nat.-(BitsN.size(BitsN.B(0x0,N)),1),p) in BitsN.>>(BitsN.<<(w,s),s) end; @@ -3287,12 +3287,12 @@ fun SignedSatQ M (i,N) = then raise ASSERT ("SignedSatQ: M < N") else () ; let - val max = Nat.toInt(Nat.-(Nat.pow(2,Nat.-(N,1)),1)) + val max = Nat.toInt(Nat.pow(2,Nat.-(N,1))) in - if Int.>(i,max) - then (BitsN.fromInt(max,M),true) + if Int.>(i,Int.-(max,1)) + then (BitsN.fromInt(Int.-(max,1),M),true) else if Int.<(i,Int.~ max) - then (BitsN.neg(BitsN.fromInt(max,M)),true) + then (BitsN.fromInt(Int.~ max,M),true) else (BitsN.fromInt(i,M),false) end ); @@ -4253,7 +4253,8 @@ fun DataProcessing (opc,(setflags,(d,(n,(imm32,C))))) = (n = (BitsN.B(0xF,4)))) andalso (not setflags) then Align 32 (PC (),4) else R n - val (result,(carry,overflow)) = DataProcessingALU(opc,(rn,(imm32,C))) + val (result,(carry,overflow)) = + DataProcessingALU(opc,(rn,(imm32,(#C) (!CPSR)))) in ( if not((BitsN.bits(opc,3,2)) = (BitsN.B(0x2,2))) then write'R(result,d) @@ -4261,17 +4262,18 @@ fun DataProcessing (opc,(setflags,(d,(n,(imm32,C))))) = ; if setflags then ( CPSR := (PSR_N_rupd((!CPSR),BitsN.bit(result,31))) ; CPSR := (PSR_Z_rupd((!CPSR),result = (BitsN.B(0x0,32)))) - ; CPSR := (PSR_C_rupd((!CPSR),carry)) ; if ArithmeticOpcode opc - then CPSR := (PSR_V_rupd((!CPSR),overflow)) - else () + then ( CPSR := (PSR_C_rupd((!CPSR),carry)) + ; CPSR := (PSR_V_rupd((!CPSR),overflow)) + ) + else CPSR := (PSR_C_rupd((!CPSR),C)) ) else () ; IncPC () ) end; -fun DataProcessingPC (opc,(setflags,(n,(imm32,C)))) = +fun DataProcessingPC (opc,(setflags,(n,imm32))) = let val rn = if (opc = (BitsN.B(0xD,4))) orelse @@ -4281,7 +4283,7 @@ fun DataProcessingPC (opc,(setflags,(n,(imm32,C)))) = (n = (BitsN.B(0xF,4)))) andalso (not setflags) then Align 32 (PC (),4) else R n - val (result,(carry,overflow)) = DataProcessingALU(opc,(rn,(imm32,C))) + val (result,_) = DataProcessingALU(opc,(rn,(imm32,(#C) (!CPSR)))) in if setflags then if CurrentModeIsHyp () @@ -4304,7 +4306,7 @@ fun dfn'Move (setflags,(negate,(d,imm12))) = val (imm32,carry) = ExpandImm_C(imm12,(#C) (!CPSR)) in if d = (BitsN.B(0xF,4)) - then DataProcessingPC(opc,(setflags,(BitsN.B(0xF,4),(imm32,carry)))) + then DataProcessingPC(opc,(setflags,(BitsN.B(0xF,4),imm32))) else DataProcessing(opc,(setflags,(d,(BitsN.B(0xF,4),(imm32,carry))))) end; @@ -4322,7 +4324,7 @@ fun dfn'ArithLogicImmediate (opc,(setflags,(d,(n,imm12)))) = val (imm32,carry) = ExpandImm_C(imm12,(#C) (!CPSR)) in if d = (BitsN.B(0xF,4)) - then DataProcessingPC(opc,(setflags,(n,(imm32,carry)))) + then DataProcessingPC(opc,(setflags,(n,imm32))) else DataProcessing(opc,(setflags,(d,(n,(imm32,carry))))) end; @@ -4330,10 +4332,9 @@ fun doRegister (opc,(setflags,(d,(n,(m,(shift_t,shift_n)))))) = let val (shifted,carry) = Shift_C 32 (R m,(shift_t,(shift_n,(#C) (!CPSR)))) - val carry = if ArithmeticOpcode opc then (#C) (!CPSR) else carry in if d = (BitsN.B(0xF,4)) - then DataProcessingPC(opc,(setflags,(n,(shifted,carry)))) + then DataProcessingPC(opc,(setflags,(n,shifted))) else DataProcessing(opc,(setflags,(d,(n,(shifted,carry))))) end; @@ -4359,7 +4360,6 @@ fun doRegisterShiftedRegister (opc,(setflags,(d,(n,(m,(shift_t,s)))))) = val (shifted,carry) = Shift_C 32 (R m,(shift_t,(BitsN.toNat(BitsN.bits(R s,7,0)),(#C) (!CPSR)))) - val carry = if ArithmeticOpcode opc then (#C) (!CPSR) else carry in DataProcessing(opc,(setflags,(d,(n,(shifted,carry))))) end; @@ -4414,7 +4414,7 @@ fun dfn'SaturatingAddSubtract (opc,(d,(m,n))) = SignedSatQ 32 (Int.+(BitsN.toInt(R m),BitsN.toInt doubled),32) in - ( result := r; sat := sat1 ) + ( result := r; sat := (sat1 orelse sat2) ) end | BitsN.B(0x3,2) => let @@ -4921,7 +4921,7 @@ fun dfn'UnsignedAddSub16 (op',(d,(n,m))) = (w, if Int.>= (res1, - if Set.mem(op',[BitsN.B(0x1,2),BitsN.B(0x2,2)]) + if Set.mem(op',[BitsN.B(0x1,2),BitsN.B(0x3,2)]) then 0 else 65536) then BitsN.B(0x3,2) @@ -5186,7 +5186,7 @@ fun dfn'ExtendByte16 (unsigned,(d,(n,(m,rotation)))) = (BitsN.bits(acc,31,16), Extend (8,16) (unsigned,BitsN.bits(rotated,23,16))) in - ( write'R(BitsN.@@(r1,r1),d); IncPC () ) + ( write'R(BitsN.@@(r2,r1),d); IncPC () ) end; fun dfn'ExtendHalfword (unsigned,(d,(n,(m,rotation)))) = @@ -9861,13 +9861,17 @@ fun DecodeARM w = val wback = (P = (BitsN.B(0x0,1))) orelse (W = (BitsN.B(0x1,1))) + val store = + (BitsN.fromBitstring([S'0],1)) = + (BitsN.B(0x1,1)) in - ( if (((((((BitsN.bit(Rt,0)) orelse - ((P = (BitsN.B(0x0,1))) andalso - (W = (BitsN.B(0x1,1))))) orelse - (Rt2 = (BitsN.B(0xF,4)))) orelse - (Rm = (BitsN.B(0xF,4)))) orelse (Rm = Rt)) orelse - (Rm = Rt2)) orelse + ( if ((((((BitsN.bit(Rt,0)) orelse + ((P = (BitsN.B(0x0,1))) andalso + (W = (BitsN.B(0x1,1))))) orelse + (Rt2 = (BitsN.B(0xF,4)))) orelse + (Rm = (BitsN.B(0xF,4)))) orelse + ((not store) andalso + ((Rm = Rt) orelse (Rm = Rt2)))) orelse (wback andalso (((Rn = (BitsN.B(0xF,4))) orelse (Rn = Rt)) orelse (Rn = Rt2)))) orelse @@ -9883,8 +9887,7 @@ fun DecodeARM w = (BitsN.B(0x1,1)) val m = register_form2 Rm in - if (BitsN.fromBitstring([S'0],1)) = - (BitsN.B(0x1,1)) + if store then Store (StoreDual (add, diff --git a/examples/l3-machine-code/arm/model/armScript.sml b/examples/l3-machine-code/arm/model/armScript.sml index 03b5c6b282..0467df2f4d 100644 --- a/examples/l3-machine-code/arm/model/armScript.sml +++ b/examples/l3-machine-code/arm/model/armScript.sml @@ -1,4 +1,4 @@ -(* armScript.sml - generated by L<3> - Thu Oct 23 14:23:23 2014 *) +(* armScript.sml - generated by L<3> - Fri Nov 21 15:10:03 2014 *) open HolKernel boolLib bossLib Import val () = Import.start "arm" @@ -3476,7 +3476,7 @@ val BitCount_def = Def ; val SignExtendFrom_def = Def ("SignExtendFrom",TP[Var("w",BTy"N"),nVar"p"], - Let(nVar"s",Bop(Sub,Mop(Size,LY(0,"N")),nVar"p"), + Let(nVar"s",Bop(Sub,Bop(Sub,Mop(Size,LY(0,"N")),LN 1),nVar"p"), Bop(Asr,Bop(Lsl,Var("w",BTy"N"),nVar"s"),nVar"s"))) ; val Extend_def = Def @@ -3491,13 +3491,11 @@ val SignedSatQ_def = Def ("SignedSatQ",TP[iVar"i",nVar"N"], Close (qVar"state", - TP[Let(iVar"max", - Mop(Cast iTy, - Bop(Sub,Bop(Exp,LN 2,Bop(Sub,nVar"N",LN 1)),LN 1)), - ITB([(Bop(Gt,iVar"i",iVar"max"), - TP[Mop(Cast(BTy"M"),iVar"max"),LT]), + TP[Let(iVar"max",Mop(Cast iTy,Bop(Exp,LN 2,Bop(Sub,nVar"N",LN 1))), + ITB([(Bop(Gt,iVar"i",Bop(Sub,iVar"max",LI 1)), + TP[Mop(Cast(BTy"M"),Bop(Sub,iVar"max",LI 1)),LT]), (Bop(Lt,iVar"i",Mop(Neg,iVar"max")), - TP[Mop(Neg,Mop(Cast(BTy"M"),iVar"max")),LT])], + TP[Mop(Cast(BTy"M"),Mop(Neg,iVar"max")),LT])], TP[Mop(Cast(BTy"M"),iVar"i"),LF])), ITE(Bop(Lt,Mop(Size,LY(0,"M")),nVar"N"), Mop(Snd, @@ -8151,7 +8149,8 @@ val DataProcessing_def = Def Let(TP[Var("result",F32),bVar"carry",bVar"overflow"], Call ("DataProcessingALU",PTy(F32,PTy(bTy,bTy)), - TP[Var("opc",F4),Var("v",F32),Var("imm32",F32),bVar"C"]), + TP[Var("opc",F4),Var("v",F32),Var("imm32",F32), + Dest("C",bTy,Dest("CPSR",CTy"PSR",qVar"s"))]), Let(qVar"s", ITE(Mop(Not, EQ(EX(Var("opc",F4),LN 3,LN 2,FTy 2),LW(2,2))), @@ -8180,18 +8179,19 @@ val DataProcessing_def = Def ("Z", TP[Dest("CPSR",CTy"PSR",qVar"s"), EQ(Var("result",F32),LW(0,32))])]), - Let(qVar"s", - Rupd - ("CPSR", - TP[qVar"s", - Rupd - ("C", - TP[Dest - ("CPSR",CTy"PSR", - qVar"s"),bVar"carry"])]), - ITE(Call - ("ArithmeticOpcode",bTy, - Var("opc",F4)), + ITE(Call + ("ArithmeticOpcode",bTy, + Var("opc",F4)), + Let(qVar"s", + Rupd + ("CPSR", + TP[qVar"s", + Rupd + ("C", + TP[Dest + ("CPSR",CTy"PSR", + qVar"s"), + bVar"carry"])]), Rupd ("CPSR", TP[qVar"s", @@ -8200,12 +8200,20 @@ val DataProcessing_def = Def TP[Dest ("CPSR",CTy"PSR", qVar"s"), - bVar"overflow"])]), - qVar"s")))),qVar"s"))))))) + bVar"overflow"])])), + Rupd + ("CPSR", + TP[qVar"s", + Rupd + ("C", + TP[Dest + ("CPSR",CTy"PSR", + qVar"s"),bVar"C"])])))), + qVar"s"))))))) ; val DataProcessingPC_def = Def ("DataProcessingPC", - TP[Var("opc",F4),bVar"setflags",Var("n",F4),Var("imm32",F32),bVar"C"], + TP[Var("opc",F4),bVar"setflags",Var("n",F4),Var("imm32",F32)], Close (qVar"state", Let(TP[Var("v",F32),qVar"s"], @@ -8221,10 +8229,11 @@ val DataProcessingPC_def = Def TP[Call("Align",F32,TP[Var("v",F32),LN 4]),qVar"s"]))], Apply (Call("R",ATy(qTy,PTy(F32,qTy)),Var("n",F4)),qVar"state")), - Let(TP[Var("result",F32),bVar"carry",bVar"overflow"], + Let(TP[Var("result",F32),AVar bTy,AVar bTy], Call ("DataProcessingALU",PTy(F32,PTy(bTy,bTy)), - TP[Var("opc",F4),Var("v",F32),Var("imm32",F32),bVar"C"]), + TP[Var("opc",F4),Var("v",F32),Var("imm32",F32), + Dest("C",bTy,Dest("CPSR",CTy"PSR",qVar"s"))]), ITE(bVar"setflags", Let(TP[bVar"v",qVar"s"], Apply @@ -8323,7 +8332,7 @@ val dfn'Move_def = Def (Call ("DataProcessingPC",ATy(qTy,PTy(uTy,qTy)), TP[Var("opc",F4),bVar"setflags",LW(15,4), - Var("imm32",F32),bVar"carry"]),qVar"s"), + Var("imm32",F32)]),qVar"s"), Apply (Call ("DataProcessing",ATy(qTy,PTy(uTy,qTy)), @@ -8369,7 +8378,7 @@ val dfn'ArithLogicImmediate_def = Def (Call ("DataProcessingPC",ATy(qTy,PTy(uTy,qTy)), TP[Var("opc",F4),bVar"setflags",Var("n",F4), - Var("imm32",F32),bVar"carry"]),qVar"s"), + Var("imm32",F32)]),qVar"s"), Apply (Call ("DataProcessing",ATy(qTy,PTy(uTy,qTy)), @@ -8395,23 +8404,18 @@ val doRegister_def = Def qVar"s"), Let(TP[Var("shifted",F32),bVar"carry"], Var("v",PTy(F32,bTy)), - Let(bVar"v", - ITE(Call("ArithmeticOpcode",bTy,Var("opc",F4)), - Dest("C",bTy,Dest("CPSR",CTy"PSR",qVar"s")), - bVar"carry"), - ITE(EQ(Var("d",F4),LW(15,4)), - Apply - (Call - ("DataProcessingPC",ATy(qTy,PTy(uTy,qTy)), - TP[Var("opc",F4),bVar"setflags", - Var("n",F4),Var("shifted",F32),bVar"v"]), - qVar"s"), - Apply - (Call - ("DataProcessing",ATy(qTy,PTy(uTy,qTy)), - TP[Var("opc",F4),bVar"setflags", - Var("d",F4),Var("n",F4), - Var("shifted",F32),bVar"v"]),qVar"s")))))))) + ITE(EQ(Var("d",F4),LW(15,4)), + Apply + (Call + ("DataProcessingPC",ATy(qTy,PTy(uTy,qTy)), + TP[Var("opc",F4),bVar"setflags",Var("n",F4), + Var("shifted",F32)]),qVar"s"), + Apply + (Call + ("DataProcessing",ATy(qTy,PTy(uTy,qTy)), + TP[Var("opc",F4),bVar"setflags",Var("d",F4), + Var("n",F4),Var("shifted",F32),bVar"carry"]), + qVar"s"))))))) ; val dfn'Register_def = Def ("dfn'Register", @@ -8488,10 +8492,8 @@ val doRegisterShiftedRegister_def = Def (Call ("DataProcessing",ATy(qTy,PTy(uTy,qTy)), TP[Var("opc",F4),bVar"setflags",Var("d",F4), - Var("n",F4),Var("shifted",F32), - ITE(Call("ArithmeticOpcode",bTy,Var("opc",F4)), - Dest("C",bTy,Dest("CPSR",CTy"PSR",qVar"s")), - bVar"carry")]),qVar"s")))))) + Var("n",F4),Var("shifted",F32),bVar"carry"]), + qVar"s")))))) ; val dfn'RegisterShiftedRegister_def = Def ("dfn'RegisterShiftedRegister", @@ -8801,7 +8803,8 @@ val dfn'SaturatingAddSubtract_def = Def Var("s3",PTy(F32,qTy))]), Let(TP[Var("r",F32),bVar"sat2"], Var("v",PTy(F32,bTy)), - TP[bVar"sat1",Var("r",F32), + TP[Bop(Or,bVar"sat1",bVar"sat2"), + Var("r",F32), Mop(Snd, Mop(Snd, Var("s", @@ -10238,7 +10241,7 @@ val dfn'UnsignedAddSub16_def = Def BFI(LN 1,LN 0, ITE(Bop(Ge,iVar"res1", ITE(Bop(In,Var("op",FTy 2), - SL[LW(1,2),LW(2,2)]), + SL[LW(1,2),LW(3,2)]), LI 0,LI 65536)),LW(3,2), LW(0,2)), Dest @@ -10902,20 +10905,27 @@ val dfn'ExtendByte16_def = Def (Call ("ROR",ATy(qTy,PTy(F32,qTy)), TP[Var("v0",F32),nVar"rotation"]),qVar"s"), - Let(Var("r1",F16), - Bop(Add,EX(Var("v",F32),LN 15,LN 0,F16), - Call - ("Extend",F16, - TP[bVar"unsigned", - EX(Var("v0",F32),LN 7,LN 0,F8)])), - Apply - (Call("IncPC",ATy(qTy,PTy(uTy,qTy)),LU), - Mop(Snd, - Apply - (Call - ("write'R",ATy(qTy,PTy(uTy,qTy)), - TP[CC[Var("r1",F16),Var("r1",F16)], - Var("d",F4)]),qVar"s"))))))))) + Apply + (Call("IncPC",ATy(qTy,PTy(uTy,qTy)),LU), + Mop(Snd, + Apply + (Call + ("write'R",ATy(qTy,PTy(uTy,qTy)), + TP[CC[Bop(Add, + EX(Var("v",F32),LN 31,LN 16,F16), + Call + ("Extend",F16, + TP[bVar"unsigned", + EX(Var("v0",F32),LN 23, + LN 16,F8)])), + Bop(Add, + EX(Var("v",F32),LN 15,LN 0,F16), + Call + ("Extend",F16, + TP[bVar"unsigned", + EX(Var("v0",F32),LN 7,LN 0, + F8)]))],Var("d",F4)]), + qVar"s")))))))) ; val dfn'ExtendHalfword_def = Def ("dfn'ExtendHalfword", @@ -26485,65 +26495,66 @@ val DecodeARM_def = Def F1), LW(1, 1))), - TP[Let(bVar"index", - EQ(Var("P", - F1), - LW(1, - 1)), - Let(bVar"add", - EQ(Mop(Cast - F1, - LL[bVar"b'23"]), + Let(bVar"store", + EQ(Mop(Cast + F1, + LL[bVar"b'5"]), + LW(1, + 1)), + TP[Let(bVar"index", + EQ(Var("P", + F1), LW(1, 1)), - Let(Var("m", - CTy"offset2"), - Call - ("register_form2", - CTy"offset2", - Var("Rm", - F4)), - ITE(EQ(Mop(Cast - F1, - LL[bVar"b'5"]), - LW(1, - 1)), - Call - ("Store", - CTy"instruction", - Call - ("StoreDual", - CTy"Store", - TP[bVar"add", - bVar"index", - bVar"wback", - Var("Rt", - F4), - Var("Rt2", - F4), - Var("Rn", - F4), - Var("m", - CTy"offset2")])), + Let(bVar"add", + EQ(Mop(Cast + F1, + LL[bVar"b'23"]), + LW(1, + 1)), + Let(Var("m", + CTy"offset2"), Call - ("Load", - CTy"instruction", - Call - ("LoadDual", - CTy"Load", - TP[bVar"add", - bVar"index", - bVar"wback", - Var("Rt", - F4), - Var("Rt2", - F4), - Var("Rn", - F4), - Var("m", - CTy"offset2")])))))), - ITE(Bop(Or, - Bop(Or, + ("register_form2", + CTy"offset2", + Var("Rm", + F4)), + ITE(bVar"store", + Call + ("Store", + CTy"instruction", + Call + ("StoreDual", + CTy"Store", + TP[bVar"add", + bVar"index", + bVar"wback", + Var("Rt", + F4), + Var("Rt2", + F4), + Var("Rn", + F4), + Var("m", + CTy"offset2")])), + Call + ("Load", + CTy"instruction", + Call + ("LoadDual", + CTy"Load", + TP[bVar"add", + bVar"index", + bVar"wback", + Var("Rt", + F4), + Var("Rt2", + F4), + Var("Rn", + F4), + Var("m", + CTy"offset2")])))))), + ITE(Bop(Or, Bop(Or, Bop(Or, Bop(Or, @@ -26571,62 +26582,66 @@ val DecodeARM_def = Def F4), LW(15, 4))), - EQ(Var("Rm", - F4), - Var("Rt", - F4))), - EQ(Var("Rm", - F4), - Var("Rt2", - F4))), - Bop(And, - bVar"wback", - Bop(Or, + Bop(And, + Mop(Not, + bVar"store"), + Bop(Or, + EQ(Var("Rm", + F4), + Var("Rt", + F4)), + EQ(Var("Rm", + F4), + Var("Rt2", + F4))))), + Bop(And, + bVar"wback", Bop(Or, + Bop(Or, + EQ(Var("Rn", + F4), + LW(15, + 4)), + EQ(Var("Rn", + F4), + Var("Rt", + F4))), EQ(Var("Rn", F4), - LW(15, - 4)), - EQ(Var("Rn", - F4), - Var("Rt", - F4))), - EQ(Var("Rn", - F4), - Var("Rt2", - F4))))), - Bop(And, + Var("Rt2", + F4))))), Bop(And, - Bop(Lt, - Mop(Fst, - Apply - (Call - ("ArchVersion", - ATy(qTy, - PTy(nTy, - qTy)), - LU), - qVar"s")), - LN - 6), - bVar"wback"), - EQ(Var("Rm", - F4), - Var("Rn", - F4)))), - Mop(Snd, - Apply - (Call - ("DECODE_UNPREDICTABLE", - ATy(qTy, - PTy(uTy, - qTy)), - TP[Var("mc", - CTy"MachineCode"), - LS - "Load/StoreDual (register)"]), - qVar"s")), - qVar"s")])), + Bop(And, + Bop(Lt, + Mop(Fst, + Apply + (Call + ("ArchVersion", + ATy(qTy, + PTy(nTy, + qTy)), + LU), + qVar"s")), + LN + 6), + bVar"wback"), + EQ(Var("Rm", + F4), + Var("Rn", + F4)))), + Mop(Snd, + Apply + (Call + ("DECODE_UNPREDICTABLE", + ATy(qTy, + PTy(uTy, + qTy)), + TP[Var("mc", + CTy"MachineCode"), + LS + "Load/StoreDual (register)"]), + qVar"s")), + qVar"s")]))), TP[Mop(Fst, Apply (Call diff --git a/examples/l3-machine-code/arm/step/arm_stepLib.sml b/examples/l3-machine-code/arm/step/arm_stepLib.sml index 2b42baaf2e..2ef439755f 100644 --- a/examples/l3-machine-code/arm/step/arm_stepLib.sml +++ b/examples/l3-machine-code/arm/step/arm_stepLib.sml @@ -2710,11 +2710,17 @@ val DataProcessingPC_nsetflags_rwt = AddWithCarry, wordsTheory.FST_ADD_WITH_CARRY, ArithmeticOpcode_def, PC_rwt, IncPC_rwt, cond_rand_thms] [] (mapl (`opc`, utilsLib.tab_fixedwidth 16 4)) - ``DataProcessingPC (opc, F, n, imm32, c)``) reg_rwts + ``DataProcessingPC (opc, F, n, imm32)``) reg_rwts |> List.concat *) local + val x = ``x: word32 # bool`` + val DataProcessing = + DataProcessing_def + |> Q.SPECL [`opc`, `setflags`, `d`, `n`, `FST ^x`, `SND ^x`] + |> REWRITE_RULE [pairTheory.PAIR] + |> utilsLib.SET_RULE val DataProcessing_rwts = List.map (fn opc => @@ -2723,12 +2729,11 @@ local val wr = if i < 8 orelse 11 < i then [write'R_rwt] else [] in EV ([R_rwt, arm_stepTheory.R_x_not_pc, - utilsLib.SET_RULE DataProcessing_def, - DataProcessingALU_def, + DataProcessing, DataProcessingALU_def, AddWithCarry, wordsTheory.FST_ADD_WITH_CARRY, ArithmeticOpcode_def, PC_rwt, IncPC_rwt, cond_rand_thms, unit_state_cond] @ wr) [] [[`opc` |-> opc]] - ``DataProcessing (opc, setflags, d, n, imm32, c)`` + ``DataProcessing (opc, setflags, d, n, imm32_c)`` end |> List.map (utilsLib.ALL_HYP_CONV_RULE From 4e5904e7185466407156e1c8b46a8a87d91b67dc Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Tue, 25 Nov 2014 12:57:05 +0000 Subject: [PATCH 032/718] Fixes for MIPS instruction parsing and encoding. --- examples/l3-machine-code/mips/model/mips.sig | 2 +- examples/l3-machine-code/mips/model/mips.sml | 36 ++++++++++---------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/examples/l3-machine-code/mips/model/mips.sig b/examples/l3-machine-code/mips/model/mips.sig index 08a09f3d89..a62b79c485 100644 --- a/examples/l3-machine-code/mips/model/mips.sig +++ b/examples/l3-machine-code/mips/model/mips.sig @@ -1,4 +1,4 @@ -(* mips - generated by L<3> - Tue Nov 18 15:34:51 2014 *) +(* mips - generated by L<3> - Tue Nov 25 12:48:12 2014 *) signature mips = sig diff --git a/examples/l3-machine-code/mips/model/mips.sml b/examples/l3-machine-code/mips/model/mips.sml index 83ac8046b2..18fa4dc421 100644 --- a/examples/l3-machine-code/mips/model/mips.sml +++ b/examples/l3-machine-code/mips/model/mips.sml @@ -1,4 +1,4 @@ -(* mips - generated by L<3> - Tue Nov 18 15:34:51 2014 *) +(* mips - generated by L<3> - Tue Nov 25 12:48:12 2014 *) structure mips :> mips = struct @@ -9554,14 +9554,14 @@ fun Encode i = form1 (BitsN.B(0x0,5), (BitsN.B(0x0,5),(rd,(BitsN.B(0x0,5),BitsN.B(0x10,6))))) - | MultDiv(MTHI rd) => - form1 - (BitsN.B(0x0,5), - (BitsN.B(0x0,5),(rd,(BitsN.B(0x0,5),BitsN.B(0x11,6))))) - | MultDiv(MFLO rs) => + | MultDiv(MTHI rs) => form1 (rs, - (BitsN.B(0x0,5),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x12,6))))) + (BitsN.B(0x0,5),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x11,6))))) + | MultDiv(MFLO rd) => + form1 + (BitsN.B(0x0,5), + (BitsN.B(0x0,5),(rd,(BitsN.B(0x0,5),BitsN.B(0x12,6))))) | MultDiv(MTLO rs) => form1 (rs, @@ -9835,23 +9835,23 @@ fun p_r2 (s,(rs,rt)) = | "dmultu" => OK(MultDiv(DMULTU(rs,rt))) | "ddiv" => OK(MultDiv(DDIV(rs,rt))) | "ddivu" => OK(MultDiv(DDIVU(rs,rt))) - | "rge" => OK(Trap(TGE(rs,rt))) - | "rgeu" => OK(Trap(TGEU(rs,rt))) - | "rlt" => OK(Trap(TLT(rs,rt))) - | "rltu" => OK(Trap(TLTU(rs,rt))) + | "tge" => OK(Trap(TGE(rs,rt))) + | "tgeu" => OK(Trap(TGEU(rs,rt))) + | "tlt" => OK(Trap(TLT(rs,rt))) + | "tltu" => OK(Trap(TLTU(rs,rt))) | "teq" => OK(Trap(TEQ(rs,rt))) | "tne" => OK(Trap(TNE(rs,rt))) | "rdhwr" => OK(RDHWR(rs,rt)) | _ => FAIL("Unrecognised mnemonic"); -fun p_r3 (s,(rd,(rt,rs))) = +fun p_r3 (s,(rd,(rs,rt))) = case s of - "sllv" => OK(Shift(SLLV(rs,(rt,rd)))) - | "srlv" => OK(Shift(SRLV(rs,(rt,rd)))) - | "srav" => OK(Shift(SRAV(rs,(rt,rd)))) - | "dsllv" => OK(Shift(DSLLV(rs,(rt,rd)))) - | "dsrlv" => OK(Shift(DSRLV(rs,(rt,rd)))) - | "dsrav" => OK(Shift(DSRAV(rs,(rt,rd)))) + "sllv" => OK(Shift(SLLV(rt,(rs,rd)))) + | "srlv" => OK(Shift(SRLV(rt,(rs,rd)))) + | "srav" => OK(Shift(SRAV(rt,(rs,rd)))) + | "dsllv" => OK(Shift(DSLLV(rt,(rs,rd)))) + | "dsrlv" => OK(Shift(DSRLV(rt,(rs,rd)))) + | "dsrav" => OK(Shift(DSRAV(rt,(rs,rd)))) | "mul" => OK(MultDiv(MUL(rs,(rt,rd)))) | "movn" => OK(ArithR(MOVN(rs,(rt,rd)))) | "movz" => OK(ArithR(MOVZ(rs,(rt,rd)))) From c0318330ee22a33b3146060e647dd4f803d4cb4f Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Tue, 25 Nov 2014 14:43:16 +0000 Subject: [PATCH 033/718] Add CHERI model under L3 examples. CHERI is MIPS with capability extensions. See http://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ --- examples/l3-machine-code/cheri/Holmakefile | 1 + .../l3-machine-code/cheri/cheriScript.sml | 37407 ++++++++++++++++ 2 files changed, 37408 insertions(+) create mode 100644 examples/l3-machine-code/cheri/Holmakefile create mode 100644 examples/l3-machine-code/cheri/cheriScript.sml diff --git a/examples/l3-machine-code/cheri/Holmakefile b/examples/l3-machine-code/cheri/Holmakefile new file mode 100644 index 0000000000..777f8b3a5b --- /dev/null +++ b/examples/l3-machine-code/cheri/Holmakefile @@ -0,0 +1 @@ +INCLUDES = ../common diff --git a/examples/l3-machine-code/cheri/cheriScript.sml b/examples/l3-machine-code/cheri/cheriScript.sml new file mode 100644 index 0000000000..8ad16ea616 --- /dev/null +++ b/examples/l3-machine-code/cheri/cheriScript.sml @@ -0,0 +1,37407 @@ +(* cheriScript.sml - generated by L<3> - Tue Nov 25 14:34:02 2014 *) +open HolKernel boolLib bossLib Import + +val () = Import.start "cheri" + +val _ = Record + ("EntryLo", + [("C",FTy 3),("D",bTy),("G",bTy),("L",bTy),("PFN",FTy 28),("S",bTy), + ("V",bTy),("entrylo'rst",FTy 28)]) +; +val _ = Record + ("TLBEntry", + [("ASID",F8),("C0",FTy 3),("C1",FTy 3),("D0",bTy),("D1",bTy),("G",bTy), + ("L0",bTy),("L1",bTy),("Mask",FTy 12),("PFN0",FTy 28),("PFN1",FTy 28), + ("R",FTy 2),("S0",bTy),("S1",bTy),("V0",bTy),("V1",bTy), + ("VPN2",FTy 27)]) +; +val _ = Construct [("IorD",[("INSTRUCTION",[]),("DATA",[])])] +; +val _ = Construct + [("AccessType",[("LOAD",[]),("STORE",[]),("CLOAD",[]),("CSTORE",[])])] +; +val _ = Record ("Index",[("Index",F8),("P",bTy),("index'rst",FTy 23)]) +; +val _ = Record ("Random",[("Random",F8),("random'rst",FTy 24)]) +; +val _ = Record ("Wired",[("Wired",F8),("wired'rst",FTy 24)]) +; +val _ = Record ("PageMask",[("Mask",FTy 12),("pagemask'rst",FTy 20)]) +; +val _ = Record + ("EntryHi", + [("ASID",F8),("R",FTy 2),("VPN2",FTy 27),("entryhi'rst",FTy 27)]) +; +val _ = Record + ("StatusRegister", + [("BEV",bTy),("CU0",bTy),("CU1",bTy),("CU2",bTy),("CU3",bTy), + ("ERL",bTy),("EXL",bTy),("FR",bTy),("IE",bTy),("IM",F8),("KSU",FTy 2), + ("KX",bTy),("RE",bTy),("SX",bTy),("UX",bTy), + ("statusregister'rst",FTy 9)]) +; +val _ = Record + ("ConfigRegister", + [("AR",FTy 3),("AT",FTy 2),("BE",bTy),("K0",FTy 3),("M",bTy), + ("MT",FTy 3),("configregister'rst",FTy 19)]) +; +val _ = Record + ("ConfigRegister1", + [("C2",bTy),("CA",bTy),("DA",FTy 3),("DL",FTy 3),("DS",FTy 3), + ("EP",bTy),("FP",bTy),("IA",FTy 3),("IL",FTy 3),("IS",FTy 3), + ("M",bTy),("MD",bTy),("MMUSize",FTy 6),("PCR",bTy),("WR",bTy)]) +; +val _ = Record + ("ConfigRegister2", + [("M",bTy),("SA",F4),("SL",F4),("SS",F4),("SU",F4),("TA",F4),("TL",F4), + ("TS",F4),("TU",FTy 3)]) +; +val _ = Record + ("ConfigRegister3", + [("DSPP",bTy),("LPA",bTy),("M",bTy),("MT",bTy),("SM",bTy),("SP",bTy), + ("TL",bTy),("ULRI",bTy),("VEIC",bTy),("VInt",bTy), + ("configregister3'rst",FTy 22)]) +; +val _ = Record + ("ConfigRegister6", + [("LTLB",bTy),("TLBSize",F16),("configregister6'rst",FTy 15)]) +; +val _ = Record + ("CauseRegister", + [("BD",bTy),("CE",FTy 2),("ExcCode",FTy 5),("IP",F8),("TI",bTy), + ("causeregister'rst",FTy 15)]) +; +val _ = Record + ("Context",[("BadVPN2",FTy 19),("PTEBase",FTy 41),("context'rst",F4)]) +; +val _ = Record + ("XContext", + [("BadVPN2",FTy 27),("PTEBase",FTy 31),("R",FTy 2),("xcontext'rst",F4)]) +; +val _ = Record + ("HWREna", + [("CC",bTy),("CCRes",bTy),("CPUNum",bTy),("UL",bTy), + ("hwrena'rst",FTy 28)]) +; +val _ = Record + ("CP0__renamed__", + [("BadVAddr",F64),("Cause",CTy"CauseRegister"),("Compare",F32), + ("Config",CTy"ConfigRegister"),("Config1",CTy"ConfigRegister1"), + ("Config2",CTy"ConfigRegister2"),("Config3",CTy"ConfigRegister3"), + ("Config6",CTy"ConfigRegister6"),("Context",CTy"Context"), + ("Count",F32),("Debug",F32),("EInstr",F32),("EPC",F64), + ("EntryHi",CTy"EntryHi"),("EntryLo0",CTy"EntryLo"), + ("EntryLo1",CTy"EntryLo"),("ErrCtl",F32),("ErrorEPC",F64), + ("HWREna",CTy"HWREna"),("Index",CTy"Index"),("LLAddr",F64), + ("PRId",F32),("PageMask",CTy"PageMask"),("Random",CTy"Random"), + ("Status",CTy"StatusRegister"),("UsrLocal",F64),("Wired",CTy"Wired"), + ("XContext",CTy"XContext")]) +; +val _ = Record + ("PIC_Config_Reg", + [("EN",bTy),("IRQ",FTy 3),("pic_config_reg'rst",FTy 60)]) +; +val _ = Record + ("JTAG_UART_data__renamed__", + [("RAVAIL",F16),("RVALID",bTy),("RW_DATA",F8), + ("jtag_uart_data'rst",FTy 7)]) +; +val _ = Record + ("JTAG_UART_control__renamed__", + [("AC",bTy),("RE",bTy),("RI",bTy),("WE",bTy),("WI",bTy),("WSPACE",F16), + ("jtag_uart_control'rst",FTy 11)]) +; +val _ = Record + ("JTAG_UART", + [("base_address",FTy 37),("control",CTy"JTAG_UART_control__renamed__"), + ("data",CTy"JTAG_UART_data__renamed__"),("read_fifo",LTy F8), + ("read_threshold",nTy),("write_fifo",LTy F8),("write_threshold",nTy)]) +; +val _ = Record + ("Perms", + [("Access_EPCC",bTy),("Access_KCC",bTy),("Access_KDC",bTy), + ("Access_KR1C",bTy),("Access_KR2C",bTy),("Global",bTy), + ("Permit_Execute",bTy),("Permit_Load",bTy), + ("Permit_Load_Capability",bTy),("Permit_Seal",bTy), + ("Permit_Set_Type",bTy),("Permit_Store",bTy), + ("Permit_Store_Capability",bTy),("Permit_Store_Local_Capability",bTy), + ("Reserved",bTy),("soft",F16)]) +; +val _ = Record + ("Capability", + [("base",F64),("length",F64),("offset",F64),("otype",FTy 24), + ("perms",FTy 31),("reserved",F8),("sealed",bTy),("tag",bTy)]) +; +val _ = Record ("CapCause",[("ExcCode",F8),("RegNum",F8)]) +; +val _ = Construct + [("ExceptionType", + [("Int",[]),("Mod",[]),("TLBL",[]),("TLBS",[]),("AdEL",[]), + ("AdES",[]),("Sys",[]),("Bp",[]),("ResI",[]),("CpU",[]),("Ov",[]), + ("Tr",[]),("CTLBL",[]),("CTLBS",[]),("C2E",[]),("XTLBRefillL",[]), + ("XTLBRefillS",[])])] +; +val _ = Construct + [("CapException", + [("capExcNone",[]),("capExcLength",[]),("capExcTag",[]), + ("capExcSeal",[]),("capExcType",[]),("capExcCall",[]), + ("capExcRet",[]),("capExcUnderflowTSS",[]),("capExcUser",[]), + ("capExcTLBNoStore",[]),("capExcGlobal",[]),("capExcPermExe",[]), + ("capExcPermLoad",[]),("capExcPermStore",[]), + ("capExcPermLoadCap",[]),("capExcPermStoreCap",[]), + ("capExcPermStoreLocalCap",[]),("capExcPermSeal",[]), + ("capExcPermSetType",[]),("capExcAccEPCC",[]),("capExcAccKDC",[]), + ("capExcAccKCC",[]),("capExcAccKR1C",[]),("capExcAccKR2C",[])])] +; +val _ = Construct + [("Branch", + [("BEQ",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("BEQL",[PTy(FTy 5,PTy(FTy 5,F16))]),("BGEZ",[PTy(FTy 5,F16)]), + ("BGEZAL",[PTy(FTy 5,F16)]),("BGEZALL",[PTy(FTy 5,F16)]), + ("BGEZL",[PTy(FTy 5,F16)]),("BGTZ",[PTy(FTy 5,F16)]), + ("BGTZL",[PTy(FTy 5,F16)]),("BLEZ",[PTy(FTy 5,F16)]), + ("BLEZL",[PTy(FTy 5,F16)]),("BLTZ",[PTy(FTy 5,F16)]), + ("BLTZAL",[PTy(FTy 5,F16)]),("BLTZALL",[PTy(FTy 5,F16)]), + ("BLTZL",[PTy(FTy 5,F16)]),("BNE",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("BNEL",[PTy(FTy 5,PTy(FTy 5,F16))]),("J",[FTy 26]),("JAL",[FTy 26]), + ("JALR",[PTy(FTy 5,FTy 5)]),("JR",[FTy 5])])] +; +val _ = Construct + [("CP", + [("DMFC0",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("DMTC0",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("MFC0",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("MTC0",[PTy(FTy 5,PTy(FTy 5,FTy 3))])])] +; +val _ = Construct + [("Store", + [("SB",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SC",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SCD",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SD",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SDL",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SDR",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SH",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SW",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SWL",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SWR",[PTy(FTy 5,PTy(FTy 5,F16))])])] +; +val _ = Construct + [("Load", + [("LB",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LBU",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LD",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LDL",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LDR",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LH",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LHU",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LL",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LLD",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LW",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LWL",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LWR",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("LWU",[PTy(FTy 5,PTy(FTy 5,F16))])])] +; +val _ = Construct + [("Trap", + [("TEQ",[PTy(FTy 5,FTy 5)]),("TEQI",[PTy(FTy 5,F16)]), + ("TGE",[PTy(FTy 5,FTy 5)]),("TGEI",[PTy(FTy 5,F16)]), + ("TGEIU",[PTy(FTy 5,F16)]),("TGEU",[PTy(FTy 5,FTy 5)]), + ("TLT",[PTy(FTy 5,FTy 5)]),("TLTI",[PTy(FTy 5,F16)]), + ("TLTIU",[PTy(FTy 5,F16)]),("TLTU",[PTy(FTy 5,FTy 5)]), + ("TNE",[PTy(FTy 5,FTy 5)]),("TNEI",[PTy(FTy 5,F16)])])] +; +val _ = Construct + [("Shift", + [("DSLL",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSLL32",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSLLV",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSRA",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSRA32",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSRAV",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSRL",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSRL32",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSRLV",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SLL",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SLLV",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRA",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRAV",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRL",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRLV",[PTy(FTy 5,PTy(FTy 5,FTy 5))])])] +; +val _ = Construct + [("MultDiv", + [("DDIV",[PTy(FTy 5,FTy 5)]),("DDIVU",[PTy(FTy 5,FTy 5)]), + ("DIV",[PTy(FTy 5,FTy 5)]),("DIVU",[PTy(FTy 5,FTy 5)]), + ("DMULT",[PTy(FTy 5,FTy 5)]),("DMULTU",[PTy(FTy 5,FTy 5)]), + ("MADD",[PTy(FTy 5,FTy 5)]),("MADDU",[PTy(FTy 5,FTy 5)]), + ("MFHI",[FTy 5]),("MFLO",[FTy 5]),("MSUB",[PTy(FTy 5,FTy 5)]), + ("MSUBU",[PTy(FTy 5,FTy 5)]),("MTHI",[FTy 5]),("MTLO",[FTy 5]), + ("MUL",[PTy(FTy 5,PTy(FTy 5,FTy 5))]),("MULT",[PTy(FTy 5,FTy 5)]), + ("MULTU",[PTy(FTy 5,FTy 5)])])] +; +val _ = Construct + [("ArithR", + [("ADD",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("ADDU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("AND",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DADD",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DADDU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSUB",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DSUBU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("MOVN",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("MOVZ",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("NOR",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("OR",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SLT",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SLTU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SUB",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SUBU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("XOR",[PTy(FTy 5,PTy(FTy 5,FTy 5))])])] +; +val _ = Construct + [("ArithI", + [("ADDI",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("ADDIU",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("ANDI",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("DADDI",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("DADDIU",[PTy(FTy 5,PTy(FTy 5,F16))]),("LUI",[PTy(FTy 5,F16)]), + ("ORI",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SLTI",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("SLTIU",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("XORI",[PTy(FTy 5,PTy(FTy 5,F16))])])] +; +val _ = Construct + [("CGet", + [("CGetBase",[PTy(FTy 5,FTy 5)]),("CGetCause",[FTy 5]), + ("CGetLen",[PTy(FTy 5,FTy 5)]),("CGetOffset",[PTy(FTy 5,FTy 5)]), + ("CGetPCC",[FTy 5]),("CGetPerm",[PTy(FTy 5,FTy 5)]), + ("CGetSealed",[PTy(FTy 5,FTy 5)]),("CGetTag",[PTy(FTy 5,FTy 5)]), + ("CGetType",[PTy(FTy 5,FTy 5)]), + ("CToPtr",[PTy(FTy 5,PTy(FTy 5,FTy 5))])])] +; +val _ = Construct + [("CSet", + [("CAndPerm",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("CClearTag",[PTy(FTy 5,FTy 5)]), + ("CFromPtr",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("CIncBase",[PTy(FTy 5,PTy(FTy 5,FTy 5))]),("CSetCause",[FTy 5]), + ("CSetLen",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("CSetOffset",[PTy(FTy 5,PTy(FTy 5,FTy 5))])])] +; +val _ = Construct + [("CCheck", + [("CCheckPerm",[PTy(FTy 5,FTy 5)]),("CCheckType",[PTy(FTy 5,FTy 5)])])] +; +val _ = Construct + [("CHERICOP2", + [("CBTS",[PTy(FTy 5,F16)]),("CBTU",[PTy(FTy 5,F16)]), + ("CCall",[PTy(FTy 5,FTy 5)]),("CCheck",[CTy"CCheck"]), + ("CGet",[CTy"CGet"]),("CJALR",[PTy(FTy 5,FTy 5)]),("CJR",[FTy 5]), + ("CPtrCmp",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))]),("CReturn",[]), + ("CSeal",[PTy(FTy 5,PTy(FTy 5,FTy 5))]),("CSet",[CTy"CSet"]), + ("CUnseal",[PTy(FTy 5,PTy(FTy 5,FTy 5))]),("DumpCapReg",[]), + ("UnknownCapInstruction",[])])] +; +val _ = Construct [("COP2",[("CHERICOP2",[CTy"CHERICOP2"])])] +; +val _ = Construct + [("CHERISWC2", + [("CSCD",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,F8)))]), + ("CStore",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(F8,FTy 2))))])])] +; +val _ = Construct [("SWC2",[("CHERISWC2",[CTy"CHERISWC2"])])] +; +val _ = Construct + [("CHERILWC2", + [("CLLD",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,F8)))]), + ("CLoad",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(F8,PTy(F1,FTy 2)))))])])] +; +val _ = Construct [("LWC2",[("CHERILWC2",[CTy"CHERILWC2"])])] +; +val _ = Construct + [("CHERILDC2",[("CLC",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 11)))])])] +; +val _ = Construct [("LDC2",[("CHERILDC2",[CTy"CHERILDC2"])])] +; +val _ = Construct + [("CHERISDC2",[("CSC",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 11)))])])] +; +val _ = Construct [("SDC2",[("CHERISDC2",[CTy"CHERISDC2"])])] +; +val _ = Construct + [("instruction", + [("ArithI",[CTy"ArithI"]),("ArithR",[CTy"ArithR"]),("BREAK",[]), + ("Branch",[CTy"Branch"]),("CACHE",[PTy(FTy 5,PTy(FTy 5,F16))]), + ("COP2",[CTy"COP2"]),("CP",[CTy"CP"]),("ERET",[]), + ("LDC2",[CTy"LDC2"]),("LWC2",[CTy"LWC2"]),("Load",[CTy"Load"]), + ("MultDiv",[CTy"MultDiv"]),("RDHWR",[PTy(FTy 5,FTy 5)]), + ("ReservedInstruction",[]),("SDC2",[CTy"SDC2"]),("SWC2",[CTy"SWC2"]), + ("SYNC",[FTy 5]),("SYSCALL",[]),("Shift",[CTy"Shift"]), + ("Store",[CTy"Store"]),("TLBP",[]),("TLBR",[]),("TLBWI",[]), + ("TLBWR",[]),("Trap",[CTy"Trap"]),("Unpredictable",[]),("WAIT",[])])] +; +val _ = Construct + [("exception",[("NoException",[]),("UNPREDICTABLE",[sTy])])] +; +val _ = Record + ("cheri_state", + [("JTAG_UART",CTy"JTAG_UART"),("MEM",ATy(FTy 37,F64)), + ("PIC_base_address",ATy(F8,FTy 37)), + ("PIC_config_regs",ATy(F8,ATy(FTy 7,CTy"PIC_Config_Reg"))), + ("PIC_external_intrs",ATy(F8,F64)),("PIC_ip_bits",ATy(F8,FTy 128)), + ("TAG",ATy(FTy 35,bTy)),("UNPREDICTABLE_HI",ATy(uTy,uTy)), + ("UNPREDICTABLE_LO",ATy(uTy,uTy)),("c_BranchDelay",ATy(F8,OTy F64)), + ("c_BranchDelayPCC",ATy(F8,OTy(PTy(F64,CTy"Capability")))), + ("c_BranchTo",ATy(F8,OTy F64)), + ("c_BranchToPCC",ATy(F8,OTy(PTy(F64,CTy"Capability")))), + ("c_CP0",ATy(F8,CTy"CP0__renamed__")),("c_LLbit",ATy(F8,OTy bTy)), + ("c_PC",ATy(F8,F64)),("c_TLB_assoc",ATy(F8,ATy(F4,CTy"TLBEntry"))), + ("c_TLB_direct",ATy(F8,ATy(FTy 7,CTy"TLBEntry"))), + ("c_capcause",ATy(F8,CTy"CapCause")), + ("c_capr",ATy(F8,ATy(FTy 5,CTy"Capability"))), + ("c_exceptionSignalled",ATy(F8,bTy)),("c_gpr",ATy(F8,ATy(FTy 5,F64))), + ("c_hi",ATy(F8,OTy F64)),("c_lo",ATy(F8,OTy F64)), + ("c_pcc",ATy(F8,CTy"Capability")),("currentInst",OTy F32), + ("done",bTy),("exception",CTy"exception"),("instCnt",nTy), + ("log",ATy(nTy,LTy sTy)),("print",ATy(sTy,uTy)), + ("println",ATy(sTy,uTy)),("procID",F8),("totalCore",nTy)]) +; +val qTy = CTy "cheri_state"; +fun qVar v = Term.mk_var (v, ParseDatatype.pretypeToType qTy); +val raise'exception_def = Def + ("raise'exception",Var("e",CTy"exception"), + Close + (qVar"state", + TP[LX(VTy"a"), + ITE(EQ(Dest("exception",CTy"exception",qVar"state"), + Const("NoException",CTy"exception")), + Rupd("exception",TP[qVar"state",Var("e",CTy"exception")]), + qVar"state")])) +; +val rec'EntryLo_def = Def + ("rec'EntryLo",Var("x",F64), + Rec(CTy"EntryLo", + [EX(Var("x",F64),LN 5,LN 3,FTy 3),Bop(Bit,Var("x",F64),LN 2), + Bop(Bit,Var("x",F64),LN 0),Bop(Bit,Var("x",F64),LN 62), + EX(Var("x",F64),LN 33,LN 6,FTy 28),Bop(Bit,Var("x",F64),LN 63), + Bop(Bit,Var("x",F64),LN 1),EX(Var("x",F64),LN 61,LN 34,FTy 28)])) +; +val reg'EntryLo_def = Def + ("reg'EntryLo",Var("x",CTy"EntryLo"), + CS(Var("x",CTy"EntryLo"), + [(Rec(CTy"EntryLo", + [Var("C",FTy 3),bVar"D",bVar"G",bVar"L",Var("PFN",FTy 28), + bVar"S",bVar"V",Var("entrylo'rst",FTy 28)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 63),bVar"S"), + (EQ(nVar"i",LN 62),bVar"L"), + (EQ(nVar"i",LN 61), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 27)), + (EQ(nVar"i",LN 60), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 26)), + (EQ(nVar"i",LN 59), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 25)), + (EQ(nVar"i",LN 58), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 24)), + (EQ(nVar"i",LN 57), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 23)), + (EQ(nVar"i",LN 56), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 22)), + (EQ(nVar"i",LN 55), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 21)), + (EQ(nVar"i",LN 54), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 20)), + (EQ(nVar"i",LN 53), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 19)), + (EQ(nVar"i",LN 52), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 18)), + (EQ(nVar"i",LN 51), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 17)), + (EQ(nVar"i",LN 50), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 16)), + (EQ(nVar"i",LN 49), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 15)), + (EQ(nVar"i",LN 48), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 14)), + (EQ(nVar"i",LN 47), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 13)), + (EQ(nVar"i",LN 46), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 12)), + (EQ(nVar"i",LN 45), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 11)), + (EQ(nVar"i",LN 44), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 10)), + (EQ(nVar"i",LN 43), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 9)), + (EQ(nVar"i",LN 42), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 8)), + (EQ(nVar"i",LN 41), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 7)), + (EQ(nVar"i",LN 40), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 6)), + (EQ(nVar"i",LN 39), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 5)), + (EQ(nVar"i",LN 38), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 4)), + (EQ(nVar"i",LN 37), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 3)), + (EQ(nVar"i",LN 36), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 2)), + (EQ(nVar"i",LN 35), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 1)), + (EQ(nVar"i",LN 34), + Bop(Bit,Var("entrylo'rst",FTy 28),LN 0)), + (EQ(nVar"i",LN 33),Bop(Bit,Var("PFN",FTy 28),LN 27)), + (EQ(nVar"i",LN 32),Bop(Bit,Var("PFN",FTy 28),LN 26)), + (EQ(nVar"i",LN 31),Bop(Bit,Var("PFN",FTy 28),LN 25)), + (EQ(nVar"i",LN 30),Bop(Bit,Var("PFN",FTy 28),LN 24)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("PFN",FTy 28),LN 23)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("PFN",FTy 28),LN 22)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("PFN",FTy 28),LN 21)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("PFN",FTy 28),LN 20)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("PFN",FTy 28),LN 19)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("PFN",FTy 28),LN 18)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("PFN",FTy 28),LN 17)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("PFN",FTy 28),LN 16)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("PFN",FTy 28),LN 15)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("PFN",FTy 28),LN 14)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("PFN",FTy 28),LN 13)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("PFN",FTy 28),LN 12)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("PFN",FTy 28),LN 11)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("PFN",FTy 28),LN 10)), + (EQ(nVar"i",LN 15),Bop(Bit,Var("PFN",FTy 28),LN 9)), + (EQ(nVar"i",LN 14),Bop(Bit,Var("PFN",FTy 28),LN 8)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("PFN",FTy 28),LN 7)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("PFN",FTy 28),LN 6)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("PFN",FTy 28),LN 5)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("PFN",FTy 28),LN 4)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("PFN",FTy 28),LN 3)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("PFN",FTy 28),LN 2)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("PFN",FTy 28),LN 1)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("PFN",FTy 28),LN 0)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("C",FTy 3),LN 2)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("C",FTy 3),LN 1)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("C",FTy 3),LN 0)), + (EQ(nVar"i",LN 2),bVar"D"),(EQ(nVar"i",LN 1),bVar"V")], + bVar"G")),LW(0,64)))])) +; +val write'rec'EntryLo_def = Def + ("write'rec'EntryLo",TP[AVar F64,Var("x",CTy"EntryLo")], + Call("reg'EntryLo",F64,Var("x",CTy"EntryLo"))) +; +val write'reg'EntryLo_def = Def + ("write'reg'EntryLo",TP[AVar(CTy"EntryLo"),Var("x",F64)], + Call("rec'EntryLo",CTy"EntryLo",Var("x",F64))) +; +val rec'Index_def = Def + ("rec'Index",Var("x",F32), + Rec(CTy"Index", + [EX(Var("x",F32),LN 7,LN 0,F8),Bop(Bit,Var("x",F32),LN 31), + EX(Var("x",F32),LN 30,LN 8,FTy 23)])) +; +val reg'Index_def = Def + ("reg'Index",Var("x",CTy"Index"), + CS(Var("x",CTy"Index"), + [(Rec(CTy"Index",[Var("Index",F8),bVar"P",Var("index'rst",FTy 23)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),bVar"P"), + (EQ(nVar"i",LN 30), + Bop(Bit,Var("index'rst",FTy 23),LN 22)), + (EQ(nVar"i",LN 29), + Bop(Bit,Var("index'rst",FTy 23),LN 21)), + (EQ(nVar"i",LN 28), + Bop(Bit,Var("index'rst",FTy 23),LN 20)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("index'rst",FTy 23),LN 19)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("index'rst",FTy 23),LN 18)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("index'rst",FTy 23),LN 17)), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("index'rst",FTy 23),LN 16)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("index'rst",FTy 23),LN 15)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("index'rst",FTy 23),LN 14)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("index'rst",FTy 23),LN 13)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("index'rst",FTy 23),LN 12)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("index'rst",FTy 23),LN 11)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("index'rst",FTy 23),LN 10)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("index'rst",FTy 23),LN 9)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("index'rst",FTy 23),LN 8)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("index'rst",FTy 23),LN 7)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("index'rst",FTy 23),LN 6)), + (EQ(nVar"i",LN 13), + Bop(Bit,Var("index'rst",FTy 23),LN 5)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("index'rst",FTy 23),LN 4)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("index'rst",FTy 23),LN 3)), + (EQ(nVar"i",LN 10), + Bop(Bit,Var("index'rst",FTy 23),LN 2)), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("index'rst",FTy 23),LN 1)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("index'rst",FTy 23),LN 0)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("Index",F8),LN 7)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("Index",F8),LN 6)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("Index",F8),LN 5)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("Index",F8),LN 4)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("Index",F8),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("Index",F8),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("Index",F8),LN 1))], + Bop(Bit,Var("Index",F8),LN 0))),LW(0,32)))])) +; +val write'rec'Index_def = Def + ("write'rec'Index",TP[AVar F32,Var("x",CTy"Index")], + Call("reg'Index",F32,Var("x",CTy"Index"))) +; +val write'reg'Index_def = Def + ("write'reg'Index",TP[AVar(CTy"Index"),Var("x",F32)], + Call("rec'Index",CTy"Index",Var("x",F32))) +; +val rec'Random_def = Def + ("rec'Random",Var("x",F32), + Rec(CTy"Random", + [EX(Var("x",F32),LN 7,LN 0,F8),EX(Var("x",F32),LN 31,LN 8,FTy 24)])) +; +val reg'Random_def = Def + ("reg'Random",Var("x",CTy"Random"), + CS(Var("x",CTy"Random"), + [(Rec(CTy"Random",[Var("Random",F8),Var("random'rst",FTy 24)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31), + Bop(Bit,Var("random'rst",FTy 24),LN 23)), + (EQ(nVar"i",LN 30), + Bop(Bit,Var("random'rst",FTy 24),LN 22)), + (EQ(nVar"i",LN 29), + Bop(Bit,Var("random'rst",FTy 24),LN 21)), + (EQ(nVar"i",LN 28), + Bop(Bit,Var("random'rst",FTy 24),LN 20)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("random'rst",FTy 24),LN 19)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("random'rst",FTy 24),LN 18)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("random'rst",FTy 24),LN 17)), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("random'rst",FTy 24),LN 16)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("random'rst",FTy 24),LN 15)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("random'rst",FTy 24),LN 14)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("random'rst",FTy 24),LN 13)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("random'rst",FTy 24),LN 12)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("random'rst",FTy 24),LN 11)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("random'rst",FTy 24),LN 10)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("random'rst",FTy 24),LN 9)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("random'rst",FTy 24),LN 8)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("random'rst",FTy 24),LN 7)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("random'rst",FTy 24),LN 6)), + (EQ(nVar"i",LN 13), + Bop(Bit,Var("random'rst",FTy 24),LN 5)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("random'rst",FTy 24),LN 4)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("random'rst",FTy 24),LN 3)), + (EQ(nVar"i",LN 10), + Bop(Bit,Var("random'rst",FTy 24),LN 2)), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("random'rst",FTy 24),LN 1)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("random'rst",FTy 24),LN 0)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("Random",F8),LN 7)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("Random",F8),LN 6)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("Random",F8),LN 5)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("Random",F8),LN 4)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("Random",F8),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("Random",F8),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("Random",F8),LN 1))], + Bop(Bit,Var("Random",F8),LN 0))),LW(0,32)))])) +; +val write'rec'Random_def = Def + ("write'rec'Random",TP[AVar F32,Var("x",CTy"Random")], + Call("reg'Random",F32,Var("x",CTy"Random"))) +; +val write'reg'Random_def = Def + ("write'reg'Random",TP[AVar(CTy"Random"),Var("x",F32)], + Call("rec'Random",CTy"Random",Var("x",F32))) +; +val rec'Wired_def = Def + ("rec'Wired",Var("x",F32), + Rec(CTy"Wired", + [EX(Var("x",F32),LN 7,LN 0,F8),EX(Var("x",F32),LN 31,LN 8,FTy 24)])) +; +val reg'Wired_def = Def + ("reg'Wired",Var("x",CTy"Wired"), + CS(Var("x",CTy"Wired"), + [(Rec(CTy"Wired",[Var("Wired",F8),Var("wired'rst",FTy 24)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31), + Bop(Bit,Var("wired'rst",FTy 24),LN 23)), + (EQ(nVar"i",LN 30), + Bop(Bit,Var("wired'rst",FTy 24),LN 22)), + (EQ(nVar"i",LN 29), + Bop(Bit,Var("wired'rst",FTy 24),LN 21)), + (EQ(nVar"i",LN 28), + Bop(Bit,Var("wired'rst",FTy 24),LN 20)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("wired'rst",FTy 24),LN 19)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("wired'rst",FTy 24),LN 18)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("wired'rst",FTy 24),LN 17)), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("wired'rst",FTy 24),LN 16)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("wired'rst",FTy 24),LN 15)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("wired'rst",FTy 24),LN 14)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("wired'rst",FTy 24),LN 13)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("wired'rst",FTy 24),LN 12)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("wired'rst",FTy 24),LN 11)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("wired'rst",FTy 24),LN 10)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("wired'rst",FTy 24),LN 9)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("wired'rst",FTy 24),LN 8)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("wired'rst",FTy 24),LN 7)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("wired'rst",FTy 24),LN 6)), + (EQ(nVar"i",LN 13), + Bop(Bit,Var("wired'rst",FTy 24),LN 5)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("wired'rst",FTy 24),LN 4)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("wired'rst",FTy 24),LN 3)), + (EQ(nVar"i",LN 10), + Bop(Bit,Var("wired'rst",FTy 24),LN 2)), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("wired'rst",FTy 24),LN 1)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("wired'rst",FTy 24),LN 0)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("Wired",F8),LN 7)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("Wired",F8),LN 6)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("Wired",F8),LN 5)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("Wired",F8),LN 4)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("Wired",F8),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("Wired",F8),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("Wired",F8),LN 1))], + Bop(Bit,Var("Wired",F8),LN 0))),LW(0,32)))])) +; +val write'rec'Wired_def = Def + ("write'rec'Wired",TP[AVar F32,Var("x",CTy"Wired")], + Call("reg'Wired",F32,Var("x",CTy"Wired"))) +; +val write'reg'Wired_def = Def + ("write'reg'Wired",TP[AVar(CTy"Wired"),Var("x",F32)], + Call("rec'Wired",CTy"Wired",Var("x",F32))) +; +val rec'PageMask_def = Def + ("rec'PageMask",Var("x",F32), + Rec(CTy"PageMask", + [EX(Var("x",F32),LN 24,LN 13,FTy 12), + CC[EX(Var("x",F32),LN 12,LN 0,FTy 13), + EX(Var("x",F32),LN 31,LN 25,FTy 7)]])) +; +val reg'PageMask_def = Def + ("reg'PageMask",Var("x",CTy"PageMask"), + CS(Var("x",CTy"PageMask"), + [(Rec(CTy"PageMask",[Var("Mask",FTy 12),Var("pagemask'rst",FTy 20)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 6)), + (EQ(nVar"i",LN 30), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 5)), + (EQ(nVar"i",LN 29), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 4)), + (EQ(nVar"i",LN 28), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 3)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 2)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 1)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 0)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("Mask",FTy 12),LN 11)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("Mask",FTy 12),LN 10)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("Mask",FTy 12),LN 9)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("Mask",FTy 12),LN 8)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("Mask",FTy 12),LN 7)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("Mask",FTy 12),LN 6)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("Mask",FTy 12),LN 5)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("Mask",FTy 12),LN 4)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("Mask",FTy 12),LN 3)), + (EQ(nVar"i",LN 15),Bop(Bit,Var("Mask",FTy 12),LN 2)), + (EQ(nVar"i",LN 14),Bop(Bit,Var("Mask",FTy 12),LN 1)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("Mask",FTy 12),LN 0)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 19)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 18)), + (EQ(nVar"i",LN 10), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 17)), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 16)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 15)), + (EQ(nVar"i",LN 7), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 14)), + (EQ(nVar"i",LN 6), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 13)), + (EQ(nVar"i",LN 5), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 12)), + (EQ(nVar"i",LN 4), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 11)), + (EQ(nVar"i",LN 3), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 10)), + (EQ(nVar"i",LN 2), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 9)), + (EQ(nVar"i",LN 1), + Bop(Bit,Var("pagemask'rst",FTy 20),LN 8))], + Bop(Bit,Var("pagemask'rst",FTy 20),LN 7))),LW(0,32)))])) +; +val write'rec'PageMask_def = Def + ("write'rec'PageMask",TP[AVar F32,Var("x",CTy"PageMask")], + Call("reg'PageMask",F32,Var("x",CTy"PageMask"))) +; +val write'reg'PageMask_def = Def + ("write'reg'PageMask",TP[AVar(CTy"PageMask"),Var("x",F32)], + Call("rec'PageMask",CTy"PageMask",Var("x",F32))) +; +val rec'EntryHi_def = Def + ("rec'EntryHi",Var("x",F64), + Rec(CTy"EntryHi", + [EX(Var("x",F64),LN 7,LN 0,F8),EX(Var("x",F64),LN 63,LN 62,FTy 2), + EX(Var("x",F64),LN 39,LN 13,FTy 27), + CC[EX(Var("x",F64),LN 12,LN 8,FTy 5), + EX(Var("x",F64),LN 61,LN 40,FTy 22)]])) +; +val reg'EntryHi_def = Def + ("reg'EntryHi",Var("x",CTy"EntryHi"), + CS(Var("x",CTy"EntryHi"), + [(Rec(CTy"EntryHi", + [Var("ASID",F8),Var("R",FTy 2),Var("VPN2",FTy 27), + Var("entryhi'rst",FTy 27)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 63),Bop(Bit,Var("R",FTy 2),LN 1)), + (EQ(nVar"i",LN 62),Bop(Bit,Var("R",FTy 2),LN 0)), + (EQ(nVar"i",LN 61), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 21)), + (EQ(nVar"i",LN 60), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 20)), + (EQ(nVar"i",LN 59), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 19)), + (EQ(nVar"i",LN 58), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 18)), + (EQ(nVar"i",LN 57), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 17)), + (EQ(nVar"i",LN 56), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 16)), + (EQ(nVar"i",LN 55), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 15)), + (EQ(nVar"i",LN 54), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 14)), + (EQ(nVar"i",LN 53), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 13)), + (EQ(nVar"i",LN 52), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 12)), + (EQ(nVar"i",LN 51), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 11)), + (EQ(nVar"i",LN 50), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 10)), + (EQ(nVar"i",LN 49), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 9)), + (EQ(nVar"i",LN 48), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 8)), + (EQ(nVar"i",LN 47), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 7)), + (EQ(nVar"i",LN 46), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 6)), + (EQ(nVar"i",LN 45), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 5)), + (EQ(nVar"i",LN 44), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 4)), + (EQ(nVar"i",LN 43), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 3)), + (EQ(nVar"i",LN 42), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 2)), + (EQ(nVar"i",LN 41), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 1)), + (EQ(nVar"i",LN 40), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 0)), + (EQ(nVar"i",LN 39),Bop(Bit,Var("VPN2",FTy 27),LN 26)), + (EQ(nVar"i",LN 38),Bop(Bit,Var("VPN2",FTy 27),LN 25)), + (EQ(nVar"i",LN 37),Bop(Bit,Var("VPN2",FTy 27),LN 24)), + (EQ(nVar"i",LN 36),Bop(Bit,Var("VPN2",FTy 27),LN 23)), + (EQ(nVar"i",LN 35),Bop(Bit,Var("VPN2",FTy 27),LN 22)), + (EQ(nVar"i",LN 34),Bop(Bit,Var("VPN2",FTy 27),LN 21)), + (EQ(nVar"i",LN 33),Bop(Bit,Var("VPN2",FTy 27),LN 20)), + (EQ(nVar"i",LN 32),Bop(Bit,Var("VPN2",FTy 27),LN 19)), + (EQ(nVar"i",LN 31),Bop(Bit,Var("VPN2",FTy 27),LN 18)), + (EQ(nVar"i",LN 30),Bop(Bit,Var("VPN2",FTy 27),LN 17)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("VPN2",FTy 27),LN 16)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("VPN2",FTy 27),LN 15)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("VPN2",FTy 27),LN 14)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("VPN2",FTy 27),LN 13)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("VPN2",FTy 27),LN 12)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("VPN2",FTy 27),LN 11)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("VPN2",FTy 27),LN 10)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("VPN2",FTy 27),LN 9)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("VPN2",FTy 27),LN 8)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("VPN2",FTy 27),LN 7)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("VPN2",FTy 27),LN 6)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("VPN2",FTy 27),LN 5)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("VPN2",FTy 27),LN 4)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("VPN2",FTy 27),LN 3)), + (EQ(nVar"i",LN 15),Bop(Bit,Var("VPN2",FTy 27),LN 2)), + (EQ(nVar"i",LN 14),Bop(Bit,Var("VPN2",FTy 27),LN 1)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("VPN2",FTy 27),LN 0)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 26)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 25)), + (EQ(nVar"i",LN 10), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 24)), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 23)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("entryhi'rst",FTy 27),LN 22)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("ASID",F8),LN 7)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("ASID",F8),LN 6)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("ASID",F8),LN 5)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("ASID",F8),LN 4)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("ASID",F8),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("ASID",F8),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("ASID",F8),LN 1))], + Bop(Bit,Var("ASID",F8),LN 0))),LW(0,64)))])) +; +val write'rec'EntryHi_def = Def + ("write'rec'EntryHi",TP[AVar F64,Var("x",CTy"EntryHi")], + Call("reg'EntryHi",F64,Var("x",CTy"EntryHi"))) +; +val write'reg'EntryHi_def = Def + ("write'reg'EntryHi",TP[AVar(CTy"EntryHi"),Var("x",F64)], + Call("rec'EntryHi",CTy"EntryHi",Var("x",F64))) +; +val rec'StatusRegister_def = Def + ("rec'StatusRegister",Var("x",F32), + Rec(CTy"StatusRegister", + [Bop(Bit,Var("x",F32),LN 22),Bop(Bit,Var("x",F32),LN 28), + Bop(Bit,Var("x",F32),LN 29),Bop(Bit,Var("x",F32),LN 30), + Bop(Bit,Var("x",F32),LN 31),Bop(Bit,Var("x",F32),LN 2), + Bop(Bit,Var("x",F32),LN 1),Bop(Bit,Var("x",F32),LN 26), + Bop(Bit,Var("x",F32),LN 0),EX(Var("x",F32),LN 15,LN 8,F8), + EX(Var("x",F32),LN 4,LN 3,FTy 2),Bop(Bit,Var("x",F32),LN 7), + Bop(Bit,Var("x",F32),LN 25),Bop(Bit,Var("x",F32),LN 6), + Bop(Bit,Var("x",F32),LN 5), + CC[EX(Var("x",F32),LN 21,LN 16,FTy 6), + EX(Var("x",F32),LN 24,LN 23,FTy 2), + EX(Var("x",F32),LN 27,LN 27,F1)]])) +; +val reg'StatusRegister_def = Def + ("reg'StatusRegister",Var("x",CTy"StatusRegister"), + CS(Var("x",CTy"StatusRegister"), + [(Rec(CTy"StatusRegister", + [bVar"BEV",bVar"CU0",bVar"CU1",bVar"CU2",bVar"CU3",bVar"ERL", + bVar"EXL",bVar"FR",bVar"IE",Var("IM",F8),Var("KSU",FTy 2), + bVar"KX",bVar"RE",bVar"SX",bVar"UX", + Var("statusregister'rst",FTy 9)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),bVar"CU3"), + (EQ(nVar"i",LN 30),bVar"CU2"), + (EQ(nVar"i",LN 29),bVar"CU1"), + (EQ(nVar"i",LN 28),bVar"CU0"), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("statusregister'rst",FTy 9),LN 0)), + (EQ(nVar"i",LN 26),bVar"FR"), + (EQ(nVar"i",LN 25),bVar"RE"), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("statusregister'rst",FTy 9),LN 2)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("statusregister'rst",FTy 9),LN 1)), + (EQ(nVar"i",LN 22),bVar"BEV"), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("statusregister'rst",FTy 9),LN 8)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("statusregister'rst",FTy 9),LN 7)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("statusregister'rst",FTy 9),LN 6)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("statusregister'rst",FTy 9),LN 5)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("statusregister'rst",FTy 9),LN 4)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("statusregister'rst",FTy 9),LN 3)), + (EQ(nVar"i",LN 15),Bop(Bit,Var("IM",F8),LN 7)), + (EQ(nVar"i",LN 14),Bop(Bit,Var("IM",F8),LN 6)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("IM",F8),LN 5)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("IM",F8),LN 4)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("IM",F8),LN 3)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("IM",F8),LN 2)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("IM",F8),LN 1)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("IM",F8),LN 0)), + (EQ(nVar"i",LN 7),bVar"KX"), + (EQ(nVar"i",LN 6),bVar"SX"), + (EQ(nVar"i",LN 5),bVar"UX"), + (EQ(nVar"i",LN 4),Bop(Bit,Var("KSU",FTy 2),LN 1)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("KSU",FTy 2),LN 0)), + (EQ(nVar"i",LN 2),bVar"ERL"), + (EQ(nVar"i",LN 1),bVar"EXL")],bVar"IE")),LW(0,32)))])) +; +val write'rec'StatusRegister_def = Def + ("write'rec'StatusRegister",TP[AVar F32,Var("x",CTy"StatusRegister")], + Call("reg'StatusRegister",F32,Var("x",CTy"StatusRegister"))) +; +val write'reg'StatusRegister_def = Def + ("write'reg'StatusRegister",TP[AVar(CTy"StatusRegister"),Var("x",F32)], + Call("rec'StatusRegister",CTy"StatusRegister",Var("x",F32))) +; +val rec'ConfigRegister_def = Def + ("rec'ConfigRegister",Var("x",F32), + Rec(CTy"ConfigRegister", + [EX(Var("x",F32),LN 12,LN 10,FTy 3), + EX(Var("x",F32),LN 14,LN 13,FTy 2),Bop(Bit,Var("x",F32),LN 15), + EX(Var("x",F32),LN 2,LN 0,FTy 3),Bop(Bit,Var("x",F32),LN 31), + EX(Var("x",F32),LN 9,LN 7,FTy 3), + CC[EX(Var("x",F32),LN 6,LN 3,F4), + EX(Var("x",F32),LN 30,LN 16,FTy 15)]])) +; +val reg'ConfigRegister_def = Def + ("reg'ConfigRegister",Var("x",CTy"ConfigRegister"), + CS(Var("x",CTy"ConfigRegister"), + [(Rec(CTy"ConfigRegister", + [Var("AR",FTy 3),Var("AT",FTy 2),bVar"BE",Var("K0",FTy 3), + bVar"M",Var("MT",FTy 3),Var("configregister'rst",FTy 19)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),bVar"M"), + (EQ(nVar"i",LN 30), + Bop(Bit,Var("configregister'rst",FTy 19),LN 14)), + (EQ(nVar"i",LN 29), + Bop(Bit,Var("configregister'rst",FTy 19),LN 13)), + (EQ(nVar"i",LN 28), + Bop(Bit,Var("configregister'rst",FTy 19),LN 12)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("configregister'rst",FTy 19),LN 11)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("configregister'rst",FTy 19),LN 10)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("configregister'rst",FTy 19),LN 9)), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("configregister'rst",FTy 19),LN 8)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("configregister'rst",FTy 19),LN 7)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("configregister'rst",FTy 19),LN 6)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("configregister'rst",FTy 19),LN 5)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("configregister'rst",FTy 19),LN 4)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("configregister'rst",FTy 19),LN 3)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("configregister'rst",FTy 19),LN 2)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("configregister'rst",FTy 19),LN 1)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("configregister'rst",FTy 19),LN 0)), + (EQ(nVar"i",LN 15),bVar"BE"), + (EQ(nVar"i",LN 14),Bop(Bit,Var("AT",FTy 2),LN 1)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("AT",FTy 2),LN 0)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("AR",FTy 3),LN 2)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("AR",FTy 3),LN 1)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("AR",FTy 3),LN 0)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("MT",FTy 3),LN 2)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("MT",FTy 3),LN 1)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("MT",FTy 3),LN 0)), + (EQ(nVar"i",LN 6), + Bop(Bit,Var("configregister'rst",FTy 19),LN 18)), + (EQ(nVar"i",LN 5), + Bop(Bit,Var("configregister'rst",FTy 19),LN 17)), + (EQ(nVar"i",LN 4), + Bop(Bit,Var("configregister'rst",FTy 19),LN 16)), + (EQ(nVar"i",LN 3), + Bop(Bit,Var("configregister'rst",FTy 19),LN 15)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("K0",FTy 3),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("K0",FTy 3),LN 1))], + Bop(Bit,Var("K0",FTy 3),LN 0))),LW(0,32)))])) +; +val write'rec'ConfigRegister_def = Def + ("write'rec'ConfigRegister",TP[AVar F32,Var("x",CTy"ConfigRegister")], + Call("reg'ConfigRegister",F32,Var("x",CTy"ConfigRegister"))) +; +val write'reg'ConfigRegister_def = Def + ("write'reg'ConfigRegister",TP[AVar(CTy"ConfigRegister"),Var("x",F32)], + Call("rec'ConfigRegister",CTy"ConfigRegister",Var("x",F32))) +; +val rec'ConfigRegister1_def = Def + ("rec'ConfigRegister1",Var("x",F32), + Rec(CTy"ConfigRegister1", + [Bop(Bit,Var("x",F32),LN 6),Bop(Bit,Var("x",F32),LN 2), + EX(Var("x",F32),LN 9,LN 7,FTy 3), + EX(Var("x",F32),LN 12,LN 10,FTy 3), + EX(Var("x",F32),LN 15,LN 13,FTy 3),Bop(Bit,Var("x",F32),LN 1), + Bop(Bit,Var("x",F32),LN 0),EX(Var("x",F32),LN 18,LN 16,FTy 3), + EX(Var("x",F32),LN 21,LN 19,FTy 3), + EX(Var("x",F32),LN 24,LN 22,FTy 3),Bop(Bit,Var("x",F32),LN 31), + Bop(Bit,Var("x",F32),LN 5),EX(Var("x",F32),LN 30,LN 25,FTy 6), + Bop(Bit,Var("x",F32),LN 4),Bop(Bit,Var("x",F32),LN 3)])) +; +val reg'ConfigRegister1_def = Def + ("reg'ConfigRegister1",Var("x",CTy"ConfigRegister1"), + CS(Var("x",CTy"ConfigRegister1"), + [(Rec(CTy"ConfigRegister1", + [bVar"C2",bVar"CA",Var("DA",FTy 3),Var("DL",FTy 3), + Var("DS",FTy 3),bVar"EP",bVar"FP",Var("IA",FTy 3), + Var("IL",FTy 3),Var("IS",FTy 3),bVar"M",bVar"MD", + Var("MMUSize",FTy 6),bVar"PCR",bVar"WR"]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),bVar"M"), + (EQ(nVar"i",LN 30),Bop(Bit,Var("MMUSize",FTy 6),LN 5)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("MMUSize",FTy 6),LN 4)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("MMUSize",FTy 6),LN 3)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("MMUSize",FTy 6),LN 2)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("MMUSize",FTy 6),LN 1)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("MMUSize",FTy 6),LN 0)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("IS",FTy 3),LN 2)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("IS",FTy 3),LN 1)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("IS",FTy 3),LN 0)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("IL",FTy 3),LN 2)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("IL",FTy 3),LN 1)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("IL",FTy 3),LN 0)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("IA",FTy 3),LN 2)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("IA",FTy 3),LN 1)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("IA",FTy 3),LN 0)), + (EQ(nVar"i",LN 15),Bop(Bit,Var("DS",FTy 3),LN 2)), + (EQ(nVar"i",LN 14),Bop(Bit,Var("DS",FTy 3),LN 1)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("DS",FTy 3),LN 0)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("DL",FTy 3),LN 2)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("DL",FTy 3),LN 1)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("DL",FTy 3),LN 0)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("DA",FTy 3),LN 2)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("DA",FTy 3),LN 1)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("DA",FTy 3),LN 0)), + (EQ(nVar"i",LN 6),bVar"C2"), + (EQ(nVar"i",LN 5),bVar"MD"), + (EQ(nVar"i",LN 4),bVar"PCR"), + (EQ(nVar"i",LN 3),bVar"WR"), + (EQ(nVar"i",LN 2),bVar"CA"), + (EQ(nVar"i",LN 1),bVar"EP")],bVar"FP")),LW(0,32)))])) +; +val write'rec'ConfigRegister1_def = Def + ("write'rec'ConfigRegister1",TP[AVar F32,Var("x",CTy"ConfigRegister1")], + Call("reg'ConfigRegister1",F32,Var("x",CTy"ConfigRegister1"))) +; +val write'reg'ConfigRegister1_def = Def + ("write'reg'ConfigRegister1", + TP[AVar(CTy"ConfigRegister1"),Var("x",F32)], + Call("rec'ConfigRegister1",CTy"ConfigRegister1",Var("x",F32))) +; +val rec'ConfigRegister2_def = Def + ("rec'ConfigRegister2",Var("x",F32), + Rec(CTy"ConfigRegister2", + [Bop(Bit,Var("x",F32),LN 31),EX(Var("x",F32),LN 3,LN 0,F4), + EX(Var("x",F32),LN 7,LN 4,F4),EX(Var("x",F32),LN 11,LN 8,F4), + EX(Var("x",F32),LN 15,LN 12,F4),EX(Var("x",F32),LN 19,LN 16,F4), + EX(Var("x",F32),LN 23,LN 20,F4),EX(Var("x",F32),LN 27,LN 24,F4), + EX(Var("x",F32),LN 30,LN 28,FTy 3)])) +; +val reg'ConfigRegister2_def = Def + ("reg'ConfigRegister2",Var("x",CTy"ConfigRegister2"), + CS(Var("x",CTy"ConfigRegister2"), + [(Rec(CTy"ConfigRegister2", + [bVar"M",Var("SA",F4),Var("SL",F4),Var("SS",F4),Var("SU",F4), + Var("TA",F4),Var("TL",F4),Var("TS",F4),Var("TU",FTy 3)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),bVar"M"), + (EQ(nVar"i",LN 30),Bop(Bit,Var("TU",FTy 3),LN 2)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("TU",FTy 3),LN 1)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("TU",FTy 3),LN 0)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("TS",F4),LN 3)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("TS",F4),LN 2)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("TS",F4),LN 1)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("TS",F4),LN 0)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("TL",F4),LN 3)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("TL",F4),LN 2)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("TL",F4),LN 1)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("TL",F4),LN 0)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("TA",F4),LN 3)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("TA",F4),LN 2)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("TA",F4),LN 1)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("TA",F4),LN 0)), + (EQ(nVar"i",LN 15),Bop(Bit,Var("SU",F4),LN 3)), + (EQ(nVar"i",LN 14),Bop(Bit,Var("SU",F4),LN 2)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("SU",F4),LN 1)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("SU",F4),LN 0)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("SS",F4),LN 3)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("SS",F4),LN 2)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("SS",F4),LN 1)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("SS",F4),LN 0)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("SL",F4),LN 3)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("SL",F4),LN 2)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("SL",F4),LN 1)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("SL",F4),LN 0)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("SA",F4),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("SA",F4),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("SA",F4),LN 1))], + Bop(Bit,Var("SA",F4),LN 0))),LW(0,32)))])) +; +val write'rec'ConfigRegister2_def = Def + ("write'rec'ConfigRegister2",TP[AVar F32,Var("x",CTy"ConfigRegister2")], + Call("reg'ConfigRegister2",F32,Var("x",CTy"ConfigRegister2"))) +; +val write'reg'ConfigRegister2_def = Def + ("write'reg'ConfigRegister2", + TP[AVar(CTy"ConfigRegister2"),Var("x",F32)], + Call("rec'ConfigRegister2",CTy"ConfigRegister2",Var("x",F32))) +; +val rec'ConfigRegister3_def = Def + ("rec'ConfigRegister3",Var("x",F32), + Rec(CTy"ConfigRegister3", + [Bop(Bit,Var("x",F32),LN 10),Bop(Bit,Var("x",F32),LN 7), + Bop(Bit,Var("x",F32),LN 31),Bop(Bit,Var("x",F32),LN 2), + Bop(Bit,Var("x",F32),LN 1),Bop(Bit,Var("x",F32),LN 4), + Bop(Bit,Var("x",F32),LN 0),Bop(Bit,Var("x",F32),LN 13), + Bop(Bit,Var("x",F32),LN 6),Bop(Bit,Var("x",F32),LN 5), + CC[EX(Var("x",F32),LN 3,LN 3,F1),EX(Var("x",F32),LN 9,LN 8,FTy 2), + EX(Var("x",F32),LN 12,LN 11,FTy 2), + EX(Var("x",F32),LN 30,LN 14,FTy 17)]])) +; +val reg'ConfigRegister3_def = Def + ("reg'ConfigRegister3",Var("x",CTy"ConfigRegister3"), + CS(Var("x",CTy"ConfigRegister3"), + [(Rec(CTy"ConfigRegister3", + [bVar"DSPP",bVar"LPA",bVar"M",bVar"MT",bVar"SM",bVar"SP", + bVar"TL",bVar"ULRI",bVar"VEIC",bVar"VInt", + Var("configregister3'rst",FTy 22)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),bVar"M"), + (EQ(nVar"i",LN 30), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 16)), + (EQ(nVar"i",LN 29), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 15)), + (EQ(nVar"i",LN 28), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 14)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 13)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 12)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 11)), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 10)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 9)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 8)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 7)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 6)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 5)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 4)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 3)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 2)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 1)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 0)), + (EQ(nVar"i",LN 13),bVar"ULRI"), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 18)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 17)), + (EQ(nVar"i",LN 10),bVar"DSPP"), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 20)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 19)), + (EQ(nVar"i",LN 7),bVar"LPA"), + (EQ(nVar"i",LN 6),bVar"VEIC"), + (EQ(nVar"i",LN 5),bVar"VInt"), + (EQ(nVar"i",LN 4),bVar"SP"), + (EQ(nVar"i",LN 3), + Bop(Bit,Var("configregister3'rst",FTy 22),LN 21)), + (EQ(nVar"i",LN 2),bVar"MT"), + (EQ(nVar"i",LN 1),bVar"SM")],bVar"TL")),LW(0,32)))])) +; +val write'rec'ConfigRegister3_def = Def + ("write'rec'ConfigRegister3",TP[AVar F32,Var("x",CTy"ConfigRegister3")], + Call("reg'ConfigRegister3",F32,Var("x",CTy"ConfigRegister3"))) +; +val write'reg'ConfigRegister3_def = Def + ("write'reg'ConfigRegister3", + TP[AVar(CTy"ConfigRegister3"),Var("x",F32)], + Call("rec'ConfigRegister3",CTy"ConfigRegister3",Var("x",F32))) +; +val rec'ConfigRegister6_def = Def + ("rec'ConfigRegister6",Var("x",F32), + Rec(CTy"ConfigRegister6", + [Bop(Bit,Var("x",F32),LN 2),EX(Var("x",F32),LN 31,LN 16,F16), + CC[EX(Var("x",F32),LN 1,LN 0,FTy 2), + EX(Var("x",F32),LN 15,LN 3,FTy 13)]])) +; +val reg'ConfigRegister6_def = Def + ("reg'ConfigRegister6",Var("x",CTy"ConfigRegister6"), + CS(Var("x",CTy"ConfigRegister6"), + [(Rec(CTy"ConfigRegister6", + [bVar"LTLB",Var("TLBSize",F16), + Var("configregister6'rst",FTy 15)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),Bop(Bit,Var("TLBSize",F16),LN 15)), + (EQ(nVar"i",LN 30),Bop(Bit,Var("TLBSize",F16),LN 14)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("TLBSize",F16),LN 13)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("TLBSize",F16),LN 12)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("TLBSize",F16),LN 11)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("TLBSize",F16),LN 10)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("TLBSize",F16),LN 9)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("TLBSize",F16),LN 8)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("TLBSize",F16),LN 7)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("TLBSize",F16),LN 6)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("TLBSize",F16),LN 5)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("TLBSize",F16),LN 4)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("TLBSize",F16),LN 3)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("TLBSize",F16),LN 2)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("TLBSize",F16),LN 1)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("TLBSize",F16),LN 0)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 12)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 11)), + (EQ(nVar"i",LN 13), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 10)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 9)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 8)), + (EQ(nVar"i",LN 10), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 7)), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 6)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 5)), + (EQ(nVar"i",LN 7), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 4)), + (EQ(nVar"i",LN 6), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 3)), + (EQ(nVar"i",LN 5), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 2)), + (EQ(nVar"i",LN 4), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 1)), + (EQ(nVar"i",LN 3), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 0)), + (EQ(nVar"i",LN 2),bVar"LTLB"), + (EQ(nVar"i",LN 1), + Bop(Bit,Var("configregister6'rst",FTy 15),LN 14))], + Bop(Bit,Var("configregister6'rst",FTy 15),LN 13))), + LW(0,32)))])) +; +val write'rec'ConfigRegister6_def = Def + ("write'rec'ConfigRegister6",TP[AVar F32,Var("x",CTy"ConfigRegister6")], + Call("reg'ConfigRegister6",F32,Var("x",CTy"ConfigRegister6"))) +; +val write'reg'ConfigRegister6_def = Def + ("write'reg'ConfigRegister6", + TP[AVar(CTy"ConfigRegister6"),Var("x",F32)], + Call("rec'ConfigRegister6",CTy"ConfigRegister6",Var("x",F32))) +; +val rec'CauseRegister_def = Def + ("rec'CauseRegister",Var("x",F32), + Rec(CTy"CauseRegister", + [Bop(Bit,Var("x",F32),LN 31),EX(Var("x",F32),LN 29,LN 28,FTy 2), + EX(Var("x",F32),LN 6,LN 2,FTy 5),EX(Var("x",F32),LN 15,LN 8,F8), + Bop(Bit,Var("x",F32),LN 30), + CC[EX(Var("x",F32),LN 1,LN 0,FTy 2),EX(Var("x",F32),LN 7,LN 7,F1), + EX(Var("x",F32),LN 27,LN 16,FTy 12)]])) +; +val reg'CauseRegister_def = Def + ("reg'CauseRegister",Var("x",CTy"CauseRegister"), + CS(Var("x",CTy"CauseRegister"), + [(Rec(CTy"CauseRegister", + [bVar"BD",Var("CE",FTy 2),Var("ExcCode",FTy 5),Var("IP",F8), + bVar"TI",Var("causeregister'rst",FTy 15)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),bVar"BD"), + (EQ(nVar"i",LN 30),bVar"TI"), + (EQ(nVar"i",LN 29),Bop(Bit,Var("CE",FTy 2),LN 1)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("CE",FTy 2),LN 0)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 11)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 10)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 9)), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 8)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 7)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 6)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 5)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 4)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 3)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 2)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 1)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 0)), + (EQ(nVar"i",LN 15),Bop(Bit,Var("IP",F8),LN 7)), + (EQ(nVar"i",LN 14),Bop(Bit,Var("IP",F8),LN 6)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("IP",F8),LN 5)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("IP",F8),LN 4)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("IP",F8),LN 3)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("IP",F8),LN 2)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("IP",F8),LN 1)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("IP",F8),LN 0)), + (EQ(nVar"i",LN 7), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 12)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("ExcCode",FTy 5),LN 4)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("ExcCode",FTy 5),LN 3)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("ExcCode",FTy 5),LN 2)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("ExcCode",FTy 5),LN 1)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("ExcCode",FTy 5),LN 0)), + (EQ(nVar"i",LN 1), + Bop(Bit,Var("causeregister'rst",FTy 15),LN 14))], + Bop(Bit,Var("causeregister'rst",FTy 15),LN 13))), + LW(0,32)))])) +; +val write'rec'CauseRegister_def = Def + ("write'rec'CauseRegister",TP[AVar F32,Var("x",CTy"CauseRegister")], + Call("reg'CauseRegister",F32,Var("x",CTy"CauseRegister"))) +; +val write'reg'CauseRegister_def = Def + ("write'reg'CauseRegister",TP[AVar(CTy"CauseRegister"),Var("x",F32)], + Call("rec'CauseRegister",CTy"CauseRegister",Var("x",F32))) +; +val rec'Context_def = Def + ("rec'Context",Var("x",F64), + Rec(CTy"Context", + [EX(Var("x",F64),LN 22,LN 4,FTy 19), + EX(Var("x",F64),LN 63,LN 23,FTy 41),EX(Var("x",F64),LN 3,LN 0,F4)])) +; +val reg'Context_def = Def + ("reg'Context",Var("x",CTy"Context"), + CS(Var("x",CTy"Context"), + [(Rec(CTy"Context", + [Var("BadVPN2",FTy 19),Var("PTEBase",FTy 41), + Var("context'rst",F4)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 63), + Bop(Bit,Var("PTEBase",FTy 41),LN 40)), + (EQ(nVar"i",LN 62), + Bop(Bit,Var("PTEBase",FTy 41),LN 39)), + (EQ(nVar"i",LN 61), + Bop(Bit,Var("PTEBase",FTy 41),LN 38)), + (EQ(nVar"i",LN 60), + Bop(Bit,Var("PTEBase",FTy 41),LN 37)), + (EQ(nVar"i",LN 59), + Bop(Bit,Var("PTEBase",FTy 41),LN 36)), + (EQ(nVar"i",LN 58), + Bop(Bit,Var("PTEBase",FTy 41),LN 35)), + (EQ(nVar"i",LN 57), + Bop(Bit,Var("PTEBase",FTy 41),LN 34)), + (EQ(nVar"i",LN 56), + Bop(Bit,Var("PTEBase",FTy 41),LN 33)), + (EQ(nVar"i",LN 55), + Bop(Bit,Var("PTEBase",FTy 41),LN 32)), + (EQ(nVar"i",LN 54), + Bop(Bit,Var("PTEBase",FTy 41),LN 31)), + (EQ(nVar"i",LN 53), + Bop(Bit,Var("PTEBase",FTy 41),LN 30)), + (EQ(nVar"i",LN 52), + Bop(Bit,Var("PTEBase",FTy 41),LN 29)), + (EQ(nVar"i",LN 51), + Bop(Bit,Var("PTEBase",FTy 41),LN 28)), + (EQ(nVar"i",LN 50), + Bop(Bit,Var("PTEBase",FTy 41),LN 27)), + (EQ(nVar"i",LN 49), + Bop(Bit,Var("PTEBase",FTy 41),LN 26)), + (EQ(nVar"i",LN 48), + Bop(Bit,Var("PTEBase",FTy 41),LN 25)), + (EQ(nVar"i",LN 47), + Bop(Bit,Var("PTEBase",FTy 41),LN 24)), + (EQ(nVar"i",LN 46), + Bop(Bit,Var("PTEBase",FTy 41),LN 23)), + (EQ(nVar"i",LN 45), + Bop(Bit,Var("PTEBase",FTy 41),LN 22)), + (EQ(nVar"i",LN 44), + Bop(Bit,Var("PTEBase",FTy 41),LN 21)), + (EQ(nVar"i",LN 43), + Bop(Bit,Var("PTEBase",FTy 41),LN 20)), + (EQ(nVar"i",LN 42), + Bop(Bit,Var("PTEBase",FTy 41),LN 19)), + (EQ(nVar"i",LN 41), + Bop(Bit,Var("PTEBase",FTy 41),LN 18)), + (EQ(nVar"i",LN 40), + Bop(Bit,Var("PTEBase",FTy 41),LN 17)), + (EQ(nVar"i",LN 39), + Bop(Bit,Var("PTEBase",FTy 41),LN 16)), + (EQ(nVar"i",LN 38), + Bop(Bit,Var("PTEBase",FTy 41),LN 15)), + (EQ(nVar"i",LN 37), + Bop(Bit,Var("PTEBase",FTy 41),LN 14)), + (EQ(nVar"i",LN 36), + Bop(Bit,Var("PTEBase",FTy 41),LN 13)), + (EQ(nVar"i",LN 35), + Bop(Bit,Var("PTEBase",FTy 41),LN 12)), + (EQ(nVar"i",LN 34), + Bop(Bit,Var("PTEBase",FTy 41),LN 11)), + (EQ(nVar"i",LN 33), + Bop(Bit,Var("PTEBase",FTy 41),LN 10)), + (EQ(nVar"i",LN 32),Bop(Bit,Var("PTEBase",FTy 41),LN 9)), + (EQ(nVar"i",LN 31),Bop(Bit,Var("PTEBase",FTy 41),LN 8)), + (EQ(nVar"i",LN 30),Bop(Bit,Var("PTEBase",FTy 41),LN 7)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("PTEBase",FTy 41),LN 6)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("PTEBase",FTy 41),LN 5)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("PTEBase",FTy 41),LN 4)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("PTEBase",FTy 41),LN 3)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("PTEBase",FTy 41),LN 2)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("PTEBase",FTy 41),LN 1)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("PTEBase",FTy 41),LN 0)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("BadVPN2",FTy 19),LN 18)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("BadVPN2",FTy 19),LN 17)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("BadVPN2",FTy 19),LN 16)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("BadVPN2",FTy 19),LN 15)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("BadVPN2",FTy 19),LN 14)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("BadVPN2",FTy 19),LN 13)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("BadVPN2",FTy 19),LN 12)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("BadVPN2",FTy 19),LN 11)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("BadVPN2",FTy 19),LN 10)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("BadVPN2",FTy 19),LN 9)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("BadVPN2",FTy 19),LN 8)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("BadVPN2",FTy 19),LN 7)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("BadVPN2",FTy 19),LN 6)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("BadVPN2",FTy 19),LN 5)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("BadVPN2",FTy 19),LN 4)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("BadVPN2",FTy 19),LN 3)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("BadVPN2",FTy 19),LN 2)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("BadVPN2",FTy 19),LN 1)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("BadVPN2",FTy 19),LN 0)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("context'rst",F4),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("context'rst",F4),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("context'rst",F4),LN 1))], + Bop(Bit,Var("context'rst",F4),LN 0))),LW(0,64)))])) +; +val write'rec'Context_def = Def + ("write'rec'Context",TP[AVar F64,Var("x",CTy"Context")], + Call("reg'Context",F64,Var("x",CTy"Context"))) +; +val write'reg'Context_def = Def + ("write'reg'Context",TP[AVar(CTy"Context"),Var("x",F64)], + Call("rec'Context",CTy"Context",Var("x",F64))) +; +val rec'XContext_def = Def + ("rec'XContext",Var("x",F64), + Rec(CTy"XContext", + [EX(Var("x",F64),LN 30,LN 4,FTy 27), + EX(Var("x",F64),LN 63,LN 33,FTy 31), + EX(Var("x",F64),LN 32,LN 31,FTy 2),EX(Var("x",F64),LN 3,LN 0,F4)])) +; +val reg'XContext_def = Def + ("reg'XContext",Var("x",CTy"XContext"), + CS(Var("x",CTy"XContext"), + [(Rec(CTy"XContext", + [Var("BadVPN2",FTy 27),Var("PTEBase",FTy 31),Var("R",FTy 2), + Var("xcontext'rst",F4)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 63), + Bop(Bit,Var("PTEBase",FTy 31),LN 30)), + (EQ(nVar"i",LN 62), + Bop(Bit,Var("PTEBase",FTy 31),LN 29)), + (EQ(nVar"i",LN 61), + Bop(Bit,Var("PTEBase",FTy 31),LN 28)), + (EQ(nVar"i",LN 60), + Bop(Bit,Var("PTEBase",FTy 31),LN 27)), + (EQ(nVar"i",LN 59), + Bop(Bit,Var("PTEBase",FTy 31),LN 26)), + (EQ(nVar"i",LN 58), + Bop(Bit,Var("PTEBase",FTy 31),LN 25)), + (EQ(nVar"i",LN 57), + Bop(Bit,Var("PTEBase",FTy 31),LN 24)), + (EQ(nVar"i",LN 56), + Bop(Bit,Var("PTEBase",FTy 31),LN 23)), + (EQ(nVar"i",LN 55), + Bop(Bit,Var("PTEBase",FTy 31),LN 22)), + (EQ(nVar"i",LN 54), + Bop(Bit,Var("PTEBase",FTy 31),LN 21)), + (EQ(nVar"i",LN 53), + Bop(Bit,Var("PTEBase",FTy 31),LN 20)), + (EQ(nVar"i",LN 52), + Bop(Bit,Var("PTEBase",FTy 31),LN 19)), + (EQ(nVar"i",LN 51), + Bop(Bit,Var("PTEBase",FTy 31),LN 18)), + (EQ(nVar"i",LN 50), + Bop(Bit,Var("PTEBase",FTy 31),LN 17)), + (EQ(nVar"i",LN 49), + Bop(Bit,Var("PTEBase",FTy 31),LN 16)), + (EQ(nVar"i",LN 48), + Bop(Bit,Var("PTEBase",FTy 31),LN 15)), + (EQ(nVar"i",LN 47), + Bop(Bit,Var("PTEBase",FTy 31),LN 14)), + (EQ(nVar"i",LN 46), + Bop(Bit,Var("PTEBase",FTy 31),LN 13)), + (EQ(nVar"i",LN 45), + Bop(Bit,Var("PTEBase",FTy 31),LN 12)), + (EQ(nVar"i",LN 44), + Bop(Bit,Var("PTEBase",FTy 31),LN 11)), + (EQ(nVar"i",LN 43), + Bop(Bit,Var("PTEBase",FTy 31),LN 10)), + (EQ(nVar"i",LN 42),Bop(Bit,Var("PTEBase",FTy 31),LN 9)), + (EQ(nVar"i",LN 41),Bop(Bit,Var("PTEBase",FTy 31),LN 8)), + (EQ(nVar"i",LN 40),Bop(Bit,Var("PTEBase",FTy 31),LN 7)), + (EQ(nVar"i",LN 39),Bop(Bit,Var("PTEBase",FTy 31),LN 6)), + (EQ(nVar"i",LN 38),Bop(Bit,Var("PTEBase",FTy 31),LN 5)), + (EQ(nVar"i",LN 37),Bop(Bit,Var("PTEBase",FTy 31),LN 4)), + (EQ(nVar"i",LN 36),Bop(Bit,Var("PTEBase",FTy 31),LN 3)), + (EQ(nVar"i",LN 35),Bop(Bit,Var("PTEBase",FTy 31),LN 2)), + (EQ(nVar"i",LN 34),Bop(Bit,Var("PTEBase",FTy 31),LN 1)), + (EQ(nVar"i",LN 33),Bop(Bit,Var("PTEBase",FTy 31),LN 0)), + (EQ(nVar"i",LN 32),Bop(Bit,Var("R",FTy 2),LN 1)), + (EQ(nVar"i",LN 31),Bop(Bit,Var("R",FTy 2),LN 0)), + (EQ(nVar"i",LN 30), + Bop(Bit,Var("BadVPN2",FTy 27),LN 26)), + (EQ(nVar"i",LN 29), + Bop(Bit,Var("BadVPN2",FTy 27),LN 25)), + (EQ(nVar"i",LN 28), + Bop(Bit,Var("BadVPN2",FTy 27),LN 24)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("BadVPN2",FTy 27),LN 23)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("BadVPN2",FTy 27),LN 22)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("BadVPN2",FTy 27),LN 21)), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("BadVPN2",FTy 27),LN 20)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("BadVPN2",FTy 27),LN 19)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("BadVPN2",FTy 27),LN 18)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("BadVPN2",FTy 27),LN 17)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("BadVPN2",FTy 27),LN 16)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("BadVPN2",FTy 27),LN 15)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("BadVPN2",FTy 27),LN 14)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("BadVPN2",FTy 27),LN 13)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("BadVPN2",FTy 27),LN 12)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("BadVPN2",FTy 27),LN 11)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("BadVPN2",FTy 27),LN 10)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("BadVPN2",FTy 27),LN 9)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("BadVPN2",FTy 27),LN 8)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("BadVPN2",FTy 27),LN 7)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("BadVPN2",FTy 27),LN 6)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("BadVPN2",FTy 27),LN 5)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("BadVPN2",FTy 27),LN 4)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("BadVPN2",FTy 27),LN 3)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("BadVPN2",FTy 27),LN 2)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("BadVPN2",FTy 27),LN 1)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("BadVPN2",FTy 27),LN 0)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("xcontext'rst",F4),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("xcontext'rst",F4),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("xcontext'rst",F4),LN 1))], + Bop(Bit,Var("xcontext'rst",F4),LN 0))),LW(0,64)))])) +; +val write'rec'XContext_def = Def + ("write'rec'XContext",TP[AVar F64,Var("x",CTy"XContext")], + Call("reg'XContext",F64,Var("x",CTy"XContext"))) +; +val write'reg'XContext_def = Def + ("write'reg'XContext",TP[AVar(CTy"XContext"),Var("x",F64)], + Call("rec'XContext",CTy"XContext",Var("x",F64))) +; +val rec'HWREna_def = Def + ("rec'HWREna",Var("x",F32), + Rec(CTy"HWREna", + [Bop(Bit,Var("x",F32),LN 2),Bop(Bit,Var("x",F32),LN 3), + Bop(Bit,Var("x",F32),LN 0),Bop(Bit,Var("x",F32),LN 29), + CC[EX(Var("x",F32),LN 1,LN 1,F1), + EX(Var("x",F32),LN 28,LN 4,FTy 25), + EX(Var("x",F32),LN 31,LN 30,FTy 2)]])) +; +val reg'HWREna_def = Def + ("reg'HWREna",Var("x",CTy"HWREna"), + CS(Var("x",CTy"HWREna"), + [(Rec(CTy"HWREna", + [bVar"CC",bVar"CCRes",bVar"CPUNum",bVar"UL", + Var("hwrena'rst",FTy 28)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 1)), + (EQ(nVar"i",LN 30), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 0)), + (EQ(nVar"i",LN 29),bVar"UL"), + (EQ(nVar"i",LN 28), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 26)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 25)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 24)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 23)), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 22)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 21)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 20)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 19)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 18)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 17)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 16)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 15)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 14)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 13)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 12)), + (EQ(nVar"i",LN 13), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 11)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 10)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 9)), + (EQ(nVar"i",LN 10), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 8)), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 7)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 6)), + (EQ(nVar"i",LN 7), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 5)), + (EQ(nVar"i",LN 6), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 4)), + (EQ(nVar"i",LN 5), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 3)), + (EQ(nVar"i",LN 4), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 2)), + (EQ(nVar"i",LN 3),bVar"CCRes"), + (EQ(nVar"i",LN 2),bVar"CC"), + (EQ(nVar"i",LN 1), + Bop(Bit,Var("hwrena'rst",FTy 28),LN 27))], + bVar"CPUNum")),LW(0,32)))])) +; +val write'rec'HWREna_def = Def + ("write'rec'HWREna",TP[AVar F32,Var("x",CTy"HWREna")], + Call("reg'HWREna",F32,Var("x",CTy"HWREna"))) +; +val write'reg'HWREna_def = Def + ("write'reg'HWREna",TP[AVar(CTy"HWREna"),Var("x",F32)], + Call("rec'HWREna",CTy"HWREna",Var("x",F32))) +; +val BYTE_def = Def0 ("BYTE",LW(0,3)) +; +val HALFWORD_def = Def0 ("HALFWORD",LW(1,3)) +; +val WORD_def = Def0 ("WORD",LW(3,3)) +; +val DOUBLEWORD_def = Def0 ("DOUBLEWORD",LW(7,3)) +; +val gpr_def = Def + ("gpr",Var("n",FTy 5), + Close + (qVar"state", + TP[Apply + (Apply + (Dest("c_gpr",ATy(F8,ATy(FTy 5,F64)),qVar"state"), + Dest("procID",F8,qVar"state")),Var("n",FTy 5)),qVar"state"])) +; +val write'gpr_def = Def + ("write'gpr",TP[Var("value",F64),Var("n",FTy 5)], + Close + (qVar"state", + TP[LU, + Let(Var("s",PTy(ATy(FTy 5,F64),qTy)), + TP[Fupd + (Apply + (Dest("c_gpr",ATy(F8,ATy(FTy 5,F64)),qVar"state"), + Dest("procID",F8,qVar"state")),Var("n",FTy 5), + Var("value",F64)),qVar"state"], + Rupd + ("c_gpr", + TP[Mop(Snd,Var("s",PTy(ATy(FTy 5,F64),qTy))), + Fupd + (Dest + ("c_gpr",ATy(F8,ATy(FTy 5,F64)), + Mop(Snd,Var("s",PTy(ATy(FTy 5,F64),qTy)))), + Dest + ("procID",F8, + Mop(Snd,Var("s",PTy(ATy(FTy 5,F64),qTy)))), + Mop(Fst,Var("s",PTy(ATy(FTy 5,F64),qTy))))]))])) +; +val PC_def = Def + ("PC",qVar"state", + TP[Apply + (Dest("c_PC",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'PC_def = Def + ("write'PC",Var("value",F64), + Close + (qVar"state", + TP[LU, + Rupd + ("c_PC", + TP[qVar"state", + Fupd + (Dest("c_PC",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",F64))])])) +; +val hi_def = Def + ("hi",qVar"state", + TP[Apply + (Dest("c_hi",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'hi_def = Def + ("write'hi",Var("value",OTy F64), + Close + (qVar"state", + TP[LU, + Rupd + ("c_hi", + TP[qVar"state", + Fupd + (Dest("c_hi",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",OTy F64))])])) +; +val lo_def = Def + ("lo",qVar"state", + TP[Apply + (Dest("c_lo",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'lo_def = Def + ("write'lo",Var("value",OTy F64), + Close + (qVar"state", + TP[LU, + Rupd + ("c_lo", + TP[qVar"state", + Fupd + (Dest("c_lo",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",OTy F64))])])) +; +val CP0_def = Def + ("CP0",qVar"state", + TP[Apply + (Dest("c_CP0",ATy(F8,CTy"CP0__renamed__"),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'CP0_def = Def + ("write'CP0",Var("value",CTy"CP0__renamed__"), + Close + (qVar"state", + TP[LU, + Rupd + ("c_CP0", + TP[qVar"state", + Fupd + (Dest("c_CP0",ATy(F8,CTy"CP0__renamed__"),qVar"state"), + Dest("procID",F8,qVar"state"), + Var("value",CTy"CP0__renamed__"))])])) +; +val BranchDelay_def = Def + ("BranchDelay",qVar"state", + TP[Apply + (Dest("c_BranchDelay",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'BranchDelay_def = Def + ("write'BranchDelay",Var("value",OTy F64), + Close + (qVar"state", + TP[LU, + Rupd + ("c_BranchDelay", + TP[qVar"state", + Fupd + (Dest("c_BranchDelay",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",OTy F64))])])) +; +val BranchTo_def = Def + ("BranchTo",qVar"state", + TP[Apply + (Dest("c_BranchTo",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'BranchTo_def = Def + ("write'BranchTo",Var("value",OTy F64), + Close + (qVar"state", + TP[LU, + Rupd + ("c_BranchTo", + TP[qVar"state", + Fupd + (Dest("c_BranchTo",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",OTy F64))])])) +; +val LLbit_def = Def + ("LLbit",qVar"state", + TP[Apply + (Dest("c_LLbit",ATy(F8,OTy bTy),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'LLbit_def = Def + ("write'LLbit",Var("value",OTy bTy), + Close + (qVar"state", + TP[LU, + Rupd + ("c_LLbit", + TP[qVar"state", + Fupd + (Dest("c_LLbit",ATy(F8,OTy bTy),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",OTy bTy))])])) +; +val exceptionSignalled_def = Def + ("exceptionSignalled",qVar"state", + TP[Apply + (Dest("c_exceptionSignalled",ATy(F8,bTy),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'exceptionSignalled_def = Def + ("write'exceptionSignalled",bVar"value", + Close + (qVar"state", + TP[LU, + Rupd + ("c_exceptionSignalled", + TP[qVar"state", + Fupd + (Dest("c_exceptionSignalled",ATy(F8,bTy),qVar"state"), + Dest("procID",F8,qVar"state"),bVar"value")])])) +; +val UserMode_def = Def + ("UserMode",qVar"state", + TP[Bop(And, + EQ(Dest + ("KSU",FTy 2, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),LW(2,2)), + Mop(Not, + Bop(Or, + Dest + ("EXL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Dest + ("ERL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))))),qVar"state"]) +; +val SupervisorMode_def = Def + ("SupervisorMode",qVar"state", + TP[Bop(And, + EQ(Dest + ("KSU",FTy 2, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),LW(1,2)), + Mop(Not, + Bop(Or, + Dest + ("EXL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Dest + ("ERL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))))),qVar"state"]) +; +val KernelMode_def = Def + ("KernelMode",qVar"state", + TP[Bop(Or, + Bop(Or, + EQ(Dest + ("KSU",FTy 2, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),LW(0,2)), + Dest + ("EXL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Dest + ("ERL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]) +; +val BigEndianMem_def = Def + ("BigEndianMem",qVar"state", + TP[Dest + ("BE",bTy, + Dest + ("Config",CTy"ConfigRegister", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]) +; +val ReverseEndian_def = Def + ("ReverseEndian",qVar"state", + TP[Mop(Cast F1, + Bop(And, + Dest + ("RE",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Mop(Fst, + Apply + (Const("UserMode",ATy(qTy,PTy(bTy,qTy))),qVar"state")))), + qVar"state"]) +; +val BigEndianCPU_def = Def + ("BigEndianCPU",qVar"state", + TP[Bop(BXor, + Mop(Cast F1, + Mop(Fst, + Apply + (Const("BigEndianMem",ATy(qTy,PTy(bTy,qTy))), + qVar"state"))), + Mop(Fst, + Apply + (Const("ReverseEndian",ATy(qTy,PTy(F1,qTy))),qVar"state"))), + qVar"state"]) +; +val NotWordValue_def = Def + ("NotWordValue",Var("value",F64), + Let(Var("top",F32),EX(Var("value",F64),LN 63,LN 32,F32), + ITE(Bop(Bit,Var("value",F64),LN 31), + Mop(Not,EQ(Var("top",F32),LW(4294967295,32))), + Mop(Not,EQ(Var("top",F32),LW(0,32)))))) +; +val CheckBranch_def = Def + ("CheckBranch",qVar"state", + ITE(Mop(IsSome, + Mop(Fst, + Apply + (Const("BranchDelay",ATy(qTy,PTy(OTy F64,qTy))), + qVar"state"))), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"Not permitted in delay slot")),qVar"state"), + TP[LU,qVar"state"])) +; +val cpr_def = Def + ("cpr",Var("r",FTy 5), + CC[LS"c0_", + CS(Var("r",FTy 5), + [(LW(0,5),LS"index"),(LW(1,5),LS"random"),(LW(2,5),LS"entrylo0"), + (LW(3,5),LS"entrylo1"),(LW(4,5),LS"context"), + (LW(5,5),LS"pagemask"),(LW(6,5),LS"wired"),(LW(7,5),LS"hwrena"), + (LW(8,5),LS"badvaddr"),(LW(9,5),LS"count"), + (LW(10,5),LS"entryhi"),(LW(11,5),LS"compare"), + (LW(12,5),LS"status"),(LW(13,5),LS"cause"),(LW(14,5),LS"epc"), + (LW(15,5),LS"prid"),(LW(16,5),LS"config"),(LW(17,5),LS"lladdr"), + (LW(18,5),LS"watchlo"),(LW(19,5),LS"watchhi"), + (LW(20,5),LS"xcontext"),(LW(21,5),LS"21"),(LW(22,5),LS"22"), + (LW(23,5),LS"debug"),(LW(24,5),LS"depc"),(LW(25,5),LS"perfcnt"), + (LW(26,5),LS"errctl"),(LW(27,5),LS"cacheerr"), + (LW(28,5),LS"taglo"),(LW(29,5),LS"taghi"), + (LW(30,5),LS"errorepc"),(LW(31,5),LS"kscratch")])]) +; +val log_sig_exception_def = Def + ("log_sig_exception",Var("ExceptionCode",FTy 5), + CC[LS"Exception 0x", + Mop(PadLeft, + TP[LSC #"0",LN 2,Mop(Cast sTy,Var("ExceptionCode",FTy 5))])]) +; +val log_w_gpr_def = Def + ("log_w_gpr",TP[Var("r",FTy 5),Var("data",F64)], + CC[LS"Reg ",Mop(Cast sTy,Mop(Cast nTy,Var("r",FTy 5))),LS" <- 0x", + Mop(PadLeft,TP[LSC #"0",LN 16,Mop(Cast sTy,Var("data",F64))])]) +; +val log_w_hi_def = Def + ("log_w_hi",Var("data",F64), + CC[LS"HI <- 0x", + Mop(PadLeft,TP[LSC #"0",LN 16,Mop(Cast sTy,Var("data",F64))])]) +; +val log_w_lo_def = Def + ("log_w_lo",Var("data",F64), + CC[LS"LO <- 0x", + Mop(PadLeft,TP[LSC #"0",LN 16,Mop(Cast sTy,Var("data",F64))])]) +; +val log_w_c0_def = Def + ("log_w_c0",TP[Var("r",FTy 5),Var("data",F64)], + CC[Call("cpr",sTy,Var("r",FTy 5)),LS" <- 0x", + Mop(PadLeft,TP[LSC #"0",LN 16,Mop(Cast sTy,Var("data",F64))])]) +; +val log_w_mem_def = Def + ("log_w_mem",TP[Var("addr",FTy 37),Var("mask",F64),Var("data",F64)], + CC[LS"MEM[0x", + Mop(PadLeft,TP[LSC #"0",LN 10,Mop(Cast sTy,Var("addr",FTy 37))]), + LS"] <- (data: 0x", + Mop(PadLeft,TP[LSC #"0",LN 16,Mop(Cast sTy,Var("data",F64))]), + LS", mask: 0x", + Mop(PadLeft,TP[LSC #"0",LN 16,Mop(Cast sTy,Var("mask",F64))]),LS")"]) +; +val log_r_mem_def = Def + ("log_r_mem",TP[Var("addr",FTy 37),Var("data",F64)], + CC[LS"data <- MEM[0x", + Mop(PadLeft,TP[LSC #"0",LN 10,Mop(Cast sTy,Var("addr",FTy 37))]), + LS"]: 0x", + Mop(PadLeft,TP[LSC #"0",LN 16,Mop(Cast sTy,Var("data",F64))])]) +; +val mark_log_def = Def + ("mark_log",TP[nVar"lvl",sVar"s"], + Close + (qVar"state", + TP[LU, + Rupd + ("log", + TP[qVar"state", + Fupd + (Dest("log",ATy(nTy,LTy sTy),qVar"state"),nVar"lvl", + LLC([sVar"s"], + Apply + (Dest("log",ATy(nTy,LTy sTy),qVar"state"), + nVar"lvl")))])])) +; +val unmark_log_def = Def + ("unmark_log",nVar"lvl", + Close + (qVar"state", + TP[LU, + Rupd + ("log", + TP[qVar"state", + Fupd + (Dest("log",ATy(nTy,LTy sTy),qVar"state"),nVar"lvl", + Mop(Tail, + Apply + (Dest("log",ATy(nTy,LTy sTy),qVar"state"), + nVar"lvl")))])])) +; +val clear_logs_def = Def + ("clear_logs",AVar uTy, + Close + (qVar"state", + Apply + (For(TP[LN 0,LN 5, + Close + (nVar"i", + Close + (qVar"state", + TP[LU, + Rupd + ("log", + TP[qVar"state", + Fupd + (Dest("log",ATy(nTy,LTy sTy),qVar"state"), + nVar"i",LNL sTy)])]))]),qVar"state"))) +; +val hex32_def = Def + ("hex32",Var("x",F32), + Mop(PadLeft,TP[LSC #"0",LN 8,Mop(Cast sTy,Var("x",F32))])) +; +val hex64_def = Def + ("hex64",Var("x",F64), + Mop(PadLeft,TP[LSC #"0",LN 16,Mop(Cast sTy,Var("x",F64))])) +; +val rec'PIC_Config_Reg_def = Def + ("rec'PIC_Config_Reg",Var("x",F64), + Rec(CTy"PIC_Config_Reg", + [Bop(Bit,Var("x",F64),LN 31),EX(Var("x",F64),LN 2,LN 0,FTy 3), + CC[EX(Var("x",F64),LN 30,LN 3,FTy 28), + EX(Var("x",F64),LN 63,LN 32,F32)]])) +; +val reg'PIC_Config_Reg_def = Def + ("reg'PIC_Config_Reg",Var("x",CTy"PIC_Config_Reg"), + CS(Var("x",CTy"PIC_Config_Reg"), + [(Rec(CTy"PIC_Config_Reg", + [bVar"EN",Var("IRQ",FTy 3),Var("pic_config_reg'rst",FTy 60)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 63), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 31)), + (EQ(nVar"i",LN 62), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 30)), + (EQ(nVar"i",LN 61), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 29)), + (EQ(nVar"i",LN 60), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 28)), + (EQ(nVar"i",LN 59), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 27)), + (EQ(nVar"i",LN 58), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 26)), + (EQ(nVar"i",LN 57), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 25)), + (EQ(nVar"i",LN 56), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 24)), + (EQ(nVar"i",LN 55), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 23)), + (EQ(nVar"i",LN 54), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 22)), + (EQ(nVar"i",LN 53), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 21)), + (EQ(nVar"i",LN 52), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 20)), + (EQ(nVar"i",LN 51), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 19)), + (EQ(nVar"i",LN 50), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 18)), + (EQ(nVar"i",LN 49), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 17)), + (EQ(nVar"i",LN 48), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 16)), + (EQ(nVar"i",LN 47), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 15)), + (EQ(nVar"i",LN 46), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 14)), + (EQ(nVar"i",LN 45), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 13)), + (EQ(nVar"i",LN 44), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 12)), + (EQ(nVar"i",LN 43), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 11)), + (EQ(nVar"i",LN 42), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 10)), + (EQ(nVar"i",LN 41), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 9)), + (EQ(nVar"i",LN 40), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 8)), + (EQ(nVar"i",LN 39), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 7)), + (EQ(nVar"i",LN 38), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 6)), + (EQ(nVar"i",LN 37), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 5)), + (EQ(nVar"i",LN 36), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 4)), + (EQ(nVar"i",LN 35), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 3)), + (EQ(nVar"i",LN 34), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 2)), + (EQ(nVar"i",LN 33), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 1)), + (EQ(nVar"i",LN 32), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 0)), + (EQ(nVar"i",LN 31),bVar"EN"), + (EQ(nVar"i",LN 30), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 59)), + (EQ(nVar"i",LN 29), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 58)), + (EQ(nVar"i",LN 28), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 57)), + (EQ(nVar"i",LN 27), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 56)), + (EQ(nVar"i",LN 26), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 55)), + (EQ(nVar"i",LN 25), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 54)), + (EQ(nVar"i",LN 24), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 53)), + (EQ(nVar"i",LN 23), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 52)), + (EQ(nVar"i",LN 22), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 51)), + (EQ(nVar"i",LN 21), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 50)), + (EQ(nVar"i",LN 20), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 49)), + (EQ(nVar"i",LN 19), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 48)), + (EQ(nVar"i",LN 18), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 47)), + (EQ(nVar"i",LN 17), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 46)), + (EQ(nVar"i",LN 16), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 45)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 44)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 43)), + (EQ(nVar"i",LN 13), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 42)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 41)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 40)), + (EQ(nVar"i",LN 10), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 39)), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 38)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 37)), + (EQ(nVar"i",LN 7), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 36)), + (EQ(nVar"i",LN 6), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 35)), + (EQ(nVar"i",LN 5), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 34)), + (EQ(nVar"i",LN 4), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 33)), + (EQ(nVar"i",LN 3), + Bop(Bit,Var("pic_config_reg'rst",FTy 60),LN 32)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("IRQ",FTy 3),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("IRQ",FTy 3),LN 1))], + Bop(Bit,Var("IRQ",FTy 3),LN 0))),LW(0,64)))])) +; +val write'rec'PIC_Config_Reg_def = Def + ("write'rec'PIC_Config_Reg",TP[AVar F64,Var("x",CTy"PIC_Config_Reg")], + Call("reg'PIC_Config_Reg",F64,Var("x",CTy"PIC_Config_Reg"))) +; +val write'reg'PIC_Config_Reg_def = Def + ("write'reg'PIC_Config_Reg",TP[AVar(CTy"PIC_Config_Reg"),Var("x",F64)], + Call("rec'PIC_Config_Reg",CTy"PIC_Config_Reg",Var("x",F64))) +; +val PIC_update_def = Def + ("PIC_update",Var("id",F8), + Close + (qVar"state", + Let(Var("v",FTy 128), + Mop(Cast(FTy 128), + Apply + (Dest("PIC_external_intrs",ATy(F8,F64),qVar"state"), + Var("id",F8))), + TP[LU, + Let(Var("s0",PTy(F8,qTy)),TP[LW(0,8),qVar"state"], + Let(Var("s",PTy(F8,qTy)), + ITE(Bop(Or, + Mop(Not, + EQ(Apply + (Dest + ("PIC_ip_bits",ATy(F8,FTy 128), + Mop(Snd,Var("s0",PTy(F8,qTy)))), + Var("id",F8)),LW(0,128))), + Mop(Not,EQ(Var("v",FTy 128),LW(0,128)))), + Mop(Snd, + Apply + (For(TP[LN 0,LN 127, + Close + (nVar"i", + Close + (Var("state0",PTy(F8,qTy)), + ITE(Bop(Or, + Bop(Bit, + Apply + (Dest + ("PIC_ip_bits", + ATy(F8, + FTy 128), + Mop(Snd, + Var("state0", + PTy(F8, + qTy)))), + Var("id",F8)), + nVar"i"), + Bop(Bit, + Var("v",FTy 128), + nVar"i")), + Let(Var("reg", + CTy"PIC_Config_Reg"), + Apply + (Apply + (Dest + ("PIC_config_regs", + ATy(F8, + ATy(FTy 7, + CTy"PIC_Config_Reg")), + qVar"state"), + Var("id",F8)), + Mop(Cast(FTy 7), + nVar"i")), + Let(nVar"i", + Mop(Cast nTy, + Dest + ("IRQ", + FTy 3, + Var("reg", + CTy"PIC_Config_Reg"))), + TP[LU, + BFI(nVar"i", + nVar"i", + Mop(Cast + F1, + Bop(Or, + Bop(Bit, + Mop(Fst, + Var("state0", + PTy(F8, + qTy))), + Mop(Cast + nTy, + Dest + ("IRQ", + FTy 3, + Var("reg", + CTy"PIC_Config_Reg")))), + Dest + ("EN", + bTy, + Var("reg", + CTy"PIC_Config_Reg")))), + Mop(Fst, + Var("state0", + PTy(F8, + qTy)))), + Mop(Snd, + Var("state0", + PTy(F8, + qTy)))])), + TP[LU, + Var("state0", + PTy(F8,qTy))])))]), + Var("s0",PTy(F8,qTy)))), + Var("s0",PTy(F8,qTy))), + Let(Var("v",CTy"CP0__renamed__"), + Apply + (Dest + ("c_CP0",ATy(F8,CTy"CP0__renamed__"), + Mop(Snd,Var("s",PTy(F8,qTy)))),Var("id",F8)), + Let(Var("x1",CTy"CauseRegister"), + Dest + ("Cause",CTy"CauseRegister", + Var("v",CTy"CP0__renamed__")), + Rupd + ("c_CP0", + TP[Mop(Snd,Var("s",PTy(F8,qTy))), + Fupd + (Dest + ("c_CP0", + ATy(F8,CTy"CP0__renamed__"), + Mop(Snd,Var("s",PTy(F8,qTy)))), + Var("id",F8), + Rupd + ("Cause", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("IP", + TP[Var("x1", + CTy"CauseRegister"), + BFI(LN 6,LN 2, + EX(Mop(Fst, + Var("s", + PTy(F8, + qTy))), + LN 4,LN 0,FTy 5), + Dest + ("IP",F8, + Var("x1", + CTy"CauseRegister")))])]))])))))]))) +; +val PIC_initialise_def = Def + ("PIC_initialise",nVar"pic", + Close + (qVar"state", + Let(Var("v",F8),Dest("procID",F8,qVar"state"), + Let(qVar"s", + Rupd + ("PIC_base_address", + TP[qVar"state", + Fupd + (Dest("PIC_base_address",ATy(F8,FTy 37),qVar"state"), + Var("v",F8), + Mop(Cast(FTy 37), + Bop(Lsr,Mop(Cast(FTy 40),nVar"pic"),LN 3)))]), + TP[LU, + Let(Var("s",PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy)), + Mop(Snd, + Apply + (For(TP[LN 0,LN 4, + Close + (nVar"i", + Close + (Var("state", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)), + Let(Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)), + Let(Var("x",FTy 7), + Mop(Cast(FTy 7),nVar"i"), + TP[Fupd + (Mop(Fst, + Var("state", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Var("x",FTy 7), + Rupd + ("EN", + TP[Apply + (Mop(Fst, + Var("state", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Var("x", + FTy 7)), + LT])), + Mop(Snd, + Var("state", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))]), + Let(Var("x",FTy 7), + Mop(Cast(FTy 7),nVar"i"), + TP[LU, + Fupd + (Mop(Fst, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Var("x",FTy 7), + Rupd + ("IRQ", + TP[Apply + (Mop(Fst, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Var("x", + FTy 7)), + Mop(Cast + (FTy 3), + nVar"i")])), + Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))]))))]), + Mop(Snd, + Apply + (For(TP[LN 0,LN 127, + Close + (nVar"i", + Close + (Var("state", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)), + Let(Var("x",FTy 7), + Mop(Cast(FTy 7), + nVar"i"), + TP[LU, + Fupd + (Mop(Fst, + Var("state", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Var("x",FTy 7), + Call + ("write'reg'PIC_Config_Reg", + CTy"PIC_Config_Reg", + TP[Apply + (Mop(Fst, + Var("state", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Var("x", + FTy 7)), + LW(0,64)])), + Mop(Snd, + Var("state", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))])))]), + TP[Apply + (Dest + ("PIC_config_regs", + ATy(F8, + ATy(FTy 7, + CTy"PIC_Config_Reg")), + qVar"s"),Var("v",F8)),qVar"s"])))), + Let(Var("s",PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy)), + TP[Mop(Fst, + Var("s", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy))), + Rupd + ("PIC_config_regs", + TP[Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"),qTy))), + Fupd + (Dest + ("PIC_config_regs", + ATy(F8, + ATy(FTy 7,CTy"PIC_Config_Reg")), + Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))),Var("v",F8), + Mop(Fst, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))))])], + Let(Var("s", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy)), + TP[Mop(Fst, + Var("s", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"), + qTy))), + Rupd + ("PIC_ip_bits", + TP[Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Fupd + (Dest + ("PIC_ip_bits",ATy(F8,FTy 128), + Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("v",F8),LW(0,128))])], + Let(Var("s", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"), + qTy)), + TP[Mop(Fst, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Rupd + ("PIC_external_intrs", + TP[Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Fupd + (Dest + ("PIC_external_intrs", + ATy(F8,F64), + Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("v",F8),LW(0,64))])], + Mop(Snd, + Apply + (Call + ("PIC_update", + ATy(qTy,PTy(uTy,qTy)), + Var("v",F8)), + Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))))))))])))) +; +val PIC_load_def = Def + ("PIC_load",TP[Var("id",F8),Var("addr",FTy 37)], + Close + (qVar"state", + Let(Var("v",FTy 37), + Bop(Sub,Var("addr",FTy 37), + Apply + (Dest("PIC_base_address",ATy(F8,FTy 37),qVar"state"), + Var("id",F8))), + Let(TP[Var("r",F64),Var("s1",PTy(F64,qTy))], + Let(Var("s",PTy(F64,qTy)), + ITB([(Bop(Lt,Var("v",FTy 37),LW(128,37)), + TP[Call + ("reg'PIC_Config_Reg",F64, + Apply + (Apply + (Dest + ("PIC_config_regs", + ATy(F8, + ATy(FTy 7,CTy"PIC_Config_Reg")), + qVar"state"),Var("id",F8)), + Mop(Cast(FTy 7),Var("v",FTy 37)))), + qVar"state"]), + (EQ(Var("v",FTy 37),LW(1024,37)), + Let(Var("s0",PTy(F64,qTy)),TP[LX F64,qVar"state"], + TP[Bop(BOr, + EX(Apply + (Dest + ("PIC_ip_bits",ATy(F8,FTy 128), + qVar"state"),Var("id",F8)), + LN 63,LN 0,F64), + Apply + (Dest + ("PIC_external_intrs",ATy(F8,F64), + Mop(Snd,Var("s0",PTy(F64,qTy)))), + Var("id",F8))), + Mop(Snd,Var("s0",PTy(F64,qTy)))]))], + TP[ITE(EQ(Var("v",FTy 37),LW(1025,37)), + EX(Apply + (Dest + ("PIC_ip_bits",ATy(F8,FTy 128), + qVar"state"),Var("id",F8)),LN 127, + LN 64,F64),LX F64),qVar"state"]), + TP[Mop(Fst,Var("s",PTy(F64,qTy))),Var("s",PTy(F64,qTy))]), + TP[Var("r",F64),Mop(Snd,Var("s1",PTy(F64,qTy)))])))) +; +val PIC_store_def = Def + ("PIC_store", + TP[Var("id",F8),Var("addr",FTy 37),Var("mask",F64),Var("data",F64)], + Close + (qVar"state", + Let(Var("v",FTy 37), + Bop(Sub,Var("addr",FTy 37), + Apply + (Dest("PIC_base_address",ATy(F8,FTy 37),qVar"state"), + Var("id",F8))), + Let(Var("v0",ATy(FTy 7,CTy"PIC_Config_Reg")), + Apply + (Dest + ("PIC_config_regs", + ATy(F8,ATy(FTy 7,CTy"PIC_Config_Reg")),qVar"state"), + Var("id",F8)), + TP[LU, + Let(Var("s",PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy)), + ITB([(Bop(Lt,Var("v",FTy 37),LW(128,37)), + Let(Var("x",FTy 7), + Mop(Cast(FTy 7),Var("v",FTy 37)), + Let(Var("s", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"), + qTy)), + TP[Var("v0", + ATy(FTy 7,CTy"PIC_Config_Reg")), + qVar"state"], + TP[Fupd + (Mop(Fst, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Var("x",FTy 7), + Call + ("write'reg'PIC_Config_Reg", + CTy"PIC_Config_Reg", + TP[Apply + (Var("v0", + ATy(FTy 7, + CTy"PIC_Config_Reg")), + Var("x",FTy 7)), + Var("data",F64)])), + Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))]))), + (Bop(Lt,Var("v",FTy 37),LW(1040,37)), + TP[Var("v0",ATy(FTy 7,CTy"PIC_Config_Reg")), + qVar"state"]), + (EQ(Var("v",FTy 37),LW(1040,37)), + Let(Var("s0", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy)), + TP[Var("v0",ATy(FTy 7,CTy"PIC_Config_Reg")), + qVar"state"], + TP[Mop(Fst, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"),qTy))), + Rupd + ("PIC_ip_bits", + TP[Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Fupd + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("id",F8), + BFI(LN 63,LN 0, + Bop(BOr, + EX(Apply + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("id",F8)), + LN 63,LN 0,F64), + Var("data",F64)), + Apply + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + qVar"state"), + Var("id",F8))))])])), + (EQ(Var("v",FTy 37),LW(1041,37)), + Let(Var("s0", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy)), + TP[Var("v0",ATy(FTy 7,CTy"PIC_Config_Reg")), + qVar"state"], + TP[Mop(Fst, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"),qTy))), + Rupd + ("PIC_ip_bits", + TP[Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Fupd + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("id",F8), + BFI(LN 127,LN 64, + Bop(BOr, + EX(Apply + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("id",F8)), + LN 127,LN 64,F64), + Var("data",F64)), + Apply + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + qVar"state"), + Var("id",F8))))])])), + (EQ(Var("v",FTy 37),LW(1056,37)), + Let(Var("s0", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy)), + TP[Var("v0",ATy(FTy 7,CTy"PIC_Config_Reg")), + qVar"state"], + TP[Mop(Fst, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"),qTy))), + Rupd + ("PIC_ip_bits", + TP[Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Fupd + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("id",F8), + BFI(LN 63,LN 0, + Bop(BAnd, + EX(Apply + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("id",F8)), + LN 63,LN 0,F64), + Mop(BNot, + Var("data",F64))), + Apply + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + qVar"state"), + Var("id",F8))))])])), + (EQ(Var("v",FTy 37),LW(1057,37)), + Let(Var("s0", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy)), + TP[Var("v0",ATy(FTy 7,CTy"PIC_Config_Reg")), + qVar"state"], + TP[Mop(Fst, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"),qTy))), + Rupd + ("PIC_ip_bits", + TP[Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))), + Fupd + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("id",F8), + BFI(LN 127,LN 64, + Bop(BAnd, + EX(Apply + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + Mop(Snd, + Var("s0", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))), + Var("id",F8)), + LN 127,LN 64,F64), + Mop(BNot, + Var("data",F64))), + Apply + (Dest + ("PIC_ip_bits", + ATy(F8,FTy 128), + qVar"state"), + Var("id",F8))))])]))], + TP[Var("v0",ATy(FTy 7,CTy"PIC_Config_Reg")), + qVar"state"]), + Let(Var("s",PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy)), + TP[Mop(Fst, + Var("s", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"),qTy))), + Rupd + ("PIC_config_regs", + TP[Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"),qTy))), + Fupd + (Dest + ("PIC_config_regs", + ATy(F8, + ATy(FTy 7,CTy"PIC_Config_Reg")), + Mop(Snd, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy)))),Var("id",F8), + Mop(Fst, + Var("s", + PTy(ATy(FTy 7, + CTy"PIC_Config_Reg"), + qTy))))])], + Mop(Snd, + Apply + (Call + ("PIC_update",ATy(qTy,PTy(uTy,qTy)), + Var("id",F8)), + Mop(Snd, + Var("s", + PTy(ATy(FTy 7,CTy"PIC_Config_Reg"), + qTy)))))))])))) +; +val rec'JTAG_UART_data_def = Def + ("rec'JTAG_UART_data",Var("x",F32), + Rec(CTy"JTAG_UART_data__renamed__", + [EX(Var("x",F32),LN 31,LN 16,F16),Bop(Bit,Var("x",F32),LN 15), + EX(Var("x",F32),LN 7,LN 0,F8),EX(Var("x",F32),LN 14,LN 8,FTy 7)])) +; +val reg'JTAG_UART_data_def = Def + ("reg'JTAG_UART_data",Var("x",CTy"JTAG_UART_data__renamed__"), + CS(Var("x",CTy"JTAG_UART_data__renamed__"), + [(Rec(CTy"JTAG_UART_data__renamed__", + [Var("RAVAIL",F16),bVar"RVALID",Var("RW_DATA",F8), + Var("jtag_uart_data'rst",FTy 7)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),Bop(Bit,Var("RAVAIL",F16),LN 15)), + (EQ(nVar"i",LN 30),Bop(Bit,Var("RAVAIL",F16),LN 14)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("RAVAIL",F16),LN 13)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("RAVAIL",F16),LN 12)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("RAVAIL",F16),LN 11)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("RAVAIL",F16),LN 10)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("RAVAIL",F16),LN 9)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("RAVAIL",F16),LN 8)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("RAVAIL",F16),LN 7)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("RAVAIL",F16),LN 6)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("RAVAIL",F16),LN 5)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("RAVAIL",F16),LN 4)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("RAVAIL",F16),LN 3)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("RAVAIL",F16),LN 2)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("RAVAIL",F16),LN 1)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("RAVAIL",F16),LN 0)), + (EQ(nVar"i",LN 15),bVar"RVALID"), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("jtag_uart_data'rst",FTy 7),LN 6)), + (EQ(nVar"i",LN 13), + Bop(Bit,Var("jtag_uart_data'rst",FTy 7),LN 5)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("jtag_uart_data'rst",FTy 7),LN 4)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("jtag_uart_data'rst",FTy 7),LN 3)), + (EQ(nVar"i",LN 10), + Bop(Bit,Var("jtag_uart_data'rst",FTy 7),LN 2)), + (EQ(nVar"i",LN 9), + Bop(Bit,Var("jtag_uart_data'rst",FTy 7),LN 1)), + (EQ(nVar"i",LN 8), + Bop(Bit,Var("jtag_uart_data'rst",FTy 7),LN 0)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("RW_DATA",F8),LN 7)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("RW_DATA",F8),LN 6)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("RW_DATA",F8),LN 5)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("RW_DATA",F8),LN 4)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("RW_DATA",F8),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("RW_DATA",F8),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("RW_DATA",F8),LN 1))], + Bop(Bit,Var("RW_DATA",F8),LN 0))),LW(0,32)))])) +; +val write'rec'JTAG_UART_data_def = Def + ("write'rec'JTAG_UART_data", + TP[AVar F32,Var("x",CTy"JTAG_UART_data__renamed__")], + Call("reg'JTAG_UART_data",F32,Var("x",CTy"JTAG_UART_data__renamed__"))) +; +val write'reg'JTAG_UART_data_def = Def + ("write'reg'JTAG_UART_data", + TP[AVar(CTy"JTAG_UART_data__renamed__"),Var("x",F32)], + Call("rec'JTAG_UART_data",CTy"JTAG_UART_data__renamed__",Var("x",F32))) +; +val rec'JTAG_UART_control_def = Def + ("rec'JTAG_UART_control",Var("x",F32), + Rec(CTy"JTAG_UART_control__renamed__", + [Bop(Bit,Var("x",F32),LN 10),Bop(Bit,Var("x",F32),LN 0), + Bop(Bit,Var("x",F32),LN 8),Bop(Bit,Var("x",F32),LN 1), + Bop(Bit,Var("x",F32),LN 9),EX(Var("x",F32),LN 31,LN 16,F16), + CC[EX(Var("x",F32),LN 7,LN 2,FTy 6), + EX(Var("x",F32),LN 15,LN 11,FTy 5)]])) +; +val reg'JTAG_UART_control_def = Def + ("reg'JTAG_UART_control",Var("x",CTy"JTAG_UART_control__renamed__"), + CS(Var("x",CTy"JTAG_UART_control__renamed__"), + [(Rec(CTy"JTAG_UART_control__renamed__", + [bVar"AC",bVar"RE",bVar"RI",bVar"WE",bVar"WI", + Var("WSPACE",F16),Var("jtag_uart_control'rst",FTy 11)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 31),Bop(Bit,Var("WSPACE",F16),LN 15)), + (EQ(nVar"i",LN 30),Bop(Bit,Var("WSPACE",F16),LN 14)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("WSPACE",F16),LN 13)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("WSPACE",F16),LN 12)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("WSPACE",F16),LN 11)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("WSPACE",F16),LN 10)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("WSPACE",F16),LN 9)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("WSPACE",F16),LN 8)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("WSPACE",F16),LN 7)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("WSPACE",F16),LN 6)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("WSPACE",F16),LN 5)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("WSPACE",F16),LN 4)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("WSPACE",F16),LN 3)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("WSPACE",F16),LN 2)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("WSPACE",F16),LN 1)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("WSPACE",F16),LN 0)), + (EQ(nVar"i",LN 15), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 4)), + (EQ(nVar"i",LN 14), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 3)), + (EQ(nVar"i",LN 13), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 2)), + (EQ(nVar"i",LN 12), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 1)), + (EQ(nVar"i",LN 11), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 0)), + (EQ(nVar"i",LN 10),bVar"AC"), + (EQ(nVar"i",LN 9),bVar"WI"), + (EQ(nVar"i",LN 8),bVar"RI"), + (EQ(nVar"i",LN 7), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 10)), + (EQ(nVar"i",LN 6), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 9)), + (EQ(nVar"i",LN 5), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 8)), + (EQ(nVar"i",LN 4), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 7)), + (EQ(nVar"i",LN 3), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 6)), + (EQ(nVar"i",LN 2), + Bop(Bit,Var("jtag_uart_control'rst",FTy 11),LN 5)), + (EQ(nVar"i",LN 1),bVar"WE")],bVar"RE")),LW(0,32)))])) +; +val write'rec'JTAG_UART_control_def = Def + ("write'rec'JTAG_UART_control", + TP[AVar F32,Var("x",CTy"JTAG_UART_control__renamed__")], + Call + ("reg'JTAG_UART_control",F32, + Var("x",CTy"JTAG_UART_control__renamed__"))) +; +val write'reg'JTAG_UART_control_def = Def + ("write'reg'JTAG_UART_control", + TP[AVar(CTy"JTAG_UART_control__renamed__"),Var("x",F32)], + Call + ("rec'JTAG_UART_control",CTy"JTAG_UART_control__renamed__", + Var("x",F32))) +; +val JTAG_UART_update_interrupt_bit_def = Def + ("JTAG_UART_update_interrupt_bit",AVar uTy, + Close + (qVar"state", + Let(bVar"v", + Bop(And, + Dest + ("RE",bTy, + Dest + ("control",CTy"JTAG_UART_control__renamed__", + Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"))), + Dest + ("RVALID",bTy, + Dest + ("data",CTy"JTAG_UART_data__renamed__", + Dest("JTAG_UART",CTy"JTAG_UART",qVar"state")))), + ITE(Mop(Not, + EQ(Dest + ("RI",bTy, + Dest + ("control",CTy"JTAG_UART_control__renamed__", + Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"))), + bVar"v")), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"state", + Rupd + ("control", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"), + Rupd + ("RI", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"state")),bVar"v"])])]), + Apply + (Call("PIC_update",ATy(qTy,PTy(uTy,qTy)),LW(0,8)), + Rupd + ("PIC_external_intrs", + TP[qVar"s", + Fupd + (Dest + ("PIC_external_intrs",ATy(F8,F64),qVar"s"), + LW(0,8), + BFI(LN 0,LN 0,Mop(Cast F1,bVar"v"), + Apply + (Dest + ("PIC_external_intrs",ATy(F8,F64), + qVar"s"),LW(0,8))))]))), + TP[LU,qVar"state"])))) +; +val JTAG_UART_load_def = Def + ("JTAG_UART_load",qVar"state", + Apply + (Call("JTAG_UART_update_interrupt_bit",ATy(qTy,PTy(uTy,qTy)),LU), + CS(Dest + ("read_fifo",LTy F8, + Dest("JTAG_UART",CTy"JTAG_UART",qVar"state")), + [(LNL F8, + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"state", + Rupd + ("data", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"), + Rupd + ("RAVAIL", + TP[Dest + ("data",CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"state")),LW(0,16)])])]), + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("data", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"), + Rupd + ("RVALID", + TP[Dest + ("data",CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART",qVar"s")), + LF])])]))), + (LLC([Var("h",F8)],Var("t",LTy F8)), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"state", + Rupd + ("data", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"), + Rupd + ("RW_DATA", + TP[Dest + ("data",CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"state")),Var("h",F8)])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("data", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"), + Rupd + ("RAVAIL", + TP[Dest + ("data", + CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s")), + Mop(Cast F16, + Mop(Length,Var("t",LTy F8)))])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("data", + TP[Dest + ("JTAG_UART",CTy"JTAG_UART",qVar"s"), + Rupd + ("RVALID", + TP[Dest + ("data", + CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s")),LT])])]), + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("read_fifo", + TP[Dest + ("JTAG_UART",CTy"JTAG_UART",qVar"s"), + Var("t",LTy F8)])])))))]))) +; +val JTAG_UART_input_def = Def + ("JTAG_UART_input",Var("l",LTy F8), + Close + (qVar"state", + Apply + (Call("JTAG_UART_update_interrupt_bit",ATy(qTy,PTy(uTy,qTy)),LU), + CS(CC[Dest + ("read_fifo",LTy F8, + Dest("JTAG_UART",CTy"JTAG_UART",qVar"state")), + Var("l",LTy F8)], + [(LNL F8, + Rupd + ("JTAG_UART", + TP[qVar"state", + Rupd + ("data", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"), + Rupd + ("RAVAIL", + TP[Dest + ("data",CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"state")),LW(0,16)])])])), + (Var("t",LTy F8), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"state", + Rupd + ("read_fifo", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"), + Var("t",LTy F8)])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("data", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"), + Rupd + ("RAVAIL", + TP[Dest + ("data", + CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s")), + Mop(Cast F16, + Mop(Length,Var("t",LTy F8)))])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s"), + Rupd + ("AC", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART",qVar"s")), + LT])])]), + ITE(Mop(Not, + Dest + ("RVALID",bTy, + Dest + ("data", + CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s")))), + Mop(Snd, + Apply + (Const + ("JTAG_UART_load", + ATy(qTy,PTy(uTy,qTy))),qVar"s")), + qVar"s")))))])))) +; +val JTAG_UART_store_def = Def + ("JTAG_UART_store",TP[Var("mask",F64),Var("MemElem",F64)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(And, + Mop(Not,EQ(EX(Var("mask",F64),LN 63,LN 56,F8),LW(0,8))), + Mop(Not, + EQ(Dest + ("WSPACE",F16, + Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART",qVar"state"))), + LW(0,16)))), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"state", + Rupd + ("control", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"), + Rupd + ("WSPACE", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"state")), + Bop(Sub, + Dest + ("WSPACE",F16, + Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"state"))),LW(1,16))])])]), + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("write_fifo", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"), + LLC([EX(Var("MemElem",F64),LN 63,LN 56,F8)], + Dest + ("write_fifo",LTy F8, + Dest + ("JTAG_UART",CTy"JTAG_UART",qVar"s")))])])), + qVar"state"), + Let(qVar"s", + ITE(Bop(Bit,Var("mask",F64),LN 24), + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"), + Rupd + ("RE", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s")), + Bop(Bit,Var("MemElem",F64),LN 24)])])]), + qVar"s"), + Let(qVar"s", + ITE(Bop(Bit,Var("mask",F64),LN 25), + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"), + Rupd + ("WE", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s")), + Bop(Bit,Var("MemElem",F64),LN 25)])])]), + qVar"s"), + Apply + (Call + ("JTAG_UART_update_interrupt_bit", + ATy(qTy,PTy(uTy,qTy)),LU), + ITE(Bop(And,Bop(Bit,Var("mask",F64),LN 18), + Bop(Bit,Var("MemElem",F64),LN 18)), + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest + ("JTAG_UART",CTy"JTAG_UART",qVar"s"), + Rupd + ("AC", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART",qVar"s")), + LF])])]),qVar"s"))))))) +; +val JTAG_UART_output_def = Def + ("JTAG_UART_output",qVar"state", + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"state", + Rupd + ("control", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"), + Rupd + ("AC", + TP[Dest + ("control",CTy"JTAG_UART_control__renamed__", + Dest("JTAG_UART",CTy"JTAG_UART",qVar"state")), + LT])])]), + Let(qVar"s0", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("write_fifo", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"),LNL F8])]), + Let(qVar"s0", + Rupd + ("JTAG_UART", + TP[qVar"s0", + Rupd + ("control", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s0"), + Rupd + ("WSPACE", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART",CTy"JTAG_UART",qVar"s0")), + Mop(Neg,LW(1,16))])])]), + TP[Mop(Rev, + Dest + ("write_fifo",LTy F8, + Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"))), + Mop(Snd, + Apply + (Call + ("JTAG_UART_update_interrupt_bit", + ATy(qTy,PTy(uTy,qTy)),LU), + Rupd + ("JTAG_UART", + TP[qVar"s0", + Rupd + ("control", + TP[Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s0"), + Rupd + ("WI", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART",qVar"s0")), + LF])])])))])))) +; +val JTAG_UART_initialise_def = Def + ("JTAG_UART_initialise",nVar"uart", + Close + (qVar"state", + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"state", + Rupd + ("base_address", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"state"), + Mop(Cast(FTy 37), + Bop(Lsr,Mop(Cast(FTy 40),nVar"uart"),LN 3))])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("read_threshold", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"), + LN 65280])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("write_threshold", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"), + LN 65520])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("read_fifo", + TP[Dest("JTAG_UART",CTy"JTAG_UART",qVar"s"), + LNL F8])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("write_fifo", + TP[Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s"),LNL F8])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("data", + TP[Dest + ("JTAG_UART",CTy"JTAG_UART", + qVar"s"), + Rupd + ("RW_DATA", + TP[Dest + ("data", + CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s")),LW(0,8)])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("data", + TP[Dest + ("JTAG_UART", + CTy"JTAG_UART",qVar"s"), + Rupd + ("RVALID", + TP[Dest + ("data", + CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s")),LF])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("data", + TP[Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s"), + Rupd + ("RAVAIL", + TP[Dest + ("data", + CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s")), + LW(0,16)])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s"), + Rupd + ("RE", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s")), + LT])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s"), + Rupd + ("WE", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s")), + LF])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s"), + Rupd + ("RI", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s")), + LF])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s"), + Rupd + ("WI", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s")), + LF])])]), + Let(qVar"s", + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s"), + Rupd + ("AC", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s")), + LF])])]), + TP[LU, + Rupd + ("JTAG_UART", + TP[qVar"s", + Rupd + ("control", + TP[Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s"), + Rupd + ("WSPACE", + TP[Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + qVar"s")), + Mop(Neg, + LW(1, + 16))])])])]))))))))))))))) +; +val rec'Perms_def = Def + ("rec'Perms",Var("x",FTy 31), + Rec(CTy"Perms", + [Bop(Bit,Var("x",FTy 31),LN 10),Bop(Bit,Var("x",FTy 31),LN 12), + Bop(Bit,Var("x",FTy 31),LN 11),Bop(Bit,Var("x",FTy 31),LN 13), + Bop(Bit,Var("x",FTy 31),LN 14),Bop(Bit,Var("x",FTy 31),LN 0), + Bop(Bit,Var("x",FTy 31),LN 1),Bop(Bit,Var("x",FTy 31),LN 2), + Bop(Bit,Var("x",FTy 31),LN 4),Bop(Bit,Var("x",FTy 31),LN 7), + Bop(Bit,Var("x",FTy 31),LN 8),Bop(Bit,Var("x",FTy 31),LN 3), + Bop(Bit,Var("x",FTy 31),LN 5),Bop(Bit,Var("x",FTy 31),LN 6), + Bop(Bit,Var("x",FTy 31),LN 9),EX(Var("x",FTy 31),LN 30,LN 15,F16)])) +; +val reg'Perms_def = Def + ("reg'Perms",Var("x",CTy"Perms"), + CS(Var("x",CTy"Perms"), + [(Rec(CTy"Perms", + [bVar"Access_EPCC",bVar"Access_KCC",bVar"Access_KDC", + bVar"Access_KR1C",bVar"Access_KR2C",bVar"Global", + bVar"Permit_Execute",bVar"Permit_Load", + bVar"Permit_Load_Capability",bVar"Permit_Seal", + bVar"Permit_Set_Type",bVar"Permit_Store", + bVar"Permit_Store_Capability", + bVar"Permit_Store_Local_Capability",bVar"Reserved", + Var("soft",F16)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 30),Bop(Bit,Var("soft",F16),LN 15)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("soft",F16),LN 14)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("soft",F16),LN 13)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("soft",F16),LN 12)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("soft",F16),LN 11)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("soft",F16),LN 10)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("soft",F16),LN 9)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("soft",F16),LN 8)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("soft",F16),LN 7)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("soft",F16),LN 6)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("soft",F16),LN 5)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("soft",F16),LN 4)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("soft",F16),LN 3)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("soft",F16),LN 2)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("soft",F16),LN 1)), + (EQ(nVar"i",LN 15),Bop(Bit,Var("soft",F16),LN 0)), + (EQ(nVar"i",LN 14),bVar"Access_KR2C"), + (EQ(nVar"i",LN 13),bVar"Access_KR1C"), + (EQ(nVar"i",LN 12),bVar"Access_KCC"), + (EQ(nVar"i",LN 11),bVar"Access_KDC"), + (EQ(nVar"i",LN 10),bVar"Access_EPCC"), + (EQ(nVar"i",LN 9),bVar"Reserved"), + (EQ(nVar"i",LN 8),bVar"Permit_Set_Type"), + (EQ(nVar"i",LN 7),bVar"Permit_Seal"), + (EQ(nVar"i",LN 6),bVar"Permit_Store_Local_Capability"), + (EQ(nVar"i",LN 5),bVar"Permit_Store_Capability"), + (EQ(nVar"i",LN 4),bVar"Permit_Load_Capability"), + (EQ(nVar"i",LN 3),bVar"Permit_Store"), + (EQ(nVar"i",LN 2),bVar"Permit_Load"), + (EQ(nVar"i",LN 1),bVar"Permit_Execute")],bVar"Global")), + LW(0,31)))])) +; +val write'rec'Perms_def = Def + ("write'rec'Perms",TP[AVar(FTy 31),Var("x",CTy"Perms")], + Call("reg'Perms",FTy 31,Var("x",CTy"Perms"))) +; +val write'reg'Perms_def = Def + ("write'reg'Perms",TP[AVar(CTy"Perms"),Var("x",FTy 31)], + Call("rec'Perms",CTy"Perms",Var("x",FTy 31))) +; +val rec'Capability_def = Def + ("rec'Capability",Var("x",FTy 257), + Rec(CTy"Capability", + [EX(Var("x",FTy 257),LN 127,LN 64,F64), + EX(Var("x",FTy 257),LN 63,LN 0,F64), + EX(Var("x",FTy 257),LN 191,LN 128,F64), + EX(Var("x",FTy 257),LN 247,LN 224,FTy 24), + EX(Var("x",FTy 257),LN 223,LN 193,FTy 31), + EX(Var("x",FTy 257),LN 255,LN 248,F8), + Bop(Bit,Var("x",FTy 257),LN 192),Bop(Bit,Var("x",FTy 257),LN 256)])) +; +val reg'Capability_def = Def + ("reg'Capability",Var("x",CTy"Capability"), + CS(Var("x",CTy"Capability"), + [(Rec(CTy"Capability", + [Var("base",F64),Var("length",F64),Var("offset",F64), + Var("otype",FTy 24),Var("perms",FTy 31),Var("reserved",F8), + bVar"sealed",bVar"tag"]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 256),bVar"tag"), + (EQ(nVar"i",LN 255),Bop(Bit,Var("reserved",F8),LN 7)), + (EQ(nVar"i",LN 254),Bop(Bit,Var("reserved",F8),LN 6)), + (EQ(nVar"i",LN 253),Bop(Bit,Var("reserved",F8),LN 5)), + (EQ(nVar"i",LN 252),Bop(Bit,Var("reserved",F8),LN 4)), + (EQ(nVar"i",LN 251),Bop(Bit,Var("reserved",F8),LN 3)), + (EQ(nVar"i",LN 250),Bop(Bit,Var("reserved",F8),LN 2)), + (EQ(nVar"i",LN 249),Bop(Bit,Var("reserved",F8),LN 1)), + (EQ(nVar"i",LN 248),Bop(Bit,Var("reserved",F8),LN 0)), + (EQ(nVar"i",LN 247),Bop(Bit,Var("otype",FTy 24),LN 23)), + (EQ(nVar"i",LN 246),Bop(Bit,Var("otype",FTy 24),LN 22)), + (EQ(nVar"i",LN 245),Bop(Bit,Var("otype",FTy 24),LN 21)), + (EQ(nVar"i",LN 244),Bop(Bit,Var("otype",FTy 24),LN 20)), + (EQ(nVar"i",LN 243),Bop(Bit,Var("otype",FTy 24),LN 19)), + (EQ(nVar"i",LN 242),Bop(Bit,Var("otype",FTy 24),LN 18)), + (EQ(nVar"i",LN 241),Bop(Bit,Var("otype",FTy 24),LN 17)), + (EQ(nVar"i",LN 240),Bop(Bit,Var("otype",FTy 24),LN 16)), + (EQ(nVar"i",LN 239),Bop(Bit,Var("otype",FTy 24),LN 15)), + (EQ(nVar"i",LN 238),Bop(Bit,Var("otype",FTy 24),LN 14)), + (EQ(nVar"i",LN 237),Bop(Bit,Var("otype",FTy 24),LN 13)), + (EQ(nVar"i",LN 236),Bop(Bit,Var("otype",FTy 24),LN 12)), + (EQ(nVar"i",LN 235),Bop(Bit,Var("otype",FTy 24),LN 11)), + (EQ(nVar"i",LN 234),Bop(Bit,Var("otype",FTy 24),LN 10)), + (EQ(nVar"i",LN 233),Bop(Bit,Var("otype",FTy 24),LN 9)), + (EQ(nVar"i",LN 232),Bop(Bit,Var("otype",FTy 24),LN 8)), + (EQ(nVar"i",LN 231),Bop(Bit,Var("otype",FTy 24),LN 7)), + (EQ(nVar"i",LN 230),Bop(Bit,Var("otype",FTy 24),LN 6)), + (EQ(nVar"i",LN 229),Bop(Bit,Var("otype",FTy 24),LN 5)), + (EQ(nVar"i",LN 228),Bop(Bit,Var("otype",FTy 24),LN 4)), + (EQ(nVar"i",LN 227),Bop(Bit,Var("otype",FTy 24),LN 3)), + (EQ(nVar"i",LN 226),Bop(Bit,Var("otype",FTy 24),LN 2)), + (EQ(nVar"i",LN 225),Bop(Bit,Var("otype",FTy 24),LN 1)), + (EQ(nVar"i",LN 224),Bop(Bit,Var("otype",FTy 24),LN 0)), + (EQ(nVar"i",LN 223),Bop(Bit,Var("perms",FTy 31),LN 30)), + (EQ(nVar"i",LN 222),Bop(Bit,Var("perms",FTy 31),LN 29)), + (EQ(nVar"i",LN 221),Bop(Bit,Var("perms",FTy 31),LN 28)), + (EQ(nVar"i",LN 220),Bop(Bit,Var("perms",FTy 31),LN 27)), + (EQ(nVar"i",LN 219),Bop(Bit,Var("perms",FTy 31),LN 26)), + (EQ(nVar"i",LN 218),Bop(Bit,Var("perms",FTy 31),LN 25)), + (EQ(nVar"i",LN 217),Bop(Bit,Var("perms",FTy 31),LN 24)), + (EQ(nVar"i",LN 216),Bop(Bit,Var("perms",FTy 31),LN 23)), + (EQ(nVar"i",LN 215),Bop(Bit,Var("perms",FTy 31),LN 22)), + (EQ(nVar"i",LN 214),Bop(Bit,Var("perms",FTy 31),LN 21)), + (EQ(nVar"i",LN 213),Bop(Bit,Var("perms",FTy 31),LN 20)), + (EQ(nVar"i",LN 212),Bop(Bit,Var("perms",FTy 31),LN 19)), + (EQ(nVar"i",LN 211),Bop(Bit,Var("perms",FTy 31),LN 18)), + (EQ(nVar"i",LN 210),Bop(Bit,Var("perms",FTy 31),LN 17)), + (EQ(nVar"i",LN 209),Bop(Bit,Var("perms",FTy 31),LN 16)), + (EQ(nVar"i",LN 208),Bop(Bit,Var("perms",FTy 31),LN 15)), + (EQ(nVar"i",LN 207),Bop(Bit,Var("perms",FTy 31),LN 14)), + (EQ(nVar"i",LN 206),Bop(Bit,Var("perms",FTy 31),LN 13)), + (EQ(nVar"i",LN 205),Bop(Bit,Var("perms",FTy 31),LN 12)), + (EQ(nVar"i",LN 204),Bop(Bit,Var("perms",FTy 31),LN 11)), + (EQ(nVar"i",LN 203),Bop(Bit,Var("perms",FTy 31),LN 10)), + (EQ(nVar"i",LN 202),Bop(Bit,Var("perms",FTy 31),LN 9)), + (EQ(nVar"i",LN 201),Bop(Bit,Var("perms",FTy 31),LN 8)), + (EQ(nVar"i",LN 200),Bop(Bit,Var("perms",FTy 31),LN 7)), + (EQ(nVar"i",LN 199),Bop(Bit,Var("perms",FTy 31),LN 6)), + (EQ(nVar"i",LN 198),Bop(Bit,Var("perms",FTy 31),LN 5)), + (EQ(nVar"i",LN 197),Bop(Bit,Var("perms",FTy 31),LN 4)), + (EQ(nVar"i",LN 196),Bop(Bit,Var("perms",FTy 31),LN 3)), + (EQ(nVar"i",LN 195),Bop(Bit,Var("perms",FTy 31),LN 2)), + (EQ(nVar"i",LN 194),Bop(Bit,Var("perms",FTy 31),LN 1)), + (EQ(nVar"i",LN 193),Bop(Bit,Var("perms",FTy 31),LN 0)), + (EQ(nVar"i",LN 192),bVar"sealed"), + (EQ(nVar"i",LN 191),Bop(Bit,Var("offset",F64),LN 63)), + (EQ(nVar"i",LN 190),Bop(Bit,Var("offset",F64),LN 62)), + (EQ(nVar"i",LN 189),Bop(Bit,Var("offset",F64),LN 61)), + (EQ(nVar"i",LN 188),Bop(Bit,Var("offset",F64),LN 60)), + (EQ(nVar"i",LN 187),Bop(Bit,Var("offset",F64),LN 59)), + (EQ(nVar"i",LN 186),Bop(Bit,Var("offset",F64),LN 58)), + (EQ(nVar"i",LN 185),Bop(Bit,Var("offset",F64),LN 57)), + (EQ(nVar"i",LN 184),Bop(Bit,Var("offset",F64),LN 56)), + (EQ(nVar"i",LN 183),Bop(Bit,Var("offset",F64),LN 55)), + (EQ(nVar"i",LN 182),Bop(Bit,Var("offset",F64),LN 54)), + (EQ(nVar"i",LN 181),Bop(Bit,Var("offset",F64),LN 53)), + (EQ(nVar"i",LN 180),Bop(Bit,Var("offset",F64),LN 52)), + (EQ(nVar"i",LN 179),Bop(Bit,Var("offset",F64),LN 51)), + (EQ(nVar"i",LN 178),Bop(Bit,Var("offset",F64),LN 50)), + (EQ(nVar"i",LN 177),Bop(Bit,Var("offset",F64),LN 49)), + (EQ(nVar"i",LN 176),Bop(Bit,Var("offset",F64),LN 48)), + (EQ(nVar"i",LN 175),Bop(Bit,Var("offset",F64),LN 47)), + (EQ(nVar"i",LN 174),Bop(Bit,Var("offset",F64),LN 46)), + (EQ(nVar"i",LN 173),Bop(Bit,Var("offset",F64),LN 45)), + (EQ(nVar"i",LN 172),Bop(Bit,Var("offset",F64),LN 44)), + (EQ(nVar"i",LN 171),Bop(Bit,Var("offset",F64),LN 43)), + (EQ(nVar"i",LN 170),Bop(Bit,Var("offset",F64),LN 42)), + (EQ(nVar"i",LN 169),Bop(Bit,Var("offset",F64),LN 41)), + (EQ(nVar"i",LN 168),Bop(Bit,Var("offset",F64),LN 40)), + (EQ(nVar"i",LN 167),Bop(Bit,Var("offset",F64),LN 39)), + (EQ(nVar"i",LN 166),Bop(Bit,Var("offset",F64),LN 38)), + (EQ(nVar"i",LN 165),Bop(Bit,Var("offset",F64),LN 37)), + (EQ(nVar"i",LN 164),Bop(Bit,Var("offset",F64),LN 36)), + (EQ(nVar"i",LN 163),Bop(Bit,Var("offset",F64),LN 35)), + (EQ(nVar"i",LN 162),Bop(Bit,Var("offset",F64),LN 34)), + (EQ(nVar"i",LN 161),Bop(Bit,Var("offset",F64),LN 33)), + (EQ(nVar"i",LN 160),Bop(Bit,Var("offset",F64),LN 32)), + (EQ(nVar"i",LN 159),Bop(Bit,Var("offset",F64),LN 31)), + (EQ(nVar"i",LN 158),Bop(Bit,Var("offset",F64),LN 30)), + (EQ(nVar"i",LN 157),Bop(Bit,Var("offset",F64),LN 29)), + (EQ(nVar"i",LN 156),Bop(Bit,Var("offset",F64),LN 28)), + (EQ(nVar"i",LN 155),Bop(Bit,Var("offset",F64),LN 27)), + (EQ(nVar"i",LN 154),Bop(Bit,Var("offset",F64),LN 26)), + (EQ(nVar"i",LN 153),Bop(Bit,Var("offset",F64),LN 25)), + (EQ(nVar"i",LN 152),Bop(Bit,Var("offset",F64),LN 24)), + (EQ(nVar"i",LN 151),Bop(Bit,Var("offset",F64),LN 23)), + (EQ(nVar"i",LN 150),Bop(Bit,Var("offset",F64),LN 22)), + (EQ(nVar"i",LN 149),Bop(Bit,Var("offset",F64),LN 21)), + (EQ(nVar"i",LN 148),Bop(Bit,Var("offset",F64),LN 20)), + (EQ(nVar"i",LN 147),Bop(Bit,Var("offset",F64),LN 19)), + (EQ(nVar"i",LN 146),Bop(Bit,Var("offset",F64),LN 18)), + (EQ(nVar"i",LN 145),Bop(Bit,Var("offset",F64),LN 17)), + (EQ(nVar"i",LN 144),Bop(Bit,Var("offset",F64),LN 16)), + (EQ(nVar"i",LN 143),Bop(Bit,Var("offset",F64),LN 15)), + (EQ(nVar"i",LN 142),Bop(Bit,Var("offset",F64),LN 14)), + (EQ(nVar"i",LN 141),Bop(Bit,Var("offset",F64),LN 13)), + (EQ(nVar"i",LN 140),Bop(Bit,Var("offset",F64),LN 12)), + (EQ(nVar"i",LN 139),Bop(Bit,Var("offset",F64),LN 11)), + (EQ(nVar"i",LN 138),Bop(Bit,Var("offset",F64),LN 10)), + (EQ(nVar"i",LN 137),Bop(Bit,Var("offset",F64),LN 9)), + (EQ(nVar"i",LN 136),Bop(Bit,Var("offset",F64),LN 8)), + (EQ(nVar"i",LN 135),Bop(Bit,Var("offset",F64),LN 7)), + (EQ(nVar"i",LN 134),Bop(Bit,Var("offset",F64),LN 6)), + (EQ(nVar"i",LN 133),Bop(Bit,Var("offset",F64),LN 5)), + (EQ(nVar"i",LN 132),Bop(Bit,Var("offset",F64),LN 4)), + (EQ(nVar"i",LN 131),Bop(Bit,Var("offset",F64),LN 3)), + (EQ(nVar"i",LN 130),Bop(Bit,Var("offset",F64),LN 2)), + (EQ(nVar"i",LN 129),Bop(Bit,Var("offset",F64),LN 1)), + (EQ(nVar"i",LN 128),Bop(Bit,Var("offset",F64),LN 0)), + (EQ(nVar"i",LN 127),Bop(Bit,Var("base",F64),LN 63)), + (EQ(nVar"i",LN 126),Bop(Bit,Var("base",F64),LN 62)), + (EQ(nVar"i",LN 125),Bop(Bit,Var("base",F64),LN 61)), + (EQ(nVar"i",LN 124),Bop(Bit,Var("base",F64),LN 60)), + (EQ(nVar"i",LN 123),Bop(Bit,Var("base",F64),LN 59)), + (EQ(nVar"i",LN 122),Bop(Bit,Var("base",F64),LN 58)), + (EQ(nVar"i",LN 121),Bop(Bit,Var("base",F64),LN 57)), + (EQ(nVar"i",LN 120),Bop(Bit,Var("base",F64),LN 56)), + (EQ(nVar"i",LN 119),Bop(Bit,Var("base",F64),LN 55)), + (EQ(nVar"i",LN 118),Bop(Bit,Var("base",F64),LN 54)), + (EQ(nVar"i",LN 117),Bop(Bit,Var("base",F64),LN 53)), + (EQ(nVar"i",LN 116),Bop(Bit,Var("base",F64),LN 52)), + (EQ(nVar"i",LN 115),Bop(Bit,Var("base",F64),LN 51)), + (EQ(nVar"i",LN 114),Bop(Bit,Var("base",F64),LN 50)), + (EQ(nVar"i",LN 113),Bop(Bit,Var("base",F64),LN 49)), + (EQ(nVar"i",LN 112),Bop(Bit,Var("base",F64),LN 48)), + (EQ(nVar"i",LN 111),Bop(Bit,Var("base",F64),LN 47)), + (EQ(nVar"i",LN 110),Bop(Bit,Var("base",F64),LN 46)), + (EQ(nVar"i",LN 109),Bop(Bit,Var("base",F64),LN 45)), + (EQ(nVar"i",LN 108),Bop(Bit,Var("base",F64),LN 44)), + (EQ(nVar"i",LN 107),Bop(Bit,Var("base",F64),LN 43)), + (EQ(nVar"i",LN 106),Bop(Bit,Var("base",F64),LN 42)), + (EQ(nVar"i",LN 105),Bop(Bit,Var("base",F64),LN 41)), + (EQ(nVar"i",LN 104),Bop(Bit,Var("base",F64),LN 40)), + (EQ(nVar"i",LN 103),Bop(Bit,Var("base",F64),LN 39)), + (EQ(nVar"i",LN 102),Bop(Bit,Var("base",F64),LN 38)), + (EQ(nVar"i",LN 101),Bop(Bit,Var("base",F64),LN 37)), + (EQ(nVar"i",LN 100),Bop(Bit,Var("base",F64),LN 36)), + (EQ(nVar"i",LN 99),Bop(Bit,Var("base",F64),LN 35)), + (EQ(nVar"i",LN 98),Bop(Bit,Var("base",F64),LN 34)), + (EQ(nVar"i",LN 97),Bop(Bit,Var("base",F64),LN 33)), + (EQ(nVar"i",LN 96),Bop(Bit,Var("base",F64),LN 32)), + (EQ(nVar"i",LN 95),Bop(Bit,Var("base",F64),LN 31)), + (EQ(nVar"i",LN 94),Bop(Bit,Var("base",F64),LN 30)), + (EQ(nVar"i",LN 93),Bop(Bit,Var("base",F64),LN 29)), + (EQ(nVar"i",LN 92),Bop(Bit,Var("base",F64),LN 28)), + (EQ(nVar"i",LN 91),Bop(Bit,Var("base",F64),LN 27)), + (EQ(nVar"i",LN 90),Bop(Bit,Var("base",F64),LN 26)), + (EQ(nVar"i",LN 89),Bop(Bit,Var("base",F64),LN 25)), + (EQ(nVar"i",LN 88),Bop(Bit,Var("base",F64),LN 24)), + (EQ(nVar"i",LN 87),Bop(Bit,Var("base",F64),LN 23)), + (EQ(nVar"i",LN 86),Bop(Bit,Var("base",F64),LN 22)), + (EQ(nVar"i",LN 85),Bop(Bit,Var("base",F64),LN 21)), + (EQ(nVar"i",LN 84),Bop(Bit,Var("base",F64),LN 20)), + (EQ(nVar"i",LN 83),Bop(Bit,Var("base",F64),LN 19)), + (EQ(nVar"i",LN 82),Bop(Bit,Var("base",F64),LN 18)), + (EQ(nVar"i",LN 81),Bop(Bit,Var("base",F64),LN 17)), + (EQ(nVar"i",LN 80),Bop(Bit,Var("base",F64),LN 16)), + (EQ(nVar"i",LN 79),Bop(Bit,Var("base",F64),LN 15)), + (EQ(nVar"i",LN 78),Bop(Bit,Var("base",F64),LN 14)), + (EQ(nVar"i",LN 77),Bop(Bit,Var("base",F64),LN 13)), + (EQ(nVar"i",LN 76),Bop(Bit,Var("base",F64),LN 12)), + (EQ(nVar"i",LN 75),Bop(Bit,Var("base",F64),LN 11)), + (EQ(nVar"i",LN 74),Bop(Bit,Var("base",F64),LN 10)), + (EQ(nVar"i",LN 73),Bop(Bit,Var("base",F64),LN 9)), + (EQ(nVar"i",LN 72),Bop(Bit,Var("base",F64),LN 8)), + (EQ(nVar"i",LN 71),Bop(Bit,Var("base",F64),LN 7)), + (EQ(nVar"i",LN 70),Bop(Bit,Var("base",F64),LN 6)), + (EQ(nVar"i",LN 69),Bop(Bit,Var("base",F64),LN 5)), + (EQ(nVar"i",LN 68),Bop(Bit,Var("base",F64),LN 4)), + (EQ(nVar"i",LN 67),Bop(Bit,Var("base",F64),LN 3)), + (EQ(nVar"i",LN 66),Bop(Bit,Var("base",F64),LN 2)), + (EQ(nVar"i",LN 65),Bop(Bit,Var("base",F64),LN 1)), + (EQ(nVar"i",LN 64),Bop(Bit,Var("base",F64),LN 0)), + (EQ(nVar"i",LN 63),Bop(Bit,Var("length",F64),LN 63)), + (EQ(nVar"i",LN 62),Bop(Bit,Var("length",F64),LN 62)), + (EQ(nVar"i",LN 61),Bop(Bit,Var("length",F64),LN 61)), + (EQ(nVar"i",LN 60),Bop(Bit,Var("length",F64),LN 60)), + (EQ(nVar"i",LN 59),Bop(Bit,Var("length",F64),LN 59)), + (EQ(nVar"i",LN 58),Bop(Bit,Var("length",F64),LN 58)), + (EQ(nVar"i",LN 57),Bop(Bit,Var("length",F64),LN 57)), + (EQ(nVar"i",LN 56),Bop(Bit,Var("length",F64),LN 56)), + (EQ(nVar"i",LN 55),Bop(Bit,Var("length",F64),LN 55)), + (EQ(nVar"i",LN 54),Bop(Bit,Var("length",F64),LN 54)), + (EQ(nVar"i",LN 53),Bop(Bit,Var("length",F64),LN 53)), + (EQ(nVar"i",LN 52),Bop(Bit,Var("length",F64),LN 52)), + (EQ(nVar"i",LN 51),Bop(Bit,Var("length",F64),LN 51)), + (EQ(nVar"i",LN 50),Bop(Bit,Var("length",F64),LN 50)), + (EQ(nVar"i",LN 49),Bop(Bit,Var("length",F64),LN 49)), + (EQ(nVar"i",LN 48),Bop(Bit,Var("length",F64),LN 48)), + (EQ(nVar"i",LN 47),Bop(Bit,Var("length",F64),LN 47)), + (EQ(nVar"i",LN 46),Bop(Bit,Var("length",F64),LN 46)), + (EQ(nVar"i",LN 45),Bop(Bit,Var("length",F64),LN 45)), + (EQ(nVar"i",LN 44),Bop(Bit,Var("length",F64),LN 44)), + (EQ(nVar"i",LN 43),Bop(Bit,Var("length",F64),LN 43)), + (EQ(nVar"i",LN 42),Bop(Bit,Var("length",F64),LN 42)), + (EQ(nVar"i",LN 41),Bop(Bit,Var("length",F64),LN 41)), + (EQ(nVar"i",LN 40),Bop(Bit,Var("length",F64),LN 40)), + (EQ(nVar"i",LN 39),Bop(Bit,Var("length",F64),LN 39)), + (EQ(nVar"i",LN 38),Bop(Bit,Var("length",F64),LN 38)), + (EQ(nVar"i",LN 37),Bop(Bit,Var("length",F64),LN 37)), + (EQ(nVar"i",LN 36),Bop(Bit,Var("length",F64),LN 36)), + (EQ(nVar"i",LN 35),Bop(Bit,Var("length",F64),LN 35)), + (EQ(nVar"i",LN 34),Bop(Bit,Var("length",F64),LN 34)), + (EQ(nVar"i",LN 33),Bop(Bit,Var("length",F64),LN 33)), + (EQ(nVar"i",LN 32),Bop(Bit,Var("length",F64),LN 32)), + (EQ(nVar"i",LN 31),Bop(Bit,Var("length",F64),LN 31)), + (EQ(nVar"i",LN 30),Bop(Bit,Var("length",F64),LN 30)), + (EQ(nVar"i",LN 29),Bop(Bit,Var("length",F64),LN 29)), + (EQ(nVar"i",LN 28),Bop(Bit,Var("length",F64),LN 28)), + (EQ(nVar"i",LN 27),Bop(Bit,Var("length",F64),LN 27)), + (EQ(nVar"i",LN 26),Bop(Bit,Var("length",F64),LN 26)), + (EQ(nVar"i",LN 25),Bop(Bit,Var("length",F64),LN 25)), + (EQ(nVar"i",LN 24),Bop(Bit,Var("length",F64),LN 24)), + (EQ(nVar"i",LN 23),Bop(Bit,Var("length",F64),LN 23)), + (EQ(nVar"i",LN 22),Bop(Bit,Var("length",F64),LN 22)), + (EQ(nVar"i",LN 21),Bop(Bit,Var("length",F64),LN 21)), + (EQ(nVar"i",LN 20),Bop(Bit,Var("length",F64),LN 20)), + (EQ(nVar"i",LN 19),Bop(Bit,Var("length",F64),LN 19)), + (EQ(nVar"i",LN 18),Bop(Bit,Var("length",F64),LN 18)), + (EQ(nVar"i",LN 17),Bop(Bit,Var("length",F64),LN 17)), + (EQ(nVar"i",LN 16),Bop(Bit,Var("length",F64),LN 16)), + (EQ(nVar"i",LN 15),Bop(Bit,Var("length",F64),LN 15)), + (EQ(nVar"i",LN 14),Bop(Bit,Var("length",F64),LN 14)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("length",F64),LN 13)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("length",F64),LN 12)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("length",F64),LN 11)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("length",F64),LN 10)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("length",F64),LN 9)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("length",F64),LN 8)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("length",F64),LN 7)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("length",F64),LN 6)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("length",F64),LN 5)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("length",F64),LN 4)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("length",F64),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("length",F64),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("length",F64),LN 1))], + Bop(Bit,Var("length",F64),LN 0))),LW(0,257)))])) +; +val write'rec'Capability_def = Def + ("write'rec'Capability",TP[AVar(FTy 257),Var("x",CTy"Capability")], + Call("reg'Capability",FTy 257,Var("x",CTy"Capability"))) +; +val write'reg'Capability_def = Def + ("write'reg'Capability",TP[AVar(CTy"Capability"),Var("x",FTy 257)], + Call("rec'Capability",CTy"Capability",Var("x",FTy 257))) +; +val rec'CapCause_def = Def + ("rec'CapCause",Var("x",F16), + Rec(CTy"CapCause", + [EX(Var("x",F16),LN 15,LN 8,F8),EX(Var("x",F16),LN 7,LN 0,F8)])) +; +val reg'CapCause_def = Def + ("reg'CapCause",Var("x",CTy"CapCause"), + CS(Var("x",CTy"CapCause"), + [(Rec(CTy"CapCause",[Var("ExcCode",F8),Var("RegNum",F8)]), + Bop(Mdfy, + Close + (TP[nVar"i",AVar bTy], + ITB([(EQ(nVar"i",LN 15),Bop(Bit,Var("ExcCode",F8),LN 7)), + (EQ(nVar"i",LN 14),Bop(Bit,Var("ExcCode",F8),LN 6)), + (EQ(nVar"i",LN 13),Bop(Bit,Var("ExcCode",F8),LN 5)), + (EQ(nVar"i",LN 12),Bop(Bit,Var("ExcCode",F8),LN 4)), + (EQ(nVar"i",LN 11),Bop(Bit,Var("ExcCode",F8),LN 3)), + (EQ(nVar"i",LN 10),Bop(Bit,Var("ExcCode",F8),LN 2)), + (EQ(nVar"i",LN 9),Bop(Bit,Var("ExcCode",F8),LN 1)), + (EQ(nVar"i",LN 8),Bop(Bit,Var("ExcCode",F8),LN 0)), + (EQ(nVar"i",LN 7),Bop(Bit,Var("RegNum",F8),LN 7)), + (EQ(nVar"i",LN 6),Bop(Bit,Var("RegNum",F8),LN 6)), + (EQ(nVar"i",LN 5),Bop(Bit,Var("RegNum",F8),LN 5)), + (EQ(nVar"i",LN 4),Bop(Bit,Var("RegNum",F8),LN 4)), + (EQ(nVar"i",LN 3),Bop(Bit,Var("RegNum",F8),LN 3)), + (EQ(nVar"i",LN 2),Bop(Bit,Var("RegNum",F8),LN 2)), + (EQ(nVar"i",LN 1),Bop(Bit,Var("RegNum",F8),LN 1))], + Bop(Bit,Var("RegNum",F8),LN 0))),LW(0,16)))])) +; +val write'rec'CapCause_def = Def + ("write'rec'CapCause",TP[AVar F16,Var("x",CTy"CapCause")], + Call("reg'CapCause",F16,Var("x",CTy"CapCause"))) +; +val write'reg'CapCause_def = Def + ("write'reg'CapCause",TP[AVar(CTy"CapCause"),Var("x",F16)], + Call("rec'CapCause",CTy"CapCause",Var("x",F16))) +; +val BranchDelayPCC_def = Def + ("BranchDelayPCC",qVar"state", + TP[Apply + (Dest + ("c_BranchDelayPCC",ATy(F8,OTy(PTy(F64,CTy"Capability"))), + qVar"state"),Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'BranchDelayPCC_def = Def + ("write'BranchDelayPCC",Var("value",OTy(PTy(F64,CTy"Capability"))), + Close + (qVar"state", + TP[LU, + Rupd + ("c_BranchDelayPCC", + TP[qVar"state", + Fupd + (Dest + ("c_BranchDelayPCC", + ATy(F8,OTy(PTy(F64,CTy"Capability"))),qVar"state"), + Dest("procID",F8,qVar"state"), + Var("value",OTy(PTy(F64,CTy"Capability"))))])])) +; +val BranchToPCC_def = Def + ("BranchToPCC",qVar"state", + TP[Apply + (Dest + ("c_BranchToPCC",ATy(F8,OTy(PTy(F64,CTy"Capability"))), + qVar"state"),Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'BranchToPCC_def = Def + ("write'BranchToPCC",Var("value",OTy(PTy(F64,CTy"Capability"))), + Close + (qVar"state", + TP[LU, + Rupd + ("c_BranchToPCC", + TP[qVar"state", + Fupd + (Dest + ("c_BranchToPCC", + ATy(F8,OTy(PTy(F64,CTy"Capability"))),qVar"state"), + Dest("procID",F8,qVar"state"), + Var("value",OTy(PTy(F64,CTy"Capability"))))])])) +; +val hex24_def = Def + ("hex24",Var("x",FTy 24), + Mop(PadLeft,TP[LSC #"0",LN 6,Mop(Cast sTy,Var("x",FTy 24))])) +; +val hex31_def = Def + ("hex31",Var("x",FTy 31), + Mop(PadLeft,TP[LSC #"0",LN 8,Mop(Cast sTy,Var("x",FTy 31))])) +; +val hex40_def = Def + ("hex40",Var("x",FTy 40), + Mop(PadLeft,TP[LSC #"0",LN 10,Mop(Cast sTy,Var("x",FTy 40))])) +; +val log_cap_write_def = Def + ("log_cap_write",Var("cap",CTy"Capability"), + CC[LS"u:", + ITE(Dest("sealed",bTy,Var("cap",CTy"Capability")),LS"1",LS"0"), + LS" perms:0x", + Call("hex31",sTy,Dest("perms",FTy 31,Var("cap",CTy"Capability"))), + LS" type:0x", + Call("hex24",sTy,Dest("otype",FTy 24,Var("cap",CTy"Capability"))), + LS" offset:0x", + Call("hex64",sTy,Dest("offset",F64,Var("cap",CTy"Capability"))), + LS" base:0x", + Call("hex64",sTy,Dest("base",F64,Var("cap",CTy"Capability"))), + LS" length:0x", + Call("hex64",sTy,Dest("length",F64,Var("cap",CTy"Capability")))]) +; +val log_cpp_write_def = Def + ("log_cpp_write",Var("cap",CTy"Capability"), + CC[LS"PCC <- ",Call("log_cap_write",sTy,Var("cap",CTy"Capability"))]) +; +val log_creg_write_def = Def + ("log_creg_write",TP[Var("r",FTy 5),Var("cap",CTy"Capability")], + CC[LS"CapReg ",Mop(Cast sTy,Mop(Cast nTy,Var("r",FTy 5))),LS" <- ", + Call("log_cap_write",sTy,Var("cap",CTy"Capability"))]) +; +val log_store_cap_def = Def + ("log_store_cap",TP[Var("pAddr",FTy 40),Var("cap",CTy"Capability")], + CC[LS"MEM[0x",Call("hex40",sTy,Var("pAddr",FTy 40)),LS"] <- ", + Call("log_cap_write",sTy,Var("cap",CTy"Capability"))]) +; +val log_cap_exce_def = Def + ("log_cap_exce",TP[Var("e",F8),Var("cr",F8)], + Close + (qVar"state", + TP[CC[LS"CapException : 0x",Mop(Cast sTy,Var("e",F8)),LS" CReg ", + Mop(Cast sTy,Mop(Cast nTy,Var("cr",F8))), + ITE(Bop(Lt,Var("cr",F8),LW(32,8)), + CC[LS" : ", + Call + ("log_cap_write",sTy, + Apply + (Apply + (Dest + ("c_capr", + ATy(F8,ATy(FTy 5,CTy"Capability")), + qVar"state"),Dest("procID",F8,qVar"state")), + Mop(Cast(FTy 5),Var("cr",F8))))],LS"")], + qVar"state"])) +; +val dumpCRegs_def = Def + ("dumpCRegs",AVar uTy, + Close + (qVar"state", + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 0,LS"====== Registers ======"]),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 0, + CC[LS"Core = ", + Mop(Cast sTy, + Mop(Cast nTy,Dest("procID",F8,qVar"s")))]]), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 0, + CC[LS"DEBUG CAP PCC ", + Call + ("log_cap_write",sTy, + Apply + (Dest + ("c_pcc", + ATy(F8,CTy"Capability"),qVar"s"), + Dest("procID",F8,qVar"s")))]]), + qVar"s")), + Apply + (For(TP[LN 0,LN 31, + Close + (nVar"i", + Close + (qVar"state", + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 0, + CC[LS"DEBUG CAP REG ", + ITE(Bop(Lt,nVar"i",LN 10), + LS" ",LS""), + Mop(Cast sTy, + Mop(Cast nTy,nVar"i")), + LS" ", + Call + ("log_cap_write",sTy, + Apply + (Apply + (Dest + ("c_capr", + ATy(F8, + ATy(FTy 5, + CTy"Capability")), + qVar"s"), + Dest + ("procID",F8, + qVar"s")), + Mop(Cast(FTy 5), + nVar"i")))]]), + qVar"state")))]),qVar"s")))))) +; +val capcause_def = Def + ("capcause",qVar"state", + TP[Apply + (Dest("c_capcause",ATy(F8,CTy"CapCause"),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'capcause_def = Def + ("write'capcause",Var("value",CTy"CapCause"), + Close + (qVar"state", + TP[LU, + Rupd + ("c_capcause", + TP[qVar"state", + Fupd + (Dest("c_capcause",ATy(F8,CTy"CapCause"),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",CTy"CapCause"))])])) +; +val PCC_def = Def + ("PCC",qVar"state", + TP[Apply + (Dest("c_pcc",ATy(F8,CTy"Capability"),qVar"state"), + Dest("procID",F8,qVar"state")),qVar"state"]) +; +val write'PCC_def = Def + ("write'PCC",Var("value",CTy"Capability"), + Close + (qVar"state", + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 2,Call("log_cpp_write",sTy,Var("value",CTy"Capability"))]), + Rupd + ("c_pcc", + TP[qVar"state", + Fupd + (Dest("c_pcc",ATy(F8,CTy"Capability"),qVar"state"), + Dest("procID",F8,qVar"state"), + Var("value",CTy"Capability"))])))) +; +val CAPR_def = Def + ("CAPR",Var("n",FTy 5), + Close + (qVar"state", + TP[Apply + (Apply + (Dest + ("c_capr",ATy(F8,ATy(FTy 5,CTy"Capability")),qVar"state"), + Dest("procID",F8,qVar"state")),Var("n",FTy 5)),qVar"state"])) +; +val write'CAPR_def = Def + ("write'CAPR",TP[Var("value",CTy"Capability"),Var("n",FTy 5)], + Close + (qVar"state", + TP[LU, + Let(Var("s",PTy(ATy(FTy 5,CTy"Capability"),qTy)), + TP[Fupd + (Apply + (Dest + ("c_capr",ATy(F8,ATy(FTy 5,CTy"Capability")), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("n",FTy 5),Var("value",CTy"Capability")), + qVar"state"], + Let(Var("s",PTy(ATy(FTy 5,CTy"Capability"),qTy)), + TP[Mop(Fst,Var("s",PTy(ATy(FTy 5,CTy"Capability"),qTy))), + Rupd + ("c_capr", + TP[Mop(Snd, + Var("s",PTy(ATy(FTy 5,CTy"Capability"),qTy))), + Fupd + (Dest + ("c_capr", + ATy(F8,ATy(FTy 5,CTy"Capability")), + Mop(Snd, + Var("s", + PTy(ATy(FTy 5,CTy"Capability"),qTy)))), + Dest + ("procID",F8, + Mop(Snd, + Var("s", + PTy(ATy(FTy 5,CTy"Capability"),qTy)))), + Mop(Fst, + Var("s", + PTy(ATy(FTy 5,CTy"Capability"),qTy))))])], + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 2, + Call + ("log_creg_write",sTy, + TP[Var("n",FTy 5), + Var("value",CTy"Capability")])]), + Mop(Snd, + Var("s",PTy(ATy(FTy 5,CTy"Capability"),qTy)))))))])) +; +val RCC_def = Def + ("RCC",qVar"state", + TP[Mop(Fst, + Apply + (Call("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)),LW(24,5)), + qVar"state")),qVar"state"]) +; +val write'RCC_def = Def + ("write'RCC",Var("value",CTy"Capability"), + Close + (qVar"state", + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("value",CTy"Capability"),LW(24,5)]),qVar"state"))) +; +val IDC_def = Def + ("IDC",qVar"state", + TP[Mop(Fst, + Apply + (Call("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)),LW(26,5)), + qVar"state")),qVar"state"]) +; +val write'IDC_def = Def + ("write'IDC",Var("value",CTy"Capability"), + Close + (qVar"state", + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("value",CTy"Capability"),LW(26,5)]),qVar"state"))) +; +val KR1C_def = Def + ("KR1C",qVar"state", + TP[Mop(Fst, + Apply + (Call("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)),LW(27,5)), + qVar"state")),qVar"state"]) +; +val write'KR1C_def = Def + ("write'KR1C",Var("value",CTy"Capability"), + Close + (qVar"state", + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("value",CTy"Capability"),LW(27,5)]),qVar"state"))) +; +val KR2C_def = Def + ("KR2C",qVar"state", + TP[Mop(Fst, + Apply + (Call("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)),LW(28,5)), + qVar"state")),qVar"state"]) +; +val write'KR2C_def = Def + ("write'KR2C",Var("value",CTy"Capability"), + Close + (qVar"state", + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("value",CTy"Capability"),LW(28,5)]),qVar"state"))) +; +val KCC_def = Def + ("KCC",qVar"state", + TP[Mop(Fst, + Apply + (Call("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)),LW(29,5)), + qVar"state")),qVar"state"]) +; +val write'KCC_def = Def + ("write'KCC",Var("value",CTy"Capability"), + Close + (qVar"state", + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("value",CTy"Capability"),LW(29,5)]),qVar"state"))) +; +val KDC_def = Def + ("KDC",qVar"state", + TP[Mop(Fst, + Apply + (Call("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)),LW(30,5)), + qVar"state")),qVar"state"]) +; +val write'KDC_def = Def + ("write'KDC",Var("value",CTy"Capability"), + Close + (qVar"state", + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("value",CTy"Capability"),LW(30,5)]),qVar"state"))) +; +val EPCC_def = Def + ("EPCC",qVar"state", + TP[Mop(Fst, + Apply + (Call("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)),LW(31,5)), + qVar"state")),qVar"state"]) +; +val write'EPCC_def = Def + ("write'EPCC",Var("value",CTy"Capability"), + Close + (qVar"state", + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("value",CTy"Capability"),LW(31,5)]),qVar"state"))) +; +val ExceptionCode_def = Def + ("ExceptionCode",Var("ExceptionType",CTy"ExceptionType"), + CS(Var("ExceptionType",CTy"ExceptionType"), + [(LC("Int",CTy"ExceptionType"),LW(0,5)), + (LC("Mod",CTy"ExceptionType"),LW(1,5)), + (LC("TLBL",CTy"ExceptionType"),LW(2,5)), + (LC("TLBS",CTy"ExceptionType"),LW(3,5)), + (LC("AdEL",CTy"ExceptionType"),LW(4,5)), + (LC("AdES",CTy"ExceptionType"),LW(5,5)), + (LC("Sys",CTy"ExceptionType"),LW(8,5)), + (LC("Bp",CTy"ExceptionType"),LW(9,5)), + (LC("ResI",CTy"ExceptionType"),LW(10,5)), + (LC("CpU",CTy"ExceptionType"),LW(11,5)), + (LC("Ov",CTy"ExceptionType"),LW(12,5)), + (LC("Tr",CTy"ExceptionType"),LW(13,5)), + (LC("CTLBL",CTy"ExceptionType"),LW(16,5)), + (LC("CTLBS",CTy"ExceptionType"),LW(17,5)), + (LC("C2E",CTy"ExceptionType"),LW(18,5)), + (LC("XTLBRefillL",CTy"ExceptionType"),LW(2,5)), + (LC("XTLBRefillS",CTy"ExceptionType"),LW(3,5))])) +; +val SignalException_def = Def + ("SignalException",Var("ExceptionType",CTy"ExceptionType"), + Close + (qVar"state", + Let(qVar"s", + ITE(Mop(Not, + Dest + ("EXL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + ITE(Mop(IsSome, + Mop(Fst, + Apply + (Const + ("BranchDelay",ATy(qTy,PTy(OTy F64,qTy))), + qVar"state"))), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EPC", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"state")), + Bop(Sub, + Mop(Fst, + Apply + (Const + ("PC", + ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64))])), + qVar"state")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Cause", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("BD", + TP[Dest + ("Cause", + CTy"CauseRegister", + Var("v", + CTy"CP0__renamed__")), + LT])])),qVar"s")))), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EPC", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"state")), + Mop(Fst, + Apply + (Const + ("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state"))])),qVar"state")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Cause", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("BD", + TP[Dest + ("Cause", + CTy"CauseRegister", + Var("v", + CTy"CP0__renamed__")), + LF])])),qVar"s"))))), + qVar"state"), + Let(qVar"s0", + ITE(Mop(IsSome,Dest("currentInst",OTy F32,qVar"s")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EInstr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Mop(ValOf, + Dest("currentInst",OTy F32,qVar"s"))])), + qVar"s")),qVar"s"), + Let(Var("v0",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s0")), + Let(qVar"s0", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Cause", + TP[Var("v0",CTy"CP0__renamed__"), + Rupd + ("ExcCode", + TP[Dest + ("Cause",CTy"CauseRegister", + Var("v0", + CTy"CP0__renamed__")), + Call + ("ExceptionCode",FTy 5, + Var("ExceptionType", + CTy"ExceptionType"))])])), + qVar"s0")), + Let(Var("v0",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s0")), + Let(qVar"s0", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Status", + TP[Var("v0",CTy"CP0__renamed__"), + Rupd + ("EXL", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v0", + CTy"CP0__renamed__")), + LT])])),qVar"s0")), + Let(Var("v0",F64), + ITE(Dest + ("BEV",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s0")))), + LW(18446744072631616000,64), + LW(18446744071562067968,64)), + Let(qVar"s0", + Mop(Snd, + Apply + (Call + ("write'exceptionSignalled", + ATy(qTy,PTy(uTy,qTy)),LT), + Mop(Snd, + Apply + (Call + ("write'BranchTo", + ATy(qTy, + PTy(uTy,qTy)), + LO F64), + Mop(Snd, + Apply + (Call + ("write'BranchDelay", + ATy(qTy, + PTy(uTy, + qTy)), + LO F64), + qVar"s0")))))), + Let(qVar"s0", + Mop(Snd, + Apply + (Call + ("write'EPCC", + ATy(qTy,PTy(uTy,qTy)), + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))), + qVar"s0"))), + qVar"s0")), + Let(qVar"s0", + Mop(Snd, + Apply + (Call + ("write'EPCC", + ATy(qTy, + PTy(uTy,qTy)), + Rupd + ("offset", + TP[Mop(Fst, + Apply + (Const + ("EPCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))), + qVar"s0")), + Mop(Fst, + Apply + (Const + ("PC", + ATy(qTy, + PTy(F64, + qTy))), + qVar"s0"))])), + qVar"s0")), + Apply + (Call + ("mark_log", + ATy(qTy,PTy(uTy,qTy)), + TP[LN 2, + Call + ("log_sig_exception", + sTy, + Call + ("ExceptionCode", + FTy 5, + Var("ExceptionType", + CTy"ExceptionType")))]), + Mop(Snd, + Apply + (Call + ("write'PC", + ATy(qTy, + PTy(uTy,qTy)), + CC[EX(Var("v0", + F64), + LN 63, + LN 30, + FTy 34), + Bop(Add, + EX(Var("v0", + F64), + LN 29, + LN 0, + FTy 30), + ITB([(Bop(And, + Bop(Or, + EQ(Var("ExceptionType", + CTy"ExceptionType"), + LC("XTLBRefillL", + CTy"ExceptionType")), + EQ(Var("ExceptionType", + CTy"ExceptionType"), + LC("XTLBRefillS", + CTy"ExceptionType"))), + Mop(Not, + Dest + ("EXL", + bTy, + Dest + ("Status", + CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")))))), + LW(128, + 30)), + (Bop(And, + EQ(Var("ExceptionType", + CTy"ExceptionType"), + LC("C2E", + CTy"ExceptionType")), + Bop(Or, + EQ(Dest + ("ExcCode", + F8, + Mop(Fst, + Apply + (Const + ("capcause", + ATy(qTy, + PTy(CTy"CapCause", + qTy))), + qVar"s"))), + LW(5, + 8)), + EQ(Dest + ("ExcCode", + F8, + Mop(Fst, + Apply + (Const + ("capcause", + ATy(qTy, + PTy(CTy"CapCause", + qTy))), + qVar"s"))), + LW(6, + 8)))), + LW(640, + 30))], + LW(384, + 30)))]), + Mop(Snd, + Apply + (Call + ("write'PCC", + ATy(qTy, + PTy(uTy, + qTy)), + Mop(Fst, + Apply + (Const + ("KCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))), + qVar"s0"))), + qVar"s0"))))))))))))))))) +; +val SignalCP2UnusableException_def = Def + ("SignalCP2UnusableException",qVar"state", + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Cause", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("CE", + TP[Dest + ("Cause",CTy"CauseRegister", + Var("v",CTy"CP0__renamed__")),LW(2,2)])])), + qVar"state"))))) +; +val SignalCapException_internal_def = Def + ("SignalCapException_internal", + TP[Var("capException",CTy"CapException"),Var("regNum",F8)], + Close + (qVar"state", + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'capcause",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("ExcCode", + TP[Mop(Fst, + Apply + (Const + ("capcause", + ATy(qTy,PTy(CTy"CapCause",qTy))), + qVar"state")), + CS(Var("capException",CTy"CapException"), + [(LC("capExcNone",CTy"CapException"),LW(0,8)), + (LC("capExcLength",CTy"CapException"), + LW(1,8)), + (LC("capExcTag",CTy"CapException"),LW(2,8)), + (LC("capExcSeal",CTy"CapException"),LW(3,8)), + (LC("capExcType",CTy"CapException"),LW(4,8)), + (LC("capExcCall",CTy"CapException"),LW(5,8)), + (LC("capExcRet",CTy"CapException"),LW(6,8)), + (LC("capExcUnderflowTSS",CTy"CapException"), + LW(7,8)), + (LC("capExcUser",CTy"CapException"),LW(8,8)), + (LC("capExcTLBNoStore",CTy"CapException"), + LW(9,8)), + (LC("capExcGlobal",CTy"CapException"), + LW(16,8)), + (LC("capExcPermExe",CTy"CapException"), + LW(17,8)), + (LC("capExcPermLoad",CTy"CapException"), + LW(18,8)), + (LC("capExcPermStore",CTy"CapException"), + LW(19,8)), + (LC("capExcPermLoadCap",CTy"CapException"), + LW(20,8)), + (LC("capExcPermStoreCap",CTy"CapException"), + LW(21,8)), + (LC("capExcPermStoreLocalCap", + CTy"CapException"),LW(22,8)), + (LC("capExcPermSeal",CTy"CapException"), + LW(23,8)), + (LC("capExcPermSetType",CTy"CapException"), + LW(24,8)), + (LC("capExcAccEPCC",CTy"CapException"), + LW(26,8)), + (LC("capExcAccKDC",CTy"CapException"), + LW(27,8)), + (LC("capExcAccKCC",CTy"CapException"), + LW(28,8)), + (LC("capExcAccKR1C",CTy"CapException"), + LW(29,8)), + (LC("capExcAccKR2C",CTy"CapException"), + LW(30,8))])])),qVar"state")), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("C2E",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'capcause",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("RegNum", + TP[Mop(Fst, + Apply + (Const + ("capcause", + ATy(qTy,PTy(CTy"CapCause",qTy))), + qVar"s")),Var("regNum",F8)])),qVar"s")))))) +; +val SignalCapException_def = Def + ("SignalCapException", + TP[Var("capException",CTy"CapException"),Var("regNum",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("SignalCapException_internal",ATy(qTy,PTy(uTy,qTy)), + TP[Var("capException",CTy"CapException"), + Mop(Cast F8,Var("regNum",FTy 5))]),qVar"state"))) +; +val SignalCapException_noReg_def = Def + ("SignalCapException_noReg",Var("capException",CTy"CapException"), + Close + (qVar"state", + Apply + (Call + ("SignalCapException_internal",ATy(qTy,PTy(uTy,qTy)), + TP[Var("capException",CTy"CapException"),LW(255,8)]), + qVar"state"))) +; +val SignalCapException_v_def = Def + ("SignalCapException_v",Var("regNum",FTy 5), + Close + (qVar"state", + CS(Var("regNum",FTy 5), + [(LW(31,5), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcAccEPCC",CTy"CapException"), + Mop(Cast(FTy 5),Var("regNum",FTy 5))]),qVar"state")), + (LW(30,5), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcAccKDC",CTy"CapException"), + Mop(Cast(FTy 5),Var("regNum",FTy 5))]),qVar"state")), + (LW(29,5), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcAccKCC",CTy"CapException"), + Mop(Cast(FTy 5),Var("regNum",FTy 5))]),qVar"state")), + (LW(27,5), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcAccKR1C",CTy"CapException"), + Mop(Cast(FTy 5),Var("regNum",FTy 5))]),qVar"state")), + (LW(28,5), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcAccKR2C",CTy"CapException"), + Mop(Cast(FTy 5),Var("regNum",FTy 5))]),qVar"state")), + (AVar(FTy 5),TP[LU,qVar"state"])]))) +; +val dfn'ERET_def = Def + ("dfn'ERET",qVar"state", + ITE(Bop(Or, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))),qVar"state"))), + Let(qVar"s", + Mop(Snd, + Apply + (Call("write'LLbit",ATy(qTy,PTy(uTy,qTy)),Mop(Some,LF)), + ITE(Dest + ("ERL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Sub, + Dest + ("ErrorEPC",F64, + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"state"))),LW(4,64))), + qVar"state")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Status", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("ERL", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LF])])),qVar"s")))), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Sub, + Dest + ("EPC",F64, + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"state"))),LW(4,64))), + qVar"state")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Status", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("EXL", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LF])])),qVar"s"))))))), + Apply + (Call + ("write'PCC",ATy(qTy,PTy(uTy,qTy)), + Mop(Fst, + Apply + (Const("EPCC",ATy(qTy,PTy(CTy"Capability",qTy))), + qVar"s"))),qVar"s")), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state"))) +; +val TLBEntries_def = Def0 ("TLBEntries",LN 16) +; +val TLB_direct_def = Def + ("TLB_direct",Var("i",FTy 7), + Close + (qVar"state", + TP[Apply + (Apply + (Dest + ("c_TLB_direct",ATy(F8,ATy(FTy 7,CTy"TLBEntry")), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("i",FTy 7)),qVar"state"])) +; +val write'TLB_direct_def = Def + ("write'TLB_direct",TP[Var("value",CTy"TLBEntry"),Var("i",FTy 7)], + Close + (qVar"state", + TP[LU, + Let(Var("s",PTy(ATy(FTy 7,CTy"TLBEntry"),qTy)), + TP[Fupd + (Apply + (Dest + ("c_TLB_direct",ATy(F8,ATy(FTy 7,CTy"TLBEntry")), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("i",FTy 7),Var("value",CTy"TLBEntry")),qVar"state"], + Rupd + ("c_TLB_direct", + TP[Mop(Snd,Var("s",PTy(ATy(FTy 7,CTy"TLBEntry"),qTy))), + Fupd + (Dest + ("c_TLB_direct",ATy(F8,ATy(FTy 7,CTy"TLBEntry")), + Mop(Snd, + Var("s",PTy(ATy(FTy 7,CTy"TLBEntry"),qTy)))), + Dest + ("procID",F8, + Mop(Snd, + Var("s",PTy(ATy(FTy 7,CTy"TLBEntry"),qTy)))), + Mop(Fst,Var("s",PTy(ATy(FTy 7,CTy"TLBEntry"),qTy))))]))])) +; +val TLB_assoc_def = Def + ("TLB_assoc",Var("i",F4), + Close + (qVar"state", + TP[Apply + (Apply + (Dest + ("c_TLB_assoc",ATy(F8,ATy(F4,CTy"TLBEntry")),qVar"state"), + Dest("procID",F8,qVar"state")),Var("i",F4)),qVar"state"])) +; +val write'TLB_assoc_def = Def + ("write'TLB_assoc",TP[Var("value",CTy"TLBEntry"),Var("i",F4)], + Close + (qVar"state", + TP[LU, + Let(Var("s",PTy(ATy(F4,CTy"TLBEntry"),qTy)), + TP[Fupd + (Apply + (Dest + ("c_TLB_assoc",ATy(F8,ATy(F4,CTy"TLBEntry")), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("i",F4),Var("value",CTy"TLBEntry")),qVar"state"], + Rupd + ("c_TLB_assoc", + TP[Mop(Snd,Var("s",PTy(ATy(F4,CTy"TLBEntry"),qTy))), + Fupd + (Dest + ("c_TLB_assoc",ATy(F8,ATy(F4,CTy"TLBEntry")), + Mop(Snd,Var("s",PTy(ATy(F4,CTy"TLBEntry"),qTy)))), + Dest + ("procID",F8, + Mop(Snd,Var("s",PTy(ATy(F4,CTy"TLBEntry"),qTy)))), + Mop(Fst,Var("s",PTy(ATy(F4,CTy"TLBEntry"),qTy))))]))])) +; +val LookupTLB_def = Def + ("LookupTLB",TP[Var("r",FTy 2),Var("vpn2",FTy 27)], + Close + (qVar"state", + Let(Var("v",CTy"TLBEntry"), + Mop(Fst, + Apply + (Call + ("TLB_direct",ATy(qTy,PTy(CTy"TLBEntry",qTy)), + EX(Var("vpn2",FTy 27),LN 6,LN 0,FTy 7)),qVar"state")), + Let(Var("nmask",FTy 27), + Mop(BNot, + Mop(Cast(FTy 27), + Dest("Mask",FTy 12,Var("v",CTy"TLBEntry")))), + Let(TP[Var("r",LTy(PTy(F8,CTy"TLBEntry"))), + Var("s1",PTy(LTy(PTy(F8,CTy"TLBEntry")),qTy))], + Let(TP[Var("v0",CTy"CP0__renamed__"), + Var("s",PTy(LTy(PTy(F8,CTy"TLBEntry")),qTy))], + Let(TP[Var("v",CTy"CP0__renamed__"),qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state")),qVar"state"], + TP[Var("v",CTy"CP0__renamed__"), + LNL(PTy(F8,CTy"TLBEntry")),qVar"s3"]), + Let(Var("s",PTy(LTy(PTy(F8,CTy"TLBEntry")),qTy)), + Mop(Snd, + Apply + (For(TP[LN 0, + Bop(Sub,Const("TLBEntries",nTy), + LN 1), + Close + (nVar"i", + Close + (Var("state", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy)), + Let(TP[Var("v",CTy"TLBEntry"), + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy))], + Let(TP[Var("v", + CTy"TLBEntry"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("TLB_assoc", + ATy(qTy, + PTy(CTy"TLBEntry", + qTy)), + Mop(Cast + F4, + nVar"i")), + Mop(Snd, + Var("state", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy))))), + Mop(Snd, + Var("state", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy)))], + TP[Var("v", + CTy"TLBEntry"), + Mop(Fst, + Var("state", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy))), + qVar"s3"]), + Let(Var("nmask",FTy 27), + Mop(BNot, + Mop(Cast(FTy 27), + Dest + ("Mask", + FTy 12, + Var("v", + CTy"TLBEntry")))), + Let(TP[Var("v0", + CTy"CP0__renamed__"), + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + Mop(Snd, + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy))))), + Mop(Snd, + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy)))], + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy))), + qVar"s3"]), + TP[LU, + ITE(Bop(And, + Bop(And, + EQ(Bop(BAnd, + Dest + ("VPN2", + FTy 27, + Var("v", + CTy"TLBEntry")), + Var("nmask", + FTy 27)), + Bop(BAnd, + Var("vpn2", + FTy 27), + Var("nmask", + FTy 27))), + EQ(Dest + ("R", + FTy 2, + Var("v", + CTy"TLBEntry")), + Var("r", + FTy 2))), + Bop(Or, + Dest + ("G", + bTy, + Var("v", + CTy"TLBEntry")), + EQ(Dest + ("ASID", + F8, + Var("v", + CTy"TLBEntry")), + Dest + ("ASID", + F8, + Dest + ("EntryHi", + CTy"EntryHi", + Var("v0", + CTy"CP0__renamed__")))))), + TP[LLC([TP[Mop(Cast + F8, + nVar"i"), + Var("v", + CTy"TLBEntry")]], + Mop(Fst, + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy)))), + Mop(Snd, + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy)))], + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy)))])))))]), + ITE(Dest + ("LTLB",bTy, + Dest + ("Config6",CTy"ConfigRegister6", + Var("v0",CTy"CP0__renamed__"))), + Let(TP[Var("v0",CTy"CP0__renamed__"), + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + Mop(Snd, + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy))))), + Mop(Snd, + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy)))], + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy))), + qVar"s3"]), + TP[ITE(Bop(And, + Bop(And, + EQ(Bop(BAnd, + Dest + ("VPN2", + FTy 27, + Var("v", + CTy"TLBEntry")), + Var("nmask", + FTy 27)), + Bop(BAnd, + Var("vpn2", + FTy 27), + Var("nmask", + FTy 27))), + EQ(Dest + ("R",FTy 2, + Var("v", + CTy"TLBEntry")), + Var("r",FTy 2))), + Bop(Or, + Dest + ("G",bTy, + Var("v", + CTy"TLBEntry")), + EQ(Dest + ("ASID",F8, + Var("v", + CTy"TLBEntry")), + Dest + ("ASID",F8, + Dest + ("EntryHi", + CTy"EntryHi", + Var("v0", + CTy"CP0__renamed__")))))), + LL[TP[ITE(Bop(Ge, + Mop(Cast nTy, + EX(Var("vpn2", + FTy 27), + LN 6, + LN 0, + FTy 7)), + Const + ("TLBEntries", + nTy)), + Mop(Cast F8, + EX(Var("vpn2", + FTy 27), + LN 6, + LN 0, + FTy 7)), + Bop(Add, + LW(128,8), + Mop(Cast F8, + EX(Var("vpn2", + FTy 27), + LN 6, + LN 0, + FTy 7)))), + Var("v", + CTy"TLBEntry")]], + LNL(PTy(F8,CTy"TLBEntry"))), + Mop(Snd, + Var("s", + PTy(LTy(PTy(F8, + CTy"TLBEntry")), + qTy)))]), + Var("s", + PTy(LTy(PTy(F8,CTy"TLBEntry")), + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(LTy(PTy(F8,CTy"TLBEntry")),qTy))), + Var("s",PTy(LTy(PTy(F8,CTy"TLBEntry")),qTy))])), + TP[Var("r",LTy(PTy(F8,CTy"TLBEntry"))), + Mop(Snd,Var("s1",PTy(LTy(PTy(F8,CTy"TLBEntry")),qTy)))]))))) +; +val SignalTLBException_def = Def + ("SignalTLBException", + TP[Var("e",CTy"ExceptionType"),Var("asid",F8),Var("vAddr",F64)], + Close + (qVar"state", + Let(Var("r",FTy 2),EX(Var("vAddr",F64),LN 63,LN 62,FTy 2), + Let(Var("vpn2",FTy 27),EX(Var("vAddr",F64),LN 39,LN 13,FTy 27), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + Var("e",CTy"ExceptionType")),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Var("vAddr",F64)])),qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EntryHi", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("R", + TP[Dest + ("EntryHi", + CTy"EntryHi", + Var("v", + CTy"CP0__renamed__")), + Var("r",FTy 2)])])), + qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EntryHi", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("VPN2", + TP[Dest + ("EntryHi", + CTy"EntryHi", + Var("v", + CTy"CP0__renamed__")), + Var("vpn2", + FTy 27)])])), + qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy,qTy)), + Rupd + ("EntryHi", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("ASID", + TP[Dest + ("EntryHi", + CTy"EntryHi", + Var("v", + CTy"CP0__renamed__")), + Var("asid", + F8)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("XContext", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("R", + TP[Dest + ("XContext", + CTy"XContext", + Var("v", + CTy"CP0__renamed__")), + Var("r", + FTy 2)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("XContext", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("BadVPN2", + TP[Dest + ("XContext", + CTy"XContext", + Var("v", + CTy"CP0__renamed__")), + Var("vpn2", + FTy 27)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + TP[LX(PTy(FTy 40, + FTy 3)), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Context", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("BadVPN2", + TP[Dest + ("Context", + CTy"Context", + Var("v", + CTy"CP0__renamed__")), + EX(Var("vAddr", + F64), + LN + 31, + LN + 13, + FTy 19)])])), + qVar"s"))]))))))))))))))))) +; +val CheckSegment_def = Def + ("CheckSegment",Var("vAddr",F64), + Close + (qVar"state", + TP[ITB([(Mop(Fst, + Apply + (Const("UserMode",ATy(qTy,PTy(bTy,qTy))),qVar"state")), + TP[LO(PTy(FTy 40,FTy 3)), + Bop(Ult,Var("vAddr",F64),LW(1099511627776,64))]), + (Mop(Fst, + Apply + (Const("SupervisorMode",ATy(qTy,PTy(bTy,qTy))), + qVar"state")), + TP[LO(PTy(FTy 40,FTy 3)), + Bop(Or, + Bop(Or, + Bop(Ult,Var("vAddr",F64),LW(1099511627776,64)), + Bop(And, + Bop(Ule,Var("vAddr",F64), + LW(4611686018427387904,64)), + Bop(Ult,Var("vAddr",F64), + LW(4611687117939015680,64)))), + Bop(And, + Bop(Ule,Var("vAddr",F64), + LW(18446744072635809792,64)), + Bop(Ult,Var("vAddr",F64), + LW(18446744073172680704,64))))]), + (Bop(Ult,Var("vAddr",F64),LW(1099511627776,64)), + TP[LO(PTy(FTy 40,FTy 3)),LT]), + (Bop(And, + Bop(Ule,LW(4611686018427387904,64),Var("vAddr",F64)), + Bop(Ult,Var("vAddr",F64),LW(4611687117939015680,64))), + TP[LO(PTy(FTy 40,FTy 3)),LT]), + (Bop(And, + Bop(Ule,LW(9223372036854775808,64),Var("vAddr",F64)), + Bop(Ult,Var("vAddr",F64),LW(13835058055282163712,64))), + TP[Mop(Some, + TP[EX(Var("vAddr",F64),LN 39,LN 0,FTy 40), + EX(Var("vAddr",F64),LN 61,LN 59,FTy 3)]), + EQ(EX(Var("vAddr",F64),LN 58,LN 40,FTy 19),LW(0,19))]), + (Bop(And, + Bop(Ule,LW(13835058055282163712,64),Var("vAddr",F64)), + Bop(Ult,Var("vAddr",F64),LW(13835059152646307840,64))), + TP[LO(PTy(FTy 40,FTy 3)),LT]), + (Bop(And, + Bop(Ule,LW(18446744071562067968,64),Var("vAddr",F64)), + Bop(Ult,Var("vAddr",F64),LW(18446744072098938880,64))), + TP[Mop(Some, + TP[Bop(Sub,EX(Var("vAddr",F64),LN 39,LN 0,FTy 40), + LW(1097364144128,40)), + Dest + ("K0",FTy 3, + Dest + ("Config",CTy"ConfigRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))]),LT]), + (Bop(And, + Bop(Ule,LW(18446744072098938880,64),Var("vAddr",F64)), + Bop(Ult,Var("vAddr",F64),LW(18446744072635809792,64))), + TP[Mop(Some, + TP[Bop(Sub,EX(Var("vAddr",F64),LN 39,LN 0,FTy 40), + LW(1097901015040,40)),LW(2,3)]),LT])], + TP[LO(PTy(FTy 40,FTy 3)), + Bop(Ule,LW(18446744072635809792,64),Var("vAddr",F64))]), + qVar"state"])) +; +val AddressTranslation_def = Def + ("AddressTranslation", + TP[Var("vAddr",F64),Var("IorD",CTy"IorD"), + Var("AccessType",CTy"AccessType")], + Close + (qVar"state", + Let(TP[Var("unmapped",OTy(PTy(FTy 40,FTy 3))),bVar"valid"], + Mop(Fst, + Apply + (Call + ("CheckSegment", + ATy(qTy,PTy(PTy(OTy(PTy(FTy 40,FTy 3)),bTy),qTy)), + Var("vAddr",F64)),qVar"state")), + ITE(bVar"valid", + CS(Var("unmapped",OTy(PTy(FTy 40,FTy 3))), + [(Mop(Some,TP[Var("pAddr",FTy 40),Var("cca",FTy 3)]), + TP[TP[Var("pAddr",FTy 40),Var("cca",FTy 3),LF,LF], + qVar"state"]), + (LO(PTy(FTy 40,FTy 3)), + CS(Mop(Fst, + Apply + (Call + ("LookupTLB", + ATy(qTy, + PTy(LTy(PTy(F8,CTy"TLBEntry")),qTy)), + TP[EX(Var("vAddr",F64),LN 63,LN 62,FTy 2), + EX(Var("vAddr",F64),LN 39,LN 13,FTy 27)]), + qVar"state")), + [(LNL(PTy(F8,CTy"TLBEntry")), + Let(TP[Var("v",PTy(FTy 40,FTy 3)),qVar"s"], + Apply + (Call + ("SignalTLBException", + ATy(qTy,PTy(PTy(FTy 40,FTy 3),qTy)), + TP[ITE(EQ(Var("AccessType", + CTy"AccessType"), + LC("LOAD",CTy"AccessType")), + LC("XTLBRefillL", + CTy"ExceptionType"), + LC("XTLBRefillS", + CTy"ExceptionType")), + Dest + ("ASID",F8, + Dest + ("EntryHi",CTy"EntryHi", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"state")))), + Var("vAddr",F64)]),qVar"state"), + TP[LX(PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + qVar"s"])), + (LL[TP[AVar F8,Var("e",CTy"TLBEntry")]], + Let(TP[nVar"v",qVar"s"], + CS(Dest("Mask",FTy 12,Var("e",CTy"TLBEntry")), + [(LW(0,12),TP[LN 12,qVar"state"]), + (LW(3,12),TP[LN 14,qVar"state"]), + (LW(15,12),TP[LN 16,qVar"state"]), + (LW(63,12),TP[LN 18,qVar"state"]), + (LW(255,12),TP[LN 20,qVar"state"]), + (LW(1023,12),TP[LN 22,qVar"state"]), + (LW(4095,12),TP[LN 24,qVar"state"]), + (AVar(FTy 12), + Apply + (Call + ("raise'exception", + ATy(qTy,PTy(nTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"TLB: bad mask")),qVar"state"))]), + Let(TP[bVar"S",bVar"L",Var("PFN",FTy 28), + Var("C",FTy 3),bVar"D",bVar"V"], + ITE(Bop(Bit,Var("vAddr",F64),nVar"v"), + TP[Dest + ("S1",bTy,Var("e",CTy"TLBEntry")), + Dest + ("L1",bTy,Var("e",CTy"TLBEntry")), + Dest + ("PFN1",FTy 28, + Var("e",CTy"TLBEntry")), + Dest + ("C1",FTy 3, + Var("e",CTy"TLBEntry")), + Dest + ("D1",bTy,Var("e",CTy"TLBEntry")), + Dest + ("V1",bTy,Var("e",CTy"TLBEntry"))], + TP[Dest + ("S0",bTy,Var("e",CTy"TLBEntry")), + Dest + ("L0",bTy,Var("e",CTy"TLBEntry")), + Dest + ("PFN0",FTy 28, + Var("e",CTy"TLBEntry")), + Dest + ("C0",FTy 3, + Var("e",CTy"TLBEntry")), + Dest + ("D0",bTy,Var("e",CTy"TLBEntry")), + Dest + ("V0",bTy,Var("e",CTy"TLBEntry"))]), + ITE(bVar"V", + ITE(Bop(And,Mop(Not,bVar"D"), + EQ(Var("AccessType", + CTy"AccessType"), + LC("STORE",CTy"AccessType"))), + Let(TP[Var("v",PTy(FTy 40,FTy 3)), + qVar"s"], + Apply + (Call + ("SignalTLBException", + ATy(qTy, + PTy(PTy(FTy 40,FTy 3), + qTy)), + TP[LC("Mod", + CTy"ExceptionType"), + Dest + ("ASID",F8, + Var("e", + CTy"TLBEntry")), + Var("vAddr",F64)]), + qVar"s"), + TP[LX(PTy(FTy 40, + PTy(FTy 3, + PTy(bTy,bTy)))), + qVar"s"]), + TP[TP[Mop(Cast(FTy 40), + CC[EX(Mop(Cast vTy, + Var("PFN", + FTy 28)), + LN 27, + Bop(Sub,nVar"v", + LN 12),vTy), + EX(Mop(Cast vTy, + Var("vAddr", + F64)), + Bop(Sub,nVar"v", + LN 1),LN 0,vTy)]), + Var("C",FTy 3),bVar"S", + bVar"L"],qVar"s"]), + Let(TP[Var("v",PTy(FTy 40,FTy 3)), + qVar"s"], + Apply + (Call + ("SignalTLBException", + ATy(qTy, + PTy(PTy(FTy 40,FTy 3), + qTy)), + TP[ITE(EQ(Var("AccessType", + CTy"AccessType"), + LC("LOAD", + CTy"AccessType")), + LC("TLBL", + CTy"ExceptionType"), + LC("TLBS", + CTy"ExceptionType")), + Dest + ("ASID",F8, + Var("e",CTy"TLBEntry")), + Var("vAddr",F64)]), + qVar"s"), + TP[LX(PTy(FTy 40, + PTy(FTy 3,PTy(bTy,bTy)))), + qVar"s"]))))), + (AVar(LTy(PTy(F8,CTy"TLBEntry"))), + Apply + (Call + ("raise'exception", + ATy(qTy, + PTy(PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy))), + qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"TLB: multiple matches")),qVar"state"))]))]), + TP[LX(PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + Mop(Snd, + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + ITE(EQ(Var("AccessType",CTy"AccessType"), + LC("LOAD",CTy"AccessType")), + LC("AdEL",CTy"ExceptionType"), + LC("AdES",CTy"ExceptionType"))), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"state")), + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))), + qVar"state"))), + Var("vAddr",F64))])), + qVar"state"))))])))) +; +val ModifyTLB_def = Def + ("ModifyTLB",Var("ie",CTy"TLBEntry"), + Close + (qVar"state", + Let(Var("v",CTy"EntryHi"), + Dest + ("EntryHi",CTy"EntryHi", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))), + Let(Var("v0",CTy"EntryLo"), + Dest + ("EntryLo1",CTy"EntryLo", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))), + Let(Var("v1",CTy"EntryLo"), + Dest + ("EntryLo0",CTy"EntryLo", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))), + Let(TP[Var("r",CTy"TLBEntry"), + Var("s1",PTy(CTy"TLBEntry",qTy))], + Let(Var("s",PTy(CTy"TLBEntry",qTy)), + TP[Var("ie",CTy"TLBEntry"),qVar"state"], + Let(Var("s",PTy(CTy"TLBEntry",qTy)), + Let(TP[Var("v",CTy"TLBEntry"), + Var("s",PTy(CTy"TLBEntry",qTy))], + Let(TP[Var("v",PTy(CTy"TLBEntry",FTy 12)), + Var("s",PTy(CTy"TLBEntry",qTy))], + Let(TP[Var("v0",CTy"CP0__renamed__"), + Var("s", + PTy(CTy"TLBEntry",qTy))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy))))), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + qVar"s3"]), + TP[TP[Var("ie",CTy"TLBEntry"), + Dest + ("Mask",FTy 12, + Dest + ("PageMask", + CTy"PageMask", + Var("v0", + CTy"CP0__renamed__")))], + Var("s", + PTy(CTy"TLBEntry",qTy))]), + TP[Rupd + ("Mask", + Var("v", + PTy(CTy"TLBEntry",FTy 12))), + Var("s",PTy(CTy"TLBEntry",qTy))]), + TP[Var("v",CTy"TLBEntry"), + Mop(Snd, + Var("s",PTy(CTy"TLBEntry",qTy)))]), + Let(Var("s",PTy(CTy"TLBEntry",qTy)), + TP[Rupd + ("R", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry",qTy))), + Dest + ("R",FTy 2, + Var("v",CTy"EntryHi"))]), + Mop(Snd, + Var("s",PTy(CTy"TLBEntry",qTy)))], + Let(Var("s",PTy(CTy"TLBEntry",qTy)), + TP[Rupd + ("VPN2", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("VPN2",FTy 27, + Var("v",CTy"EntryHi"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry",qTy)))], + Let(Var("s",PTy(CTy"TLBEntry",qTy)), + TP[Rupd + ("ASID", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("ASID",F8, + Var("v",CTy"EntryHi"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry",qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry",qTy)), + TP[Rupd + ("S1", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("S",bTy, + Var("v0", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("L1", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("L",bTy, + Var("v0", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("PFN1", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("PFN", + FTy 28, + Var("v0", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("C1", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("C", + FTy 3, + Var("v0", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("D1", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("D", + bTy, + Var("v0", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("V1", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("V", + bTy, + Var("v0", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("G", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Bop(And, + Dest + ("G", + bTy, + Var("v0", + CTy"EntryLo")), + Dest + ("G", + bTy, + Var("v1", + CTy"EntryLo")))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("S0", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("S", + bTy, + Var("v1", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("L0", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("L", + bTy, + Var("v1", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("PFN0", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("PFN", + FTy 28, + Var("v1", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("C0", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("C", + FTy 3, + Var("v1", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("D0", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("D", + bTy, + Var("v1", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + Let(Var("s", + PTy(CTy"TLBEntry", + qTy)), + TP[Rupd + ("V0", + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Dest + ("V", + bTy, + Var("v1", + CTy"EntryLo"))]), + Mop(Snd, + Var("s", + PTy(CTy"TLBEntry", + qTy)))], + TP[Mop(Fst, + Var("s", + PTy(CTy"TLBEntry", + qTy))), + Var("s", + PTy(CTy"TLBEntry", + qTy))])))))))))))))))))), + TP[Var("r",CTy"TLBEntry"), + Mop(Snd,Var("s1",PTy(CTy"TLBEntry",qTy)))])))))) +; +val dfn'TLBR_def = Def + ("dfn'TLBR",qVar"state", + ITE(Bop(And, + Mop(Not, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Mop(Not, + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))), + qVar"state")))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state"), + Let(Var("v",F8), + Dest + ("Index",F8, + Dest + ("Index",CTy"Index", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Let(Var("v",CTy"TLBEntry"), + ITE(Bop(Ge,Mop(Cast nTy,Var("v",F8)), + Const("TLBEntries",nTy)), + Mop(Fst, + Apply + (Call + ("TLB_direct",ATy(qTy,PTy(CTy"TLBEntry",qTy)), + EX(Var("v",F8),LN 6,LN 0,FTy 7)),qVar"state")), + Mop(Fst, + Apply + (Call + ("TLB_assoc",ATy(qTy,PTy(CTy"TLBEntry",qTy)), + Mop(Cast F4,Var("v",F8))),qVar"state"))), + Let(Var("v0",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("PageMask", + TP[Var("v0",CTy"CP0__renamed__"), + Rupd + ("Mask", + TP[Dest + ("PageMask",CTy"PageMask", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("Mask",FTy 12, + Var("v",CTy"TLBEntry"))])])), + qVar"state")), + Let(Var("v0",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EntryHi", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("R", + TP[Dest + ("EntryHi", + CTy"EntryHi", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("R",FTy 2, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EntryHi", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("VPN2", + TP[Dest + ("EntryHi", + CTy"EntryHi", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("VPN2", + FTy 27, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy,qTy)), + Rupd + ("EntryHi", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("ASID", + TP[Dest + ("EntryHi", + CTy"EntryHi", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("ASID", + F8, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo1", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("S", + TP[Dest + ("EntryLo1", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("S1", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo1", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("L", + TP[Dest + ("EntryLo1", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("L1", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo1", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("PFN", + TP[Dest + ("EntryLo1", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("PFN1", + FTy 28, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo1", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("C", + TP[Dest + ("EntryLo1", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("C1", + FTy 3, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo1", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("D", + TP[Dest + ("EntryLo1", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("D1", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo1", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("V", + TP[Dest + ("EntryLo1", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("V1", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo1", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("G", + TP[Dest + ("EntryLo1", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("G", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo0", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("S", + TP[Dest + ("EntryLo0", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("S0", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo0", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("L", + TP[Dest + ("EntryLo0", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("L0", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo0", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("PFN", + TP[Dest + ("EntryLo0", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("PFN0", + FTy 28, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo0", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("C", + TP[Dest + ("EntryLo0", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("C0", + FTy 3, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo0", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("D", + TP[Dest + ("EntryLo0", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("D0", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo0", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("V", + TP[Dest + ("EntryLo0", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("V0", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")), + Let(Var("v0", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("EntryLo0", + TP[Var("v0", + CTy"CP0__renamed__"), + Rupd + ("G", + TP[Dest + ("EntryLo0", + CTy"EntryLo", + Var("v0", + CTy"CP0__renamed__")), + Dest + ("G", + bTy, + Var("v", + CTy"TLBEntry"))])])), + qVar"s")))))))))))))))))))))))))))))))))))))))) +; +val dfn'TLBP_def = Def + ("dfn'TLBP",qVar"state", + ITE(Bop(And, + Mop(Not, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Mop(Not, + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))), + qVar"state")))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state"), + CS(Mop(Fst, + Apply + (Call + ("LookupTLB", + ATy(qTy,PTy(LTy(PTy(F8,CTy"TLBEntry")),qTy)), + TP[Dest + ("R",FTy 2, + Dest + ("EntryHi",CTy"EntryHi", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Dest + ("VPN2",FTy 27, + Dest + ("EntryHi",CTy"EntryHi", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))]),qVar"state")), + [(LNL(PTy(F8,CTy"TLBEntry")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Index", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("P", + TP[Dest + ("Index",CTy"Index", + Var("v",CTy"CP0__renamed__")), + LT])])),qVar"state")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Index", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("Index", + TP[Dest + ("Index",CTy"Index", + Var("v",CTy"CP0__renamed__")), + LX F8])])),qVar"s"))))), + (LL[TP[Var("i",F8),Var("e",CTy"TLBEntry")]], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Index", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("P", + TP[Dest + ("Index",CTy"Index", + Var("v",CTy"CP0__renamed__")), + LF])])),qVar"state")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Index", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("Index", + TP[Dest + ("Index",CTy"Index", + Var("v",CTy"CP0__renamed__")), + Var("i",F8)])])),qVar"s"))))), + (AVar(LTy(PTy(F8,CTy"TLBEntry"))), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"TLB: multiple matches")),qVar"state"))]))) +; +val dfn'TLBWI_def = Def + ("dfn'TLBWI",qVar"state", + ITB([(Bop(And, + Mop(Not, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Mop(Not, + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))), + qVar"state")))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state")), + (Bop(Ge, + Mop(Cast nTy, + Dest + ("Index",F8, + Dest + ("Index",CTy"Index", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),Const("TLBEntries",nTy)), + Let(Var("v",FTy 7), + EX(Dest + ("VPN2",FTy 27, + Dest + ("EntryHi",CTy"EntryHi", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),LN 6,LN 0,FTy 7), + Apply + (Call + ("write'TLB_direct",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("ModifyTLB", + ATy(qTy,PTy(CTy"TLBEntry",qTy)), + Mop(Fst, + Apply + (Call + ("TLB_direct", + ATy(qTy,PTy(CTy"TLBEntry",qTy)), + Var("v",FTy 7)),qVar"state"))), + qVar"state")),Var("v",FTy 7)]),qVar"state")))], + Let(Var("v",F4), + Mop(Cast F4, + Dest + ("Index",F8, + Dest + ("Index",CTy"Index", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Call + ("write'TLB_assoc",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("ModifyTLB",ATy(qTy,PTy(CTy"TLBEntry",qTy)), + Mop(Fst, + Apply + (Call + ("TLB_assoc", + ATy(qTy,PTy(CTy"TLBEntry",qTy)), + Var("v",F4)),qVar"state"))), + qVar"state")),Var("v",F4)]),qVar"state")))) +; +val dfn'TLBWR_def = Def + ("dfn'TLBWR",qVar"state", + ITB([(Bop(And, + Mop(Not, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Mop(Not, + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))), + qVar"state")))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state")), + (Dest + ("LTLB",bTy, + Dest + ("Config6",CTy"ConfigRegister6", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Let(Var("v",FTy 7), + EX(Dest + ("VPN2",FTy 27, + Dest + ("EntryHi",CTy"EntryHi", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),LN 6,LN 0,FTy 7), + Let(Var("v0",CTy"TLBEntry"), + Mop(Fst, + Apply + (Call + ("TLB_direct",ATy(qTy,PTy(CTy"TLBEntry",qTy)), + Var("v",FTy 7)),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'TLB_direct",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("ModifyTLB", + ATy(qTy,PTy(CTy"TLBEntry",qTy)), + Var("v0",CTy"TLBEntry")), + qVar"state")),Var("v",FTy 7)]), + qVar"state")), + ITE(Bop(And,Dest("V0",bTy,Var("v0",CTy"TLBEntry")), + Dest("V1",bTy,Var("v0",CTy"TLBEntry"))), + Apply + (Call + ("write'TLB_assoc",ATy(qTy,PTy(uTy,qTy)), + TP[Var("v0",CTy"TLBEntry"), + Mop(Cast F4, + Dest + ("Random",F8, + Dest + ("Random",CTy"Random", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")))))]),qVar"s"), + TP[LU,qVar"s"])))))], + Let(Var("v",F8), + Dest + ("Random",F8, + Dest + ("Random",CTy"Random", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Apply + (Call + ("write'TLB_assoc",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("ModifyTLB",ATy(qTy,PTy(CTy"TLBEntry",qTy)), + Mop(Fst, + Apply + (Call + ("TLB_assoc", + ATy(qTy,PTy(CTy"TLBEntry",qTy)), + Mop(Cast F4,Var("v",F8))), + qVar"state"))),qVar"state")), + Mop(Cast F4,Var("v",F8))]),qVar"state")))) +; +val r_def = Def + ("r",Var("n",FTy 5),CC[LS"$",Mop(Cast sTy,Mop(Cast nTy,Var("n",FTy 5)))]) +; +val c_def = Def + ("c",Var("n",FTy 5),CC[LS", ",Call("r",sTy,Var("n",FTy 5))]) +; +val i_def = Def + ("i",Var("n",BTy"N"), + CC[LS", ",ITE(Bop(Ult,Var("n",BTy"N"),LY(10,"N")),LS"",LS"0x"), + Mop(Cast sTy,Var("n",BTy"N"))]) +; +val oi_def = Def + ("oi",Var("n",BTy"N"), + ITE(EQ(Var("n",BTy"N"),LY(0,"N")),LS"",Call("i",sTy,Var("n",BTy"N")))) +; +val op1i_def = Def + ("op1i",TP[sVar"s",Var("n",BTy"N")], + CC[Mop(PadRight,TP[LSC #" ",LN 12,sVar"s"]),LS"0x", + Mop(Cast sTy,Var("n",BTy"N"))]) +; +val op1r_def = Def + ("op1r",TP[sVar"s",Var("n",FTy 5)], + CC[Mop(PadRight,TP[LSC #" ",LN 12,sVar"s"]), + Call("r",sTy,Var("n",FTy 5))]) +; +val op1ri_def = Def + ("op1ri",TP[sVar"s",Var("r1",FTy 5),Var("n",BTy"N")], + CC[Call("op1r",sTy,TP[sVar"s",Var("r1",FTy 5)]), + Call("i",sTy,Var("n",BTy"N"))]) +; +val op2r_def = Def + ("op2r",TP[sVar"s",Var("r1",FTy 5),Var("r2",FTy 5)], + CC[Call("op1r",sTy,TP[sVar"s",Var("r1",FTy 5)]), + Call("c",sTy,Var("r2",FTy 5))]) +; +val op2ri_def = Def + ("op2ri",TP[sVar"s",Var("r1",FTy 5),Var("r2",FTy 5),Var("n",BTy"N")], + CC[Call("op2r",sTy,TP[sVar"s",Var("r1",FTy 5),Var("r2",FTy 5)]), + Call("i",sTy,Var("n",BTy"N"))]) +; +val op3r_def = Def + ("op3r",TP[sVar"s",Var("r1",FTy 5),Var("r2",FTy 5),Var("r3",FTy 5)], + CC[Call("op2r",sTy,TP[sVar"s",Var("r1",FTy 5),Var("r2",FTy 5)]), + Call("c",sTy,Var("r3",FTy 5))]) +; +val op3ro_def = Def + ("op3ro", + TP[sVar"s",Var("r1",FTy 5),Var("r2",FTy 5),Var("r3",FTy 5), + Var("n",BTy"N")], + CC[Call("op2r",sTy,TP[sVar"s",Var("r1",FTy 5),Var("r2",FTy 5)]), + Call("i",sTy,Var("n",BTy"N")),LS"(",Call("r",sTy,Var("r3",FTy 5)), + LS")"]) +; +val op2roi_def = Def + ("op2roi",TP[sVar"s",Var("r1",FTy 5),Var("r2",FTy 5),Var("n",BTy"N")], + CC[Call("op1r",sTy,TP[sVar"s",Var("r1",FTy 5)]),LS", ", + Call("cpr",sTy,Var("r2",FTy 5)),Call("oi",sTy,Var("n",BTy"N"))]) +; +val opmem_def = Def + ("opmem",TP[sVar"s",Var("r1",FTy 5),Var("r2",FTy 5),Var("n",BTy"N")], + CC[Call("op1ri",sTy,TP[sVar"s",Var("r1",FTy 5),Var("n",BTy"N")]),LS"(", + Call("r",sTy,Var("r2",FTy 5)),LS")"]) +; +val form1_def = Def + ("form1", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + Var("function",FTy 6)], + CC[LW(0,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5), + Var("imm5",FTy 5),Var("function",FTy 6)]) +; +val form2_def = Def + ("form2",TP[Var("rs",FTy 5),Var("function",FTy 5),Var("imm",F16)], + CC[LW(1,6),Var("rs",FTy 5),Var("function",FTy 5),Var("imm",F16)]) +; +val form3_def = Def + ("form3", + TP[Var("function",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5), + Var("sel",FTy 3)], + CC[LW(16,6),Var("function",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5), + LW(0,8),Var("sel",FTy 3)]) +; +val form4_def = Def + ("form4", + TP[Var("function",FTy 6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)], + CC[Var("function",FTy 6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)]) +; +val form5_def = Def + ("form5", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5), + Var("function",FTy 6)], + CC[LW(28,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + Var("function",FTy 6)]) +; +val form6_def = Def + ("form6",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("function",FTy 6)], + CC[LW(31,6),LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + Var("function",FTy 6)]) +; +val PSIZE_def = Def0 ("PSIZE",LN 40) +; +val GPR_def = Def + ("GPR",Var("n",FTy 5), + Close + (qVar"state", + TP[ITE(EQ(Var("n",FTy 5),LW(0,5)),LW(0,64), + Mop(Fst, + Apply + (Call("gpr",ATy(qTy,PTy(F64,qTy)),Var("n",FTy 5)), + qVar"state"))),qVar"state"])) +; +val write'GPR_def = Def + ("write'GPR",TP[Var("value",F64),Var("n",FTy 5)], + Close + (qVar"state", + ITE(Mop(Not,EQ(Var("n",FTy 5),LW(0,5))), + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 2, + Call + ("log_w_gpr",sTy,TP[Var("n",FTy 5),Var("value",F64)])]), + Mop(Snd, + Apply + (Call + ("write'gpr",ATy(qTy,PTy(uTy,qTy)), + TP[Var("value",F64),Var("n",FTy 5)]),qVar"state"))), + TP[LU,qVar"state"]))) +; +val dumpRegs_def = Def + ("dumpRegs",AVar uTy, + Close + (qVar"state", + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 0,LS"====== Registers ======"]),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 0, + CC[LS"Core = ", + Mop(Cast sTy, + Mop(Cast nTy,Dest("procID",F8,qVar"s")))]]), + qVar"s")), + Apply + (For(TP[LN 0,LN 31, + Close + (nVar"i", + Close + (qVar"state", + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 0, + CC[LS"Reg ", + ITE(Bop(Lt,nVar"i",LN 10),LS" ", + LS""),Mop(Cast sTy,nVar"i"), + LS" ", + Call + ("hex64",sTy, + Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy, + PTy(F64,qTy)), + Mop(Cast(FTy 5), + nVar"i")), + qVar"state")))]]), + qVar"state")))]), + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 0, + CC[LS"PC ", + Call + ("hex64",sTy, + Mop(Fst, + Apply + (Const + ("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")))]]),qVar"s"))))))) +; +val HI_def = Def + ("HI",qVar"state", + CS(Mop(Fst,Apply(Const("hi",ATy(qTy,PTy(OTy F64,qTy))),qVar"state")), + [(Mop(Some,Var("v",F64)),TP[Var("v",F64),qVar"state"]), + (LO F64,TP[LX F64,qVar"state"])])) +; +val write'HI_def = Def + ("write'HI",Var("value",F64), + Close + (qVar"state", + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 2,Call("log_w_hi",sTy,Var("value",F64))]), + Mop(Snd, + Apply + (Call + ("write'hi",ATy(qTy,PTy(uTy,qTy)), + Mop(Some,Var("value",F64))),qVar"state"))))) +; +val LO_def = Def + ("LO",qVar"state", + CS(Mop(Fst,Apply(Const("lo",ATy(qTy,PTy(OTy F64,qTy))),qVar"state")), + [(Mop(Some,Var("v",F64)),TP[Var("v",F64),qVar"state"]), + (LO F64,TP[LX F64,qVar"state"])])) +; +val write'LO_def = Def + ("write'LO",Var("value",F64), + Close + (qVar"state", + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 2,Call("log_w_lo",sTy,Var("value",F64))]), + Mop(Snd, + Apply + (Call + ("write'lo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some,Var("value",F64))),qVar"state"))))) +; +val flip_endian_word_def = Def + ("flip_endian_word",Var("w",F32), + CS(BL(32,Var("w",F32)), + [(TP[bVar"a'7",bVar"a'6",bVar"a'5",bVar"a'4",bVar"a'3",bVar"a'2", + bVar"a'1",bVar"a'0",bVar"b'7",bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0",bVar"c'7",bVar"c'6", + bVar"c'5",bVar"c'4",bVar"c'3",bVar"c'2",bVar"c'1",bVar"c'0", + bVar"d'7",bVar"d'6",bVar"d'5",bVar"d'4",bVar"d'3",bVar"d'2", + bVar"d'1",bVar"d'0"], + CC[Mop(Cast F8, + LL[bVar"d'7",bVar"d'6",bVar"d'5",bVar"d'4",bVar"d'3", + bVar"d'2",bVar"d'1",bVar"d'0"]), + Mop(Cast F8, + LL[bVar"c'7",bVar"c'6",bVar"c'5",bVar"c'4",bVar"c'3", + bVar"c'2",bVar"c'1",bVar"c'0"]), + Mop(Cast F8, + LL[bVar"b'7",bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3", + bVar"b'2",bVar"b'1",bVar"b'0"]), + Mop(Cast F8, + LL[bVar"a'7",bVar"a'6",bVar"a'5",bVar"a'4",bVar"a'3", + bVar"a'2",bVar"a'1",bVar"a'0"])])])) +; +val flip_endian_dword_def = Def + ("flip_endian_dword",Var("dw",F64), + CS(BL(64,Var("dw",F64)), + [(TP[bVar"a'7",bVar"a'6",bVar"a'5",bVar"a'4",bVar"a'3",bVar"a'2", + bVar"a'1",bVar"a'0",bVar"b'7",bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0",bVar"c'7",bVar"c'6", + bVar"c'5",bVar"c'4",bVar"c'3",bVar"c'2",bVar"c'1",bVar"c'0", + bVar"d'7",bVar"d'6",bVar"d'5",bVar"d'4",bVar"d'3",bVar"d'2", + bVar"d'1",bVar"d'0",bVar"e'7",bVar"e'6",bVar"e'5",bVar"e'4", + bVar"e'3",bVar"e'2",bVar"e'1",bVar"e'0",bVar"f'7",bVar"f'6", + bVar"f'5",bVar"f'4",bVar"f'3",bVar"f'2",bVar"f'1",bVar"f'0", + bVar"g'7",bVar"g'6",bVar"g'5",bVar"g'4",bVar"g'3",bVar"g'2", + bVar"g'1",bVar"g'0",bVar"h'7",bVar"h'6",bVar"h'5",bVar"h'4", + bVar"h'3",bVar"h'2",bVar"h'1",bVar"h'0"], + CC[Mop(Cast F8, + LL[bVar"h'7",bVar"h'6",bVar"h'5",bVar"h'4",bVar"h'3", + bVar"h'2",bVar"h'1",bVar"h'0"]), + Mop(Cast F8, + LL[bVar"g'7",bVar"g'6",bVar"g'5",bVar"g'4",bVar"g'3", + bVar"g'2",bVar"g'1",bVar"g'0"]), + Mop(Cast F8, + LL[bVar"f'7",bVar"f'6",bVar"f'5",bVar"f'4",bVar"f'3", + bVar"f'2",bVar"f'1",bVar"f'0"]), + Mop(Cast F8, + LL[bVar"e'7",bVar"e'6",bVar"e'5",bVar"e'4",bVar"e'3", + bVar"e'2",bVar"e'1",bVar"e'0"]), + Mop(Cast F8, + LL[bVar"d'7",bVar"d'6",bVar"d'5",bVar"d'4",bVar"d'3", + bVar"d'2",bVar"d'1",bVar"d'0"]), + Mop(Cast F8, + LL[bVar"c'7",bVar"c'6",bVar"c'5",bVar"c'4",bVar"c'3", + bVar"c'2",bVar"c'1",bVar"c'0"]), + Mop(Cast F8, + LL[bVar"b'7",bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3", + bVar"b'2",bVar"b'1",bVar"b'0"]), + Mop(Cast F8, + LL[bVar"a'7",bVar"a'6",bVar"a'5",bVar"a'4",bVar"a'3", + bVar"a'2",bVar"a'1",bVar"a'0"])])])) +; +val CPR_def = Def + ("CPR",TP[nVar"n",Var("reg",FTy 5),Var("sel",FTy 3)], + Close + (qVar"state", + CS(TP[nVar"n",Var("reg",FTy 5),Var("sel",FTy 3)], + [(TP[LN 0,LW(0,5),LW(0,3)], + TP[Mop(Cast F64, + Call + ("reg'Index",F32, + Dest + ("Index",CTy"Index", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(1,5),LW(0,3)], + TP[Mop(Cast F64, + Call + ("reg'Random",F32, + Dest + ("Random",CTy"Random", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(2,5),LW(0,3)], + TP[Call + ("reg'EntryLo",F64, + Dest + ("EntryLo0",CTy"EntryLo", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(3,5),LW(0,3)], + TP[Call + ("reg'EntryLo",F64, + Dest + ("EntryLo1",CTy"EntryLo", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(4,5),LW(0,3)], + TP[Call + ("reg'Context",F64, + Dest + ("Context",CTy"Context", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(4,5),LW(2,3)], + TP[Dest + ("UsrLocal",F64, + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))),qVar"state"]), + (TP[LN 0,LW(5,5),LW(0,3)], + TP[Mop(Cast F64, + Call + ("reg'PageMask",F32, + Dest + ("PageMask",CTy"PageMask", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(6,5),LW(0,3)], + TP[Mop(Cast F64, + Call + ("reg'Wired",F32, + Dest + ("Wired",CTy"Wired", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(7,5),LW(0,3)], + TP[Mop(Cast F64, + Call + ("reg'HWREna",F32, + Dest + ("HWREna",CTy"HWREna", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(8,5),LW(0,3)], + TP[Dest + ("BadVAddr",F64, + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))),qVar"state"]), + (TP[LN 0,LW(8,5),LW(1,3)], + TP[Mop(Cast F64, + Dest + ("EInstr",F32, + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(9,5),LW(0,3)], + TP[Mop(Cast F64, + Dest + ("Count",F32, + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(10,5),LW(0,3)], + TP[Call + ("reg'EntryHi",F64, + Dest + ("EntryHi",CTy"EntryHi", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(11,5),LW(0,3)], + TP[Mop(Cast F64, + Dest + ("Compare",F32, + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(12,5),LW(0,3)], + TP[Mop(Cast F64, + Call + ("reg'StatusRegister",F32, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(13,5),LW(0,3)], + TP[Mop(Cast F64, + Call + ("reg'CauseRegister",F32, + Dest + ("Cause",CTy"CauseRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(14,5),LW(0,3)], + TP[Dest + ("EPC",F64, + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))),qVar"state"]), + (TP[LN 0,LW(15,5),LW(0,3)], + TP[Mop(Cast F64, + Dest + ("PRId",F32, + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(15,5),LW(1,3)], + TP[Mop(Cast F64, + CC[Mop(Cast F16, + Bop(Sub,Dest("totalCore",nTy,qVar"state"),LN 1)), + Mop(Cast F16,Dest("procID",F8,qVar"state"))]), + qVar"state"]), + (TP[LN 0,LW(15,5),LW(6,3)], + TP[Mop(Cast F64, + CC[Mop(Cast F16, + Bop(Sub,Dest("totalCore",nTy,qVar"state"),LN 1)), + Mop(Cast F16,Dest("procID",F8,qVar"state"))]), + qVar"state"]), + (TP[LN 0,LW(16,5),LW(0,3)], + TP[Mop(Cast F64, + Call + ("reg'ConfigRegister",F32, + Dest + ("Config",CTy"ConfigRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(16,5),LW(1,3)], + TP[Mop(Cast F64, + Call + ("reg'ConfigRegister1",F32, + Dest + ("Config1",CTy"ConfigRegister1", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(16,5),LW(2,3)], + TP[Mop(Cast F64, + Call + ("reg'ConfigRegister2",F32, + Dest + ("Config2",CTy"ConfigRegister2", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(16,5),LW(3,3)], + TP[Mop(Cast F64, + Call + ("reg'ConfigRegister3",F32, + Dest + ("Config3",CTy"ConfigRegister3", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(16,5),LW(4,3)],TP[LW(1,64),qVar"state"]), + (TP[LN 0,LW(16,5),LW(5,3)],TP[LW(1,64),qVar"state"]), + (TP[LN 0,LW(16,5),LW(6,3)], + TP[Mop(Cast F64, + Call + ("reg'ConfigRegister6",F32, + Dest + ("Config6",CTy"ConfigRegister6", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))),qVar"state"]), + (TP[LN 0,LW(17,5),LW(0,3)], + TP[Mop(Cast F64, + Dest + ("LLAddr",F64, + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(20,5),LW(0,3)], + TP[Call + ("reg'XContext",F64, + Dest + ("XContext",CTy"XContext", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(23,5),LW(0,3)], + TP[Mop(Cast F64, + Dest + ("Debug",F32, + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(26,5),LW(0,3)], + TP[Mop(Cast F64, + Dest + ("ErrCtl",F32, + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),qVar"state"]), + (TP[LN 0,LW(30,5),LW(0,3)], + TP[Dest + ("ErrorEPC",F64, + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))),qVar"state"]), + (AVar(PTy(nTy,PTy(FTy 5,FTy 3))),TP[LX F64,qVar"state"])]))) +; +val write'CPR_def = Def + ("write'CPR", + TP[Var("value",F64),nVar"n",Var("reg",FTy 5),Var("sel",FTy 3)], + Close + (qVar"state", + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 2, + Call + ("log_w_c0",sTy, + TP[Var("reg",FTy 5),Var("value",F64)])]), + qVar"state")), + CS(TP[nVar"n",Var("reg",FTy 5),Var("sel",FTy 3)], + [(TP[LN 0,LW(0,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Index", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("Index", + TP[Dest + ("Index",CTy"Index", + Var("v",CTy"CP0__renamed__")), + EX(Var("value",F64),LN 7,LN 0,F8)])])), + qVar"s"))), + (TP[LN 0,LW(2,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EntryLo0", + TP[Var("v",CTy"CP0__renamed__"), + Call + ("write'reg'EntryLo",CTy"EntryLo", + TP[Dest + ("EntryLo0",CTy"EntryLo", + Var("v",CTy"CP0__renamed__")), + Var("value",F64)])])),qVar"s"))), + (TP[LN 0,LW(3,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EntryLo1", + TP[Var("v",CTy"CP0__renamed__"), + Call + ("write'reg'EntryLo",CTy"EntryLo", + TP[Dest + ("EntryLo1",CTy"EntryLo", + Var("v",CTy"CP0__renamed__")), + Var("value",F64)])])),qVar"s"))), + (TP[LN 0,LW(4,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Context", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("PTEBase", + TP[Dest + ("Context",CTy"Context", + Var("v",CTy"CP0__renamed__")), + EX(Var("value",F64),LN 63,LN 23, + FTy 41)])])),qVar"s"))), + (TP[LN 0,LW(4,5),LW(2,3)], + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("UsrLocal", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")),Var("value",F64)])),qVar"s")), + (TP[LN 0,LW(5,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("PageMask", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("Mask", + TP[Dest + ("PageMask",CTy"PageMask", + Var("v",CTy"CP0__renamed__")), + EX(Var("value",F64),LN 24,LN 13, + FTy 12)])])),qVar"s"))), + (TP[LN 0,LW(6,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Wired", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("Wired", + TP[Dest + ("Wired",CTy"Wired", + Var("v", + CTy"CP0__renamed__")), + EX(Var("value",F64),LN 7, + LN 0,F8)])])),qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Random", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("Random", + TP[Dest + ("Random",CTy"Random", + Var("v", + CTy"CP0__renamed__")), + Mop(Cast F8, + Bop(Sub, + Const + ("TLBEntries",nTy), + LN 1))])])),qVar"s"))))), + (TP[LN 0,LW(7,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("HWREna", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("CPUNum", + TP[Dest + ("HWREna",CTy"HWREna", + Var("v", + CTy"CP0__renamed__")), + Bop(Bit,Var("value",F64),LN 0)])])), + qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("HWREna", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("CC", + TP[Dest + ("HWREna", + CTy"HWREna", + Var("v", + CTy"CP0__renamed__")), + Bop(Bit, + Var("value",F64), + LN 2)])])), + qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("HWREna", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("CCRes", + TP[Dest + ("HWREna", + CTy"HWREna", + Var("v", + CTy"CP0__renamed__")), + Bop(Bit, + Var("value", + F64), + LN 3)])])), + qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("HWREna", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("UL", + TP[Dest + ("HWREna", + CTy"HWREna", + Var("v", + CTy"CP0__renamed__")), + Bop(Bit, + Var("value", + F64), + LN 29)])])), + qVar"s"))))))))), + (TP[LN 0,LW(9,5),LW(0,3)], + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Count", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + EX(Var("value",F64),LN 31,LN 0,F32)])),qVar"s")), + (TP[LN 0,LW(10,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EntryHi", + TP[Var("v",CTy"CP0__renamed__"), + Call + ("write'reg'EntryHi",CTy"EntryHi", + TP[Dest + ("EntryHi",CTy"EntryHi", + Var("v",CTy"CP0__renamed__")), + Var("value",F64)])])),qVar"s"))), + (TP[LN 0,LW(11,5),LW(0,3)], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Compare", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + EX(Var("value",F64),LN 31,LN 0,F32)])), + qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Let(qVar"s", + Let(Var("x0",CTy"CauseRegister"), + Dest + ("Cause",CTy"CauseRegister", + Var("v",CTy"CP0__renamed__")), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Cause", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("IP", + TP[Var("x0", + CTy"CauseRegister"), + BFI(LN 7,LN 7, + Mop(Cast F1,LF), + Dest + ("IP",F8, + Var("x0", + CTy"CauseRegister")))])])), + qVar"s"))), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Cause", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("TI", + TP[Dest + ("Cause", + CTy"CauseRegister", + Var("v", + CTy"CP0__renamed__")), + LF])])),qVar"s")))))), + (TP[LN 0,LW(12,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Status", + TP[Var("v",CTy"CP0__renamed__"), + Call + ("write'reg'StatusRegister", + CTy"StatusRegister", + TP[Dest + ("Status",CTy"StatusRegister", + Var("v",CTy"CP0__renamed__")), + EX(Var("value",F64),LN 31,LN 0,F32)])])), + qVar"s"))), + (TP[LN 0,LW(13,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Cause", + TP[Var("v",CTy"CP0__renamed__"), + Call + ("write'reg'CauseRegister", + CTy"CauseRegister", + TP[Dest + ("Cause",CTy"CauseRegister", + Var("v",CTy"CP0__renamed__")), + EX(Var("value",F64),LN 31,LN 0,F32)])])), + qVar"s"))), + (TP[LN 0,LW(14,5),LW(0,3)], + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("EPC", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")),Var("value",F64)])),qVar"s")), + (TP[LN 0,LW(16,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Config", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("K0", + TP[Dest + ("Config",CTy"ConfigRegister", + Var("v",CTy"CP0__renamed__")), + EX(Var("value",F64),LN 2,LN 0,FTy 3)])])), + qVar"s"))), + (TP[LN 0,LW(16,5),LW(2,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Config2", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("SU", + TP[Dest + ("Config2",CTy"ConfigRegister2", + Var("v",CTy"CP0__renamed__")), + EX(Var("value",F64),LN 15,LN 12,F4)])])), + qVar"s"))), + (TP[LN 0,LW(16,5),LW(6,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Config6", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("LTLB", + TP[Dest + ("Config6",CTy"ConfigRegister6", + Var("v",CTy"CP0__renamed__")), + Bop(Bit,Var("value",F64),LN 2)])])), + qVar"s"))), + (TP[LN 0,LW(20,5),LW(0,3)], + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("XContext", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("PTEBase", + TP[Dest + ("XContext",CTy"XContext", + Var("v",CTy"CP0__renamed__")), + EX(Var("value",F64),LN 63,LN 33, + FTy 31)])])),qVar"s"))), + (TP[LN 0,LW(23,5),LW(0,3)], + TP[LU, + Rupd + ("done", + TP[Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Debug", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + EX(Var("value",F64),LN 31,LN 0,F32)])), + qVar"s")),LT])]), + (TP[LN 0,LW(26,5),LW(0,3)], + Apply + (Call("dumpRegs",ATy(qTy,PTy(uTy,qTy)),LU), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("ErrCtl", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + EX(Var("value",F64),LN 31,LN 0,F32)])), + qVar"s")))), + (TP[LN 0,LW(30,5),LW(0,3)], + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("ErrorEPC", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")),Var("value",F64)])),qVar"s")), + (AVar(PTy(nTy,PTy(FTy 5,FTy 3))), + Apply + (Call("unmark_log",ATy(qTy,PTy(uTy,qTy)),LN 2),qVar"s"))])))) +; +val dfn'CACHE_def = Def + ("dfn'CACHE",TP[Var("base",FTy 5),Var("opn",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Bop(And, + Mop(Not, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Mop(Not, + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))), + qVar"state")))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state"), + Let(TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))),qVar"s"], + Apply + (Call + ("AddressTranslation", + ATy(qTy,PTy(PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy))),qTy)), + TP[Bop(Add, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("base",FTy 5)),qVar"state")), + Mop(SE F64,Var("offset",F16))), + LC("DATA",CTy"IorD"),LC("LOAD",CTy"AccessType")]), + qVar"state"),TP[LU,qVar"s"])))) +; +val dfn'RDHWR_def = Def + ("dfn'RDHWR",TP[Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + ITE(Bop(Or, + Bop(Or, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))), + qVar"state"))), + Bop(Bit, + Call + ("reg'HWREna",F32, + Dest + ("HWREna",CTy"HWREna", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Mop(Cast nTy,Var("rd",FTy 5)))), + CS(Var("rd",FTy 5), + [(LW(0,5), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Bop(Sub,Dest("totalCore",nTy,qVar"state"),LN 1)), + Var("rt",FTy 5)]),qVar"state")), + (LW(2,5), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Dest + ("Count",F32, + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))),Var("rt",FTy 5)]), + qVar"state")), + (LW(3,5), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[LW(1,64),Var("rt",FTy 5)]),qVar"state")), + (LW(29,5), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Dest + ("UsrLocal",F64, + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))),Var("rt",FTy 5)]), + qVar"state")), + (AVar(FTy 5), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state"))]), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state")))) +; +val InitMEM_def = Def + ("InitMEM",qVar"state", + TP[LU,Rupd("MEM",TP[qVar"state",Mop(K1(FTy 37),LW(0,64))])]) +; +val ReadData_def = Def + ("ReadData",Var("pAddr",FTy 37), + Close + (qVar"state", + Let(Var("v",F64), + Apply + (Dest("MEM",ATy(FTy 37,F64),qVar"state"),Var("pAddr",FTy 37)), + TP[Var("v",F64), + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 2, + Call + ("log_r_mem",sTy, + TP[Var("pAddr",FTy 37),Var("v",F64)])]), + qVar"state"))]))) +; +val WriteData_def = Def + ("WriteData",TP[Var("pAddr",FTy 37),Var("data",F64),Var("mask",F64)], + Close + (qVar"state", + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 2, + Call + ("log_w_mem",sTy, + TP[Var("pAddr",FTy 37),Var("mask",F64),Var("data",F64)])]), + Rupd + ("MEM", + TP[qVar"state", + Fupd + (Dest("MEM",ATy(FTy 37,F64),qVar"state"), + Var("pAddr",FTy 37), + Bop(BOr, + Bop(BAnd, + Apply + (Dest("MEM",ATy(FTy 37,F64),qVar"state"), + Var("pAddr",FTy 37)), + Mop(BNot,Var("mask",F64))), + Bop(BAnd,Var("data",F64),Var("mask",F64))))])))) +; +val ReadInst_def = Def + ("ReadInst",Var("a",FTy 40), + Close + (qVar"state", + TP[ITE(Bop(Bit,Var("a",FTy 40),LN 2), + EX(Apply + (Dest("MEM",ATy(FTy 37,F64),qVar"state"), + EX(Var("a",FTy 40),LN 39,LN 3,FTy 37)),LN 31,LN 0,F32), + EX(Apply + (Dest("MEM",ATy(FTy 37,F64),qVar"state"), + EX(Var("a",FTy 40),LN 39,LN 3,FTy 37)),LN 63,LN 32,F32)), + qVar"state"])) +; +val WriteDWORD_def = Def + ("WriteDWORD",TP[Var("pAddr",FTy 37),Var("data",F64)], + Close + (qVar"state", + TP[LU, + Rupd + ("MEM", + TP[qVar"state", + Fupd + (Dest("MEM",ATy(FTy 37,F64),qVar"state"), + Var("pAddr",FTy 37),Var("data",F64))])])) +; +val Write256_def = Def + ("Write256",TP[Var("pAddr",FTy 35),Var("data",FTy 256)], + Close + (qVar"state", + Let(qVar"s", + Rupd + ("MEM", + TP[qVar"state", + Fupd + (Dest("MEM",ATy(FTy 37,F64),qVar"state"), + CC[Var("pAddr",FTy 35),LW(0,2)], + EX(Var("data",FTy 256),LN 63,LN 0,F64))]), + Let(qVar"s", + Rupd + ("MEM", + TP[qVar"s", + Fupd + (Dest("MEM",ATy(FTy 37,F64),qVar"s"), + CC[Var("pAddr",FTy 35),LW(1,2)], + EX(Var("data",FTy 256),LN 127,LN 64,F64))]), + Let(qVar"s", + Rupd + ("MEM", + TP[qVar"s", + Fupd + (Dest("MEM",ATy(FTy 37,F64),qVar"s"), + CC[Var("pAddr",FTy 35),LW(2,2)], + EX(Var("data",FTy 256),LN 191,LN 128,F64))]), + TP[LU, + Rupd + ("MEM", + TP[qVar"s", + Fupd + (Dest("MEM",ATy(FTy 37,F64),qVar"s"), + CC[Var("pAddr",FTy 35),LW(3,2)], + EX(Var("data",FTy 256),LN 255,LN 192,F64))])]))))) +; +val LoadMemoryCap_def = Def + ("LoadMemoryCap", + TP[Var("MemType",FTy 3),Var("vAddr",F64),Var("IorD",CTy"IorD"), + Var("AccessType",CTy"AccessType"),bVar"link"], + Close + (qVar"state", + Let(TP[Var("r",F64),Var("s1",PTy(FTy 40,qTy))], + Let(TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + Var("s",PTy(FTy 40,qTy))], + Let(TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))),qVar"s3"], + Apply + (Call + ("AddressTranslation", + ATy(qTy, + PTy(PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy))),qTy)), + TP[Var("vAddr",F64),LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType")]),qVar"state"), + TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + LX(FTy 40),qVar"s3"]), + Let(TP[Var("tmp",FTy 40),Var("CCA",FTy 3),bVar"S",bVar"L"], + Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + Let(Var("s",PTy(FTy 40,qTy)), + TP[Var("tmp",FTy 40), + Mop(Snd,Var("s",PTy(FTy 40,qTy)))], + Let(Var("s",PTy(FTy 40,qTy)), + Let(TP[Var("v",FTy 40),Var("s",PTy(FTy 40,qTy))], + Let(TP[Var("v0",FTy 3), + Var("s0",PTy(FTy 40,qTy))], + CS(Var("MemType",FTy 3), + [(LW(0,3), + Let(TP[Var("v0",F1), + Var("s0",PTy(FTy 40,qTy))], + Let(TP[Var("v",F1),qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("ReverseEndian", + ATy(qTy, + PTy(F1,qTy))), + Mop(Snd, + Var("s", + PTy(FTy 40, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 40,qTy)))], + TP[Var("v",F1), + Mop(Fst, + Var("s", + PTy(FTy 40,qTy))), + qVar"s3"]), + TP[Bop(BXor, + EX(Mop(Fst, + Var("s", + PTy(FTy 40, + qTy))), + LN 2,LN 0,FTy 3), + REP(Var("v0",F1),LN 3, + FTy 3)), + Var("s0",PTy(FTy 40,qTy))])), + (LW(1,3), + Let(TP[Var("v0",F1), + Var("s0",PTy(FTy 40,qTy))], + Let(TP[Var("v",F1),qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("ReverseEndian", + ATy(qTy, + PTy(F1,qTy))), + Mop(Snd, + Var("s", + PTy(FTy 40, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 40,qTy)))], + TP[Var("v",F1), + Mop(Fst, + Var("s", + PTy(FTy 40,qTy))), + qVar"s3"]), + TP[Bop(BXor, + EX(Mop(Fst, + Var("s", + PTy(FTy 40, + qTy))), + LN 2,LN 0,FTy 3), + CC[REP(Var("v0",F1), + LN 2,FTy 2), + LW(0,1)]), + Var("s0",PTy(FTy 40,qTy))])), + (LW(3,3), + Let(TP[Var("v0",F1), + Var("s0",PTy(FTy 40,qTy))], + Let(TP[Var("v",F1),qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("ReverseEndian", + ATy(qTy, + PTy(F1,qTy))), + Mop(Snd, + Var("s", + PTy(FTy 40, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 40,qTy)))], + TP[Var("v",F1), + Mop(Fst, + Var("s", + PTy(FTy 40,qTy))), + qVar"s3"]), + TP[Bop(BXor, + EX(Mop(Fst, + Var("s", + PTy(FTy 40, + qTy))), + LN 2,LN 0,FTy 3), + CC[Var("v0",F1),LW(0,2)]), + Var("s0",PTy(FTy 40,qTy))])), + (LW(7,3), + TP[EX(Mop(Fst, + Var("s",PTy(FTy 40,qTy))), + LN 2,LN 0,FTy 3), + Var("s",PTy(FTy 40,qTy))]), + (AVar(FTy 3), + Let(TP[Var("v",FTy 3),qVar"s3"], + Apply + (Call + ("raise'exception", + ATy(qTy,PTy(FTy 3,qTy)), + Call + ("UNPREDICTABLE", + CTy"exception", + LS"bad access length")), + Mop(Snd, + Var("s",PTy(FTy 40,qTy)))), + TP[Var("v",FTy 3), + Mop(Fst, + Var("s",PTy(FTy 40,qTy))), + qVar"s3"]))]), + TP[BFI(LN 2,LN 0,Var("v0",FTy 3), + Mop(Fst,Var("s",PTy(FTy 40,qTy)))), + Var("s0",PTy(FTy 40,qTy))]), + TP[Var("v",FTy 40), + Mop(Snd,Var("s",PTy(FTy 40,qTy)))]), + Let(TP[bVar"v",Var("s",PTy(FTy 40,qTy))], + Let(TP[bVar"v",qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("BigEndianMem", + ATy(qTy,PTy(bTy,qTy))), + Mop(Snd, + Var("s",PTy(FTy 40,qTy))))), + Mop(Snd,Var("s",PTy(FTy 40,qTy)))], + TP[bVar"v", + Mop(Fst,Var("s",PTy(FTy 40,qTy))), + qVar"s3"]), + Let(Var("s",PTy(FTy 40,qTy)), + TP[ITE(bVar"v", + Mop(Fst,Var("s",PTy(FTy 40,qTy))), + Bop(BAnd, + Mop(Fst, + Var("s",PTy(FTy 40,qTy))), + Mop(BNot,LW(7,40)))), + Mop(Snd,Var("s",PTy(FTy 40,qTy)))], + Let(TP[bVar"v",Var("s",PTy(FTy 40,qTy))], + Let(TP[bVar"v",qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy, + PTy(bTy,qTy))), + Mop(Snd, + Var("s", + PTy(FTy 40,qTy))))), + Mop(Snd, + Var("s",PTy(FTy 40,qTy)))], + TP[bVar"v", + Mop(Fst, + Var("s",PTy(FTy 40,qTy))), + qVar"s3"]), + ITE(Mop(Not,bVar"v"), + Let(Var("v",FTy 37), + EX(Mop(Fst, + Var("s", + PTy(FTy 40,qTy))), + LN 39,LN 3,FTy 37), + Let(TP[Var("r",F64), + Var("s1", + PTy(F64, + PTy(FTy 40, + qTy)))], + Let(TP[Var("r",F64), + Var("s1", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))], + Let(Var("s0", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))), + TP[LF,LX F64, + Var("s", + PTy(FTy 40, + qTy))], + Let(Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))), + ITE(EQ(Var("v", + FTy 37), + Dest + ("base_address", + FTy 37, + Dest + ("JTAG_UART", + CTy"JTAG_UART", + Mop(Snd, + Var("s", + PTy(FTy 40, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))), + TP[LT, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))], + Let(Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + CC[Call + ("flip_endian_word", + F32, + Call + ("reg'JTAG_UART_data", + F32, + Dest + ("data", + CTy"JTAG_UART_data__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))))))), + Call + ("flip_endian_word", + F32, + Call + ("reg'JTAG_UART_control", + F32, + Dest + ("control", + CTy"JTAG_UART_control__renamed__", + Dest + ("JTAG_UART", + CTy"JTAG_UART", + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))))))], + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))], + ITE(EQ(EX(Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + LN + 2, + LN + 0, + FTy 3), + LW(0, + 3)), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Const + ("JTAG_UART_load", + ATy(qTy, + PTy(uTy, + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))))], + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (For(TP[LN + 0, + Bop(Sub, + Dest + ("totalCore", + nTy, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))), + LN + 1), + Close + (nVar"core", + Close + (Var("state", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))), + ITE(Bop(And, + Bop(Uge, + Var("v", + FTy 37), + Apply + (Dest + ("PIC_base_address", + ATy(F8, + FTy 37), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))), + Mop(Cast + F8, + nVar"core"))), + Bop(Ult, + Var("v", + FTy 37), + Bop(Add, + Apply + (Dest + ("PIC_base_address", + ATy(F8, + FTy 37), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))), + Mop(Cast + F8, + nVar"core")), + LW(1072, + 37)))), + Let(Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))), + TP[LT, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))], + Let(TP[Var("v", + F64), + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(F64, + PTy(FTy 40, + qTy)))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 40, + qTy))], + Let(TP[Var("v", + F64), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("PIC_load", + ATy(qTy, + PTy(F64, + qTy)), + TP[Mop(Cast + F8, + nVar"core"), + Var("v", + FTy 37)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))], + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + qVar"s3"]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))), + Var("s3", + PTy(FTy 40, + qTy))]), + TP[Var("v", + F64), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + Var("s3", + PTy(F64, + PTy(FTy 40, + qTy)))]), + TP[LU, + Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + Var("v", + F64), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))])), + TP[LU, + Var("state", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))])))]), + Var("s0", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + Let(Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))), + ITE(bVar"link", + Let(Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Call + ("write'LLbit", + ATy(qTy, + PTy(uTy, + qTy)), + Mop(Some, + LT)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(F64, + PTy(FTy 40, + qTy)))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(FTy 40, + qTy))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))], + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + qVar"s3"]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))), + Var("s3", + PTy(FTy 40, + qTy))]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + Var("s3", + PTy(F64, + PTy(FTy 40, + qTy)))]), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("LLAddr", + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Cast + F64, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))))])), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))))])), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Call + ("write'LLbit", + ATy(qTy, + PTy(uTy, + qTy)), + LO bTy), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))))]), + Let(Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))), + ITE(EQ(Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + LF), + Let(TP[Var("v", + F64), + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(F64, + PTy(FTy 40, + qTy)))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 40, + qTy))], + Let(TP[Var("v", + F64), + qVar"s3"], + Apply + (Call + ("ReadData", + ATy(qTy, + PTy(F64, + qTy)), + Var("v", + FTy 37)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))))), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))), + qVar"s3"]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))), + Var("s3", + PTy(FTy 40, + qTy))]), + TP[Var("v", + F64), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + Var("s3", + PTy(F64, + PTy(FTy 40, + qTy)))]), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + Var("v", + F64), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))))]), + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))), + TP[Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))), + Var("s", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy))))])))), + TP[Var("r",F64), + Mop(Snd, + Var("s1", + PTy(bTy, + PTy(F64, + PTy(FTy 40, + qTy)))))]), + TP[Var("r",F64), + Mop(Snd, + Var("s1", + PTy(F64, + PTy(FTy 40, + qTy))))])), + TP[LX F64, + Var("s",PTy(FTy 40,qTy))])))))))), + TP[Var("r",F64),Mop(Snd,Var("s1",PTy(FTy 40,qTy)))]))) +; +val LoadMemory_def = Def + ("LoadMemory", + TP[Var("MemType",FTy 3),Var("AccessLength",FTy 3),Var("vAddr",F64), + Var("IorD",CTy"IorD"),Var("AccessType",CTy"AccessType"),bVar"link"], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Bop(Add,Var("vAddr",F64), + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))), + ITB([(Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))), + TP[LX F64, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),LW(0,5)]), + qVar"state"))]), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state"))), + TP[LX F64, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),LW(0,5)]), + qVar"state"))]), + (Bop(Ult,Var("v",F64), + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))), + TP[LX F64, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + LW(0,5)]),qVar"state"))]), + (Bop(Ugt,Var("v",F64), + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state"))), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state"))))), + TP[LX F64, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + LW(0,5)]),qVar"state"))]), + (Mop(Not, + Dest + ("Permit_Load",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))))), + TP[LX F64, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermLoad",CTy"CapException"), + LW(0,5)]),qVar"state"))])], + Apply + (Call + ("LoadMemoryCap",ATy(qTy,PTy(F64,qTy)), + TP[Var("MemType",FTy 3),Var("v",F64), + Var("IorD",CTy"IorD"), + Var("AccessType",CTy"AccessType"),bVar"link"]), + qVar"state"))))) +; +val LoadCap_def = Def + ("LoadCap",Var("vAddr",F64), + Close + (qVar"state", + Let(TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))),qVar"s"], + Apply + (Call + ("AddressTranslation", + ATy(qTy,PTy(PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy))),qTy)), + TP[Var("vAddr",F64),LC("DATA",CTy"IorD"), + LC("CLOAD",CTy"AccessType")]),qVar"state"), + Let(TP[Var("pAddr",FTy 40),Var("CCA",FTy 3),bVar"S",bVar"L"], + Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled",ATy(qTy,PTy(bTy,qTy))), + qVar"s"))), + Let(Var("a",FTy 35), + EX(Var("pAddr",FTy 40),LN 39,LN 5,FTy 35), + Let(TP[Var("r",CTy"Capability"), + Var("s1",PTy(CTy"Capability",qTy))], + Let(Var("s",PTy(CTy"Capability",qTy)), + TP[LX(CTy"Capability"), + ITE(EQ(Var("a",FTy 35), + EX(Dest + ("base_address",FTy 37, + Dest + ("JTAG_UART", + CTy"JTAG_UART",qVar"s")), + LN 36,LN 2,FTy 35)), + Mop(Snd, + Apply + (Call + ("raise'exception", + ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE", + CTy"exception", + LS + "Capability load attempted on UART")), + qVar"s")), + Mop(Snd, + Apply + (For(TP[LN 0, + Bop(Sub, + Dest + ("totalCore",nTy, + qVar"s"),LN 1), + Close + (nVar"core", + Close + (qVar"state", + ITE(Bop(And, + Bop(Uge, + Var("a", + FTy 35), + EX(Apply + (Dest + ("PIC_base_address", + ATy(F8, + FTy 37), + qVar"state"), + Mop(Cast + F8, + nVar"core")), + LN + 36, + LN + 2, + FTy 35)), + Bop(Ult, + Var("a", + FTy 35), + EX(Bop(Add, + Apply + (Dest + ("PIC_base_address", + ATy(F8, + FTy 37), + qVar"state"), + Mop(Cast + F8, + nVar"core")), + LW(1072, + 37)), + LN + 36, + LN + 2, + FTy 35))), + Apply + (Call + ("raise'exception", + ATy(qTy, + PTy(uTy, + qTy)), + Call + ("UNPREDICTABLE", + CTy"exception", + LS + "Capability load attempted on PIC")), + qVar"state"), + TP[LU, + qVar"state"])))]), + qVar"s")))], + Let(Var("s",PTy(CTy"Capability",qTy)), + Let(TP[Var("v",CTy"Capability"), + Var("s",PTy(CTy"Capability",qTy))], + Let(TP[Var("v", + PTy(CTy"Capability", + FTy 257)), + Var("s", + PTy(CTy"Capability",qTy))], + Let(TP[Var("v0",F64), + Var("s0", + PTy(CTy"Capability", + qTy))], + Let(TP[Var("v",F64),qVar"s3"], + Apply + (Call + ("ReadData", + ATy(qTy, + PTy(F64,qTy)), + CC[Var("a",FTy 35), + LW(0,2)]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))), + TP[Var("v",F64), + Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + qVar"s3"]), + TP[TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + BFI(LN 255,LN 192, + Var("v0",F64), + Call + ("reg'Capability", + FTy 257, + LX(CTy"Capability")))], + Var("s0", + PTy(CTy"Capability", + qTy))]), + TP[Call + ("write'reg'Capability", + CTy"Capability", + Var("v", + PTy(CTy"Capability", + FTy 257))), + Var("s", + PTy(CTy"Capability",qTy))]), + TP[Var("v",CTy"Capability"), + Mop(Snd, + Var("s", + PTy(CTy"Capability",qTy)))]), + Let(Var("s",PTy(CTy"Capability",qTy)), + Let(TP[Var("v",CTy"Capability"), + Var("s", + PTy(CTy"Capability",qTy))], + Let(TP[Var("v", + PTy(CTy"Capability", + FTy 257)), + Var("s", + PTy(CTy"Capability", + qTy))], + Let(TP[Var("v0",F64), + Var("s0", + PTy(CTy"Capability", + qTy))], + Let(TP[Var("v",F64), + qVar"s3"], + Apply + (Call + ("ReadData", + ATy(qTy, + PTy(F64, + qTy)), + CC[Var("a", + FTy 35), + LW(1,2)]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))), + TP[Var("v",F64), + Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + qVar"s3"]), + TP[TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + BFI(LN 191,LN 128, + Var("v0",F64), + Call + ("reg'Capability", + FTy 257, + Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy)))))], + Var("s0", + PTy(CTy"Capability", + qTy))]), + TP[Call + ("write'reg'Capability", + CTy"Capability", + Var("v", + PTy(CTy"Capability", + FTy 257))), + Var("s", + PTy(CTy"Capability", + qTy))]), + TP[Var("v",CTy"Capability"), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))]), + Let(Var("s",PTy(CTy"Capability",qTy)), + Let(TP[Var("v",CTy"Capability"), + Var("s", + PTy(CTy"Capability", + qTy))], + Let(TP[Var("v", + PTy(CTy"Capability", + FTy 257)), + Var("s", + PTy(CTy"Capability", + qTy))], + Let(TP[Var("v0",F64), + Var("s0", + PTy(CTy"Capability", + qTy))], + Let(TP[Var("v",F64), + qVar"s3"], + Apply + (Call + ("ReadData", + ATy(qTy, + PTy(F64, + qTy)), + CC[Var("a", + FTy 35), + LW(2,2)]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))), + TP[Var("v",F64), + Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + qVar"s3"]), + TP[TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + BFI(LN 127, + LN 64, + Var("v0", + F64), + Call + ("reg'Capability", + FTy 257, + Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy)))))], + Var("s0", + PTy(CTy"Capability", + qTy))]), + TP[Call + ("write'reg'Capability", + CTy"Capability", + Var("v", + PTy(CTy"Capability", + FTy 257))), + Var("s", + PTy(CTy"Capability", + qTy))]), + TP[Var("v",CTy"Capability"), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))]), + Let(Var("s", + PTy(CTy"Capability",qTy)), + Let(TP[Var("v", + CTy"Capability"), + Var("s", + PTy(CTy"Capability", + qTy))], + Let(TP[Var("v", + PTy(CTy"Capability", + FTy 257)), + Var("s", + PTy(CTy"Capability", + qTy))], + Let(TP[Var("v0",F64), + Var("s0", + PTy(CTy"Capability", + qTy))], + Let(TP[Var("v", + F64), + qVar"s3"], + Apply + (Call + ("ReadData", + ATy(qTy, + PTy(F64, + qTy)), + CC[Var("a", + FTy 35), + LW(3, + 2)]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))), + TP[Var("v", + F64), + Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + qVar"s3"]), + TP[TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + BFI(LN 63, + LN 0, + Var("v0", + F64), + Call + ("reg'Capability", + FTy 257, + Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy)))))], + Var("s0", + PTy(CTy"Capability", + qTy))]), + TP[Call + ("write'reg'Capability", + CTy"Capability", + Var("v", + PTy(CTy"Capability", + FTy 257))), + Var("s", + PTy(CTy"Capability", + qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))]), + Let(Var("s", + PTy(CTy"Capability", + qTy)), + TP[Rupd + ("tag", + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + ITE(bVar"L",LF, + Apply + (Dest + ("TAG", + ATy(FTy 35, + bTy), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))), + Var("a", + FTy 35)))]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))], + Let(Var("s", + PTy(CTy"Capability", + qTy)), + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + Mop(Snd, + Apply + (Call + ("write'LLbit", + ATy(qTy, + PTy(uTy, + qTy)), + LO bTy), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + qTy)))))], + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + qTy))), + Var("s", + PTy(CTy"Capability", + qTy))]))))))), + TP[Var("r",CTy"Capability"), + Mop(Snd,Var("s1",PTy(CTy"Capability",qTy)))])), + TP[LX(CTy"Capability"),qVar"s"]))))) +; +val StoreMemoryCap_def = Def + ("StoreMemoryCap", + TP[Var("MemType",FTy 3),Var("AccessLength",FTy 3),Var("MemElem",F64), + Var("vAddr",F64),Var("IorD",CTy"IorD"), + Var("AccessType",CTy"AccessType"),bVar"cond"], + Close + (qVar"state", + Let(TP[bVar"r",Var("s1",PTy(FTy 40,qTy))], + Let(TP[bVar"r",Var("s1",PTy(bTy,PTy(FTy 40,qTy)))], + Let(TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + Var("s",PTy(bTy,PTy(FTy 40,qTy)))], + Let(TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + Var("s3",PTy(FTy 40,qTy))], + Let(TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + qVar"s3"], + Apply + (Call + ("AddressTranslation", + ATy(qTy, + PTy(PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy))), + qTy)), + TP[Var("vAddr",F64),LC("DATA",CTy"IorD"), + LC("STORE",CTy"AccessType")]), + qVar"state"), + TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + LX(FTy 40),qVar"s3"]), + TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))),LF, + Var("s3",PTy(FTy 40,qTy))]), + Let(TP[Var("tmp",FTy 40),Var("CCA",FTy 3),bVar"S", + bVar"L"], + Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + Let(Var("s",PTy(bTy,PTy(FTy 40,qTy))), + TP[Mop(Fst,Var("s",PTy(bTy,PTy(FTy 40,qTy)))), + Var("tmp",FTy 40), + Mop(Snd, + Mop(Snd,Var("s",PTy(bTy,PTy(FTy 40,qTy)))))], + Let(Var("s",PTy(bTy,PTy(FTy 40,qTy))), + Let(TP[Var("v",FTy 40), + Var("s",PTy(bTy,PTy(FTy 40,qTy)))], + Let(TP[Var("v0",FTy 3), + Var("s0",PTy(bTy,PTy(FTy 40,qTy)))], + CS(Var("MemType",FTy 3), + [(LW(0,3), + Let(TP[Var("v0",F1), + Var("s0", + PTy(bTy, + PTy(FTy 40,qTy)))], + Let(TP[Var("v",F1), + Var("s3", + PTy(FTy 40,qTy))], + Let(TP[Var("v",F1), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("ReverseEndian", + ATy(qTy, + PTy(F1, + qTy))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))))], + TP[Var("v",F1), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + qVar"s3"]), + TP[Var("v",F1), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))), + Var("s3", + PTy(FTy 40,qTy))]), + TP[Bop(BXor, + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + LN 2,LN 0,FTy 3), + REP(Var("v0",F1), + LN 3,FTy 3)), + Var("s0", + PTy(bTy, + PTy(FTy 40,qTy)))])), + (LW(1,3), + Let(TP[Var("v0",F1), + Var("s0", + PTy(bTy, + PTy(FTy 40,qTy)))], + Let(TP[Var("v",F1), + Var("s3", + PTy(FTy 40,qTy))], + Let(TP[Var("v",F1), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("ReverseEndian", + ATy(qTy, + PTy(F1, + qTy))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))))], + TP[Var("v",F1), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + qVar"s3"]), + TP[Var("v",F1), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))), + Var("s3", + PTy(FTy 40,qTy))]), + TP[Bop(BXor, + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + LN 2,LN 0,FTy 3), + CC[REP(Var("v0",F1), + LN 2,FTy 2), + LW(0,1)]), + Var("s0", + PTy(bTy, + PTy(FTy 40,qTy)))])), + (LW(3,3), + Let(TP[Var("v0",F1), + Var("s0", + PTy(bTy, + PTy(FTy 40,qTy)))], + Let(TP[Var("v",F1), + Var("s3", + PTy(FTy 40,qTy))], + Let(TP[Var("v",F1), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("ReverseEndian", + ATy(qTy, + PTy(F1, + qTy))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))))], + TP[Var("v",F1), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + qVar"s3"]), + TP[Var("v",F1), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))), + Var("s3", + PTy(FTy 40,qTy))]), + TP[Bop(BXor, + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + LN 2,LN 0,FTy 3), + CC[Var("v0",F1), + LW(0,2)]), + Var("s0", + PTy(bTy, + PTy(FTy 40,qTy)))])), + (LW(7,3), + TP[EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + LN 2,LN 0,FTy 3), + Var("s", + PTy(bTy,PTy(FTy 40,qTy)))]), + (AVar(FTy 3), + Let(TP[Var("v",FTy 3), + Var("s3",PTy(FTy 40,qTy))], + Let(TP[Var("v",FTy 3), + qVar"s3"], + Apply + (Call + ("raise'exception", + ATy(qTy, + PTy(FTy 3,qTy)), + Call + ("UNPREDICTABLE", + CTy"exception", + LS + "bad access length")), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))))), + TP[Var("v",FTy 3), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + qVar"s3"]), + TP[Var("v",FTy 3), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))), + Var("s3",PTy(FTy 40,qTy))]))]), + TP[BFI(LN 2,LN 0,Var("v0",FTy 3), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Var("s0",PTy(bTy,PTy(FTy 40,qTy)))]), + TP[Mop(Fst, + Var("s",PTy(bTy,PTy(FTy 40,qTy)))), + Var("v",FTy 40), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy,PTy(FTy 40,qTy)))))]), + Let(TP[bVar"v", + Var("s",PTy(bTy,PTy(FTy 40,qTy)))], + CS(Let(TP[bVar"v",qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("BigEndianMem", + ATy(qTy,PTy(bTy,qTy))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40,qTy)))))], + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40,qTy))))), + qVar"s3"]), + [(TP[bVar"v", + Var("s3",PTy(FTy 40,qTy))], + TP[bVar"v", + Mop(Fst, + Var("s", + PTy(bTy,PTy(FTy 40,qTy)))), + Var("s3",PTy(FTy 40,qTy))])]), + Let(Var("s",PTy(bTy,PTy(FTy 40,qTy))), + TP[Mop(Fst, + Var("s", + PTy(bTy,PTy(FTy 40,qTy)))), + ITE(bVar"v", + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + Bop(BAnd, + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + Mop(BNot,LW(7,40)))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40,qTy)))))], + Let(TP[bVar"v", + Var("s", + PTy(bTy,PTy(FTy 40,qTy)))], + CS(Let(TP[bVar"v",qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy, + PTy(bTy, + qTy))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))))], + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + qVar"s3"]), + [(TP[bVar"v", + Var("s3",PTy(FTy 40,qTy))], + TP[bVar"v", + Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))), + Var("s3",PTy(FTy 40,qTy))])]), + Let(Var("s", + PTy(bTy,PTy(FTy 40,qTy))), + ITE(Mop(Not,bVar"v"), + Let(Var("v",FTy 37), + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy))))), + LN 39,LN 3,FTy 37), + Let(nVar"l", + Bop(Sub,LN 64, + Bop(Mul, + Bop(Add, + Bop(Add, + Mop(Cast + nTy, + Var("AccessLength", + FTy 3)), + LN + 1), + Mop(Cast + nTy, + EX(Var("vAddr", + F64), + LN + 2, + LN + 0, + FTy 3))), + LN 8)), + Let(Var("mask", + F64), + Mop(Cast F64, + Bop(Sub, + Bop(Exp, + LN + 2, + Bop(Add, + nVar"l", + Bop(Mul, + Bop(Add, + Mop(Cast + nTy, + Var("AccessLength", + FTy 3)), + LN + 1), + LN + 8))), + Bop(Exp, + LN + 2, + nVar"l"))), + Let(Var("s0", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + TP[LF, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))], + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + ITE(EQ(Var("v", + FTy 37), + Dest + ("base_address", + FTy 37, + Dest + ("JTAG_UART", + CTy"JTAG_UART", + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + TP[LT, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))], + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Call + ("JTAG_UART_store", + ATy(qTy, + PTy(uTy, + qTy)), + TP[Var("mask", + F64), + Var("MemElem", + F64)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))))]), + Mop(Snd, + Apply + (For(TP[LN + 0, + Bop(Sub, + Dest + ("totalCore", + nTy, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))), + LN + 1), + Close + (nVar"core", + Close + (Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + ITE(Bop(And, + Bop(Uge, + Var("v", + FTy 37), + Apply + (Dest + ("PIC_base_address", + ATy(F8, + FTy 37), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))), + Mop(Cast + F8, + nVar"core"))), + Bop(Ult, + Var("v", + FTy 37), + Bop(Add, + Apply + (Dest + ("PIC_base_address", + ATy(F8, + FTy 37), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))), + Mop(Cast + F8, + nVar"core")), + LW(1072, + 37)))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + TP[LT, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))], + TP[LU, + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Call + ("PIC_store", + ATy(qTy, + PTy(uTy, + qTy)), + TP[Mop(Cast + F8, + nVar"core"), + Var("v", + FTy 37), + Var("mask", + F64), + Var("MemElem", + F64)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))))]), + TP[LU, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))])))]), + Var("s0", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + ITE(bVar"cond", + Let(TP[Var("v", + OTy bTy), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))], + Let(TP[Var("v", + OTy bTy), + Var("s3", + PTy(bTy, + PTy(FTy 40, + qTy)))], + Let(TP[Var("v", + OTy bTy), + Var("s3", + PTy(FTy 40, + qTy))], + Let(TP[Var("v", + OTy bTy), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("LLbit", + ATy(qTy, + PTy(OTy bTy, + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))], + TP[Var("v", + OTy bTy), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + qVar"s3"]), + TP[Var("v", + OTy bTy), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Var("s3", + PTy(FTy 40, + qTy))]), + TP[Var("v", + OTy bTy), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + Var("s3", + PTy(bTy, + PTy(FTy 40, + qTy)))]), + CS(Var("v", + OTy bTy), + [(LO bTy, + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Call + ("raise'exception", + ATy(qTy, + PTy(uTy, + qTy)), + Call + ("UNPREDICTABLE", + CTy"exception", + LS + "conditional store: LLbit not set")), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))))]), + (Mop(Some, + LF), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + LF, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))]), + (Mop(Some, + LT), + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(bTy, + PTy(FTy 40, + qTy)))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(FTy 40, + qTy))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))], + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + qVar"s3"]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Var("s3", + PTy(FTy 40, + qTy))]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + Var("s3", + PTy(bTy, + PTy(FTy 40, + qTy)))]), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + ITE(EQ(EX(Dest + ("LLAddr", + F64, + Var("v", + CTy"CP0__renamed__")), + LN + 39, + LN + 5, + FTy 35), + EX(Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + LN + 39, + LN + 5, + FTy 35)), + TP[LT, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))], + TP[Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Call + ("raise'exception", + ATy(qTy, + PTy(uTy, + qTy)), + Call + ("UNPREDICTABLE", + CTy"exception", + LS + "conditional store: address does not match previous LL address")), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))))])]))])), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Call + ("write'LLbit", + ATy(qTy, + PTy(uTy, + qTy)), + LO bTy), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))))], + ITE(Mop(Not, + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + Mop(Snd, + Apply + (For(TP[LN + 0, + Bop(Sub, + Dest + ("totalCore", + nTy, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))), + LN + 1), + Close + (nVar"core", + Close + (Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + TP[LU, + ITE(Bop(And, + Bop(And, + Mop(Not, + EQ(nVar"core", + Mop(Cast + nTy, + Dest + ("procID", + F8, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))))))), + EQ(Apply + (Dest + ("c_LLbit", + ATy(F8, + OTy bTy), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))), + Mop(Cast + F8, + nVar"core")), + Mop(Some, + LT))), + EQ(EX(Dest + ("LLAddr", + F64, + Apply + (Dest + ("c_CP0", + ATy(F8, + CTy"CP0__renamed__"), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))), + Mop(Cast + F8, + nVar"core"))), + LN + 39, + LN + 5, + FTy 35), + EX(Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + LN + 39, + LN + 5, + FTy 35))), + TP[Mop(Fst, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + Let(Var("s0", + PTy(bTy, + PTy(FTy 40, + qTy))), + Mop(Snd, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + TP[Mop(Fst, + Var("s0", + PTy(bTy, + PTy(FTy 40, + qTy)))), + Let(Var("s0", + PTy(FTy 40, + qTy)), + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 40, + qTy)))), + TP[Mop(Fst, + Var("s0", + PTy(FTy 40, + qTy))), + Rupd + ("c_LLbit", + TP[Mop(Snd, + Var("s0", + PTy(FTy 40, + qTy))), + Fupd + (Dest + ("c_LLbit", + ATy(F8, + OTy bTy), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))), + Mop(Cast + F8, + nVar"core"), + Mop(Some, + LF))])])])], + Var("state", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))]))]), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + ITE(Bop(Or, + Mop(Not, + bVar"cond"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Apply + (Call + ("WriteData", + ATy(qTy, + PTy(uTy, + qTy)), + TP[Var("v", + FTy 37), + Var("MemElem", + F64), + Var("mask", + F64)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))))], + Let(Var("s0", + PTy(bTy, + PTy(FTy 40, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))), + TP[Mop(Fst, + Var("s0", + PTy(bTy, + PTy(FTy 40, + qTy)))), + Let(Var("s0", + PTy(FTy 40, + qTy)), + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 40, + qTy)))), + TP[Mop(Fst, + Var("s0", + PTy(FTy 40, + qTy))), + Rupd + ("TAG", + TP[Mop(Snd, + Var("s0", + PTy(FTy 40, + qTy))), + Fupd + (Dest + ("TAG", + ATy(FTy 35, + bTy), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy)))))))), + EX(Var("v", + FTy 37), + LN + 36, + LN + 2, + FTy 35), + LF)])])])), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(FTy 40, + qTy))))))))))))), + Var("s", + PTy(bTy, + PTy(FTy 40,qTy)))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 40, + qTy)))), + Var("s", + PTy(bTy, + PTy(FTy 40,qTy)))])))))))), + TP[bVar"r",Mop(Snd,Var("s1",PTy(bTy,PTy(FTy 40,qTy))))]), + TP[bVar"r",Mop(Snd,Var("s1",PTy(FTy 40,qTy)))]))) +; +val StoreMemory_def = Def + ("StoreMemory", + TP[Var("MemType",FTy 3),Var("AccessLength",FTy 3),Var("MemElem",F64), + Var("vAddr",F64),Var("IorD",CTy"IorD"), + Var("AccessType",CTy"AccessType"),bVar"cond"], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Bop(Add,Var("vAddr",F64), + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))), + ITB([(Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))), + TP[LX bTy, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),LW(0,5)]), + qVar"state"))]), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state"))), + TP[LX bTy, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),LW(0,5)]), + qVar"state"))]), + (Bop(Ult,Var("v",F64), + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))), + TP[LX bTy, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + LW(0,5)]),qVar"state"))]), + (Bop(Ugt,Var("v",F64), + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state"))), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state"))))), + TP[LX bTy, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + LW(0,5)]),qVar"state"))]), + (Mop(Not, + Dest + ("Permit_Store",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + LW(0,5)),qVar"state")))))), + TP[LX bTy, + Mop(Snd, + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermStore",CTy"CapException"), + LW(0,5)]),qVar"state"))])], + Apply + (Call + ("StoreMemoryCap",ATy(qTy,PTy(bTy,qTy)), + TP[Var("MemType",FTy 3),Var("AccessLength",FTy 3), + Var("MemElem",F64),Var("v",F64), + Var("IorD",CTy"IorD"), + Var("AccessType",CTy"AccessType"),bVar"cond"]), + qVar"state"))))) +; +val StoreCap_def = Def + ("StoreCap",TP[Var("vAddr",F64),Var("Capability",CTy"Capability")], + Close + (qVar"state", + Let(TP[Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))),qVar"s"], + Apply + (Call + ("AddressTranslation", + ATy(qTy,PTy(PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy))),qTy)), + TP[Var("vAddr",F64),LC("DATA",CTy"IorD"), + LC("CSTORE",CTy"AccessType")]),qVar"state"), + Let(TP[Var("pAddr",FTy 40),Var("CCA",FTy 3),bVar"S",bVar"L"], + Var("v",PTy(FTy 40,PTy(FTy 3,PTy(bTy,bTy)))), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled",ATy(qTy,PTy(bTy,qTy))), + qVar"s"))), + Let(Var("a",FTy 35), + EX(Var("pAddr",FTy 40),LN 39,LN 5,FTy 35), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'LLbit",ATy(qTy,PTy(uTy,qTy)), + LO bTy), + ITE(EQ(Var("a",FTy 35), + EX(Dest + ("base_address",FTy 37, + Dest + ("JTAG_UART", + CTy"JTAG_UART",qVar"s")), + LN 36,LN 2,FTy 35)), + Mop(Snd, + Apply + (Call + ("raise'exception", + ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE", + CTy"exception", + LS + "Capability store attempted on UART")), + qVar"s")), + Mop(Snd, + Apply + (For(TP[LN 0, + Bop(Sub, + Dest + ("totalCore",nTy, + qVar"s"),LN 1), + Close + (nVar"core", + Close + (qVar"state", + ITE(Bop(And, + Bop(Uge, + Var("a", + FTy 35), + EX(Apply + (Dest + ("PIC_base_address", + ATy(F8, + FTy 37), + qVar"state"), + Mop(Cast + F8, + nVar"core")), + LN + 36, + LN + 2, + FTy 35)), + Bop(Ult, + Var("a", + FTy 35), + EX(Bop(Add, + Apply + (Dest + ("PIC_base_address", + ATy(F8, + FTy 37), + qVar"state"), + Mop(Cast + F8, + nVar"core")), + LW(1072, + 37)), + LN + 36, + LN + 2, + FTy 35))), + Apply + (Call + ("raise'exception", + ATy(qTy, + PTy(uTy, + qTy)), + Call + ("UNPREDICTABLE", + CTy"exception", + LS + "Capability store attempted on PIC")), + qVar"state"), + TP[LU, + qVar"state"])))]), + qVar"s"))))), + ITE(Bop(And,bVar"S", + Dest + ("tag",bTy, + Var("Capability",CTy"Capability"))), + Apply + (Call + ("SignalCapException_noReg", + ATy(qTy,PTy(uTy,qTy)), + LC("capExcTLBNoStore", + CTy"CapException")),qVar"s"), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("WriteData", + ATy(qTy,PTy(uTy,qTy)), + TP[CC[Var("a",FTy 35),LW(3,2)], + EX(Call + ("reg'Capability", + FTy 257, + Var("Capability", + CTy"Capability")), + LN 63,LN 0,F64), + Mop(BNot,LW(0,64))]), + Mop(Snd, + Apply + (Call + ("WriteData", + ATy(qTy,PTy(uTy,qTy)), + TP[CC[Var("a",FTy 35), + LW(2,2)], + EX(Call + ("reg'Capability", + FTy 257, + Var("Capability", + CTy"Capability")), + LN 127,LN 64,F64), + Mop(BNot,LW(0,64))]), + Mop(Snd, + Apply + (Call + ("WriteData", + ATy(qTy, + PTy(uTy,qTy)), + TP[CC[Var("a", + FTy 35), + LW(1,2)], + EX(Call + ("reg'Capability", + FTy 257, + Var("Capability", + CTy"Capability")), + LN 191, + LN 128,F64), + Mop(BNot, + LW(0,64))]), + Mop(Snd, + Apply + (Call + ("WriteData", + ATy(qTy, + PTy(uTy, + qTy)), + TP[CC[Var("a", + FTy 35), + LW(0, + 2)], + EX(Call + ("reg'Capability", + FTy 257, + Var("Capability", + CTy"Capability")), + LN + 255, + LN + 192, + F64), + Mop(BNot, + LW(0, + 64))]), + Mop(Snd, + Apply + (Call + ("mark_log", + ATy(qTy, + PTy(uTy, + qTy)), + TP[LN + 2, + Call + ("log_store_cap", + sTy, + TP[Var("pAddr", + FTy 40), + Var("Capability", + CTy"Capability")])]), + Mop(Snd, + Apply + (For(TP[LN + 0, + Bop(Sub, + Dest + ("totalCore", + nTy, + qVar"s"), + LN + 1), + Close + (nVar"core", + Close + (qVar"state", + TP[LU, + ITE(Bop(And, + Bop(And, + Mop(Not, + EQ(nVar"core", + Mop(Cast + nTy, + Dest + ("procID", + F8, + qVar"state")))), + EQ(Apply + (Dest + ("c_LLbit", + ATy(F8, + OTy bTy), + qVar"state"), + Mop(Cast + F8, + nVar"core")), + Mop(Some, + LT))), + EQ(EX(Dest + ("LLAddr", + F64, + Apply + (Dest + ("c_CP0", + ATy(F8, + CTy"CP0__renamed__"), + qVar"state"), + Mop(Cast + F8, + nVar"core"))), + LN + 39, + LN + 5, + FTy 35), + EX(Var("pAddr", + FTy 40), + LN + 39, + LN + 5, + FTy 35))), + Rupd + ("c_LLbit", + TP[qVar"state", + Fupd + (Dest + ("c_LLbit", + ATy(F8, + OTy bTy), + qVar"state"), + Mop(Cast + F8, + nVar"core"), + Mop(Some, + LF))]), + qVar"state")]))]), + qVar"s")))))))))))), + TP[LU, + Rupd + ("TAG", + TP[qVar"s", + Fupd + (Dest + ("TAG",ATy(FTy 35,bTy), + qVar"s"),Var("a",FTy 35), + Dest + ("tag",bTy, + Var("Capability", + CTy"Capability")))])])))), + TP[LU,qVar"s"]))))) +; +val Fetch_def = Def + ("Fetch",qVar"state", + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Random", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("Random", + TP[Dest + ("Random",CTy"Random", + Var("v",CTy"CP0__renamed__")), + ITE(EQ(Dest + ("Random",F8, + Dest + ("Random",CTy"Random", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"state")))), + Dest + ("Wired",F8, + Dest + ("Wired",CTy"Wired", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"state"))))), + Mop(Cast F8, + Bop(Sub,Const("TLBEntries",nTy), + LN 1)), + Bop(Sub, + Dest + ("Random",F8, + Dest + ("Random",CTy"Random", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"state")))), + LW(1,8)))])])),qVar"state")), + Let(qVar"s", + ITE(EQ(Dest + ("Compare",F32, + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s"))), + Dest + ("Count",F32, + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")))), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Let(qVar"s", + Let(Var("x0",CTy"CauseRegister"), + Dest + ("Cause",CTy"CauseRegister", + Var("v",CTy"CP0__renamed__")), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Cause", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("IP", + TP[Var("x0", + CTy"CauseRegister"), + BFI(LN 7,LN 7, + Mop(Cast F1,LT), + Dest + ("IP",F8, + Var("x0", + CTy"CauseRegister")))])])), + qVar"s"))), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Cause", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("TI", + TP[Dest + ("Cause", + CTy"CauseRegister", + Var("v", + CTy"CP0__renamed__")), + LT])])),qVar"s"))))), + qVar"s"), + Let(qVar"s", + ITE(Bop(And, + Dest + ("IE",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"s")))), + Mop(Not, + Bop(Or, + Dest + ("EXL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")))), + Dest + ("ERL",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s"))))))), + ITE(Mop(Not, + EQ(Bop(BAnd, + EX(Dest + ("IM",F8, + Dest + ("Status", + CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")))),LN 7, + LN 2,FTy 6), + EX(Dest + ("IP",F8, + Dest + ("Cause",CTy"CauseRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")))),LN 7, + LN 2,FTy 6)),LW(0,6))), + Mop(Snd, + Apply + (Call + ("SignalException", + ATy(qTy,PTy(uTy,qTy)), + LC("Int",CTy"ExceptionType")),qVar"s")), + qVar"s"),qVar"s"), + ITB([(Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s")), + TP[LO F32,qVar"s"]), + (EQ(EX(Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")),LN 1,LN 0,FTy 2),LW(0,2)), + Let(Var("v",F64), + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")), + Dest + ("base",F64, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability",qTy))), + qVar"s")))), + ITB([(Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))),qVar"s")))), + TP[LO F32, + Mop(Snd, + Apply + (Call + ("SignalCapException_noReg", + ATy(qTy,PTy(uTy,qTy)), + LC("capExcTag", + CTy"CapException")), + qVar"s"))]), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))),qVar"s"))), + TP[LO F32, + Mop(Snd, + Apply + (Call + ("SignalCapException_noReg", + ATy(qTy,PTy(uTy,qTy)), + LC("capExcSeal", + CTy"CapException")), + qVar"s"))]), + (Bop(Ugt,Var("v",F64), + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))), + qVar"s"))), + Dest + ("length",F64, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))), + qVar"s"))))), + TP[LO F32, + Mop(Snd, + Apply + (Call + ("SignalCapException_noReg", + ATy(qTy,PTy(uTy,qTy)), + LC("capExcLength", + CTy"CapException")), + qVar"s"))]), + (Bop(Ult,Var("v",F64), + Dest + ("base",F64, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))),qVar"s")))), + TP[LO F32, + Mop(Snd, + Apply + (Call + ("SignalCapException_noReg", + ATy(qTy,PTy(uTy,qTy)), + LC("capExcLength", + CTy"CapException")), + qVar"s"))]), + (Mop(Not, + Dest + ("Permit_Execute",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))), + qVar"s")))))), + TP[LO F32, + Mop(Snd, + Apply + (Call + ("SignalCapException_noReg", + ATy(qTy,PTy(uTy,qTy)), + LC("capExcPermExe", + CTy"CapException")), + qVar"s"))])], + Let(TP[Var("v", + PTy(FTy 40, + PTy(FTy 3,PTy(bTy,bTy)))), + qVar"s"], + Apply + (Call + ("AddressTranslation", + ATy(qTy, + PTy(PTy(FTy 40, + PTy(FTy 3, + PTy(bTy,bTy))), + qTy)), + TP[Var("v",F64), + LC("INSTRUCTION",CTy"IorD"), + LC("LOAD",CTy"AccessType")]), + qVar"s"), + Let(TP[Var("pc",FTy 40), + Var("cca", + PTy(FTy 3,PTy(bTy,bTy)))], + Var("v", + PTy(FTy 40, + PTy(FTy 3,PTy(bTy,bTy)))), + TP[ITE(Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy, + PTy(bTy,qTy))), + qVar"s")),LO F32, + Mop(Some, + Mop(Fst, + Apply + (Call + ("ReadInst", + ATy(qTy, + PTy(F32, + qTy)), + Var("pc", + FTy 40)), + qVar"s")))), + qVar"s"])))))], + TP[LO F32, + Mop(Snd, + Apply + (Call + ("SignalException", + ATy(qTy,PTy(uTy,qTy)), + LC("AdEL",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability", + qTy))), + qVar"s"))), + Mop(Fst, + Apply + (Const + ("PC", + ATy(qTy, + PTy(F64, + qTy))), + qVar"s")))])), + qVar"s"))))])))))) +; +val dfn'JALR_def = Def + ("dfn'JALR",TP[Var("rs",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(8,64)),Var("rd",FTy 5)]), + qVar"state"))))) +; +val register_inaccessible_def = Def + ("register_inaccessible",Var("cb",FTy 5), + Close + (qVar"state", + Let(Var("v",CTy"Perms"), + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Const("PCC",ATy(qTy,PTy(CTy"Capability",qTy))), + qVar"state")))), + TP[Bop(Or, + Bop(Or, + Bop(Or, + Bop(Or, + Bop(And,EQ(Var("cb",FTy 5),LW(31,5)), + Mop(Not, + Dest + ("Access_EPCC",bTy, + Var("v",CTy"Perms")))), + Bop(And,EQ(Var("cb",FTy 5),LW(30,5)), + Mop(Not, + Dest + ("Access_KDC",bTy, + Var("v",CTy"Perms"))))), + Bop(And,EQ(Var("cb",FTy 5),LW(29,5)), + Mop(Not, + Dest + ("Access_KCC",bTy,Var("v",CTy"Perms"))))), + Bop(And,EQ(Var("cb",FTy 5),LW(27,5)), + Mop(Not, + Dest("Access_KR1C",bTy,Var("v",CTy"Perms"))))), + Bop(And,EQ(Var("cb",FTy 5),LW(28,5)), + Mop(Not,Dest("Access_KR2C",bTy,Var("v",CTy"Perms"))))), + qVar"state"]))) +; +val SignExtendBitString_def = Def + ("SignExtendBitString",TP[nVar"w",vVar"x"], + Mop(PadLeft,TP[Mop(Head,vVar"x"),nVar"w",vVar"x"])) +; +val dfn'DumpCapReg_def = Def + ("dfn'DumpCapReg",qVar"state", + Apply(Call("dumpCRegs",ATy(qTy,PTy(uTy,qTy)),LU),qVar"state")) +; +val dfn'CGetBase_def = Def + ("dfn'CGetBase",TP[Var("rd",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state"))], + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Var("rd",FTy 5)]),qVar"state")))) +; +val dfn'CGetOffset_def = Def + ("dfn'CGetOffset",TP[Var("rd",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state"))], + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Var("rd",FTy 5)]),qVar"state")))) +; +val dfn'CGetLen_def = Def + ("dfn'CGetLen",TP[Var("rd",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state"))], + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Var("rd",FTy 5)]),qVar"state")))) +; +val dfn'CGetTag_def = Def + ("dfn'CGetTag",TP[Var("rd",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 0,LN 0, + Mop(Cast F1, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + qVar"state")))), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"state"))), + Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 63,LN 1,LW(0,63), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"s"))), + Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'CGetSealed_def = Def + ("dfn'CGetSealed",TP[Var("rd",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 0,LN 0, + Mop(Cast F1, + Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + qVar"state")))), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"state"))), + Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 63,LN 1,LW(0,63), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"s"))), + Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'CGetPerm_def = Def + ("dfn'CGetPerm",TP[Var("rd",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 30,LN 0, + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"state"))), + Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 63,LN 31,LW(0,33), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"s"))), + Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'CGetType_def = Def + ("dfn'CGetType",TP[Var("rd",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 23,LN 0, + Dest + ("otype",FTy 24, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"state"))), + Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 63,LN 24,LW(0,40), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"s"))), + Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'CGetPCC_def = Def + ("dfn'CGetPCC",Var("cd",FTy 5), + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy,PTy(CTy"Capability",qTy))), + qVar"state")),Var("cd",FTy 5)]), + qVar"state")), + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("offset", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s"))]),Var("cd",FTy 5)]),qVar"s"))))) +; +val dfn'CGetCause_def = Def + ("dfn'CGetCause",Var("rd",FTy 5), + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Not, + Dest + ("Access_EPCC",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Const + ("PCC",ATy(qTy,PTy(CTy"Capability",qTy))), + qVar"state")))))), + Apply + (Call + ("SignalCapException_noReg",ATy(qTy,PTy(uTy,qTy)), + LC("capExcAccEPCC",CTy"CapException")),qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 7,LN 0, + Dest + ("RegNum",F8, + Mop(Fst, + Apply + (Const + ("capcause", + ATy(qTy,PTy(CTy"CapCause",qTy))), + qVar"state"))), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"state"))), + Var("rd",FTy 5)]),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 15,LN 8, + Dest + ("ExcCode",F8, + Mop(Fst, + Apply + (Const + ("capcause", + ATy(qTy, + PTy(CTy"CapCause",qTy))), + qVar"s"))), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"s"))), + Var("rd",FTy 5)]),qVar"s")), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[BFI(LN 63,LN 16,LW(0,48), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rd",FTy 5)),qVar"s"))), + Var("rd",FTy 5)]),qVar"s")))))) +; +val dfn'CSetCause_def = Def + ("dfn'CSetCause",Var("rt",FTy 5), + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Not, + Dest + ("Access_EPCC",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Const + ("PCC",ATy(qTy,PTy(CTy"Capability",qTy))), + qVar"state")))))), + Apply + (Call + ("SignalCapException_noReg",ATy(qTy,PTy(uTy,qTy)), + LC("capExcAccEPCC",CTy"CapException")),qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'capcause",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("ExcCode", + TP[Mop(Fst, + Apply + (Const + ("capcause", + ATy(qTy,PTy(CTy"CapCause",qTy))), + qVar"state")), + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 15,LN 8,F8)])),qVar"state")), + Apply + (Call + ("write'capcause",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("RegNum", + TP[Mop(Fst, + Apply + (Const + ("capcause", + ATy(qTy,PTy(CTy"CapCause",qTy))), + qVar"s")), + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 7, + LN 0,F8)])),qVar"s"))))) +; +val dfn'CIncBase_def = Def + ("dfn'CIncBase",TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Bop(And, + Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Mop(Not, + EQ(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")),LW(0,64)))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Bop(And, + Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Mop(Not, + EQ(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")),LW(0,64)))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Bop(Ugt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")), + Var("cd",FTy 5)]),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("base", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + qVar"s"))), + Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s")))]), + Var("cd",FTy 5)]),qVar"s")), + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("length", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + Bop(Sub, + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)),qVar"s"))), + Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")))]), + Var("cd",FTy 5)]),qVar"s")))))) +; +val dfn'CSetLen_def = Def + ("dfn'CSetLen",TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Bop(Ugt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")), + Var("cd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("length", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s"))]), + Var("cd",FTy 5)]),qVar"s"))))) +; +val dfn'CClearTag_def = Def + ("dfn'CClearTag",TP[Var("cd",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")), + Var("cd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("tag", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")),LF]), + Var("cd",FTy 5)]),qVar"s"))))) +; +val dfn'CAndPerm_def = Def + ("dfn'CAndPerm",TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")), + Var("cd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("perms", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + Bop(BAnd, + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s"))), + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 30,LN 0,FTy 31))]),Var("cd",FTy 5)]), + qVar"s"))))) +; +val dfn'CSetOffset_def = Def + ("dfn'CSetOffset",TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Bop(And, + Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")), + Var("cd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("offset", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s"))]), + Var("cd",FTy 5)]),qVar"s"))))) +; +val dfn'CCheckPerm_def = Def + ("dfn'CCheckPerm",TP[Var("cs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state")), + (Mop(Not, + EQ(Bop(BAnd, + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state"))), + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")),LN 30, + LN 0,FTy 31)), + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")),LN 30,LN 0, + FTy 31))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcUser",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state"))],TP[LU,qVar"state"]))) +; +val dfn'CCheckType_def = Def + ("dfn'CCheckType",TP[Var("cs",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Mop(Not, + EQ(Dest + ("otype",FTy 24, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state"))), + Dest + ("otype",FTy 24, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcType",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state"))],TP[LU,qVar"state"]))) +; +val dfn'CFromPtr_def = Def + ("dfn'CFromPtr",TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")),LW(0,64)), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("tag", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"state")), + LF]),Var("cd",FTy 5)]),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("sealed", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cd",FTy 5)),qVar"s")), + LF]),Var("cd",FTy 5)]),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("perms", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cd",FTy 5)), + qVar"s")),LW(0,31)]), + Var("cd",FTy 5)]),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("base", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cd",FTy 5)), + qVar"s")),LW(0,64)]), + Var("cd",FTy 5)]),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR", + ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("length", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cd", + FTy 5)), + qVar"s")), + LW(0,64)]), + Var("cd",FTy 5)]),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR", + ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("offset", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cd", + FTy 5)), + qVar"s")), + LW(0,64)]), + Var("cd",FTy 5)]),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR", + ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("otype", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cd", + FTy 5)), + qVar"s")), + LW(0,24)]), + Var("cd",FTy 5)]), + qVar"s")), + Apply + (Call + ("write'CAPR", + ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("reserved", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cd", + FTy 5)), + qVar"s")), + LW(0,8)]), + Var("cd",FTy 5)]),qVar"s"))))))))), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Bop(Ugt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")), + Var("cd",FTy 5)]),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("base", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + qVar"s"))), + Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s")))]), + Var("cd",FTy 5)]),qVar"s")), + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("length", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + Bop(Sub, + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)),qVar"s"))), + Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")))]), + Var("cd",FTy 5)]),qVar"s")))))) +; +val dfn'CToPtr_def = Def + ("dfn'CToPtr",TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("ct",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("ct",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("ct",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("ct",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[LW(0,64),Var("rd",FTy 5)]),qVar"state"))], + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Sub, + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))), + Var("rd",FTy 5)]),qVar"state")))) +; +val dfn'CPtrCmp_def = Def + ("dfn'CPtrCmp", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("ct",FTy 5),Var("t",FTy 3)], + Close + (qVar"state", + ITE(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state"), + TP[LU, + Let(TP[bVar"v", + Var("s", + PTy(bTy,PTy(bTy,PTy(bTy,PTy(bTy,PTy(bTy,qTy))))))], + CS(Let(TP[bVar"v", + Var("s3",PTy(bTy,PTy(bTy,PTy(bTy,qTy))))], + Let(TP[bVar"v",Var("s3",PTy(bTy,PTy(bTy,qTy)))], + Let(TP[bVar"v",Var("s3",PTy(bTy,qTy))], + Let(TP[bVar"v",qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("register_inaccessible", + ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)), + qVar"state")),qVar"state"], + TP[bVar"v",LF,qVar"s3"]), + TP[bVar"v",LX bTy,Var("s3",PTy(bTy,qTy))]), + TP[bVar"v",LX bTy, + Var("s3",PTy(bTy,PTy(bTy,qTy)))]), + TP[bVar"v",LX bTy, + Var("s3",PTy(bTy,PTy(bTy,PTy(bTy,qTy))))]), + [(TP[bVar"v", + Var("s3",PTy(bTy,PTy(bTy,PTy(bTy,PTy(bTy,qTy)))))], + TP[bVar"v",LX bTy, + Var("s3",PTy(bTy,PTy(bTy,PTy(bTy,PTy(bTy,qTy)))))])]), + Let(Var("s", + PTy(bTy,PTy(bTy,PTy(bTy,PTy(bTy,PTy(bTy,qTy)))))), + ITE(bVar"v", + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy,PTy(bTy,PTy(bTy,qTy))))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy,PTy(bTy,qTy)))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy,qTy))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + Mop(Snd, + Apply + (Call + ("SignalCapException_v", + ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))))], + Let(TP[bVar"v", + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy,PTy(bTy,PTy(bTy,qTy))))))], + CS(Let(TP[bVar"v", + Var("s3", + PTy(bTy,PTy(bTy,PTy(bTy,qTy))))], + Let(TP[bVar"v", + Var("s3",PTy(bTy,PTy(bTy,qTy)))], + Let(TP[bVar"v", + Var("s3",PTy(bTy,qTy))], + Let(TP[bVar"v",qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("register_inaccessible", + ATy(qTy, + PTy(bTy, + qTy)), + Var("ct", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))], + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + qVar"s3"]), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Var("s3",PTy(bTy,qTy))]), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Var("s3",PTy(bTy,PTy(bTy,qTy)))]), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Var("s3", + PTy(bTy,PTy(bTy,PTy(bTy,qTy))))]), + [(TP[bVar"v", + Var("s3", + PTy(bTy, + PTy(bTy,PTy(bTy,PTy(bTy,qTy)))))], + TP[bVar"v", + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy,qTy))))))), + Var("s3", + PTy(bTy, + PTy(bTy,PTy(bTy,PTy(bTy,qTy)))))])]), + ITE(bVar"v", + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy,qTy))))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + Mop(Snd, + Apply + (Call + ("SignalCapException_v", + ATy(qTy,PTy(uTy,qTy)), + Var("ct",FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))))], + Let(TP[Var("v",CTy"Capability"), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy,qTy))))))], + Let(TP[Var("v",CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy,qTy)))))], + Let(TP[Var("v",CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy,qTy))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy,qTy)))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy,qTy))], + Let(TP[Var("v", + CTy"Capability"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))], + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Var("s3", + PTy(bTy,qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Var("s3", + PTy(bTy, + PTy(bTy,qTy)))]), + TP[Var("v",CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy,qTy))))]), + TP[Var("v",CTy"Capability"), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy,qTy)))))]), + Let(TP[bVar"v", + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[bVar"v", + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[Var("v0", + CTy"Capability"), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + qTy))], + Let(TP[Var("v", + CTy"Capability"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("ct", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))], + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Var("s3", + PTy(bTy, + qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))]), + TP[EQ(Dest + ("tag",bTy, + Var("v", + CTy"Capability")), + Dest + ("tag",bTy, + Var("v0", + CTy"Capability"))), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))]), + TP[Mop(Not,bVar"v"), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))]), + ITE(bVar"v", + Let(TP[Var("v", + CTy"Capability"), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + qTy))], + Let(TP[Var("v", + CTy"Capability"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))], + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Var("s3", + PTy(bTy, + qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))]), + ITE(Dest + ("tag",bTy, + Var("v", + CTy"Capability")), + TP[LT, + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + TP[LF, + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + LF, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))]))], + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))), + LT, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))])], + TP[LF, + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + TP[LT, + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + LT, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))]))], + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))), + LF, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))])])), + Let(TP[Var("v", + CTy"Capability"), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + qTy))], + Let(TP[Var("v", + CTy"Capability"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))], + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Var("s3", + PTy(bTy, + qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))]), + Let(TP[Var("v",F64), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[Var("v0", + CTy"Capability"), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + qTy))], + Let(TP[Var("v", + CTy"Capability"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))], + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Var("s3", + PTy(bTy, + qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))]), + TP[Bop(Add, + Dest + ("base", + F64, + Var("v", + CTy"Capability")), + Dest + ("offset", + F64, + Var("v0", + CTy"Capability"))), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))]), + Let(TP[Var("v0", + CTy"Capability"), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + qTy))], + Let(TP[Var("v", + CTy"Capability"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("ct", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))], + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Var("s3", + PTy(bTy, + qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))]), + Let(TP[Var("v0", + F64), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[Var("v1", + CTy"Capability"), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + qTy))], + Let(TP[Var("v", + CTy"Capability"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("ct", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))], + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Var("s3", + PTy(bTy, + qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + qTy)))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + Var("s3", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))]), + TP[Bop(Add, + Dest + ("base", + F64, + Var("v0", + CTy"Capability")), + Dest + ("offset", + F64, + Var("v1", + CTy"Capability"))), + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))]), + TP[Bop(Ugt, + Var("v", + F64), + Var("v0", + F64)), + Bop(Ult, + Var("v", + F64), + Var("v0", + F64)), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + qTy)))), + EQ(Var("v", + F64), + Var("v0", + F64)), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + qTy)))))])])]), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))), + Bop(Lt, + Var("v", + F64), + Var("v0", + F64)), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))])]), + TP[Bop(Gt, + Var("v", + F64), + Var("v0", + F64)), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))])])))))))))), + CS(Var("t",FTy 3), + [(LW(0,3), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))), + Var("rd",FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))))), + (LW(1,3), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Mop(Not, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Var("rd",FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))))), + (LW(2,3), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))), + Var("rd",FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))))), + (LW(3,3), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Bop(Or, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Var("rd",FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))))), + (LW(4,3), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))), + Var("rd",FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))))), + (LW(5,3), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Bop(Or, + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))), + Var("rd",FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy)))))))))))))), + (AVar(FTy 3), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + PTy(bTy, + qTy))))))))))))])))]))) +; +val dfn'CBTU_def = Def + ("dfn'CBTU",TP[Var("cb",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible", + ATy(qTy,PTy(bTy,qTy)),Var("cb",FTy 5)), + qVar"s")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"s")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))), + ITE(Bop(Ugt, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const + ("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")), + Mop(SE F64,Var("offset",F16))), + LW(4,64)), + Dest + ("length",F64, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy,PTy(CTy"Capability",qTy))), + qVar"s")))), + Apply + (Call + ("SignalCapException_noReg", + ATy(qTy,PTy(uTy,qTy)), + LC("capExcLength",CTy"CapException")), + qVar"s"), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const + ("PC", + ATy(qTy,PTy(F64,qTy))), + qVar"s")),LW(4,64)), + Bop(Lsl, + Mop(SE F64,Var("offset",F16)), + LN 2)))),qVar"s")))], + TP[LU,qVar"s"]))))) +; +val dfn'CBTS_def = Def + ("dfn'CBTS",TP[Var("cb",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible", + ATy(qTy,PTy(bTy,qTy)),Var("cb",FTy 5)), + qVar"s")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"s")), + (Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s"))), + ITE(Bop(Ugt, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const + ("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")), + Mop(SE F64,Var("offset",F16))), + LW(4,64)), + Dest + ("length",F64, + Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy,PTy(CTy"Capability",qTy))), + qVar"s")))), + Apply + (Call + ("SignalCapException_noReg", + ATy(qTy,PTy(uTy,qTy)), + LC("capExcLength",CTy"CapException")), + qVar"s"), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const + ("PC", + ATy(qTy,PTy(F64,qTy))), + qVar"s")),LW(4,64)), + Bop(Lsl, + Mop(SE F64,Var("offset",F16)), + LN 2)))),qVar"s")))], + TP[LU,qVar"s"]))))) +; +val dfn'CSC_def = Def + ("dfn'CSC", + TP[Var("cs",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5),Var("offset",FTy 11)], + Close + (qVar"state", + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("Permit_Store_Capability",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermStoreCap",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Bop(And, + Bop(And, + Mop(Not, + Dest + ("Permit_Store_Local_Capability",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))))), + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state")))), + Mop(Not, + Dest + ("Global",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state"))))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermStoreLocalCap",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state"))], + Let(Var("v",F64), + Bop(Add, + Bop(Add, + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))), + Mop(SE F64,Var("offset",FTy 11))), + ITB([(Bop(Ugt, + Bop(Add, + Bop(Add, + CC[LW(0,1), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))], + Mop(SE(FTy 65),Var("offset",FTy 11))), + LW(32,65)), + CC[LW(0,1), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))]), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Bop(Lt, + Bop(Add, + CC[LW(0,1), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))], + Mop(SE(FTy 65),Var("offset",FTy 11))),LW(0,65)), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Mop(Not,EQ(EX(Var("v",F64),LN 4,LN 0,FTy 5),LW(0,5))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdES",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"state")),Var("v",F64)])), + qVar"state"))))], + Apply + (Call("write'LLbit",ATy(qTy,PTy(uTy,qTy)),LO bTy), + Mop(Snd, + Apply + (Call + ("StoreCap",ATy(qTy,PTy(uTy,qTy)), + TP[Var("v",F64), + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state"))]), + qVar"state")))))))) +; +val dfn'CLC_def = Def + ("dfn'CLC", + TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5),Var("offset",FTy 11)], + Close + (qVar"state", + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("Permit_Load_Capability",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermLoadCap",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state"))], + Let(Var("v",F64), + Bop(Add, + Bop(Add, + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))), + Mop(SE F64,Var("offset",FTy 11))), + ITB([(Bop(Ugt, + Bop(Add, + Bop(Add, + CC[LW(0,1), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))], + Mop(SE(FTy 65),Var("offset",FTy 11))), + LW(32,65)), + CC[LW(0,1), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))]), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Bop(Lt, + Bop(Add, + CC[LW(0,1), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))], + Mop(SE(FTy 65),Var("offset",FTy 11))),LW(0,65)), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Mop(Not,EQ(EX(Var("v",F64),LN 4,LN 0,FTy 5),LW(0,5))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdEL",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"state")),Var("v",F64)])), + qVar"state"))))], + Let(TP[Var("v",CTy"Capability"),qVar"s"], + Apply + (Call + ("LoadCap",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("v",F64)),qVar"state"), + Apply + (Call("write'LLbit",ATy(qTy,PTy(uTy,qTy)),LO bTy), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s"))), + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("v",CTy"Capability"), + Var("cd",FTy 5)]),qVar"s")), + qVar"s")))))))) +; +val dfn'CLoad_def = Def + ("dfn'CLoad", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5),Var("offset",F8), + Var("s",F1),Var("t",FTy 2)], + Close + (qVar"state", + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("Permit_Load",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermLoad",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state"))], + TP[LU, + Let(TP[Var("v",CTy"Capability"), + Var("s0",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))], + Let(TP[Var("v",CTy"Capability"), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))], + Let(TP[Var("v",CTy"Capability"), + Var("s3",PTy(FTy 3,qTy))], + Let(TP[Var("v",CTy"Capability"),qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")), + qVar"state"], + TP[Var("v",CTy"Capability"),LX(FTy 3), + qVar"s3"]), + TP[Var("v",CTy"Capability"),LX(FTy 65), + Var("s3",PTy(FTy 3,qTy))]), + TP[Var("v",CTy"Capability"),LX bTy, + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))]), + Let(TP[Var("v",F64), + Var("s0",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))], + Let(TP[Var("v0",CTy"Capability"), + Var("s",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))], + Let(TP[Var("v",CTy"Capability"), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))], + Let(TP[Var("v",CTy"Capability"), + Var("s3",PTy(FTy 3,qTy))], + Let(TP[Var("v",CTy"Capability"),qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))], + TP[Var("v",CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + qVar"s3"]), + TP[Var("v",CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy)))))), + Var("s3",PTy(FTy 3,qTy))]), + TP[Var("v",CTy"Capability"), + Mop(Fst, + Var("s0", + PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))]), + TP[Bop(Add, + Dest("base",F64,Var("v",CTy"Capability")), + Dest + ("offset",F64,Var("v0",CTy"Capability"))), + Var("s",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))]), + Let(TP[Var("v0",F64), + Var("s0",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))], + Let(TP[Var("v",F64), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))], + Let(TP[Var("v",F64),Var("s3",PTy(FTy 3,qTy))], + Let(TP[Var("v",F64),qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))], + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + qVar"s3"]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy)))))), + Var("s3",PTy(FTy 3,qTy))]), + TP[Var("v",F64), + Mop(Fst, + Var("s0", + PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))]), + Let(Var("v",F64), + Bop(Add,Bop(Add,Var("v",F64),Var("v0",F64)), + Mop(SE F64,Var("offset",F8))), + Let(Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65,PTy(FTy 3,qTy)))))), + CS(Var("t",FTy 2), + [(LW(0,2), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[LW(0,3), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Var("v",F64), + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + LW(1,65), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Let(Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Const + ("BYTE", + FTy 3), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))))])])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(TP[Var("v",FTy 3), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v0",F1), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F1), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy, + PTy(F1, + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + F1), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + TP[Bop(BXor, + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 2, + LN 0, + FTy 3), + REP(Var("v0", + F1), + LN 3, + FTy 3)), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + TP[Var("v",FTy 3), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))]), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + LT, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))])])))), + (LW(1,2), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[LW(0,3), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Var("v",F64), + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + LW(2,65), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Let(Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Const + ("HALFWORD", + FTy 3), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))))])])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(TP[Var("v",FTy 3), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v0",F1), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F1), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy, + PTy(F1, + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + F1), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + TP[Bop(BXor, + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 2, + LN 0, + FTy 3), + CC[REP(Var("v0", + F1), + LN + 2, + FTy 2), + LW(0,1)]), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + TP[Var("v",FTy 3), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))]), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + EQ(Bop(Bit, + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 0), + LF), + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))])])))), + (LW(2,2), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[LW(0,3), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Var("v",F64), + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + LW(4,65), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Let(Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Const + ("WORD", + FTy 3), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))))])])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(TP[Var("v",FTy 3), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v0",F1), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F1), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy, + PTy(F1, + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + F1), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + TP[Bop(BXor, + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 2, + LN 0, + FTy 3), + CC[Var("v0", + F1), + LW(0,2)]), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + TP[Var("v",FTy 3), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))]), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + EQ(EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 1, + LN 0, + FTy 2), + LW(0,2)), + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))])])))), + (LW(3,2), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[LW(0,3), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Var("v",F64), + Var("s0", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + LW(8,65), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Let(Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Const + ("DOUBLEWORD", + FTy 3), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))))])])])], + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + EQ(EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 2,LN 0, + FTy 3), + LW(0,3)), + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))])])))]), + Let(TP[Var("v",F64), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy))))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy)))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(FTy 65, + PTy(FTy 3,qTy)))], + Let(TP[Var("v",F64), + Var("s3", + PTy(FTy 3,qTy))], + Let(TP[Var("v",F64), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy, + PTy(F64, + qTy)), + Var("rt", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3,qTy))]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3,qTy)))]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy))))]), + TP[Var("v",F64), + Mop(Fst, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy)))))]), + Let(TP[bVar"v", + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v0",CTy"Capability"), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + CTy"Capability"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + TP[Bop(Ugt, + Bop(Add, + Bop(Add, + Mop(SE(FTy 65), + Var("offset", + F8)), + CC[LW(0,1), + Var("v",F64)]), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + CC[LW(0,1), + Dest + ("length",F64, + Var("v0", + CTy"Capability"))]), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + ITE(bVar"v", + Mop(Snd, + Apply + (Call + ("SignalCapException", + ATy(qTy, + PTy(uTy,qTy)), + TP[LC("capExcLength", + CTy"CapException"), + Var("cb",FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Let(TP[Var("v",F64), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F64), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy, + PTy(F64, + qTy)), + Var("rt", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v",F64), + Mop(Fst, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + ITB([(Bop(Lt, + Bop(Add, + Mop(SE(FTy 65), + Var("offset", + F8)), + CC[LW(0,1), + Var("v", + F64)]), + LW(0,65)), + Mop(Snd, + Apply + (Call + ("SignalCapException", + ATy(qTy, + PTy(uTy, + qTy)), + TP[LC("capExcLength", + CTy"CapException"), + Var("cb", + FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))))), + (Mop(Not, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("BadVAddr", + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))])), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))))], + Mop(Snd, + Apply + (Call + ("SignalException", + ATy(qTy, + PTy(uTy, + qTy)), + LC("AdEL", + CTy"ExceptionType")), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))))))], + Let(TP[Var("v",F64), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F64), + qVar"s3"], + Apply + (Call + ("LoadMemoryCap", + ATy(qTy, + PTy(F64, + qTy)), + TP[Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LC("DATA", + CTy"IorD"), + LC("LOAD", + CTy"AccessType"), + LF]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + F64), + Mop(Fst, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + Let(TP[bVar"v0", + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[bVar"v", + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[bVar"v", + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[bVar"v", + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[bVar"v", + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[bVar"v", + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy, + PTy(bTy, + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[bVar"v", + Mop(Fst, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + ITE(Mop(Not, + bVar"v0"), + Let(vVar"final_data", + EX(Mop(Cast + vTy, + Var("v", + F64)), + Bop(Sub, + Bop(Add, + Bop(Mul, + Mop(Cast + nTy, + Mop(Fst, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN + 8), + Bop(Mul, + Mop(Cast + nTy, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + LN + 8)), + LN + 1), + Bop(Mul, + Mop(Cast + nTy, + Mop(Fst, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN + 8), + vTy), + ITE(EQ(Var("s", + F1), + LW(0, + 1)), + Mop(Snd, + Apply + (Call + ("write'GPR", + ATy(qTy, + PTy(uTy, + qTy)), + TP[Mop(Cast + F64, + vVar"final_data"), + Var("rd", + FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Apply + (Call + ("write'GPR", + ATy(qTy, + PTy(uTy, + qTy)), + TP[Mop(Cast + F64, + Call + ("SignExtendBitString", + vTy, + TP[LN + 64, + vVar"final_data"])), + Var("rd", + FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))))))))))))))]))) +; +val dfn'CLLD_def = Def + ("dfn'CLLD", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5),Var("offset",F8)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Bop(Add, + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))),Mop(SE F64,Var("offset",F8))), + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Mop(Not, + Dest + ("Permit_Load",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermLoad",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Bop(Ugt, + Bop(Add, + Bop(Add,Mop(SE(FTy 65),Var("offset",F8)), + CC[LW(0,1), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))]), + LW(8,65)), + CC[LW(0,1), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))]), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Bop(Lt, + Bop(Add,Mop(SE(FTy 65),Var("offset",F8)), + CC[LW(0,1), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))]), + LW(0,65)), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Mop(Not,EQ(EX(Var("v",F64),LN 3,LN 0,F4),LW(0,4))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdEL",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"state")), + Var("v",F64)])),qVar"state"))))], + Let(TP[Var("v",F64),qVar"s"], + Apply + (Call + ("LoadMemoryCap",ATy(qTy,PTy(F64,qTy)), + TP[Const("DOUBLEWORD",FTy 3),Var("v",F64), + LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),LT]),qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("v",F64),Var("rd",FTy 5)]),qVar"s")))))) +; +val dfn'CStore_def = Def + ("dfn'CStore", + TP[Var("rs",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5),Var("offset",F8), + Var("t",FTy 2)], + Close + (qVar"state", + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("Permit_Store",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermStore",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state"))], + TP[LU, + Let(TP[Var("v",CTy"Capability"), + Var("s",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))], + Let(TP[Var("v",CTy"Capability"), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))], + Let(TP[Var("v",CTy"Capability"), + Var("s3",PTy(FTy 3,qTy))], + Let(TP[Var("v",CTy"Capability"),qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")), + qVar"state"], + TP[Var("v",CTy"Capability"),LX(FTy 3), + qVar"s3"]), + TP[Var("v",CTy"Capability"),LX(FTy 65), + Var("s3",PTy(FTy 3,qTy))]), + TP[Var("v",CTy"Capability"),LX bTy, + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))]), + Let(TP[Var("v",F64), + Var("s",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))], + Let(TP[Var("v0",CTy"Capability"), + Var("s",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))], + Let(TP[Var("v",CTy"Capability"), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))], + Let(TP[Var("v",CTy"Capability"), + Var("s3",PTy(FTy 3,qTy))], + Let(TP[Var("v",CTy"Capability"),qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))], + TP[Var("v",CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + qVar"s3"]), + TP[Var("v",CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy)))))), + Var("s3",PTy(FTy 3,qTy))]), + TP[Var("v",CTy"Capability"), + Mop(Fst, + Var("s", + PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))]), + TP[Bop(Add, + Dest("base",F64,Var("v",CTy"Capability")), + Dest + ("offset",F64,Var("v0",CTy"Capability"))), + Var("s",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))]), + Let(TP[Var("v0",F64), + Var("s",PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))], + Let(TP[Var("v",F64), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))], + Let(TP[Var("v",F64),Var("s3",PTy(FTy 3,qTy))], + Let(TP[Var("v",F64),qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))], + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + qVar"s3"]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy)))))), + Var("s3",PTy(FTy 3,qTy))]), + TP[Var("v",F64), + Mop(Fst, + Var("s", + PTy(bTy,PTy(FTy 65,PTy(FTy 3,qTy))))), + Var("s3",PTy(FTy 65,PTy(FTy 3,qTy)))]), + Let(Var("v",F64), + Bop(Add,Bop(Add,Var("v",F64),Var("v0",F64)), + Mop(SE F64,Var("offset",F8))), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65,PTy(FTy 3,qTy)))))), + CS(Var("t",FTy 2), + [(LW(0,2), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[LW(0,3), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Var("v",F64), + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + LW(1,65), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Let(Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Const + ("BYTE", + FTy 3), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))))])])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(TP[Var("v",FTy 3), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v0",F1), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F1), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy, + PTy(F1, + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + F1), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + TP[Bop(BXor, + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 2, + LN 0, + FTy 3), + REP(Var("v0", + F1), + LN 3, + FTy 3)), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + TP[Var("v",FTy 3), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))]), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + LT, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))])])))), + (LW(1,2), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[LW(0,3), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Var("v",F64), + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + LW(2,65), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Let(Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Const + ("HALFWORD", + FTy 3), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))))])])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(TP[Var("v",FTy 3), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v0",F1), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F1), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy, + PTy(F1, + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + F1), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + TP[Bop(BXor, + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 2, + LN 0, + FTy 3), + CC[REP(Var("v0", + F1), + LN + 2, + FTy 2), + LW(0,1)]), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + TP[Var("v",FTy 3), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))]), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + EQ(Bop(Bit, + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 0), + LF), + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))])])))), + (LW(2,2), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[LW(0,3), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Var("v",F64), + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + LW(4,65), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Let(Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Const + ("WORD", + FTy 3), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))))])])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(TP[Var("v",FTy 3), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v0",F1), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F1), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F1), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy, + PTy(F1, + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + F1), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + F1), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + TP[Bop(BXor, + EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 2, + LN 0, + FTy 3), + CC[REP(Var("v0", + F1), + LN + 1, + F1), + LW(0,2)]), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + TP[Var("v",FTy 3), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))]), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + EQ(EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 1, + LN 0, + FTy 2), + LW(0,2)), + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))])])))), + (LW(3,2), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[LW(0,3), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Var("v",F64), + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + LW(8,65), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))])])], + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + Let(Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Mop(Snd, + Var("s", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Let(Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy))), + Mop(Snd, + Var("s", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))), + Const + ("DOUBLEWORD", + FTy 3), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 65, + PTy(FTy 3, + qTy)))))])])])], + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Let(Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))), + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + TP[Mop(Fst, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + EQ(EX(Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LN 2,LN 0, + FTy 3), + LW(0,3)), + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))])])))]), + Let(TP[Var("v",F64), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy))))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy)))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(FTy 65, + PTy(FTy 3,qTy)))], + Let(TP[Var("v",F64), + Var("s3", + PTy(FTy 3,qTy))], + Let(TP[Var("v",F64), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy, + PTy(F64, + qTy)), + Var("rt", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3,qTy))]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3,qTy)))]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy))))]), + TP[Var("v",F64), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3,qTy)))))]), + Let(TP[bVar"v", + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v0",CTy"Capability"), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + CTy"Capability"), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + CTy"Capability"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + CTy"Capability"), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + TP[Bop(Ugt, + Bop(Add, + Bop(Add, + Mop(SE(FTy 65), + Var("offset", + F8)), + CC[LW(0,1), + Var("v",F64)]), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + CC[LW(0,1), + Dest + ("length",F64, + Var("v0", + CTy"Capability"))]), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + ITE(bVar"v", + Mop(Snd, + Apply + (Call + ("SignalCapException", + ATy(qTy, + PTy(uTy,qTy)), + TP[LC("capExcLength", + CTy"CapException"), + Var("cb",FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Let(TP[Var("v",F64), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v",F64), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F64), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy, + PTy(F64, + qTy)), + Var("rt", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v",F64), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v",F64), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + ITB([(Bop(Lt, + Bop(Add, + Mop(SE(FTy 65), + Var("offset", + F8)), + CC[LW(0,1), + Var("v", + F64)]), + LW(0,65)), + Mop(Snd, + Apply + (Call + ("SignalCapException", + ATy(qTy, + PTy(uTy, + qTy)), + TP[LC("capExcLength", + CTy"CapException"), + Var("cb", + FTy 5)]), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))))), + (Mop(Not, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + CTy"CP0__renamed__"), + qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + Let(Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))), + TP[Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("BadVAddr", + TP[Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))])), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))))], + Mop(Snd, + Apply + (Call + ("SignalException", + ATy(qTy, + PTy(uTy, + qTy)), + LC("AdES", + CTy"ExceptionType")), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))))))], + Let(TP[bVar"v", + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + PTy(FTy 3, + PTy(FTy 3, + PTy(F64, + PTy(F64, + PTy(CTy"IorD", + PTy(CTy"AccessType", + bTy))))))), + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v0", + PTy(FTy 3, + PTy(F64, + PTy(F64, + PTy(CTy"IorD", + PTy(CTy"AccessType", + bTy)))))), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v1", + F64), + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[Var("v", + F64), + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[Var("v", + F64), + qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy, + PTy(F64, + qTy)), + Var("rs", + FTy 5)), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))], + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[Var("v", + F64), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[Var("v", + F64), + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))]), + TP[TP[Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + Bop(Lsl, + Var("v1", + F64), + Bop(Mul, + LN + 8, + Mop(Cast + nTy, + Mop(Fst, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Mop(Fst, + Mop(Snd, + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + LC("DATA", + CTy"IorD"), + LC("STORE", + CTy"AccessType"), + LF], + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + TP[TP[Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + Var("v0", + PTy(FTy 3, + PTy(F64, + PTy(F64, + PTy(CTy"IorD", + PTy(CTy"AccessType", + bTy))))))], + Var("s0", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))]), + Let(TP[bVar"v", + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))], + Let(TP[bVar"v", + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))], + Let(TP[bVar"v", + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))], + Let(TP[bVar"v", + Var("s3", + PTy(FTy 3, + qTy))], + Let(TP[bVar"v", + qVar"s3"], + Apply + (Call + ("StoreMemoryCap", + ATy(qTy, + PTy(bTy, + qTy)), + Var("v", + PTy(FTy 3, + PTy(FTy 3, + PTy(F64, + PTy(F64, + PTy(CTy"IorD", + PTy(CTy"AccessType", + bTy)))))))), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))))), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))), + qVar"s3"]), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))))), + Var("s3", + PTy(FTy 3, + qTy))]), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))), + Var("s3", + PTy(FTy 65, + PTy(FTy 3, + qTy)))]), + TP[bVar"v", + Mop(Fst, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))))), + Var("s3", + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))]), + TP[bVar"v", + Mop(Fst, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))), + Var("s3", + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy)))))])), + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(FTy 3, + PTy(F64, + PTy(bTy, + PTy(FTy 65, + PTy(FTy 3, + qTy))))))))))))))))))))))]))) +; +val dfn'CSCD_def = Def + ("dfn'CSCD", + TP[Var("rs",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5),Var("offset",F8)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Bop(Add, + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))),Mop(SE F64,Var("offset",F8))), + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cb",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Mop(Not, + Dest + ("Permit_Store",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermStore",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Bop(Ugt, + Bop(Add, + Bop(Add,Mop(SE(FTy 65),Var("offset",F8)), + CC[LW(0,1), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))]), + LW(32,65)), + CC[LW(0,1), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"state")))]), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Bop(Lt, + Bop(Add,Mop(SE(FTy 65),Var("offset",F8)), + CC[LW(0,1), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state"))]), + LW(0,65)), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"state")), + (Mop(Not,EQ(EX(Var("v",F64),LN 4,LN 0,FTy 5),LW(0,5))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdES",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"state")), + Var("v",F64)])),qVar"state"))))], + Let(TP[Var("v",PTy(F64,FTy 5)),qVar"s"], + Let(TP[Var("v",F64),qVar"s"], + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("StoreMemoryCap",ATy(qTy,PTy(bTy,qTy)), + TP[Const("DOUBLEWORD",FTy 3), + Const("DOUBLEWORD",FTy 3), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")), + Var("v",F64),LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),LT]), + qVar"state"), + TP[ITE(bVar"v",LW(1,64),LW(0,64)),qVar"s"]), + TP[TP[Var("v",F64),Var("rs",FTy 5)],qVar"s"]), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + Var("v",PTy(F64,FTy 5))),qVar"s")))))) +; +val dfn'CJR_def = Def + ("dfn'CJR",Var("cb",FTy 5), + Close + (qVar"state", + ITE(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible", + ATy(qTy,PTy(bTy,qTy)),Var("cb",FTy 5)), + qVar"s")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"s")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Mop(Not, + Dest + ("Permit_Execute",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermExe",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Mop(Not, + Dest + ("Global",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcGlobal",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Bop(Ugt, + Bop(Add, + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s"))), + LW(4,64)), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Mop(Not, + EQ(EX(Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))), + LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdEL",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + qVar"s"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + qVar"s"))))])), + qVar"s"))))], + Apply + (Call + ("write'BranchToPCC",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + TP[Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s"))), + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s"))])), + qVar"s")))))) +; +val dfn'CJALR_def = Def + ("dfn'CJALR",TP[Var("cd",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITE(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + ITB([(Mop(Fst, + Apply + (Call + ("register_inaccessible", + ATy(qTy,PTy(bTy,qTy)),Var("cd",FTy 5)), + qVar"s")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"s")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible", + ATy(qTy,PTy(bTy,qTy)),Var("cb",FTy 5)), + qVar"s")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cb",FTy 5)),qVar"s")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Mop(Not, + Dest + ("Permit_Execute",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermExe",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Mop(Not, + Dest + ("Global",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcGlobal",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Bop(Ugt, + Bop(Add, + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s"))), + LW(4,64)), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"), + Var("cb",FTy 5)]),qVar"s")), + (Mop(Not, + EQ(EX(Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cb",FTy 5)),qVar"s")))), + LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdEL",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + qVar"s"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + qVar"s"))))])), + qVar"s"))))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Const + ("PCC", + ATy(qTy, + PTy(CTy"Capability",qTy))), + qVar"s")),Var("cd",FTy 5)]), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("offset", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cd",FTy 5)), + qVar"s")), + Bop(Add, + Mop(Fst, + Apply + (Const + ("PC", + ATy(qTy, + PTy(F64,qTy))), + qVar"s")),LW(8,64))]), + Var("cd",FTy 5)]),qVar"s")), + Apply + (Call + ("write'BranchToPCC",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + TP[Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)), + qVar"s"))), + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cb",FTy 5)),qVar"s"))])), + qVar"s")))))))) +; +val dfn'CSeal_def = Def + ("dfn'CSeal",TP[Var("cd",FTy 5),Var("cs",FTy 5),Var("ct",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("ct",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("ct",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("ct",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("ct",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("Permit_Seal",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermSeal",CTy"CapException"), + Var("ct",FTy 5)]),qVar"state")), + (Bop(Uge, + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state"))), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"),Var("ct",FTy 5)]), + qVar"state")), + (Bop(Uge, + Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))), + LW(16777216,64)), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"),Var("ct",FTy 5)]), + qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state")), + Var("cd",FTy 5)]),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("sealed", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + LT]),Var("cd",FTy 5)]),qVar"s")), + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("otype", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + EX(Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("ct",FTy 5)), + qVar"s"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("ct",FTy 5)), + qVar"s")))),LN 23,LN 0, + FTy 24)]),Var("cd",FTy 5)]),qVar"s")))))) +; +val dfn'CUnseal_def = Def + ("dfn'CUnseal",TP[Var("cd",FTy 5),Var("cs",FTy 5),Var("ct",FTy 5)], + Close + (qVar"state", + ITB([(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cd",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("cs",FTy 5)),qVar"state")), + (Mop(Fst, + Apply + (Call + ("register_inaccessible",ATy(qTy,PTy(bTy,qTy)), + Var("ct",FTy 5)),qVar"state")), + Apply + (Call + ("SignalCapException_v",ATy(qTy,PTy(uTy,qTy)), + Var("ct",FTy 5)),qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("tag",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcTag",CTy"CapException"),Var("ct",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state")), + (Dest + ("sealed",bTy, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state"))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcSeal",CTy"CapException"),Var("ct",FTy 5)]), + qVar"state")), + (Mop(Not, + EQ(EX(Bop(Add, + Dest + ("base",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state"))), + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))), + LN 23,LN 0,FTy 24), + Dest + ("otype",FTy 24, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state"))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcType",CTy"CapException"),Var("ct",FTy 5)]), + qVar"state")), + (Mop(Not, + Dest + ("Permit_Seal",bTy, + Call + ("rec'Perms",CTy"Perms", + Dest + ("perms",FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcPermSeal",CTy"CapException"), + Var("ct",FTy 5)]),qVar"state")), + (Bop(Uge, + Dest + ("offset",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state"))), + Dest + ("length",F64, + Mop(Fst, + Apply + (Call + ("CAPR",ATy(qTy,PTy(CTy"Capability",qTy)), + Var("ct",FTy 5)),qVar"state")))), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcLength",CTy"CapException"),Var("ct",FTy 5)]), + qVar"state"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cs",FTy 5)),qVar"state")), + Var("cd",FTy 5)]),qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("sealed", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + LF]),Var("cd",FTy 5)]),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("otype", + TP[Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cd",FTy 5)), + qVar"s")),LW(0,24)]), + Var("cd",FTy 5)]),qVar"s")), + Let(Var("v",CTy"Capability"), + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy,PTy(CTy"Capability",qTy)), + Var("cd",FTy 5)),qVar"s")), + Let(Var("x1",FTy 31), + Dest + ("perms",FTy 31,Var("v",CTy"Capability")), + Apply + (Call + ("write'CAPR",ATy(qTy,PTy(uTy,qTy)), + TP[Rupd + ("perms", + TP[Var("v",CTy"Capability"), + Call + ("write'rec'Perms",FTy 31, + TP[Var("x1",FTy 31), + Rupd + ("Global", + TP[Call + ("rec'Perms", + CTy"Perms", + Var("x1", + FTy 31)), + Bop(And, + Dest + ("Global", + bTy, + Call + ("rec'Perms", + CTy"Perms", + Dest + ("perms", + FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("cs", + FTy 5)), + qVar"s"))))), + Dest + ("Global", + bTy, + Call + ("rec'Perms", + CTy"Perms", + Dest + ("perms", + FTy 31, + Mop(Fst, + Apply + (Call + ("CAPR", + ATy(qTy, + PTy(CTy"Capability", + qTy)), + Var("ct", + FTy 5)), + qVar"s"))))))])])]), + Var("cd",FTy 5)]),qVar"s"))))))))) +; +val dfn'CCall_def = Def + ("dfn'CCall",TP[Var("cs",FTy 5),Var("cb",FTy 5)], + Close + (qVar"state", + ITE(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state"), + Apply + (Call + ("SignalCapException",ATy(qTy,PTy(uTy,qTy)), + TP[LC("capExcCall",CTy"CapException"),Var("cs",FTy 5)]), + qVar"state")))) +; +val dfn'CReturn_def = Def + ("dfn'CReturn",qVar"state", + ITE(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state"), + Apply + (Call + ("SignalCapException_noReg",ATy(qTy,PTy(uTy,qTy)), + LC("capExcRet",CTy"CapException")),qVar"state"))) +; +val dfn'UnknownCapInstruction_def = Def + ("dfn'UnknownCapInstruction",qVar"state", + ITE(Mop(Not, + Dest + ("CU2",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state"))))), + Apply + (Const("SignalCP2UnusableException",ATy(qTy,PTy(uTy,qTy))), + qVar"state"), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state"))) +; +val dfn'ADDI_def = Def + ("dfn'ADDI",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Let(qVar"s", + ITE(Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"ADDI: NotWordValue")),qVar"state")), + qVar"state"), + Let(Var("v",FTy 33), + Bop(Add, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"s")),LN 32,LN 0,FTy 33), + Mop(SE(FTy 33),Var("immediate",F16))), + ITE(Mop(Not, + EQ(Bop(Bit,Var("v",FTy 33),LN 32), + Bop(Bit,Var("v",FTy 33),LN 31))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Ov",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64,EX(Var("v",FTy 33),LN 31,LN 0,F32)), + Var("rt",FTy 5)]),qVar"s")))))) +; +val dfn'ADDIU_def = Def + ("dfn'ADDIU",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Let(qVar"s", + ITE(Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"ADDIU: NotWordValue")),qVar"state")), + qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Add, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")),LN 31, + LN 0,F32),Mop(SE F32,Var("immediate",F16)))), + Var("rt",FTy 5)]),qVar"s")))) +; +val dfn'DADDI_def = Def + ("dfn'DADDI",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Let(Var("v",FTy 65), + Bop(Add, + Mop(SE(FTy 65), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Mop(SE(FTy 65),Var("immediate",F16))), + ITE(Mop(Not, + EQ(Bop(Bit,Var("v",FTy 65),LN 64), + Bop(Bit,Var("v",FTy 65),LN 63))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Ov",CTy"ExceptionType")),qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[EX(Var("v",FTy 65),LN 63,LN 0,F64),Var("rt",FTy 5)]), + qVar"state"))))) +; +val dfn'DADDIU_def = Def + ("dfn'DADDIU",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(SE F64,Var("immediate",F16))), + Var("rt",FTy 5)]),qVar"state"))) +; +val dfn'SLTI_def = Def + ("dfn'SLTI",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Bop(Lt, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")), + Mop(SE F64,Var("immediate",F16)))),Var("rt",FTy 5)]), + qVar"state"))) +; +val dfn'SLTIU_def = Def + ("dfn'SLTIU",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Bop(Ult, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")), + Mop(SE F64,Var("immediate",F16)))),Var("rt",FTy 5)]), + qVar"state"))) +; +val dfn'ANDI_def = Def + ("dfn'ANDI",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(BAnd, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(Cast F64,Var("immediate",F16))), + Var("rt",FTy 5)]),qVar"state"))) +; +val dfn'ORI_def = Def + ("dfn'ORI",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(BOr, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(Cast F64,Var("immediate",F16))), + Var("rt",FTy 5)]),qVar"state"))) +; +val dfn'XORI_def = Def + ("dfn'XORI",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(BXor, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(Cast F64,Var("immediate",F16))), + Var("rt",FTy 5)]),qVar"state"))) +; +val dfn'LUI_def = Def + ("dfn'LUI",TP[Var("rt",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64,CC[Var("immediate",F16),LW(0,16)]), + Var("rt",FTy 5)]),qVar"state"))) +; +val dfn'ADD_def = Def + ("dfn'ADD",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"ADD: NotWordValue")),qVar"state")), + qVar"state"), + Let(Var("v",FTy 33), + Bop(Add, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"s")),LN 32,LN 0,FTy 33), + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"s")),LN 32,LN 0,FTy 33)), + ITE(Mop(Not, + EQ(Bop(Bit,Var("v",FTy 33),LN 32), + Bop(Bit,Var("v",FTy 33),LN 31))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Ov",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64,EX(Var("v",FTy 33),LN 31,LN 0,F32)), + Var("rd",FTy 5)]),qVar"s")))))) +; +val dfn'ADDU_def = Def + ("dfn'ADDU",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"ADDU: NotWordValue")),qVar"state")), + qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Add, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")),LN 31, + LN 0,F32), + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32))),Var("rd",FTy 5)]),qVar"s")))) +; +val dfn'SUB_def = Def + ("dfn'SUB",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"SUB: NotWordValue")),qVar"state")), + qVar"state"), + Let(Var("v",FTy 33), + Bop(Sub, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"s")),LN 32,LN 0,FTy 33), + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"s")),LN 32,LN 0,FTy 33)), + ITE(Mop(Not, + EQ(Bop(Bit,Var("v",FTy 33),LN 32), + Bop(Bit,Var("v",FTy 33),LN 31))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Ov",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64,EX(Var("v",FTy 33),LN 31,LN 0,F32)), + Var("rd",FTy 5)]),qVar"s")))))) +; +val dfn'SUBU_def = Def + ("dfn'SUBU",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"SUBU: NotWordValue")),qVar"state")), + qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Sub, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")),LN 31, + LN 0,F32), + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32))),Var("rd",FTy 5)]),qVar"s")))) +; +val dfn'DADD_def = Def + ("dfn'DADD",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Let(Var("v",FTy 65), + Bop(Add, + Mop(SE(FTy 65), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Mop(SE(FTy 65), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + ITE(Mop(Not, + EQ(Bop(Bit,Var("v",FTy 65),LN 64), + Bop(Bit,Var("v",FTy 65),LN 63))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Ov",CTy"ExceptionType")),qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[EX(Var("v",FTy 65),LN 63,LN 0,F64),Var("rd",FTy 5)]), + qVar"state"))))) +; +val dfn'DADDU_def = Def + ("dfn'DADDU",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'DSUB_def = Def + ("dfn'DSUB",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Let(Var("v",FTy 65), + Bop(Sub, + Mop(SE(FTy 65), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Mop(SE(FTy 65), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + ITE(Mop(Not, + EQ(Bop(Bit,Var("v",FTy 65),LN 64), + Bop(Bit,Var("v",FTy 65),LN 63))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Ov",CTy"ExceptionType")),qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[EX(Var("v",FTy 65),LN 63,LN 0,F64),Var("rd",FTy 5)]), + qVar"state"))))) +; +val dfn'DSUBU_def = Def + ("dfn'DSUBU",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Sub, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'SLT_def = Def + ("dfn'SLT",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Bop(Lt, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'SLTU_def = Def + ("dfn'SLTU",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Cast F64, + Bop(Ult, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'AND_def = Def + ("dfn'AND",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(BAnd, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'OR_def = Def + ("dfn'OR",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(BOr, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'XOR_def = Def + ("dfn'XOR",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(BXor, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'NOR_def = Def + ("dfn'NOR",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(BNot, + Bop(BOr, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")), + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'MOVN_def = Def + ("dfn'MOVN",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + ITE(Mop(Not, + EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")),LW(0,64))), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'MOVZ_def = Def + ("dfn'MOVZ",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + ITE(EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'MADD_def = Def + ("dfn'MADD",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"MADD: NotWordValue")),qVar"state")), + qVar"state"), + Let(Var("v",F64), + Bop(Add, + CC[EX(Mop(Fst, + Apply + (Const("HI",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LN 31,LN 0,F32), + EX(Mop(Fst, + Apply + (Const("LO",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LN 31,LN 0,F32)], + Bop(Mul, + Mop(SE F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")),LN 31, + LN 0,F32)), + Mop(SE F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32)))), + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 31,LN 0,F32))), + Mop(Snd, + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 63,LN 32,F32))), + qVar"s"))))))) +; +val dfn'MADDU_def = Def + ("dfn'MADDU",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"MADDU: NotWordValue")),qVar"state")), + qVar"state"), + Let(Var("v",F64), + Bop(Add, + CC[EX(Mop(Fst, + Apply + (Const("HI",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LN 31,LN 0,F32), + EX(Mop(Fst, + Apply + (Const("LO",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LN 31,LN 0,F32)], + Bop(Mul, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")),LN 31, + LN 0,F32)), + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32)))), + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 31,LN 0,F32))), + Mop(Snd, + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 63,LN 32,F32))), + qVar"s"))))))) +; +val dfn'MSUB_def = Def + ("dfn'MSUB",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"MSUB: NotWordValue")),qVar"state")), + qVar"state"), + Let(Var("v",F64), + Bop(Sub, + CC[EX(Mop(Fst, + Apply + (Const("HI",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LN 31,LN 0,F32), + EX(Mop(Fst, + Apply + (Const("LO",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LN 31,LN 0,F32)], + Bop(Mul, + Mop(SE F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")),LN 31, + LN 0,F32)), + Mop(SE F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32)))), + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 31,LN 0,F32))), + Mop(Snd, + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 63,LN 32,F32))), + qVar"s"))))))) +; +val dfn'MSUBU_def = Def + ("dfn'MSUBU",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"MSUBU: NotWordValue")),qVar"state")), + qVar"state"), + Let(Var("v",F64), + Bop(Sub, + CC[EX(Mop(Fst, + Apply + (Const("HI",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LN 31,LN 0,F32), + EX(Mop(Fst, + Apply + (Const("LO",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LN 31,LN 0,F32)], + Bop(Mul, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")),LN 31, + LN 0,F32)), + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32)))), + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 31,LN 0,F32))), + Mop(Snd, + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 63,LN 32,F32))), + qVar"s"))))))) +; +val dfn'MUL_def = Def + ("dfn'MUL",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"MUL: NotWordValue")),qVar"state")), + qVar"state"), + Apply + (Call("write'hi",ATy(qTy,PTy(uTy,qTy)),LO F64), + Mop(Snd, + Apply + (Call("write'lo",ATy(qTy,PTy(uTy,qTy)),LO F64), + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Mul, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)), + qVar"s")),LN 31,LN 0, + F32), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s")),LN 31,LN 0, + F32))),Var("rd",FTy 5)]), + qVar"s")))))))) +; +val dfn'MULT_def = Def + ("dfn'MULT",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"MULT: NotWordValue")),qVar"state")), + qVar"state"), + Let(Var("v",F64), + Bop(Mul, + Mop(SE F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")),LN 31,LN 0, + F32)), + Mop(SE F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31,LN 0, + F32))), + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 63,LN 32,F32))), + Mop(Snd, + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 31,LN 0,F32))), + qVar"s"))))))) +; +val dfn'MULTU_def = Def + ("dfn'MULTU",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Or, + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"MULTU: NotWordValue")),qVar"state")), + qVar"state"), + Let(Var("v",F64), + Bop(Mul, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")),LN 31,LN 0, + F32)), + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31,LN 0, + F32))), + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 63,LN 32,F32))), + Mop(Snd, + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64,EX(Var("v",F64),LN 31,LN 0,F32))), + qVar"s"))))))) +; +val dfn'DMULT_def = Def + ("dfn'DMULT",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(Var("v",FTy 128), + Bop(Mul, + Mop(SE(FTy 128), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Mop(SE(FTy 128), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + EX(Var("v",FTy 128),LN 127,LN 64,F64)), + Mop(Snd, + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + EX(Var("v",FTy 128),LN 63,LN 0,F64)),qVar"state")))))) +; +val dfn'DMULTU_def = Def + ("dfn'DMULTU",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(Var("v",FTy 128), + Bop(Mul, + Mop(Cast(FTy 128), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))), + Mop(Cast(FTy 128), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + EX(Var("v",FTy 128),LN 127,LN 64,F64)), + Mop(Snd, + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + EX(Var("v",FTy 128),LN 63,LN 0,F64)),qVar"state")))))) +; +val dfn'DIV_def = Def + ("dfn'DIV",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Let(Var("v0",F64), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Let(qVar"s1", + ITE(Bop(Or,Call("NotWordValue",bTy,Var("v",F64)), + Call("NotWordValue",bTy,Var("v0",F64))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"DIV: NotWordValue")),qVar"state")), + qVar"state"), + ITE(EQ(Var("v0",F64),LW(0,64)), + Apply + (Call("write'hi",ATy(qTy,PTy(uTy,qTy)),LO F64), + Mop(Snd, + Apply + (Call + ("write'lo",ATy(qTy,PTy(uTy,qTy)),LO F64), + qVar"s1"))), + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64, + Bop(Rem,EX(Var("v",F64),LN 31,LN 0,F32), + EX(Var("v0",F64),LN 31,LN 0,F32)))), + Mop(Snd, + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64, + Bop(Quot, + EX(Var("v",F64),LN 31,LN 0,F32), + EX(Var("v0",F64),LN 31,LN 0,F32)))), + qVar"s1"))))))))) +; +val dfn'DIVU_def = Def + ("dfn'DIVU",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Let(Var("v0",F64), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Let(qVar"s1", + ITE(Bop(Or,Call("NotWordValue",bTy,Var("v",F64)), + Call("NotWordValue",bTy,Var("v0",F64))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"DIVU: NotWordValue")),qVar"state")), + qVar"state"), + ITE(EQ(Var("v0",F64),LW(0,64)), + Apply + (Call("write'hi",ATy(qTy,PTy(uTy,qTy)),LO F64), + Mop(Snd, + Apply + (Call + ("write'lo",ATy(qTy,PTy(uTy,qTy)),LO F64), + qVar"s1"))), + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64, + Bop(Mod,EX(Var("v",F64),LN 31,LN 0,F32), + EX(Var("v0",F64),LN 31,LN 0,F32)))), + Mop(Snd, + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Mop(SE F64, + Bop(Div, + EX(Var("v",F64),LN 31,LN 0,F32), + EX(Var("v0",F64),LN 31,LN 0,F32)))), + qVar"s1"))))))))) +; +val dfn'DDIV_def = Def + ("dfn'DDIV",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + ITE(EQ(Var("v",F64),LW(0,64)), + Apply + (Call("write'hi",ATy(qTy,PTy(uTy,qTy)),LO F64), + Mop(Snd, + Apply + (Call("write'lo",ATy(qTy,PTy(uTy,qTy)),LO F64), + qVar"state"))), + Let(Var("v0",F64), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Bop(Rem,Var("v0",F64),Var("v",F64))), + Mop(Snd, + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Bop(Quot,Var("v0",F64),Var("v",F64))), + qVar"state")))))))) +; +val dfn'DDIVU_def = Def + ("dfn'DDIVU",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + ITE(EQ(Var("v",F64),LW(0,64)), + Apply + (Call("write'hi",ATy(qTy,PTy(uTy,qTy)),LO F64), + Mop(Snd, + Apply + (Call("write'lo",ATy(qTy,PTy(uTy,qTy)),LO F64), + qVar"state"))), + Let(Var("v0",F64), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Bop(Mod,Var("v0",F64),Var("v",F64))), + Mop(Snd, + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Bop(Div,Var("v0",F64),Var("v",F64))), + qVar"state")))))))) +; +val dfn'MFHI_def = Def + ("dfn'MFHI",Var("rd",FTy 5), + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply(Const("HI",ATy(qTy,PTy(F64,qTy))),qVar"state")), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'MFLO_def = Def + ("dfn'MFLO",Var("rd",FTy 5), + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply(Const("LO",ATy(qTy,PTy(F64,qTy))),qVar"state")), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'MTHI_def = Def + ("dfn'MTHI",Var("rs",FTy 5), + Close + (qVar"state", + Apply + (Call + ("write'HI",ATy(qTy,PTy(uTy,qTy)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))),qVar"state"))) +; +val dfn'MTLO_def = Def + ("dfn'MTLO",Var("rs",FTy 5), + Close + (qVar"state", + Apply + (Call + ("write'LO",ATy(qTy,PTy(uTy,qTy)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state"))),qVar"state"))) +; +val dfn'SLL_def = Def + ("dfn'SLL",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sa",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Lsl, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")),LN 31, + LN 0,F32),Mop(Cast nTy,Var("sa",FTy 5)))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'SRL_def = Def + ("dfn'SRL",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sa",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"SRL: NotWordValue")),qVar"state")), + qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Lsr, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32),Mop(Cast nTy,Var("sa",FTy 5)))), + Var("rd",FTy 5)]),qVar"s")))) +; +val dfn'SRA_def = Def + ("dfn'SRA",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sa",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"SRA: NotWordValue")),qVar"state")), + qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Asr, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32),Mop(Cast nTy,Var("sa",FTy 5)))), + Var("rd",FTy 5)]),qVar"s")))) +; +val dfn'SLLV_def = Def + ("dfn'SLLV",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Lsl, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")),LN 31, + LN 0,F32), + Mop(Cast nTy, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")), + LN 4,LN 0,FTy 5)))),Var("rd",FTy 5)]), + qVar"state"))) +; +val dfn'SRLV_def = Def + ("dfn'SRLV",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"SRLV: NotWordValue")),qVar"state")), + qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Lsr, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32), + Mop(Cast nTy, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")), + LN 4,LN 0,FTy 5)))),Var("rd",FTy 5)]), + qVar"s")))) +; +val dfn'SRAV_def = Def + ("dfn'SRAV",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Let(qVar"s", + ITE(Call + ("NotWordValue",bTy, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception", + LS"SRAV: NotWordValue")),qVar"state")), + qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + Bop(Asr, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")),LN 31, + LN 0,F32), + Mop(Cast nTy, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"s")), + LN 4,LN 0,FTy 5)))),Var("rd",FTy 5)]), + qVar"s")))) +; +val dfn'DSLL_def = Def + ("dfn'DSLL",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sa",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lsl, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")),Mop(Cast nTy,Var("sa",FTy 5))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'DSRL_def = Def + ("dfn'DSRL",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sa",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lsr, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")),Mop(Cast nTy,Var("sa",FTy 5))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'DSRA_def = Def + ("dfn'DSRA",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sa",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Asr, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")),Mop(Cast nTy,Var("sa",FTy 5))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'DSLLV_def = Def + ("dfn'DSLLV",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lsl, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Mop(Cast nTy, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")),LN 5, + LN 0,FTy 6))),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'DSRLV_def = Def + ("dfn'DSRLV",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lsr, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Mop(Cast nTy, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")),LN 5, + LN 0,FTy 6))),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'DSRAV_def = Def + ("dfn'DSRAV",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Asr, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Mop(Cast nTy, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rs",FTy 5)),qVar"state")),LN 5, + LN 0,FTy 6))),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'DSLL32_def = Def + ("dfn'DSLL32",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sa",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lsl, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Bop(Add,Mop(Cast nTy,Var("sa",FTy 5)),LN 32)), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'DSRL32_def = Def + ("dfn'DSRL32",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sa",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Lsr, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Bop(Add,Mop(Cast nTy,Var("sa",FTy 5)),LN 32)), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'DSRA32_def = Def + ("dfn'DSRA32",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sa",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Asr, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")), + Bop(Add,Mop(Cast nTy,Var("sa",FTy 5)),LN 32)), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'TGE_def = Def + ("dfn'TGE",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITE(Bop(Ge, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TGEU_def = Def + ("dfn'TGEU",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITE(Bop(Uge, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TLT_def = Def + ("dfn'TLT",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITE(Bop(Lt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TLTU_def = Def + ("dfn'TLTU",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITE(Bop(Ult, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TEQ_def = Def + ("dfn'TEQ",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITE(EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TNE_def = Def + ("dfn'TNE",TP[Var("rs",FTy 5),Var("rt",FTy 5)], + Close + (qVar"state", + ITE(Mop(Not, + EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TGEI_def = Def + ("dfn'TGEI",TP[Var("rs",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + ITE(Bop(Ge, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(SE F64,Var("immediate",F16))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TGEIU_def = Def + ("dfn'TGEIU",TP[Var("rs",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + ITE(Bop(Uge, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(SE F64,Var("immediate",F16))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TLTI_def = Def + ("dfn'TLTI",TP[Var("rs",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + ITE(Bop(Lt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(SE F64,Var("immediate",F16))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TLTIU_def = Def + ("dfn'TLTIU",TP[Var("rs",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + ITE(Bop(Ult, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(SE F64,Var("immediate",F16))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TEQI_def = Def + ("dfn'TEQI",TP[Var("rs",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + ITE(EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(SE F64,Var("immediate",F16))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val dfn'TNEI_def = Def + ("dfn'TNEI",TP[Var("rs",FTy 5),Var("immediate",F16)], + Close + (qVar"state", + ITE(Mop(Not, + EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),Mop(SE F64,Var("immediate",F16)))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Tr",CTy"ExceptionType")),qVar"state"), + TP[LU,qVar"state"]))) +; +val loadByte_def = Def + ("loadByte", + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),bVar"unsigned"], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(TP[Var("v0",F64),qVar"s"], + Apply + (Call + ("LoadMemory",ATy(qTy,PTy(F64,qTy)), + TP[Const("BYTE",FTy 3),Const("BYTE",FTy 3), + Var("v",F64),LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),LF]),qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled",ATy(qTy,PTy(bTy,qTy))), + qVar"s"))), + Let(Var("v1",FTy 3), + Bop(BXor,EX(Var("v",F64),LN 2,LN 0,FTy 3), + REP(Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy,PTy(F1,qTy))),qVar"s")), + LN 3,FTy 3)), + Let(Var("membyte",F8), + EX(Var("v0",F64), + Bop(Add,LN 7, + Bop(Mul,LN 8, + Mop(Cast nTy,Var("v1",FTy 3)))), + Bop(Mul,LN 8,Mop(Cast nTy,Var("v1",FTy 3))), + F8), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[ITE(bVar"unsigned", + Mop(Cast F64,Var("membyte",F8)), + Mop(SE F64,Var("membyte",F8))), + Var("rt",FTy 5)]),qVar"s"))), + TP[LU,qVar"s"]))))) +; +val loadHalf_def = Def + ("loadHalf", + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),bVar"unsigned"], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + ITE(Bop(Bit,Var("v",F64),LN 0), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdEL",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state")),Var("v",F64)])), + qVar"state"))), + Let(TP[Var("v0",F64),qVar"s"], + Apply + (Call + ("LoadMemory",ATy(qTy,PTy(F64,qTy)), + TP[Const("HALFWORD",FTy 3), + Const("HALFWORD",FTy 3),Var("v",F64), + LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),LF]),qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s"))), + Let(Var("v1",FTy 3), + Bop(BXor,EX(Var("v",F64),LN 2,LN 0,FTy 3), + CC[REP(Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy,PTy(F1,qTy))), + qVar"s")),LN 2,FTy 2),LW(0,1)]), + Let(Var("memhalf",F16), + EX(Var("v0",F64), + Bop(Add,LN 15, + Bop(Mul,LN 8, + Mop(Cast nTy,Var("v1",FTy 3)))), + Bop(Mul,LN 8, + Mop(Cast nTy,Var("v1",FTy 3))),F16), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[ITE(bVar"unsigned", + Mop(Cast F64,Var("memhalf",F16)), + Mop(SE F64,Var("memhalf",F16))), + Var("rt",FTy 5)]),qVar"s"))), + TP[LU,qVar"s"])))))) +; +val loadWord_def = Def + ("loadWord", + TP[bVar"link",Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16), + bVar"unsigned"], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdEL",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state")),Var("v",F64)])), + qVar"state"))), + Let(TP[Var("v0",F64),qVar"s"], + Apply + (Call + ("LoadMemory",ATy(qTy,PTy(F64,qTy)), + TP[Const("WORD",FTy 3),Const("WORD",FTy 3), + Var("v",F64),LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),bVar"link"]), + qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s"))), + Let(Var("v1",FTy 3), + Bop(BXor,EX(Var("v",F64),LN 2,LN 0,FTy 3), + CC[Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy,PTy(F1,qTy))),qVar"s")), + LW(0,2)]), + Let(Var("memword",F32), + EX(Var("v0",F64), + Bop(Add,LN 31, + Bop(Mul,LN 8, + Mop(Cast nTy,Var("v1",FTy 3)))), + Bop(Mul,LN 8, + Mop(Cast nTy,Var("v1",FTy 3))),F32), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[ITE(bVar"unsigned", + Mop(Cast F64,Var("memword",F32)), + Mop(SE F64,Var("memword",F32))), + Var("rt",FTy 5)]),qVar"s"))), + TP[LU,qVar"s"])))))) +; +val loadDoubleword_def = Def + ("loadDoubleword", + TP[bVar"link",Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdEL",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state")),Var("v",F64)])), + qVar"state"))), + Let(TP[Var("v",F64),qVar"s"], + Apply + (Call + ("LoadMemory",ATy(qTy,PTy(F64,qTy)), + TP[Const("DOUBLEWORD",FTy 3), + Const("DOUBLEWORD",FTy 3),Var("v",F64), + LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),bVar"link"]), + qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s"))), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("v",F64),Var("rt",FTy 5)]),qVar"s"), + TP[LU,qVar"s"])))))) +; +val dfn'LB_def = Def + ("dfn'LB",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("loadByte",ATy(qTy,PTy(uTy,qTy)), + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LF]), + qVar"state"))) +; +val dfn'LBU_def = Def + ("dfn'LBU",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("loadByte",ATy(qTy,PTy(uTy,qTy)), + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LT]), + qVar"state"))) +; +val dfn'LH_def = Def + ("dfn'LH",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("loadHalf",ATy(qTy,PTy(uTy,qTy)), + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LF]), + qVar"state"))) +; +val dfn'LHU_def = Def + ("dfn'LHU",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("loadHalf",ATy(qTy,PTy(uTy,qTy)), + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LT]), + qVar"state"))) +; +val dfn'LW_def = Def + ("dfn'LW",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("loadWord",ATy(qTy,PTy(uTy,qTy)), + TP[LF,Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LF]), + qVar"state"))) +; +val dfn'LWU_def = Def + ("dfn'LWU",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("loadWord",ATy(qTy,PTy(uTy,qTy)), + TP[LF,Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LT]), + qVar"state"))) +; +val dfn'LL_def = Def + ("dfn'LL",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("loadWord",ATy(qTy,PTy(uTy,qTy)), + TP[LT,Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LF]), + qVar"state"))) +; +val dfn'LD_def = Def + ("dfn'LD",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("loadDoubleword",ATy(qTy,PTy(uTy,qTy)), + TP[LF,Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)]), + qVar"state"))) +; +val dfn'LLD_def = Def + ("dfn'LLD",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Apply + (Call + ("loadDoubleword",ATy(qTy,PTy(uTy,qTy)), + TP[LT,Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)]), + qVar"state"))) +; +val dfn'LWL_def = Def + ("dfn'LWL",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(Var("v0",FTy 2), + Bop(BXor,EX(Var("v",F64),LN 1,LN 0,FTy 2), + REP(Mop(Fst, + Apply + (Const("BigEndianCPU",ATy(qTy,PTy(F1,qTy))), + qVar"state")),LN 2,FTy 2)), + Let(TP[Var("v1",F64),qVar"s0"], + Apply + (Call + ("LoadMemory",ATy(qTy,PTy(F64,qTy)), + TP[Const("WORD",FTy 3), + CC[LW(0,1),Var("v0",FTy 2)],Var("v",F64), + LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),LF]),qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s0"))), + Let(TP[Var("v",F32),qVar"s"], + CS(TP[Bop(BXor,EX(Var("v",F64),LN 2,LN 2,F1), + Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy,PTy(F1,qTy))), + qVar"state"))),Var("v0",FTy 2)], + [(TP[LW(0,1),LW(0,2)], + TP[CC[EX(Var("v1",F64),LN 7,LN 0,F8), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 23,LN 0, + FTy 24)],qVar"s0"]), + (TP[LW(0,1),LW(1,2)], + TP[CC[EX(Var("v1",F64),LN 15,LN 0,F16), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 15,LN 0,F16)], + qVar"s0"]), + (TP[LW(0,1),LW(2,2)], + TP[CC[EX(Var("v1",F64),LN 23,LN 0,FTy 24), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 7,LN 0,F8)], + qVar"s0"]), + (TP[LW(0,1),LW(3,2)], + TP[EX(Var("v1",F64),LN 31,LN 0,F32), + qVar"s0"]), + (TP[LW(1,1),LW(0,2)], + TP[CC[EX(Var("v1",F64),LN 39,LN 32,F8), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 23,LN 0, + FTy 24)],qVar"s0"]), + (TP[LW(1,1),LW(1,2)], + TP[CC[EX(Var("v1",F64),LN 47,LN 32,F16), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 15,LN 0,F16)], + qVar"s0"]), + (TP[LW(1,1),LW(2,2)], + TP[CC[EX(Var("v1",F64),LN 55,LN 32,FTy 24), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 7,LN 0,F8)], + qVar"s0"]), + (TP[LW(1,1),LW(3,2)], + TP[EX(Var("v1",F64),LN 63,LN 32,F32), + qVar"s0"])]), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64,Var("v",F32)), + Var("rt",FTy 5)]),qVar"s")), + TP[LU,qVar"s0"])))))) +; +val dfn'LWR_def = Def + ("dfn'LWR",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(Var("v0",FTy 2), + Bop(BXor,EX(Var("v",F64),LN 1,LN 0,FTy 2), + REP(Mop(Fst, + Apply + (Const("BigEndianCPU",ATy(qTy,PTy(F1,qTy))), + qVar"state")),LN 2,FTy 2)), + Let(TP[Var("v1",F64),qVar"s0"], + Apply + (Call + ("LoadMemory",ATy(qTy,PTy(F64,qTy)), + TP[Const("WORD",FTy 3), + Bop(Sub,Const("WORD",FTy 3), + CC[LW(0,1),Var("v0",FTy 2)]),Var("v",F64), + LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),LF]),qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s0"))), + Let(TP[Var("v",F32),qVar"s"], + CS(TP[Bop(BXor,EX(Var("v",F64),LN 2,LN 2,F1), + Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy,PTy(F1,qTy))), + qVar"state"))),Var("v0",FTy 2)], + [(TP[LW(0,1),LW(0,2)], + TP[EX(Var("v1",F64),LN 31,LN 0,F32), + qVar"s0"]), + (TP[LW(0,1),LW(1,2)], + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 31,LN 24,F8), + EX(Var("v1",F64),LN 31,LN 8,FTy 24)], + qVar"s0"]), + (TP[LW(0,1),LW(2,2)], + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 31,LN 16,F16), + EX(Var("v1",F64),LN 31,LN 16,F16)], + qVar"s0"]), + (TP[LW(0,1),LW(3,2)], + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 31,LN 8, + FTy 24), + EX(Var("v1",F64),LN 31,LN 24,F8)], + qVar"s0"]), + (TP[LW(1,1),LW(0,2)], + TP[EX(Var("v1",F64),LN 63,LN 32,F32), + qVar"s0"]), + (TP[LW(1,1),LW(1,2)], + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 31,LN 24,F8), + EX(Var("v1",F64),LN 63,LN 40,FTy 24)], + qVar"s0"]), + (TP[LW(1,1),LW(2,2)], + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 31,LN 16,F16), + EX(Var("v1",F64),LN 63,LN 48,F16)], + qVar"s0"]), + (TP[LW(1,1),LW(3,2)], + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"s0")),LN 31,LN 8, + FTy 24), + EX(Var("v1",F64),LN 63,LN 56,F8)], + qVar"s0"])]), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64,Var("v",F32)), + Var("rt",FTy 5)]),qVar"s")), + TP[LU,qVar"s0"])))))) +; +val dfn'LDL_def = Def + ("dfn'LDL",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(Var("v0",FTy 3), + Bop(BXor,EX(Var("v",F64),LN 2,LN 0,FTy 3), + REP(Mop(Fst, + Apply + (Const("BigEndianCPU",ATy(qTy,PTy(F1,qTy))), + qVar"state")),LN 3,FTy 3)), + Let(TP[Var("v1",F64),qVar"s"], + Apply + (Call + ("LoadMemory",ATy(qTy,PTy(F64,qTy)), + TP[Const("DOUBLEWORD",FTy 3),Var("v0",FTy 3), + Var("v",F64),LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),LF]),qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s"))), + Let(TP[Var("v",F64),qVar"s"], + CS(Var("v0",FTy 3), + [(LW(0,3), + TP[CC[EX(Var("v1",F64),LN 7,LN 0,F8), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 55,LN 0,FTy 56)],qVar"s"]), + (LW(1,3), + TP[CC[EX(Var("v1",F64),LN 15,LN 0,F16), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 47,LN 0,FTy 48)],qVar"s"]), + (LW(2,3), + TP[CC[EX(Var("v1",F64),LN 23,LN 0,FTy 24), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 39,LN 0,FTy 40)],qVar"s"]), + (LW(3,3), + TP[CC[EX(Var("v1",F64),LN 31,LN 0,F32), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 31,LN 0,F32)],qVar"s"]), + (LW(4,3), + TP[CC[EX(Var("v1",F64),LN 39,LN 0,FTy 40), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 23,LN 0,FTy 24)],qVar"s"]), + (LW(5,3), + TP[CC[EX(Var("v1",F64),LN 47,LN 0,FTy 48), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 15,LN 0,F16)],qVar"s"]), + (LW(6,3), + TP[CC[EX(Var("v1",F64),LN 55,LN 0,FTy 56), + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 7,LN 0,F8)],qVar"s"]), + (LW(7,3), + TP[EX(Var("v1",F64),LN 63,LN 0,F64),qVar"s"])]), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("v",F64),Var("rt",FTy 5)]),qVar"s")), + TP[LU,qVar"s"])))))) +; +val dfn'LDR_def = Def + ("dfn'LDR",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(Var("v0",FTy 3), + Bop(BXor,EX(Var("v",F64),LN 2,LN 0,FTy 3), + REP(Mop(Fst, + Apply + (Const("BigEndianCPU",ATy(qTy,PTy(F1,qTy))), + qVar"state")),LN 3,FTy 3)), + Let(TP[Var("v1",F64),qVar"s"], + Apply + (Call + ("LoadMemory",ATy(qTy,PTy(F64,qTy)), + TP[Const("DOUBLEWORD",FTy 3), + Bop(Sub,Const("DOUBLEWORD",FTy 3), + Var("v0",FTy 3)),Var("v",F64), + LC("DATA",CTy"IorD"), + LC("LOAD",CTy"AccessType"),LF]),qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s"))), + Let(TP[Var("v",F64),qVar"s"], + CS(Var("v0",FTy 3), + [(LW(0,3), + TP[EX(Var("v1",F64),LN 63,LN 0,F64),qVar"s"]), + (LW(1,3), + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 63,LN 56,F8), + EX(Var("v1",F64),LN 63,LN 8,FTy 56)], + qVar"s"]), + (LW(2,3), + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 63,LN 48,F16), + EX(Var("v1",F64),LN 63,LN 16,FTy 48)], + qVar"s"]), + (LW(3,3), + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 63,LN 40,FTy 24), + EX(Var("v1",F64),LN 63,LN 24,FTy 40)], + qVar"s"]), + (LW(4,3), + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 63,LN 32,F32), + EX(Var("v1",F64),LN 63,LN 32,F32)], + qVar"s"]), + (LW(5,3), + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 63,LN 24,FTy 40), + EX(Var("v1",F64),LN 63,LN 40,FTy 24)], + qVar"s"]), + (LW(6,3), + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 63,LN 16,FTy 48), + EX(Var("v1",F64),LN 63,LN 48,F16)], + qVar"s"]), + (LW(7,3), + TP[CC[EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"s")), + LN 63,LN 8,FTy 56), + EX(Var("v1",F64),LN 63,LN 56,F8)], + qVar"s"])]), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Var("v",F64),Var("rt",FTy 5)]),qVar"s")), + TP[LU,qVar"s"])))))) +; +val dfn'SB_def = Def + ("dfn'SB",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("StoreMemory",ATy(qTy,PTy(bTy,qTy)), + TP[Const("BYTE",FTy 3),Const("BYTE",FTy 3), + Bop(Lsl, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + Bop(Mul,LN 8, + Mop(Cast nTy, + Bop(BXor, + EX(Var("v",F64),LN 2,LN 0,FTy 3), + REP(Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy,PTy(F1,qTy))), + qVar"state")),LN 3,FTy 3))))), + Var("v",F64),LC("DATA",CTy"IorD"), + LC("STORE",CTy"AccessType"),LF]),qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled",ATy(qTy,PTy(bTy,qTy))), + qVar"s"))), + Apply + (Call("write'LLbit",ATy(qTy,PTy(uTy,qTy)),LO bTy), + qVar"s"),TP[LU,qVar"s"]))))) +; +val dfn'SH_def = Def + ("dfn'SH",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + ITE(Bop(Bit,Var("v",F64),LN 0), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("AdES",CTy"ExceptionType")), + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state")),Var("v",F64)])), + qVar"state"))), + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("StoreMemory",ATy(qTy,PTy(bTy,qTy)), + TP[Const("HALFWORD",FTy 3), + Const("HALFWORD",FTy 3), + Bop(Lsl, + Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + Bop(Mul,LN 8, + Mop(Cast nTy, + Bop(BXor, + EX(Var("v",F64),LN 2,LN 0,FTy 3), + CC[REP(Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy, + PTy(F1,qTy))), + qVar"state")), + LN 2,FTy 2),LW(0,1)])))), + Var("v",F64),LC("DATA",CTy"IorD"), + LC("STORE",CTy"AccessType"),LF]),qVar"state"), + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))),qVar"s"))), + Apply + (Call("write'LLbit",ATy(qTy,PTy(uTy,qTy)),LO bTy), + qVar"s"),TP[LU,qVar"s"])))))) +; +val storeWord_def = Def + ("storeWord", + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),bVar"cond"], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(TP[bVar"r",Var("s1",PTy(bTy,qTy))], + Let(Var("s",PTy(bTy,qTy)), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Let(TP[Var("v0",CTy"CP0__renamed__"), + Var("s",PTy(bTy,qTy))], + Let(TP[Var("v",CTy"CP0__renamed__"),qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state")),qVar"state"], + TP[Var("v",CTy"CP0__renamed__"),LF,qVar"s3"]), + Let(Var("s",PTy(bTy,qTy)), + TP[Mop(Fst,Var("s",PTy(bTy,qTy))), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Var("v0", + CTy"CP0__renamed__"), + Var("v",F64)])), + Mop(Snd,Var("s",PTy(bTy,qTy)))))], + TP[Mop(Fst,Var("s",PTy(bTy,qTy))), + Mop(Snd, + Apply + (Call + ("SignalException", + ATy(qTy,PTy(uTy,qTy)), + LC("AdES",CTy"ExceptionType")), + Mop(Snd,Var("s",PTy(bTy,qTy)))))])), + Let(TP[Var("v0",F1),Var("s",PTy(bTy,qTy))], + Let(TP[Var("v",F1),qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy,PTy(F1,qTy))), + qVar"state")),qVar"state"], + TP[Var("v",F1),LF,qVar"s3"]), + Let(TP[Var("v1",F64),Var("s",PTy(bTy,qTy))], + Let(TP[Var("v",F64),qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + Mop(Snd,Var("s",PTy(bTy,qTy))))), + Mop(Snd,Var("s",PTy(bTy,qTy)))], + TP[Var("v",F64), + Mop(Fst,Var("s",PTy(bTy,qTy))), + qVar"s3"]), + Let(TP[bVar"v",Var("s",PTy(bTy,qTy))], + CS(Apply + (Call + ("StoreMemory", + ATy(qTy,PTy(bTy,qTy)), + TP[Const("WORD",FTy 3), + Const("WORD",FTy 3), + Bop(Lsl,Var("v1",F64), + Bop(Mul,LN 8, + Mop(Cast nTy, + Bop(BXor, + EX(Var("v", + F64), + LN 2, + LN 0, + FTy 3), + CC[Var("v0", + F1), + LW(0,2)])))), + Var("v",F64), + LC("DATA",CTy"IorD"), + LC("STORE",CTy"AccessType"), + bVar"cond"]), + Mop(Snd,Var("s",PTy(bTy,qTy)))), + [(TP[bVar"v",qVar"s3"], + TP[bVar"v", + Mop(Fst,Var("s",PTy(bTy,qTy))), + qVar"s3"])]), + TP[bVar"v", + Mop(Snd,Var("s",PTy(bTy,qTy)))])))), + TP[Mop(Fst,Var("s",PTy(bTy,qTy))),Var("s",PTy(bTy,qTy))]), + TP[bVar"r",Mop(Snd,Var("s1",PTy(bTy,qTy)))])))) +; +val storeDoubleword_def = Def + ("storeDoubleword", + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),bVar"cond"], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(TP[bVar"r",Var("s1",PTy(bTy,qTy))], + Let(Var("s",PTy(bTy,qTy)), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Let(TP[Var("v0",CTy"CP0__renamed__"), + Var("s",PTy(bTy,qTy))], + Let(TP[Var("v",CTy"CP0__renamed__"),qVar"s3"], + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"state")),qVar"state"], + TP[Var("v",CTy"CP0__renamed__"),LF,qVar"s3"]), + Let(Var("s",PTy(bTy,qTy)), + TP[Mop(Fst,Var("s",PTy(bTy,qTy))), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("BadVAddr", + TP[Var("v0", + CTy"CP0__renamed__"), + Var("v",F64)])), + Mop(Snd,Var("s",PTy(bTy,qTy)))))], + TP[Mop(Fst,Var("s",PTy(bTy,qTy))), + Mop(Snd, + Apply + (Call + ("SignalException", + ATy(qTy,PTy(uTy,qTy)), + LC("AdES",CTy"ExceptionType")), + Mop(Snd,Var("s",PTy(bTy,qTy)))))])), + Let(TP[Var("v0",F64),Var("s",PTy(bTy,qTy))], + Let(TP[Var("v",F64),qVar"s3"], + TP[Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + qVar"state"],TP[Var("v",F64),LF,qVar"s3"]), + Let(TP[bVar"v",Var("s",PTy(bTy,qTy))], + CS(Apply + (Call + ("StoreMemory", + ATy(qTy,PTy(bTy,qTy)), + TP[Const("DOUBLEWORD",FTy 3), + Const("DOUBLEWORD",FTy 3), + Var("v0",F64),Var("v",F64), + LC("DATA",CTy"IorD"), + LC("STORE",CTy"AccessType"), + bVar"cond"]), + Mop(Snd,Var("s",PTy(bTy,qTy)))), + [(TP[bVar"v",qVar"s3"], + TP[bVar"v", + Mop(Fst,Var("s",PTy(bTy,qTy))), + qVar"s3"])]), + TP[bVar"v",Mop(Snd,Var("s",PTy(bTy,qTy)))]))), + TP[Mop(Fst,Var("s",PTy(bTy,qTy))),Var("s",PTy(bTy,qTy))]), + TP[bVar"r",Mop(Snd,Var("s1",PTy(bTy,qTy)))])))) +; +val dfn'SW_def = Def + ("dfn'SW",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("storeWord",ATy(qTy,PTy(bTy,qTy)), + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LF]), + qVar"state"),TP[LU,qVar"s"]))) +; +val dfn'SD_def = Def + ("dfn'SD",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("storeDoubleword",ATy(qTy,PTy(bTy,qTy)), + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LF]), + qVar"state"),TP[LU,qVar"s"]))) +; +val dfn'SC_def = Def + ("dfn'SC",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("storeWord",ATy(qTy,PTy(bTy,qTy)), + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LT]), + qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[ITE(bVar"v",LW(1,64),LW(0,64)),Var("rt",FTy 5)]), + qVar"s")))) +; +val dfn'SCD_def = Def + ("dfn'SCD",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("storeDoubleword",ATy(qTy,PTy(bTy,qTy)), + TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16),LT]), + qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[ITE(bVar"v",LW(1,64),LW(0,64)),Var("rt",FTy 5)]), + qVar"s")))) +; +val dfn'SWL_def = Def + ("dfn'SWL",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(Var("v0",FTy 2), + Bop(BXor,EX(Var("v",F64),LN 1,LN 0,FTy 2), + REP(Mop(Fst, + Apply + (Const("BigEndianCPU",ATy(qTy,PTy(F1,qTy))), + qVar"state")),LN 2,FTy 2)), + Let(TP[Var("v1",F64),qVar"s0"], + CS(Var("v0",FTy 2), + [(LW(0,2), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 31,LN 24,F8)),qVar"state"]), + (LW(1,2), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 31,LN 16,F16)),qVar"state"]), + (LW(2,2), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 31,LN 8,FTy 24)),qVar"state"]), + (LW(3,2), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 31,LN 0,F32)),qVar"state"])]), + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("StoreMemory",ATy(qTy,PTy(bTy,qTy)), + TP[Const("WORD",FTy 3), + Mop(Cast(FTy 3),Var("v0",FTy 2)), + ITE(EQ(Bop(BXor, + EX(Var("v",F64),LN 2,LN 2,F1), + Mop(Fst, + Apply + (Const + ("BigEndianCPU", + ATy(qTy,PTy(F1,qTy))), + qVar"state"))),LW(1,1)), + Bop(Lsl,Var("v1",F64),LN 32), + Var("v1",F64)), + ITE(Mop(Fst, + Apply + (Const + ("BigEndianMem", + ATy(qTy,PTy(bTy,qTy))), + qVar"s0")),Var("v",F64), + Bop(BAnd,Var("v",F64), + Mop(BNot,LW(3,64)))), + LC("DATA",CTy"IorD"), + LC("STORE",CTy"AccessType"),LF]),qVar"s0"), + TP[LU,qVar"s"])))))) +; +val dfn'SWR_def = Def + ("dfn'SWR",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(Var("v0",FTy 2), + Bop(BXor,EX(Var("v",F64),LN 1,LN 0,FTy 2), + REP(Mop(Fst, + Apply + (Const("BigEndianCPU",ATy(qTy,PTy(F1,qTy))), + qVar"state")),LN 2,FTy 2)), + Let(TP[Var("v1",F64),qVar"s"], + CS(TP[Bop(BXor,EX(Var("v",F64),LN 2,LN 2,F1), + Mop(Fst, + Apply + (Const + ("BigEndianCPU",ATy(qTy,PTy(F1,qTy))), + qVar"state"))),Var("v0",FTy 2)], + [(TP[LW(0,1),LW(0,2)], + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 31,LN 0,F32)),qVar"state"]), + (TP[LW(0,1),LW(1,2)], + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 23,LN 0, + FTy 24)),LN 8),qVar"state"]), + (TP[LW(0,1),LW(2,2)], + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 15,LN 0,F16)), + LN 16),qVar"state"]), + (TP[LW(0,1),LW(3,2)], + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 7,LN 0,F8)), + LN 24),qVar"state"]), + (TP[LW(1,1),LW(0,2)], + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 31,LN 0,F32)), + LN 32),qVar"state"]), + (TP[LW(1,1),LW(1,2)], + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 23,LN 0, + FTy 24)),LN 40),qVar"state"]), + (TP[LW(1,1),LW(2,2)], + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 15,LN 0,F16)), + LN 48),qVar"state"]), + (TP[LW(1,1),LW(3,2)], + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 7,LN 0,F8)), + LN 56),qVar"state"])]), + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("StoreMemory",ATy(qTy,PTy(bTy,qTy)), + TP[Const("WORD",FTy 3), + Bop(Sub,Const("WORD",FTy 3), + Mop(Cast(FTy 3),Var("v0",FTy 2))), + Var("v1",F64), + ITE(Mop(Fst, + Apply + (Const + ("BigEndianMem", + ATy(qTy,PTy(bTy,qTy))), + qVar"s")), + Bop(BAnd,Var("v",F64), + Mop(BNot,LW(3,64))),Var("v",F64)), + LC("DATA",CTy"IorD"), + LC("STORE",CTy"AccessType"),LF]),qVar"s"), + TP[LU,qVar"s"])))))) +; +val dfn'SDL_def = Def + ("dfn'SDL",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(Var("v0",FTy 3), + Bop(BXor,EX(Var("v",F64),LN 2,LN 0,FTy 3), + REP(Mop(Fst, + Apply + (Const("BigEndianCPU",ATy(qTy,PTy(F1,qTy))), + qVar"state")),LN 3,FTy 3)), + Let(TP[Var("v1",F64),qVar"s"], + CS(Var("v0",FTy 3), + [(LW(0,3), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 63,LN 56,F8)),qVar"state"]), + (LW(1,3), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 63,LN 48,F16)),qVar"state"]), + (LW(2,3), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 63,LN 40,FTy 24)),qVar"state"]), + (LW(3,3), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 63,LN 32,F32)),qVar"state"]), + (LW(4,3), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 63,LN 24,FTy 40)),qVar"state"]), + (LW(5,3), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 63,LN 16,FTy 48)),qVar"state"]), + (LW(6,3), + TP[Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + LN 63,LN 8,FTy 56)),qVar"state"]), + (LW(7,3), + TP[Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + qVar"state"])]), + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("StoreMemory",ATy(qTy,PTy(bTy,qTy)), + TP[Const("DOUBLEWORD",FTy 3),Var("v0",FTy 3), + Var("v1",F64), + ITE(Mop(Fst, + Apply + (Const + ("BigEndianMem", + ATy(qTy,PTy(bTy,qTy))), + qVar"s")),Var("v",F64), + Bop(BAnd,Var("v",F64), + Mop(BNot,LW(7,64)))), + LC("DATA",CTy"IorD"), + LC("STORE",CTy"AccessType"),LF]),qVar"s"), + TP[LU,qVar"s"])))))) +; +val dfn'SDR_def = Def + ("dfn'SDR",TP[Var("base",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Mop(SE F64,Var("offset",F16)), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("base",FTy 5)), + qVar"state"))), + Let(Var("v0",FTy 3), + Bop(BXor,EX(Var("v",F64),LN 2,LN 0,FTy 3), + REP(Mop(Fst, + Apply + (Const("BigEndianCPU",ATy(qTy,PTy(F1,qTy))), + qVar"state")),LN 3,FTy 3)), + Let(TP[Var("v1",F64),qVar"s"], + CS(Var("v0",FTy 3), + [(LW(0,3), + TP[Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)),qVar"state")), + qVar"state"]), + (LW(1,3), + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 55,LN 0, + FTy 56)),LN 8),qVar"state"]), + (LW(2,3), + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 47,LN 0, + FTy 48)),LN 16),qVar"state"]), + (LW(3,3), + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 39,LN 0, + FTy 40)),LN 24),qVar"state"]), + (LW(4,3), + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 31,LN 0,F32)), + LN 32),qVar"state"]), + (LW(5,3), + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 23,LN 0, + FTy 24)),LN 40),qVar"state"]), + (LW(6,3), + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 15,LN 0,F16)), + LN 48),qVar"state"]), + (LW(7,3), + TP[Bop(Lsl, + Mop(Cast F64, + EX(Mop(Fst, + Apply + (Call + ("GPR", + ATy(qTy,PTy(F64,qTy)), + Var("rt",FTy 5)), + qVar"state")),LN 7,LN 0,F8)), + LN 56),qVar"state"])]), + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("StoreMemory",ATy(qTy,PTy(bTy,qTy)), + TP[Const("DOUBLEWORD",FTy 3), + Bop(Sub,Const("DOUBLEWORD",FTy 3), + Var("v0",FTy 3)),Var("v1",F64), + ITE(Mop(Fst, + Apply + (Const + ("BigEndianMem", + ATy(qTy,PTy(bTy,qTy))), + qVar"s")), + Bop(BAnd,Var("v",F64), + Mop(BNot,LW(7,64))),Var("v",F64)), + LC("DATA",CTy"IorD"), + LC("STORE",CTy"AccessType"),LF]),qVar"s"), + TP[LU,qVar"s"])))))) +; +val dfn'SYNC_def = Def ("dfn'SYNC",Var("stype",FTy 5),LU) +; +val dfn'BREAK_def = Def + ("dfn'BREAK",qVar"state", + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Bp",CTy"ExceptionType")),qVar"state")) +; +val dfn'SYSCALL_def = Def + ("dfn'SYSCALL",qVar"state", + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("Sys",CTy"ExceptionType")),qVar"state")) +; +val dfn'MTC0_def = Def + ("dfn'MTC0",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)], + Close + (qVar"state", + ITE(Bop(Or, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))),qVar"state"))), + Apply + (Call + ("write'CPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")),LN 0,Var("rd",FTy 5), + Var("sel",FTy 3)]),qVar"state"), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state")))) +; +val dfn'DMTC0_def = Def + ("dfn'DMTC0",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)], + Close + (qVar"state", + ITE(Bop(Or, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))),qVar"state"))), + Apply + (Call + ("write'CPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")),LN 0,Var("rd",FTy 5), + Var("sel",FTy 3)]),qVar"state"), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state")))) +; +val dfn'MFC0_def = Def + ("dfn'MFC0",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)], + Close + (qVar"state", + ITE(Bop(Or, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))),qVar"state"))), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(SE F64, + EX(Mop(Fst, + Apply + (Call + ("CPR",ATy(qTy,PTy(F64,qTy)), + TP[LN 0,Var("rd",FTy 5), + Var("sel",FTy 3)]),qVar"state")), + LN 31,LN 0,F32)),Var("rt",FTy 5)]),qVar"state"), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state")))) +; +val dfn'DMFC0_def = Def + ("dfn'DMFC0",TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)], + Close + (qVar"state", + ITE(Bop(Or, + Dest + ("CU0",bTy, + Dest + ("Status",CTy"StatusRegister", + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")))), + Mop(Fst, + Apply + (Const("KernelMode",ATy(qTy,PTy(bTy,qTy))),qVar"state"))), + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Mop(Fst, + Apply + (Call + ("CPR",ATy(qTy,PTy(F64,qTy)), + TP[LN 0,Var("rd",FTy 5),Var("sel",FTy 3)]), + qVar"state")),Var("rt",FTy 5)]),qVar"state"), + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("CpU",CTy"ExceptionType")),qVar"state")))) +; +val dfn'J_def = Def + ("dfn'J",Var("instr_index",FTy 26), + Close + (qVar"state", + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + CC[EX(Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))),qVar"state")), + LN 63,LN 28,FTy 36),Var("instr_index",FTy 26), + LW(0,2)])),qVar"state"))) +; +val dfn'JAL_def = Def + ("dfn'JAL",Var("instr_index",FTy 26), + Close + (qVar"state", + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(8,64)),LW(31,5)]), + qVar"state")), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + CC[EX(Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LN 63,LN 28,FTy 36),Var("instr_index",FTy 26), + LW(0,2)])),qVar"s")))) +; +val dfn'JR_def = Def + ("dfn'JR",Var("rs",FTy 5), + Close + (qVar"state", + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")))),qVar"state"))) +; +val dfn'BEQ_def = Def + ("dfn'BEQ",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) +; +val dfn'BNE_def = Def + ("dfn'BNE",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Mop(Not, + EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) +; +val dfn'BLEZ_def = Def + ("dfn'BLEZ",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Bop(Le, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) +; +val dfn'BGTZ_def = Def + ("dfn'BGTZ",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Bop(Gt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) +; +val dfn'BLTZ_def = Def + ("dfn'BLTZ",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Bop(Lt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) +; +val dfn'BGEZ_def = Def + ("dfn'BGEZ",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Bop(Ge, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"state")))) +; +val dfn'BLTZAL_def = Def + ("dfn'BLTZAL",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(8,64)),LW(31,5)]), + qVar"state")), + ITE(Bop(Lt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"s"), + Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"s"))))) +; +val dfn'BGEZAL_def = Def + ("dfn'BGEZAL",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(8,64)),LW(31,5)]), + qVar"state")), + ITE(Bop(Ge, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"s"), + Apply(Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))),qVar"s"))))) +; +val dfn'BEQL_def = Def + ("dfn'BEQL",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state"))), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LW(4,64))),qVar"s"))))) +; +val dfn'BNEL_def = Def + ("dfn'BNEL",TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Mop(Not, + EQ(Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")), + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rt",FTy 5)), + qVar"state")))), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LW(4,64))),qVar"s"))))) +; +val dfn'BLEZL_def = Def + ("dfn'BLEZL",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Bop(Le, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LW(4,64))),qVar"s"))))) +; +val dfn'BGTZL_def = Def + ("dfn'BGTZL",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Bop(Gt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LW(4,64))),qVar"s"))))) +; +val dfn'BLTZL_def = Def + ("dfn'BLTZL",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Bop(Lt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LW(4,64))),qVar"s"))))) +; +val dfn'BGEZL_def = Def + ("dfn'BGEZL",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + ITE(Bop(Ge, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"state"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))),qVar"s")), + LW(4,64))),qVar"s"))))) +; +val dfn'BLTZALL_def = Def + ("dfn'BLTZALL",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(8,64)),LW(31,5)]), + qVar"state")), + ITE(Bop(Lt, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"s"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"s")), + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")),LW(4,64))),qVar"s")))))) +; +val dfn'BGEZALL_def = Def + ("dfn'BGEZALL",TP[Var("rs",FTy 5),Var("offset",F16)], + Close + (qVar"state", + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'GPR",ATy(qTy,PTy(uTy,qTy)), + TP[Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"state")),LW(8,64)),LW(31,5)]), + qVar"state")), + ITE(Bop(Ge, + Mop(Fst, + Apply + (Call("GPR",ATy(qTy,PTy(F64,qTy)),Var("rs",FTy 5)), + qVar"state")),LW(0,64)), + Apply + (Call + ("write'BranchTo",ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Bop(Add, + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")),LW(4,64)), + Bop(Lsl,Mop(SE F64,Var("offset",F16)),LN 2)))), + qVar"s"), + Let(qVar"s", + Mop(Snd, + Apply + (Const("CheckBranch",ATy(qTy,PTy(uTy,qTy))), + qVar"s")), + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const("PC",ATy(qTy,PTy(F64,qTy))), + qVar"s")),LW(4,64))),qVar"s")))))) +; +val dfn'WAIT_def = Def0 ("dfn'WAIT",LU) +; +val dfn'ReservedInstruction_def = Def + ("dfn'ReservedInstruction",qVar"state", + Apply + (Call + ("SignalException",ATy(qTy,PTy(uTy,qTy)), + LC("ResI",CTy"ExceptionType")),qVar"state")) +; +val dfn'Unpredictable_def = Def + ("dfn'Unpredictable",qVar"state", + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE",CTy"exception",LS"Unpredictable instruction")), + qVar"state")) +; +val Run_def = Def + ("Run",Var("v0",CTy"instruction"), + Close + (qVar"state", + CS(Var("v0",CTy"instruction"), + [(Const("BREAK",CTy"instruction"), + Apply(Const("dfn'BREAK",ATy(qTy,PTy(uTy,qTy))),qVar"state")), + (Const("ERET",CTy"instruction"), + Apply(Const("dfn'ERET",ATy(qTy,PTy(uTy,qTy))),qVar"state")), + (Const("ReservedInstruction",CTy"instruction"), + Apply + (Const("dfn'ReservedInstruction",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Const("SYSCALL",CTy"instruction"), + Apply(Const("dfn'SYSCALL",ATy(qTy,PTy(uTy,qTy))),qVar"state")), + (Const("TLBP",CTy"instruction"), + Apply(Const("dfn'TLBP",ATy(qTy,PTy(uTy,qTy))),qVar"state")), + (Const("TLBR",CTy"instruction"), + Apply(Const("dfn'TLBR",ATy(qTy,PTy(uTy,qTy))),qVar"state")), + (Const("TLBWI",CTy"instruction"), + Apply(Const("dfn'TLBWI",ATy(qTy,PTy(uTy,qTy))),qVar"state")), + (Const("TLBWR",CTy"instruction"), + Apply(Const("dfn'TLBWR",ATy(qTy,PTy(uTy,qTy))),qVar"state")), + (Const("Unpredictable",CTy"instruction"), + Apply + (Const("dfn'Unpredictable",ATy(qTy,PTy(uTy,qTy))),qVar"state")), + (Const("WAIT",CTy"instruction"), + TP[Const("dfn'WAIT",uTy),qVar"state"]), + (Call + ("CACHE",CTy"instruction", + Var("v173",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'CACHE",ATy(qTy,PTy(uTy,qTy)), + Var("v173",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("RDHWR",CTy"instruction",Var("v174",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'RDHWR",ATy(qTy,PTy(uTy,qTy)), + Var("v174",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("SYNC",CTy"instruction",Var("v175",FTy 5)), + TP[Call("dfn'SYNC",uTy,Var("v175",FTy 5)),qVar"state"]), + (Call("ArithI",CTy"instruction",Var("v1",CTy"ArithI")), + CS(Var("v1",CTy"ArithI"), + [(Call + ("ADDI",CTy"ArithI",Var("v2",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'ADDI",ATy(qTy,PTy(uTy,qTy)), + Var("v2",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("ADDIU",CTy"ArithI",Var("v3",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'ADDIU",ATy(qTy,PTy(uTy,qTy)), + Var("v3",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("ANDI",CTy"ArithI",Var("v4",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'ANDI",ATy(qTy,PTy(uTy,qTy)), + Var("v4",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("DADDI",CTy"ArithI",Var("v5",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'DADDI",ATy(qTy,PTy(uTy,qTy)), + Var("v5",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("DADDIU",CTy"ArithI", + Var("v6",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'DADDIU",ATy(qTy,PTy(uTy,qTy)), + Var("v6",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("LUI",CTy"ArithI",Var("v7",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'LUI",ATy(qTy,PTy(uTy,qTy)), + Var("v7",PTy(FTy 5,F16))),qVar"state")), + (Call + ("ORI",CTy"ArithI",Var("v8",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'ORI",ATy(qTy,PTy(uTy,qTy)), + Var("v8",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SLTI",CTy"ArithI",Var("v9",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SLTI",ATy(qTy,PTy(uTy,qTy)), + Var("v9",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SLTIU",CTy"ArithI", + Var("v10",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SLTIU",ATy(qTy,PTy(uTy,qTy)), + Var("v10",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("XORI",CTy"ArithI",Var("v11",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'XORI",ATy(qTy,PTy(uTy,qTy)), + Var("v11",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state"))])), + (Call("ArithR",CTy"instruction",Var("v12",CTy"ArithR")), + CS(Var("v12",CTy"ArithR"), + [(Call + ("ADD",CTy"ArithR", + Var("v13",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'ADD",ATy(qTy,PTy(uTy,qTy)), + Var("v13",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("ADDU",CTy"ArithR", + Var("v14",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'ADDU",ATy(qTy,PTy(uTy,qTy)), + Var("v14",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("AND",CTy"ArithR", + Var("v15",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'AND",ATy(qTy,PTy(uTy,qTy)), + Var("v15",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DADD",CTy"ArithR", + Var("v16",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DADD",ATy(qTy,PTy(uTy,qTy)), + Var("v16",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DADDU",CTy"ArithR", + Var("v17",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DADDU",ATy(qTy,PTy(uTy,qTy)), + Var("v17",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSUB",CTy"ArithR", + Var("v18",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSUB",ATy(qTy,PTy(uTy,qTy)), + Var("v18",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSUBU",CTy"ArithR", + Var("v19",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSUBU",ATy(qTy,PTy(uTy,qTy)), + Var("v19",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("MOVN",CTy"ArithR", + Var("v20",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'MOVN",ATy(qTy,PTy(uTy,qTy)), + Var("v20",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("MOVZ",CTy"ArithR", + Var("v21",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'MOVZ",ATy(qTy,PTy(uTy,qTy)), + Var("v21",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("NOR",CTy"ArithR", + Var("v22",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'NOR",ATy(qTy,PTy(uTy,qTy)), + Var("v22",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("OR",CTy"ArithR",Var("v23",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'OR",ATy(qTy,PTy(uTy,qTy)), + Var("v23",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SLT",CTy"ArithR", + Var("v24",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SLT",ATy(qTy,PTy(uTy,qTy)), + Var("v24",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SLTU",CTy"ArithR", + Var("v25",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SLTU",ATy(qTy,PTy(uTy,qTy)), + Var("v25",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SUB",CTy"ArithR", + Var("v26",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SUB",ATy(qTy,PTy(uTy,qTy)), + Var("v26",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SUBU",CTy"ArithR", + Var("v27",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SUBU",ATy(qTy,PTy(uTy,qTy)), + Var("v27",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("XOR",CTy"ArithR", + Var("v28",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'XOR",ATy(qTy,PTy(uTy,qTy)), + Var("v28",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state"))])), + (Call("Branch",CTy"instruction",Var("v29",CTy"Branch")), + CS(Var("v29",CTy"Branch"), + [(Call + ("BEQ",CTy"Branch",Var("v30",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'BEQ",ATy(qTy,PTy(uTy,qTy)), + Var("v30",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("BEQL",CTy"Branch",Var("v31",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'BEQL",ATy(qTy,PTy(uTy,qTy)), + Var("v31",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("BGEZ",CTy"Branch",Var("v32",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BGEZ",ATy(qTy,PTy(uTy,qTy)), + Var("v32",PTy(FTy 5,F16))),qVar"state")), + (Call("BGEZAL",CTy"Branch",Var("v33",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BGEZAL",ATy(qTy,PTy(uTy,qTy)), + Var("v33",PTy(FTy 5,F16))),qVar"state")), + (Call("BGEZALL",CTy"Branch",Var("v34",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BGEZALL",ATy(qTy,PTy(uTy,qTy)), + Var("v34",PTy(FTy 5,F16))),qVar"state")), + (Call("BGEZL",CTy"Branch",Var("v35",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BGEZL",ATy(qTy,PTy(uTy,qTy)), + Var("v35",PTy(FTy 5,F16))),qVar"state")), + (Call("BGTZ",CTy"Branch",Var("v36",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BGTZ",ATy(qTy,PTy(uTy,qTy)), + Var("v36",PTy(FTy 5,F16))),qVar"state")), + (Call("BGTZL",CTy"Branch",Var("v37",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BGTZL",ATy(qTy,PTy(uTy,qTy)), + Var("v37",PTy(FTy 5,F16))),qVar"state")), + (Call("BLEZ",CTy"Branch",Var("v38",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BLEZ",ATy(qTy,PTy(uTy,qTy)), + Var("v38",PTy(FTy 5,F16))),qVar"state")), + (Call("BLEZL",CTy"Branch",Var("v39",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BLEZL",ATy(qTy,PTy(uTy,qTy)), + Var("v39",PTy(FTy 5,F16))),qVar"state")), + (Call("BLTZ",CTy"Branch",Var("v40",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BLTZ",ATy(qTy,PTy(uTy,qTy)), + Var("v40",PTy(FTy 5,F16))),qVar"state")), + (Call("BLTZAL",CTy"Branch",Var("v41",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BLTZAL",ATy(qTy,PTy(uTy,qTy)), + Var("v41",PTy(FTy 5,F16))),qVar"state")), + (Call("BLTZALL",CTy"Branch",Var("v42",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BLTZALL",ATy(qTy,PTy(uTy,qTy)), + Var("v42",PTy(FTy 5,F16))),qVar"state")), + (Call("BLTZL",CTy"Branch",Var("v43",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'BLTZL",ATy(qTy,PTy(uTy,qTy)), + Var("v43",PTy(FTy 5,F16))),qVar"state")), + (Call + ("BNE",CTy"Branch",Var("v44",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'BNE",ATy(qTy,PTy(uTy,qTy)), + Var("v44",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("BNEL",CTy"Branch",Var("v45",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'BNEL",ATy(qTy,PTy(uTy,qTy)), + Var("v45",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("J",CTy"Branch",Var("v46",FTy 26)), + Apply + (Call("dfn'J",ATy(qTy,PTy(uTy,qTy)),Var("v46",FTy 26)), + qVar"state")), + (Call("JAL",CTy"Branch",Var("v47",FTy 26)), + Apply + (Call("dfn'JAL",ATy(qTy,PTy(uTy,qTy)),Var("v47",FTy 26)), + qVar"state")), + (Call("JALR",CTy"Branch",Var("v48",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'JALR",ATy(qTy,PTy(uTy,qTy)), + Var("v48",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("JR",CTy"Branch",Var("v49",FTy 5)), + Apply + (Call("dfn'JR",ATy(qTy,PTy(uTy,qTy)),Var("v49",FTy 5)), + qVar"state"))])), + (Call("COP2",CTy"instruction",Var("v50",CTy"COP2")), + CS(Var("v50",CTy"COP2"), + [(Call("CHERICOP2",CTy"COP2",Var("v51",CTy"CHERICOP2")), + CS(Var("v51",CTy"CHERICOP2"), + [(Const("CReturn",CTy"CHERICOP2"), + Apply + (Const("dfn'CReturn",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Const("DumpCapReg",CTy"CHERICOP2"), + Apply + (Const("dfn'DumpCapReg",ATy(qTy,PTy(uTy,qTy))), + qVar"state")), + (Const("UnknownCapInstruction",CTy"CHERICOP2"), + Apply + (Const + ("dfn'UnknownCapInstruction", + ATy(qTy,PTy(uTy,qTy))),qVar"state")), + (Call("CBTS",CTy"CHERICOP2",Var("v74",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'CBTS",ATy(qTy,PTy(uTy,qTy)), + Var("v74",PTy(FTy 5,F16))),qVar"state")), + (Call("CBTU",CTy"CHERICOP2",Var("v75",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'CBTU",ATy(qTy,PTy(uTy,qTy)), + Var("v75",PTy(FTy 5,F16))),qVar"state")), + (Call + ("CCall",CTy"CHERICOP2",Var("v76",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CCall",ATy(qTy,PTy(uTy,qTy)), + Var("v76",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("CJALR",CTy"CHERICOP2",Var("v77",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CJALR",ATy(qTy,PTy(uTy,qTy)), + Var("v77",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("CJR",CTy"CHERICOP2",Var("v78",FTy 5)), + Apply + (Call + ("dfn'CJR",ATy(qTy,PTy(uTy,qTy)), + Var("v78",FTy 5)),qVar"state")), + (Call + ("CPtrCmp",CTy"CHERICOP2", + Var("v79",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + Apply + (Call + ("dfn'CPtrCmp",ATy(qTy,PTy(uTy,qTy)), + Var("v79", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + qVar"state")), + (Call + ("CSeal",CTy"CHERICOP2", + Var("v80",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'CSeal",ATy(qTy,PTy(uTy,qTy)), + Var("v80",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + qVar"state")), + (Call + ("CUnseal",CTy"CHERICOP2", + Var("v81",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'CUnseal",ATy(qTy,PTy(uTy,qTy)), + Var("v81",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + qVar"state")), + (Call("CCheck",CTy"CHERICOP2",Var("v52",CTy"CCheck")), + CS(Var("v52",CTy"CCheck"), + [(Call + ("CCheckPerm",CTy"CCheck", + Var("v53",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CCheckPerm",ATy(qTy,PTy(uTy,qTy)), + Var("v53",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("CCheckType",CTy"CCheck", + Var("v54",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CCheckType",ATy(qTy,PTy(uTy,qTy)), + Var("v54",PTy(FTy 5,FTy 5))),qVar"state"))])), + (Call("CGet",CTy"CHERICOP2",Var("v55",CTy"CGet")), + CS(Var("v55",CTy"CGet"), + [(Call + ("CGetBase",CTy"CGet", + Var("v56",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CGetBase",ATy(qTy,PTy(uTy,qTy)), + Var("v56",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("CGetCause",CTy"CGet",Var("v57",FTy 5)), + Apply + (Call + ("dfn'CGetCause",ATy(qTy,PTy(uTy,qTy)), + Var("v57",FTy 5)),qVar"state")), + (Call + ("CGetLen",CTy"CGet", + Var("v58",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CGetLen",ATy(qTy,PTy(uTy,qTy)), + Var("v58",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("CGetOffset",CTy"CGet", + Var("v59",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CGetOffset",ATy(qTy,PTy(uTy,qTy)), + Var("v59",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("CGetPCC",CTy"CGet",Var("v60",FTy 5)), + Apply + (Call + ("dfn'CGetPCC",ATy(qTy,PTy(uTy,qTy)), + Var("v60",FTy 5)),qVar"state")), + (Call + ("CGetPerm",CTy"CGet", + Var("v61",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CGetPerm",ATy(qTy,PTy(uTy,qTy)), + Var("v61",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("CGetSealed",CTy"CGet", + Var("v62",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CGetSealed",ATy(qTy,PTy(uTy,qTy)), + Var("v62",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("CGetTag",CTy"CGet", + Var("v63",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CGetTag",ATy(qTy,PTy(uTy,qTy)), + Var("v63",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("CGetType",CTy"CGet", + Var("v64",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CGetType",ATy(qTy,PTy(uTy,qTy)), + Var("v64",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("CToPtr",CTy"CGet", + Var("v65",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'CToPtr",ATy(qTy,PTy(uTy,qTy)), + Var("v65",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + qVar"state"))])), + (Call("CSet",CTy"CHERICOP2",Var("v66",CTy"CSet")), + CS(Var("v66",CTy"CSet"), + [(Call + ("CAndPerm",CTy"CSet", + Var("v67",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'CAndPerm",ATy(qTy,PTy(uTy,qTy)), + Var("v67",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + qVar"state")), + (Call + ("CClearTag",CTy"CSet", + Var("v68",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'CClearTag",ATy(qTy,PTy(uTy,qTy)), + Var("v68",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("CFromPtr",CTy"CSet", + Var("v69",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'CFromPtr",ATy(qTy,PTy(uTy,qTy)), + Var("v69",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + qVar"state")), + (Call + ("CIncBase",CTy"CSet", + Var("v70",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'CIncBase",ATy(qTy,PTy(uTy,qTy)), + Var("v70",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + qVar"state")), + (Call("CSetCause",CTy"CSet",Var("v71",FTy 5)), + Apply + (Call + ("dfn'CSetCause",ATy(qTy,PTy(uTy,qTy)), + Var("v71",FTy 5)),qVar"state")), + (Call + ("CSetLen",CTy"CSet", + Var("v72",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'CSetLen",ATy(qTy,PTy(uTy,qTy)), + Var("v72",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + qVar"state")), + (Call + ("CSetOffset",CTy"CSet", + Var("v73",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'CSetOffset",ATy(qTy,PTy(uTy,qTy)), + Var("v73",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + qVar"state"))]))]))])), + (Call("CP",CTy"instruction",Var("v82",CTy"CP")), + CS(Var("v82",CTy"CP"), + [(Call + ("DMFC0",CTy"CP",Var("v83",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'DMFC0",ATy(qTy,PTy(uTy,qTy)), + Var("v83",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("DMTC0",CTy"CP",Var("v84",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'DMTC0",ATy(qTy,PTy(uTy,qTy)), + Var("v84",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("MFC0",CTy"CP",Var("v85",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'MFC0",ATy(qTy,PTy(uTy,qTy)), + Var("v85",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("MTC0",CTy"CP",Var("v86",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'MTC0",ATy(qTy,PTy(uTy,qTy)), + Var("v86",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state"))])), + (Call("LDC2",CTy"instruction",Var("v87",CTy"LDC2")), + CS(Var("v87",CTy"LDC2"), + [(Call("CHERILDC2",CTy"LDC2",Var("v88",CTy"CHERILDC2")), + CS(Var("v88",CTy"CHERILDC2"), + [(Call + ("CLC",CTy"CHERILDC2", + Var("v89",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 11))))), + Apply + (Call + ("dfn'CLC",ATy(qTy,PTy(uTy,qTy)), + Var("v89", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 11))))), + qVar"state"))]))])), + (Call("LWC2",CTy"instruction",Var("v90",CTy"LWC2")), + CS(Var("v90",CTy"LWC2"), + [(Call("CHERILWC2",CTy"LWC2",Var("v91",CTy"CHERILWC2")), + CS(Var("v91",CTy"CHERILWC2"), + [(Call + ("CLLD",CTy"CHERILWC2", + Var("v92",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,F8))))), + Apply + (Call + ("dfn'CLLD",ATy(qTy,PTy(uTy,qTy)), + Var("v92",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,F8))))), + qVar"state")), + (Call + ("CLoad",CTy"CHERILWC2", + Var("v93", + PTy(FTy 5, + PTy(FTy 5,PTy(FTy 5,PTy(F8,PTy(F1,FTy 2))))))), + Apply + (Call + ("dfn'CLoad",ATy(qTy,PTy(uTy,qTy)), + Var("v93", + PTy(FTy 5, + PTy(FTy 5, + PTy(FTy 5,PTy(F8,PTy(F1,FTy 2))))))), + qVar"state"))]))])), + (Call("Load",CTy"instruction",Var("v94",CTy"Load")), + CS(Var("v94",CTy"Load"), + [(Call("LB",CTy"Load",Var("v95",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LB",ATy(qTy,PTy(uTy,qTy)), + Var("v95",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("LBU",CTy"Load",Var("v96",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LBU",ATy(qTy,PTy(uTy,qTy)), + Var("v96",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("LD",CTy"Load",Var("v97",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LD",ATy(qTy,PTy(uTy,qTy)), + Var("v97",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("LDL",CTy"Load",Var("v98",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LDL",ATy(qTy,PTy(uTy,qTy)), + Var("v98",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("LDR",CTy"Load",Var("v99",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LDR",ATy(qTy,PTy(uTy,qTy)), + Var("v99",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("LH",CTy"Load",Var("v100",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LH",ATy(qTy,PTy(uTy,qTy)), + Var("v100",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("LHU",CTy"Load",Var("v101",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LHU",ATy(qTy,PTy(uTy,qTy)), + Var("v101",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("LL",CTy"Load",Var("v102",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LL",ATy(qTy,PTy(uTy,qTy)), + Var("v102",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("LLD",CTy"Load",Var("v103",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LLD",ATy(qTy,PTy(uTy,qTy)), + Var("v103",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call("LW",CTy"Load",Var("v104",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LW",ATy(qTy,PTy(uTy,qTy)), + Var("v104",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("LWL",CTy"Load",Var("v105",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LWL",ATy(qTy,PTy(uTy,qTy)), + Var("v105",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("LWR",CTy"Load",Var("v106",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LWR",ATy(qTy,PTy(uTy,qTy)), + Var("v106",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("LWU",CTy"Load",Var("v107",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'LWU",ATy(qTy,PTy(uTy,qTy)), + Var("v107",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state"))])), + (Call("MultDiv",CTy"instruction",Var("v108",CTy"MultDiv")), + CS(Var("v108",CTy"MultDiv"), + [(Call("DDIV",CTy"MultDiv",Var("v109",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'DDIV",ATy(qTy,PTy(uTy,qTy)), + Var("v109",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("DDIVU",CTy"MultDiv",Var("v110",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'DDIVU",ATy(qTy,PTy(uTy,qTy)), + Var("v110",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("DIV",CTy"MultDiv",Var("v111",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'DIV",ATy(qTy,PTy(uTy,qTy)), + Var("v111",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("DIVU",CTy"MultDiv",Var("v112",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'DIVU",ATy(qTy,PTy(uTy,qTy)), + Var("v112",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("DMULT",CTy"MultDiv",Var("v113",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'DMULT",ATy(qTy,PTy(uTy,qTy)), + Var("v113",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("DMULTU",CTy"MultDiv",Var("v114",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'DMULTU",ATy(qTy,PTy(uTy,qTy)), + Var("v114",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("MADD",CTy"MultDiv",Var("v115",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'MADD",ATy(qTy,PTy(uTy,qTy)), + Var("v115",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("MADDU",CTy"MultDiv",Var("v116",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'MADDU",ATy(qTy,PTy(uTy,qTy)), + Var("v116",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("MFHI",CTy"MultDiv",Var("v117",FTy 5)), + Apply + (Call + ("dfn'MFHI",ATy(qTy,PTy(uTy,qTy)),Var("v117",FTy 5)), + qVar"state")), + (Call("MFLO",CTy"MultDiv",Var("v118",FTy 5)), + Apply + (Call + ("dfn'MFLO",ATy(qTy,PTy(uTy,qTy)),Var("v118",FTy 5)), + qVar"state")), + (Call("MSUB",CTy"MultDiv",Var("v119",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'MSUB",ATy(qTy,PTy(uTy,qTy)), + Var("v119",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("MSUBU",CTy"MultDiv",Var("v120",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'MSUBU",ATy(qTy,PTy(uTy,qTy)), + Var("v120",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("MTHI",CTy"MultDiv",Var("v121",FTy 5)), + Apply + (Call + ("dfn'MTHI",ATy(qTy,PTy(uTy,qTy)),Var("v121",FTy 5)), + qVar"state")), + (Call("MTLO",CTy"MultDiv",Var("v122",FTy 5)), + Apply + (Call + ("dfn'MTLO",ATy(qTy,PTy(uTy,qTy)),Var("v122",FTy 5)), + qVar"state")), + (Call + ("MUL",CTy"MultDiv", + Var("v123",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'MUL",ATy(qTy,PTy(uTy,qTy)), + Var("v123",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call("MULT",CTy"MultDiv",Var("v124",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'MULT",ATy(qTy,PTy(uTy,qTy)), + Var("v124",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("MULTU",CTy"MultDiv",Var("v125",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'MULTU",ATy(qTy,PTy(uTy,qTy)), + Var("v125",PTy(FTy 5,FTy 5))),qVar"state"))])), + (Call("SDC2",CTy"instruction",Var("v126",CTy"SDC2")), + CS(Var("v126",CTy"SDC2"), + [(Call("CHERISDC2",CTy"SDC2",Var("v127",CTy"CHERISDC2")), + CS(Var("v127",CTy"CHERISDC2"), + [(Call + ("CSC",CTy"CHERISDC2", + Var("v128",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 11))))), + Apply + (Call + ("dfn'CSC",ATy(qTy,PTy(uTy,qTy)), + Var("v128", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 11))))), + qVar"state"))]))])), + (Call("SWC2",CTy"instruction",Var("v129",CTy"SWC2")), + CS(Var("v129",CTy"SWC2"), + [(Call("CHERISWC2",CTy"SWC2",Var("v130",CTy"CHERISWC2")), + CS(Var("v130",CTy"CHERISWC2"), + [(Call + ("CSCD",CTy"CHERISWC2", + Var("v131",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,F8))))), + Apply + (Call + ("dfn'CSCD",ATy(qTy,PTy(uTy,qTy)), + Var("v131",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,F8))))), + qVar"state")), + (Call + ("CStore",CTy"CHERISWC2", + Var("v132", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(F8,FTy 2)))))), + Apply + (Call + ("dfn'CStore",ATy(qTy,PTy(uTy,qTy)), + Var("v132", + PTy(FTy 5, + PTy(FTy 5,PTy(FTy 5,PTy(F8,FTy 2)))))), + qVar"state"))]))])), + (Call("Shift",CTy"instruction",Var("v133",CTy"Shift")), + CS(Var("v133",CTy"Shift"), + [(Call + ("DSLL",CTy"Shift", + Var("v134",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSLL",ATy(qTy,PTy(uTy,qTy)), + Var("v134",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSLL32",CTy"Shift", + Var("v135",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSLL32",ATy(qTy,PTy(uTy,qTy)), + Var("v135",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSLLV",CTy"Shift", + Var("v136",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSLLV",ATy(qTy,PTy(uTy,qTy)), + Var("v136",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSRA",CTy"Shift", + Var("v137",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSRA",ATy(qTy,PTy(uTy,qTy)), + Var("v137",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSRA32",CTy"Shift", + Var("v138",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSRA32",ATy(qTy,PTy(uTy,qTy)), + Var("v138",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSRAV",CTy"Shift", + Var("v139",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSRAV",ATy(qTy,PTy(uTy,qTy)), + Var("v139",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSRL",CTy"Shift", + Var("v140",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSRL",ATy(qTy,PTy(uTy,qTy)), + Var("v140",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSRL32",CTy"Shift", + Var("v141",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSRL32",ATy(qTy,PTy(uTy,qTy)), + Var("v141",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DSRLV",CTy"Shift", + Var("v142",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DSRLV",ATy(qTy,PTy(uTy,qTy)), + Var("v142",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SLL",CTy"Shift", + Var("v143",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SLL",ATy(qTy,PTy(uTy,qTy)), + Var("v143",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SLLV",CTy"Shift", + Var("v144",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SLLV",ATy(qTy,PTy(uTy,qTy)), + Var("v144",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRA",CTy"Shift", + Var("v145",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRA",ATy(qTy,PTy(uTy,qTy)), + Var("v145",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRAV",CTy"Shift", + Var("v146",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRAV",ATy(qTy,PTy(uTy,qTy)), + Var("v146",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRL",CTy"Shift", + Var("v147",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRL",ATy(qTy,PTy(uTy,qTy)), + Var("v147",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRLV",CTy"Shift", + Var("v148",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRLV",ATy(qTy,PTy(uTy,qTy)), + Var("v148",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state"))])), + (Call("Store",CTy"instruction",Var("v149",CTy"Store")), + CS(Var("v149",CTy"Store"), + [(Call + ("SB",CTy"Store",Var("v150",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SB",ATy(qTy,PTy(uTy,qTy)), + Var("v150",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SC",CTy"Store",Var("v151",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SC",ATy(qTy,PTy(uTy,qTy)), + Var("v151",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SCD",CTy"Store",Var("v152",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SCD",ATy(qTy,PTy(uTy,qTy)), + Var("v152",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SD",CTy"Store",Var("v153",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SD",ATy(qTy,PTy(uTy,qTy)), + Var("v153",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SDL",CTy"Store",Var("v154",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SDL",ATy(qTy,PTy(uTy,qTy)), + Var("v154",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SDR",CTy"Store",Var("v155",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SDR",ATy(qTy,PTy(uTy,qTy)), + Var("v155",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SH",CTy"Store",Var("v156",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SH",ATy(qTy,PTy(uTy,qTy)), + Var("v156",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SW",CTy"Store",Var("v157",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SW",ATy(qTy,PTy(uTy,qTy)), + Var("v157",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SWL",CTy"Store",Var("v158",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SWL",ATy(qTy,PTy(uTy,qTy)), + Var("v158",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state")), + (Call + ("SWR",CTy"Store",Var("v159",PTy(FTy 5,PTy(FTy 5,F16)))), + Apply + (Call + ("dfn'SWR",ATy(qTy,PTy(uTy,qTy)), + Var("v159",PTy(FTy 5,PTy(FTy 5,F16)))),qVar"state"))])), + (Call("Trap",CTy"instruction",Var("v160",CTy"Trap")), + CS(Var("v160",CTy"Trap"), + [(Call("TEQ",CTy"Trap",Var("v161",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'TEQ",ATy(qTy,PTy(uTy,qTy)), + Var("v161",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("TEQI",CTy"Trap",Var("v162",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'TEQI",ATy(qTy,PTy(uTy,qTy)), + Var("v162",PTy(FTy 5,F16))),qVar"state")), + (Call("TGE",CTy"Trap",Var("v163",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'TGE",ATy(qTy,PTy(uTy,qTy)), + Var("v163",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("TGEI",CTy"Trap",Var("v164",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'TGEI",ATy(qTy,PTy(uTy,qTy)), + Var("v164",PTy(FTy 5,F16))),qVar"state")), + (Call("TGEIU",CTy"Trap",Var("v165",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'TGEIU",ATy(qTy,PTy(uTy,qTy)), + Var("v165",PTy(FTy 5,F16))),qVar"state")), + (Call("TGEU",CTy"Trap",Var("v166",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'TGEU",ATy(qTy,PTy(uTy,qTy)), + Var("v166",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("TLT",CTy"Trap",Var("v167",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'TLT",ATy(qTy,PTy(uTy,qTy)), + Var("v167",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("TLTI",CTy"Trap",Var("v168",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'TLTI",ATy(qTy,PTy(uTy,qTy)), + Var("v168",PTy(FTy 5,F16))),qVar"state")), + (Call("TLTIU",CTy"Trap",Var("v169",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'TLTIU",ATy(qTy,PTy(uTy,qTy)), + Var("v169",PTy(FTy 5,F16))),qVar"state")), + (Call("TLTU",CTy"Trap",Var("v170",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'TLTU",ATy(qTy,PTy(uTy,qTy)), + Var("v170",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("TNE",CTy"Trap",Var("v171",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'TNE",ATy(qTy,PTy(uTy,qTy)), + Var("v171",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("TNEI",CTy"Trap",Var("v172",PTy(FTy 5,F16))), + Apply + (Call + ("dfn'TNEI",ATy(qTy,PTy(uTy,qTy)), + Var("v172",PTy(FTy 5,F16))),qVar"state"))]))]))) +; +val COP2Decode_def = Def + ("COP2Decode",Var("v",FTy 26), + Call + ("COP2",CTy"instruction", + Call + ("CHERICOP2",CTy"COP2", + Let(TP[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22",bVar"b'21", + bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17",bVar"b'16", + bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4",bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"],BL(26,Var("v",FTy 26)), + ITB([(bVar"b'23", + ITB([(bVar"b'24", + ITE(Mop(Not,bVar"b'25"), + ITB([(Bop(And,Mop(Not,bVar"b'22"), + Bop(And,bVar"b'21", + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,bVar"b'1", + Mop(Not,bVar"b'0"))))), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetOffset",CTy"CGet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,bVar"b'21", + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,Mop(Not,bVar"b'1"), + bVar"b'0")))), + Call + ("CSet",CTy"CHERICOP2", + Call + ("CSetOffset",CTy"CSet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Mop(Not,bVar"b'21")), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CToPtr",CTy"CGet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,bVar"b'22",Mop(Not,bVar"b'21")), + Call + ("CPtrCmp",CTy"CHERICOP2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7", + bVar"b'6"]), + Mop(Cast(FTy 3), + LL[bVar"b'2",bVar"b'1", + bVar"b'0"])]))], + Const + ("UnknownCapInstruction",CTy"CHERICOP2")), + Const("UnknownCapInstruction",CTy"CHERICOP2"))), + (Mop(Not,bVar"b'25"), + ITB([(Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'2", + Bop(And,bVar"b'1", + Mop(Not,bVar"b'0"))))), + Const("DumpCapReg",CTy"CHERICOP2")), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not,bVar"b'18"), + Bop(And, + Mop(Not,bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))))), + Call + ("CSet",CTy"CHERICOP2", + Call + ("CSetCause",CTy"CSet", + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7",bVar"b'6"])))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,bVar"b'1", + Mop(Not,bVar"b'0"))))), + Call + ("CSet",CTy"CHERICOP2", + Call + ("CIncBase",CTy"CSet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,bVar"b'1",bVar"b'0")))), + Call + ("CSet",CTy"CHERICOP2", + Call + ("CSetLen",CTy"CSet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'2", + Bop(And,Mop(Not,bVar"b'1"), + bVar"b'0")))), + Call + ("CSet",CTy"CHERICOP2", + Call + ("CClearTag",CTy"CSet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,Mop(Not,bVar"b'1"), + Mop(Not,bVar"b'0"))))), + Call + ("CSet",CTy"CHERICOP2", + Call + ("CAndPerm",CTy"CSet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'2", + Bop(And,bVar"b'1",bVar"b'0")))), + Call + ("CSet",CTy"CHERICOP2", + Call + ("CFromPtr",CTy"CSet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,bVar"b'22",bVar"b'21"), + Call + ("CJALR",CTy"CHERICOP2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"])])), + (Bop(And,Mop(Not,bVar"b'22"),bVar"b'21"), + Call + ("CCall",CTy"CHERICOP2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"])])), + (Bop(And,bVar"b'22",Mop(Not,bVar"b'21")), + Const("CReturn",CTy"CHERICOP2"))], + Const("UnknownCapInstruction",CTy"CHERICOP2")))], + Const("UnknownCapInstruction",CTy"CHERICOP2"))), + (bVar"b'24", + ITE(Mop(Not,bVar"b'25"), + ITB([(Bop(And,bVar"b'22", + Bop(And,bVar"b'21", + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,Mop(Not,bVar"b'1"), + Mop(Not,bVar"b'0"))))), + Call + ("CCheck",CTy"CHERICOP2", + Call + ("CCheckPerm",CTy"CCheck", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7",bVar"b'6"])]))), + (Bop(And,bVar"b'22", + Bop(And,bVar"b'21", + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,Mop(Not,bVar"b'1"), + bVar"b'0")))), + Call + ("CCheck",CTy"CHERICOP2", + Call + ("CCheckType",CTy"CCheck", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'22"),bVar"b'21"), + Call + ("CBTU",CTy"CHERICOP2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4",bVar"b'3", + bVar"b'2",bVar"b'1",bVar"b'0"])])), + (Bop(And,bVar"b'22",Mop(Not,bVar"b'21")), + Call + ("CBTS",CTy"CHERICOP2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4",bVar"b'3", + bVar"b'2",bVar"b'1",bVar"b'0"])])), + (Bop(And,Mop(Not,bVar"b'22"), + Mop(Not,bVar"b'21")), + Call + ("CJR",CTy"CHERICOP2", + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"])))], + Const("UnknownCapInstruction",CTy"CHERICOP2")), + Const("UnknownCapInstruction",CTy"CHERICOP2"))), + (Mop(Not,bVar"b'25"), + ITB([(Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,bVar"b'1",Mop(Not,bVar"b'0"))))), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetBase",CTy"CGet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,bVar"b'1",bVar"b'0")))), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetLen",CTy"CGet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'2", + Bop(And,Mop(Not,bVar"b'1"),bVar"b'0")))), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetTag",CTy"CGet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'2", + Bop(And,bVar"b'1",Mop(Not,bVar"b'0"))))), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetSealed",CTy"CGet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,Mop(Not,bVar"b'1"), + Mop(Not,bVar"b'0"))))), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetPerm",CTy"CGet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,Mop(Not,bVar"b'1"),bVar"b'0")))), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetType",CTy"CGet", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'2", + Bop(And,bVar"b'1",bVar"b'0")))), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetPCC",CTy"CGet", + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"])))), + (Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And, + Mop(Not,bVar"b'11"), + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0")))))))))), + Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetCause",CTy"CGet", + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"])))), + (Bop(And,bVar"b'22",Mop(Not,bVar"b'21")), + Call + ("CSeal",CTy"CHERICOP2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6"])])), + (Bop(And,bVar"b'22",bVar"b'21"), + Call + ("CUnseal",CTy"CHERICOP2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6"])]))], + Const("UnknownCapInstruction",CTy"CHERICOP2")))], + Const("UnknownCapInstruction",CTy"CHERICOP2")))))) +; +val LWC2Decode_def = Def + ("LWC2Decode",Var("v",FTy 26), + Call + ("LWC2",CTy"instruction", + Call + ("CHERILWC2",CTy"LWC2", + Let(TP[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22",bVar"b'21", + bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17",bVar"b'16", + bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4",bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"],BL(26,Var("v",FTy 26)), + ITB([(Mop(Not,bVar"b'2"), + Call + ("CLoad",CTy"CHERILWC2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast F8, + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3"]), + LW(0,1),Mop(Cast(FTy 2),LL[bVar"b'1",bVar"b'0"])])), + (Bop(And,bVar"b'2", + Bop(And,Mop(Not,bVar"b'1"),Mop(Not,bVar"b'0"))), + Call + ("CLoad",CTy"CHERILWC2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast F8, + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3"]), + LW(1,1),LW(0,2)])), + (Bop(And,bVar"b'2",Bop(And,Mop(Not,bVar"b'1"),bVar"b'0")), + Call + ("CLoad",CTy"CHERILWC2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast F8, + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3"]), + LW(1,1),LW(1,2)])), + (Bop(And,bVar"b'2",Bop(And,bVar"b'1",Mop(Not,bVar"b'0"))), + Call + ("CLoad",CTy"CHERILWC2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast F8, + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3"]), + LW(1,1),LW(2,2)]))], + Call + ("CLLD",CTy"CHERILWC2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast F8, + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3"])])))))) +; +val LDC2Decode_def = Def + ("LDC2Decode",Var("v",FTy 26), + CS(BL(26,Var("v",FTy 26)), + [(TP[bVar"cd'4",bVar"cd'3",bVar"cd'2",bVar"cd'1",bVar"cd'0", + bVar"cb'4",bVar"cb'3",bVar"cb'2",bVar"cb'1",bVar"cb'0", + bVar"rt'4",bVar"rt'3",bVar"rt'2",bVar"rt'1",bVar"rt'0", + bVar"offset'10",bVar"offset'9",bVar"offset'8",bVar"offset'7", + bVar"offset'6",bVar"offset'5",bVar"offset'4",bVar"offset'3", + bVar"offset'2",bVar"offset'1",bVar"offset'0"], + Call + ("LDC2",CTy"instruction", + Call + ("CHERILDC2",CTy"LDC2", + Call + ("CLC",CTy"CHERILDC2", + TP[Mop(Cast(FTy 5), + LL[bVar"cd'4",bVar"cd'3",bVar"cd'2",bVar"cd'1", + bVar"cd'0"]), + Mop(Cast(FTy 5), + LL[bVar"cb'4",bVar"cb'3",bVar"cb'2",bVar"cb'1", + bVar"cb'0"]), + Mop(Cast(FTy 5), + LL[bVar"rt'4",bVar"rt'3",bVar"rt'2",bVar"rt'1", + bVar"rt'0"]), + Mop(Cast(FTy 11), + LL[bVar"offset'10",bVar"offset'9",bVar"offset'8", + bVar"offset'7",bVar"offset'6",bVar"offset'5", + bVar"offset'4",bVar"offset'3",bVar"offset'2", + bVar"offset'1",bVar"offset'0"])]))))])) +; +val SWC2Decode_def = Def + ("SWC2Decode",Var("v",FTy 26), + Let(TP[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22",bVar"b'21", + bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17",bVar"b'16", + bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7",bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"], + BL(26,Var("v",FTy 26)), + ITB([(Mop(Not,bVar"b'2"), + Call + ("SWC2",CTy"instruction", + Call + ("CHERISWC2",CTy"SWC2", + Call + ("CStore",CTy"CHERISWC2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast F8, + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3"]), + Mop(Cast(FTy 2),LL[bVar"b'1",bVar"b'0"])])))), + (Bop(And,bVar"b'2",Bop(And,bVar"b'1",bVar"b'0")), + Call + ("SWC2",CTy"instruction", + Call + ("CHERISWC2",CTy"SWC2", + Call + ("CSCD",CTy"CHERISWC2", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast F8, + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3"])]))))], + Call + ("COP2",CTy"instruction", + Call + ("CHERICOP2",CTy"COP2", + Const("UnknownCapInstruction",CTy"CHERICOP2")))))) +; +val SDC2Decode_def = Def + ("SDC2Decode",Var("v",FTy 26), + CS(BL(26,Var("v",FTy 26)), + [(TP[bVar"cs'4",bVar"cs'3",bVar"cs'2",bVar"cs'1",bVar"cs'0", + bVar"cb'4",bVar"cb'3",bVar"cb'2",bVar"cb'1",bVar"cb'0", + bVar"rt'4",bVar"rt'3",bVar"rt'2",bVar"rt'1",bVar"rt'0", + bVar"offset'10",bVar"offset'9",bVar"offset'8",bVar"offset'7", + bVar"offset'6",bVar"offset'5",bVar"offset'4",bVar"offset'3", + bVar"offset'2",bVar"offset'1",bVar"offset'0"], + Call + ("SDC2",CTy"instruction", + Call + ("CHERISDC2",CTy"SDC2", + Call + ("CSC",CTy"CHERISDC2", + TP[Mop(Cast(FTy 5), + LL[bVar"cs'4",bVar"cs'3",bVar"cs'2",bVar"cs'1", + bVar"cs'0"]), + Mop(Cast(FTy 5), + LL[bVar"cb'4",bVar"cb'3",bVar"cb'2",bVar"cb'1", + bVar"cb'0"]), + Mop(Cast(FTy 5), + LL[bVar"rt'4",bVar"rt'3",bVar"rt'2",bVar"rt'1", + bVar"rt'0"]), + Mop(Cast(FTy 11), + LL[bVar"offset'10",bVar"offset'9",bVar"offset'8", + bVar"offset'7",bVar"offset'6",bVar"offset'5", + bVar"offset'4",bVar"offset'3",bVar"offset'2", + bVar"offset'1",bVar"offset'0"])]))))])) +; +val Decode_def = Def + ("Decode",Var("w",F32), + Let(TP[bVar"b'31",bVar"b'30",bVar"b'29",bVar"b'28",bVar"b'27", + bVar"b'26",bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4",bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"], + BL(32,Var("w",F32)), + ITB([(bVar"b'26", + ITB([(bVar"b'28", + ITB([(bVar"b'31", + ITB([(Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Mop(Not,bVar"b'27"))), + Call + ("Load",CTy"instruction", + Call + ("LHU",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"),bVar"b'27")), + Call + ("Load",CTy"instruction", + Call + ("LWU",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29",Mop(Not,bVar"b'27"))), + Call + ("Store",CTy"instruction", + Call + ("SDR",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"),bVar"b'27")), + Call + ("Load",CTy"instruction", + Call + ("LD",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'30", + Bop(And,bVar"b'29",bVar"b'27")), + Call + ("Store",CTy"instruction", + Call + ("SD",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29",bVar"b'27")), + Call + ("CACHE",CTy"instruction", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))], + Const("ReservedInstruction",CTy"instruction"))), + (Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And, + Mop(Not,bVar"b'17"), + Mop(Not,bVar"b'16")))))))), + Call + ("Branch",CTy"instruction", + Call + ("BGTZ",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And, + Mop(Not,bVar"b'22"), + Mop(Not,bVar"b'21")))))))), + Call + ("ArithI",CTy"instruction", + Call + ("LUI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And, + Mop(Not,bVar"b'17"), + Mop(Not,bVar"b'16")))))))), + Call + ("Branch",CTy"instruction", + Call + ("BGTZL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Mop(Not,bVar"b'27"))), + Call + ("Branch",CTy"instruction", + Call + ("BNE",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29",Mop(Not,bVar"b'27"))), + Call + ("ArithI",CTy"instruction", + Call + ("ORI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Mop(Not,bVar"b'27"))), + Call + ("Branch",CTy"instruction", + Call + ("BNEL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And, + Mop(Not,bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))))))))), + Call + ("RDHWR",CTy"instruction", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"])]))], + Const("ReservedInstruction",CTy"instruction"))), + (bVar"b'29", + ITB([(Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Mop(Not,bVar"b'27"))), + Call + ("ArithI",CTy"instruction", + Call + ("ADDIU",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"),bVar"b'27")), + Call + ("ArithI",CTy"instruction", + Call + ("SLTIU",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30",Mop(Not,bVar"b'27"))), + Call + ("ArithI",CTy"instruction", + Call + ("DADDIU",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30",bVar"b'27")), + Call + ("Load",CTy"instruction", + Call + ("LDR",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Mop(Not,bVar"b'27"))), + Call + ("Store",CTy"instruction", + Call + ("SH",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"),bVar"b'27")), + Call + ("Store",CTy"instruction", + Call + ("SW",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])])))], + Const("ReservedInstruction",CTy"instruction"))), + (Mop(Not,bVar"b'30"), + ITB([(Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + Mop(Not,bVar"b'16"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BLTZ",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + bVar"b'16")))))), + Call + ("Branch",CTy"instruction", + Call + ("BGEZ",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,bVar"b'17", + Mop(Not,bVar"b'16"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BLTZL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,bVar"b'17",bVar"b'16")))))), + Call + ("Branch",CTy"instruction", + Call + ("BGEZL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,bVar"b'19", + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + Mop(Not,bVar"b'16"))))))), + Call + ("Trap",CTy"instruction", + Call + ("TGEI",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,bVar"b'19", + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + bVar"b'16")))))), + Call + ("Trap",CTy"instruction", + Call + ("TGEIU",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,bVar"b'19", + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,bVar"b'17", + Mop(Not,bVar"b'16"))))))), + Call + ("Trap",CTy"instruction", + Call + ("TLTI",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,bVar"b'19", + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,bVar"b'17",bVar"b'16")))))), + Call + ("Trap",CTy"instruction", + Call + ("TLTIU",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,bVar"b'19", + Bop(And,bVar"b'18", + Bop(And,Mop(Not,bVar"b'17"), + Mop(Not,bVar"b'16"))))))), + Call + ("Trap",CTy"instruction", + Call + ("TEQI",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,bVar"b'19", + Bop(And,bVar"b'18", + Bop(And,bVar"b'17", + Mop(Not,bVar"b'16"))))))), + Call + ("Trap",CTy"instruction", + Call + ("TNEI",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'25", + Bop(And,bVar"b'24", + Bop(And,bVar"b'23", + Bop(And,bVar"b'22", + Bop(And,bVar"b'21", + Bop(And,bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'19"), + Mop(Not, + bVar"b'18")))))))))), + Const("Unpredictable",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'20", + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + Mop(Not,bVar"b'16"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BLTZAL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'20", + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + bVar"b'16")))))), + Call + ("Branch",CTy"instruction", + Call + ("BGEZAL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'20", + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,bVar"b'17", + Mop(Not,bVar"b'16"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BLTZALL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'20", + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,bVar"b'17",bVar"b'16")))))), + Call + ("Branch",CTy"instruction", + Call + ("BGEZALL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"),bVar"b'27"), + Call + ("Branch",CTy"instruction", + Call + ("JAL",CTy"Branch", + Mop(Cast(FTy 26), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20", + bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])))), + (Bop(And,bVar"b'31",Mop(Not,bVar"b'27")), + Call + ("Load",CTy"instruction", + Call + ("LH",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'31",bVar"b'27"), + Call + ("Load",CTy"instruction", + Call + ("LW",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])])))], + Const("ReservedInstruction",CTy"instruction")))], + Const("ReservedInstruction",CTy"instruction"))), + (bVar"b'30", + ITB([(bVar"b'29", + ITB([(bVar"b'28", + ITB([(Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0")))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MADD",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0"))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MADDU",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0")))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MSUB",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0"))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MSUBU",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MUL",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,bVar"b'31",Mop(Not,bVar"b'27")), + Call + ("Store",CTy"instruction", + Call + ("SCD",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24", + bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19", + bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'31",bVar"b'27"), + Call + ("SDC2Decode",CTy"instruction", + Mop(Cast(FTy 26), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20", + bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])))], + Const("ReservedInstruction",CTy"instruction"))), + (Bop(And,Mop(Not,bVar"b'31"),Mop(Not,bVar"b'27")), + Call + ("ArithI",CTy"instruction", + Call + ("DADDI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'31"),bVar"b'27"), + Call + ("Load",CTy"instruction", + Call + ("LDL",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'31",Mop(Not,bVar"b'27")), + Call + ("Store",CTy"instruction", + Call + ("SC",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'31",bVar"b'27"), + Call + ("SWC2Decode",CTy"instruction", + Mop(Cast(FTy 26), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20", + bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])))], + Const("ReservedInstruction",CTy"instruction"))), + (bVar"b'31", + ITB([(Bop(And,Mop(Not,bVar"b'28"),Mop(Not,bVar"b'27")), + Call + ("Load",CTy"instruction", + Call + ("LL",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'28",Mop(Not,bVar"b'27")), + Call + ("Load",CTy"instruction", + Call + ("LLD",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'28"),bVar"b'27"), + Call + ("LWC2Decode",CTy"instruction", + Mop(Cast(FTy 26), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20", + bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"]))), + (Bop(And,bVar"b'28",bVar"b'27"), + Call + ("LDC2Decode",CTy"instruction", + Mop(Cast(FTy 26), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20", + bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])))], + Const("ReservedInstruction",CTy"instruction"))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not,bVar"b'20"), + Bop(And, + Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0"))))))))))))))))))))))))))), + Const("TLBR",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not,bVar"b'20"), + Bop(And, + Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0")))))))))))))))))))))))))))), + Const("TLBWI",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not,bVar"b'20"), + Bop(And, + Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + bVar"b'2", + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0")))))))))))))))))))))))))))), + Const("TLBWR",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not,bVar"b'20"), + Bop(And, + Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0")))))))))))))))))))))))))))), + Const("TLBP",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not,bVar"b'20"), + Bop(And, + Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0")))))))))))))))))))))))))))), + Const("ERET",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not,bVar"b'10"), + Bop(And, + Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Mop(Not, + bVar"b'3"))))))))))))))), + Call + ("CP",CTy"instruction", + Call + ("MFC0",CTy"CP", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast(FTy 3), + LL[bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,bVar"b'21", + Bop(And, + Mop(Not,bVar"b'10"), + Bop(And, + Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Mop(Not, + bVar"b'3"))))))))))))))), + Call + ("CP",CTy"instruction", + Call + ("DMFC0",CTy"CP", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast(FTy 3), + LL[bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,bVar"b'23", + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not,bVar"b'10"), + Bop(And, + Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Mop(Not, + bVar"b'3"))))))))))))))), + Call + ("CP",CTy"instruction", + Call + ("MTC0",CTy"CP", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast(FTy 3), + LL[bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,bVar"b'23", + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,bVar"b'21", + Bop(And, + Mop(Not,bVar"b'10"), + Bop(And, + Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Mop(Not, + bVar"b'3"))))))))))))))), + Call + ("CP",CTy"instruction", + Call + ("DMTC0",CTy"CP", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11"]), + Mop(Cast(FTy 3), + LL[bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'28", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + Mop(Not,bVar"b'16"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BLEZL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'28",Mop(Not,bVar"b'27")), + Call + ("Branch",CTy"instruction", + Call + ("BEQL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not,bVar"b'20"), + Bop(And, + Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0")))))))))))))))))))))))))))), + Const("WAIT",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'28"),bVar"b'27"), + Call + ("COP2Decode",CTy"instruction", + Mop(Cast(FTy 26), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16",bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4",bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])))], + Const("ReservedInstruction",CTy"instruction"))), + (bVar"b'31", + ITB([(bVar"b'29", + ITB([(Bop(And,Mop(Not,bVar"b'28"),Mop(Not,bVar"b'27")), + Call + ("Store",CTy"instruction", + Call + ("SB",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'28"),bVar"b'27"), + Call + ("Store",CTy"instruction", + Call + ("SWL",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'28",Mop(Not,bVar"b'27")), + Call + ("Store",CTy"instruction", + Call + ("SDL",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])]))), + (Bop(And,bVar"b'28",bVar"b'27"), + Call + ("Store",CTy"instruction", + Call + ("SWR",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1", + bVar"b'0"])])))], + Const("ReservedInstruction",CTy"instruction"))), + (Bop(And,Mop(Not,bVar"b'28"),Mop(Not,bVar"b'27")), + Call + ("Load",CTy"instruction", + Call + ("LB",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'28"),bVar"b'27"), + Call + ("Load",CTy"instruction", + Call + ("LWL",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'28",Mop(Not,bVar"b'27")), + Call + ("Load",CTy"instruction", + Call + ("LBU",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'28",bVar"b'27"), + Call + ("Load",CTy"instruction", + Call + ("LWR",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])])))], + Const("ReservedInstruction",CTy"instruction"))), + (bVar"b'29", + ITB([(Bop(And,Mop(Not,bVar"b'28"),Mop(Not,bVar"b'27")), + Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,Mop(Not,bVar"b'28"),bVar"b'27"), + Call + ("ArithI",CTy"instruction", + Call + ("SLTI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'28",Mop(Not,bVar"b'27")), + Call + ("ArithI",CTy"instruction", + Call + ("ANDI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'28",bVar"b'27"), + Call + ("ArithI",CTy"instruction", + Call + ("XORI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13", + bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])])))], + Const("ReservedInstruction",CTy"instruction"))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SLL",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRL",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRA",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SLLV",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRLV",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRAV",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + Bop(And,Mop(Not,bVar"b'16"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0")))))))))))))))))), + Call + ("Branch",CTy"instruction", + Call + ("JR",CTy"Branch", + Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"])))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + Bop(And,Mop(Not,bVar"b'16"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0")))))))))))), + Call + ("Branch",CTy"instruction", + Call + ("JALR",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("MOVZ",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("MOVN",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))), + Const("SYSCALL",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0")))))))))))), + Const("BREAK",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not,bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + Bop(And, + bVar"b'2", + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))))))))))))), + Call + ("SYNC",CTy"instruction", + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7",bVar"b'6"]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not,bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MFHI",CTy"MultDiv", + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + Bop(And,Mop(Not,bVar"b'16"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0")))))))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MTHI",CTy"MultDiv", + Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"])))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And, + Mop(Not,bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MFLO",CTy"MultDiv", + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + Bop(And,Mop(Not,bVar"b'16"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MTLO",CTy"MultDiv", + Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"])))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("DSLLV",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("DSRLV",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("DSRAV",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not,bVar"b'8"), + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0")))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MULT",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not,bVar"b'8"), + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0"))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("MULTU",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not,bVar"b'8"), + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0")))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("DIV",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not,bVar"b'8"), + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + Mop(Not, + bVar"b'2"), + Bop(And, + bVar"b'1", + bVar"b'0"))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("DIVU",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not,bVar"b'8"), + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0")))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("DMULT",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not,bVar"b'8"), + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0"))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("DMULTU",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not,bVar"b'8"), + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + bVar"b'2", + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0")))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("DDIV",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'15"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And, + Mop(Not,bVar"b'8"), + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Bop(And, + bVar"b'2", + Bop(And, + bVar"b'1", + bVar"b'0"))))))))))))))))), + Call + ("MultDiv",CTy"instruction", + Call + ("DDIVU",CTy"MultDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("ADD",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0")))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("ADDU",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("SUB",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("SUBU",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("AND",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0")))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("OR",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("XOR",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("NOR",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("SLT",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("SLTU",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("DADD",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0")))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("DADDU",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("DSUB",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("DSUBU",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,Mop(Not,bVar"b'1"), + Mop(Not,bVar"b'0")))))))), + Call + ("Trap",CTy"instruction", + Call + ("TGE",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,Mop(Not,bVar"b'1"),bVar"b'0"))))))), + Call + ("Trap",CTy"instruction", + Call + ("TGEU",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,bVar"b'1",Mop(Not,bVar"b'0")))))))), + Call + ("Trap",CTy"instruction", + Call + ("TLT",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Bop(And,Mop(Not,bVar"b'2"), + Bop(And,bVar"b'1",bVar"b'0"))))))), + Call + ("Trap",CTy"instruction", + Call + ("TLTU",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And,Mop(Not,bVar"b'1"), + Mop(Not,bVar"b'0")))))))), + Call + ("Trap",CTy"instruction", + Call + ("TEQ",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Bop(And,bVar"b'2", + Bop(And,bVar"b'1",Mop(Not,bVar"b'0")))))))), + Call + ("Trap",CTy"instruction", + Call + ("TNE",CTy"Trap", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,bVar"b'3", + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("DSLL",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,bVar"b'3", + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("DSRL",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,bVar"b'3", + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("DSRA",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,bVar"b'3", + Bop(And,bVar"b'2", + Bop(And, + Mop(Not, + bVar"b'1"), + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("DSLL32",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,bVar"b'3", + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + Mop(Not, + bVar"b'0"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("DSRL32",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And,Mop(Not,bVar"b'22"), + Bop(And,Mop(Not,bVar"b'21"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,bVar"b'3", + Bop(And,bVar"b'2", + Bop(And, + bVar"b'1", + bVar"b'0")))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("DSRA32",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast(FTy 5), + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11"]), + Mop(Cast(FTy 5), + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7", + bVar"b'6"])]))), + (Bop(And,Mop(Not,bVar"b'28"),bVar"b'27"), + Call + ("Branch",CTy"instruction", + Call + ("J",CTy"Branch", + Mop(Cast(FTy 26), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20",bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16",bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12",bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4",bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"])))), + (Bop(And,bVar"b'28", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'20"), + Bop(And,Mop(Not,bVar"b'19"), + Bop(And,Mop(Not,bVar"b'18"), + Bop(And,Mop(Not,bVar"b'17"), + Mop(Not,bVar"b'16"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BLEZ",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])]))), + (Bop(And,bVar"b'28",Mop(Not,bVar"b'27")), + Call + ("Branch",CTy"instruction", + Call + ("BEQ",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21"]), + Mop(Cast(FTy 5), + LL[bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16"]), + Mop(Cast F16, + LL[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7",bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"])])))], + Const("ReservedInstruction",CTy"instruction")))) +; +val COP2InstructionToString_def = Def + ("COP2InstructionToString",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call + ("COP2",CTy"instruction", + Call("CHERICOP2",CTy"COP2",Var("j",CTy"CHERICOP2"))), + CS(Var("j",CTy"CHERICOP2"), + [(Const("DumpCapReg",CTy"CHERICOP2"),LS"mtc2 ?,?,6"), + (Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetBase",CTy"CGet", + TP[Var("rd",FTy 5),Var("cb",FTy 5)])), + Call + ("op2r",sTy, + TP[LS"cgetbase",Var("rd",FTy 5),Var("cb",FTy 5)])), + (Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetOffset",CTy"CGet", + TP[Var("rd",FTy 5),Var("cb",FTy 5)])), + Call + ("op2r",sTy, + TP[LS"cgetoffset",Var("rd",FTy 5),Var("cb",FTy 5)])), + (Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetLen",CTy"CGet",TP[Var("rd",FTy 5),Var("cb",FTy 5)])), + Call + ("op2r",sTy,TP[LS"cgetlen",Var("rd",FTy 5),Var("cb",FTy 5)])), + (Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetTag",CTy"CGet",TP[Var("rd",FTy 5),Var("cb",FTy 5)])), + Call + ("op2r",sTy,TP[LS"cgettag",Var("rd",FTy 5),Var("cb",FTy 5)])), + (Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetSealed",CTy"CGet", + TP[Var("rd",FTy 5),Var("cb",FTy 5)])), + Call + ("op2r",sTy, + TP[LS"cgetsealed",Var("rd",FTy 5),Var("cb",FTy 5)])), + (Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetPerm",CTy"CGet", + TP[Var("rd",FTy 5),Var("cb",FTy 5)])), + Call + ("op2r",sTy, + TP[LS"cgetperm",Var("rd",FTy 5),Var("cb",FTy 5)])), + (Call + ("CGet",CTy"CHERICOP2", + Call + ("CGetType",CTy"CGet", + TP[Var("rd",FTy 5),Var("cb",FTy 5)])), + Call + ("op2r",sTy, + TP[LS"cgettype",Var("rd",FTy 5),Var("cb",FTy 5)])), + (Call + ("CGet",CTy"CHERICOP2", + Call("CGetPCC",CTy"CGet",Var("cd",FTy 5))), + Call("op1r",sTy,TP[LS"cgetpcc",Var("cd",FTy 5)])), + (Call + ("CGet",CTy"CHERICOP2", + Call("CGetCause",CTy"CGet",Var("rd",FTy 5))), + Call("op1r",sTy,TP[LS"cgetcause",Var("rd",FTy 5)])), + (Call + ("CSet",CTy"CHERICOP2", + Call("CSetCause",CTy"CSet",Var("rt",FTy 5))), + Call("op1r",sTy,TP[LS"csetcause",Var("rt",FTy 5)])), + (Call + ("CSet",CTy"CHERICOP2", + Call + ("CIncBase",CTy"CSet", + TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"cincbase",Var("cd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5)])), + (Call + ("CSet",CTy"CHERICOP2", + Call + ("CSetLen",CTy"CSet", + TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"csetlen",Var("cd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5)])), + (Call + ("CSet",CTy"CHERICOP2", + Call + ("CClearTag",CTy"CSet", + TP[Var("cd",FTy 5),Var("cb",FTy 5)])), + Call + ("op2r",sTy, + TP[LS"ccleartag",Var("cd",FTy 5),Var("cb",FTy 5)])), + (Call + ("CSet",CTy"CHERICOP2", + Call + ("CAndPerm",CTy"CSet", + TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"candperm",Var("cd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5)])), + (Call + ("CSet",CTy"CHERICOP2", + Call + ("CSetOffset",CTy"CSet", + TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"csetoffset",Var("cd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5)])), + (Call + ("CCheck",CTy"CHERICOP2", + Call + ("CCheckPerm",CTy"CCheck", + TP[Var("cs",FTy 5),Var("rt",FTy 5)])), + Call + ("op2r",sTy, + TP[LS"ccheckperm",Var("cs",FTy 5),Var("rt",FTy 5)])), + (Call + ("CCheck",CTy"CHERICOP2", + Call + ("CCheckType",CTy"CCheck", + TP[Var("cs",FTy 5),Var("cb",FTy 5)])), + Call + ("op2r",sTy, + TP[LS"cchecktype",Var("cs",FTy 5),Var("cb",FTy 5)])), + (Call + ("CSet",CTy"CHERICOP2", + Call + ("CFromPtr",CTy"CSet", + TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"cfromptr",Var("cd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5)])), + (Call + ("CGet",CTy"CHERICOP2", + Call + ("CToPtr",CTy"CGet", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("ct",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"ctoptr",Var("rd",FTy 5),Var("cb",FTy 5), + Var("ct",FTy 5)])), + (Call + ("CPtrCmp",CTy"CHERICOP2", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("ct",FTy 5), + Var("t",FTy 3)]), + CS(Var("t",FTy 3), + [(LW(0,3), + Call + ("op3r",sTy, + TP[LS"ceq",Var("rd",FTy 5),Var("cb",FTy 5), + Var("ct",FTy 5)])), + (LW(1,3), + Call + ("op3r",sTy, + TP[LS"cne",Var("rd",FTy 5),Var("cb",FTy 5), + Var("ct",FTy 5)])), + (LW(2,3), + Call + ("op3r",sTy, + TP[LS"clt",Var("rd",FTy 5),Var("cb",FTy 5), + Var("ct",FTy 5)])), + (LW(3,3), + Call + ("op3r",sTy, + TP[LS"cle",Var("rd",FTy 5),Var("cb",FTy 5), + Var("ct",FTy 5)])), + (LW(4,3), + Call + ("op3r",sTy, + TP[LS"cltu",Var("rd",FTy 5),Var("cb",FTy 5), + Var("ct",FTy 5)])), + (LW(5,3), + Call + ("op3r",sTy, + TP[LS"cleu",Var("rd",FTy 5),Var("cb",FTy 5), + Var("ct",FTy 5)])), + (AVar(FTy 3),LS"unmatched_cap_inst")])), + (Call + ("CBTU",CTy"CHERICOP2", + TP[Var("cb",FTy 5),Var("offset",F16)]), + Call + ("op1ri",sTy,TP[LS"cbtu",Var("cb",FTy 5),Var("offset",F16)])), + (Call + ("CBTS",CTy"CHERICOP2", + TP[Var("cb",FTy 5),Var("offset",F16)]), + Call + ("op1ri",sTy,TP[LS"cbts",Var("cb",FTy 5),Var("offset",F16)])), + (Call("CJR",CTy"CHERICOP2",Var("cb",FTy 5)), + Call("op1r",sTy,TP[LS"cjr",Var("cb",FTy 5)])), + (Call + ("CJALR",CTy"CHERICOP2",TP[Var("cd",FTy 5),Var("cb",FTy 5)]), + Call + ("op2r",sTy,TP[LS"cjalr",Var("cd",FTy 5),Var("cb",FTy 5)])), + (Call + ("CSeal",CTy"CHERICOP2", + TP[Var("cd",FTy 5),Var("cs",FTy 5),Var("ct",FTy 5)]), + Call + ("op3r",sTy, + TP[LS"cseal",Var("cd",FTy 5),Var("cs",FTy 5), + Var("ct",FTy 5)])), + (Call + ("CUnseal",CTy"CHERICOP2", + TP[Var("cd",FTy 5),Var("cs",FTy 5),Var("ct",FTy 5)]), + Call + ("op3r",sTy, + TP[LS"cunseal",Var("cd",FTy 5),Var("cs",FTy 5), + Var("ct",FTy 5)])), + (Call + ("CCall",CTy"CHERICOP2",TP[Var("cs",FTy 5),Var("cb",FTy 5)]), + Call + ("op2r",sTy,TP[LS"ccall",Var("cs",FTy 5),Var("cb",FTy 5)])), + (Const("CReturn",CTy"CHERICOP2"),LS"creturn"), + (Const("UnknownCapInstruction",CTy"CHERICOP2"), + LS"unknown_cap_inst")])), + (AVar(CTy"instruction"),LS"unmatched_cap_inst")])) +; +val LWC2InstructionToString_def = Def + ("LWC2InstructionToString",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call + ("LWC2",CTy"instruction", + Call("CHERILWC2",CTy"LWC2",Var("j",CTy"CHERILWC2"))), + CS(Var("j",CTy"CHERILWC2"), + [(Call + ("CLoad",CTy"CHERILWC2", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5), + Var("offset",F8),LW(0,1),Var("t",FTy 2)]), + CS(Var("t",FTy 2), + [(LW(0,2), + Call + ("op3ro",sTy, + TP[LS"clbu",Var("rd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (LW(1,2), + Call + ("op3ro",sTy, + TP[LS"clhu",Var("rd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (LW(2,2), + Call + ("op3ro",sTy, + TP[LS"clwu",Var("rd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (LW(3,2), + Call + ("op3ro",sTy, + TP[LS"cld",Var("rd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)]))])), + (Call + ("CLoad",CTy"CHERILWC2", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5), + Var("offset",F8),LW(1,1),LW(0,2)]), + Call + ("op3ro",sTy, + TP[LS"clb",Var("rd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (Call + ("CLoad",CTy"CHERILWC2", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5), + Var("offset",F8),LW(1,1),LW(1,2)]), + Call + ("op3ro",sTy, + TP[LS"clh",Var("rd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (Call + ("CLoad",CTy"CHERILWC2", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5), + Var("offset",F8),LW(1,1),LW(2,2)]), + Call + ("op3ro",sTy, + TP[LS"clw",Var("rd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (Call + ("CLLD",CTy"CHERILWC2", + TP[Var("rd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5), + Var("offset",F8)]), + Call + ("op3ro",sTy, + TP[LS"clld",Var("rd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (AVar(CTy"CHERILWC2"),LS"unmatched_cap_inst")])), + (AVar(CTy"instruction"),LS"unmatched_cap_inst")])) +; +val LDC2InstructionToString_def = Def + ("LDC2InstructionToString",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call + ("LDC2",CTy"instruction", + Call("CHERILDC2",CTy"LDC2",Var("j",CTy"CHERILDC2"))), + CS(Var("j",CTy"CHERILDC2"), + [(Call + ("CLC",CTy"CHERILDC2", + TP[Var("cd",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5), + Var("offset",FTy 11)]), + Call + ("op3ro",sTy, + TP[LS"clc",Var("cd",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",FTy 11)]))])), + (AVar(CTy"instruction"),LS"unmatched_cap_inst")])) +; +val SWC2InstructionToString_def = Def + ("SWC2InstructionToString",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call + ("SWC2",CTy"instruction", + Call("CHERISWC2",CTy"SWC2",Var("j",CTy"CHERISWC2"))), + CS(Var("j",CTy"CHERISWC2"), + [(Call + ("CStore",CTy"CHERISWC2", + TP[Var("rs",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5), + Var("offset",F8),Var("t",FTy 2)]), + CS(Var("t",FTy 2), + [(LW(0,2), + Call + ("op3ro",sTy, + TP[LS"csb",Var("rs",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (LW(1,2), + Call + ("op3ro",sTy, + TP[LS"csh",Var("rs",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (LW(2,2), + Call + ("op3ro",sTy, + TP[LS"csw",Var("rs",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)])), + (LW(3,2), + Call + ("op3ro",sTy, + TP[LS"csd",Var("rs",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)]))])), + (Call + ("CSCD",CTy"CHERISWC2", + TP[Var("rs",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5), + Var("offset",F8)]), + Call + ("op3ro",sTy, + TP[LS"cscd",Var("rs",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",F8)]))])), + (AVar(CTy"instruction"),LS"unmatched_cap_inst")])) +; +val SDC2InstructionToString_def = Def + ("SDC2InstructionToString",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call + ("SDC2",CTy"instruction", + Call("CHERISDC2",CTy"SDC2",Var("j",CTy"CHERISDC2"))), + CS(Var("j",CTy"CHERISDC2"), + [(Call + ("CSC",CTy"CHERISDC2", + TP[Var("cs",FTy 5),Var("cb",FTy 5),Var("rt",FTy 5), + Var("offset",FTy 11)]), + Call + ("op3ro",sTy, + TP[LS"csc",Var("cs",FTy 5),Var("cb",FTy 5), + Var("rt",FTy 5),Var("offset",FTy 11)]))])), + (AVar(CTy"instruction"),LS"unmatched_cap_inst")])) +; +val COP2Encode_def = Def + ("COP2Encode",Var("i",CTy"instruction"),CC[LW(18,6),LW(0,26)]) +; +val LWC2Encode_def = Def + ("LWC2Encode",Var("i",CTy"instruction"),CC[LW(50,6),LW(0,26)]) +; +val LDC2Encode_def = Def + ("LDC2Encode",Var("i",CTy"instruction"),CC[LW(54,6),LW(0,26)]) +; +val SWC2Encode_def = Def + ("SWC2Encode",Var("i",CTy"instruction"),CC[LW(58,6),LW(0,26)]) +; +val SDC2Encode_def = Def + ("SDC2Encode",Var("i",CTy"instruction"),CC[LW(62,6),LW(0,26)]) +; +val instructionToString_def = Def + ("instructionToString",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call + ("Shift",CTy"instruction", + Call("SLL",CTy"Shift",TP[LW(0,5),LW(0,5),LW(0,5)])),LS"nop"), + (Call + ("Shift",CTy"instruction", + Call("SLL",CTy"Shift",TP[LW(0,5),LW(0,5),LW(1,5)])),LS"ssnop"), + (Call + ("Shift",CTy"instruction", + Call + ("SLL",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("op2ri",sTy, + TP[LS"sll",Var("rd",FTy 5),Var("rt",FTy 5),Var("imm5",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRL",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("op2ri",sTy, + TP[LS"srl",Var("rd",FTy 5),Var("rt",FTy 5),Var("imm5",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRA",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("op2ri",sTy, + TP[LS"sra",Var("rd",FTy 5),Var("rt",FTy 5),Var("imm5",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLLV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"sllv",Var("rd",FTy 5),Var("rt",FTy 5),Var("rs",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRLV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"srlv",Var("rd",FTy 5),Var("rt",FTy 5),Var("rs",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRAV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"srav",Var("rd",FTy 5),Var("rt",FTy 5),Var("rs",FTy 5)])), + (Call + ("Branch",CTy"instruction", + Call("JR",CTy"Branch",Var("rs",FTy 5))), + Call("op1r",sTy,TP[LS"jr",Var("rs",FTy 5)])), + (Call + ("Branch",CTy"instruction", + Call("JALR",CTy"Branch",TP[Var("rs",FTy 5),Var("rd",FTy 5)])), + Call("op2r",sTy,TP[LS"jalr",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MFHI",CTy"MultDiv",Var("rd",FTy 5))), + Call("op1r",sTy,TP[LS"mfhi",Var("rd",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MTHI",CTy"MultDiv",Var("rd",FTy 5))), + Call("op1r",sTy,TP[LS"mthi",Var("rd",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MFLO",CTy"MultDiv",Var("rs",FTy 5))), + Call("op1r",sTy,TP[LS"mflo",Var("rs",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MTLO",CTy"MultDiv",Var("rs",FTy 5))), + Call("op1r",sTy,TP[LS"mtlo",Var("rs",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSLLV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"dsllv",Var("rd",FTy 5),Var("rt",FTy 5),Var("rs",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRLV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"dsrlv",Var("rd",FTy 5),Var("rt",FTy 5),Var("rs",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRAV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"dsrav",Var("rd",FTy 5),Var("rt",FTy 5),Var("rs",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MADD",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"madd",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MADDU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"maddu",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MSUB",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"msub",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MSUBU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"msubu",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call + ("MUL",CTy"MultDiv", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"mul",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MULT",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"mult",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("MULTU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"multu",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("DIV",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"div",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("DIVU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"divu",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("DMULT",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"dmult",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("DMULTU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"dmultu",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("DDIV",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"ddiv",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("MultDiv",CTy"instruction", + Call("DDIVU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"ddivu",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("MOVN",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"movn",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("MOVZ",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"movz",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("ADD",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"add",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("ADDU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"addu",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SUB",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"sub",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SUBU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"subu",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("AND",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"and",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("OR",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"or",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("XOR",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"xor",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("NOR",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"nor",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SLT",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"slt",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SLTU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"sltu",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("DADD",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"dadd",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("DADDU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"daddu",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("DSUB",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"dsub",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("DSUBU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("op3r",sTy, + TP[LS"dsubu",Var("rd",FTy 5),Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("Trap",CTy"instruction", + Call("TGE",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"tge",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("Trap",CTy"instruction", + Call("TGEU",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"tgeu",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("Trap",CTy"instruction", + Call("TLT",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"tlt",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("Trap",CTy"instruction", + Call("TLTU",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"tltu",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("Trap",CTy"instruction", + Call("TEQ",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"teq",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("Trap",CTy"instruction", + Call("TNE",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call("op2r",sTy,TP[LS"tne",Var("rs",FTy 5),Var("rt",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSLL",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("op2ri",sTy, + TP[LS"dsll",Var("rd",FTy 5),Var("rt",FTy 5),Var("imm5",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRL",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("op2ri",sTy, + TP[LS"dsrl",Var("rd",FTy 5),Var("rt",FTy 5),Var("imm5",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRA",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("op2ri",sTy, + TP[LS"dsra",Var("rd",FTy 5),Var("rt",FTy 5),Var("imm5",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSLL32",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("op2ri",sTy, + TP[LS"dsll32",Var("rd",FTy 5),Var("rt",FTy 5),Var("imm5",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRL32",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("op2ri",sTy, + TP[LS"dsrl32",Var("rd",FTy 5),Var("rt",FTy 5),Var("imm5",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRA32",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("op2ri",sTy, + TP[LS"dsra32",Var("rd",FTy 5),Var("rt",FTy 5),Var("imm5",FTy 5)])), + (Call + ("Branch",CTy"instruction", + Call("BLTZ",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bltz",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGEZ",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bgez",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLTZL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bltzl",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGEZL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bgezl",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TGEI",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"tgei",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TGEIU",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"tgeiu",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TLTI",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"tlti",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TLTIU",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"tltiu",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TEQI",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"teqi",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TNEI",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"tnei",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLTZAL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bltzal",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGEZAL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bgezal",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLTZALL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bltzall",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGEZALL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bgezall",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("J",CTy"Branch",Var("imm",FTy 26))), + Call("op1i",sTy,TP[LS"j",Var("imm",FTy 26)])), + (Call + ("Branch",CTy"instruction", + Call("JAL",CTy"Branch",Var("imm",FTy 26))), + Call("op1i",sTy,TP[LS"jal",Var("imm",FTy 26)])), + (Call + ("CP",CTy"instruction", + Call + ("MFC0",CTy"CP", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + Call + ("op2roi",sTy, + TP[LS"mfc0",Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + (Call + ("CP",CTy"instruction", + Call + ("DMFC0",CTy"CP", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + Call + ("op2roi",sTy, + TP[LS"dmfc0",Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + (Call + ("CP",CTy"instruction", + Call + ("MTC0",CTy"CP", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + Call + ("op2roi",sTy, + TP[LS"mtc0",Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + (Call + ("CP",CTy"instruction", + Call + ("DMTC0",CTy"CP", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + Call + ("op2roi",sTy, + TP[LS"dmtc0",Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + (Call + ("Branch",CTy"instruction", + Call("BEQ",CTy"Branch",TP[LW(0,5),LW(0,5),Var("imm",F16)])), + Call("op1i",sTy,TP[LS"b",Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call + ("BEQ",CTy"Branch", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"beq",Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call + ("BNE",CTy"Branch", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"bne",Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLEZ",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"blez",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGTZ",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bgtz",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"addi",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ADDIU",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"addiu",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("SLTI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"slti",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("SLTIU",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"sltiu",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ANDI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"andi",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ORI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"ori",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("XORI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"xori",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call("LUI",CTy"ArithI",TP[Var("rt",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"lui",Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call + ("BEQL",CTy"Branch", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"beql",Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call + ("BNEL",CTy"Branch", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"bnel",Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLEZL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"blezl",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGTZL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("op1ri",sTy,TP[LS"bgtzl",Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("DADDI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"daddi",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("DADDIU",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("op2ri",sTy, + TP[LS"daddiu",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LDL",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"ldl",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LDR",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"ldr",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LB",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"lb",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LH",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"lh",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LWL",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"lwl",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LW",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"lw",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LBU",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"lbu",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LHU",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"lhu",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LWR",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"lwr",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LWU",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"lwu",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SB",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"sb",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SH",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"sh",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SWL",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"swl",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SW",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"sw",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SDL",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"sdl",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SDR",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"sdr",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SWR",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"swr",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LL",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"ll",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LLD",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"lld",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LD",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"ld",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SC",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"sc",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SCD",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"scd",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SD",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("opmem",sTy, + TP[LS"sd",Var("rt",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Call + ("CACHE",CTy"instruction", + TP[Var("rs",FTy 5),Var("opn",FTy 5),Var("imm",F16)]), + Call + ("opmem",sTy, + TP[LS"cache",Var("opn",FTy 5),Var("rs",FTy 5),Var("imm",F16)])), + (Const("SYSCALL",CTy"instruction"),LS"syscall"), + (Const("BREAK",CTy"instruction"),LS"break"), + (Call("SYNC",CTy"instruction",Var("imm5",FTy 5)), + CC[LS"sync ",Mop(Cast sTy,Var("imm5",FTy 5))]), + (Const("TLBR",CTy"instruction"),LS"tlbr"), + (Const("TLBWI",CTy"instruction"),LS"tlbwi"), + (Const("TLBWR",CTy"instruction"),LS"tlbwr"), + (Const("TLBP",CTy"instruction"),LS"tlbp"), + (Const("ERET",CTy"instruction"),LS"eret"), + (Call("RDHWR",CTy"instruction",TP[Var("rt",FTy 5),Var("rd",FTy 5)]), + Call("op2r",sTy,TP[LS"rdhwr",Var("rt",FTy 5),Var("rd",FTy 5)])), + (Const("WAIT",CTy"instruction"),LS"wait"), + (Call("COP2",CTy"instruction",AVar(CTy"COP2")), + Call("COP2InstructionToString",sTy,Var("i",CTy"instruction"))), + (Call("LWC2",CTy"instruction",AVar(CTy"LWC2")), + Call("LWC2InstructionToString",sTy,Var("i",CTy"instruction"))), + (Call("LDC2",CTy"instruction",AVar(CTy"LDC2")), + Call("LDC2InstructionToString",sTy,Var("i",CTy"instruction"))), + (Call("SWC2",CTy"instruction",AVar(CTy"SWC2")), + Call("SWC2InstructionToString",sTy,Var("i",CTy"instruction"))), + (Call("SDC2",CTy"instruction",AVar(CTy"SDC2")), + Call("SDC2InstructionToString",sTy,Var("i",CTy"instruction"))), + (Const("Unpredictable",CTy"instruction"),LS"???"), + (Const("ReservedInstruction",CTy"instruction"),LS"???")])) +; +val Encode_def = Def + ("Encode",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call + ("Shift",CTy"instruction", + Call + ("SLL",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("form1",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + LW(0,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRL",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("form1",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + LW(2,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRA",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("form1",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + LW(3,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLLV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(4,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRLV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(6,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRAV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(7,6)])), + (Call + ("Branch",CTy"instruction", + Call("JR",CTy"Branch",Var("rs",FTy 5))), + Call + ("form1",F32,TP[Var("rs",FTy 5),LW(0,5),LW(0,5),LW(0,5),LW(8,6)])), + (Call + ("Branch",CTy"instruction", + Call("JALR",CTy"Branch",TP[Var("rs",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),LW(0,5),Var("rd",FTy 5),LW(0,5),LW(9,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MFHI",CTy"MultDiv",Var("rd",FTy 5))), + Call + ("form1",F32, + TP[LW(0,5),LW(0,5),Var("rd",FTy 5),LW(0,5),LW(16,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MTHI",CTy"MultDiv",Var("rs",FTy 5))), + Call + ("form1",F32, + TP[Var("rs",FTy 5),LW(0,5),LW(0,5),LW(0,5),LW(17,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MFLO",CTy"MultDiv",Var("rd",FTy 5))), + Call + ("form1",F32, + TP[LW(0,5),LW(0,5),Var("rd",FTy 5),LW(0,5),LW(18,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MTLO",CTy"MultDiv",Var("rs",FTy 5))), + Call + ("form1",F32, + TP[Var("rs",FTy 5),LW(0,5),LW(0,5),LW(0,5),LW(19,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSLLV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(20,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRLV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(22,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRAV",CTy"Shift", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(23,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MADD",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form5",F32,TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MADDU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form5",F32,TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(1,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MSUB",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form5",F32,TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(4,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MSUBU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form5",F32,TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(5,6)])), + (Call + ("MultDiv",CTy"instruction", + Call + ("MUL",CTy"MultDiv", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form5",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(2,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MULT",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(24,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("MULTU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(25,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("DIV",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(26,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("DIVU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(27,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("DMULT",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(28,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("DMULTU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(29,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("DDIV",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(30,6)])), + (Call + ("MultDiv",CTy"instruction", + Call("DDIVU",CTy"MultDiv",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(31,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("MOVZ",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(10,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("MOVN",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(11,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("ADD",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(32,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("ADDU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(33,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SUB",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(34,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SUBU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(35,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("AND",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(36,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("OR",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(37,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("XOR",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(38,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("NOR",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(39,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SLT",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(42,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SLTU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(43,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("DADD",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(44,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("DADDU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(45,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("DSUB",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(46,6)])), + (Call + ("ArithR",CTy"instruction", + Call + ("DSUBU",CTy"ArithR", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("rd",FTy 5),LW(0,5), + LW(47,6)])), + (Call + ("Trap",CTy"instruction", + Call("TGE",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(48,6)])), + (Call + ("Trap",CTy"instruction", + Call("TGEU",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(49,6)])), + (Call + ("Trap",CTy"instruction", + Call("TLT",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(50,6)])), + (Call + ("Trap",CTy"instruction", + Call("TLTU",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(51,6)])), + (Call + ("Trap",CTy"instruction", + Call("TEQ",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(52,6)])), + (Call + ("Trap",CTy"instruction", + Call("TNE",CTy"Trap",TP[Var("rs",FTy 5),Var("rt",FTy 5)])), + Call + ("form1",F32, + TP[Var("rs",FTy 5),Var("rt",FTy 5),LW(0,5),LW(0,5),LW(54,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSLL",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("form1",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + LW(56,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRL",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("form1",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + LW(58,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRA",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("form1",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + LW(59,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSLL32",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("form1",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + LW(60,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRL32",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("form1",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + LW(62,6)])), + (Call + ("Shift",CTy"instruction", + Call + ("DSRA32",CTy"Shift", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5)])), + Call + ("form1",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("imm5",FTy 5), + LW(63,6)])), + (Call + ("Branch",CTy"instruction", + Call("BLTZ",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(0,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGEZ",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(1,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLTZL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(2,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGEZL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(3,5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TGEI",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(8,5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TGEIU",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(9,5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TLTI",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(10,5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TLTIU",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(11,5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TEQI",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(12,5),Var("imm",F16)])), + (Call + ("Trap",CTy"instruction", + Call("TNEI",CTy"Trap",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(14,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLTZAL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(16,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGEZAL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(17,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLTZALL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(18,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGEZALL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call("form2",F32,TP[Var("rs",FTy 5),LW(19,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("J",CTy"Branch",Var("imm",FTy 26))), + CC[LW(2,6),Var("imm",FTy 26)]), + (Call + ("Branch",CTy"instruction", + Call("JAL",CTy"Branch",Var("imm",FTy 26))), + CC[LW(3,6),Var("imm",FTy 26)]), + (Call + ("CP",CTy"instruction", + Call + ("MFC0",CTy"CP", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + Call + ("form3",F32, + TP[LW(0,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + (Call + ("CP",CTy"instruction", + Call + ("DMFC0",CTy"CP", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + Call + ("form3",F32, + TP[LW(1,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + (Call + ("CP",CTy"instruction", + Call + ("MTC0",CTy"CP", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + Call + ("form3",F32, + TP[LW(4,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + (Call + ("CP",CTy"instruction", + Call + ("DMTC0",CTy"CP", + TP[Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + Call + ("form3",F32, + TP[LW(5,5),Var("rt",FTy 5),Var("rd",FTy 5),Var("sel",FTy 3)])), + (Call + ("Branch",CTy"instruction", + Call + ("BEQ",CTy"Branch", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(4,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call + ("BNE",CTy"Branch", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(5,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLEZ",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call + ("form4",F32,TP[LW(6,6),Var("rs",FTy 5),LW(0,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGTZ",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call + ("form4",F32,TP[LW(7,6),Var("rs",FTy 5),LW(0,5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(8,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ADDIU",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(9,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("SLTI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(10,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("SLTIU",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(11,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ANDI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(12,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ORI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(13,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("XORI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(14,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call("LUI",CTy"ArithI",TP[Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32,TP[LW(15,6),LW(0,5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call + ("BEQL",CTy"Branch", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(20,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call + ("BNEL",CTy"Branch", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(21,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BLEZL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call + ("form4",F32,TP[LW(22,6),Var("rs",FTy 5),LW(0,5),Var("imm",F16)])), + (Call + ("Branch",CTy"instruction", + Call("BGTZL",CTy"Branch",TP[Var("rs",FTy 5),Var("imm",F16)])), + Call + ("form4",F32,TP[LW(23,6),Var("rs",FTy 5),LW(0,5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("DADDI",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(24,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("ArithI",CTy"instruction", + Call + ("DADDIU",CTy"ArithI", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(25,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LDL",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(26,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LDR",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(27,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LB",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(32,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LH",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(33,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LWL",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(34,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LW",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(35,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LBU",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(36,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LHU",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(37,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LWR",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(38,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LWU",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(39,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SB",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(40,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SH",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(41,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SWL",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(42,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SW",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(43,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SDL",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(44,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SDR",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(45,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SWR",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(46,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LL",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(48,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LLD",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(52,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Load",CTy"instruction", + Call + ("LD",CTy"Load", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(55,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SC",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(56,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SCD",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(60,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("Store",CTy"instruction", + Call + ("SD",CTy"Store", + TP[Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + Call + ("form4",F32, + TP[LW(63,6),Var("rs",FTy 5),Var("rt",FTy 5),Var("imm",F16)])), + (Call + ("CACHE",CTy"instruction", + TP[Var("rs",FTy 5),Var("opn",FTy 5),Var("imm",F16)]), + Call + ("form4",F32, + TP[LW(47,6),Var("rs",FTy 5),Var("opn",FTy 5),Var("imm",F16)])), + (Const("SYSCALL",CTy"instruction"),Mop(Cast F32,LW(12,6))), + (Const("BREAK",CTy"instruction"),Mop(Cast F32,LW(13,6))), + (Call("SYNC",CTy"instruction",Var("imm5",FTy 5)), + Mop(Cast F32,CC[Var("imm5",FTy 5),LW(15,6)])), + (Const("TLBR",CTy"instruction"),LW(1107296257,32)), + (Const("TLBWI",CTy"instruction"),LW(1107296258,32)), + (Const("TLBWR",CTy"instruction"),LW(1107296262,32)), + (Const("TLBP",CTy"instruction"),LW(1107296264,32)), + (Const("ERET",CTy"instruction"),LW(1107296280,32)), + (Call("RDHWR",CTy"instruction",TP[Var("rt",FTy 5),Var("rd",FTy 5)]), + Call("form6",F32,TP[Var("rt",FTy 5),Var("rd",FTy 5),LW(59,6)])), + (Const("WAIT",CTy"instruction"),LW(1107296288,32)), + (Call("COP2",CTy"instruction",AVar(CTy"COP2")), + Call("COP2Encode",F32,Var("i",CTy"instruction"))), + (Call("LWC2",CTy"instruction",AVar(CTy"LWC2")), + Call("LWC2Encode",F32,Var("i",CTy"instruction"))), + (Call("LDC2",CTy"instruction",AVar(CTy"LDC2")), + Call("LDC2Encode",F32,Var("i",CTy"instruction"))), + (Call("SWC2",CTy"instruction",AVar(CTy"SWC2")), + Call("SWC2Encode",F32,Var("i",CTy"instruction"))), + (Call("SDC2",CTy"instruction",AVar(CTy"SDC2")), + Call("SDC2Encode",F32,Var("i",CTy"instruction"))), + (Const("Unpredictable",CTy"instruction"),LW(133169152,32)), + (Const("ReservedInstruction",CTy"instruction"),LW(0,32))])) +; +val log_instruction_def = Def + ("log_instruction",TP[Var("w",F32),Var("inst",CTy"instruction")], + Close + (qVar"state", + TP[CC[LS"instr ",Mop(Cast sTy,Dest("procID",F8,qVar"state")),LS" ", + Mop(Cast sTy,Dest("instCnt",nTy,qVar"state")),LS" ", + Call + ("hex64",sTy, + Mop(Fst, + Apply(Const("PC",ATy(qTy,PTy(F64,qTy))),qVar"state"))), + LS" : ",Call("hex32",sTy,Var("w",F32)),LS" ", + Call("instructionToString",sTy,Var("inst",CTy"instruction"))], + qVar"state"])) +; +val Next_def = Def + ("Next",qVar"state", + Let(TP[Var("v",OTy F32),qVar"s"], + Apply + (Const("Fetch",ATy(qTy,PTy(OTy F32,qTy))), + Rupd + ("currentInst", + TP[Mop(Snd, + Apply + (Call("clear_logs",ATy(qTy,PTy(uTy,qTy)),LU), + qVar"state")),LO F32])), + Let(qVar"s",Rupd("currentInst",TP[qVar"s",Var("v",OTy F32)]), + Let(qVar"s", + CS(Dest("currentInst",OTy F32,qVar"s"), + [(Mop(Some,Var("w",F32)), + Let(Var("inst",CTy"instruction"), + Call("Decode",CTy"instruction",Var("w",F32)), + Mop(Snd, + Apply + (Call + ("Run",ATy(qTy,PTy(uTy,qTy)), + Var("inst",CTy"instruction")), + Mop(Snd, + Apply + (Call + ("mark_log",ATy(qTy,PTy(uTy,qTy)), + TP[LN 1, + Mop(Fst, + Apply + (Call + ("log_instruction", + ATy(qTy,PTy(sTy,qTy)), + TP[Var("w",F32), + Var("inst", + CTy"instruction")]), + qVar"s"))]),qVar"s")))))), + (LO F32,qVar"s")]), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'exceptionSignalled", + ATy(qTy,PTy(uTy,qTy)),LF), + CS(TP[Mop(Fst, + Apply + (Const + ("BranchDelay", + ATy(qTy,PTy(OTy F64,qTy))), + qVar"s")), + Mop(Fst, + Apply + (Const + ("BranchTo", + ATy(qTy,PTy(OTy F64,qTy))), + qVar"s")), + Mop(Fst, + Apply + (Const + ("BranchDelayPCC", + ATy(qTy, + PTy(OTy(PTy(F64, + CTy"Capability")), + qTy))),qVar"s")), + Mop(Fst, + Apply + (Const + ("BranchToPCC", + ATy(qTy, + PTy(OTy(PTy(F64, + CTy"Capability")), + qTy))),qVar"s"))], + [(TP[LO F64,LO F64, + LO(PTy(F64,CTy"Capability")), + LO(PTy(F64,CTy"Capability"))], + ITE(Mop(Not, + Mop(Fst, + Apply + (Const + ("exceptionSignalled", + ATy(qTy,PTy(bTy,qTy))), + qVar"s"))), + Mop(Snd, + Apply + (Call + ("write'PC", + ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const + ("PC", + ATy(qTy, + PTy(F64,qTy))), + qVar"s")),LW(4,64))), + qVar"s")),qVar"s")), + (TP[Mop(Some,Var("addr",F64)),LO F64, + LO(PTy(F64,CTy"Capability")), + LO(PTy(F64,CTy"Capability"))], + Mop(Snd, + Apply + (Call + ("write'PC",ATy(qTy,PTy(uTy,qTy)), + Var("addr",F64)), + Mop(Snd, + Apply + (Call + ("write'BranchDelay", + ATy(qTy,PTy(uTy,qTy)), + LO F64),qVar"s"))))), + (TP[LO F64,Mop(Some,Var("addr",F64)), + LO(PTy(F64,CTy"Capability")), + LO(PTy(F64,CTy"Capability"))], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'BranchTo", + ATy(qTy,PTy(uTy,qTy)),LO F64), + Mop(Snd, + Apply + (Call + ("write'BranchDelay", + ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + Var("addr",F64))), + qVar"s")))), + Mop(Snd, + Apply + (Call + ("write'PC", + ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const + ("PC", + ATy(qTy, + PTy(F64,qTy))), + qVar"s")),LW(4,64))), + qVar"s")))), + (TP[LO F64,LO F64, + Mop(Some, + TP[Var("addr",F64), + Var("cap",CTy"Capability")]), + LO(PTy(F64,CTy"Capability"))], + Mop(Snd, + Apply + (Call + ("write'PCC", + ATy(qTy,PTy(uTy,qTy)), + Var("cap",CTy"Capability")), + Mop(Snd, + Apply + (Call + ("write'PC", + ATy(qTy,PTy(uTy,qTy)), + Var("addr",F64)), + Mop(Snd, + Apply + (Call + ("write'BranchDelayPCC", + ATy(qTy, + PTy(uTy,qTy)), + LO(PTy(F64, + CTy"Capability"))), + qVar"s"))))))), + (TP[LO F64,LO F64, + LO(PTy(F64,CTy"Capability")), + Mop(Some, + TP[Var("addr",F64), + Var("cap",CTy"Capability")])], + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'BranchToPCC", + ATy(qTy,PTy(uTy,qTy)), + LO(PTy(F64,CTy"Capability"))), + Mop(Snd, + Apply + (Call + ("write'BranchDelayPCC", + ATy(qTy,PTy(uTy,qTy)), + Mop(Some, + TP[Var("addr",F64), + Var("cap", + CTy"Capability")])), + qVar"s")))), + Mop(Snd, + Apply + (Call + ("write'PC", + ATy(qTy,PTy(uTy,qTy)), + Bop(Add, + Mop(Fst, + Apply + (Const + ("PC", + ATy(qTy, + PTy(F64,qTy))), + qVar"s")),LW(4,64))), + qVar"s")))), + (AVar + (PTy(OTy F64, + PTy(OTy F64, + PTy(OTy(PTy(F64,CTy"Capability")), + OTy(PTy(F64,CTy"Capability")))))), + Mop(Snd, + Apply + (Call + ("raise'exception", + ATy(qTy,PTy(uTy,qTy)), + Call + ("UNPREDICTABLE", + CTy"exception", + LS"Branch follows branch")), + qVar"s")))]))), + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Count", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Bop(Add, + Dest + ("Count",F32, + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s"))), + LW(1,32))])),qVar"s")))))) +; +val hasCP2_def = Def0 ("hasCP2",LT) +; +val COP2Init_def = Def + ("COP2Init",AVar uTy, + Close + (qVar"state", + TP[LU, + Let(Var("s",PTy(CTy"CapCause",qTy)), + TP[Rupd("ExcCode",TP[LX(CTy"CapCause"),LW(0,8)]), + Rupd("TAG",TP[qVar"state",Mop(K1(FTy 35),LF)])], + Let(Var("s",PTy(CTy"CapCause",qTy)), + TP[Rupd + ("RegNum", + TP[Mop(Fst,Var("s",PTy(CTy"CapCause",qTy))),LW(0,8)]), + Mop(Snd,Var("s",PTy(CTy"CapCause",qTy)))], + Let(Var("s",PTy(CTy"Capability",PTy(CTy"CapCause",qTy))), + TP[Rupd("tag",TP[LX(CTy"Capability"),LT]), + Mop(Fst,Var("s",PTy(CTy"CapCause",qTy))), + Mop(Snd, + Apply + (Call + ("write'capcause",ATy(qTy,PTy(uTy,qTy)), + Mop(Fst,Var("s",PTy(CTy"CapCause",qTy)))), + Mop(Snd,Var("s",PTy(CTy"CapCause",qTy)))))], + Let(Var("s", + PTy(CTy"Capability",PTy(CTy"CapCause",qTy))), + TP[Rupd + ("sealed", + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy)))),LF]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy))))], + Let(Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy))), + TP[Rupd + ("offset", + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy)))), + LW(0,64)]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy))))], + Let(Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy))), + TP[Rupd + ("base", + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))),LW(0,64)]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy))))], + Let(Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy))), + TP[Rupd + ("length", + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))), + Mop(BNot,LW(0,64))]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy))))], + Let(Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy))), + TP[Rupd + ("otype", + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))), + LW(0,24)]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy))))], + Let(Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause",qTy))), + TP[Rupd + ("perms", + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))), + Mop(BNot,LW(0,31))]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy))))], + Let(Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy))), + TP[Rupd + ("reserved", + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))), + LW(0,8)]), + Mop(Snd, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy))))], + Mop(Snd, + Mop(Snd, + Mop(Snd, + Apply + (For(TP[LN + 0, + LN + 31, + Close + (nVar"i", + Close + (Var("state", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy))), + TP[LU, + Mop(Fst, + Var("state", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))), + Mop(Fst, + Mop(Snd, + Var("state", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy))))), + Mop(Snd, + Apply + (Call + ("write'CAPR", + ATy(qTy, + PTy(uTy, + qTy)), + TP[Mop(Fst, + Var("state", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))), + Mop(Cast + (FTy 5), + nVar"i")]), + Mop(Snd, + Mop(Snd, + Var("state", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))))))]))]), + TP[Mop(Fst, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))), + Mop(Fst, + Mop(Snd, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy))))), + Mop(Snd, + Apply + (Call + ("write'PCC", + ATy(qTy, + PTy(uTy, + qTy)), + Mop(Fst, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy))))), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(CTy"Capability", + PTy(CTy"CapCause", + qTy)))))))]))))))))))))))])) +; +val initTLB_def = Def + ("initTLB",qVar"state", + Let(TP[Var("r",CTy"TLBEntry"),Var("s1",PTy(CTy"TLBEntry",qTy))], + Let(Var("s",PTy(CTy"TLBEntry",qTy)), + TP[Rupd("R",TP[LX(CTy"TLBEntry"),LW(2,2)]),qVar"state"], + TP[Mop(Fst,Var("s",PTy(CTy"TLBEntry",qTy))), + Var("s",PTy(CTy"TLBEntry",qTy))]), + TP[Var("r",CTy"TLBEntry"),Mop(Snd,Var("s1",PTy(CTy"TLBEntry",qTy)))])) +; +val initMips_def = Def + ("initMips",TP[nVar"pc",nVar"uart"], + Close + (qVar"state", + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"state")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Config", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("M", + TP[Dest + ("Config",CTy"ConfigRegister", + Var("v",CTy"CP0__renamed__")),LT])])), + qVar"state")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0",ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Config", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("BE", + TP[Dest + ("Config", + CTy"ConfigRegister", + Var("v",CTy"CP0__renamed__")), + LT])])),qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy,PTy(CTy"CP0__renamed__",qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0",ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Config", + TP[Var("v",CTy"CP0__renamed__"), + Rupd + ("MT", + TP[Dest + ("Config", + CTy"ConfigRegister", + Var("v", + CTy"CP0__renamed__")), + LW(1,3)])])),qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy,PTy(uTy,qTy)), + Rupd + ("Config", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("AR", + TP[Dest + ("Config", + CTy"ConfigRegister", + Var("v", + CTy"CP0__renamed__")), + LW(0,3)])])), + qVar"s")), + Let(Var("v",CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))),qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy,qTy)), + Rupd + ("Config", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("AT", + TP[Dest + ("Config", + CTy"ConfigRegister", + Var("v", + CTy"CP0__renamed__")), + LW(2,2)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("M", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LT])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("MMUSize", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LW(15, + 6)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("IS", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LW(3, + 3)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("IL", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LW(4, + 3)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("IA", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 3)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("DS", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LW(3, + 3)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("DL", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LW(4, + 3)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("DA", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 3)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("C2", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + Const + ("hasCP2", + bTy)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("MD", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("PCR", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("WR", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("CA", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("EP", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config1", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("FP", + TP[Dest + ("Config1", + CTy"ConfigRegister1", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config2", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("M", + TP[Dest + ("Config2", + CTy"ConfigRegister2", + Var("v", + CTy"CP0__renamed__")), + LT])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config2", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("TU", + TP[Dest + ("Config2", + CTy"ConfigRegister2", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 3)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config2", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("TS", + TP[Dest + ("Config2", + CTy"ConfigRegister2", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 4)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config2", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("TL", + TP[Dest + ("Config2", + CTy"ConfigRegister2", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 4)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config2", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("TA", + TP[Dest + ("Config2", + CTy"ConfigRegister2", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 4)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config2", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("SU", + TP[Dest + ("Config2", + CTy"ConfigRegister2", + Var("v", + CTy"CP0__renamed__")), + LW(3, + 4)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config2", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("SS", + TP[Dest + ("Config2", + CTy"ConfigRegister2", + Var("v", + CTy"CP0__renamed__")), + LW(8, + 4)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config2", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("SL", + TP[Dest + ("Config2", + CTy"ConfigRegister2", + Var("v", + CTy"CP0__renamed__")), + LW(4, + 4)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config2", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("SA", + TP[Dest + ("Config2", + CTy"ConfigRegister2", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 4)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("M", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LT])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("ULRI", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LT])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("DSPP", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("LPA", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("VEIC", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("VInt", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("SP", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("MT", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("SM", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config3", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("TL", + TP[Dest + ("Config3", + CTy"ConfigRegister3", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config6", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("TLBSize", + TP[Dest + ("Config6", + CTy"ConfigRegister6", + Var("v", + CTy"CP0__renamed__")), + LW(143, + 16)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Config6", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("LTLB", + TP[Dest + ("Config6", + CTy"ConfigRegister6", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Status", + TP[Var("v", + CTy"CP0__renamed__"), + Call + ("write'reg'StatusRegister", + CTy"StatusRegister", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 32)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Status", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("BEV", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LT])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Status", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("KSU", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 2)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Status", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("EXL", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Status", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("ERL", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Status", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("KX", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LT])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Status", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("SX", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LT])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Status", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("UX", + TP[Dest + ("Status", + CTy"StatusRegister", + Var("v", + CTy"CP0__renamed__")), + LT])])), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Count", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + LW(0, + 32)])), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Compare", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + LW(0, + 32)])), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("PRId", + TP[Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + LW(1024, + 32)])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Index", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("P", + TP[Dest + ("Index", + CTy"Index", + Var("v", + CTy"CP0__renamed__")), + LF])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Index", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("Index", + TP[Dest + ("Index", + CTy"Index", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 8)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Random", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("Random", + TP[Dest + ("Random", + CTy"Random", + Var("v", + CTy"CP0__renamed__")), + Mop(Cast + F8, + Bop(Sub, + Const + ("TLBEntries", + nTy), + LN + 1))])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("Wired", + TP[Var("v", + CTy"CP0__renamed__"), + Rupd + ("Wired", + TP[Dest + ("Wired", + CTy"Wired", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 8)])])), + qVar"s")), + Let(Var("v", + CTy"CP0__renamed__"), + Mop(Fst, + Apply + (Const + ("CP0", + ATy(qTy, + PTy(CTy"CP0__renamed__", + qTy))), + qVar"s")), + Let(qVar"s", + Mop(Snd, + Apply + (For(TP[LN + 0, + LN + 31, + Close + (nVar"i", + Close + (qVar"state", + Apply + (Call + ("write'gpr", + ATy(qTy, + PTy(uTy, + qTy)), + TP[LW(12297829382473034410, + 64), + Mop(Cast + (FTy 5), + nVar"i")]), + qVar"state")))]), + Rupd + ("done", + TP[Mop(Snd, + Apply + (Call + ("COP2Init", + ATy(qTy, + PTy(uTy, + qTy)), + LU), + Mop(Snd, + Apply + (Call + ("write'PC", + ATy(qTy, + PTy(uTy, + qTy)), + Mop(Cast + F64, + nVar"pc")), + Mop(Snd, + Apply + (Call + ("write'lo", + ATy(qTy, + PTy(uTy, + qTy)), + LO F64), + Mop(Snd, + Apply + (Call + ("write'hi", + ATy(qTy, + PTy(uTy, + qTy)), + LO F64), + Mop(Snd, + Apply + (Call + ("write'LLbit", + ATy(qTy, + PTy(uTy, + qTy)), + LO bTy), + Mop(Snd, + Apply + (Call + ("write'BranchTo", + ATy(qTy, + PTy(uTy, + qTy)), + LO F64), + Mop(Snd, + Apply + (Call + ("write'BranchDelay", + ATy(qTy, + PTy(uTy, + qTy)), + LO F64), + Mop(Snd, + Apply + (For(TP[LN + 0, + LN + 127, + Close + (nVar"i", + Close + (qVar"state", + Apply + (Call + ("write'TLB_assoc", + ATy(qTy, + PTy(uTy, + qTy)), + TP[Mop(Fst, + Apply + (Const + ("initTLB", + ATy(qTy, + PTy(CTy"TLBEntry", + qTy))), + qVar"state")), + Mop(Cast + F4, + nVar"i")]), + qVar"state")))]), + Mop(Snd, + Apply + (Call + ("write'CP0", + ATy(qTy, + PTy(uTy, + qTy)), + Rupd + ("HWREna", + TP[Var("v", + CTy"CP0__renamed__"), + Call + ("write'reg'HWREna", + CTy"HWREna", + TP[Dest + ("HWREna", + CTy"HWREna", + Var("v", + CTy"CP0__renamed__")), + LW(0, + 32)])])), + qVar"s")))))))))))))))))), + LF]))), + Let(qVar"s", + Mop(Snd, + Apply + (Call + ("PIC_initialise", + ATy(qTy, + PTy(uTy, + qTy)), + Bop(Add, + LN + 2139111424, + Bop(Mul, + Mop(Cast + nTy, + Dest + ("procID", + F8, + qVar"s")), + LN + 16384))), + qVar"s")), + ITE(EQ(Dest + ("procID", + F8, + qVar"s"), + LW(0, + 8)), + Apply + (Const + ("InitMEM", + ATy(qTy, + PTy(uTy, + qTy))), + Mop(Snd, + Apply + (Call + ("JTAG_UART_initialise", + ATy(qTy, + PTy(uTy, + qTy)), + nVar"uart"), + qVar"s"))), + TP[LU, + qVar"s"]))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) + +val () = Import.finish 1 \ No newline at end of file From b8492ebdb874d0e330405033cb4cda411ad7de19 Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Thu, 27 Nov 2014 15:20:05 +0000 Subject: [PATCH 034/718] Add support for MIPS instructions SC and SCD. --- .../mips/prog/mips_progLib.sml | 2 + .../mips/step/mips_stepLib.sml | 16 +++++- .../mips/step/mips_stepScript.sml | 49 +++++++++++++++++++ 3 files changed, 66 insertions(+), 1 deletion(-) diff --git a/examples/l3-machine-code/mips/prog/mips_progLib.sml b/examples/l3-machine-code/mips/prog/mips_progLib.sml index 43c5ef05c4..f4948d5a4e 100644 --- a/examples/l3-machine-code/mips/prog/mips_progLib.sml +++ b/examples/l3-machine-code/mips/prog/mips_progLib.sml @@ -96,6 +96,8 @@ val state_id = ["CP0", "PC", "gpr", "hi", "lo"], ["CP0", "LLbit", "MEM", "PC"], ["CP0", "MEM", "PC"], + ["CP0", "MEM", "PC", "exceptionSignalled", "gpr"], + ["MEM", "PC", "exceptionSignalled", "gpr"], ["MEM", "PC"], ["gpr", "hi", "lo"], ["gpr"]] diff --git a/examples/l3-machine-code/mips/step/mips_stepLib.sml b/examples/l3-machine-code/mips/step/mips_stepLib.sml index b0713f8515..a3cffe53e3 100644 --- a/examples/l3-machine-code/mips/step/mips_stepLib.sml +++ b/examples/l3-machine-code/mips/step/mips_stepLib.sml @@ -95,7 +95,7 @@ fun mips_thms thms = val COND_UPDATE_CONV = REWRITE_CONV (utilsLib.mk_cond_update_thms [``:mips_state``, ``:CP0``, ``:StatusRegister``]) - THENC REWRITE_CONV (mips_thms []) + THENC REWRITE_CONV (mips_stepTheory.cond_update_memory :: mips_thms []) val COND_UPDATE_RULE = Conv.CONV_RULE COND_UPDATE_CONV @@ -491,6 +491,18 @@ val SD = EVR (store_rule []) (dfn'SD_def :: mem_thms) dmemcntxts [] ``dfn'SD (base, rt, offset)`` +val sc = List.map (fn l => ``^st.LLbit = SOME llbit`` :: l) + +val SC = + EVR (COND_UPDATE_RULE o store_rule [bit_1_0_2_0, bit_1_0_2_0_4]) + ([dfn'SC_def, extract_word] @ mem_thms) (sc memcntxts) [] + ``dfn'SC (base, rt, offset)`` + +val SCD = + EVR (COND_UPDATE_RULE o store_rule []) + ([dfn'SCD_def, extract_word] @ mem_thms) (sc dmemcntxts) [] + ``dfn'SCD (base, rt, offset)`` + (* ------------------------------------------------------------------------- *) (* Coprocessor instructions *) @@ -725,6 +737,8 @@ val mips_patterns = List.map (I ## utilsLib.pattern) ("LL", "TTFFFF__________________________"), ("LLD", "TTFTFF__________________________"), ("LD", "TTFTTT__________________________"), + ("SC", "TTTFFF__________________________"), + ("SCD", "TTTTFF__________________________"), ("SD", "TTTTTT__________________________"), ("ERET", "FTFFFFTFFFFFFFFFFFFFFFFFFFFTTFFF") ] diff --git a/examples/l3-machine-code/mips/step/mips_stepScript.sml b/examples/l3-machine-code/mips/step/mips_stepScript.sml index cc724a826e..97a006b238 100644 --- a/examples/l3-machine-code/mips/step/mips_stepScript.sml +++ b/examples/l3-machine-code/mips/step/mips_stepScript.sml @@ -542,6 +542,55 @@ val StoreMemory_doubleword = Q.store_thm("StoreMemory_doubleword", (* ------------------------------------------------------------------------ *) +val cond_update_memory = Q.store_thm("cond_update_memory", + `(!a: word64 b x0 x1 x2 x3 m. + (if b then + (a =+ x0) ((a + 1w =+ x1) ((a + 2w =+ x2) ((a + 3w =+ x3) m))) + else m) = + (a =+ (if b then x0 else m a)) + ((a + 1w =+ (if b then x1 else m (a + 1w))) + ((a + 2w =+ (if b then x2 else m (a + 2w))) + ((a + 3w =+ (if b then x3 else m (a + 3w))) m)))) /\ + (!a: word64 b x0 x1 x2 x3 m. + (if b then + (a + 3w =+ x0) ((a + 2w =+ x1) ((a + 1w =+ x2) ((a =+ x3) m))) + else m) = + (a + 3w =+ (if b then x0 else m (a + 3w))) + ((a + 2w =+ (if b then x1 else m (a + 2w))) + ((a + 1w =+ (if b then x2 else m (a + 1w))) + ((a =+ (if b then x3 else m a)) m)))) /\ + (!a: word64 b x0 x1 x2 x3 x4 x5 x6 x7 m. + (if b then + (a =+ x0) ((a + 1w =+ x1) ((a + 2w =+ x2) ((a + 3w =+ x3) + ((a + 4w =+ x4) ((a + 5w =+ x5) ((a + 6w =+ x6) + ((a + 7w =+ x7) m))))))) + else m) = + (a =+ (if b then x0 else m a)) + ((a + 1w =+ (if b then x1 else m (a + 1w))) + ((a + 2w =+ (if b then x2 else m (a + 2w))) + ((a + 3w =+ (if b then x3 else m (a + 3w))) + ((a + 4w =+ (if b then x4 else m (a + 4w))) + ((a + 5w =+ (if b then x5 else m (a + 5w))) + ((a + 6w =+ (if b then x6 else m (a + 6w))) + ((a + 7w =+ (if b then x7 else m (a + 7w))) m)))))))) /\ + (!a: word64 b x0 x1 x2 x3 x4 x5 x6 x7 m. + (if b then + (a + 7w =+ x0) ((a + 6w =+ x1) ((a + 5w =+ x2) ((a + 4w =+ x3) + ((a + 3w =+ x4) ((a + 2w =+ x5) ((a + 1w =+ x6) ((a =+ x7) m))))))) + else m) = + (a + 7w =+ (if b then x0 else m (a + 7w))) + ((a + 6w =+ (if b then x1 else m (a + 6w))) + ((a + 5w =+ (if b then x2 else m (a + 5w))) + ((a + 4w =+ (if b then x3 else m (a + 4w))) + ((a + 3w =+ (if b then x4 else m (a + 3w))) + ((a + 2w =+ (if b then x5 else m (a + 2w))) + ((a + 1w =+ (if b then x6 else m (a + 1w))) + ((a =+ (if b then x7 else m a)) m))))))))`, + rw [combinTheory.UPDATE_def, FUN_EQ_THM] + ) + +(* ------------------------------------------------------------------------ *) + val branch_delay = Q.store_thm("branch_delay", `(!b x y. (case (if b then (F, x) else (T, y)) of From 88a392b2177a0b3aa3fd20540706955a4b803be5 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Thu, 27 Nov 2014 15:20:16 +0000 Subject: [PATCH 035/718] Fix optionSyntax.is_is_some --- src/option/optionSyntax.sml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/option/optionSyntax.sml b/src/option/optionSyntax.sml index d45f14bed3..1913fb2955 100644 --- a/src/option/optionSyntax.sml +++ b/src/option/optionSyntax.sml @@ -101,7 +101,7 @@ val is_none = can dest_none val is_some = can dest_some val is_the = can dest_the val is_is_none = can dest_is_none -val is_is_some = can dest_is_none +val is_is_some = can dest_is_some val is_option_map = can dest_option_map val is_option_join = can dest_option_join val is_option_case = can dest_option_case From 8230d99eb54a5e3da0c5e5e896cd27be25a713a7 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Sat, 29 Nov 2014 18:21:40 +1100 Subject: [PATCH 036/718] some new doc files to do with list_tactics --- help/Docfiles/Tactical.ALLGOALS.doc | 27 +++++++++++++ help/Docfiles/Tactical.ALL_LT.doc | 27 +++++++++++++ help/Docfiles/Tactical.HEADGOAL.doc | 33 ++++++++++++++++ help/Docfiles/Tactical.LASTGOAL.doc | 33 ++++++++++++++++ help/Docfiles/Tactical.NTH_GOAL.doc | 35 +++++++++++++++++ help/Docfiles/Tactical.REVERSE_LT.doc | 24 ++++++++++++ help/Docfiles/Tactical.ROTATE_LT.doc | 33 ++++++++++++++++ help/Docfiles/Tactical.SPLIT_LT.doc | 35 +++++++++++++++++ help/Docfiles/Tactical.TACS_TO_LT.doc | 33 ++++++++++++++++ help/Docfiles/Tactical.THEN_LT.doc | 55 +++++++++++++++++++++++++++ src/1/Tactical.sml | 3 +- 11 files changed, 337 insertions(+), 1 deletion(-) create mode 100644 help/Docfiles/Tactical.ALLGOALS.doc create mode 100644 help/Docfiles/Tactical.ALL_LT.doc create mode 100644 help/Docfiles/Tactical.HEADGOAL.doc create mode 100644 help/Docfiles/Tactical.LASTGOAL.doc create mode 100644 help/Docfiles/Tactical.NTH_GOAL.doc create mode 100644 help/Docfiles/Tactical.REVERSE_LT.doc create mode 100644 help/Docfiles/Tactical.ROTATE_LT.doc create mode 100644 help/Docfiles/Tactical.SPLIT_LT.doc create mode 100644 help/Docfiles/Tactical.TACS_TO_LT.doc create mode 100644 help/Docfiles/Tactical.THEN_LT.doc diff --git a/help/Docfiles/Tactical.ALLGOALS.doc b/help/Docfiles/Tactical.ALLGOALS.doc new file mode 100644 index 0000000000..66f6dba6ff --- /dev/null +++ b/help/Docfiles/Tactical.ALLGOALS.doc @@ -0,0 +1,27 @@ +\DOC ALLGOALS + +\TYPE {ALLGOALS : tactic -> list_tactic} + +\SYNOPSIS +Applies a tactic to every goal in a list + +\KEYWORDS +tactical, list_tactic. + +\DESCRIBE +If {tac} is a tactic, {ALLGOALS tac} is a list_tactic which +applies the tactic {tac} to all the goals in the given list. + +\FAILURE +The application of {ALLGOALS} to a tactic never fails. +The resulting list_tactic fails if +{tac} fails when applied to any of the goals in the given list. + +\EXAMPLE +Where {tac1} and {tac2} are tactics, +{tac1 THEN_LT ALLGOALS tac2} is equivalent to {tac1 THEN tac2} + +\SEEALSO +Tactical.THEN_LT, Tactical.THEN +\ENDDOC + diff --git a/help/Docfiles/Tactical.ALL_LT.doc b/help/Docfiles/Tactical.ALL_LT.doc new file mode 100644 index 0000000000..b7475a5ced --- /dev/null +++ b/help/Docfiles/Tactical.ALL_LT.doc @@ -0,0 +1,27 @@ +\DOC ALL_LT + +\TYPE {ALL_LT : list_tactic} + +\SYNOPSIS +Passes on a goal list unchanged. + +\KEYWORDS +list_tactic, identity. + +\DESCRIBE +{ALL_LT} applied to a goal list {gl} +simply produces the goal list {gl}. It is +the identity for the {THEN_LT} tactical. + +\FAILURE +Never fails. + +\EXAMPLE +To apply tactic {tac1} to a goal, and then to apply {tac2} +to all resulting subgoals except the first, use +{ + tac1 THEN_LT SPLIT_LT 1 (ALL_LT, ALLGOALS tac2) +} +\SEEALSO +Tactical.THEN_LT, Tactical.SPLIT_LT, Tactical.ALLGOALS +\ENDDOC diff --git a/help/Docfiles/Tactical.HEADGOAL.doc b/help/Docfiles/Tactical.HEADGOAL.doc new file mode 100644 index 0000000000..8460e4a075 --- /dev/null +++ b/help/Docfiles/Tactical.HEADGOAL.doc @@ -0,0 +1,33 @@ +\DOC HEADGOAL + +\TYPE {HEADGOAL : tactic -> list_tactic} + +\SYNOPSIS +The list_tactic which applies a tactic to the first member of a list of goals. + +\KEYWORDS +tactical. + +\DESCRIBE +If {tac} is a tactic, {HEADGOAL tac} is a +list_tactic which applies the tactic {tac} to the +first member of a list of goals. + +\FAILURE +The application of {HEADGOAL} to a tactic never fails. +The resulting list_tactic fails the goal list is empty or +or finally if {tac} fails when applied to the first member of the goal list. + +\USES +Applying a tactic to the first subgoal. + +\EXAMPLE +Where {tac1} and {tac2} are tactics, {tac1 THEN_LT HEADGOAL tac2} +applies {tac1} to a goal, and then applies {tac2} to the first resulting +subgoal. + +\SEEALSO +Tactical.THEN_LT, Tactical.NTH_GOAL, Tactical.THEN1, Tactical.LASTGOAL. +\ENDDOC + + diff --git a/help/Docfiles/Tactical.LASTGOAL.doc b/help/Docfiles/Tactical.LASTGOAL.doc new file mode 100644 index 0000000000..65e6367540 --- /dev/null +++ b/help/Docfiles/Tactical.LASTGOAL.doc @@ -0,0 +1,33 @@ +\DOC LASTGOAL + +\TYPE {LASTGOAL : tactic -> list_tactic} + +\SYNOPSIS +The list_tactic which applies a tactic to the last member of a list of goals. + +\KEYWORDS +tactical. + +\DESCRIBE +If {tac} is a tactic, {LASTGOAL tac} is a +list_tactic which applies the tactic {tac} to the +last member of a list of goals. + +\FAILURE +The application of {LASTGOAL} to a tactic never fails. +The resulting list_tactic fails the goal list is empty or +or finally if {tac} fails when applied to the last member of the goal list. + +\USES +Applying a tactic to the last subgoal. + +\EXAMPLE +Where {tac1} and {tac2} are tactics, {tac1 THEN_LT LASTGOAL tac2} +applies {tac1} to a goal, and then applies {tac2} to the last resulting +subgoal. + +\SEEALSO +Tactical.THEN_LT, Tactical.NTH_GOAL, Tactical.HEADGOAL. +\ENDDOC + + diff --git a/help/Docfiles/Tactical.NTH_GOAL.doc b/help/Docfiles/Tactical.NTH_GOAL.doc new file mode 100644 index 0000000000..3e525ac04f --- /dev/null +++ b/help/Docfiles/Tactical.NTH_GOAL.doc @@ -0,0 +1,35 @@ +\DOC NTH_GOAL + +\TYPE {NTH_GOAL : tactic -> int -> list_tactic} + +\SYNOPSIS +The list_tactic which applies a tactic to the +{n}'th member of a list of goals. + +\KEYWORDS +tactical. + +\DESCRIBE +If {tac} is a tactic, {NTH_GOAL n tac} is a +list_tactic which applies the tactic {tac} to the +{n}'th member of a list of goals. + +\FAILURE +The application of {NTH_GOAL} to a tactic and integer never fails. +The resulting list_tactic fails if {n} is less than 1 or greater than the +length of the goal list, +or finally if {tac} fails when applied to the {n}'th member of the goal list. + +\USES +Applying a tactic to a particular subgoal. + +\EXAMPLE +Where {tac1} and {tac2} are tactics, {tac1 THEN_LT NTH_GOAL n tac2} +applies {tac1} to a goal, and then applies {tac2} to the {n}'th resulting +subgoal. + +\SEEALSO +Tactical.THEN_LT, Tactical.THEN1, Tactical.HEADGOAL, Tactical.LASTGOAL. +\ENDDOC + + diff --git a/help/Docfiles/Tactical.REVERSE_LT.doc b/help/Docfiles/Tactical.REVERSE_LT.doc new file mode 100644 index 0000000000..db94a2b606 --- /dev/null +++ b/help/Docfiles/Tactical.REVERSE_LT.doc @@ -0,0 +1,24 @@ +\DOC REVERSE_LT + +\TYPE {REVERSE_LT : list_tactic} + +\SYNOPSIS +Reverses the order of a list of subgoals. + +\KEYWORDS +list_tactic. + +\DESCRIBE +The list_tactic {REVERSE_LT} reverses +the order of a list of subgoals. + +\FAILURE +Never fails. + +\EXAMPLE +Where {tac} is a tactic, +{tac THEN_LT REVERSE_LT} is equivalent to {REVERSE tac} + +\SEEALSO +Tactical.THEN_LT, Tactical.REVERSE, Tactical.ROTATE_LT +\ENDDOC diff --git a/help/Docfiles/Tactical.ROTATE_LT.doc b/help/Docfiles/Tactical.ROTATE_LT.doc new file mode 100644 index 0000000000..72a57ca89e --- /dev/null +++ b/help/Docfiles/Tactical.ROTATE_LT.doc @@ -0,0 +1,33 @@ +\DOC ROTATE_LT + +\TYPE {ROTATE_LT : int -> list_tactic} + +\SYNOPSIS +Rotates a list of goals + +\KEYWORDS +list_tactic. + +\DESCRIBE +{ROTATE_LT n gl} rotates a goal list {gl} by {n} places. +For {n >= 0}, this means moving the first {n} goals to the end of the list. +A negative {n} means rotating the list in the opposite direction. + +\FAILURE +Never fails. + +\EXAMPLE +To bring the third goal to first position, leaving the others in order, use +{ + SPLIT_LT 3 (ROTATE_LT ~1, ALL_LT) +} + +\COMMENTS +Using {SPLIT_LT}, {ROTATE_LT} and {REVERSE_LT}, +any reordering of a list of goals is possible. + +\SEEALSO +proofManagerLib.rotate, proofManagerLib.r, +Tactical.SPLIT_LT, Tactical.REVERSE_LT, Tactical.ALL_LT +\ENDDOC + diff --git a/help/Docfiles/Tactical.SPLIT_LT.doc b/help/Docfiles/Tactical.SPLIT_LT.doc new file mode 100644 index 0000000000..3c2896772d --- /dev/null +++ b/help/Docfiles/Tactical.SPLIT_LT.doc @@ -0,0 +1,35 @@ +\DOC SPLIT_LT + +\TYPE {SPLIT_LT : int -> list_tactic * list_tactic -> list_tactic} + +\SYNOPSIS +Splits a list of goals into two and applies a list_tactic to each part + +\KEYWORDS +list_tactic. + +\DESCRIBE +For list_tactics {ltac1} and {ltac2}, integer {n} and goal list {gl}, +the application {SPLIT_LT n (ltac1, ltac2) gl} +applies {ltac1} to the first {n} goals in {gl}, and {ltac2} to the remainder. +If {n} is negative, {ltac1} is applied to the goals before the last {-n}, +and {ltac2} to the last {-n} goals. + +\FAILURE +The application {SPLIT_LT n (ltac1, ltac2)} never fails, +but when applied to a goal list, +it fails if the index {n} is (in absolute value) +larger then the length of the list, +or if either of the list_tactics {ltac1} and {ltac2} fails. + +\EXAMPLE +To apply tactic {tac1} to a goal, and then to apply {tac2} +to all resulting subgoals except the first, use +{ + tac1 THEN_LT SPLIT_LT 1 (ALL_LT, ALLGOALS tac2) +} + +\SEEALSO +Tactical.THEN_LT, Tactical.ALL_LT, Tactical.ALLGOALS +\ENDDOC + diff --git a/help/Docfiles/Tactical.TACS_TO_LT.doc b/help/Docfiles/Tactical.TACS_TO_LT.doc new file mode 100644 index 0000000000..06565d1076 --- /dev/null +++ b/help/Docfiles/Tactical.TACS_TO_LT.doc @@ -0,0 +1,33 @@ +\DOC TACS_TO_LT + +\TYPE {TACS_TO_LT : tactic list -> list_tactic} + +\SYNOPSIS +The list_tactic which applies a list of tactics to the +corresponding members of a list of goals. + +\KEYWORDS +tactical. + +\DESCRIBE +If {T1,...,Tn} are tactics, {TACS_TO_LT [T1,...,Tn]} is a +list_tactic which applies the tactics {T1,...,Tn} to the +corresponding goals. + +\FAILURE +The application of {TACS_TO_LT} to a tactic list never fails. +The resulting list_tactic fails if length of the goal list +is not the same as that of the tactic list, +or finally if {Ti} fails when applied to the {i}'th member of the goal list. + +\USES +Applying different tactics to different subgoals. + +\EXAMPLE +Where {tac1} is a tactic and {tacs2} is a list of tactics, +{tac1 THEN_LT TACS_TO_LT tacs2} is equivalent to {tac1 THENL tacs2} + +\SEEALSO +Tactical.THEN_LT, Tactical.THENL. +\ENDDOC + diff --git a/help/Docfiles/Tactical.THEN_LT.doc b/help/Docfiles/Tactical.THEN_LT.doc new file mode 100644 index 0000000000..6c166b2b4d --- /dev/null +++ b/help/Docfiles/Tactical.THEN_LT.doc @@ -0,0 +1,55 @@ +\DOC THEN_LT + +\TYPE {op THEN_LT : tactic -> list_tactic -> tactic +op THEN_LT : list_tactic -> list_tactic -> list_tactic} + +\SYNOPSIS +Applies a list_tactic to the corresponding subgoals generated by a tactic +or by a previous list_tactic. + +\KEYWORDS +tactical, list_tactic. + +\DESCRIBE +If {tac} is a tactic and {ltac} is a list_tactic, +then {tac THEN_LT ltac} is a tactic which applies +{tac} to a goal, and if it does not fail, +applies the list_tactic {ltac} to the +resulting list of subgoals. + +If {ltac1} and {ltac2} are list_tactics, +then {ltac1 THEN_LT ltac2} is a list_tactic which applies +{ltac1} to a goal list, and if it does not fail, +applies {ltac2} to the resulting list of goals. + +\FAILURE +The application of {THEN_LT} to a tactic or list_tactic and a list_tactic +never fails. + +The tactic {tac THEN_LT ltac} fails +if {tac} fails when applied to the goal, +or if {ltac} fails when applied to the resulting subgoal list. + +The list_tactic {ltac1 THEN_LT ltac2} fails +if {ltac1} fails when applied to the goal list, +or if {ltac2} fails when applied to the goal list result of {ltac1}. + +\USES +Applying a combination of tactics to a list of subgoals, +or otherwise manipulating a list of subgoals. + +\EXAMPLE +Where {tac1} and {tac2} are tactics, +{tac1 THEN_LT ALLGOALS tac2} is equivalent to {tac1 THEN tac2} + +Where {tac1} is a tactic and {tacs2} is a list of tactics, +{tac1 THEN_LT TACS_TO_LT tacs2} is equivalent to {tac1 THENL tacs2} + +Where {tac} is a tactic, +{tac THEN_LT REVERSE_LT} is equivalent to {REVERSE tac} + +\SEEALSO +Tactical.ALLGOALS, Tactical.THEN, Tactical.TACS_TO_LT, Tactical.THENL, +Tactical.NTH_GOAL, Tactical.REVERSE_LT, Tactical.REVERSE +\ENDDOC + diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index 1bb7376990..8ebc1c8b55 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -285,7 +285,8 @@ fun HEADGOAL tac gl1 = NTH_GOAL tac 1 gl1 ; first n goals, and ltacb to the rest *---------------------------------------------------------------------------*) fun SPLIT_LT n (ltaca, ltacb) gl = - let val (gla, glb) = Lib.split_after n gl ; + let val fixn = if n >= 0 then n else length gl + n ; + val (gla, glb) = Lib.split_after fixn gl ; val (glra, vfa) = ltaca gla ; val (glrb, vfb) = ltacb glb ; fun vf ths = From 8a8d11a3b1e30067541abeb6a61d722fb9cb66c2 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Mon, 1 Dec 2014 17:10:02 +1100 Subject: [PATCH 037/718] changed list_tactic to list-tactic in doc files, where not the ML type --- help/Docfiles/Tactical.ALLGOALS.doc | 6 +++--- help/Docfiles/Tactical.ALL_LT.doc | 2 +- help/Docfiles/Tactical.HEADGOAL.doc | 6 +++--- help/Docfiles/Tactical.LASTGOAL.doc | 6 +++--- help/Docfiles/Tactical.NTH_GOAL.doc | 6 +++--- help/Docfiles/Tactical.REVERSE_LT.doc | 4 ++-- help/Docfiles/Tactical.ROTATE_LT.doc | 2 +- help/Docfiles/Tactical.SPLIT_LT.doc | 8 ++++---- help/Docfiles/Tactical.TACS_TO_LT.doc | 6 +++--- help/Docfiles/Tactical.THEN_LT.doc | 18 +++++++++--------- 10 files changed, 32 insertions(+), 32 deletions(-) diff --git a/help/Docfiles/Tactical.ALLGOALS.doc b/help/Docfiles/Tactical.ALLGOALS.doc index 66f6dba6ff..e9b0430ebb 100644 --- a/help/Docfiles/Tactical.ALLGOALS.doc +++ b/help/Docfiles/Tactical.ALLGOALS.doc @@ -6,15 +6,15 @@ Applies a tactic to every goal in a list \KEYWORDS -tactical, list_tactic. +tactical, list-tactic. \DESCRIBE -If {tac} is a tactic, {ALLGOALS tac} is a list_tactic which +If {tac} is a tactic, {ALLGOALS tac} is a list-tactic which applies the tactic {tac} to all the goals in the given list. \FAILURE The application of {ALLGOALS} to a tactic never fails. -The resulting list_tactic fails if +The resulting list-tactic fails if {tac} fails when applied to any of the goals in the given list. \EXAMPLE diff --git a/help/Docfiles/Tactical.ALL_LT.doc b/help/Docfiles/Tactical.ALL_LT.doc index b7475a5ced..1656431c22 100644 --- a/help/Docfiles/Tactical.ALL_LT.doc +++ b/help/Docfiles/Tactical.ALL_LT.doc @@ -6,7 +6,7 @@ Passes on a goal list unchanged. \KEYWORDS -list_tactic, identity. +list-tactic, identity. \DESCRIBE {ALL_LT} applied to a goal list {gl} diff --git a/help/Docfiles/Tactical.HEADGOAL.doc b/help/Docfiles/Tactical.HEADGOAL.doc index 8460e4a075..54cecbf2eb 100644 --- a/help/Docfiles/Tactical.HEADGOAL.doc +++ b/help/Docfiles/Tactical.HEADGOAL.doc @@ -3,19 +3,19 @@ \TYPE {HEADGOAL : tactic -> list_tactic} \SYNOPSIS -The list_tactic which applies a tactic to the first member of a list of goals. +The list-tactic which applies a tactic to the first member of a list of goals. \KEYWORDS tactical. \DESCRIBE If {tac} is a tactic, {HEADGOAL tac} is a -list_tactic which applies the tactic {tac} to the +list-tactic which applies the tactic {tac} to the first member of a list of goals. \FAILURE The application of {HEADGOAL} to a tactic never fails. -The resulting list_tactic fails the goal list is empty or +The resulting list-tactic fails the goal list is empty or or finally if {tac} fails when applied to the first member of the goal list. \USES diff --git a/help/Docfiles/Tactical.LASTGOAL.doc b/help/Docfiles/Tactical.LASTGOAL.doc index 65e6367540..0da1328341 100644 --- a/help/Docfiles/Tactical.LASTGOAL.doc +++ b/help/Docfiles/Tactical.LASTGOAL.doc @@ -3,19 +3,19 @@ \TYPE {LASTGOAL : tactic -> list_tactic} \SYNOPSIS -The list_tactic which applies a tactic to the last member of a list of goals. +The list-tactic which applies a tactic to the last member of a list of goals. \KEYWORDS tactical. \DESCRIBE If {tac} is a tactic, {LASTGOAL tac} is a -list_tactic which applies the tactic {tac} to the +list-tactic which applies the tactic {tac} to the last member of a list of goals. \FAILURE The application of {LASTGOAL} to a tactic never fails. -The resulting list_tactic fails the goal list is empty or +The resulting list-tactic fails the goal list is empty or or finally if {tac} fails when applied to the last member of the goal list. \USES diff --git a/help/Docfiles/Tactical.NTH_GOAL.doc b/help/Docfiles/Tactical.NTH_GOAL.doc index 3e525ac04f..5dc7a85005 100644 --- a/help/Docfiles/Tactical.NTH_GOAL.doc +++ b/help/Docfiles/Tactical.NTH_GOAL.doc @@ -3,7 +3,7 @@ \TYPE {NTH_GOAL : tactic -> int -> list_tactic} \SYNOPSIS -The list_tactic which applies a tactic to the +The list-tactic which applies a tactic to the {n}'th member of a list of goals. \KEYWORDS @@ -11,12 +11,12 @@ tactical. \DESCRIBE If {tac} is a tactic, {NTH_GOAL n tac} is a -list_tactic which applies the tactic {tac} to the +list-tactic which applies the tactic {tac} to the {n}'th member of a list of goals. \FAILURE The application of {NTH_GOAL} to a tactic and integer never fails. -The resulting list_tactic fails if {n} is less than 1 or greater than the +The resulting list-tactic fails if {n} is less than 1 or greater than the length of the goal list, or finally if {tac} fails when applied to the {n}'th member of the goal list. diff --git a/help/Docfiles/Tactical.REVERSE_LT.doc b/help/Docfiles/Tactical.REVERSE_LT.doc index db94a2b606..08f8abdb63 100644 --- a/help/Docfiles/Tactical.REVERSE_LT.doc +++ b/help/Docfiles/Tactical.REVERSE_LT.doc @@ -6,10 +6,10 @@ Reverses the order of a list of subgoals. \KEYWORDS -list_tactic. +list-tactic. \DESCRIBE -The list_tactic {REVERSE_LT} reverses +The list-tactic {REVERSE_LT} reverses the order of a list of subgoals. \FAILURE diff --git a/help/Docfiles/Tactical.ROTATE_LT.doc b/help/Docfiles/Tactical.ROTATE_LT.doc index 72a57ca89e..7c721d7605 100644 --- a/help/Docfiles/Tactical.ROTATE_LT.doc +++ b/help/Docfiles/Tactical.ROTATE_LT.doc @@ -6,7 +6,7 @@ Rotates a list of goals \KEYWORDS -list_tactic. +list-tactic. \DESCRIBE {ROTATE_LT n gl} rotates a goal list {gl} by {n} places. diff --git a/help/Docfiles/Tactical.SPLIT_LT.doc b/help/Docfiles/Tactical.SPLIT_LT.doc index 3c2896772d..4414b086f2 100644 --- a/help/Docfiles/Tactical.SPLIT_LT.doc +++ b/help/Docfiles/Tactical.SPLIT_LT.doc @@ -3,13 +3,13 @@ \TYPE {SPLIT_LT : int -> list_tactic * list_tactic -> list_tactic} \SYNOPSIS -Splits a list of goals into two and applies a list_tactic to each part +Splits a list of goals into two and applies a list-tactic to each part \KEYWORDS -list_tactic. +list-tactic. \DESCRIBE -For list_tactics {ltac1} and {ltac2}, integer {n} and goal list {gl}, +For list-tactics {ltac1} and {ltac2}, integer {n} and goal list {gl}, the application {SPLIT_LT n (ltac1, ltac2) gl} applies {ltac1} to the first {n} goals in {gl}, and {ltac2} to the remainder. If {n} is negative, {ltac1} is applied to the goals before the last {-n}, @@ -20,7 +20,7 @@ The application {SPLIT_LT n (ltac1, ltac2)} never fails, but when applied to a goal list, it fails if the index {n} is (in absolute value) larger then the length of the list, -or if either of the list_tactics {ltac1} and {ltac2} fails. +or if either of the list-tactics {ltac1} and {ltac2} fails. \EXAMPLE To apply tactic {tac1} to a goal, and then to apply {tac2} diff --git a/help/Docfiles/Tactical.TACS_TO_LT.doc b/help/Docfiles/Tactical.TACS_TO_LT.doc index 06565d1076..59fd4c7e12 100644 --- a/help/Docfiles/Tactical.TACS_TO_LT.doc +++ b/help/Docfiles/Tactical.TACS_TO_LT.doc @@ -3,7 +3,7 @@ \TYPE {TACS_TO_LT : tactic list -> list_tactic} \SYNOPSIS -The list_tactic which applies a list of tactics to the +The list-tactic which applies a list of tactics to the corresponding members of a list of goals. \KEYWORDS @@ -11,12 +11,12 @@ tactical. \DESCRIBE If {T1,...,Tn} are tactics, {TACS_TO_LT [T1,...,Tn]} is a -list_tactic which applies the tactics {T1,...,Tn} to the +list-tactic which applies the tactics {T1,...,Tn} to the corresponding goals. \FAILURE The application of {TACS_TO_LT} to a tactic list never fails. -The resulting list_tactic fails if length of the goal list +The resulting list-tactic fails if length of the goal list is not the same as that of the tactic list, or finally if {Ti} fails when applied to the {i}'th member of the goal list. diff --git a/help/Docfiles/Tactical.THEN_LT.doc b/help/Docfiles/Tactical.THEN_LT.doc index 6c166b2b4d..cf3cab16fc 100644 --- a/help/Docfiles/Tactical.THEN_LT.doc +++ b/help/Docfiles/Tactical.THEN_LT.doc @@ -4,33 +4,33 @@ op THEN_LT : list_tactic -> list_tactic -> list_tactic} \SYNOPSIS -Applies a list_tactic to the corresponding subgoals generated by a tactic -or by a previous list_tactic. +Applies a list-tactic to the corresponding subgoals generated by a tactic +or by a previous list-tactic. \KEYWORDS -tactical, list_tactic. +tactical, list-tactic. \DESCRIBE -If {tac} is a tactic and {ltac} is a list_tactic, +If {tac} is a tactic and {ltac} is a list-tactic, then {tac THEN_LT ltac} is a tactic which applies {tac} to a goal, and if it does not fail, -applies the list_tactic {ltac} to the +applies the list-tactic {ltac} to the resulting list of subgoals. -If {ltac1} and {ltac2} are list_tactics, -then {ltac1 THEN_LT ltac2} is a list_tactic which applies +If {ltac1} and {ltac2} are list-tactics, +then {ltac1 THEN_LT ltac2} is a list-tactic which applies {ltac1} to a goal list, and if it does not fail, applies {ltac2} to the resulting list of goals. \FAILURE -The application of {THEN_LT} to a tactic or list_tactic and a list_tactic +The application of {THEN_LT} to a tactic or list-tactic and a list-tactic never fails. The tactic {tac THEN_LT ltac} fails if {tac} fails when applied to the goal, or if {ltac} fails when applied to the resulting subgoal list. -The list_tactic {ltac1 THEN_LT ltac2} fails +The list-tactic {ltac1 THEN_LT ltac2} fails if {ltac1} fails when applied to the goal list, or if {ltac2} fails when applied to the goal list result of {ltac1}. From 279c6472105f62550a4a314337013672568c6c90 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Mon, 1 Dec 2014 23:51:48 +1100 Subject: [PATCH 038/718] replacing code for THEN and THENL using ALLGOALS and TACS_TO_LT also defines NULL_OK_LT to implement change to THENL (see https://github.com/HOL-Theorem-Prover/HOL/issues/214 ) --- help/Docfiles/Tactical.NULL_OK_LT.doc | 26 ++++++ help/Docfiles/Tactical.THEN_LT.doc | 5 +- src/1/Tactical.sig | 1 + src/1/Tactical.sml | 122 +++++++------------------- 4 files changed, 62 insertions(+), 92 deletions(-) create mode 100644 help/Docfiles/Tactical.NULL_OK_LT.doc diff --git a/help/Docfiles/Tactical.NULL_OK_LT.doc b/help/Docfiles/Tactical.NULL_OK_LT.doc new file mode 100644 index 0000000000..92893e6b43 --- /dev/null +++ b/help/Docfiles/Tactical.NULL_OK_LT.doc @@ -0,0 +1,26 @@ +\DOC NULL_OK_LT + +\TYPE {NULL_OK_LT : list_tactic -> list_tactic} + +\SYNOPSIS +Makes a list-tactic succeed with no effect when applied to the empty goal list. + +\KEYWORDS +list-tactical, failure. + +\DESCRIBE +For any list-tactic {ltac}, the application {NULL_OK_LT ltac} +gives a new list-tactic which has the same effect as {ltac} when applied to +a non-empty goal list. Applied to the empty goal list it succeeds with no +effect. + +\FAILURE +The application of {NULL_OK_LT} to a list-tactic {ltac} never fails. +The resulting list-tactic fails if applies to a non-empty goal list on which +{ltac} fails. + +\SEEALSO +Tactical.ALL_LT, Tactical.THENL + +\ENDDOC + diff --git a/help/Docfiles/Tactical.THEN_LT.doc b/help/Docfiles/Tactical.THEN_LT.doc index cf3cab16fc..3de3f8f8e4 100644 --- a/help/Docfiles/Tactical.THEN_LT.doc +++ b/help/Docfiles/Tactical.THEN_LT.doc @@ -43,13 +43,14 @@ Where {tac1} and {tac2} are tactics, {tac1 THEN_LT ALLGOALS tac2} is equivalent to {tac1 THEN tac2} Where {tac1} is a tactic and {tacs2} is a list of tactics, -{tac1 THEN_LT TACS_TO_LT tacs2} is equivalent to {tac1 THENL tacs2} +{tac1 THEN_LT NULL_OK_LT (TACS_TO_LT tacs2)} is equivalent to +{tac1 THENL tacs2} Where {tac} is a tactic, {tac THEN_LT REVERSE_LT} is equivalent to {REVERSE tac} \SEEALSO Tactical.ALLGOALS, Tactical.THEN, Tactical.TACS_TO_LT, Tactical.THENL, -Tactical.NTH_GOAL, Tactical.REVERSE_LT, Tactical.REVERSE +Tactical.NULL_OK_LT, Tactical.NTH_GOAL, Tactical.REVERSE_LT, Tactical.REVERSE \ENDDOC diff --git a/src/1/Tactical.sig b/src/1/Tactical.sig index 701ce57c9f..e28ea96503 100644 --- a/src/1/Tactical.sig +++ b/src/1/Tactical.sig @@ -16,6 +16,7 @@ sig val THEN_LT : list_tactic * list_tactic -> list_tactic *) val TACS_TO_LT : tactic list -> list_tactic + val NULL_OK_LT : list_tactic -> list_tactic val ALLGOALS : tactic -> list_tactic val NTH_GOAL : tactic -> int -> list_tactic val LASTGOAL : tactic -> list_tactic diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index 8ebc1c8b55..aae33f9255 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -77,91 +77,6 @@ fun store_thm (name, tm, tac) = infix THEN THENL THEN1 ORELSE THEN_LT -(*--------------------------------------------------------------------------- - * fun (tac1:tactic) THEN (tac2:tactic) : tactic = fn g => - * let val (gl,p) = tac1 g - * val (gll,pl) = unzip(map tac2 gl) - * in - * (flatten gll, (p o mapshape(map length gll)pl)) - * end; - *---------------------------------------------------------------------------*) - -fun tac1 THEN tac2 = - fn g => - let - val (gl, vf) = tac1 g - in - case itlist - (fn goal => fn (G, V, lengths) => - case tac2 goal of - ([], vfun) => let - val th = vfun [] - in - (G, empty th :: V, 0 :: lengths) - end - | (goals, vfun) => - (goals @ G, vfun :: V, length goals :: lengths)) - gl ([], [], []) of - ([], V, _) => - ([], let val th = vf (map (fn f => f []) V) in empty th end) - | (G, V, lengths) => (G, (vf o mapshape lengths V)) - end - -(*--------------------------------------------------------------------------- - * fun (tac1:tactic) THENL (tac2l: tactic list) : tactic = fn g => - * let val (gl,p) = tac1 g - * val tac2gl = zip tac2l gl - * val (gll,pl) = unzip (map (fn (tac2,g) => tac2 g) tac2gl) - * in - * (flatten gll, p o mapshape(map length gll) pl) - * end - *---------------------------------------------------------------------------*) - -fun (tac1: tactic) THENL (tacl: tactic list) : tactic = - fn g => - let - val (gl, vf) = tac1 g - val (G, V, lengths) = - itlist2 - (fn goal => fn tac => fn (G, V, lengths) => - case tac goal of - ([], vfun) => let - val th = vfun [] - in - (G, (empty th) :: V, 0 :: lengths) - end - | (goals, vfun) => - (goals @ G, vfun :: V, length goals :: lengths)) - gl tacl ([], [], []) - in - case G of - [] => ([], let val th = vf (map (fn f => f []) V) in empty th end) - | _ => (G, vf o mapshape lengths V) - end - -fun (tac1 ORELSE tac2) g = tac1 g handle HOL_ERR _ => tac2 g - -(*--------------------------------------------------------------------------- - * tac1 THEN1 tac2: A tactical like THEN that applies tac2 only to the - * first subgoal of tac1 - *---------------------------------------------------------------------------*) - -fun op THEN1 (tac1: tactic, tac2: tactic) : tactic = - fn g => - let - val (gl, jf) = tac1 g - val (h_g, t_gl) = - case gl of - [] => raise ERR "THEN1" "goal completely solved by first tactic" - | h :: t => (h, t) - val (h_gl, h_jf) = tac2 h_g - val _ = - if null h_gl then () - else raise ERR "THEN1" "first subgoal not solved by second tactic" - in - (t_gl, fn thl => jf (h_jf [] :: thl)) - end - (*--------------------------------------------------------------------------- * tac1 THEN_LT ltac2: * A tactical that applies ltac2 to the list of subgoals resulting from tac1 @@ -206,6 +121,17 @@ fun ALLGOALS tac2 gl = ([], let val ths = map (fn f => f []) V in empty ths end) | (G, V, lengths) => (G, mapshape lengths V) +(*--------------------------------------------------------------------------- + * fun (tac1:tactic) THEN (tac2:tactic) : tactic = fn g => + * let val (gl,p) = tac1 g + * val (gll,pl) = unzip(map tac2 gl) + * in + * (flatten gll, (p o mapshape(map length gll)pl)) + * end; + *---------------------------------------------------------------------------*) + +fun tac1 THEN tac2 = tac1 THEN_LT ALLGOALS tac2 ; + (*--------------------------------------------------------------------------- * fun TACS_TO_LT (tac2l: tactic list) : list_tactic = fn gl => * let @@ -238,6 +164,27 @@ fun TACS_TO_LT (tacl: tactic list) : list_tactic = | _ => (G, mapshape lengths V) end +(*--------------------------------------------------------------------------- + * NULL_OK_LT ltac: A list-tactical like ltac but succeeds with no effect + * when applied to an ampty goal list + *---------------------------------------------------------------------------*) + +fun NULL_OK_LT ltac [] = ([], Lib.I) + | NULL_OK_LT ltac gl = ltac gl ; + +(*--------------------------------------------------------------------------- + * fun (tac1:tactic) THENL (tac2l: tactic list) : tactic = fn g => + * let val (gl,p) = tac1 g + * val tac2gl = zip tac2l gl + * val (gll,pl) = unzip (map (fn (tac2,g) => tac2 g) tac2gl) + * in + * (flatten gll, p o mapshape(map length gll) pl) + * end + * BUT - if gl is empty, just return (gl, p) + *---------------------------------------------------------------------------*) + +fun tac1 THENL tacs2 = tac1 THEN_LT NULL_OK_LT (TACS_TO_LT tacs2) ; + fun (tac1 ORELSE tac2) g = tac1 g handle HOL_ERR _ => tac2 g (*--------------------------------------------------------------------------- @@ -335,11 +282,6 @@ fun REVERSE_LT gl = (rev gl, rev) ; fun REVERSE tac = tac THEN_LT REVERSE_LT ; *) -(* for testing, redefine THEN and THENL -fun tac1 THENL tacs2 = tac1 THEN_LT TACS_TO_LT tacs2 ; -fun tac1 THEN tac2 = tac1 THEN_LT ALLGOALS tac2 ; -*) - (*--------------------------------------------------------------------------- * Fail with the given token. Useful in tactic programs to check that a * tactic produces no subgoals. Write From 404e6efef5dd692b32148e8659068f6c66a67aeb Mon Sep 17 00:00:00 2001 From: Thomas Tuerk Date: Thu, 4 Dec 2014 07:47:11 +0100 Subject: [PATCH 039/718] add an experimental deep embedding of pattern matching this is work in progress and far from finished --- examples/deep_matches/README | 2 + examples/deep_matches/constrFamiliesLib.sig | 6 + examples/deep_matches/constrFamiliesLib.sml | 78 ++ examples/deep_matches/deepMatchesExamples.sml | 97 ++ examples/deep_matches/deepMatchesLib.sig | 48 + examples/deep_matches/deepMatchesLib.sml | 952 ++++++++++++++++++ examples/deep_matches/deepMatchesScript.sml | 405 ++++++++ examples/deep_matches/deepMatchesSyntax.sig | 71 ++ examples/deep_matches/deepMatchesSyntax.sml | 167 +++ 9 files changed, 1826 insertions(+) create mode 100644 examples/deep_matches/README create mode 100644 examples/deep_matches/constrFamiliesLib.sig create mode 100644 examples/deep_matches/constrFamiliesLib.sml create mode 100644 examples/deep_matches/deepMatchesExamples.sml create mode 100644 examples/deep_matches/deepMatchesLib.sig create mode 100644 examples/deep_matches/deepMatchesLib.sml create mode 100644 examples/deep_matches/deepMatchesScript.sml create mode 100644 examples/deep_matches/deepMatchesSyntax.sig create mode 100644 examples/deep_matches/deepMatchesSyntax.sml diff --git a/examples/deep_matches/README b/examples/deep_matches/README new file mode 100644 index 0000000000..26e3de4d74 --- /dev/null +++ b/examples/deep_matches/README @@ -0,0 +1,2 @@ +This directory contains a deep embedding of pattern matching. +It is work in progress and still far from stable. diff --git a/examples/deep_matches/constrFamiliesLib.sig b/examples/deep_matches/constrFamiliesLib.sig new file mode 100644 index 0000000000..21b802d6bf --- /dev/null +++ b/examples/deep_matches/constrFamiliesLib.sig @@ -0,0 +1,6 @@ +signature constrFamiliesLib = +sig + include Abbrev + + val gen_case_expand_thm : thm -> thm -> thm +end diff --git a/examples/deep_matches/constrFamiliesLib.sml b/examples/deep_matches/constrFamiliesLib.sml new file mode 100644 index 0000000000..ef846a6dcd --- /dev/null +++ b/examples/deep_matches/constrFamiliesLib.sml @@ -0,0 +1,78 @@ +structure constrFamiliesLib :> constrFamiliesLib = +struct + +open Abbrev + +(* Contructor families are lists of constructors. + Constructors are functions that are injective and + pairwise distinct. Moreover, a case-expansion theorem needs to be provided. + + Let's assume we have a datatype t with + C1 of bool, C2, C3 of nat. Then we need the following theorems + + !b1 b2. (C1 b1 = C1 b2) <-> (b1 = b2) + !n1 n2. (C3 n1 = C3 n2) <-> (n1 = n2) + (!b. not (C1 b = C2)) + (!b. not (C2 = C1 b)) + (!b n. not (C1 b = C3 n)) + (!b n. not (C3 n = C3 b)) + (!n. not (C3 n = C2)) + (!n. not (C2 = C3 n)) + + and a case split theorem like + + !f v. f v = (case v of + C1 b -> f (C1 b) + | C2 -> f C2 + | C3 n -> f (C3 n)) +*) + +type constrFamily = { + constructors : term list, + one_one_thm : thm, + distinct_thm : thm, + case_split_thm: thm +} + + + +fun gen_case_expand_thm case_def_thm nchotomy_thm = let + val c = fst ( + strip_comb (lhs (snd (strip_forall (hd (strip_conj (concl case_def_thm))))))) + val (a, cases) = dest_forall (concl nchotomy_thm) + + val res_ty = snd (strip_fun (type_of c)) + val ff_tm = mk_var ("ff", (type_of a) --> res_ty) + + val args = let + val cases_tms = strip_disj cases + fun process_case ct = let + val (vars, b) = strip_exists ct + val b' = rhs b + in + list_mk_abs (vars, (mk_comb (ff_tm, b'))) + end + in + map process_case cases_tms + end + + val t_rhs = list_mk_comb (c, a::args) + val t_lhs = mk_comb (ff_tm, a) + val t = list_mk_forall([ff_tm, a], mk_eq (t_lhs, t_rhs)) + + val res_thm = prove (t, + REPEAT GEN_TAC THEN + MP_TAC (ISPEC a nchotomy_thm) THEN + SIMP_TAC std_ss [DISJ_IMP_THM, case_def_thm, + GSYM LEFT_FORALL_IMP_THM]) +in + res_thm +end + + + + + + + +end diff --git a/examples/deep_matches/deepMatchesExamples.sml b/examples/deep_matches/deepMatchesExamples.sml new file mode 100644 index 0000000000..f90f647de8 --- /dev/null +++ b/examples/deep_matches/deepMatchesExamples.sml @@ -0,0 +1,97 @@ +open bossLib +open deepMatchesLib + + +(* Introducing case expressions *) + +val t = ``case x of (NONE, []) => 0`` +val t' = convert_case t +val thm_t = PMATCH_INTRO_CONV t + +(* check that SIMP works *) +val thm_t' = PMATCH_REMOVE_ARB_CONV t' +val thm_t' = PMATCH_SIMP_CONV t' + +(* more fancy *) + +val t = ``case x of + (NONE, []) => 0 + | (SOME 2, []) => 2 + | (SOME 3, (x :: xs)) => 3 + x + | (SOME _, (x :: xs)) => x`` + +val t' = convert_case t +val thm_t = PMATCH_INTRO_CONV t + +val thm_t' = PMATCH_REMOVE_ARB_CONV t' +val thm_t' = PMATCH_SIMP_CONV t' + +(* Playing around with some examples *) + +val example1 = `` +PMATCH (a,x,xs) + [PMATCH_ROW (\x. ((NONE,x,[]),x)); + PMATCH_ROW (\x. ((NONE,x,[2]),x)); + PMATCH_ROW (\(x,v18). ((NONE,x,[v18]),3)); + PMATCH_ROW (\(x,v12,v16,v17). ((NONE,x,v12::v16::v17),3)); + PMATCH_ROW (\(y,x,z,zs). ((SOME y,x,[z]),x+5+z)); + PMATCH_ROW (\(y,v23,v24). ((SOME y,0,v23::v24),v23+y)); + PMATCH_ROW (\(y,z,v23). ((SOME y,SUC z,[v23]),3)); + PMATCH_ROW (\(y,z). ((SOME y,SUC z,[1; 2]),y + z)); + PMATCH_ROW (\(y,z,v38). ((SOME y,SUC z,[1; v38]),3)); + PMATCH_ROW (\(y,x). ((y,x,[2;4;3]),3+x)); + PMATCH_ROW + (\(y,z,v29,v36,v37). ((SOME y,SUC z,1::v29::v36::v37),z+v36+v29)); + PMATCH_ROW (\(y,z,v31,v29,v30). ((SOME y,SUC z,v31::v29::v30),v31+z))]`` + +val example2 = ``PMATCH (h::t) + [PMATCH_ROW (\_ . ([],x)); + PMATCH_ROW (\_. ([2],x)); PMATCH_ROW (\v18. ([v18],3)); + PMATCH_ROW (\(v12,v16,v17). (v12::v16::v17,3)); + PMATCH_ROW (\_. ([2; 4; 3],3 + x))]`` + +val example3 = + ``PMATCH (NONE,x,xs) + [PMATCH_ROW (\x. ((NONE,x,[]),x)); + PMATCH_ROW (\x. ((NONE,x,[2]),x)); + PMATCH_ROW (\(x,v18). ((NONE,x,[v18]),3)); + PMATCH_ROW (\(x,v12,v16,v17). ((NONE,x,v12::v16::v17),3)); + PMATCH_ROW (\(y,x). ((y,x,[2; 4; 3]),3 + x))]``; + + +(* turn off pretty printer *) + +set_trace "use pmatch_pp" 0; +example1; +set_trace "use pmatch_pp" 1; +example1; + + +PMATCH_SIMP_CONV example1 +PMATCH_SIMP_CONV example2 +PMATCH_SIMP_CONV example3 + +set_goal ([], ``^example1 = XXX``); + +e (Cases_on `a`) +e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) +e (Cases_on `xs`) +e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) + +proofManagerLib.restart () + +e (Cases_on `xs`) +e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) + +proofManagerLib.restart () + +e (Cases_on `x`) +e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) +e (Cases_on `xs`) + +proofManagerLib.rotate 1 +e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) +SIMP_TAC std_ss [] + +proofManagerLib.drop () + diff --git a/examples/deep_matches/deepMatchesLib.sig b/examples/deep_matches/deepMatchesLib.sig new file mode 100644 index 0000000000..cf1c3726fe --- /dev/null +++ b/examples/deep_matches/deepMatchesLib.sig @@ -0,0 +1,48 @@ +signature deepMatchesLib = +sig + include Abbrev + + (********************************) + (* turn shallow case-terms into *) + (* deeply embedded ones *) + (********************************) + + val convert_case : term -> term + val PMATCH_INTRO_CONV : conv + + + (********************************) + (* simplify PMATCH-terms *) + (********************************) + + (* There are various ways of simplifying + PMATCH. One can e.g. remove redundant rows + or partially evaluate it. The conversion + PMATCH_SIMP_CONV does this. *) + val PMATCH_SIMP_CONV : conv + + (* There is also a more generic version that + allows to provide extra ssfrags. This might + be handy, if the PMATCH contains functions + not known by the default methods. *) + val PMATCH_SIMP_CONV_GEN : ssfrag list -> conv + + + (* PMATCH_SIMP_CONV consists of various + component conversions. These can be used + independently as well. *) + val PMATCH_REMOVE_ARB_CONV : conv + val PMATCH_REMOVE_ARB_CONV_GEN : ssfrag list -> conv + + val PMATCH_CLEANUP_PVARS_CONV : conv + + val PMATCH_CLEANUP_CONV : conv + val PMATCH_CLEANUP_CONV_GEN : ssfrag list -> conv + + val PMATCH_SIMP_COLS_CONV : conv + val PMATCH_SIMP_COLS_CONV_GEN : ssfrag list -> conv + + val PMATCH_EXPAND_COLS_CONV : conv + + +end diff --git a/examples/deep_matches/deepMatchesLib.sml b/examples/deep_matches/deepMatchesLib.sml new file mode 100644 index 0000000000..4f2ac6a2f8 --- /dev/null +++ b/examples/deep_matches/deepMatchesLib.sml @@ -0,0 +1,952 @@ +structure deepMatchesLib :> deepMatchesLib = +struct + +open deepMatchesTheory bossLib +open quantHeuristicsLib +open deepMatchesSyntax +open constrFamiliesLib + +(***********************************************) +(* Simpset to evaluate PMATCH_ROWS *) +(***********************************************) + +val PAIR_EQ_COLLAPSE = prove ( +``((FST x = a) /\ (SND x = b)) = (x = (a, b))``, +Cases_on `x` THEN SIMP_TAC std_ss []) + +(* +val rc = DEPTH_CONV pairTools.PABS_ELIM_CONV THENC SIMP_CONV list_ss [pairTheory.EXISTS_PROD, pairTheory.FORALL_PROD, PMATCH_ROW_EQ_NONE, PAIR_EQ_COLLAPSE, oneTheory.one] +*) + +val pabs_elim_ss = + simpLib.conv_ss + {name = "PABS_ELIM_CONV", + trace = 2, + key = SOME ([],``UNCURRY (f:'a -> 'b -> bool)``), + conv = K (K pairTools.PABS_ELIM_CONV)} + +fun rc_ss gl = list_ss ++ simpLib.merge_ss + (gl @ + [pabs_elim_ss, + pairSimps.paired_forall_ss, + pairSimps.paired_exists_ss, + pairSimps.gen_beta_ss, + simpLib.rewrites [ + pairTheory.EXISTS_PROD, + pairTheory.FORALL_PROD, + PMATCH_ROW_EQ_NONE, + PAIR_EQ_COLLAPSE, + oneTheory.one]]) + + +(***********************************************) +(* converting case-splits to PMATCH *) +(***********************************************) + +(* +val t = ``case x of + (NONE, []) => 0`` *) + +fun type_names ty = + let val {Thy,Tyop,Args} = Type.dest_thy_type ty + in {Thy=Thy,Tyop=Tyop} + end; + +(* destruct variant cases, see dest_case_fun *) +fun dest_case_fun_aux1 t = let + val (f, args) = strip_comb t + val (tys, _) = strip_fun (type_of f) + val _ = if (List.null args) then failwith "dest_case_fun" else () + val ty = case tys of + [] => failwith "dest_case_fun" + | (ty::_) => ty + val tn = type_names ty + val ti = case TypeBase.fetch ty of + NONE => failwith "dest_case_fun" + | SOME ti => ti + + val _ = if (same_const (TypeBasePure.case_const_of ti) f) then + () else failwith "dest_case_fun" + + val ty_s = match_type (type_of (TypeBasePure.case_const_of ti)) (type_of f) + val constrs = List.map (inst ty_s) (TypeBasePure.constructors_of ti) + + val a = hd args + val ps = map2 (fn c => fn arg => let + val (vars, res) = strip_abs arg in + (list_mk_comb (c, vars), res) end) constrs (tl args) +in + (a, ps) +end + +(* destruct literal cases, see dest_case_fun *) +fun dest_case_fun_aux2 t = let + val _ = if is_literal_case t then () else failwith "dest_case_fun" + + val (f, args) = strip_comb t + + val v = (el 2 args) + val (v', b) = dest_abs (el 1 args) + + fun strip_cond acc b = let + val (c, t_t, t_f) = dest_cond b + val (c_l, c_r) = dest_eq c + val _ = if (aconv c_l v') then () else failwith "dest_case_fun" + in + strip_cond ((c_r, t_t)::acc) t_f + end handle HOL_ERR _ => (acc, b) + + val (ps_rev, c_else) = strip_cond [] b + val ps = List.rev ((v', c_else) :: ps_rev) +in + (v, ps) +end + + +(* destruct a case-function. + The top-most split is split into the input + a list of rows. + Each row consists of a pattern + the right-hand side. *) +fun dest_case_fun t = dest_case_fun_aux1 t handle HOL_ERR _ => dest_case_fun_aux2 t + + +fun convert_case_aux x t = let + val (a, ps) = dest_case_fun t + + fun process_arg (p, rh) = let + val x' = subst [a |-> p] x + in + (* recursive call *) + case convert_case_aux x' rh of + NONE => [(x', rh)] + | SOME resl => resl + end + + val ps = flatten (map process_arg ps) +in + SOME ps +end handle HOL_ERR _ => NONE; + +(* convert a case-term into a PMATCH-term, without any proofs *) +fun convert_case t = let + val (f, args) = strip_comb t + val _ = if (List.null args) then failwith "not a case-split" else () + + val (p,patterns) = if is_literal_case t then (el 2 args, [el 1 args]) else + (hd args, tl args) + val v = genvar (type_of p) + + val t0 = if is_literal_case t then list_mk_comb (f, patterns @ [v]) else list_mk_comb (f, v::patterns) + val ps = case convert_case_aux v t0 of + NONE => failwith "not a case-split" + | SOME ps => ps + + fun process_pattern (p, rh) = let + val fvs = List.rev (free_vars p) + in + mk_PMATCH_ROW fvs p rh + end + val rows = List.map process_pattern ps + val rows_tm = listSyntax.mk_list (rows, type_of (hd rows)) + + val rows_tm_p = subst [v |-> p] rows_tm +in + mk_PMATCH p rows_tm_p +end + +fun PMATCH_INTRO_CONV t = let + val t' = convert_case t + val tm = mk_eq (t, t') + + (* very slow, simple approach. Just brute force. + TODO: change implementation to get more runtime-speed *) + val my_tac = ( + CASE_TAC THEN + FULL_SIMP_TAC (rc_ss []) [PMATCH_EVAL] + ) +in + (* set_goal ([], tm) *) + prove (tm, REPEAT my_tac) +end handle HOL_ERR _ => NO_CONV t; + + +(***********************************************) +(* removing ARB rows *) +(***********************************************) + +(* when converting CASE expressions into PMATCH, + often ARB rows are introduced for the not + covered cases. These ARB rows are + not needed for PMATCH and can be removed. *) + +(* +val ssl = [] +val t = ``PMATCH x + [PMATCH_ROW (\_ . (NONE,0)); + PMATCH_ROW (\v. (SOME v,ARB))]`` + +val t = + ``PMATCH x + [PMATCH_ROW (\_. ((NONE,[]),0)); + PMATCH_ROW (\(v4,v5). ((NONE,v4::v5),ARB)); + PMATCH_ROW (\(v2,v1). ((SOME v2,v1),ARB))]`` + +*) + +fun PMATCH_REMOVE_ARB_CONV_GEN_SINGLE ssl t = let + val (v, rows) = dest_PMATCH t + val rows_rev = List.rev rows + + val i_rev = index (fn row => ( + is_arb (#3(dest_PMATCH_ROW row))) + handle HOL_ERR _ => false) rows_rev + val i = length rows - (i_rev + 1) + + val rows1 = List.take (rows, i) + val r = List.nth (rows, i) + val rows2 = List.drop (rows, i+1) + + val r_ty = type_of r + val rows1_tm = listSyntax.mk_list (rows1, r_ty) + val rows2_tm = listSyntax.mk_list (rows2, r_ty) + val r_thm = (snd (PMATCH_ROW_PABS_ELIM_CONV r)) handle + UNCHANGED => REFL r + + val input_rows = + listSyntax.mk_append (rows1_tm, + listSyntax.mk_cons (rhs (concl r_thm), rows2_tm)) + + val thm0 = HO_PART_MATCH (rand o lhs o snd o dest_imp o #2 o strip_forall) ( + ISPEC v (FRESH_TY_VARS_RULE PMATCH_REMOVE_ARB_NO_OVERLAP) + ) input_rows + + + val pre = rand (rator (concl thm0)) + val pre_thm = prove (pre, SIMP_TAC (rc_ss ssl) []) + val thm1 = MP thm0 pre_thm + val thm2 = CONV_RULE + ((RHS_CONV o RAND_CONV) listLib.APPEND_CONV) + thm1 + + val thm2_lhs_tm = mk_eq (t, lhs (concl thm2)) + val thm2_lhs = prove (thm2_lhs_tm, + MP_TAC r_thm THEN SIMP_TAC (rc_ss []) []) + + val thm3 = TRANS thm2_lhs thm2 +in + thm3 +end handle HOL_ERR _ => raise UNCHANGED + +fun PMATCH_REMOVE_ARB_CONV_GEN ssl = REPEATC (PMATCH_REMOVE_ARB_CONV_GEN_SINGLE ssl) +val PMATCH_REMOVE_ARB_CONV = PMATCH_REMOVE_ARB_CONV_GEN [] + + +(***********************************************) +(* Cleaning up unused vars in PMATCH_ROW *) +(***********************************************) + +(*val t = `` +PMATCH (SOME x, xz) + [PMATCH_ROW (\x. ((SOME 2,x,[]),x)); + PMATCH_ROW (\y:'a. ((SOME 2,3,[]),x)); + PMATCH_ROW (\(z,x,yy). ((z,x,[2]),x)); + PMATCH_ROW (\(z,yy,xs). ((SOME z,xs),3+z)); + PMATCH_ROW (\(z,xs). ((SOME z,xs),3+z)); + PMATCH_ROW (\(yy,x,xs). ((NONE,xs),3))]`` +*) + +(* Many simps depend on patterns being injective. This means + in particular that no extra, unused vars occur in the patterns. + The following removes such unused vars. *) + +fun PMATCH_CLEANUP_PVARS_CONV t = let + val _ = if is_PMATCH t then () else raise UNCHANGED + + fun row_conv row = let + val (vars_tm, pt, rh) = dest_PMATCH_ROW row + val _ = if (type_of vars_tm = ``:unit``) then raise UNCHANGED else () + val vars = pairSyntax.strip_pair vars_tm + val used_vars = FVL [pt, rh] empty_tmset + + val filtered_vars = filter (fn v => HOLset.member (used_vars, v)) vars + + val _ = if (length vars = length filtered_vars) then + raise UNCHANGED else () + + val row' = mk_PMATCH_ROW filtered_vars pt rh + + val eq_tm = mk_eq (row, row') + (* set_goal ([], eq_tm) *) + val eq_thm = prove (eq_tm, + CONV_TAC (DEPTH_CONV pairTools.PABS_ELIM_CONV) THEN + HO_MATCH_MP_TAC PMATCH_ROW_EQ_AUX THEN + SIMP_TAC (rc_ss []) [] + ) + in + eq_thm + end +in + DEPTH_CONV row_conv t +end + + +(***********************************************) +(* Cleaning up by removing rows that *) +(* don't match or are redundant *) +(* also remove the whole PMATCH, if first *) +(* row matches *) +(***********************************************) + +fun map_filter f l = case l of + [] => [] + | x::xs => (case f x of + NONE => map_filter f xs + | SOME y => y :: (map_filter f xs)); + +(* remove redundant rows *) +fun PMATCH_CLEANUP_CONV_GEN ssl t = let + val (v, rows) = dest_PMATCH t + val rc_conv = SIMP_CONV (rc_ss ssl) [] + + fun check_row r = let + val r_tm = mk_eq (mk_comb (r, v), optionSyntax.mk_none (type_of t)) val r_thm = rc_conv r_tm + val res_tm = rhs (concl r_thm) + in + if (same_const res_tm T) then SOME (true, r_thm) else + (if (same_const res_tm F) then SOME (false, r_thm) else NONE) + end handle HOL_ERR _ => NONE + + val (rows_checked_rev, _) = foldl (fn (r, (acc, abort)) => + if abort then ((r, NONE)::acc, true) else ( + let + val res = check_row r + val abort = (case res of + (SOME (false, _)) => true + | _ => false) + in + ((r, res)::acc, abort) + end)) ([], false) rows + val rows_checked = List.rev rows_checked_rev + + (* did we get any results? *) + fun check_row_exists v rows = + exists (fn x => case x of (_, SOME (v', _)) => v = v' | _ => false) rows + + val _ = if ((check_row_exists true rows_checked_rev) orelse (check_row_exists false (tl rows_checked_rev))) then () else raise UNCHANGED + + val row_ty = type_of (hd rows) + + (* drop redundant rows *) + val (thm0, rows_checked0) = let + val n = index (fn x => case x of (_, SOME (false, _)) => true | _ => false) rows_checked + val n_tm = numSyntax.term_of_int n + + val thma = ISPECL [v, listSyntax.mk_list (rows, row_ty), n_tm] + (FRESH_TY_VARS_RULE PMATCH_ROWS_DROP_REDUNDANT_TRIVIAL_SOUNDNESS) + + val precond = fst (dest_imp (concl thma)) + val precond_thm = prove (precond, + MP_TAC (snd(valOf (snd (el (n+1) rows_checked)))) THEN + SIMP_TAC list_ss [quantHeuristicsTheory.IS_SOME_EQ_NOT_NONE]) + + val thmb = MP thma precond_thm + + val take_conv = RATOR_CONV (RAND_CONV reduceLib.SUC_CONV) THENC + listLib.FIRSTN_CONV + val thmc = CONV_RULE (RHS_CONV (RAND_CONV take_conv)) thmb + in + (thmc, List.take (rows_checked, n+1)) + end handle HOL_ERR _ => (REFL t, rows_checked) + + (* drop false rows *) + val (thm1, rows_checked1) = let + val _ = if (exists (fn x => case x of (_, (SOME (true, _))) => true | _ => false) rows_checked0) then () else failwith "nothing to do" + + fun process_row ((r, r_thm_opt), thm) = (case r_thm_opt of + (SOME (true, r_thm)) => let + val thmA = PMATCH_EXTEND_OLD + val thmB = HO_MATCH_MP thmA (EQT_ELIM r_thm) + val thmC = HO_MATCH_MP thmB thm + in + thmC + end + | _ => let + val thmA = PMATCH_EXTEND_BOTH_ID + val thmB = HO_MATCH_MP thmA thm + in + ISPEC r thmB + end) + + val base_thm = INST_TYPE [gamma |-> type_of t] (ISPECL [v, v] PMATCH_EXTEND_BASE) + val thma = foldl process_row base_thm (List.rev rows_checked0) + + val rows_checked1 = filter (fn (_, res_opt) => case res_opt of + SOME (true, thm) => false + | _ => true) rows_checked0 + in + (thma, rows_checked1) + end handle HOL_ERR _ => (REFL (rhs (concl thm0)), rows_checked0) + + + (* if first line matches, evaluate *) + val thm2 = let + val _ = if (not (List.null rows_checked1) andalso + (case hd rows_checked1 of (_, (SOME (false, _))) => true | _ => false)) then () else failwith "nothing to do" + + val thm1_tm = rhs (concl thm1) + val thm2a = DEPTH_CONV pairTools.PABS_ELIM_CONV thm1_tm handle UNCHANGED => REFL thm1_tm + val (vars,_) = pairLib.dest_pabs (rand (rand (rator (rand (thm1_tm))))) + + val thm2a0 = HO_PART_MATCH (lhs o rand) PMATCH_EVAL_MATCH (rhs (concl thm2a)) + + val pre_tm = fst (dest_imp (concl thm2a0)) + val pre_thm0 = snd (valOf(snd (hd rows_checked1))) + val pre_thm = prove (pre_tm, + MP_TAC pre_thm0 THEN + SIMP_TAC (rc_ss ssl) []) + + val thm2a1 = MP thm2a0 pre_thm + + val thm2b = TRANS thm2a thm2a1 + val thm2c = CONV_RULE (RHS_CONV (RAND_CONV rc_conv)) thm2b handle HOL_ERR _ => thm2b + in + thm2c + end handle HOL_ERR _ => let + val _ = if (List.null rows_checked1) then () else failwith "nothing to do" + in + (REWR_CONV (CONJUNCT1 PMATCH_def)) (rhs (concl thm1)) + end handle HOL_ERR _ => REFL (rhs (concl thm1)) +in + TRANS (TRANS thm0 thm1) thm2 +end handle HOL_ERR _ => raise UNCHANGED + + +fun PMATCH_CLEANUP_CONV t = PMATCH_CLEANUP_CONV_GEN [] t + + + +(***********************************************) +(* simplify a column *) +(***********************************************) + +fun pair_get_col col v = let + val vs = pairSyntax.strip_pair v + val c_v = List.nth (vs, col) + val vs' = List.take (vs, col) @ + List.drop (vs, col+1) + val _ = if (List.null vs') then failwith "pair_get_col" + else () + val v' = pairSyntax.list_mk_pair vs' +in + (v', c_v) +end; + +(*----------------*) +(* drop a column *) +(*----------------*) + +fun PMATCH_REMOVE_COL_AUX ssl col t = let + val (v, rows) = dest_PMATCH t + val (v', c_v) = pair_get_col col v + + fun PMATCH_ROW_REMOVE_FUN_VAR_COL_AUX row = let + val (vars_tm, pt, rh) = dest_PMATCH_ROW row + val vars = pairSyntax.strip_pair vars_tm + + val (pt', pv) = pair_get_col col pt + + val pv_i_opt = SOME (index (aconv pv) vars) handle HOL_ERR _ => NONE + val (vars'_tm, g') = case pv_i_opt of + (SOME pv_i) => (let + (* we eliminate a variabe column *) + val vars' = let + val vars' = List.take (vars, pv_i) @ List.drop (vars, pv_i+1) + in + if (List.null vars') then [genvar ``:unit``] else vars' + end + + val vars'_tm = pairSyntax.list_mk_pair vars' + val g' = let + val vs = List.take (vars, pv_i) @ (c_v :: List.drop (vars, pv_i+1)) + val vs_tm = pairSyntax.list_mk_pair vs + in + pairSyntax.mk_pabs (vars'_tm, vs_tm) + end + in + (vars'_tm, g') + end) + | NONE => (let + (* we eliminate a costant columns *) + val (sub, _) = match_term pv c_v + val _ = if List.all (fn x => List.exists (aconv (#redex x)) vars) sub then () else failwith "not a constant-col after all" + + val vars' = filter (fn v => not (List.exists (fn x => (aconv v (#redex x))) sub)) vars + val vars' = if (List.null vars') then [genvar ``:unit``] else vars' + val vars'_tm = pairSyntax.list_mk_pair vars' + + val g' = pairSyntax.mk_pabs (vars'_tm, Term.subst sub vars_tm) + in + (vars'_tm, g') + end) + + val f = pairSyntax.mk_pabs (vars_tm, pt) + val f' = pairSyntax.mk_pabs (vars'_tm, pt') + val g = pairSyntax.mk_pabs (vars_tm, rh) + + val thm0 = let + val thm = FRESH_TY_VARS_RULE PMATCH_ROW_REMOVE_FUN_VAR + val thm = ISPEC v thm + val thm = ISPEC v' thm + val thm = ISPEC f thm + val thm = ISPEC g thm + val thm = ISPEC f' thm + val thm = ISPEC g' thm + + fun elim_conv vs = RATOR_CONV (RAND_CONV ( + (pairTools.PABS_INTRO_CONV vs) THENC + (DEPTH_CONV (pairLib.PAIRED_BETA_CONV ORELSEC BETA_CONV)) + )) + + val thm = CONV_RULE ((RAND_CONV o LHS_CONV) (elim_conv vars_tm)) thm + val thm = CONV_RULE ((RAND_CONV o RHS_CONV) (elim_conv vars'_tm)) thm + + val tm_eq = mk_eq(lhs (rand (concl thm)), mk_comb (row, v)) + val eq_thm = prove (tm_eq, SIMP_TAC (rc_ss ssl) []) + + val thm = CONV_RULE (RAND_CONV (LHS_CONV (K eq_thm))) thm + in + thm + end + + val pre_tm = fst (dest_imp (concl thm0)) +(* set_goal ([], pre_tm) *) + val pre_thm = prove (pre_tm, SIMP_TAC (rc_ss ssl) []) + val thm1 = MP thm0 pre_thm + in + thm1 + end + + fun process_row (row, thm) = let + val row_thm = PMATCH_ROW_REMOVE_FUN_VAR_COL_AUX row + val thmA = PMATCH_EXTEND_BOTH + val thmB = HO_MATCH_MP thmA row_thm + val thmC = HO_MATCH_MP thmB thm + in + thmC + end + + val base_thm = INST_TYPE [gamma |-> type_of t] (ISPECL [v, v'] PMATCH_EXTEND_BASE) + val thm0 = List.foldl process_row base_thm (List.rev rows) +in + thm0 +end handle HOL_ERR _ => raise UNCHANGED + + + +(*------------------------------------*) +(* remove a constructor from a column *) +(*------------------------------------*) + +fun PMATCH_REMOVE_FUN_AUX ssl col t = let + val (v, rows) = dest_PMATCH t + + val (ff_tm, ff_inv, ff_inv_var, c) = let + val vs = pairSyntax.strip_pair v + val c_args = List.nth(vs, col) + val (c, args) = strip_comb c_args + + val vs_vars = List.map (fn t => genvar (type_of t)) vs + val args_vars = List.map (fn t => genvar (type_of t)) args + + val vars = List.take (vs_vars, col) @ args_vars @ + List.drop (vs_vars, col+1) + val ff_res = List.take (vs_vars, col) @ list_mk_comb (c, args_vars) :: List.drop (vs_vars, col+1) + val ff_tm = pairSyntax.mk_pabs (pairSyntax.list_mk_pair vars, + pairSyntax.list_mk_pair ff_res) + + fun ff_inv tt = let + val tts = pairSyntax.strip_pair tt + val tt_args = List.nth(tts, col) + + val (c', args') = strip_comb tt_args + val _ = if (aconv c c') then () else failwith "different constr" + + val vars = List.take (tts, col) @ args' @ + List.drop (tts, col+1) + in + pairSyntax.list_mk_pair vars + end + + fun ff_inv_var avoid tt = let + val tts = pairSyntax.strip_pair tt + val tt_col = List.nth(tts, col) + + val _ = if (is_var tt_col) then () else failwith "no var" + + val (var_basename, _) = dest_var (tt_col) + fun gen_var i arg = let + val n = var_basename ^ "_"^int_to_string i + in + mk_var (n, type_of arg) + end + + + val (args, _) = quantHeuristicsTools.list_variant avoid (mapi gen_var args_vars) + + val vars = List.take (tts, col) @ args @ + List.drop (tts, col+1) + in + (pairSyntax.list_mk_pair vars, tt_col, args) + end + + in + (ff_tm, ff_inv, ff_inv_var, c) + end + + val ff_thm_tm = ``!x y. (^ff_tm x = ^ff_tm y) ==> (x = y)`` + val ff_thm = prove (ff_thm_tm, SIMP_TAC (rc_ss ssl) []) + + val v' = ff_inv v + + val PMATCH_ROW_REMOVE_FUN' = let + val thm0 = (HO_MATCH_MP PMATCH_ROW_REMOVE_FUN ff_thm) + val thm1 = ISPEC v' thm0 + + val thm_v' = prove (``^ff_tm ^v' = ^v``, SIMP_TAC (rc_ss ssl) []) + val thm2 = CONV_RULE (STRIP_QUANT_CONV (LHS_CONV (RAND_CONV (K thm_v')))) thm1 + in + thm2 + end + + fun PMATCH_ROW_REMOVE_FUN_COL_AUX row = let + val (vars_tm, pt, rh) = dest_PMATCH_ROW row + + val pt' = ff_inv pt + val f = pairSyntax.mk_pabs (vars_tm, pt') + val g = pairSyntax.mk_pabs (vars_tm, rh) + + val thm0 = ISPEC g (ISPEC f PMATCH_ROW_REMOVE_FUN') + val eq_thm_tm = mk_eq (lhs (concl thm0), mk_comb (row, v)) + val eq_thm = prove (eq_thm_tm, SIMP_TAC (rc_ss ssl) []) + + val thm1 = CONV_RULE (LHS_CONV (K eq_thm)) thm0 + + val vi_conv = (pairTools.PABS_INTRO_CONV vars_tm) THENC + (DEPTH_CONV (pairLib.PAIRED_BETA_CONV ORELSEC BETA_CONV)) + + val thm2 = CONV_RULE (RHS_CONV (RATOR_CONV (RAND_CONV vi_conv))) thm1 + in + thm2 + end + + fun PMATCH_ROW_REMOVE_VAR_COL_AUX row = let + val (vars_tm, pt, rh) = dest_PMATCH_ROW row + val vars = pairSyntax.strip_pair vars_tm + + val avoid = vars @ free_vars pt @ free_vars rh + val (pt', pv, new_vars) = ff_inv_var avoid pt + + val pv_i = index (aconv pv) vars + + val vars' = let + val vars' = List.take (vars, pv_i) @ new_vars @ List.drop (vars, pv_i+1) + in + if (List.null vars') then [genvar ``:unit``] else vars' + end + + val vars'_tm = pairSyntax.list_mk_pair vars' + val g' = let + val c_v = list_mk_comb (c, new_vars) + val vs = List.take (vars, pv_i) @ (c_v :: List.drop (vars, pv_i+1)) + val vs_tm = pairSyntax.list_mk_pair vs + in + pairSyntax.mk_pabs (vars'_tm, vs_tm) + end + + val f = pairSyntax.mk_pabs (vars_tm, pt) + val f' = pairSyntax.mk_pabs (vars'_tm, pt') + val g = pairSyntax.mk_pabs (vars_tm, rh) + + val thm0 = let + val thm = FRESH_TY_VARS_RULE PMATCH_ROW_REMOVE_FUN_VAR + val thm = ISPEC v thm + val thm = ISPEC v' thm + val thm = ISPEC f thm + val thm = ISPEC g thm + val thm = ISPEC f' thm + val thm = ISPEC g' thm + + fun elim_conv vs = RATOR_CONV (RAND_CONV ( + (pairTools.PABS_INTRO_CONV vs) THENC + (DEPTH_CONV (pairLib.PAIRED_BETA_CONV ORELSEC BETA_CONV)) + )) + + val thm = CONV_RULE ((RAND_CONV o LHS_CONV) (elim_conv vars_tm)) thm + val thm = CONV_RULE ((RAND_CONV o RHS_CONV) (elim_conv vars'_tm)) thm + + val tm_eq = mk_eq(lhs (rand (concl thm)), mk_comb (row, v)) + val eq_thm = prove (tm_eq, + SIMP_TAC (rc_ss ssl) []) + + val thm = CONV_RULE (RAND_CONV (LHS_CONV (K eq_thm))) thm + in + thm + end + + val pre_tm = fst (dest_imp (concl thm0)) + val pre_thm = prove (pre_tm, SIMP_TAC (rc_ss ssl) []) + + val thm1 = MP thm0 pre_thm + in + thm1 + end + + + fun process_row (row, thm) = let + val row_thm = PMATCH_ROW_REMOVE_FUN_COL_AUX row handle HOL_ERR _ => + PMATCH_ROW_REMOVE_VAR_COL_AUX row + val thmA = PMATCH_EXTEND_BOTH + val thmB = HO_MATCH_MP thmA row_thm + val thmC = HO_MATCH_MP thmB thm + in + thmC + end + +(* + val row = el 1 (List.rev rows) + val thm = base_thm + val thm = thm0 +*) + + val base_thm = INST_TYPE [gamma |-> type_of t] (ISPECL [v, v'] PMATCH_EXTEND_BASE) + val thm0 = foldl process_row base_thm (List.rev rows) +in + thm0 +end handle HOL_ERR _ => raise UNCHANGED + + +(*------------------------*) +(* Combine auxiliary funs *) +(*------------------------*) + +fun PMATCH_SIMP_COLS_CONV_GEN ssl t = let + val cols = dest_PMATCH_COLS t +(* + val (col_v, col) = el 1 cols + val (vars, col_pat) = el 3 col +*) + fun do_match col_v (vars, col_pat) = let + val (sub, _) = match_term col_pat col_v + val vars_ok = List.all (fn x => (List.exists (aconv (#redex x)) vars)) sub + in + vars_ok + end handle HOL_ERR _ => false + + fun elim_col_ok (col_v, col) = + List.all (do_match col_v) col + + fun simp_col_ok (col_v, col) = let + val (c, args) = strip_comb col_v + val _ = if (List.null args) then failwith "elim_col instead" else () + + fun check_line (vars, pt) = + (List.exists (aconv pt) vars) orelse + (aconv (fst (strip_comb pt)) c) + in + List.all check_line col + end handle HOL_ERR _ => false + + fun process_col i col = if (elim_col_ok col) then + SOME (PMATCH_REMOVE_COL_AUX ssl i t) + else if (simp_col_ok col) then + SOME (PMATCH_REMOVE_FUN_AUX ssl i t) + else NONE + + val thm_opt = first_opt process_col cols +in + case thm_opt of NONE => raise UNCHANGED + | SOME thm => thm +end + +val PMATCH_SIMP_COLS_CONV = PMATCH_SIMP_COLS_CONV_GEN [] + + +(***********************************************) +(* Expand columns *) +(***********************************************) + +(* Sometimes not all rows of a PMATCH have the same number of + explicit columns. This can happen, if some patterns are + explicit pairs, while others are not. The following tries + to expand columns into explicit ones. *) + +fun PMATCH_EXPAND_COLS_CONV t = let + val (v, rows) = dest_PMATCH t + + val col_no_v = length (pairSyntax.strip_pair v) + val col_no = foldl (fn (r, m) => let + val (_, pt, _) = dest_PMATCH_ROW r + val m' = length (pairSyntax.strip_pair pt) + val m'' = if m' > m then m' else m + in m'' end) col_no_v rows + + fun split_var avoid cols l = let + fun splits acc no ty = if (no = 0) then List.rev (ty::acc) else + let + val (ty_s, ty') = pairSyntax.dest_prod ty + in + splits (ty_s::acc) (no - 1) ty' + end + + val types = splits [] (col_no - cols) (type_of l) + + val var_basename = fst (dest_var l) handle HOL_ERR _ => "v" + fun gen_var i ty = let + val n = var_basename ^ "_"^int_to_string i + in + mk_var (n, ty) + end + + val (new_vars, _) = quantHeuristicsTools.list_variant avoid (mapi gen_var types) + in + new_vars + end + + fun PMATCH_ROW_EXPAND_COLS row = let + val (vars_tm, pt, rh) = dest_PMATCH_ROW row + + val vars = pairSyntax.strip_pair vars_tm + val pts = pairSyntax.strip_pair pt + val cols = length pts + + val _ = if (cols < col_no) then () else failwith "nothing to do" + val l = last pts + + val _ = if (List.exists (aconv l) vars) then () else failwith "nothing to do" + + val avoids = vars @ free_vars pt @ free_vars rh + val new_vars = split_var avoids cols l + + val sub = [l |-> pairSyntax.list_mk_pair new_vars] + val pt' = Term.subst sub pt + val rh' = Term.subst sub rh + val vars_tm' = Term.subst sub vars_tm + val new_f = pairSyntax.mk_pabs(vars_tm', pairSyntax.mk_pair (pt', rh')) + + val eq_tm = mk_eq(rand row, new_f) + val eq_thm = prove (eq_tm, SIMP_TAC (rc_ss []) []) + + val thm = RATOR_CONV (RAND_CONV (K eq_thm)) (mk_comb (row, v)) + in + thm + end handle HOL_ERR _ => REFL (mk_comb (row, v)) + + fun process_row (row, thm) = let + val row_thm = PMATCH_ROW_EXPAND_COLS row + val thmA = PMATCH_EXTEND_BOTH + val thmB = HO_MATCH_MP thmA row_thm + val thmC = HO_MATCH_MP thmB thm + in + thmC + end + + val base_thm = INST_TYPE [gamma |-> type_of t] (ISPECL [v, v] PMATCH_EXTEND_BASE) + val thm0 = foldl process_row base_thm (List.rev rows) + + val thm1 = if (col_no_v >= col_no) then thm0 else let + val avoids = free_vars t + val vs = pairSyntax.strip_pair v + val l = List.last vs + val new_vars = split_var avoids col_no_v l + val new_vars_tm = pairSyntax.list_mk_pair new_vars + + val sub = [l |-> new_vars_tm] + + val tt = rhs (concl thm0) + val tt' = Term.subst sub tt + val tt'' = boolSyntax.mk_let (pairSyntax.mk_pabs (new_vars_tm, tt'), l) + + val thm_eq = prove (mk_eq (tt, tt''), + SIMP_TAC (rc_ss []) [LET_DEF]) + in + TRANS thm0 thm_eq + end +in + thm1 +end handle HOL_ERR _ => raise UNCHANGED + + +(***********************************************) +(* PMATCH_SIMP_CONV *) +(***********************************************) +fun PMATCH_SIMP_CONV_GEN rc = REPEATC (FIRST_CONV [ + CHANGED_CONV (PMATCH_CLEANUP_PVARS_CONV), + CHANGED_CONV (PMATCH_CLEANUP_CONV_GEN rc), + CHANGED_CONV (PMATCH_REMOVE_ARB_CONV_GEN rc), + CHANGED_CONV (PMATCH_SIMP_COLS_CONV_GEN rc)]) + +val PMATCH_SIMP_CONV = PMATCH_SIMP_CONV_GEN [] + + +(***********************************************) +(* Case_splits *) +(* This is work in progress *) +(***********************************************) + +fun STRIP_ABS_CONV conv t = + if (is_abs t) then ABS_CONV (STRIP_ABS_CONV conv) t else + conv t + +fun PMATCH_CASE_SPLIT_AUX col expand_thm conv t = let + val (v, rows) = dest_PMATCH t + val vs = pairSyntax.strip_pair v + + val arg = el (col+1) vs + val arg_v = genvar (type_of arg) + val vs' = pairSyntax.list_mk_pair (List.take (vs, col) @ (arg_v :: (List.drop (vs, col+1)))) + + val ff = let + val (x, xs) = strip_comb t + val t' = list_mk_comb(x, vs' :: (tl xs)) + in + mk_abs (arg_v, t') + end + + val thm0 = ISPEC arg (ISPEC ff expand_thm) + val thm1 = CONV_RULE (LHS_CONV BETA_CONV) thm0 + + fun is_case_conv_end t = + is_comb (fst (dest_comb t)) handle HOL_ERR _ => false + + fun case_conv conv t = + if not (is_case_conv_end t) then REFL t else + (RAND_CONV (STRIP_ABS_CONV conv) THENC RATOR_CONV (case_conv conv)) t + + val thm2 = CONV_RULE (RHS_CONV (case_conv (BETA_CONV THENC TRY_CONV conv))) thm1 +in + thm2 +end + +fun PMATCH_CASE_SPLIT_CONV_GEN ssl col t = let + val thm0 = QCHANGED_CONV ( + PMATCH_SIMP_CONV_GEN ssl) t handle HOL_ERR _ => REFL t + + val t' = rhs (concl thm0) + val (v, _) = dest_PMATCH t' + val vs = pairSyntax.strip_pair v + val ty = type_of (el (col+1) vs) + + val expand_thm = let + val case_def_thm = TypeBase.case_def_of ty + val nchotomy_thm = TypeBase.nchotomy_of ty + in + constrFamiliesLib.gen_case_expand_thm case_def_thm nchotomy_thm + end + + val thm1 = QCHANGED_CONV (PMATCH_CASE_SPLIT_AUX col expand_thm (PMATCH_SIMP_CONV_GEN ssl)) t' handle HOL_ERR _ => (REFL t') +in + TRANS thm0 thm1 +end + +end + + diff --git a/examples/deep_matches/deepMatchesScript.sml b/examples/deep_matches/deepMatchesScript.sml new file mode 100644 index 0000000000..c876f148aa --- /dev/null +++ b/examples/deep_matches/deepMatchesScript.sml @@ -0,0 +1,405 @@ +open HolKernel Parse boolLib bossLib; +open quantHeuristicsLib + +val _ = new_theory "deepMatches" + +(***************************************************) +(* Main Definitions *) +(***************************************************) + +(* rows of a pattern match are pairs of a pattern to match + against p and a result r. The result and pattern are linked + with free variables [v] bound in both. So it looks like + (\v. (p v, r v)) *) +val PMATCH_ROW_def = Define `PMATCH_ROW row i = + (if ?x. FST (row x) = i then + SOME (SND (row (@x. FST (row x) = i))) + else NONE)` + +(* We defined semantics or single rows. Let's extend + it to multiple ones, i.e. full pattern matches now *) +val PMATCH_INCOMPLETE_def = Define `PMATCH_INCOMPLETE = ARB` +val PMATCH_def = Define ` + (PMATCH v [] = PMATCH_INCOMPLETE) /\ + (PMATCH v (r::rs) = option_CASE (r v) (PMATCH v rs) I)` + + +val PMATCH_IS_EXHAUSTIVE_def = Define ` + PMATCH_IS_EXHAUSTIVE rs = ( + !v. EXISTS (\r. IS_SOME (r v)) rs)` + +val PMATCH_ROW_REDUNDANT_def = Define ` + PMATCH_ROW_REDUNDANT rs i = ( + (i < LENGTH rs /\ (!v. ?j. ((j < i) /\ + (IS_SOME ((EL i rs) v) ==> + IS_SOME ((EL j rs) v))))))` + +val PMATCH_REDUNDANT_ROWS_def = Define ` + PMATCH_REDUNDANT_ROWS rs = {i | (PMATCH_ROW_REDUNDANT rs i)}` + + +(***************************************************) +(* Rewrites *) +(***************************************************) + +val PMATCH_ROW_EQ_AUX = store_thm ("PMATCH_ROW_EQ_AUX", + ``((!i. (?x. (g x = i)) = (?x'. (g' x' = i))) /\ + (!x x'. (g x = g' x') ==> (f x = f' x'))) ==> + (PMATCH_ROW (\x:'a. (g x, f x)) = + PMATCH_ROW (\x':'b. (g' x', f' x')))``, +REPEAT STRIP_TAC THEN +SIMP_TAC std_ss [PMATCH_ROW_def, FUN_EQ_THM] THEN +CONV_TAC (RENAME_VARS_CONV ["i"]) THEN +GEN_TAC THEN +Q.PAT_ASSUM `!i. (_ = _)` (fn thm => ASSUME_TAC (Q.SPEC `i` thm)) THEN +Cases_on `?x'. g' x' = i` THEN ( + ASM_REWRITE_TAC[] +) THEN +FULL_SIMP_TAC std_ss [] THEN +SELECT_ELIM_TAC THEN +REPEAT STRIP_TAC THEN1 PROVE_TAC[] THEN +SELECT_ELIM_TAC THEN +REPEAT STRIP_TAC THEN1 PROVE_TAC[] THEN +PROVE_TAC[]) + +val PMATCH_ROW_EQ_NONE = store_thm ("PMATCH_ROW_EQ_NONE", + ``(PMATCH_ROW (\x. (g x, f x)) v = NONE) <=> + (!x. ~(g x = v))``, +SIMP_TAC std_ss [PMATCH_ROW_def]); + +val PMATCH_EVAL = store_thm ("PMATCH_EVAL", + ``(PMATCH v [] = PMATCH_INCOMPLETE) /\ + (PMATCH v ((PMATCH_ROW (\x. (g x, f x))) :: rs) = + if (?x. (g x = v)) then + (f (@x. g x = v)) else PMATCH v rs)``, + +SIMP_TAC std_ss [PMATCH_def] THEN +Cases_on `PMATCH_ROW (\x. (g x,f x)) v` THEN ( + FULL_SIMP_TAC std_ss [PMATCH_ROW_def] THEN + METIS_TAC[] +)) + +val PMATCH_EVAL_MATCH = store_thm ("PMATCH_EVAL_MATCH", + ``~(PMATCH_ROW (\x. (g x, f x)) v = NONE) ==> + (PMATCH v ((PMATCH_ROW (\x. (g x, f x))) :: rs) = + (f (@x. g x = v)))``, + +SIMP_TAC std_ss [PMATCH_def] THEN +Cases_on `PMATCH_ROW (\x. (g x,f x)) v` THEN ( + FULL_SIMP_TAC std_ss [PMATCH_ROW_def] THEN + METIS_TAC[] +)) + + +(***************************************************) +(* Changing rows and removing redundant ones *) +(***************************************************) + +(* An easy way is to start with an empty set of rows + and then step by step add rows to either one or both + sides till the desired correspondance is shown. This + is achieved by the following theorems. *) +val PMATCH_EXTEND_BASE = store_thm ("PMATCH_EXTEND_BASE", +``!v_old v_new. (PMATCH v_old [] = PMATCH v_new [])``, +SIMP_TAC std_ss [PMATCH_def]) + +val PMATCH_EXTEND_BOTH = store_thm ("PMATCH_EXTEND_BOTH", +``!v_old v_new rows_old rows_new r_old r_new. + (r_old v_old = r_new v_new) ==> + (PMATCH v_old rows_old = PMATCH v_new rows_new) ==> + (PMATCH v_old (r_old::rows_old) = PMATCH v_new (r_new :: rows_new))``, +SIMP_TAC std_ss [PMATCH_def]) + +val PMATCH_EXTEND_BOTH_ID = store_thm ("PMATCH_EXTEND_BOTH_ID", +``!v rows_old rows_new r. + (PMATCH v rows_old = PMATCH v rows_new) ==> + (PMATCH v (r::rows_old) = PMATCH v (r :: rows_new))``, +SIMP_TAC std_ss [PMATCH_def]) + +val PMATCH_EXTEND_OLD = store_thm ("PMATCH_EXTEND_OLD", +``!v_old v_new rows_old rows_new r_old. + (r_old v_old = NONE) ==> + (PMATCH v_old rows_old = PMATCH v_new rows_new) ==> + (PMATCH v_old (r_old::rows_old) = PMATCH v_new rows_new)``, +SIMP_TAC std_ss [PMATCH_def]) + + + +(***************************************************) +(* Equivalent sets of rows *) +(***************************************************) + +val PMATCH_EQUIV_ROWS_def = Define ` + PMATCH_EQUIV_ROWS v rows1 rows2 = ( + (PMATCH v rows1 = PMATCH v rows2) /\ + ((?r. MEM r rows1 /\ IS_SOME (r v)) = + (?r. MEM r rows2 /\ IS_SOME (r v))))` + +val PMATCH_EQUIV_ROWS_is_equiv_1 = store_thm ("PMATCH_EQUIV_ROWS_is_equiv_1", + ``(!rows. (PMATCH_EQUIV_ROWS v rows rows))``, +SIMP_TAC std_ss [PMATCH_EQUIV_ROWS_def]) + + +val PMATCH_EQUIV_ROWS_is_equiv_2 = store_thm ("PMATCH_EQUIV_ROWS_is_equiv_2", + ``(!rows1 rows2. ((PMATCH_EQUIV_ROWS v rows1 rows2) = + (PMATCH_EQUIV_ROWS v rows2 rows1)))``, +SIMP_TAC std_ss [PMATCH_EQUIV_ROWS_def] THEN METIS_TAC[]) + +val PMATCH_EQUIV_ROWS_is_equiv_3 = store_thm ("PMATCH_EQUIV_ROWS_is_equiv_3", + ``(!rows1 rows2 rows3. + (PMATCH_EQUIV_ROWS v rows1 rows2) ==> + (PMATCH_EQUIV_ROWS v rows2 rows3) ==> + (PMATCH_EQUIV_ROWS v rows1 rows3))``, +SIMP_TAC std_ss [PMATCH_EQUIV_ROWS_def]); + +val PMATCH_EQUIV_ROWS_MATCH = store_thm ("PMATCH_EQUIV_ROWS_MATCH", + ``PMATCH_EQUIV_ROWS v rows1 rows2 ==> + (PMATCH v rows1 = PMATCH v rows2)``, +SIMP_TAC std_ss [PMATCH_EQUIV_ROWS_def]) + +val PMATCH_APPEND_SEM = store_thm ("PMATCH_APPEND_SEM", + ``!v rows1 rows2. PMATCH v (rows1 ++ rows2) = ( + if (?r. MEM r rows1 /\ IS_SOME (r v)) then PMATCH v rows1 else PMATCH v rows2)``, +REPEAT GEN_TAC THEN +Induct_on `rows1` THEN1 ( + SIMP_TAC list_ss [] +) THEN +ASM_SIMP_TAC list_ss [PMATCH_def, RIGHT_AND_OVER_OR, EXISTS_OR_THM] THEN +GEN_TAC THEN +Cases_on `h v` THEN ( + ASM_SIMP_TAC std_ss [] +)) + +val PMATCH_APPEND = store_thm ("PMATCH_EXTEND_APPEND", +``!v rows1a rows1b rows2a rows2b. + (PMATCH_EQUIV_ROWS v rows1a rows1b) ==> + (PMATCH_EQUIV_ROWS v rows2a rows2b) ==> + (PMATCH_EQUIV_ROWS v (rows1a ++ rows2a) (rows1b ++ rows2b))``, +REPEAT STRIP_TAC THEN +FULL_SIMP_TAC list_ss [PMATCH_EQUIV_ROWS_def, RIGHT_AND_OVER_OR, + EXISTS_OR_THM, PMATCH_APPEND_SEM]) + + +(* If we have a row that matches, everything after it can be dropped *) +val PMATCH_ROWS_DROP_REDUNDANT_TRIVIAL_SOUNDNESS_EQUIV = store_thm ("PMATCH_ROWS_DROP_REDUNDANT_TRIVIAL_SOUNDNESS_EQUIV", +``!v rows n. ((n < LENGTH rows) /\ (IS_SOME ((EL n rows) v))) ==> + (PMATCH_EQUIV_ROWS v rows (TAKE (SUC n) rows))``, + +REPEAT STRIP_TAC THEN +Tactical.REVERSE (`PMATCH_EQUIV_ROWS v (TAKE (SUC n) rows ++ DROP (SUC n) rows) (TAKE (SUC n) rows)` by ALL_TAC) THEN1 ( + FULL_SIMP_TAC list_ss [] +) THEN + +SIMP_TAC std_ss [PMATCH_EQUIV_ROWS_def, PMATCH_APPEND_SEM] THEN +SIMP_TAC list_ss [] THEN + +Tactical.REVERSE (`?r. MEM r (TAKE (SUC n) rows) /\ IS_SOME (r v)` by ALL_TAC) THEN1 ( + METIS_TAC[] +) THEN +Q.EXISTS_TAC `EL n (TAKE (SUC n) rows)` THEN +ASM_SIMP_TAC list_ss [rich_listTheory.MEM_TAKE, rich_listTheory.EL_MEM, + listTheory.LENGTH_TAKE, rich_listTheory.EL_TAKE]); + + +val PMATCH_ROWS_DROP_REDUNDANT_TRIVIAL_SOUNDNESS = store_thm ("PMATCH_ROWS_DROP_REDUNDANT_TRIVIAL_SOUNDNESS", +``!v rows n. ((n < LENGTH rows) /\ (IS_SOME ((EL n rows) v))) ==> + (PMATCH v rows = PMATCH v (TAKE (SUC n) rows))``, + +REPEAT STRIP_TAC THEN +MATCH_MP_TAC PMATCH_EQUIV_ROWS_MATCH THEN +MATCH_MP_TAC PMATCH_ROWS_DROP_REDUNDANT_TRIVIAL_SOUNDNESS_EQUIV THEN +ASM_REWRITE_TAC[]) + + +val PMATCH_REMOVE_ARB = store_thm ("PMATCH_REMOVE_ARB", +``(PMATCH v (SNOC (PMATCH_ROW (\x. (f x, ARB))) rows) = + PMATCH v rows)``, + +Induct_on `rows` THENL [ + SIMP_TAC list_ss [PMATCH_def, PMATCH_ROW_def] THEN + Cases_on `?x. f x = v` THEN ( + ASM_SIMP_TAC std_ss [PMATCH_INCOMPLETE_def] + ), + + ASM_SIMP_TAC list_ss [PMATCH_def] +]) + +(* ARB rows can be removed, since a match failiure is the same + as ARB *) +val PMATCH_REMOVE_ARB_NO_OVERLAP = store_thm ("PMATCH_REMOVE_ARB_NO_OVERLAP", +``!v ff rows1 rows2. + (!x. (v = ff x) ==> EVERY (\r. (r (ff x) = NONE)) rows2) ==> + (PMATCH v (rows1 ++ ((PMATCH_ROW (\x. (ff x, ARB))) :: rows2)) = + PMATCH v (rows1 ++ rows2))``, + +REPEAT STRIP_TAC THEN +Tactical.REVERSE (Induct_on `rows1`) THEN ( + ASM_SIMP_TAC list_ss [PMATCH_def] +) THEN + +ASM_SIMP_TAC list_ss [PMATCH_def, PMATCH_ROW_def] THEN +Cases_on `?x. ff x = v` THEN ( + ASM_SIMP_TAC std_ss [PMATCH_INCOMPLETE_def] +) THEN +FULL_SIMP_TAC std_ss [] THEN +Q.PAT_ASSUM `_ = v` (ASSUME_TAC o GSYM) THEN +Induct_on `rows2` THEN ( + FULL_SIMP_TAC list_ss [PMATCH_def, PMATCH_INCOMPLETE_def] +)) + + + +(* Add an injective function to the pattern and the value. + This can be used to eliminate constructors. *) +val PMATCH_ROW_REMOVE_FUN = store_thm ("PMATCH_ROW_REMOVE_FUN", +``!ff v f g. (!x y. (ff x = ff y) ==> (x = y)) ==> + + (PMATCH_ROW (\x. (ff (f x), g x)) (ff v) = + PMATCH_ROW (\x. (f x, g x)) v)``, + +REPEAT STRIP_TAC THEN +`!x y. (ff x = ff y) = (x = y)` by PROVE_TAC[] THEN +ASM_SIMP_TAC std_ss [PMATCH_ROW_def]) + + +val PMATCH_ROW_REMOVE_FUN_EXT = store_thm ("PMATCH_ROW_REMOVE_FUN_EXT", +``!ff v f f' g g'. + + ((?x. f' x = ff v) = (?x. f x = v)) ==> + (!x x'. (f' x = ff v) ==> (f x' = v) ==> (g x v = g' x')) ==> + + (PMATCH_ROW (\x. (f' x, g x v)) (ff v) = + PMATCH_ROW (\x. (f x, g' x)) v)``, + +REPEAT STRIP_TAC THEN +ASM_SIMP_TAC std_ss [PMATCH_ROW_def] THEN +Cases_on `?x. f x = v` THEN ( + ASM_REWRITE_TAC[] +) THEN +SELECT_ELIM_TAC THEN +ASM_REWRITE_TAC [] THEN +REPEAT STRIP_TAC THEN +SELECT_ELIM_TAC THEN +ASM_REWRITE_TAC [] THEN +REPEAT STRIP_TAC THEN +PROVE_TAC[]) + + + +(* The following lemma looks rather complicated. It is + intended to work together with PMATCH_ROW_REMOVE_FUN to + propagate information in the var cases. + + as an example consider + + val t = ``PMATCH (SOME x, y) [ + PMATCH_ROW (\ x. ((SOME x, 0), SOME (x + y))); + PMATCH_ROW (\ (x', y). ((x', y), x')) + ]`` + + We want to simplify this to + + val t' = ``PMATCH (x, y) [ + PMATCH_ROW (\ x. ((x, 0), SOME (x + y))); + PMATCH_ROW (\ (x'', y). ((x'', y), SOME x'')) + ]`` + + This is done via PMATCH_ROWS_SIMP and PMATCH_ROWS_SIMP_SOUNDNESS. + We need to show that the rows correspond to each other. + + For the first row, PMATCH_ROW_REMOVE_FUN is used with + + v := (x, y) + ff (x, y) := (SOME x, y) + + f x := (x, 0) + g x := SOME (x + y) + + + For the second row, PMATCH_ROW_REMOVE_FUN is used with + + v := (SOME x, y) + v' := (x, y) + f (x', y) := (x', y) + g (x', y) := x' + f' (x'', y) = (x'', y) + g' (x'', y) := (SOME x'', y) +*) + +val PMATCH_ROW_REMOVE_FUN_VAR = store_thm ("PMATCH_ROW_REMOVE_FUN_VAR", +``!v v' f g f' g'. + ((!x'. (f' x' = v') = (f (g' x') = v)) /\ + ((!x. (f x = v) ==> ?x'. g' x' = x)) /\ + ((!x y. (f x = f y) ==> (x = y)))) ==> + (PMATCH_ROW (\x. (f x, g x)) v = + PMATCH_ROW (\x'. (f' x'), g (g' x')) v')``, + +REPEAT STRIP_TAC THEN +ASM_SIMP_TAC std_ss [PMATCH_ROW_def] THEN +`(?x'. f (g' x') = v) = (?x. f x = v)` by ALL_TAC THEN1 ( + METIS_TAC[] +) THEN +Cases_on `?x. f x = v` THEN ( + ASM_SIMP_TAC std_ss [] +) THEN + +SELECT_ELIM_TAC THEN +ASM_SIMP_TAC std_ss [] THEN +SELECT_ELIM_TAC THEN +REPEAT STRIP_TAC THEN ( + METIS_TAC[] +)); + + + +(***************************************************) +(* THEOREMS ABOUT FLATTENING *) +(***************************************************) + +val PMATCH_FLATTEN_FUN_def = Define ` + PMATCH_FLATTEN_FUN f g h v = + if (?x. g x = v) then h (f (@x. g x = v)) else NONE` + +val PMATCH_FLATTEN_THM_AUX = prove ( + ``(PMATCH v [PMATCH_ROW (\x. (g x, (PMATCH (f x) (MAP (\r. r x) rows'))))]) = + (PMATCH v (MAP (\r. (PMATCH_FLATTEN_FUN f g) (r (@x. g x = v))) rows'))``, + +Induct_on `rows'` THEN1 ( + Cases_on `?x. g x = v` THEN + ASM_SIMP_TAC list_ss [PMATCH_def, PMATCH_ROW_def] +) THEN + +Cases_on `?x. g x = v` THENL [ + GEN_TAC THEN + ASM_SIMP_TAC list_ss [PMATCH_def, PMATCH_ROW_def, PMATCH_FLATTEN_FUN_def] THEN + FULL_SIMP_TAC list_ss [PMATCH_def, PMATCH_ROW_def], + + GEN_TAC THEN + `!r. (PMATCH_FLATTEN_FUN f g r v) = NONE` by ALL_TAC THEN1 ( + ASM_SIMP_TAC std_ss [PMATCH_FLATTEN_FUN_def] + ) THEN + FULL_SIMP_TAC list_ss [PMATCH_def, PMATCH_ROW_def] +]) + + +val PMATCH_FLATTEN_FUN_PMATCH_ROW = store_thm ("PMATCH_FLATTEN_FUN_PMATCH_ROW", +``(!x1 x2. (g x1 = g x2) ==> (x1 = x2)) ==> + (!x y. (g'' x = y) = (g' x = f y)) ==> ( + PMATCH_FLATTEN_FUN f g (PMATCH_ROW (\x'. (g' x', f' x'))) = + PMATCH_ROW (\x. (g (g'' x), f' x)))``, + +REPEAT STRIP_TAC THEN +SIMP_TAC std_ss [PMATCH_FLATTEN_FUN_def, FUN_EQ_THM, PMATCH_ROW_def] THEN +GEN_TAC THEN +Tactical.REVERSE (Cases_on `?x'. g x' = x`) THEN1 ( + `~(?x'. g (g'' x') = x)` by METIS_TAC[] THEN + ASM_REWRITE_TAC[] +) THEN +FULL_SIMP_TAC std_ss [] THEN +`!x''. (g x'' = x) = (x'' = x')` by METIS_TAC[] THEN +ASM_SIMP_TAC std_ss [] THEN +METIS_TAC[]) + + +val _ = export_theory() + diff --git a/examples/deep_matches/deepMatchesSyntax.sig b/examples/deep_matches/deepMatchesSyntax.sig new file mode 100644 index 0000000000..8642d89c37 --- /dev/null +++ b/examples/deep_matches/deepMatchesSyntax.sig @@ -0,0 +1,71 @@ +signature deepMatchesSyntax = +sig + include Abbrev + + val PMATCH_tm : term + val PMATCH_ROW_tm : term + + (* auxiliary function that introduces fresh + typevars for all type-vars used by + free vars of a thm *) + val FRESH_TY_VARS_RULE : rule + + + (******************) + (* PMATCH_ROW *) + (******************) + + (* dest_PMATCH_ROW ``PMATCH_ROW (\(x, y). (p x y, rh x y)`` + returns (``(x,y)``, ``p x y``, ``rh x y``). *) + val dest_PMATCH_ROW : term -> (term * term * term) + + val is_PMATCH_ROW : term -> bool + + (* [mk_PMATCH_ROW vars p rh] constructs the term + ``PMATCH_ROW (\vars. (p vars, rh vars))``. *) + val mk_PMATCH_ROW : term list -> term -> term -> term + + (* [PMATCH_ROW_PABS_ELIM_CONV ``PMATCH_ROW (\(v1, ... vn). ( p (v1, + ... vn), rh (v1, ... vn))``] removes the pair [(v1, ... vn)] and + replaces the paired lambda abstraction with a normal lambda + abstraction. It returns a theorem stating the equivalence as + well as the original varstruct removed. *) + val PMATCH_ROW_PABS_ELIM_CONV : term -> (term * thm) + + (* [PMATCH_ROW_PABS_INTRO_CONV vars t] reintroduces + paired abstraction again after being removed by e.g. + [PMATCH_ROW_PABS_ELIM_CONV]. It uses [vars] for the newly + introduced varstruct. *) + val PMATCH_ROW_PABS_INTRO_CONV : term -> term -> thm + + + (******************) + (* PMATCH *) + (******************) + + (* [dest_PMATCH ``PMATCH v rows``] returns (``v``, ``rows``). *) + val dest_PMATCH : term -> (term * term list) + + val is_PMATCH : term -> bool + + val mk_PMATCH : term -> term -> term + + (* [dest_PMATCH_COLS ``PMATCH v rows``] tries to extract the columns + of the pattern match. Each column consists of the value of v, + the free variables in the pattern and the column of the pattern + for each row. *) + val dest_PMATCH_COLS : term -> (term * (term list * term) list) list + + + (******************) + (* Pretty printer *) + (******************) + + (* A pretty printer is defined and added for PMATCH. + Whether it is use can be controled via the trace + + "use pmatch_pp" + *) + + +end diff --git a/examples/deep_matches/deepMatchesSyntax.sml b/examples/deep_matches/deepMatchesSyntax.sml new file mode 100644 index 0000000000..e4dba29c11 --- /dev/null +++ b/examples/deep_matches/deepMatchesSyntax.sml @@ -0,0 +1,167 @@ +structure deepMatchesSyntax :> deepMatchesSyntax = +struct + +open deepMatchesTheory bossLib + + +(***********************************************) +(* Terms *) +(***********************************************) + +val PMATCH_ROW_tm = ``PMATCH_ROW`` +val PMATCH_tm = ``PMATCH`` + +(***********************************************) +(* Matching support *) +(***********************************************) + +val thm = PMATCH_REMOVE_ARB_NO_OVERLAP + +fun FRESH_TY_VARS_RULE thm = let + val (vars0, _) = strip_forall (concl thm) + val vars1 = free_vars (concl thm) + val vars = vars0 @ vars1 + val tys = type_varsl (map type_of vars) + val subst = map (fn ty => (ty |-> gen_tyvar ())) tys +in + INST_TYPE subst thm +end + +(***********************************************) +(* PMATCH_ROW *) +(***********************************************) + +fun dest_PMATCH_ROW row = let + val (f, args) = strip_comb row + val _ = if (same_const f PMATCH_ROW_tm) andalso (List.length args = 1) then () else failwith "dest_PMATCH_ROW" + + val arg = hd args + + val (vars_tm, prh) = pairSyntax.dest_pabs arg + val (p, rh) = pairSyntax.dest_pair prh +in + (vars_tm, p, rh) +end + +fun is_PMATCH_ROW t = can dest_PMATCH_ROW t + +fun mk_PMATCH_ROW vars p rh = let + val prh = pairSyntax.mk_pair(p, rh) + val pabs = case vars of + [] => mk_abs (genvar ``:unit``, prh) + | [v] => mk_abs (v, prh) + | _ => pairSyntax.mk_pabs (pairSyntax.list_mk_pair vars, prh) + in + mk_icomb (PMATCH_ROW_tm, pabs) + end + + +fun PMATCH_ROW_PABS_ELIM_CONV r = let + val (vars, _, _) = dest_PMATCH_ROW r + val thm = (RAND_CONV pairTools.PABS_ELIM_CONV) r +in + (vars, thm) +end + +fun PMATCH_ROW_PABS_INTRO_CONV vars r = let + val _ = if (is_PMATCH_ROW r) then () else failwith "PMATCH_ROW_PABS_INTRO_CONV" + val thm = (RAND_CONV (pairTools.PABS_INTRO_CONV vars)) r +in + thm +end + + + +(***********************************************) +(* PMATCH *) +(***********************************************) + +fun mk_PMATCH v rows = let + val rows_ty = let + val ty0 = type_of PMATCH_tm + val (arg_tys, _) = wfrecUtils.strip_fun_type ty0 + in el 2 arg_tys end + + val ty_subst = match_type rows_ty (type_of rows) + val b_tm = inst ty_subst PMATCH_tm + val t1 = mk_comb (b_tm, v) + val t2 = mk_comb (t1, rows) +in + t2 +end + +fun dest_PMATCH t = let + val (f, args) = strip_comb t + val _ = if (same_const f PMATCH_tm) andalso (List.length args = 2) then () else failwith "dest_PMATCH" + val (l, _) = listSyntax.dest_list (el 2 args) +in + (el 1 args, l) +end + +fun is_PMATCH t = can dest_PMATCH t + +fun dest_PMATCH_COLS t = let + val (v, rows) = dest_PMATCH t + val vs = pairSyntax.strip_pair v + + fun split_row r = let + val (vars_tm, pt, rh) = dest_PMATCH_ROW r + val vars = pairSyntax.strip_pair vars_tm + val pts = pairSyntax.strip_pair pt + in + List.map (fn x => (vars, x)) pts + end + val rows' = map split_row rows + + fun get_cols acc vs rows = case vs of + [] => List.rev acc + | (v::vs') => let + val col = map hd rows + val rows' = map tl rows + in + get_cols ((v, col)::acc) vs' rows' + end + val cols = get_cols [] vs rows' +in + cols +end + + + +(***********************************************) +(* Pretty Printing *) +(***********************************************) + +val use_pmatch_pp = ref true +val _ = Feedback.register_btrace ("use pmatch_pp", use_pmatch_pp); + +fun pmatch_printer GS backend sys (ppfns:term_pp_types.ppstream_funs) gravs d t = + let + open Portable term_pp_types smpp + infix >> + val _ = if (!use_pmatch_pp) then () else raise term_pp_types.UserPP_Failed + val {add_string,add_break,ublock,add_newline,ustyle,...} = ppfns + val (v,rows) = dest_PMATCH t; + + val rows' = map dest_PMATCH_ROW rows + + fun pp_row (vars, pat, rh) = ( + term_pp_utils.record_bvars (pairSyntax.strip_pair vars) ( + ublock PP.CONSISTENT 0 ( + add_string "|" >> add_break (1, 0) >> + sys (Top, Top, Top) (d - 1) pat >> + add_break (1, 0) >> add_string "=>" >> add_break (1, 0) >> + sys (Top, Top, Top) (d - 1) rh + )) + ) + in + (ublock PP.CONSISTENT 2 (add_string "CASE" >> add_break(1,2) >> + sys (Top, Top, Top) (d - 1) v >> + add_break(1,0) >> add_string "OF")) >> + add_break (1, 0) >> + smpp.pr_list pp_row (add_break (0, 0)) rows' + end handle HOL_ERR _ => raise term_pp_types.UserPP_Failed; + +val _ = add_user_printer ("PMATCH", ``PMATCH v l``, pmatch_printer); + +end From c231f2c949505030530fc0659509837d8fc596c9 Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Thu, 4 Dec 2014 16:00:57 +0000 Subject: [PATCH 040/718] Expose conversion in x64_stepLib. --- examples/l3-machine-code/x64/step/x64_stepLib.sig | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/l3-machine-code/x64/step/x64_stepLib.sig b/examples/l3-machine-code/x64/step/x64_stepLib.sig index 48dde76cfd..fa1b48a09a 100644 --- a/examples/l3-machine-code/x64/step/x64_stepLib.sig +++ b/examples/l3-machine-code/x64/step/x64_stepLib.sig @@ -1,5 +1,6 @@ signature x64_stepLib = sig + val x64_CONV: Conv.conv val x64_step: Term.term list -> Thm.thm val x64_step_hex: string -> Thm.thm val x64_step_code: string quotation -> Thm.thm list From 29fbf94c125075ca301e9b57e929a3089ce193c6 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Mon, 8 Dec 2014 10:52:08 +1100 Subject: [PATCH 041/718] Remove HOL88-isms from FREEZE_THEN's doc-file. Prompted by question from Rob Arthan on hol-info mailing list. --- help/Docfiles/Tactic.FREEZE_THEN.doc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/help/Docfiles/Tactic.FREEZE_THEN.doc b/help/Docfiles/Tactic.FREEZE_THEN.doc index d8ae4e5f72..3a2eeed75a 100644 --- a/help/Docfiles/Tactic.FREEZE_THEN.doc +++ b/help/Docfiles/Tactic.FREEZE_THEN.doc @@ -35,7 +35,7 @@ tactic arises if the hypotheses of the theorem are not alpha-convertible to assumptions of the goal. \EXAMPLE -Given the goal {([ "b < c"; "a < b" ], "(SUC a) <= c")}, and the +Given the goal {([ ``b < c``, ``a < b`` ], ``SUC a <= c``)}, and the specialized variant of the theorem {LESS_TRANS}: { th = |- !p. a < b /\ b < p ==> a < p @@ -43,7 +43,7 @@ specialized variant of the theorem {LESS_TRANS}: {IMP_RES_TAC th} will generate several unneeded assumptions: { {b < c, a < b, a < c, !p. c < p ==> b < p, !a'. a' < a ==> a' < b} - ?- (SUC a) <= c + ?- SUC a <= c } which can be avoided by first `freezing' the theorem, using the tactic @@ -52,7 +52,7 @@ the tactic } This prevents the variables {a} and {b} from being instantiated. { - {b < c, a < b, a < c} ?- (SUC a) <= c + {b < c, a < b, a < c} ?- SUC a <= c } From 61756ea72f601162487f0ee463f6b2a70104e452 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Mon, 8 Dec 2014 10:58:12 +1100 Subject: [PATCH 042/718] Changes to goal assumptions in FREEZE_THEN described more accurately --- help/Docfiles/Tactic.FREEZE_THEN.doc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/help/Docfiles/Tactic.FREEZE_THEN.doc b/help/Docfiles/Tactic.FREEZE_THEN.doc index 3a2eeed75a..9ad51286fe 100644 --- a/help/Docfiles/Tactic.FREEZE_THEN.doc +++ b/help/Docfiles/Tactic.FREEZE_THEN.doc @@ -13,16 +13,16 @@ theorem-tactic, selective, free. and a theorem {(A1 |- w)} as arguments. The tactic-generating function {f} is applied to the theorem {(w |- w)}. If this tactic generates the subgoal: { - A ?- t + A0 ?- t ========= f (w |- w) - A ?- t1 + A ?- t1 } then applying {FREEZE_THEN f (A1 |- w)} -to the goal {(A ?- t)} produces the subgoal: +to the goal {(A0 ?- t)} produces the subgoal: { - A ?- t - ========= FREEZE_THEN f (A1 |- w) - A ?- t1 + A0 ?- t + =================== FREEZE_THEN f (A1 |- w) + A - {w}, A1 ?- t1 } Since the term {w} is a hypothesis of the argument to the function {f}, none of the free variables present in {w} may be From a582063128d2ab97cbab179918eed9cfa0a1e86f Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Mon, 8 Dec 2014 11:37:29 +1100 Subject: [PATCH 043/718] Remove calls to print_theory in enumfset/script files. print_theory is fine to call interactively, but just adds verbiage when done as part of a build. Having done a build, looking at a Theory.sig file is a good way to see what one has achieved. --- src/enumfset/enumeralScript.sml | 13 ++++++------- src/enumfset/fmapalScript.sml | 17 ++++++++--------- src/enumfset/inttoScript.sml | 1 - src/enumfset/tcScript.sml | 7 +++---- src/enumfset/totoScript.sml | 1 - src/enumfset/wotScript.sml | 1 - 6 files changed, 17 insertions(+), 23 deletions(-) diff --git a/src/enumfset/enumeralScript.sml b/src/enumfset/enumeralScript.sml index 091ca90030..9078879d67 100644 --- a/src/enumfset/enumeralScript.sml +++ b/src/enumfset/enumeralScript.sml @@ -102,7 +102,7 @@ val K2 = Define`K2 (a:'a) = 2`; val bt_rev_size = maybe_thm ("bt_rev_size", Term `!ft bl:'a bl. bl_size K2 (bt_rev ft bl) = bt_size K2 ft + bl_size K2 bl`, -Induct THEN +Induct THEN ASM_REWRITE_TAC [bl_size_def, bt_size_def, K2,bt_rev,arithmeticTheory.ADD] THEN SIMP_TAC arith_ss []); @@ -167,7 +167,7 @@ val smerge_set = maybe_thm ("smerge_set", ``!cmp:'a toto l m. (set (smerge cmp l m) = set l UNION set m)``, GEN_TAC THEN Induct THEN SRW_TAC [] [smerge, smerge_nil] THEN -Induct_on `m` THEN +Induct_on `m` THEN SRW_TAC [] [smerge, smerge_nil] THEN Cases_on `apto cmp h h'` THENL [ALL_TAC, `h = h'` by IMP_RES_TAC toto_equal_eq, ALL_TAC] THEN @@ -179,7 +179,7 @@ val smerge_OL = store_thm ("smerge_OL", ``!cmp:'a toto l m. OL cmp l /\ OL cmp m ==> OL cmp (smerge cmp l m)``, GEN_TAC THEN Induct THEN SRW_TAC [] [smerge, OL, smerge_nil] THEN -Induct_on `m` THEN +Induct_on `m` THEN SRW_TAC [] [smerge, OL, smerge_nil] THEN Cases_on `apto cmp h h'` THEN SRW_TAC [] [OL] THENL [`MEM p l \/ MEM p (h' :: m)` @@ -212,7 +212,7 @@ val OL_sublists = Define val OL_sublists_ind = theorem "OL_sublists_ind"; -(* OL_sublists_ind = |- !P. (!cmp. P cmp []) /\ +(* OL_sublists_ind = |- !P. (!cmp. P cmp []) /\ (!cmp lol. P cmp lol ==> P cmp (NONE::lol)) /\ (!cmp m lol. P cmp lol ==> P cmp (SOME m::lol)) ==> !v v1. P v v1 *) @@ -663,7 +663,7 @@ val OU_EMPTY = store_thm ("OU_EMPTY", ``!cmp:'a toto t:'a set. OU cmp t {} = t``, REWRITE_TAC [OU, NOT_IN_EMPTY, UNION_EMPTY, GSPEC_ID]); -val sing_UO = maybe_thm ("sing_UO",``!cmp:'a toto x:'a t:'a set. +val sing_UO = maybe_thm ("sing_UO",``!cmp:'a toto x:'a t:'a set. {x} UNION {y | y IN t /\ (apto cmp x y = LESS)} = UO cmp {x} t``, RW_TAC bool_ss [UO, IN_SING]); @@ -673,7 +673,7 @@ val LESS_UO_LEM = store_thm ("LESS_UO_LEM", RW_TAC bool_ss [GSYM sing_UO] THEN EQ_TAC THEN REWRITE_TAC [IN_UNION, IN_SING] THEN CONV_TAC (ONCE_DEPTH_CONV SET_SPEC_CONV) THENL -[CONV_TAC LEFT_IMP_FORALL_CONV THEN +[CONV_TAC LEFT_IMP_FORALL_CONV THEN Q.EXISTS_TAC `x` THEN RW_TAC bool_ss [] ,REPEAT STRIP_TAC THENL [AR, IMP_RES_TAC toto_trans_less] ]); @@ -1167,6 +1167,5 @@ val set_OWL_thm = store_thm ("set_OWL_thm", REWRITE_TAC [OWL, incr_ssort_set, incr_ssort_OL]); val _ = export_theory (); -val _ = print_theory "-"; end; diff --git a/src/enumfset/fmapalScript.sml b/src/enumfset/fmapalScript.sml index 7e725bb591..4b55ae8d5c 100644 --- a/src/enumfset/fmapalScript.sml +++ b/src/enumfset/fmapalScript.sml @@ -248,7 +248,7 @@ val ORL_single_valued = prove (Term`!cmp l. ORL cmp l ==> !x:'a y:'b z. MEM (x,y) l /\ MEM (x,z) l ==> (z = y)`, GEN_TAC THEN Induct THENL [REWRITE_TAC [MEM] -,P_PGEN_TAC (Term`p:'a,q:'b`) THEN +,P_PGEN_TAC (Term`p:'a,q:'b`) THEN DISCH_TAC THEN IMP_RES_TAC ORL THEN REPEAT GEN_TAC THEN Cases_on `apto cmp x p` THEN IMP_RES_TAC toto_glneq THEN IMP_RES_TAC toto_equal_imp_eq THEN @@ -382,7 +382,7 @@ MATCH_MP_TAC assocv_merge THEN AR); val incr_merge = Define` (incr_merge cmp (l:('a#'b)list) [] = [SOME l]) /\ (incr_merge cmp (l:('a#'b)list) (NONE :: lol) = SOME l :: lol) -/\ (incr_merge cmp (l:('a#'b)list) (SOME m :: lol) = +/\ (incr_merge cmp (l:('a#'b)list) (SOME m :: lol) = NONE :: incr_merge cmp (merge cmp l m) lol)`; val ORL_sublists = Define`(ORL_sublists cmp ([]:('a#'b)list option list) = T) @@ -676,7 +676,7 @@ SRW_TAC [] [assocv_APPEND, incr_build, merge_out] THENL val incr_sort_fun = maybe_thm ("incr_sort_fun", ``!cmp: 'a toto l:('a#'b)list. assocv (incr_sort cmp l) = assocv l``, REPEAT GEN_TAC THEN REWRITE_TAC [incr_sort, incr_flat] THEN -Q.SUBGOAL_THEN `assocv l = assocv ([] ++ l)` SUBST1_TAC +Q.SUBGOAL_THEN `assocv l = assocv ([] ++ l)` SUBST1_TAC THEN1 REWRITE_TAC [APPEND] THEN MATCH_MP_TAC assocv_incr_build THEN REWRITE_TAC [ORL]); @@ -1402,7 +1402,7 @@ val MEM_IN_DOM_fmap = maybe_thm ("MEM_IN_DOM_fmap", GEN_TAC THEN Induct THENL [REWRITE_TAC [FDOM_FEMPTY, fmap_rec, NOT_IN_EMPTY, MEM] ,P_PGEN_TAC ``x:'a,y:'b`` THEN - DISCH_THEN (fn orlc => + DISCH_THEN (fn orlc => STRIP_ASSUME_TAC (MATCH_MP (CONJUNCT1 ORL_NOT_MEM) orlc) THEN STRIP_ASSUME_TAC (REWRITE_RULE [ORL] orlc)) THEN SRW_TAC [] [fmap_rec, FAPPLY_FUPDATE_THM, FDOM_FUPDATE] THEN @@ -1564,8 +1564,8 @@ val bl_to_bt_fmap = maybe_thm ("bl_to_bt_fmap", ``!cmp b:('a#'b)bl. FMAPAL cmp (bl_to_bt b) = bl_to_fmap cmp b``, REWRITE_TAC [bl_to_bt, bl_rev_fmap_lem, bt_to_fmap, FEMPTY_OFU]); -(* Imitating enumeralTheory as usual, we next aim to show that building a - bl from a list does the same, and to begin with that +(* Imitating enumeralTheory as usual, we next aim to show that building a + bl from a list does the same, and to begin with that LESS_ALL cmp x (FDOM (bl_to_fmap cmp b)) ==> (bl_to_fmap cmp (BL_CONS (x,y) b) = bl_to_fmap cmp b |+ (x,y), @@ -1703,7 +1703,7 @@ REWRITE_TAC [combinTheory.o_THM] THEN Induct THENL val FDOM_assocv = maybe_thm ("FDOM_assocv", ``!l:('a#'b)list. FDOM (unlookup (assocv l)) = set (MAP FST l)``, -GEN_TAC THEN +GEN_TAC THEN MP_TAC (ISPEC ``MAP FST (l:('a#'b)list)`` FINITE_LIST_TO_SET) THEN REWRITE_TAC [GSYM IS_SOME_assocv] THEN MATCH_ACCEPT_TAC unlookup_FDOM); @@ -1726,7 +1726,7 @@ val fmap_ALT = maybe_thm ("fmap_ALT", ``!l:('a#'b)list. fmap l = unlookup (assocv l)``, REWRITE_TAC [FUPDATE_ALT, fmap_EXT] THEN GEN_TAC THEN CONJ_TAC THENL [REWRITE_TAC [fmap_FDOM, FDOM_assocv] -,GEN_TAC THEN +,GEN_TAC THEN REWRITE_TAC [fmap_FDOM, fmap, SPECIFICATION] THEN Induct_on `l` THENL [REWRITE_TAC [MAP, LIST_TO_SET_THM, rrs NOT_IN_EMPTY] @@ -2516,6 +2516,5 @@ val fmap_ORWL_thm = store_thm ("fmap_ORWL_thm", REWRITE_TAC [ORWL, incr_sort_fmap, incr_sort_ORL]); val _ = export_theory (); -val _ = print_theory "-"; end; diff --git a/src/enumfset/inttoScript.sml b/src/enumfset/inttoScript.sml index 5c0e0e0b7d..f9229adb39 100644 --- a/src/enumfset/inttoScript.sml +++ b/src/enumfset/inttoScript.sml @@ -124,6 +124,5 @@ val ZERO_eq_neg_ZERO_thm = store_thm ("ZERO_eq_neg_ZERO_thm", SRW_TAC [] [TO_of_LinearOrder, intOrd, GSYM arithmeticTheory.ALT_ZERO]); val _ = export_theory (); -val _ = print_theory "-"; end; diff --git a/src/enumfset/tcScript.sml b/src/enumfset/tcScript.sml index ad6f007683..34517f612e 100644 --- a/src/enumfset/tcScript.sml +++ b/src/enumfset/tcScript.sml @@ -400,7 +400,7 @@ GEN_TAC THEN REPEAT (CONV_TAC FUN_EQ_CONV THEN GEN_TAC) THEN EQ_TAC THENL MATCH_MP_TAC RTC_MONOTONE THEN REWRITE_TAC [BRESTR, DRESTR, RRESTR] THEN REPEAT STRIP_TAC THEN AR ,MATCH_MP_TAC TC_INDUCT THEN REWRITE_TAC [subTC] THEN - REPEAT STRIP_TAC + REPEAT STRIP_TAC THEN1 AR THEN DISJ2_TAC THENL [Q.EXISTS_TAC `y` THEN Q.EXISTS_TAC `y` THEN ASM_REWRITE_TAC [RTC_REFL, IN_RDOM] THEN Q.EXISTS_TAC `z` THEN AR @@ -552,11 +552,11 @@ HO_MATCH_MP_TAC FINITE_INDUCT THEN CONJ_TAC THENL val subTC_FDOM = store_thm ("subTC_FDOM", ``!g R:'a reln. (subTC R (RDOM R) = FMAP_TO_RELN g) ==> (subTC R (FDOM g) = subTC R (RDOM R))``, REPEAT STRIP_TAC THEN -Q.SUBGOAL_THEN `RDOM R SUBSET FDOM g` +Q.SUBGOAL_THEN `RDOM R SUBSET FDOM g` (SUBST1_TAC o GSYM o REWRITE_RULE [SUBSET_UNION_ABSORPTION]) THENL [Q.SUBGOAL_THEN `RDOM (subTC R (RDOM R)) = RDOM R` (SUBST1_TAC o SYM) THEN1 MATCH_ACCEPT_TAC RDOM_subTC THEN - ASM_REWRITE_TAC [RDOM_SUBSET_FDOM] + ASM_REWRITE_TAC [RDOM_SUBSET_FDOM] ,MATCH_MP_TAC subTC_SUPERSET_RDOM THEN MATCH_ACCEPT_TAC FDOM_FINITE ]); @@ -632,6 +632,5 @@ GEN_TAC THEN Induct THENL ]]]); val _ = export_theory (); -val _ = print_theory "-"; end; (* struct *) diff --git a/src/enumfset/totoScript.sml b/src/enumfset/totoScript.sml index 6dabe108eb..fb11fc2617 100644 --- a/src/enumfset/totoScript.sml +++ b/src/enumfset/totoScript.sml @@ -1000,6 +1000,5 @@ IMP_RES_THEN SUBST1_TAC TO_apto_TO_IMP THEN REWRITE_TAC [oneOrd]); (* intto moved to inttoTheory, to avoid always loading intLib *) val _ = export_theory (); -val _ = print_theory "-"; end; diff --git a/src/enumfset/wotScript.sml b/src/enumfset/wotScript.sml index 5e1ed69a7d..0b945eb63c 100644 --- a/src/enumfset/wotScript.sml +++ b/src/enumfset/wotScript.sml @@ -542,6 +542,5 @@ Q.EXISTS_TAC `$mex_less` THEN REWRITE_TAC [WellOrd_mex_less, GSYM StrongWellOrder]); val _ = export_theory (); -val _ = print_theory "-"; end; From 6ac8ba082fd3f5bc5e7f9077abbfd7beb2de2211 Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Mon, 8 Dec 2014 15:34:54 +0000 Subject: [PATCH 044/718] Add tool support for the MIPS instructions LWL, LWR, LDL and LDR. --- .../mips/prog/mips_progLib.sml | 1 + .../mips/step/mips_stepLib.sml | 72 ++++++++++++++++++- .../mips/step/mips_stepScript.sml | 30 ++++++++ 3 files changed, 101 insertions(+), 2 deletions(-) diff --git a/examples/l3-machine-code/mips/prog/mips_progLib.sml b/examples/l3-machine-code/mips/prog/mips_progLib.sml index f4948d5a4e..6c20ebf92d 100644 --- a/examples/l3-machine-code/mips/prog/mips_progLib.sml +++ b/examples/l3-machine-code/mips/prog/mips_progLib.sml @@ -88,6 +88,7 @@ val state_id = ["CP0", "PC", "exceptionSignalled", "hi", "lo"], ["CP0", "LLbit", "PC"], ["CP0", "LLbit", "PC", "exceptionSignalled"], + ["CP0", "LLbit", "PC", "exceptionSignalled", "gpr"], ["CP0", "LLbit", "PC", "gpr"], ["CP0", "PC"], ["CP0", "PC", "lo"], diff --git a/examples/l3-machine-code/mips/step/mips_stepLib.sml b/examples/l3-machine-code/mips/step/mips_stepLib.sml index a3cffe53e3..37dc2fde49 100644 --- a/examples/l3-machine-code/mips/step/mips_stepLib.sml +++ b/examples/l3-machine-code/mips/step/mips_stepLib.sml @@ -336,6 +336,46 @@ val ERET = (* Load/Store thms and tools *) +val cond_0_1 = Q.prove( + `!w: word1 a b c. + (if w = 0w then a else if w = 1w then b else c) = + (if w = 0w then a else b)`, + wordsLib.Cases_word_value \\ simp []) + +val cond_0_3 = Q.prove( + `!w: word2 a b c d e. + (if w = 0w then a + else if w = 1w then b + else if w = 2w then c + else if w = 3w then d + else e) = + (if w = 0w then a + else if w = 1w then b + else if w = 2w then c + else d)`, + wordsLib.Cases_word_value \\ simp []) + +val cond_0_7 = Q.prove( + `!w: word3 a b c d e f g h i. + (if w = 0w then a + else if w = 1w then b + else if w = 2w then c + else if w = 3w then d + else if w = 4w then e + else if w = 5w then f + else if w = 6w then g + else if w = 7w then h + else i) = + (if w = 0w then a + else if w = 1w then b + else if w = 2w then c + else if w = 3w then d + else if w = 4w then e + else if w = 5w then f + else if w = 6w then g + else h)`, + wordsLib.Cases_word_value \\ simp []) + val mem_thms = [AddressTranslation_def, LoadMemory_def, StoreMemory_byte, storeWord_def, storeDoubleword_def, @@ -345,6 +385,9 @@ val mem_thms = BYTE_def, HALFWORD_def, WORD_def, DOUBLEWORD_def, address_align, address_align2, cond_sign_extend, byte_address, extract_byte, wordsTheory.word_concat_0_0, wordsTheory.WORD_XOR_CLAUSES, + cond_0_1, cond_0_3, cond_0_7, + EVAL ``word_replicate 2 (0w: word1) : word2``, + EVAL ``word_replicate 2 (1w: word1) : word2``, EVAL ``((1w:word1) @@ (0w:word2)) : word3``, EVAL ``(word_replicate 2 (0w:word1) : word2 @@ (0w:word1)) : word3``, EVAL ``(word_replicate 2 (1w:word1) : word2 @@ (0w:word1)) : word3``, @@ -353,8 +396,9 @@ val mem_thms = val select_rule = REWRITE_RULE - [select_byte_le, select_byte_be, byte_address, - wordsTheory.WORD_XOR_ASSOC, wordsTheory.WORD_XOR_CLAUSES] o + [select_byte_le, select_byte_be, byte_address, + SIMP_RULE (bool_ss++boolSimps.LET_ss) [] select_parts, + wordsTheory.WORD_XOR_ASSOC, wordsTheory.WORD_XOR_CLAUSES] o utilsLib.INST_REWRITE_RULE [select_half_le, select_half_be, select_word_le, select_word_be, @@ -376,6 +420,10 @@ val memcntxts = val addr = ``sw2sw (offset:word16) + if base = 0w then 0w else ^st.gpr base`` +val unaligned_memcntxts = + List.map (fn l => [``rt <> 0w:word5``, ``~^st.exceptionSignalled``] @ l) + memcntxts + val memcntxts = List.map (fn l => @@ -468,6 +516,22 @@ val LL = EVL loadWord ``dfn'LL (base, rt, offset) ^st`` val LD = EVL loadDoubleword ``dfn'LD (base, rt, offset) ^st`` val LLD = EVL loadDoubleword ``dfn'LLD (base, rt, offset) ^st`` +val LWL = + EVR select_rule (dfn'LWL_def :: mem_thms) unaligned_memcntxts [] + ``dfn'LWL (base, rt, offset)`` + +val LWR = + EVR select_rule (dfn'LWR_def :: mem_thms) unaligned_memcntxts [] + ``dfn'LWR (base, rt, offset)`` + +val LDL = + EVR select_rule (dfn'LDL_def :: mem_thms) unaligned_memcntxts [] + ``dfn'LDL (base, rt, offset)`` + +val LDR = + EVR select_rule (dfn'LDR_def :: mem_thms) unaligned_memcntxts [] + ``dfn'LDR (base, rt, offset)`` + (* Store instructions *) val SB = @@ -725,11 +789,15 @@ val mips_patterns = List.map (I ## utilsLib.pattern) ("BNEL", "FTFTFT__________________________"), ("BLEZL", "FTFTTF_____FFFFF________________"), ("BGTZL", "FTFTTT_____FFFFF________________"), + ("LDL", "FTTFTF__________________________"), + ("LDR", "FTTFTT__________________________"), ("LB", "TFFFFF__________________________"), ("LH", "TFFFFT__________________________"), + ("LWL", "TFFFTF__________________________"), ("LW", "TFFFTT__________________________"), ("LBU", "TFFTFF__________________________"), ("LHU", "TFFTFT__________________________"), + ("LWR", "TFFTTF__________________________"), ("LWU", "TFFTTT__________________________"), ("SB", "TFTFFF__________________________"), ("SH", "TFTFFT__________________________"), diff --git a/examples/l3-machine-code/mips/step/mips_stepScript.sml b/examples/l3-machine-code/mips/step/mips_stepScript.sml index 97a006b238..bdfa8784e4 100644 --- a/examples/l3-machine-code/mips/step/mips_stepScript.sml +++ b/examples/l3-machine-code/mips/step/mips_stepScript.sml @@ -277,6 +277,36 @@ val select_word_be = Q.prove( tac ) +val select_parts = Q.store_thm("select_parts", + `!a0: word8 a1: word8 a2: word8 a3: word8 a4: word8 a5: word8 a6: word8 + a7: word8. + let w = a7 @@ a6 @@ a5 @@ a4 @@ a3 @@ a2 @@ a1 @@ a0 + in + ((7 >< 0) w = a0) /\ + ((15 >< 0) w = (a1 @@ a0) : word16) /\ + ((23 >< 0) w = (a2 @@ a1 @@ a0) : word24) /\ + ((31 >< 0) w = (a3 @@ a2 @@ a1 @@ a0) : word32) /\ + ((39 >< 0) w = (a4 @@ a3 @@ a2 @@ a1 @@ a0) : 40 word) /\ + ((47 >< 0) w = (a5 @@ a4 @@ a3 @@ a2 @@ a1 @@ a0) : word48) /\ + ((55 >< 0) w = (a6 @@ a5 @@ a4 @@ a3 @@ a2 @@ a1 @@ a0) : 56 word) /\ + ((63 >< 0) w = w) /\ + ((39 >< 32) w = a4) /\ + ((47 >< 32) w = (a5 @@ a4) : word16) /\ + ((55 >< 32) w = (a6 @@ a5 @@ a4) : word24) /\ + ((63 >< 32) w = (a7 @@ a6 @@ a5 @@ a4) : word32) /\ + ((31 >< 8) w = (a3 @@ a2 @@ a1) : word24) /\ + ((31 >< 16) w = (a3 @@ a2) : word16) /\ + ((31 >< 24) w = a3) /\ + ((63 >< 8) w = (a7 @@ a6 @@ a5 @@ a4 @@ a3 @@ a2 @@ a1) : 56 word) /\ + ((63 >< 16) w = (a7 @@ a6 @@ a5 @@ a4 @@ a3 @@ a2) : word48) /\ + ((63 >< 24) w = (a7 @@ a6 @@ a5 @@ a4 @@ a3) : 40 word) /\ + ((63 >< 32) w = (a7 @@ a6 @@ a5 @@ a4) : word32) /\ + ((63 >< 40) w = (a7 @@ a6 @@ a5) : word24) /\ + ((63 >< 48) w = (a7 @@ a6) : word16) /\ + ((63 >< 56) w = a7 : word8)`, + SIMP_TAC (srw_ss()++boolSimps.LET_ss++wordsLib.WORD_EXTRACT_ss) [] + ) + (* ------------------------------------------------------------------------ *) val bit_0_2_0 = Theory.save_thm("bit_0_2_0", From 4588239f712f1a8aea84bffbc8555ad429286e5c Mon Sep 17 00:00:00 2001 From: Thomas Tuerk Date: Mon, 8 Dec 2014 23:12:33 +0100 Subject: [PATCH 045/718] more work on deep-matches - split pat and rh side of PMATCH_ROW - this removes the need for higher order matching - added guards to PMATCH_ROW - add congruence rules for PMATCH - work on parsing PMATCH - work on using the simplifier with PMATCH --- examples/deep_matches/constrFamiliesLib.sig | 4 + examples/deep_matches/constrFamiliesLib.sml | 7 + examples/deep_matches/deepMatchesExamples.sml | 128 +++-- examples/deep_matches/deepMatchesLib.sig | 24 + examples/deep_matches/deepMatchesLib.sml | 436 +++++++++++++----- examples/deep_matches/deepMatchesScript.sml | 267 +++++++---- examples/deep_matches/deepMatchesSyntax.sig | 50 +- examples/deep_matches/deepMatchesSyntax.sml | 219 +++++++-- 8 files changed, 843 insertions(+), 292 deletions(-) diff --git a/examples/deep_matches/constrFamiliesLib.sig b/examples/deep_matches/constrFamiliesLib.sig index 21b802d6bf..9ee176a0df 100644 --- a/examples/deep_matches/constrFamiliesLib.sig +++ b/examples/deep_matches/constrFamiliesLib.sig @@ -3,4 +3,8 @@ sig include Abbrev val gen_case_expand_thm : thm -> thm -> thm + + val get_case_expand_thm : term * ((term list * term) list) -> + thm + end diff --git a/examples/deep_matches/constrFamiliesLib.sml b/examples/deep_matches/constrFamiliesLib.sml index ef846a6dcd..bcf87776ef 100644 --- a/examples/deep_matches/constrFamiliesLib.sml +++ b/examples/deep_matches/constrFamiliesLib.sml @@ -69,6 +69,13 @@ in res_thm end +fun get_case_expand_thm (v, _) = let + val ty = type_of v + val case_def_thm = TypeBase.case_def_of ty + val nchotomy_thm = TypeBase.nchotomy_of ty +in + gen_case_expand_thm case_def_thm nchotomy_thm +end diff --git a/examples/deep_matches/deepMatchesExamples.sml b/examples/deep_matches/deepMatchesExamples.sml index f90f647de8..cd856ae8d3 100644 --- a/examples/deep_matches/deepMatchesExamples.sml +++ b/examples/deep_matches/deepMatchesExamples.sml @@ -1,6 +1,7 @@ open bossLib open deepMatchesLib - +open deepMatchesTheory +open deepMatchesSyntax (* Introducing case expressions *) @@ -13,50 +14,63 @@ val thm_t' = PMATCH_REMOVE_ARB_CONV t' val thm_t' = PMATCH_SIMP_CONV t' (* more fancy *) - val t = ``case x of (NONE, []) => 0 | (SOME 2, []) => 2 | (SOME 3, (x :: xs)) => 3 + x | (SOME _, (x :: xs)) => x`` - val t' = convert_case t val thm_t = PMATCH_INTRO_CONV t val thm_t' = PMATCH_REMOVE_ARB_CONV t' val thm_t' = PMATCH_SIMP_CONV t' + (* Playing around with some examples *) val example1 = `` PMATCH (a,x,xs) - [PMATCH_ROW (\x. ((NONE,x,[]),x)); - PMATCH_ROW (\x. ((NONE,x,[2]),x)); - PMATCH_ROW (\(x,v18). ((NONE,x,[v18]),3)); - PMATCH_ROW (\(x,v12,v16,v17). ((NONE,x,v12::v16::v17),3)); - PMATCH_ROW (\(y,x,z,zs). ((SOME y,x,[z]),x+5+z)); - PMATCH_ROW (\(y,v23,v24). ((SOME y,0,v23::v24),v23+y)); - PMATCH_ROW (\(y,z,v23). ((SOME y,SUC z,[v23]),3)); - PMATCH_ROW (\(y,z). ((SOME y,SUC z,[1; 2]),y + z)); - PMATCH_ROW (\(y,z,v38). ((SOME y,SUC z,[1; v38]),3)); - PMATCH_ROW (\(y,x). ((y,x,[2;4;3]),3+x)); - PMATCH_ROW - (\(y,z,v29,v36,v37). ((SOME y,SUC z,1::v29::v36::v37),z+v36+v29)); - PMATCH_ROW (\(y,z,v31,v29,v30). ((SOME y,SUC z,v31::v29::v30),v31+z))]`` + [PMATCH_ROW (\x. (NONE,x,[])) (\x. T) (\x. x); + PMATCH_ROW (\x. (NONE,x,[2])) (\x. T) (\x. x); + PMATCH_ROW (\ (x,v18). (NONE,x,[v18])) (\ (x, v18). T) (\ (x, v18). 3); + PMATCH_ROW (\ (x,v12,v16,v17). (NONE,x,v12::v16::v17)) + (\ (x,v12,v16,v17). T) + (\ (x,v12,v16,v17). 3); + PMATCH_ROW (\ (y,x,z,zs). (SOME y,x,[z])) + (\ (y,x,z,zs). T) + (\ (y,x,z,zs). x+5+z); + PMATCH_ROW (\ (y,v23,v24). (SOME y,0,v23::v24)) + (\ (y,v23,v24). T) + (\ (y,v23,v24). v23+y); + PMATCH_ROW (\ (y,z,v23). (SOME y,SUC z,[v23])) + (\ (y,z,v23). y > 5) + (\ (y,z,v23). 3); + PMATCH_ROW (\ (y,z). (SOME y,SUC z,[1; 2])) + (\ (y,z). T) + (\ (y,z). y + z) + ]`` + val example2 = ``PMATCH (h::t) - [PMATCH_ROW (\_ . ([],x)); - PMATCH_ROW (\_. ([2],x)); PMATCH_ROW (\v18. ([v18],3)); - PMATCH_ROW (\(v12,v16,v17). (v12::v16::v17,3)); - PMATCH_ROW (\_. ([2; 4; 3],3 + x))]`` + [PMATCH_ROW (\_ . []) (\_. T) (\_. x); + PMATCH_ROW (\_. [2]) (\_. T) (\_. x); + PMATCH_ROW (\v18. [v18]) (\v18. T) (\v18. 3); + PMATCH_ROW (\ (v12,v16,v17). (v12::v16::v17)) + (\ (v12,v16,v17). T) + (\ (v12,v16,v17). 3); + PMATCH_ROW (\_. [2; 4; 3]) (\_. T) (\_. 3 + x)]`` val example3 = ``PMATCH (NONE,x,xs) - [PMATCH_ROW (\x. ((NONE,x,[]),x)); - PMATCH_ROW (\x. ((NONE,x,[2]),x)); - PMATCH_ROW (\(x,v18). ((NONE,x,[v18]),3)); - PMATCH_ROW (\(x,v12,v16,v17). ((NONE,x,v12::v16::v17),3)); - PMATCH_ROW (\(y,x). ((y,x,[2; 4; 3]),3 + x))]``; + [PMATCH_ROW (\x. (NONE,x,[])) (\x. T) (\x. x); + PMATCH_ROW (\x. (NONE,x,[2])) (\x. T) (\x. x); + PMATCH_ROW (\ (x,v18). (NONE,x,[v18])) (\ (x,v18). T) (\ (x,v18). 3); + PMATCH_ROW (\ (x,v12,v16,v17). (NONE,x,v12::v16::v17)) + (\ (x,v12,v16,v17). T) + (\ (x,v12,v16,v17). 3); + PMATCH_ROW (\ (y,x). (y,x,[2; 4; 3])) + (\ (y,x). x > 5) + (\ (y,x). 3 + x)]``; (* turn off pretty printer *) @@ -74,7 +88,7 @@ PMATCH_SIMP_CONV example3 set_goal ([], ``^example1 = XXX``); e (Cases_on `a`) -e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) +e (SIMP_TAC (std_ss++PMATCH_SIMP_ss) []) e (Cases_on `xs`) e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) @@ -86,12 +100,68 @@ e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) proofManagerLib.restart () e (Cases_on `x`) -e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) +e (SIMP_TAC (std_ss++PMATCH_SIMP_ss) []) e (Cases_on `xs`) proofManagerLib.rotate 1 -e (CONV_TAC (DEPTH_CONV PMATCH_SIMP_CONV)) -SIMP_TAC std_ss [] +e (SIMP_TAC (std_ss++PMATCH_SIMP_ss) []) proofManagerLib.drop () + +(**************************************) +(* Playing around with parsing *) +(**************************************) + +(* set parsing of case expression to deep ones *) +set_trace "parse deep cases" 1; + +val ex1 = ``case (x, y, z) of + (x, [], NONE) => x + | (x, [], SOME y) => x+y + | (_, z::zs, _) => z`` + +(* there are new features as well. Multiple + occurences of the same variable in a pattern are fine *) + +val ex2 = ``case (x, y) of + (x, x) => T + | _ => F`` + +(* let's prove that this really behaves as expected. + Notice that here the simpset-fragments for + PMATCH pick out information from the context to + simplify the PMATCH. *) + +val ex2_thm = prove (``^ex2 = (x = y)``, + +SIMP_TAC (std_ss++PMATCH_SIMP_ss) [] THEN +Cases_on `x=y` THEN ( + ASM_SIMP_TAC (std_ss++PMATCH_SIMP_ss) [] +)) + + +(**************************************) +(* PMATCH has necessary congruences *) +(* theorems to use for recursive defs *) +(**************************************) + +val _ = set_trace "parse deep cases" 1; + +val my_d_def = Define + `my_d xx = case xx of + (x, []) => x + | (x, y::ys) => my_d (x + y, ys)` + +val my_d_thms = store_thm ("my_d_thms", +``(!x. my_d (x, []) = x) /\ + (!x y ys. my_d (x, y::ys) = my_d (x + y, ys))``, + +REPEAT STRIP_TAC THENL [ + SIMP_TAC (std_ss++PMATCH_SIMP_ss) [my_d_def], + + CONV_TAC (LHS_CONV (ONCE_REWRITE_CONV [my_d_def])) THEN + SIMP_TAC (std_ss ++ PMATCH_SIMP_ss) [] +]) + + diff --git a/examples/deep_matches/deepMatchesLib.sig b/examples/deep_matches/deepMatchesLib.sig index cf1c3726fe..8fcb6545de 100644 --- a/examples/deep_matches/deepMatchesLib.sig +++ b/examples/deep_matches/deepMatchesLib.sig @@ -2,6 +2,27 @@ signature deepMatchesLib = sig include Abbrev + (********************************) + (* eliminating select *) + (********************************) + + (* PMATCH leads to selects consisting of + conjunctions that determine the value of one + component of the variable. An example is + + @x. SND (SND x = ..) /\ (FST x = ..) /\ (FST (SND x) = ..) + + by resorting these conjunctions, one can + easily derive a form + + @x. x = .. + + and therefore eliminate the select operator. + This is done by the following conversion + ssfrag. *) + val ELIM_FST_SND_SELECT_CONV : conv + val elim_fst_snd_select_ss : ssfrag + + (********************************) (* turn shallow case-terms into *) (* deeply embedded ones *) @@ -27,6 +48,9 @@ sig not known by the default methods. *) val PMATCH_SIMP_CONV_GEN : ssfrag list -> conv + (* corresponding ssfrags *) + val PMATCH_SIMP_GEN_ss : ssfrag list -> ssfrag + val PMATCH_SIMP_ss : ssfrag (* PMATCH_SIMP_CONV consists of various component conversions. These can be used diff --git a/examples/deep_matches/deepMatchesLib.sml b/examples/deep_matches/deepMatchesLib.sml index 4f2ac6a2f8..3270e28c5d 100644 --- a/examples/deep_matches/deepMatchesLib.sml +++ b/examples/deep_matches/deepMatchesLib.sml @@ -11,8 +11,39 @@ open constrFamiliesLib (***********************************************) val PAIR_EQ_COLLAPSE = prove ( -``((FST x = a) /\ (SND x = b)) = (x = (a, b))``, -Cases_on `x` THEN SIMP_TAC std_ss []) +``(((FST x = (a:'a)) /\ (SND x = (b:'b))) = (x = (a, b)))``, +Cases_on `x` THEN SIMP_TAC std_ss [] THEN METIS_TAC[]) + + +fun is_FST_eq x t = let + val (l, r) = dest_eq t + val pred = aconv (pairSyntax.mk_fst x) +in + pred l +end + +fun FST_SND_CONJUNCT_COLLAPSE v conj = let + val conj'_thm = markerLib.move_conj_left (is_FST_eq v) conj + + val v' = pairSyntax.mk_snd v + + val thm_coll = (TRY_CONV (RAND_CONV (FST_SND_CONJUNCT_COLLAPSE v')) THENC + (REWR_CONV PAIR_EQ_COLLAPSE)) + (rhs (concl conj'_thm)) +in + TRANS conj'_thm thm_coll +end handle HOL_ERR _ => raise UNCHANGED + +fun ELIM_FST_SND_SELECT_CONV t = let + val (v, conj) = boolSyntax.dest_select t + val thm0 = FST_SND_CONJUNCT_COLLAPSE v conj + + val thm1 = RAND_CONV (ABS_CONV (K thm0)) t + val thm2 = CONV_RULE (RHS_CONV (REWR_CONV SELECT_REFL)) thm1 +in + thm2 +end handle HOL_ERR _ => raise UNCHANGED + (* val rc = DEPTH_CONV pairTools.PABS_ELIM_CONV THENC SIMP_CONV list_ss [pairTheory.EXISTS_PROD, pairTheory.FORALL_PROD, PMATCH_ROW_EQ_NONE, PAIR_EQ_COLLAPSE, oneTheory.one] @@ -25,19 +56,47 @@ val pabs_elim_ss = key = SOME ([],``UNCURRY (f:'a -> 'b -> bool)``), conv = K (K pairTools.PABS_ELIM_CONV)} +val elim_fst_snd_select_ss = + simpLib.conv_ss + {name = "ELIM_FST_SND_SELECT_CONV", + trace = 2, + key = SOME ([],``$@ (f:'a -> bool)``), + conv = K (K ELIM_FST_SND_SELECT_CONV)} + fun rc_ss gl = list_ss ++ simpLib.merge_ss (gl @ [pabs_elim_ss, pairSimps.paired_forall_ss, pairSimps.paired_exists_ss, pairSimps.gen_beta_ss, + elim_fst_snd_select_ss, simpLib.rewrites [ pairTheory.EXISTS_PROD, pairTheory.FORALL_PROD, PMATCH_ROW_EQ_NONE, + PMATCH_ROW_COND_def, PAIR_EQ_COLLAPSE, oneTheory.one]]) +fun callback_CONV cb_opt t = (case cb_opt of + NONE => raise UNCHANGED + | SOME cb => ( + if (aconv t T) orelse (aconv t F) then (raise UNCHANGED) else + (EQT_INTRO (cb t) + handle HOL_ERR _ => EQF_INTRO (cb (mk_neg t))))) + +fun rc_conv (gl, callback_opt) = + SIMP_CONV (rc_ss gl) [] THENC + TRY_CONV (callback_CONV callback_opt) + +fun rc_tac (gl, callback_opt) = + CONV_TAC (rc_conv (gl, callback_opt)) + +fun PMATCH_ROW_ARGS_CONV c = + RATOR_CONV (RAND_CONV (TRY_CONV c)) THENC + RATOR_CONV (RATOR_CONV (RAND_CONV (TRY_CONV c))) THENC + RATOR_CONV (RATOR_CONV (RATOR_CONV (RAND_CONV (TRY_CONV c)))) + (***********************************************) (* converting case-splits to PMATCH *) @@ -143,7 +202,7 @@ fun convert_case t = let fun process_pattern (p, rh) = let val fvs = List.rev (free_vars p) in - mk_PMATCH_ROW fvs p rh + mk_PMATCH_ROW_PABS fvs (p, T, rh) end val rows = List.map process_pattern ps val rows_tm = listSyntax.mk_list (rows, type_of (hd rows)) @@ -161,12 +220,12 @@ fun PMATCH_INTRO_CONV t = let TODO: change implementation to get more runtime-speed *) val my_tac = ( CASE_TAC THEN - FULL_SIMP_TAC (rc_ss []) [PMATCH_EVAL] + FULL_SIMP_TAC (rc_ss []) [PMATCH_EVAL, PMATCH_ROW_COND_def] ) in (* set_goal ([], tm) *) prove (tm, REPEAT my_tac) -end handle HOL_ERR _ => NO_CONV t; +end handle HOL_ERR _ => raise UNCHANGED (***********************************************) @@ -179,25 +238,24 @@ end handle HOL_ERR _ => NO_CONV t; not needed for PMATCH and can be removed. *) (* -val ssl = [] -val t = ``PMATCH x - [PMATCH_ROW (\_ . (NONE,0)); - PMATCH_ROW (\v. (SOME v,ARB))]`` +val rc_arg = [] + +set_trace "parse deep cases" 0 +val t = convert_case ``case x of NONE => 0`` -val t = - ``PMATCH x - [PMATCH_ROW (\_. ((NONE,[]),0)); - PMATCH_ROW (\(v4,v5). ((NONE,v4::v5),ARB)); - PMATCH_ROW (\(v2,v1). ((SOME v2,v1),ARB))]`` +val t = convert_case ``case (x, y, z) of + (0, y, z) => 2 + | (x, NONE, []) => x + | (x, SOME y, l) => x+y`` *) -fun PMATCH_REMOVE_ARB_CONV_GEN_SINGLE ssl t = let +fun PMATCH_REMOVE_ARB_CONV_GENCALL_SINGLE rc_arg t = let val (v, rows) = dest_PMATCH t val rows_rev = List.rev rows val i_rev = index (fn row => ( - is_arb (#3(dest_PMATCH_ROW row))) + is_arb (#4(dest_PMATCH_ROW_ABS row))) handle HOL_ERR _ => false) rows_rev val i = length rows - (i_rev + 1) @@ -215,13 +273,13 @@ fun PMATCH_REMOVE_ARB_CONV_GEN_SINGLE ssl t = let listSyntax.mk_append (rows1_tm, listSyntax.mk_cons (rhs (concl r_thm), rows2_tm)) - val thm0 = HO_PART_MATCH (rand o lhs o snd o dest_imp o #2 o strip_forall) ( + val thm0 = PART_MATCH (rand o lhs o snd o dest_imp o #2 o strip_forall) ( ISPEC v (FRESH_TY_VARS_RULE PMATCH_REMOVE_ARB_NO_OVERLAP) ) input_rows val pre = rand (rator (concl thm0)) - val pre_thm = prove (pre, SIMP_TAC (rc_ss ssl) []) + val pre_thm = prove (pre, rc_tac rc_arg) val thm1 = MP thm0 pre_thm val thm2 = CONV_RULE ((RHS_CONV o RAND_CONV) listLib.APPEND_CONV) @@ -229,14 +287,16 @@ fun PMATCH_REMOVE_ARB_CONV_GEN_SINGLE ssl t = let val thm2_lhs_tm = mk_eq (t, lhs (concl thm2)) val thm2_lhs = prove (thm2_lhs_tm, - MP_TAC r_thm THEN SIMP_TAC (rc_ss []) []) + MP_TAC r_thm THEN + rc_tac rc_arg) val thm3 = TRANS thm2_lhs thm2 in thm3 end handle HOL_ERR _ => raise UNCHANGED -fun PMATCH_REMOVE_ARB_CONV_GEN ssl = REPEATC (PMATCH_REMOVE_ARB_CONV_GEN_SINGLE ssl) +fun PMATCH_REMOVE_ARB_CONV_GENCALL rc_arg = REPEATC (PMATCH_REMOVE_ARB_CONV_GENCALL_SINGLE rc_arg) +fun PMATCH_REMOVE_ARB_CONV_GEN ssl = PMATCH_REMOVE_ARB_CONV_GENCALL (ssl, NONE) val PMATCH_REMOVE_ARB_CONV = PMATCH_REMOVE_ARB_CONV_GEN [] @@ -246,14 +306,12 @@ val PMATCH_REMOVE_ARB_CONV = PMATCH_REMOVE_ARB_CONV_GEN [] (*val t = `` PMATCH (SOME x, xz) - [PMATCH_ROW (\x. ((SOME 2,x,[]),x)); - PMATCH_ROW (\y:'a. ((SOME 2,3,[]),x)); - PMATCH_ROW (\(z,x,yy). ((z,x,[2]),x)); - PMATCH_ROW (\(z,yy,xs). ((SOME z,xs),3+z)); - PMATCH_ROW (\(z,xs). ((SOME z,xs),3+z)); - PMATCH_ROW (\(yy,x,xs). ((NONE,xs),3))]`` + [PMATCH_ROW (\x. (SOME 2,x,[])) (\x. T) (\x. x); + PMATCH_ROW (\y:'a. ((SOME 2,3,[]))) (\y. T) (\y. x); + PMATCH_ROW (\(z,x,yy). (z,x,[2])) (\(z,x,yy). T) (\(z,x,yy). x)]`` *) + (* Many simps depend on patterns being injective. This means in particular that no extra, unused vars occur in the patterns. The following removes such unused vars. *) @@ -262,7 +320,7 @@ fun PMATCH_CLEANUP_PVARS_CONV t = let val _ = if is_PMATCH t then () else raise UNCHANGED fun row_conv row = let - val (vars_tm, pt, rh) = dest_PMATCH_ROW row + val (vars_tm, pt, gt, rh) = dest_PMATCH_ROW_ABS row val _ = if (type_of vars_tm = ``:unit``) then raise UNCHANGED else () val vars = pairSyntax.strip_pair vars_tm val used_vars = FVL [pt, rh] empty_tmset @@ -272,21 +330,20 @@ fun PMATCH_CLEANUP_PVARS_CONV t = let val _ = if (length vars = length filtered_vars) then raise UNCHANGED else () - val row' = mk_PMATCH_ROW filtered_vars pt rh + val row' = mk_PMATCH_ROW_PABS filtered_vars (pt, gt, rh) val eq_tm = mk_eq (row, row') (* set_goal ([], eq_tm) *) val eq_thm = prove (eq_tm, - CONV_TAC (DEPTH_CONV pairTools.PABS_ELIM_CONV) THEN - HO_MATCH_MP_TAC PMATCH_ROW_EQ_AUX THEN - SIMP_TAC (rc_ss []) [] + MATCH_MP_TAC PMATCH_ROW_EQ_AUX THEN + rc_tac ([], NONE) ) in eq_thm end in - DEPTH_CONV row_conv t -end + CHANGED_CONV (DEPTH_CONV (PMATCH_ROW_FORCE_SAME_VARS_CONV THENC row_conv)) t +end handle HOL_ERR _ => raise UNCHANGED (***********************************************) @@ -296,6 +353,22 @@ end (* row matches *) (***********************************************) +(* +val t = `` +PMATCH (NONE,x,l) + [PMATCH_ROW (\x. (NONE,x,[])) (\x. T) (\x. x); + PMATCH_ROW (\x. (NONE,x,[2])) (\x. F) (\x. x); + PMATCH_ROW (\x. (NONE,x,[2])) (\x. T) (\x. x); + PMATCH_ROW (\(x,y). (y,x,[2])) (\(x, y). T) (\(x, y). x); + PMATCH_ROW (\x. (SOME 3,x,[])) (\x. T) (\x. x) + ]`` + +val t = ``PMATCH y [PMATCH_ROW (\_0_1. _0_1) (\_0_1. T) (\_0_1. F)]`` +val rc_arg = [] + +val t' = rhs (concl (PMATCH_CLEANUP_CONV t)) +*) + fun map_filter f l = case l of [] => [] | x::xs => (case f x of @@ -303,12 +376,11 @@ fun map_filter f l = case l of | SOME y => y :: (map_filter f xs)); (* remove redundant rows *) -fun PMATCH_CLEANUP_CONV_GEN ssl t = let +fun PMATCH_CLEANUP_CONV_GENCALL rc_arg t = let val (v, rows) = dest_PMATCH t - val rc_conv = SIMP_CONV (rc_ss ssl) [] fun check_row r = let - val r_tm = mk_eq (mk_comb (r, v), optionSyntax.mk_none (type_of t)) val r_thm = rc_conv r_tm + val r_tm = mk_eq (mk_comb (r, v), optionSyntax.mk_none (type_of t)) val r_thm = rc_conv rc_arg r_tm val res_tm = rhs (concl r_thm) in if (same_const res_tm T) then SOME (true, r_thm) else @@ -331,7 +403,7 @@ fun PMATCH_CLEANUP_CONV_GEN ssl t = let fun check_row_exists v rows = exists (fn x => case x of (_, SOME (v', _)) => v = v' | _ => false) rows - val _ = if ((check_row_exists true rows_checked_rev) orelse (check_row_exists false (tl rows_checked_rev))) then () else raise UNCHANGED + val _ = if ((check_row_exists true rows_checked_rev) orelse (check_row_exists false rows_checked_rev)) then () else raise UNCHANGED val row_ty = type_of (hd rows) @@ -391,23 +463,15 @@ fun PMATCH_CLEANUP_CONV_GEN ssl t = let val thm2 = let val _ = if (not (List.null rows_checked1) andalso (case hd rows_checked1 of (_, (SOME (false, _))) => true | _ => false)) then () else failwith "nothing to do" - + val thm1_tm = rhs (concl thm1) - val thm2a = DEPTH_CONV pairTools.PABS_ELIM_CONV thm1_tm handle UNCHANGED => REFL thm1_tm - val (vars,_) = pairLib.dest_pabs (rand (rand (rator (rand (thm1_tm))))) - - val thm2a0 = HO_PART_MATCH (lhs o rand) PMATCH_EVAL_MATCH (rhs (concl thm2a)) - - val pre_tm = fst (dest_imp (concl thm2a0)) - val pre_thm0 = snd (valOf(snd (hd rows_checked1))) - val pre_thm = prove (pre_tm, - MP_TAC pre_thm0 THEN - SIMP_TAC (rc_ss ssl) []) + val thm2a = PART_MATCH (lhs o rand) PMATCH_EVAL_MATCH thm1_tm + val pre_thm = EQF_ELIM (snd (valOf(snd (hd rows_checked1)))) + val thm2b = MP thm2a pre_thm - val thm2a1 = MP thm2a0 pre_thm - - val thm2b = TRANS thm2a thm2a1 - val thm2c = CONV_RULE (RHS_CONV (RAND_CONV rc_conv)) thm2b handle HOL_ERR _ => thm2b + val thm2c = CONV_RULE (RHS_CONV + (RAND_CONV (rc_conv rc_arg) THENC + pairLib.GEN_BETA_CONV)) thm2b handle HOL_ERR _ => thm2b in thm2c end handle HOL_ERR _ => let @@ -420,7 +484,8 @@ in end handle HOL_ERR _ => raise UNCHANGED -fun PMATCH_CLEANUP_CONV t = PMATCH_CLEANUP_CONV_GEN [] t +fun PMATCH_CLEANUP_CONV_GEN ssl = PMATCH_CLEANUP_CONV_GENCALL (ssl, NONE) +val PMATCH_CLEANUP_CONV = PMATCH_CLEANUP_CONV_GEN [] @@ -444,24 +509,53 @@ end; (* drop a column *) (*----------------*) -fun PMATCH_REMOVE_COL_AUX ssl col t = let +(* +val t = `` +PMATCH (NONE,x,l) + [PMATCH_ROW (\x. (NONE,x,[])) (\x. T) (\x. x); + PMATCH_ROW (\z. (NONE,z,[2])) (\z. F) (\z. z); + PMATCH_ROW (\x. (NONE,x,[2])) (\x. T) (\x. x); + PMATCH_ROW (\(z,y). (y,z,[2])) (\(z, y). IS_SOME y) (\(z, y). y) + ]`` + + +val t = `` + PMATCH (x + y,ys) + [PMATCH_ROW (λx. (x,[])) (λx. T) (λx. x); + PMATCH_ROW (λ(x,y,ys). (x,y::ys)) (λ(x,y,ys). T) + (λ(x,y,ys). my_d (x + y,ys))]`` + + +val t = ``PMATCH (x,y) + [PMATCH_ROW (λx. (x,x)) (λx. T) (λx. T); + PMATCH_ROW (λ (z, y). (z, y)) (λ (z, y). T) (λ (z, y). F)]`` + + +val rc_arg = [] +val col = 0 +*) + +fun PMATCH_REMOVE_COL_AUX rc_arg col t = let val (v, rows) = dest_PMATCH t val (v', c_v) = pair_get_col col v + val vs = free_vars c_v fun PMATCH_ROW_REMOVE_FUN_VAR_COL_AUX row = let - val (vars_tm, pt, rh) = dest_PMATCH_ROW row + val (vars_tm, pt, gt, rh) = dest_PMATCH_ROW_ABS_VARIANT vs row val vars = pairSyntax.strip_pair vars_tm + val avoid = free_varsl [pt, gt, rh] - val (pt', pv) = pair_get_col col pt + val (pt0', pv) = pair_get_col col pt + val pt' = subst [pv |-> c_v] pt0' val pv_i_opt = SOME (index (aconv pv) vars) handle HOL_ERR _ => NONE - val (vars'_tm, g') = case pv_i_opt of + val (vars'_tm, f) = case pv_i_opt of (SOME pv_i) => (let (* we eliminate a variabe column *) val vars' = let val vars' = List.take (vars, pv_i) @ List.drop (vars, pv_i+1) in - if (List.null vars') then [genvar ``:unit``] else vars' + if (List.null vars') then [variant avoid ``uv:unit``] else vars' end val vars'_tm = pairSyntax.list_mk_pair vars' @@ -488,29 +582,36 @@ fun PMATCH_REMOVE_COL_AUX ssl col t = let (vars'_tm, g') end) - val f = pairSyntax.mk_pabs (vars_tm, pt) +(* val f = pairSyntax.mk_pabs (vars_tm, pt) val f' = pairSyntax.mk_pabs (vars'_tm, pt') val g = pairSyntax.mk_pabs (vars_tm, rh) +*) + val p = pairSyntax.mk_pabs (vars_tm, pt) + val p' = pairSyntax.mk_pabs (vars'_tm, pt') + val g = pairSyntax.mk_pabs (vars_tm, gt) + val r = pairSyntax.mk_pabs (vars_tm, rh) + val thm0 = let val thm = FRESH_TY_VARS_RULE PMATCH_ROW_REMOVE_FUN_VAR val thm = ISPEC v thm val thm = ISPEC v' thm val thm = ISPEC f thm + val thm = ISPEC p thm val thm = ISPEC g thm - val thm = ISPEC f' thm - val thm = ISPEC g' thm + val thm = ISPEC r thm + val thm = ISPEC p' thm - fun elim_conv vs = RATOR_CONV (RAND_CONV ( + fun elim_conv_aux vs = ( (pairTools.PABS_INTRO_CONV vs) THENC (DEPTH_CONV (pairLib.PAIRED_BETA_CONV ORELSEC BETA_CONV)) - )) + ) - val thm = CONV_RULE ((RAND_CONV o LHS_CONV) (elim_conv vars_tm)) thm + fun elim_conv vs = PMATCH_ROW_ARGS_CONV (elim_conv_aux vs) val thm = CONV_RULE ((RAND_CONV o RHS_CONV) (elim_conv vars'_tm)) thm val tm_eq = mk_eq(lhs (rand (concl thm)), mk_comb (row, v)) - val eq_thm = prove (tm_eq, SIMP_TAC (rc_ss ssl) []) + val eq_thm = prove (tm_eq, rc_tac rc_arg) val thm = CONV_RULE (RAND_CONV (LHS_CONV (K eq_thm))) thm in @@ -519,7 +620,7 @@ fun PMATCH_REMOVE_COL_AUX ssl col t = let val pre_tm = fst (dest_imp (concl thm0)) (* set_goal ([], pre_tm) *) - val pre_thm = prove (pre_tm, SIMP_TAC (rc_ss ssl) []) + val pre_thm = prove (pre_tm, rc_tac rc_arg) val thm1 = MP thm0 pre_thm in thm1 @@ -541,12 +642,25 @@ in end handle HOL_ERR _ => raise UNCHANGED - (*------------------------------------*) (* remove a constructor from a column *) (*------------------------------------*) -fun PMATCH_REMOVE_FUN_AUX ssl col t = let +(* +val t = `` +PMATCH (SOME y,x,l) + [PMATCH_ROW (\x. (SOME 0,x,[])) (\x. T) (\x. x); + PMATCH_ROW (\z. (SOME 1,z,[2])) (\z. F) (\z. z); + PMATCH_ROW (\x. (SOME 3,x,[2])) (\x. T) (\x. x); + PMATCH_ROW (\(z,y). (y,z,[2])) (\(z, y). IS_SOME y) (\(z, y). y) + ]`` + +val rc_arg = [] +val col = 0 +*) + + +fun PMATCH_REMOVE_FUN_AUX rc_arg col t = let val (v, rows) = dest_PMATCH t val (ff_tm, ff_inv, ff_inv_var, c) = let @@ -603,46 +717,49 @@ fun PMATCH_REMOVE_FUN_AUX ssl col t = let end val ff_thm_tm = ``!x y. (^ff_tm x = ^ff_tm y) ==> (x = y)`` - val ff_thm = prove (ff_thm_tm, SIMP_TAC (rc_ss ssl) []) + val ff_thm = prove (ff_thm_tm, rc_tac rc_arg) val v' = ff_inv v val PMATCH_ROW_REMOVE_FUN' = let - val thm0 = (HO_MATCH_MP PMATCH_ROW_REMOVE_FUN ff_thm) - val thm1 = ISPEC v' thm0 + val thm0 = FRESH_TY_VARS_RULE PMATCH_ROW_REMOVE_FUN + val thm1 = ISPEC ff_tm thm0 + val thm2 = ISPEC v' thm1 + val thm3 = MATCH_MP thm2 ff_thm - val thm_v' = prove (``^ff_tm ^v' = ^v``, SIMP_TAC (rc_ss ssl) []) - val thm2 = CONV_RULE (STRIP_QUANT_CONV (LHS_CONV (RAND_CONV (K thm_v')))) thm1 + val thm_v' = prove (``^ff_tm ^v' = ^v``, rc_tac rc_arg) + val thm4 = CONV_RULE (STRIP_QUANT_CONV (LHS_CONV (RAND_CONV (K thm_v')))) thm3 in - thm2 + thm4 end fun PMATCH_ROW_REMOVE_FUN_COL_AUX row = let - val (vars_tm, pt, rh) = dest_PMATCH_ROW row + val (vars_tm, pt, gt, rh) = dest_PMATCH_ROW_ABS row val pt' = ff_inv pt - val f = pairSyntax.mk_pabs (vars_tm, pt') - val g = pairSyntax.mk_pabs (vars_tm, rh) + val vpt' = pairSyntax.mk_pabs (vars_tm, pt') + val vgt = pairSyntax.mk_pabs (vars_tm, gt) + val vrh = pairSyntax.mk_pabs (vars_tm, rh) - val thm0 = ISPEC g (ISPEC f PMATCH_ROW_REMOVE_FUN') + val thm0 = ISPECL [vpt', vgt, vrh] PMATCH_ROW_REMOVE_FUN' val eq_thm_tm = mk_eq (lhs (concl thm0), mk_comb (row, v)) - val eq_thm = prove (eq_thm_tm, SIMP_TAC (rc_ss ssl) []) + val eq_thm = prove (eq_thm_tm, rc_tac rc_arg) val thm1 = CONV_RULE (LHS_CONV (K eq_thm)) thm0 val vi_conv = (pairTools.PABS_INTRO_CONV vars_tm) THENC (DEPTH_CONV (pairLib.PAIRED_BETA_CONV ORELSEC BETA_CONV)) - val thm2 = CONV_RULE (RHS_CONV (RATOR_CONV (RAND_CONV vi_conv))) thm1 + val thm2 = CONV_RULE (RHS_CONV (PMATCH_ROW_ARGS_CONV vi_conv)) thm1 in thm2 end fun PMATCH_ROW_REMOVE_VAR_COL_AUX row = let - val (vars_tm, pt, rh) = dest_PMATCH_ROW row + val (vars_tm, pt, gt, rh) = dest_PMATCH_ROW_ABS row val vars = pairSyntax.strip_pair vars_tm - val avoid = vars @ free_vars pt @ free_vars rh + val avoid = vars @ free_vars pt @ free_vars rh @ free_vars gt val (pt', pv, new_vars) = ff_inv_var avoid pt val pv_i = index (aconv pv) vars @@ -650,11 +767,11 @@ fun PMATCH_REMOVE_FUN_AUX ssl col t = let val vars' = let val vars' = List.take (vars, pv_i) @ new_vars @ List.drop (vars, pv_i+1) in - if (List.null vars') then [genvar ``:unit``] else vars' + if (List.null vars') then [variant avoid ``uv:unit``] else vars' end val vars'_tm = pairSyntax.list_mk_pair vars' - val g' = let + val f_tm = let val c_v = list_mk_comb (c, new_vars) val vs = List.take (vars, pv_i) @ (c_v :: List.drop (vars, pv_i+1)) val vs_tm = pairSyntax.list_mk_pair vs @@ -662,30 +779,30 @@ fun PMATCH_REMOVE_FUN_AUX ssl col t = let pairSyntax.mk_pabs (vars'_tm, vs_tm) end - val f = pairSyntax.mk_pabs (vars_tm, pt) - val f' = pairSyntax.mk_pabs (vars'_tm, pt') - val g = pairSyntax.mk_pabs (vars_tm, rh) + val vpt = pairSyntax.mk_pabs (vars_tm, pt) + val vpt' = pairSyntax.mk_pabs (vars'_tm, pt') + val vrh = pairSyntax.mk_pabs (vars_tm, rh) + val vgt = pairSyntax.mk_pabs (vars_tm, gt) val thm0 = let val thm = FRESH_TY_VARS_RULE PMATCH_ROW_REMOVE_FUN_VAR val thm = ISPEC v thm val thm = ISPEC v' thm - val thm = ISPEC f thm - val thm = ISPEC g thm - val thm = ISPEC f' thm - val thm = ISPEC g' thm + val thm = ISPEC f_tm thm + val thm = ISPEC vpt thm + val thm = ISPEC vgt thm + val thm = ISPEC vrh thm + val thm = ISPEC vpt' thm - fun elim_conv vs = RATOR_CONV (RAND_CONV ( + fun elim_conv vs = PMATCH_ROW_ARGS_CONV ( (pairTools.PABS_INTRO_CONV vs) THENC (DEPTH_CONV (pairLib.PAIRED_BETA_CONV ORELSEC BETA_CONV)) - )) + ) - val thm = CONV_RULE ((RAND_CONV o LHS_CONV) (elim_conv vars_tm)) thm val thm = CONV_RULE ((RAND_CONV o RHS_CONV) (elim_conv vars'_tm)) thm val tm_eq = mk_eq(lhs (rand (concl thm)), mk_comb (row, v)) - val eq_thm = prove (tm_eq, - SIMP_TAC (rc_ss ssl) []) + val eq_thm = prove (tm_eq, rc_tac rc_arg) val thm = CONV_RULE (RAND_CONV (LHS_CONV (K eq_thm))) thm in @@ -693,7 +810,7 @@ fun PMATCH_REMOVE_FUN_AUX ssl col t = let end val pre_tm = fst (dest_imp (concl thm0)) - val pre_thm = prove (pre_tm, SIMP_TAC (rc_ss ssl) []) + val pre_thm = prove (pre_tm, rc_tac rc_arg) val thm1 = MP thm0 pre_thm in @@ -728,7 +845,18 @@ end handle HOL_ERR _ => raise UNCHANGED (* Combine auxiliary funs *) (*------------------------*) -fun PMATCH_SIMP_COLS_CONV_GEN ssl t = let +(* +val t = `` +PMATCH (SOME y,x,l) + [PMATCH_ROW (\x. (SOME 0,x,[])) (\x. T) (\x. x); + PMATCH_ROW (\z. z) (\z. F) (\z. (FST (SND z))); + PMATCH_ROW (\x. (SOME 3,x)) (\x. T) (\x. (FST x)); + PMATCH_ROW (\(z,y). (y,z,[2])) (\(z, y). IS_SOME y) (\(z, y). y) + ]`` +val rc_arg = [] +*) + +fun PMATCH_SIMP_COLS_CONV_GENCALL rc_arg t = let val cols = dest_PMATCH_COLS t (* val (col_v, col) = el 1 cols @@ -756,9 +884,9 @@ fun PMATCH_SIMP_COLS_CONV_GEN ssl t = let end handle HOL_ERR _ => false fun process_col i col = if (elim_col_ok col) then - SOME (PMATCH_REMOVE_COL_AUX ssl i t) + SOME (PMATCH_REMOVE_COL_AUX rc_arg i t) else if (simp_col_ok col) then - SOME (PMATCH_REMOVE_FUN_AUX ssl i t) + SOME (PMATCH_REMOVE_FUN_AUX rc_arg i t) else NONE val thm_opt = first_opt process_col cols @@ -767,6 +895,7 @@ in | SOME thm => thm end +fun PMATCH_SIMP_COLS_CONV_GEN ssl = PMATCH_SIMP_COLS_CONV_GENCALL (ssl, NONE) val PMATCH_SIMP_COLS_CONV = PMATCH_SIMP_COLS_CONV_GEN [] @@ -779,6 +908,17 @@ val PMATCH_SIMP_COLS_CONV = PMATCH_SIMP_COLS_CONV_GEN [] explicit pairs, while others are not. The following tries to expand columns into explicit ones. *) +(* +val t = `` +PMATCH (SOME y,x,l) + [PMATCH_ROW (\x. (SOME 0,x,[])) (\x. T) (\x. x); + PMATCH_ROW (\z. z) (\z. F) (\z. (FST (SND z))); + PMATCH_ROW (\x. (SOME 3,x)) (\x. T) (\x. (FST x)); + PMATCH_ROW (\(z,y). (y,z,[2])) (\(z, y). IS_SOME y) (\(z, y). y) + ]`` +*) + + fun PMATCH_EXPAND_COLS_CONV t = let val (v, rows) = dest_PMATCH t @@ -812,7 +952,7 @@ fun PMATCH_EXPAND_COLS_CONV t = let end fun PMATCH_ROW_EXPAND_COLS row = let - val (vars_tm, pt, rh) = dest_PMATCH_ROW row + val (vars_tm, pt, gt, rh) = dest_PMATCH_ROW_ABS row val vars = pairSyntax.strip_pair vars_tm val pts = pairSyntax.strip_pair pt @@ -823,19 +963,20 @@ fun PMATCH_EXPAND_COLS_CONV t = let val _ = if (List.exists (aconv l) vars) then () else failwith "nothing to do" - val avoids = vars @ free_vars pt @ free_vars rh + val avoids = vars @ free_vars pt @ free_vars gt @ free_vars rh val new_vars = split_var avoids cols l val sub = [l |-> pairSyntax.list_mk_pair new_vars] val pt' = Term.subst sub pt + val gt' = Term.subst sub gt val rh' = Term.subst sub rh - val vars_tm' = Term.subst sub vars_tm - val new_f = pairSyntax.mk_pabs(vars_tm', pairSyntax.mk_pair (pt', rh')) + val vars' = pairSyntax.strip_pair (Term.subst sub vars_tm) - val eq_tm = mk_eq(rand row, new_f) - val eq_thm = prove (eq_tm, SIMP_TAC (rc_ss []) []) + val row' = mk_PMATCH_ROW_PABS vars' (pt', gt', rh') - val thm = RATOR_CONV (RAND_CONV (K eq_thm)) (mk_comb (row, v)) + val eq_tm = mk_eq(row, row') + val eq_thm = prove (eq_tm, rc_tac ([], NONE)) + val thm = AP_THM eq_thm v in thm end handle HOL_ERR _ => REFL (mk_comb (row, v)) @@ -878,20 +1019,74 @@ end handle HOL_ERR _ => raise UNCHANGED (***********************************************) (* PMATCH_SIMP_CONV *) (***********************************************) -fun PMATCH_SIMP_CONV_GEN rc = REPEATC (FIRST_CONV [ + +(* +val t = `` +PMATCH (SOME y,x,l) + [PMATCH_ROW (\x. (SOME 0,x,[])) (\y. T) (\x. x); + PMATCH_ROW (\z. z) (\z. F) (\z. (FST (SND z))); + PMATCH_ROW (\x. (SOME 3,x)) (\x. T) (\x. (FST x)); + PMATCH_ROW (\(z,y). (y,z,[2])) (\(z, y). IS_SOME y) (\(z, y). y) + ]`` +*) + +fun PMATCH_SIMP_CONV_GENCALL rc_arg = REPEATC (FIRST_CONV [ CHANGED_CONV (PMATCH_CLEANUP_PVARS_CONV), - CHANGED_CONV (PMATCH_CLEANUP_CONV_GEN rc), - CHANGED_CONV (PMATCH_REMOVE_ARB_CONV_GEN rc), - CHANGED_CONV (PMATCH_SIMP_COLS_CONV_GEN rc)]) + CHANGED_CONV (PMATCH_CLEANUP_CONV_GENCALL rc_arg), + CHANGED_CONV (PMATCH_REMOVE_ARB_CONV_GENCALL rc_arg), + CHANGED_CONV (PMATCH_SIMP_COLS_CONV_GENCALL rc_arg), + CHANGED_CONV (PMATCH_EXPAND_COLS_CONV), + CHANGED_CONV PMATCH_FORCE_SAME_VARS_CONV +]) + +fun PMATCH_SIMP_CONV_GEN ssl = PMATCH_SIMP_CONV_GENCALL (ssl, NONE) val PMATCH_SIMP_CONV = PMATCH_SIMP_CONV_GEN [] +fun PMATCH_SIMP_convdata_conv ssl callback back = + PMATCH_SIMP_CONV_GENCALL (ssl, SOME (callback back)) + + +fun PMATCH_SIMP_GEN_ss ssl = simpLib.conv_ss + { name = "PMATCH_SIMP_CONV", + key = SOME ([], ``(PMATCH (v:'a) rows):'b``), + trace = 1, + conv = PMATCH_SIMP_convdata_conv ssl + } + +val PMATCH_SIMP_ss = PMATCH_SIMP_GEN_ss [] + + (***********************************************) (* Case_splits *) (* This is work in progress *) (***********************************************) +(* +val t = `` +PMATCH (a,x,xs) + [PMATCH_ROW (\x. (NONE,x,[])) (\x. T) (\x. x); + PMATCH_ROW (\x. (NONE,x,[2])) (\x. T) (\x. x); + PMATCH_ROW (\ (x,v18). (NONE,x,[v18])) (\ (x, v18). T) (\ (x, v18). 3); + PMATCH_ROW (\ (x,v12,v16,v17). (NONE,x,v12::v16::v17)) + (\ (x,v12,v16,v17). T) + (\ (x,v12,v16,v17). 3); + PMATCH_ROW (\ (y,x,z,zs). (SOME y,x,[z])) + (\ (y,x,z,zs). T) + (\ (y,x,z,zs). x+5+z); + PMATCH_ROW (\ (y,v23,v24). (SOME y,0,v23::v24)) + (\ (y,v23,v24). T) + (\ (y,v23,v24). v23+y); + PMATCH_ROW (\ (y,z,v23). (SOME y,SUC z,[v23])) + (\ (y,z,v23). y > 5) + (\ (y,z,v23). 3); + PMATCH_ROW (\ (y,z). (SOME y,SUC z,[1; 2])) + (\ (y,z). T) + (\ (y,z). y + z) + ]`` +*) + fun STRIP_ABS_CONV conv t = if (is_abs t) then ABS_CONV (STRIP_ABS_CONV conv) t else conv t @@ -926,23 +1121,18 @@ in thm2 end -fun PMATCH_CASE_SPLIT_CONV_GEN ssl col t = let + +fun PMATCH_CASE_SPLIT_CONV_GENCALL rc_arg col_no t = let val thm0 = QCHANGED_CONV ( - PMATCH_SIMP_CONV_GEN ssl) t handle HOL_ERR _ => REFL t + PMATCH_SIMP_CONV_GENCALL rc_arg) t handle HOL_ERR _ => REFL t val t' = rhs (concl thm0) - val (v, _) = dest_PMATCH t' - val vs = pairSyntax.strip_pair v - val ty = type_of (el (col+1) vs) - val expand_thm = let - val case_def_thm = TypeBase.case_def_of ty - val nchotomy_thm = TypeBase.nchotomy_of ty - in - constrFamiliesLib.gen_case_expand_thm case_def_thm nchotomy_thm - end + val (v, col) = el (col_no+1) (dest_PMATCH_COLS t') + + val expand_thm = get_case_expand_thm (v, col) - val thm1 = QCHANGED_CONV (PMATCH_CASE_SPLIT_AUX col expand_thm (PMATCH_SIMP_CONV_GEN ssl)) t' handle HOL_ERR _ => (REFL t') + val thm1 = QCHANGED_CONV (PMATCH_CASE_SPLIT_AUX col_no expand_thm (PMATCH_SIMP_CONV_GENCALL rc_arg)) t' handle HOL_ERR _ => (REFL t') in TRANS thm0 thm1 end diff --git a/examples/deep_matches/deepMatchesScript.sml b/examples/deep_matches/deepMatchesScript.sml index c876f148aa..7b6c669410 100644 --- a/examples/deep_matches/deepMatchesScript.sml +++ b/examples/deep_matches/deepMatchesScript.sml @@ -1,5 +1,6 @@ open HolKernel Parse boolLib bossLib; open quantHeuristicsLib +open optionTheory val _ = new_theory "deepMatches" @@ -8,15 +9,15 @@ val _ = new_theory "deepMatches" (***************************************************) (* rows of a pattern match are pairs of a pattern to match - against p and a result r. The result and pattern are linked - with free variables [v] bound in both. So it looks like - (\v. (p v, r v)) *) -val PMATCH_ROW_def = Define `PMATCH_ROW row i = - (if ?x. FST (row x) = i then - SOME (SND (row (@x. FST (row x) = i))) - else NONE)` - -(* We defined semantics or single rows. Let's extend + against pat, a guard and a result value. *) +val PMATCH_ROW_COND_def = Define `PMATCH_ROW_COND pat guard i x = + (pat x = i) /\ (guard x)` + +val PMATCH_ROW_def = Define `PMATCH_ROW pat guard res i = + (OPTION_MAP res (some x. PMATCH_ROW_COND pat guard i x))` + + +(* We defined semantics of single rows. Let's extend it to multiple ones, i.e. full pattern matches now *) val PMATCH_INCOMPLETE_def = Define `PMATCH_INCOMPLETE = ARB` val PMATCH_def = Define ` @@ -38,57 +39,144 @@ val PMATCH_REDUNDANT_ROWS_def = Define ` PMATCH_REDUNDANT_ROWS rs = {i | (PMATCH_ROW_REDUNDANT rs i)}` + +(***************************************************) +(* Congruences *) +(***************************************************) + +val some_eq_SOME = store_thm ("some_eq_SOME", + ``!P x. ((some x. P x) = SOME x) ==> (P x)``, +SIMP_TAC std_ss [some_def] THEN +REPEAT STRIP_TAC THEN +SELECT_ELIM_TAC THEN +PROVE_TAC[]) + +val some_eq_NONE = store_thm ("some_eq_NONE", + ``!P. ((some x. P x) = NONE) <=> (!x. ~(P x))``, +SIMP_TAC std_ss [some_def]) + +val some_IS_SOME = store_thm ("some_IS_SOME", + ``!P. (IS_SOME (some x. P x)) <=> (?x. P x)``, +SIMP_TAC (std_ss++boolSimps.LIFT_COND_ss) [some_def]) + +val some_IS_SOME_EXISTS = store_thm ("some_IS_SOME_EXISTS", + ``!P. (IS_SOME (some x. P x)) <=> (?x. P x /\ ((some x. P x) = SOME x))``, +GEN_TAC THEN EQ_TAC THEN REPEAT STRIP_TAC THEN ( + ASM_SIMP_TAC std_ss [] +) THEN +Cases_on `some x. P x` THEN FULL_SIMP_TAC std_ss [] THEN +MATCH_MP_TAC some_eq_SOME THEN +ASM_REWRITE_TAC[]) + + +val OPTION_MAP_EQ_OPTION_MAP = store_thm ("OPTION_MAP_EQ_OPTION_MAP", +``(OPTION_MAP f x = OPTION_MAP f' x') = + (((x = NONE) /\ (x' = NONE)) \/ + (?y y'. (x = SOME y) /\ (x' = SOME y') /\ (f y = f' y')))``, + +Cases_on `x` THEN Cases_on `x'` THEN ( + SIMP_TAC std_ss [] +)) + +val PMATCH_ROW_CONG = store_thm ("PMATCH_ROW_CONG", +``!p p' g g' r r' v v'. + (p = p') /\ (v = v') /\ + (!x. (v = (p x)) ==> (g x = g' x)) /\ + (!x. ((v = (p x)) /\ (g x)) ==> + (r x = r' x)) ==> + (PMATCH_ROW p g r v = PMATCH_ROW p' g' r' v')``, + +REPEAT STRIP_TAC THEN +ASM_SIMP_TAC (std_ss++boolSimps.CONJ_ss) [PMATCH_ROW_def, + PMATCH_ROW_COND_def] THEN +Cases_on `some x. (p' x = v') /\ (g' x)` THEN ( + ASM_SIMP_TAC std_ss [] +) THEN +POP_ASSUM (fn thm => MP_TAC (HO_MATCH_MP (SPEC_ALL some_eq_SOME) thm)) THEN +ASM_SIMP_TAC std_ss []) + +val PMATCH_CONG = store_thm ("PMATCH_CONG", +``!v v' rows rows'. ((v = v') /\ (r v' = r' v') /\ + (PMATCH v' rows = PMATCH v' rows')) ==> + (PMATCH v (r :: rows) = PMATCH v' (r' :: rows'))``, +SIMP_TAC std_ss [PMATCH_def]) + +val _ = DefnBase.export_cong "PMATCH_ROW_CONG"; +val _ = DefnBase.export_cong "PMATCH_CONG"; + + (***************************************************) (* Rewrites *) (***************************************************) val PMATCH_ROW_EQ_AUX = store_thm ("PMATCH_ROW_EQ_AUX", - ``((!i. (?x. (g x = i)) = (?x'. (g' x' = i))) /\ - (!x x'. (g x = g' x') ==> (f x = f' x'))) ==> - (PMATCH_ROW (\x:'a. (g x, f x)) = - PMATCH_ROW (\x':'b. (g' x', f' x')))``, + ``((!i. (?x. PMATCH_ROW_COND p g i x) = + (?x'. PMATCH_ROW_COND p' g' i x')) /\ + (!x x'. ((p x = p' x') /\ g x /\ g' x') ==> (r x = r' x'))) ==> + (PMATCH_ROW p g r = PMATCH_ROW p' g' r')``, REPEAT STRIP_TAC THEN -SIMP_TAC std_ss [PMATCH_ROW_def, FUN_EQ_THM] THEN +SIMP_TAC std_ss [FUN_EQ_THM, PMATCH_ROW_def, + OPTION_MAP_EQ_OPTION_MAP] THEN CONV_TAC (RENAME_VARS_CONV ["i"]) THEN GEN_TAC THEN Q.PAT_ASSUM `!i. (_ = _)` (fn thm => ASSUME_TAC (Q.SPEC `i` thm)) THEN -Cases_on `?x'. g' x' = i` THEN ( - ASM_REWRITE_TAC[] +Tactical.REVERSE (Cases_on `?x. PMATCH_ROW_COND p g i x`) THEN ( + FULL_SIMP_TAC std_ss [] ) THEN -FULL_SIMP_TAC std_ss [] THEN -SELECT_ELIM_TAC THEN -REPEAT STRIP_TAC THEN1 PROVE_TAC[] THEN -SELECT_ELIM_TAC THEN -REPEAT STRIP_TAC THEN1 PROVE_TAC[] THEN -PROVE_TAC[]) +DISJ2_TAC THEN +`IS_SOME (some x. PMATCH_ROW_COND p g i x) /\ + IS_SOME (some x. PMATCH_ROW_COND p' g' i x)` by ALL_TAC THEN1 ( + ASM_SIMP_TAC std_ss [some_IS_SOME] THEN + PROVE_TAC[] +) THEN +FULL_SIMP_TAC std_ss [some_IS_SOME_EXISTS] THEN +FULL_SIMP_TAC std_ss [PMATCH_ROW_COND_def]) val PMATCH_ROW_EQ_NONE = store_thm ("PMATCH_ROW_EQ_NONE", - ``(PMATCH_ROW (\x. (g x, f x)) v = NONE) <=> - (!x. ~(g x = v))``, -SIMP_TAC std_ss [PMATCH_ROW_def]); + ``(PMATCH_ROW p g r i = NONE) <=> + (!x. ~(PMATCH_ROW_COND p g i x))``, +SIMP_TAC std_ss [PMATCH_ROW_def, some_eq_NONE]); + + +val PMATCH_ROW_EQ_SOME = store_thm ("PMATCH_ROW_EQ_SOME", + ``(PMATCH_ROW p g r i = SOME y) ==> + (?x. (PMATCH_ROW_COND p g i x) /\ (y = r x))``, +SIMP_TAC std_ss [PMATCH_ROW_def] THEN +REPEAT STRIP_TAC THEN +Q.EXISTS_TAC `z` THEN +IMP_RES_TAC some_eq_SOME THEN +ASM_SIMP_TAC std_ss []); + val PMATCH_EVAL = store_thm ("PMATCH_EVAL", ``(PMATCH v [] = PMATCH_INCOMPLETE) /\ - (PMATCH v ((PMATCH_ROW (\x. (g x, f x))) :: rs) = - if (?x. (g x = v)) then - (f (@x. g x = v)) else PMATCH v rs)``, + (PMATCH v ((PMATCH_ROW p g r) :: rs) = + if (?x. (PMATCH_ROW_COND p g v x)) then + (r (@x. PMATCH_ROW_COND p g v x)) else PMATCH v rs)``, SIMP_TAC std_ss [PMATCH_def] THEN -Cases_on `PMATCH_ROW (\x. (g x,f x)) v` THEN ( - FULL_SIMP_TAC std_ss [PMATCH_ROW_def] THEN +Cases_on `PMATCH_ROW p g r v` THENL [ + FULL_SIMP_TAC std_ss [PMATCH_ROW_def, some_eq_NONE], + + FULL_SIMP_TAC std_ss [PMATCH_ROW_def, some_def] THEN METIS_TAC[] -)) +]) val PMATCH_EVAL_MATCH = store_thm ("PMATCH_EVAL_MATCH", - ``~(PMATCH_ROW (\x. (g x, f x)) v = NONE) ==> - (PMATCH v ((PMATCH_ROW (\x. (g x, f x))) :: rs) = - (f (@x. g x = v)))``, + ``~(PMATCH_ROW p g r v = NONE) ==> + (PMATCH v ((PMATCH_ROW p g r) :: rs) = + (r (@x.PMATCH_ROW_COND p g v x)))``, -SIMP_TAC std_ss [PMATCH_def] THEN -Cases_on `PMATCH_ROW (\x. (g x,f x)) v` THEN ( - FULL_SIMP_TAC std_ss [PMATCH_ROW_def] THEN - METIS_TAC[] -)) +SIMP_TAC std_ss [PMATCH_EVAL, + PMATCH_ROW_EQ_NONE]) + +val PMATCH_EVAL_MATCH = store_thm ("PMATCH_EVAL_MATCH", + ``~(PMATCH_ROW p g r v = NONE) ==> + (PMATCH v ((PMATCH_ROW p g r) :: rs) = + (r (@x.PMATCH_ROW_COND p g v x)))``, + +SIMP_TAC std_ss [PMATCH_EVAL, + PMATCH_ROW_EQ_NONE]) (***************************************************) @@ -212,24 +300,22 @@ ASM_REWRITE_TAC[]) val PMATCH_REMOVE_ARB = store_thm ("PMATCH_REMOVE_ARB", -``(PMATCH v (SNOC (PMATCH_ROW (\x. (f x, ARB))) rows) = +``(!x. r x = ARB) ==> + (PMATCH v (SNOC (PMATCH_ROW p g r) rows) = PMATCH v rows)``, Induct_on `rows` THENL [ - SIMP_TAC list_ss [PMATCH_def, PMATCH_ROW_def] THEN - Cases_on `?x. f x = v` THEN ( - ASM_SIMP_TAC std_ss [PMATCH_INCOMPLETE_def] - ), - + SIMP_TAC list_ss [PMATCH_EVAL, PMATCH_INCOMPLETE_def], ASM_SIMP_TAC list_ss [PMATCH_def] ]) (* ARB rows can be removed, since a match failiure is the same as ARB *) val PMATCH_REMOVE_ARB_NO_OVERLAP = store_thm ("PMATCH_REMOVE_ARB_NO_OVERLAP", -``!v ff rows1 rows2. - (!x. (v = ff x) ==> EVERY (\r. (r (ff x) = NONE)) rows2) ==> - (PMATCH v (rows1 ++ ((PMATCH_ROW (\x. (ff x, ARB))) :: rows2)) = +``!v p g r rows1 rows2. + ((!x. (r x = ARB)) /\ + (!x. ((v = p x) /\ (g x)) ==> EVERY (\row. (row (p x) = NONE)) rows2)) ==> + (PMATCH v (rows1 ++ ((PMATCH_ROW p g r) :: rows2)) = PMATCH v (rows1 ++ rows2))``, REPEAT STRIP_TAC THEN @@ -237,14 +323,14 @@ Tactical.REVERSE (Induct_on `rows1`) THEN ( ASM_SIMP_TAC list_ss [PMATCH_def] ) THEN -ASM_SIMP_TAC list_ss [PMATCH_def, PMATCH_ROW_def] THEN -Cases_on `?x. ff x = v` THEN ( - ASM_SIMP_TAC std_ss [PMATCH_INCOMPLETE_def] +Cases_on `PMATCH_ROW p g r v` THEN ( + ASM_SIMP_TAC std_ss [] ) THEN -FULL_SIMP_TAC std_ss [] THEN -Q.PAT_ASSUM `_ = v` (ASSUME_TAC o GSYM) THEN +IMP_RES_TAC PMATCH_ROW_EQ_SOME THEN +Q.PAT_ASSUM `!x. P x ==> Q x` (MP_TAC o Q.SPEC `x'`) THEN +FULL_SIMP_TAC std_ss [PMATCH_ROW_COND_def] THEN Induct_on `rows2` THEN ( - FULL_SIMP_TAC list_ss [PMATCH_def, PMATCH_INCOMPLETE_def] + ASM_SIMP_TAC list_ss [PMATCH_def, PMATCH_INCOMPLETE_def] )) @@ -252,16 +338,16 @@ Induct_on `rows2` THEN ( (* Add an injective function to the pattern and the value. This can be used to eliminate constructors. *) val PMATCH_ROW_REMOVE_FUN = store_thm ("PMATCH_ROW_REMOVE_FUN", -``!ff v f g. (!x y. (ff x = ff y) ==> (x = y)) ==> +``!ff v p g r. (!x y. (ff x = ff y) ==> (x = y)) ==> - (PMATCH_ROW (\x. (ff (f x), g x)) (ff v) = - PMATCH_ROW (\x. (f x, g x)) v)``, + (PMATCH_ROW (\x. (ff (p x))) g r (ff v) = + PMATCH_ROW (\x. (p x)) g r v)``, REPEAT STRIP_TAC THEN `!x y. (ff x = ff y) = (x = y)` by PROVE_TAC[] THEN -ASM_SIMP_TAC std_ss [PMATCH_ROW_def]) - +ASM_SIMP_TAC std_ss [PMATCH_ROW_def, PMATCH_ROW_COND_def]) +(* val PMATCH_ROW_REMOVE_FUN_EXT = store_thm ("PMATCH_ROW_REMOVE_FUN_EXT", ``!ff v f f' g g'. @@ -284,7 +370,7 @@ ASM_REWRITE_TAC [] THEN REPEAT STRIP_TAC THEN PROVE_TAC[]) - +*) (* The following lemma looks rather complicated. It is intended to work together with PMATCH_ROW_REMOVE_FUN to @@ -293,15 +379,15 @@ PROVE_TAC[]) as an example consider val t = ``PMATCH (SOME x, y) [ - PMATCH_ROW (\ x. ((SOME x, 0), SOME (x + y))); - PMATCH_ROW (\ (x', y). ((x', y), x')) + PMATCH_ROW (\x. (SOME x, 0)) (K T) (\x. (SOME (x + y))); + PMATCH_ROW (\(x', y). (x', y)) (K T) (\(x', y). x') ]`` We want to simplify this to - val t' = ``PMATCH (x, y) [ - PMATCH_ROW (\ x. ((x, 0), SOME (x + y))); - PMATCH_ROW (\ (x'', y). ((x'', y), SOME x'')) + val t = ``PMATCH (x, y) [ + PMATCH_ROW (\x. (x, 0)) (K T) (\x. (SOME (x + y))); + PMATCH_ROW (\(x'', y). (x'', y)) (K T) (\(x'', y). SOME x'') ]`` This is done via PMATCH_ROWS_SIMP and PMATCH_ROWS_SIMP_SOUNDNESS. @@ -312,45 +398,48 @@ PROVE_TAC[]) v := (x, y) ff (x, y) := (SOME x, y) - f x := (x, 0) - g x := SOME (x + y) + p x := (x, 0) + r x := SOME (x + y) For the second row, PMATCH_ROW_REMOVE_FUN is used with v := (SOME x, y) v' := (x, y) - f (x', y) := (x', y) - g (x', y) := x' - f' (x'', y) = (x'', y) - g' (x'', y) := (SOME x'', y) + p (x', y) := (x', y) + r (x', y) := x' + p' (x'', y) = (x'', y) + f (x'', y) := (SOME x'', y) *) val PMATCH_ROW_REMOVE_FUN_VAR = store_thm ("PMATCH_ROW_REMOVE_FUN_VAR", -``!v v' f g f' g'. - ((!x'. (f' x' = v') = (f (g' x') = v)) /\ - ((!x. (f x = v) ==> ?x'. g' x' = x)) /\ - ((!x y. (f x = f y) ==> (x = y)))) ==> - (PMATCH_ROW (\x. (f x, g x)) v = - PMATCH_ROW (\x'. (f' x'), g (g' x')) v')``, +``!v v' f p g r p' . + ((!x'. (p' x' = v') = (p (f x') = v)) /\ + ((!x. (p x = v) ==> ?x'. f x' = x)) /\ + ((!x y. (p x = p y) ==> (x = y)))) ==> + (PMATCH_ROW p g r v = + PMATCH_ROW p' (\x. g (f x)) (\x. r (f x)) v')``, REPEAT STRIP_TAC THEN ASM_SIMP_TAC std_ss [PMATCH_ROW_def] THEN -`(?x'. f (g' x') = v) = (?x. f x = v)` by ALL_TAC THEN1 ( - METIS_TAC[] +`IS_SOME (some x. PMATCH_ROW_COND p' (\x. g (f x)) v' x) = + IS_SOME (some x. PMATCH_ROW_COND p g v x)` by ALL_TAC THEN1 ( + ASM_SIMP_TAC std_ss [some_IS_SOME, PMATCH_ROW_COND_def] THEN + EQ_TAC THEN1 PROVE_TAC[] THEN + REPEAT STRIP_TAC THEN + `?x'. f x' = x` by PROVE_TAC[] THEN + Q.EXISTS_TAC `x'` THEN + ASM_REWRITE_TAC[] ) THEN -Cases_on `?x. f x = v` THEN ( - ASM_SIMP_TAC std_ss [] +Tactical.REVERSE (Cases_on `IS_SOME (some x. PMATCH_ROW_COND p g v x)`) THEN ( + FULL_SIMP_TAC std_ss [] ) THEN - -SELECT_ELIM_TAC THEN -ASM_SIMP_TAC std_ss [] THEN -SELECT_ELIM_TAC THEN -REPEAT STRIP_TAC THEN ( - METIS_TAC[] -)); +FULL_SIMP_TAC std_ss [some_IS_SOME_EXISTS] THEN +FULL_SIMP_TAC std_ss [PMATCH_ROW_COND_def] THEN +METIS_TAC[]); +(* (***************************************************) (* THEOREMS ABOUT FLATTENING *) @@ -400,6 +489,6 @@ FULL_SIMP_TAC std_ss [] THEN ASM_SIMP_TAC std_ss [] THEN METIS_TAC[]) - +*) val _ = export_theory() diff --git a/examples/deep_matches/deepMatchesSyntax.sig b/examples/deep_matches/deepMatchesSyntax.sig index 8642d89c37..f47e85f64d 100644 --- a/examples/deep_matches/deepMatchesSyntax.sig +++ b/examples/deep_matches/deepMatchesSyntax.sig @@ -10,34 +10,54 @@ sig free vars of a thm *) val FRESH_TY_VARS_RULE : rule - (******************) (* PMATCH_ROW *) (******************) - (* dest_PMATCH_ROW ``PMATCH_ROW (\(x, y). (p x y, rh x y)`` - returns (``(x,y)``, ``p x y``, ``rh x y``). *) + (* dest_PMATCH_ROW ``PMATCH_ROW p g r`` + returns (``p``, ``g``, ``r``). *) val dest_PMATCH_ROW : term -> (term * term * term) val is_PMATCH_ROW : term -> bool - (* [mk_PMATCH_ROW vars p rh] constructs the term - ``PMATCH_ROW (\vars. (p vars, rh vars))``. *) - val mk_PMATCH_ROW : term list -> term -> term -> term + (* [mk_PMATCH_ROW (p, g, rh)] constructs the term + ``PMATCH_ROW p g rh``. *) + val mk_PMATCH_ROW : term * term * term -> term + + (* [mk_PMATCH_ROW vars (p, g, rh)] constructs the term + ``PMATCH_ROW (\vars. p) (\vars. g) (\vars. rh)``. *) + val mk_PMATCH_ROW_PABS : term list -> term * term * term -> term + + (* dest_PMATCH_ROW_ABS ``PMATCH_ROW (\(x,y). p x y) + (\(x,y). g x y) (\(x,y). r x y)`` + returns (``(x,y)``, ``p x y``, ``g x y``, ``r x y``). + It fails, if not all paired abstractions use the same + variable names. *) + val dest_PMATCH_ROW_ABS : term -> (term * term * term * term) + + (* calls dest_PMATCH_ROW_ABS and renames the abstracted vars + consistently to be different from the list of given vars. *) + val dest_PMATCH_ROW_ABS_VARIANT : term list -> term -> (term * term * term * term) - (* [PMATCH_ROW_PABS_ELIM_CONV ``PMATCH_ROW (\(v1, ... vn). ( p (v1, - ... vn), rh (v1, ... vn))``] removes the pair [(v1, ... vn)] and - replaces the paired lambda abstraction with a normal lambda + + (* [PMATCH_ROW_PABS_ELIM_CONV t] + replaces paired lambda abstraction in t with a normal lambda abstraction. It returns a theorem stating the equivalence as - well as the original varstruct removed. *) + well as the original varstruct of p removed. *) val PMATCH_ROW_PABS_ELIM_CONV : term -> (term * thm) (* [PMATCH_ROW_PABS_INTRO_CONV vars t] reintroduces paired abstraction again after being removed by e.g. [PMATCH_ROW_PABS_ELIM_CONV]. It uses [vars] for the newly introduced varstruct. *) - val PMATCH_ROW_PABS_INTRO_CONV : term -> term -> thm + val PMATCH_ROW_PABS_INTRO_CONV : term -> conv + (* [PMATCH_ROW_FORCE_SAME_VARS_CONV] renames the + abstracted variables for the pattern, guard and right hand side + of a row to match with each other. This invariant + is required by many operations working on PMATCH_ROW *) + val PMATCH_ROW_FORCE_SAME_VARS_CONV : conv + val PMATCH_FORCE_SAME_VARS_CONV : conv (******************) (* PMATCH *) @@ -68,4 +88,12 @@ sig *) + (******************) + (* Parser *) + (******************) + + (* Writing a parser for CASES is tricky. The existing + one can be used however. If the trace "parse deep cases" + is set to true, standard case-expressions are parsed + to deep-matches, otherwise the default state-expressions. *) end diff --git a/examples/deep_matches/deepMatchesSyntax.sml b/examples/deep_matches/deepMatchesSyntax.sml index e4dba29c11..d6843885b1 100644 --- a/examples/deep_matches/deepMatchesSyntax.sml +++ b/examples/deep_matches/deepMatchesSyntax.sml @@ -4,28 +4,53 @@ struct open deepMatchesTheory bossLib + +(* Stolen from pairTools. TODO: + add it to interface there. *) +fun variant_of_term vs t = +let + val check_vars = free_vars t; + val (_,sub) = + foldl (fn (v, (vs,sub)) => + let + val v' = variant vs v; + val vs' = v'::vs; + val sub' = if (aconv v v') then sub else + (v |-> v')::sub; + in + (vs',sub') + end) (vs,[]) check_vars; + val t' = subst sub t +in + (t', sub) +end; + + (***********************************************) (* Terms *) (***********************************************) +val ty_var_subst = [alpha |-> gen_tyvar (), + beta |-> gen_tyvar (), + gamma |-> gen_tyvar (), + delta |-> gen_tyvar (), + ``:'e`` |-> gen_tyvar (), + ``:'f`` |-> gen_tyvar (), + ``:'g`` |-> gen_tyvar (), + ``:'h`` |-> gen_tyvar (), + ``:'i`` |-> gen_tyvar (), + ``:'j`` |-> gen_tyvar () + ] + val PMATCH_ROW_tm = ``PMATCH_ROW`` -val PMATCH_tm = ``PMATCH`` +val PMATCH_ROW_gtm = inst ty_var_subst PMATCH_ROW_tm -(***********************************************) -(* Matching support *) -(***********************************************) +val PMATCH_tm = ``PMATCH`` +val PMATCH_gtm = inst ty_var_subst PMATCH_tm -val thm = PMATCH_REMOVE_ARB_NO_OVERLAP +fun FRESH_TY_VARS_RULE thm = + INST_TYPE ty_var_subst thm -fun FRESH_TY_VARS_RULE thm = let - val (vars0, _) = strip_forall (concl thm) - val vars1 = free_vars (concl thm) - val vars = vars0 @ vars1 - val tys = type_varsl (map type_of vars) - val subst = map (fn ty => (ty |-> gen_tyvar ())) tys -in - INST_TYPE subst thm -end (***********************************************) (* PMATCH_ROW *) @@ -33,44 +58,97 @@ end fun dest_PMATCH_ROW row = let val (f, args) = strip_comb row - val _ = if (same_const f PMATCH_ROW_tm) andalso (List.length args = 1) then () else failwith "dest_PMATCH_ROW" - - val arg = hd args - - val (vars_tm, prh) = pairSyntax.dest_pabs arg - val (p, rh) = pairSyntax.dest_pair prh + val _ = if (same_const f PMATCH_ROW_tm) andalso (List.length args = 3) then () else failwith "dest_PMATCH_ROW" in - (vars_tm, p, rh) + (el 1 args, el 2 args, el 3 args) end fun is_PMATCH_ROW t = can dest_PMATCH_ROW t -fun mk_PMATCH_ROW vars p rh = let - val prh = pairSyntax.mk_pair(p, rh) - val pabs = case vars of - [] => mk_abs (genvar ``:unit``, prh) - | [v] => mk_abs (v, prh) - | _ => pairSyntax.mk_pabs (pairSyntax.list_mk_pair vars, prh) +fun mk_PMATCH_ROW (p_t, g_t, r_t) = + list_mk_icomb (PMATCH_ROW_gtm, [p_t, g_t, r_t]) + +fun mk_PMATCH_ROW_PABS vars (p_t, g_t, r_t) = let + val mk_pabs = case vars of + [] => let + val uv = variant (free_varsl [p_t, g_t, r_t]) ``uv:unit`` + in + fn t => mk_abs (uv, t) + end + | [v] => (fn t => mk_abs (v, t)) + | _ => (fn t => pairSyntax.mk_pabs (pairSyntax.list_mk_pair vars, t)) in - mk_icomb (PMATCH_ROW_tm, pabs) + mk_PMATCH_ROW (mk_pabs p_t, mk_pabs g_t, mk_pabs r_t) end + +fun dest_PMATCH_ROW_ABS row = let + val (p_t, g_t, r_t) = dest_PMATCH_ROW row + val (p_vars, p_body) = pairSyntax.dest_pabs p_t + val (g_vars, g_body) = pairSyntax.dest_pabs g_t + val (r_vars, r_body) = pairSyntax.dest_pabs r_t -fun PMATCH_ROW_PABS_ELIM_CONV r = let - val (vars, _, _) = dest_PMATCH_ROW r - val thm = (RAND_CONV pairTools.PABS_ELIM_CONV) r + val _ = if (aconv p_vars g_vars) andalso (aconv g_vars r_vars) then + () else failwith "dest_PMATCH_ROW_ABS" +in + (p_vars, p_body, g_body, r_body) +end + + +fun dest_PMATCH_ROW_ABS_VARIANT vs row = let + val (p_vars, p_body, g_body, r_body) = dest_PMATCH_ROW_ABS row + val (p_vars', sub) = variant_of_term vs p_vars +in + (p_vars', subst sub p_body, subst sub g_body, subst sub r_body) +end + + +fun PMATCH_ROW_PABS_ELIM_CONV row = let + val (p, _, _) = dest_PMATCH_ROW row + val (vars, _) = pairSyntax.dest_pabs p + + val c = TRY_CONV pairTools.PABS_ELIM_CONV + val thm = ((RAND_CONV c) THENC + (RATOR_CONV (RAND_CONV c)) THENC + (RATOR_CONV (RATOR_CONV (RAND_CONV c)))) row + handle UNCHANGED => REFL row in (vars, thm) end -fun PMATCH_ROW_PABS_INTRO_CONV vars r = let - val _ = if (is_PMATCH_ROW r) then () else failwith "PMATCH_ROW_PABS_INTRO_CONV" - val thm = (RAND_CONV (pairTools.PABS_INTRO_CONV vars)) r + +fun PMATCH_ROW_PABS_INTRO_CONV vars row = let + val _ = if (is_PMATCH_ROW row) then () else failwith "PMATCH_ROW_PABS_INTRO_CONV" + + val (vars', _) = variant_of_term (free_vars row) vars + val c = pairTools.PABS_INTRO_CONV vars' + val thm = ((RAND_CONV c) THENC + (RATOR_CONV (RAND_CONV c)) THENC + (RATOR_CONV (RATOR_CONV (RAND_CONV c)))) row in thm end +fun PMATCH_ROW_FORCE_SAME_VARS_CONV row = let + val _ = if not (is_PMATCH_ROW row) then raise UNCHANGED else () + val _ = if can dest_PMATCH_ROW_ABS row then raise UNCHANGED else () + + val (vars, thm0) = PMATCH_ROW_PABS_ELIM_CONV row + val thm1 = PMATCH_ROW_PABS_INTRO_CONV vars (rhs (concl thm0)) +in + TRANS thm0 thm1 +end handle HOL_ERR _ => raise UNCHANGED +(* +val row = `` + PMATCH_ROW (\ (y,z). (SOME y,SUC z,[1; 2])) + (\ x. T) + (\ (y,z). y + z)`` + +val (vars, thm) = PMATCH_ROW_PABS_ELIM_CONV row +val thm2 = PMATCH_ROW_PABS_INTRO_CONV vars (rhs (concl thm)) +val row = rhs (concl thm2) +*) (***********************************************) (* PMATCH *) @@ -105,7 +183,7 @@ fun dest_PMATCH_COLS t = let val vs = pairSyntax.strip_pair v fun split_row r = let - val (vars_tm, pt, rh) = dest_PMATCH_ROW r + val (vars_tm, pt, gt, rh) = dest_PMATCH_ROW_ABS r val vars = pairSyntax.strip_pair vars_tm val pts = pairSyntax.strip_pair pt in @@ -124,9 +202,13 @@ fun dest_PMATCH_COLS t = let val cols = get_cols [] vs rows' in cols -end - +end handle Empty => failwith "dest_PMATCH_COLS" +fun PMATCH_FORCE_SAME_VARS_CONV t = let + val _ = if not (is_PMATCH t) then raise UNCHANGED else () +in + DEPTH_CONV PMATCH_ROW_FORCE_SAME_VARS_CONV t +end (***********************************************) (* Pretty Printing *) @@ -143,13 +225,17 @@ fun pmatch_printer GS backend sys (ppfns:term_pp_types.ppstream_funs) gravs d t val {add_string,add_break,ublock,add_newline,ustyle,...} = ppfns val (v,rows) = dest_PMATCH t; - val rows' = map dest_PMATCH_ROW rows + val rows' = map dest_PMATCH_ROW_ABS rows - fun pp_row (vars, pat, rh) = ( + fun pp_row (vars, pat, guard, rh) = ( term_pp_utils.record_bvars (pairSyntax.strip_pair vars) ( ublock PP.CONSISTENT 0 ( add_string "|" >> add_break (1, 0) >> sys (Top, Top, Top) (d - 1) pat >> + (if (aconv guard T) then nothing else ( + add_break (1, 0) >> add_string "when" >> add_break (1, 0) >> + sys (Top, Top, Top) (d - 1) guard + )) >> add_break (1, 0) >> add_string "=>" >> add_break (1, 0) >> sys (Top, Top, Top) (d - 1) rh )) @@ -159,9 +245,62 @@ fun pmatch_printer GS backend sys (ppfns:term_pp_types.ppstream_funs) gravs d t sys (Top, Top, Top) (d - 1) v >> add_break(1,0) >> add_string "OF")) >> add_break (1, 0) >> - smpp.pr_list pp_row (add_break (0, 0)) rows' + smpp.pr_list pp_row (add_break (1, 0)) rows' end handle HOL_ERR _ => raise term_pp_types.UserPP_Failed; val _ = add_user_printer ("PMATCH", ``PMATCH v l``, pmatch_printer); + +(***********************************************) +(* Parser *) +(***********************************************) + + +fun case_magic_to_deep_case t = let + val rows = strip_conj t + + val v = rator (lhs (hd rows)) + val (arg_tyL, res_ty) = strip_fun (type_of v) + + fun process_row row = let + val (l,r) = dest_eq row + val p = rand l + + val vars = free_vars_lr p + in + mk_PMATCH_ROW_PABS vars (p, T, r) + end + + val prows = map process_row rows + val i = genvar (hd arg_tyL) + val prows' = listSyntax.mk_list (prows, type_of (hd prows)) + val pmatch_t = mk_PMATCH i prows' +in + mk_abs (v, mk_abs (i, pmatch_t)) +end + + +val parse_case_as_pmatch = ref false +val _ = Feedback.register_btrace ("parse deep cases", parse_case_as_pmatch); + +val _ = + let fun lookup s = + case TypeBase.read s + of SOME tyi => SOME {constructors = TypeBasePure.constructors_of tyi, + case_const = TypeBasePure.case_const_of tyi} + | NONE => NONE + open GrammarSpecials + in + set_case_specials ((fn t => + if !parse_case_as_pmatch then + case_magic_to_deep_case t + else + #functional (Pmatch.mk_functional lookup t)), + + (fn s => + case lookup s of + NONE => [] + | SOME {constructors,...} => constructors)) + end + end From 8d315d0c67a88c69a958cfbf35266246131989cd Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Wed, 10 Dec 2014 16:34:13 +1100 Subject: [PATCH 046/718] Delete trailing whitespace in src/ This needs doing periodically, and is best done to a whole bunch of files at once. --- src/1/PmatchHeuristics.sig | 24 +- src/1/Tactical.sig | 4 +- src/1/Tactical.sml | 52 ++--- src/datatype/DatatypeSimps.sig | 10 +- src/datatype/DatatypeSimps.sml | 56 ++--- src/enumfset/enumTacs.sml | 20 +- src/enumfset/fmapalTacs.sml | 14 +- src/enumfset/inttoTacs.sml | 2 +- src/enumfset/tcTacs.sml | 10 +- src/enumfset/totoTacs.sml | 16 +- src/floating-point/binary_ieeeSyntax.sml | 4 +- src/num/extra_theories/numeral_bitScript.sml | 2 +- src/portableML/mosml/Arbnumcore.sml | 2 +- src/probability/extrealScript.sml | 4 +- src/probability/lebesgueScript.sml | 8 +- src/quantHeuristics/doc/quantHeu.tex | 220 +++++++++---------- src/quantHeuristics/selftest.sml | 2 +- src/tfl/src/Defn.sml | 6 +- src/tfl/src/Induction.sml | 14 +- 19 files changed, 235 insertions(+), 235 deletions(-) diff --git a/src/1/PmatchHeuristics.sig b/src/1/PmatchHeuristics.sig index 69910e99c3..5e940264c9 100644 --- a/src/1/PmatchHeuristics.sig +++ b/src/1/PmatchHeuristics.sig @@ -7,25 +7,25 @@ sig {case_const : term, constructors : term list} option type pmatch_heuristic = {skip_rows : bool, (* skip splitting for redundant rows? *) collapse_cases : bool, (* collapse cases that lead to the same result ? *) - (* given a list of rows of patterns, which column to split on? *) + (* given a list of rows of patterns, which column to split on? *) col_fun : thry -> term list list -> int } - (* some predefined heuristics *) + (* some predefined heuristics *) val pheu_classic : pmatch_heuristic (* HOL 4's old heuristic *) - val pheu_first_row : pmatch_heuristic + val pheu_first_row : pmatch_heuristic val pheu_constr_prefix : pmatch_heuristic val pheu_qba : pmatch_heuristic (* the recommended one *) - val pheu_cqba : pmatch_heuristic - val pheu_first_col : pmatch_heuristic - val pheu_last_col : pmatch_heuristic + val pheu_cqba : pmatch_heuristic + val pheu_first_col : pmatch_heuristic + val pheu_last_col : pmatch_heuristic (* A heuristic based on column ranks. Given a pattern match matrix like p_11 ... p_1n - ... + ... p_m1 --- p_mn - and a list of ranking functions prheuL = [r_1, ... r_j]. The + and a list of ranking functions prheuL = [r_1, ... r_j]. The heuristic pheu_rank applies all ranking functions to all columns. Let's denote the result of "r_i current_thyr [p_k1, ... pkm]" with c_ik. It then picks column i such that [c_1i, ... c_ji] is maximal @@ -39,7 +39,7 @@ sig val prheu_small_branching_factor : thry -> term list -> int val prheu_arity : thry -> term list -> int - (* A comparison for the results of heuristic application + (* A comparison for the results of heuristic application (list of pattern lists, resulting decision tree) *) type pmatch_heuristic_res_compare = (term list list * term) Lib.cmp val pmatch_heuristic_cases_cmp : pmatch_heuristic_res_compare (* few cases are good *) @@ -48,7 +48,7 @@ sig (* Using such comparisons, we can supply multiple heuristics and choose the best results. For technical reasons, this function might be stateful and therefore get's unit arguments. - The usage of a heu_fun by the Pmatch library is as follows. Heu_fun initialises the functions and returns a + The usage of a heu_fun by the Pmatch library is as follows. Heu_fun initialises the functions and returns a compare function and a function heu_fun' which provides heuristics. As long as heu_fun' () provides fresh heuristics these are tried. Then the best result of all these heuristics according to the compare function is choosen. *) @@ -59,7 +59,7 @@ sig (* An exhaustive heuristic_fun. It tries all possibilities and very quickly blows up! Only usable for very small examples! *) - val exhaustive_heuristic_fun : pmatch_heuristic_res_compare -> pmatch_heuristic_fun + val exhaustive_heuristic_fun : pmatch_heuristic_res_compare -> pmatch_heuristic_fun (* custom pmatch_heuristic_fun can be easiest constructed by an explicit list of heuristics and a compare function *) @@ -70,7 +70,7 @@ sig (* The pmatch_heuristic_fun to be used by default and various functions to set it *) - val pmatch_heuristic : pmatch_heuristic_fun ref + val pmatch_heuristic : pmatch_heuristic_fun ref val set_heuristic : pmatch_heuristic -> unit val set_heuristic_fun : pmatch_heuristic_fun -> unit diff --git a/src/1/Tactical.sig b/src/1/Tactical.sig index e28ea96503..088bbb9597 100644 --- a/src/1/Tactical.sig +++ b/src/1/Tactical.sig @@ -11,7 +11,7 @@ sig val THEN1 : tactic * tactic -> tactic val THEN_LT : ('a -> goal list * (thm list -> 'b)) * list_tactic -> 'a -> goal list * (thm list -> 'b) - (* could be used as + (* could be used as val THEN_LT : tactic * list_tactic -> tactic val THEN_LT : list_tactic * list_tactic -> list_tactic *) @@ -24,7 +24,7 @@ sig val SPLIT_LT : int -> list_tactic * list_tactic -> list_tactic val ROTATE_LT : int -> list_tactic val REVERSE : tactic -> tactic - val REVERSE_LT : list_tactic + val REVERSE_LT : list_tactic val FAIL_TAC : string -> tactic val NO_TAC : tactic val ALL_TAC : tactic diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index aae33f9255..0b73f26e1e 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -78,7 +78,7 @@ fun store_thm (name, tm, tac) = infix THEN THENL THEN1 ORELSE THEN_LT (*--------------------------------------------------------------------------- - * tac1 THEN_LT ltac2: + * tac1 THEN_LT ltac2: * A tactical that applies ltac2 to the list of subgoals resulting from tac1 * tac1 may be a tactic or a list_tactic *---------------------------------------------------------------------------*) @@ -87,17 +87,17 @@ fun op THEN_LT (tac1, ltac2 : list_tactic) = let val (gl1, vf1) = tac1 g val (gl2, vf2) = ltac2 gl1 ; - in - (gl2, vf1 o vf2) - end + in + (gl2, vf1 o vf2) + end (* first argument can be a tactic or a list-tactic *) val _ = op THEN_LT : tactic * list_tactic -> tactic ; val _ = op THEN_LT : list_tactic * list_tactic -> list_tactic ; - + (*--------------------------------------------------------------------------- * fun ALLGOALS (tac2:tactic) : list_tactic = fn gl => - * let + * let * val (gll,pl) = unzip(map tac2 gl) * in * (flatten gll, mapshape(map length gll)pl) @@ -134,13 +134,13 @@ fun tac1 THEN tac2 = tac1 THEN_LT ALLGOALS tac2 ; (*--------------------------------------------------------------------------- * fun TACS_TO_LT (tac2l: tactic list) : list_tactic = fn gl => - * let + * let * val tac2gl = zip tac2l gl * val (gll,pl) = unzip (map (fn (tac2,g) => tac2 g) tac2gl) * in * (flatten gll, mapshape(map length gll) pl) * end - * Converts a list of tactics to a single list_tactic + * Converts a list of tactics to a single list_tactic *---------------------------------------------------------------------------*) fun TACS_TO_LT (tacl: tactic list) : list_tactic = @@ -210,50 +210,50 @@ fun op THEN1 (tac1: tactic, tac2: tactic) : tactic = (*--------------------------------------------------------------------------- * NTH_GOAL tac n: A list_tactic that applies tac to the nth goal - (counting goals from 1) + (counting goals from 1) *---------------------------------------------------------------------------*) -fun NTH_GOAL tac n gl1 = - let val (gl_before, g :: gl_after) = Lib.split_after (n-1) gl1 ; +fun NTH_GOAL tac n gl1 = + let val (gl_before, g :: gl_after) = Lib.split_after (n-1) gl1 ; val (gl2, vf2) = tac g ; val gl_result = gl_before @ gl2 @ gl_after ; - fun vf thl = + fun vf thl = let val (th_before, th_rest) = Lib.split_after (n-1) thl ; val (th2, th_after) = Lib.split_after (length gl2) th_rest ; - val th_result = th_before @ vf2 th2 :: th_after ; + val th_result = th_before @ vf2 th2 :: th_after ; in th_result end ; - in (gl_result, vf) end + in (gl_result, vf) end handle _ => raise ERR "NTH_GOAL" "no nth subgoal in list" ; fun LASTGOAL tac gl1 = NTH_GOAL tac (length gl1) gl1 ; fun HEADGOAL tac gl1 = NTH_GOAL tac 1 gl1 ; (*--------------------------------------------------------------------------- - * SPLIT_LT n (ltaca, ltacb) : A list_tactic that applies ltaca to the - first n goals, and ltacb to the rest + * SPLIT_LT n (ltaca, ltacb) : A list_tactic that applies ltaca to the + first n goals, and ltacb to the rest *---------------------------------------------------------------------------*) -fun SPLIT_LT n (ltaca, ltacb) gl = +fun SPLIT_LT n (ltaca, ltacb) gl = let val fixn = if n >= 0 then n else length gl + n ; val (gla, glb) = Lib.split_after fixn gl ; val (glra, vfa) = ltaca gla ; val (glrb, vfb) = ltacb glb ; - fun vf ths = + fun vf ths = let val (thsa, thsb) = Lib.split_after (length glra) ths ; - in vfa thsa @ vfb thsb end ; + in vfa thsa @ vfb thsb end ; in (glra @ glrb, vf) end ; (*--------------------------------------------------------------------------- - * ROTATE_LT n : + * ROTATE_LT n : * A list_tactic that moves the first n goals to the end of the goal list * first n goals *---------------------------------------------------------------------------*) -fun ROTATE_LT n [] = ([], Lib.I) - | ROTATE_LT n gl = +fun ROTATE_LT n [] = ([], Lib.I) + | ROTATE_LT n gl = let val lgl = length gl ; val fixn = Int.mod (n, lgl) ; val (gla, glb) = Lib.split_after fixn gl ; - fun vf ths = + fun vf ths = let val (thsb, thsa) = Lib.split_after (lgl - fixn) ths ; - in thsa @ thsb end ; + in thsa @ thsb end ; in (glb @ gla, vf) end ; (*--------------------------------------------------------------------------- @@ -278,7 +278,7 @@ fun REVERSE tac g = fun REVERSE_LT gl = (rev gl, rev) ; -(* for testing, redefine REVERSE +(* for testing, redefine REVERSE fun REVERSE tac = tac THEN_LT REVERSE_LT ; *) @@ -299,7 +299,7 @@ fun NO_TAC g = FAIL_TAC "NO_TAC" g (* for testing, redefine THEN1 fun tac1 THEN1 tac2 = tac1 THEN_LT NTH_GOAL (tac2 THEN NO_TAC) 1 ; -fun tac1 THEN1 tac2 = tac1 THEN_LT REVERSE_LT THEN_LT +fun tac1 THEN1 tac2 = tac1 THEN_LT REVERSE_LT THEN_LT LASTGOAL (tac2 THEN NO_TAC) THEN_LT REVERSE_LT ; *) diff --git a/src/datatype/DatatypeSimps.sig b/src/datatype/DatatypeSimps.sig index 07123d07c0..eaabf50a3e 100644 --- a/src/datatype/DatatypeSimps.sig +++ b/src/datatype/DatatypeSimps.sig @@ -37,9 +37,9 @@ val mk_case_cong_thm_tyinfo : tyinfo -> thm val mk_type_rewrites_tyinfo : tyinfo -> thm list (* mk_case_cong_thm_tyinfo generates an elimination theorem - that fires if all inputs give the same result. - - |- !M c. (case M of C1 => c | C2 x0 => c) = c + that fires if all inputs give the same result. + + |- !M c. (case M of C1 => c | C2 x0 => c) = c *) val mk_case_elim_thm_tyinfo : tyinfo -> thm @@ -58,7 +58,7 @@ val mk_type_quant_thms_tyinfo : tyinfo -> thm * thm (* mk_case_rand_thm_tyinfo, mk_case_rand_thm_tyinfo and mk_case_abs_thm_tyinfo provide theorems that are used for lifting case constants. Use carefully, since their application - easily loops. + easily loops. |- !M f f0 f1. f (case M of C1 => f0 | C2 x0 => f1 x0) = @@ -76,7 +76,7 @@ val mk_type_quant_thms_tyinfo : tyinfo -> thm * thm val mk_case_rand_thm_tyinfo : tyinfo -> thm val mk_case_rator_thm_tyinfo : tyinfo -> thm val mk_case_abs_thm_tyinfo : tyinfo -> thm - + (*---------------------------------------------------------------------------*) (* Simpsets *) (*---------------------------------------------------------------------------*) diff --git a/src/datatype/DatatypeSimps.sml b/src/datatype/DatatypeSimps.sml index 169062952c..45eb3dd59d 100644 --- a/src/datatype/DatatypeSimps.sml +++ b/src/datatype/DatatypeSimps.sml @@ -31,7 +31,7 @@ fun make_variant_list n s avoid [] = [] end fun make_args_simple [] = [] - | make_args_simple (ty :: tys) = + | make_args_simple (ty :: tys) = let val arg0 = mk_var("M", ty); val args = make_variant_list 0 "f" [arg0] tys; @@ -83,7 +83,7 @@ fun mk_type_quant_thms_tyinfo tyinfo = let val P_neg_tm = mk_abs (P_arg_tm, mk_neg (mk_comb (P_tm, P_arg_tm))) val thm0 = SPEC P_neg_tm forall_thm - val thm1 = AP_TERM boolSyntax.negation thm0 + val thm1 = AP_TERM boolSyntax.negation thm0 val thm3 = CONV_RULE (BINOP_CONV (SIMP_CONV std_ss [])) thm1 val thm4 = GEN P_tm thm3 in @@ -91,7 +91,7 @@ in end -fun mk_type_exists_thm_tyinfo tyinfo = +fun mk_type_exists_thm_tyinfo tyinfo = snd (mk_type_quant_thms_tyinfo tyinfo) @@ -124,7 +124,7 @@ fun mk_type_rewrites_tyinfo tyinfo = let val thms_dist = case (distinct_of tyinfo) of NONE => [] - | SOME thm_dist0 => let + | SOME thm_dist0 => let val thms_dist1 = CONJUNCTS thm_dist0 val thms_dist = thms_dist1 @ List.map GSYM thms_dist1 in thms_dist end @@ -164,8 +164,8 @@ fun mk_case_cong_thm_tyinfo tyinfo = let val constr = constructors_of tyinfo val M_eq = mk_eq (input_arg, input_arg') fun mk_imp args c c' cr = let - val t0 = list_mk_icomb (c, args) - val t1 = list_mk_icomb (c', args) + val t0 = list_mk_icomb (c, args) + val t1 = list_mk_icomb (c', args) val t2 = mk_eq (t0, t1) val u0 = list_mk_icomb (cr, args) val u1 = mk_eq (input_arg', u0) @@ -174,12 +174,12 @@ fun mk_case_cong_thm_tyinfo tyinfo = let in t4 end - val imps = List.map (fn (((args, c), (_, c')), cr) => + val imps = List.map (fn (((args, c), (_, c')), cr) => mk_imp args c c' cr) (zip (zip case_args case_args') constr) - val t3 = boolSyntax.list_mk_imp (M_eq::imps, t2) + val t3 = boolSyntax.list_mk_imp (M_eq::imps, t2) val t4 = list_mk_forall ([input_arg, input_arg']@(List.map snd case_args)@(List.map snd case_args'), t3) val forall_thm = mk_type_forall_thm_tyinfo tyinfo @@ -207,7 +207,7 @@ fun mk_case_rand_thm_tyinfo tyinfo = let val t2a = mk_comb (const, t1) val case_args1 = List.map (fn (args, c) => - list_mk_abs (args, mk_comb (const, list_mk_comb (c, args)))) + list_mk_abs (args, mk_comb (const, list_mk_comb (c, args)))) case_args val t2b = list_mk_icomb (case_c, [input_arg] @ case_args1) @@ -244,7 +244,7 @@ fun mk_case_rator_thm_tyinfo tyinfo = let val t3a = mk_icomb (t2, const) val case_args1 = List.map (fn (args, c) => - list_mk_abs (args, mk_comb (inst_ty (list_mk_comb (c, args)), const))) + list_mk_abs (args, mk_comb (inst_ty (list_mk_comb (c, args)), const))) case_args val t3b = list_mk_icomb (case_c, [input_arg] @ case_args1) @@ -279,7 +279,7 @@ fun mk_case_abs_thm_tyinfo tyinfo = let val t2a = mk_abs (const, t1) val case_args1 = List.map (fn (args, c) => - list_mk_abs (args, mk_abs (const, mk_comb (inst_ty (list_mk_comb (c, args)), const)))) + list_mk_abs (args, mk_abs (const, mk_comb (inst_ty (list_mk_comb (c, args)), const)))) case_args val t2b = list_mk_icomb (case_c, [input_arg] @ case_args1) @@ -303,14 +303,14 @@ end fun lift_case_const_CONV stop_consts rand_thms = let val conv = Ho_Rewrite.GEN_REWRITE_CONV I rand_thms -in (fn t => let - val thm = conv t - val (c, args) = strip_comb t +in (fn t => let + val thm = conv t + val (c, args) = strip_comb t in if (List.length args > 1 andalso List.exists (same_const c) stop_consts) then raise UNCHANGED else thm -end handle HOL_ERR _ => raise UNCHANGED) end - +end handle HOL_ERR _ => raise UNCHANGED) end + fun lift_cases_typeinfos_ss til = let val rand_thms = Lib.mapfilter mk_case_rand_thm_tyinfo til @@ -318,11 +318,11 @@ fun lift_cases_typeinfos_ss til = let val abs_thms = Lib.mapfilter mk_case_abs_thm_tyinfo til val consts = Lib.mapfilter case_const_of til - val conv_rand = lift_case_const_CONV consts rand_thms + val conv_rand = lift_case_const_CONV consts rand_thms val conv_rand_ss = simpLib.std_conv_ss { name = "lift_case_const_CONV", pats = [``f x``], - conv = conv_rand} + conv = conv_rand} val rewr_ss = simpLib.rewrites (abs_thms @ rator_thms) in @@ -340,30 +340,30 @@ fun lift_cases_stateful_ss () = lift_cases_typeinfos_ss (TypeBase.elts ()) fun unlift_case_const_CONV stop_consts rand_thms = let val conv = Rewrite.GEN_REWRITE_CONV I empty_rewrites rand_thms -in (fn t => let - val thm = conv t +in (fn t => let + val thm = conv t val (c, args) = strip_comb (rhs (concl thm)) in if (List.length args > 1 andalso List.exists (same_const c) stop_consts) then raise UNCHANGED else thm -end handle HOL_ERR _ => raise UNCHANGED) end - +end handle HOL_ERR _ => raise UNCHANGED) end + fun unlift_cases_typeinfos_ss til = let val rand_thms = List.map GSYM (Lib.mapfilter mk_case_rand_thm_tyinfo til) val rator_thms = List.map GSYM (Lib.mapfilter mk_case_rator_thm_tyinfo til) val abs_thms = List.map GSYM (Lib.mapfilter mk_case_abs_thm_tyinfo til) val consts = Lib.mapfilter case_const_of til - val conv_rand = unlift_case_const_CONV consts rand_thms + val conv_rand = unlift_case_const_CONV consts rand_thms val conv_rand_ss = simpLib.std_conv_ss { name = "unlift_case_const_CONV", pats = [``f x``], - conv = conv_rand} + conv = conv_rand} val conv_rator_ss = simpLib.std_conv_ss { name = "unlift_case_const_CONV", pats = [``f x``], - conv = Rewrite.GEN_REWRITE_CONV I empty_rewrites rator_thms} + conv = Rewrite.GEN_REWRITE_CONV I empty_rewrites rator_thms} val rewr_ss = simpLib.rewrites abs_thms in @@ -406,7 +406,7 @@ fun case_cong_stateful_ss () = case_cong_typeinfos_ss (TypeBase.elts ()) fun expand_type_quants_typeinfos_ss til = - rewrites (flatten (List.map (fn (x, y) => [x, y]) (Lib.mapfilter + rewrites (flatten (List.map (fn (x, y) => [x, y]) (Lib.mapfilter mk_type_quant_thms_tyinfo til))) fun expand_type_quants_ss tyL = expand_type_quants_typeinfos_ss (tyinfos_of_tys tyL) @@ -420,7 +420,7 @@ fun expand_type_quants_stateful_ss () = expand_type_quants_typeinfos_ss (TypeBas fun cases_to_top_RULE thm = let val input_thmL = BODY_CONJUNCTS thm - val (input_eqL, input_restL) = partition (fn thm => is_eq (concl thm)) input_thmL + val (input_eqL, input_restL) = partition (fn thm => is_eq (concl thm)) input_thmL fun process_eq eq_thm = let val free_vars_lhs = free_vars (lhs (concl eq_thm)); @@ -464,7 +464,7 @@ fun cases_to_top_RULE thm = let | SOME eq_thms => process_all acc (eq_thms @ thms)) val processed_eq_thms = process_all [] input_eqL - val all_thms = processed_eq_thms @ input_restL + val all_thms = processed_eq_thms @ input_restL in LIST_CONJ (List.map GEN_ALL all_thms) end diff --git a/src/enumfset/enumTacs.sml b/src/enumfset/enumTacs.sml index a9da911f5c..b5a61e3c6b 100644 --- a/src/enumfset/enumTacs.sml +++ b/src/enumfset/enumTacs.sml @@ -1,6 +1,6 @@ (* File: enumTacs.sml. Author: F. Lockwood Morris. Begun 6 Aug 2013. *) -(* Basic conversions and conversionals, and inference rules for *) +(* Basic conversions and conversionals, and inference rules for *) (* sorting lists, building ENUMERALS, look-up and converting them to *) (* OWL's, performing merge-based opns. on OWL's, recovering ENUMERALS. *) @@ -214,7 +214,7 @@ val [blr_nbl, blr_zer, blr_one] = CONJUNCTS bl_rev; blr_zer = |- !ft b. bl_rev ft (zerbl b) = bl_rev ft b blr_one = |- !ft a f b. bl_rev ft (onebl a f b) = bl_rev (node ft a f) b *) -fun bl_rev_CONV t = +fun bl_rev_CONV t = ((REWR_CONV blr_one THENC bl_rev_CONV) ORELSEC (REWR_CONV blr_zer THENC bl_rev_CONV) ORELSEC REWR_CONV blr_nbl) t; @@ -250,7 +250,7 @@ let val (s, ty) = dest_const t; val ety = hd (snd (dest_type ty)) in INST_TYPE [alpha |-> ety] LIST_TO_SET_NIL end else -let val (elem, st) = dest_binop (Term`($INSERT):'a->('a->bool)->'a->bool`) +let val (elem, st) = dest_binop (Term`($INSERT):'a->('a->bool)->'a->bool`) (ERR "DISPLAY_TO_set_CONV" "not a finite set extension") t; val ety = type_of elem in SPEC elem (MATCH_MP (INST_TYPE [alpha |-> ety] LIST_TO_SET_CONS) @@ -368,7 +368,7 @@ let fun olc t = ORELSEC olc))) t in olc end; -(* Top-level conversion works on a bt_to_ol, not a bt_to_ol_ac, term. +(* Top-level conversion works on a bt_to_ol, not a bt_to_ol_ac, term. Improved to check OL_bt first, and if this comes out T, as it always should, to use bt_to_list_CONV in place of bt_to_ol_lb/ub_CONV. *) @@ -376,7 +376,7 @@ val [aTT, aTF, aFT, aFF] = CONJUNCTS (prove ( ``(T/\T=T) /\ (T/\F=F) /\ (F/\T=F) /\ (F/\F=F)``, REWRITE_TAC [AND_CLAUSES])); -val AND_CONV = REWR_CONV aTT ORELSEC REWR_CONV aTF ORELSEC +val AND_CONV = REWR_CONV aTT ORELSEC REWR_CONV aTF ORELSEC REWR_CONV aFT ORELSEC REWR_CONV aFF; val [OL_lu_nt, OL_lu_node] = CONJUNCTS OL_bt_lb_ub; @@ -387,7 +387,7 @@ val [OL_lu_nt, OL_lu_node] = CONJUNCTS OL_bt_lb_ub; OL_bt_lb_ub cmp lb (node l x r) ub <=> OL_bt_lb_ub cmp lb l x /\ OL_bt_lb_ub cmp x r ub *) -fun OL_bt_lb_ub_CONV keyconv = +fun OL_bt_lb_ub_CONV keyconv = let fun olu t = ((REWR_CONV OL_lu_nt THENC LAND_CONV keyconv THENC EQ_LESS_CONV) ORELSEC (REWR_CONV OL_lu_node THENC @@ -401,7 +401,7 @@ val [OL_l_nt, OL_l_node] = CONJUNCTS OL_bt_lb; |- !cmp lb l x r. OL_bt_lb cmp lb (node l x r) <=> OL_bt_lb_ub cmp lb l x /\ OL_bt_lb cmp x r *) -fun OL_bt_lb_CONV keyconv = +fun OL_bt_lb_CONV keyconv = let fun ol t = ((REWR_CONV OL_l_node THENC LAND_CONV (OL_bt_lb_ub_CONV keyconv) THENC RAND_CONV ol THENC AND_CONV) @@ -415,7 +415,7 @@ val [OL_u_nt, OL_u_node] = CONJUNCTS OL_bt_ub; OL_bt_ub cmp (node l x r) ub <=> OL_bt_ub cmp l x /\ OL_bt_lb_ub cmp x r ub *) -fun OL_bt_ub_CONV keyconv = +fun OL_bt_ub_CONV keyconv = let fun ou t = ((REWR_CONV OL_u_node THENC LAND_CONV ou THENC RAND_CONV (OL_bt_lb_ub_CONV keyconv) THENC AND_CONV) @@ -645,7 +645,7 @@ incr_smerge_CONV numto_CONV imz; val ibl = Term`incr_sbuild numto [3; 1; 3; 4; 2; 1]`; incr_sbuild_CONV numto_CONV ibl; - + val mo5 = Term`smerge_out numto [5] [NONE; SOME [1; 3]; SOME [1; 2; 3; 4]]`; smerge_out_CONV numto_CONV mo5; @@ -773,7 +773,7 @@ SET_DIFF_CONV numto_CONV itwet'; val ta = rand (concl (DISPLAY_TO_ENUMERAL_CONV numto_CONV ``numto`` ``{4;1;3;5;2}``)); val tb = rand (concl (DISPLAY_TO_ENUMERAL_CONV - numto_CONV ``numto`` ``{3; 4; 6; 7; 3}``)); + numto_CONV ``numto`` ``{3; 4; 6; 7; 3}``)); val tc = rand (concl (DISPLAY_TO_ENUMERAL_CONV numto_CONV ``numto`` ``{5; 6; 4; 8; 3; 1}``)); diff --git a/src/enumfset/fmapalTacs.sml b/src/enumfset/fmapalTacs.sml index 885541ba6b..9194d0773f 100644 --- a/src/enumfset/fmapalTacs.sml +++ b/src/enumfset/fmapalTacs.sml @@ -1,6 +1,6 @@ (* File: fmapalTacs.sml. Author: F. Lockwood Morris. Begun 6 Aug 2013. *) -(* Basic conversions and conversionals, and inference rules for *) +(* Basic conversions and conversionals, and inference rules for *) (* sorting lists, building FMAPALS, look-up and converting them to *) (* lists and uniting and restricting them. *) @@ -256,7 +256,7 @@ val [ORL_lu_nt, ORL_lu_node] = CONJUNCTS ORL_bt_lb_ub; ORL_bt_lb_ub cmp lb (node l (x,y) r) ub <=> ORL_bt_lb_ub cmp lb l x /\ ORL_bt_lb_ub cmp x r ub *) -fun ORL_bt_lb_ub_CONV keyconv = +fun ORL_bt_lb_ub_CONV keyconv = let fun olu t = ((REWR_CONV ORL_lu_nt THENC LAND_CONV keyconv THENC EQ_LESS_CONV) ORELSEC (REWR_CONV ORL_lu_node THENC @@ -270,7 +270,7 @@ val [ORL_l_nt, ORL_l_node] = CONJUNCTS ORL_bt_lb; ORL_bt_lb cmp lb (node l (x,y) r) <=> ORL_bt_lb_ub cmp lb l x /\ ORL_bt_lb cmp x r *) -fun ORL_bt_lb_CONV keyconv = +fun ORL_bt_lb_CONV keyconv = let fun ol t = ((REWR_CONV ORL_l_node THENC LAND_CONV (ORL_bt_lb_ub_CONV keyconv) THENC RAND_CONV ol THENC AND_CONV) @@ -284,7 +284,7 @@ val [ORL_u_nt, ORL_u_node] = CONJUNCTS ORL_bt_ub; ORL_bt_ub cmp (node l (x,y) r) ub <=> ORL_bt_ub cmp l x /\ ORL_bt_lb_ub cmp x r ub *) -fun ORL_bt_ub_CONV keyconv = +fun ORL_bt_ub_CONV keyconv = let fun ou t = ((REWR_CONV ORL_u_node THENC LAND_CONV ou THENC RAND_CONV (ORL_bt_lb_ub_CONV keyconv) THENC AND_CONV) @@ -610,7 +610,7 @@ else FMAPAL_FUPDATE_CONV keyconv t; (* ******************************************************************* *) fun FMAPAL_EXPR_TO_ORWL keyconv t = -let val c = rator (rator t) +let val c = rator (rator t) in if is_const c then let val d = fst (dest_const c) in if d = "FMAPAL" then FMAPAL_TO_ORWL keyconv t @@ -623,7 +623,7 @@ in if is_const c then ORWL_DRESTRICT_COMPL keyconv (FMAPAL_EXPR_TO_ORWL keyconv (rand (rator t))) (ENUMERAL_TO_OWL keyconv (rand (rand t))) - else + else ORWL_DRESTRICT keyconv (FMAPAL_EXPR_TO_ORWL keyconv (rand (rator t))) (ENUMERAL_TO_OWL keyconv (rand t)) @@ -659,7 +659,7 @@ incr_merge_CONV numto_CONV imz; val ibl = Term`incr_build numto [(3,()); (1,()); (3,()); (4,()); (2,()); (1,())]`; incr_build_CONV numto_CONV ibl; - + val mo5 = Term`merge_out numto [(5,())] [NONE; SOME [(1,()); (3,())]; SOME [(1,()); (2,()); (3,()); (4,())]]`; merge_out_CONV numto_CONV mo5; diff --git a/src/enumfset/inttoTacs.sml b/src/enumfset/inttoTacs.sml index 27716e6133..27f4d65d6a 100644 --- a/src/enumfset/inttoTacs.sml +++ b/src/enumfset/inttoTacs.sml @@ -60,7 +60,7 @@ end; ``intOrd 2i 3i``, ``intOrd 2i (-3i)``, ``intOrd 3i (-3i)``, ``intOrd 0i (-2i)``, ``intOrd (0i) (-3i)``, ``intOrd 0i (-0i)``]; *) -val intto_CONV = +val intto_CONV = RATOR_CONV (RATOR_CONV (REWR_CONV apintto_thm)) THENC intOrd_CONV; diff --git a/src/enumfset/tcTacs.sml b/src/enumfset/tcTacs.sml index 83301b8194..9ebb47f53a 100644 --- a/src/enumfset/tcTacs.sml +++ b/src/enumfset/tcTacs.sml @@ -1,6 +1,6 @@ (* File: tcTacs.sml. Author: F. Lockwood Morris. Begun 6 Aug 2013. *) -(* Conversions culminating in TC_CONV, applicable to a term of the *) +(* Conversions culminating in TC_CONV, applicable to a term of the *) (* form (FMAP_TO_RELN (FMAPAL ... ))^+ (with ENUMERAL-sets as *) (* the map values), which it proves equal to one of the form *) (* (FMAP_TO_RELN (FMAPAL ......... )), alternatively applicable to a *) @@ -93,17 +93,17 @@ val cormenex = ``[(2, {4; 3}); (3, {2}); (4, {3; 1}); (1, {})]``; val corfmap = rand (concl (ENUF_CONV numto_CONV ``numto`` ``fmap ^cormenex``)); val Aplus = ``(FMAP_TO_RELN ^corfmap)^+``; - val keyconv = numto_CONV; + val keyconv = numto_CONV; - PRE_TC_CONV keyconv ``(FMAP_TO_RELN ^corfmap)^+``; - PRE_TC_CONV NO_CONV ``(FMAP_TO_RELN (fmap ^cormenex))^+``; + PRE_TC_CONV keyconv ``(FMAP_TO_RELN ^corfmap)^+``; + PRE_TC_CONV NO_CONV ``(FMAP_TO_RELN (fmap ^cormenex))^+``; val s123 = rand (concl (DISPLAY_TO_ENUMERAL_CONV numto_CONV ``numto`` ``{1; 2; 3}``)); val s345 = rand (concl (DISPLAY_TO_ENUMERAL_CONV numto_CONV ``numto`` ``{5; 4; 3}``)); TC_MOD_CONV numto_CONV ``TC_MOD 5 ^s123 ^s345``; - TC_MOD_CONV numto_CONV ``TC_MOD 5 ^s345 ^s123``; + TC_MOD_CONV numto_CONV ``TC_MOD 5 ^s345 ^s123``; val t123 = ``{1; 2; 3}``; val t345 = ``{5; 4; 3}``; TC_MOD_CONV REDUCE_CONV ``TC_MOD 5 ^t123 ^t345``; diff --git a/src/enumfset/totoTacs.sml b/src/enumfset/totoTacs.sml index 6bb7102695..36bd1aed3f 100644 --- a/src/enumfset/totoTacs.sml +++ b/src/enumfset/totoTacs.sml @@ -54,7 +54,7 @@ val cpn_REWR_CONV = REWR_CONV LESS_REWR ORELSEC REWR_CONV EQUAL_REWR ORELSEC (* **** Getting to toto-deciding conversions. **** *) (* *********************************************************************** *) -(* Given +(* Given lin_ord_thm: |- LinearOrder phi; toto_of_thm: |- cmp = toto_of_LinearOrder phi; eq_conv: reduces equations of ground terms (of phi's arg. type) to T/F; @@ -78,7 +78,7 @@ in fn (t:term) => (* supposed to have the form apto cmp t1 t2 *) let val (t1, t2) = (rand (rator t), rand t); val eq_verdict = eq_conv (mk_eq (t1, t2)) in PURE_MATCH_MP eq_thm eq_verdict - handle _ => + handle _ => let val cond = PURE_MATCH_MP uneq_thm eq_verdict; (* cond = `if phi x y then ... = LESS else ... = GREATER` *) val (phi12, arm1, arm2) = dest_cond (concl cond); @@ -121,7 +121,7 @@ fun numOrd_CONV t = Raise (ERR "numOrd_CONV" "not a numOrd test") end end; -val numto_CONV = +val numto_CONV = RATOR_CONV (RATOR_CONV (REWR_CONV apnumto_thm)) THENC numOrd_CONV; @@ -163,7 +163,7 @@ fun qk_numOrd_CONV t = Raise (ERR "qk_numOrd_CONV" "not a qk_numOrd test") end end; -val qk_numto_CONV = +val qk_numto_CONV = RATOR_CONV (RATOR_CONV (REWR_CONV ap_qk_numto_thm)) THENC qk_numOrd_CONV; @@ -198,8 +198,8 @@ val [lsnn, lsnc, lscn, lscc] = map GEN_ALL (CONJUNCTS (SPEC_ALL aplistoto)); fun listoto_CONV elem_conv = let fun lis_c t = - ((REWR_CONV lscc THENC - RATOR_CONV (RATOR_CONV (RATOR_CONV (RAND_CONV elem_conv))) THENC + ((REWR_CONV lscc THENC + RATOR_CONV (RATOR_CONV (RATOR_CONV (RAND_CONV elem_conv))) THENC ((REWR_CONV EQUAL_REWR THENC lis_c) ORELSEC REWR_CONV LESS_REWR ORELSEC REWR_CONV GREATER_REWR)) ORELSEC REWR_CONV lsnn ORELSEC REWR_CONV lsnc ORELSEC REWR_CONV lscn) t @@ -210,7 +210,7 @@ fun listoto_CONV elem_conv = val refl_clause_string = MATCH_MP TO_refl (ISPEC (Term`stringto`) TotOrd_apto); -fun stringto_CONV t = +fun stringto_CONV t = if rand (rator t) = rand t then SPEC (rand t) refl_clause_string else (RATOR_CONV (RATOR_CONV (RAND_CONV (REWR_CONV stringto))) THENC listoto_CONV charto_CONV) t; @@ -233,7 +233,7 @@ charto_CONV (Term`apto charto #"8" #"7"`); val testn = Count.apply (numto_CONV o Term); testn`apto numto 5 7`; -testn`apto numto 0 0`; +testn`apto numto 0 0`; val testc = Count.apply (charOrd_CONV o Term); diff --git a/src/floating-point/binary_ieeeSyntax.sml b/src/floating-point/binary_ieeeSyntax.sml index d30b825bf3..4b234b941f 100644 --- a/src/floating-point/binary_ieeeSyntax.sml +++ b/src/floating-point/binary_ieeeSyntax.sml @@ -129,7 +129,7 @@ val etw_monop = boolSyntax.mk_icomb (tm1, pairSyntax.mk_pair (t1, t2)) end) -val tw_binop = +val tw_binop = HolKernel.syntax_fns "binary_ieee" 2 (fn tm1 => fn e => fn tm2 => let @@ -304,7 +304,7 @@ val (float_mul_add_tm, mk_float_mul_add, dest_float_mul_add, is_float_mul_add) = val (round_tm, mk_round, dest_round, is_round) = tw_binop "round" -val (float_round_tm, mk_float_round, dest_float_round, is_float_round) = +val (float_round_tm, mk_float_round, dest_float_round, is_float_round) = tw_triop "float_round" (* ------------------------------------------------------------------------- *) diff --git a/src/num/extra_theories/numeral_bitScript.sml b/src/num/extra_theories/numeral_bitScript.sml index 998f9755e0..dca6542116 100644 --- a/src/num/extra_theories/numeral_bitScript.sml +++ b/src/num/extra_theories/numeral_bitScript.sml @@ -509,7 +509,7 @@ val MOD_2EXP_MAX = Q.store_thm("MOD_2EXP_MAX", [GSYM BITS_ZERO3, SYM BIT0_ODD, GSYM BIT_BITS_THM, BIT_DIV2, DIV2_def] \\ EQ_TAC \\ RW_TAC arith_ss [BIT_EXP_SUB1] - \\ Cases_on `x` + \\ Cases_on `x` \\ RW_TAC arith_ss []) (* ------------------------------------------------------------------------- *) diff --git a/src/portableML/mosml/Arbnumcore.sml b/src/portableML/mosml/Arbnumcore.sml index 3a8a92564f..b0526768c1 100644 --- a/src/portableML/mosml/Arbnumcore.sml +++ b/src/portableML/mosml/Arbnumcore.sml @@ -479,7 +479,7 @@ fun isqrt n = if n < two then n else let - fun iter a = + fun iter a = if a * a <= n andalso n < (a + one) * (a + one) then a else iter (div2 ((a * a + n) div a)) diff --git a/src/probability/extrealScript.sml b/src/probability/extrealScript.sml index 8bd8ba0129..4f210c7861 100644 --- a/src/probability/extrealScript.sml +++ b/src/probability/extrealScript.sml @@ -2635,11 +2635,11 @@ val sup_add_mono = store_thm ++ ONCE_REWRITE_TAC [GSYM SPECIFICATION] ++ METIS_TAC [IN_UNIV,IN_IMAGE]) ++ Cases_on `sup (IMAGE f UNIV) = PosInf` - >> (`sup (IMAGE (\n. sup (IMAGE f UNIV) + g n) UNIV) = PosInf` + >> (`sup (IMAGE (\n. sup (IMAGE f UNIV) + g n) UNIV) = PosInf` by (RW_TAC std_ss [extreal_add_def,sup_eq,le_infty] ++ POP_ASSUM (MP_TAC o Q.SPEC `PosInf`) ++ RW_TAC std_ss [] - ++ `PosInf <= y'` + ++ `PosInf <= y'` by (POP_ASSUM MATCH_MP_TAC ++ ONCE_REWRITE_TAC [GSYM SPECIFICATION] ++ RW_TAC std_ss [IN_UNIV,IN_IMAGE]) diff --git a/src/probability/lebesgueScript.sml b/src/probability/lebesgueScript.sml index 260b9e0132..a4c57bcb75 100644 --- a/src/probability/lebesgueScript.sml +++ b/src/probability/lebesgueScript.sml @@ -2293,7 +2293,7 @@ val lemma_fn_in_psfis = store_thm val integral_sequence = store_thm ("integral_sequence",``!m f. (!x. 0 <= f x) /\ measure_space m /\ f IN measurable (m_space m,measurable_sets m) Borel - ==> (pos_fn_integral m f = sup (IMAGE (\i. pos_fn_integral m (fn_seq m f i)) UNIV))``, + ==> (pos_fn_integral m f = sup (IMAGE (\i. pos_fn_integral m (fn_seq m f i)) UNIV))``, RW_TAC std_ss [] ++ MATCH_MP_TAC lebesgue_monotone_convergence ++ RW_TAC std_ss [lemma_fn_sup,lemma_fn_mono_increasing,lemma_fn_upper_bounded,lemma_fn_5] @@ -2301,7 +2301,7 @@ val integral_sequence = store_thm val measurable_sequence = store_thm -("measurable_sequence",``!m f. measure_space m /\ f IN measurable (m_space m,measurable_sets m) Borel ==> +("measurable_sequence",``!m f. measure_space m /\ f IN measurable (m_space m,measurable_sets m) Borel ==> (?fi ri. (!x. mono_increasing (\i. fi i x)) /\ (!x. x IN m_space m ==> (sup (IMAGE (\i. fi i x) UNIV) = fn_plus f x)) /\ (!i. ri i IN psfis m (fi i)) /\ @@ -2948,7 +2948,7 @@ val integrable_not_infty_alt3 = store_thm by (RW_TAC std_ss [fn_plus_def,FUN_EQ_THM] ++ Cases_on `f x` ++ METIS_TAC [lt_infty]) ++ `fn_minus (\x. if (f x = NegInf) \/ (f x = PosInf) then 0 else f x) = - (\x. if fn_minus f x = PosInf then 0 else fn_minus f x)` + (\x. if fn_minus f x = PosInf then 0 else fn_minus f x)` by (RW_TAC std_ss [fn_minus_def,FUN_EQ_THM] ++ Cases_on `f x` ++ METIS_TAC [lt_infty, lt_refl, extreal_ainv_def, extreal_not_infty]) @@ -3123,7 +3123,7 @@ val integral_mspace = store_thm val integral_mono = store_thm ("integral_mono", ``!m f1 f2. measure_space m /\ (!t. t IN m_space m ==> f1 t <= f2 t) ==> - (integral m f1 <= integral m f2)``, + (integral m f1 <= integral m f2)``, RW_TAC std_ss [] ++ ONCE_REWRITE_TAC [(UNDISCH o Q.SPECL [`m`,`f`]) integral_mspace] ++ RW_TAC std_ss [integral_def] diff --git a/src/quantHeuristics/doc/quantHeu.tex b/src/quantHeuristics/doc/quantHeu.tex index fbef37ef30..08ccae740f 100644 --- a/src/quantHeuristics/doc/quantHeu.tex +++ b/src/quantHeuristics/doc/quantHeu.tex @@ -2,7 +2,7 @@ \usepackage{amsthm} \usepackage{palatino} -\usepackage{amssymb} +\usepackage{amssymb} \usepackage{amsmath} \usepackage[sort&compress]{natbib} \usepackage{hyperref} @@ -64,13 +64,13 @@ \section{Motivation} and \[ \exists x_1\ \ldots x_i \ldots x_n.\ P_1 \wedge \ldots \wedge x_i = c \wedge \ldots \wedge P_n \] can be simplified by -instantiating $x_i$ with $c$. Because unwind-conversions are +instantiating $x_i$ with $c$. Because unwind-conversions are part of \texttt{bool\_ss}, they are used with nearly every call of the simplifier and often simplify proofs considerably. However, the unwind library can only handle these common cases. If the term structure is only slightly more complicated, it fails. For example, $\exists x.\ P(a) \Longrightarrow (x = 2) \wedge Q(x)$ cannot be tackled. -There is also the satisfy library\footnote{see \texttt{src/simp/src/Satisfy.sml}}, which uses unification to +There is also the satisfy library\footnote{see \texttt{src/simp/src/Satisfy.sml}}, which uses unification to show existentially quantified formulas. It can handle problems like $\exists x.\ P_1(x,c_1)\ \wedge \ldots P_n(x,c_n)$ if given theorems of the form $\forall x\ c.\ P_i(x, c)$. This is often handy, but still rather limited. @@ -101,10 +101,10 @@ \section{Motivation} $\forall x.\ x = 2$ & $\textit{false}$ \\ \tablehead{complicated nestings of standard operators} -$\exists x_1. \forall x_2.\ (x_1 = 2) \wedge P(x_1, x_2)$ & +$\exists x_1. \forall x_2.\ (x_1 = 2) \wedge P(x_1, x_2)$ & $\forall x_2.\ P(2, x_2)$ \\ -$\exists x_1, x_2.\ P_1(x_2) \Longrightarrow (x_1 = 2) \wedge P(x_1, x_2)$ & +$\exists x_1, x_2.\ P_1(x_2) \Longrightarrow (x_1 = 2) \wedge P(x_1, x_2)$ & $\exists x_2.\ P_1(x_2) \Longrightarrow P(2, x_2)$ \\ $\exists x.\ ((x = 2) \vee (2 = x)) \wedge P(x)$ & $P(2)$ \\ @@ -150,7 +150,7 @@ \section{Structure} this abstract presentation, Section~\ref{sec_examples} shows how guess-search works for simple examples. -The second part starts with a high level presentation of the user-interface in +The second part starts with a high level presentation of the user-interface in Section~\ref{sec_interface}. An important concept of the interface are quantifier heuristic parameters, which allow configuring the behaviour of the library. In Section~\ref{sec_qps} first predefined parameters are presented. @@ -169,7 +169,7 @@ \subsection{Weak Guesses for Existential Quantifiers} is a search based on heuristics. Abstractly, given a term $\exists x.\ P(x)$ we want to find an instantiation $\lambda \fv. i(\fv)$ such that $\exists x.\ P(x) \Longleftrightarrow \exists \fv.\ P(i(\fv))$ -holds. In the following, such an $i$ is called a \emph{guess} for +holds. In the following, such an $i$ is called a \emph{guess} for variable $x$ in $P(x)$. In order to justify such a guess, we define special predicates that capture the intended semantics. @@ -184,22 +184,22 @@ \subsection{Weak Guesses for Existential Quantifiers} \Longleftrightarrow 2 = 2$ holds. More interestingly, $\GE(\lambda(x, xs').\ x::xs'), \lambda xs.\ xs \neq [] \wedge P(xs))$ holds. Therefore, $\exists xs.\ xs \neq []\ \wedge\ P(xs)$ can be simplified -to $\exists x\ xs'.\ x::xs' \neq []\ \wedge\ P(x::xs')$. +to $\exists x\ xs'.\ x::xs' \neq []\ \wedge\ P(x::xs')$. \end{example} So, when trying to process $\exists x.\ P(x)$, we search for an existential guess $i$ such that $\GE(i, \lambda x. P(x))$ holds. If such a guess is found, the original term can be simplified to $\exists \fv.\ P(i(\fv))$, which is really \emph{simpler} provided sensible heuristics for creating -guesses are used. In particular, guesses $i$ that do not depend on $\fv$ frequently occur in practice. +guesses are used. In particular, guesses $i$ that do not depend on $\fv$ frequently occur in practice. The quantifier disappears completely in this common case. \subsection{Strong Guesses for Existential Quantifiers} -The general idea for coming up with a guess $\GE(i, P)$ is preforming +The general idea for coming up with a guess $\GE(i, P)$ is preforming a bottom-up search of the syntax tree of $P$. Unluckily, $\GE$ is -not well suited for such a search, because it is too weak to easily lift -guesses for subterms. Consider, for example, terms of the form +not well suited for such a search, because it is too weak to easily lift +guesses for subterms. Consider, for example, terms of the form $\exists x.\ P_1(x) \vee P_2(x)$. If we have a guess $\GE(i, P_1)$, we unluckily can't lift it to a guess $\GE(i, \lambda x.\ P_1(x) \vee P_2(x))$ in general. A counterexample is $P_1(x) := \textit{false}$, $P_2(x) := (x = 2)$ and $i := K\ 3 = \lambda \fv.\ 3$. @@ -228,7 +228,7 @@ \subsection{Strong Guesses for Existential Quantifiers} \begin{example} In addition to weak existential guesses $\GE(i,P)$, gap existential guesses $\GEG(i,P)$ carry information about all points except the gap $i$. -The guess $\GEG(K\ 2, \lambda x.\ x = 2\ \wedge\ Q(x))$ holds, because $\lambda x.\ (x = 2)\ \wedge\ Q(x)$ +The guess $\GEG(K\ 2, \lambda x.\ x = 2\ \wedge\ Q(x))$ holds, because $\lambda x.\ (x = 2)\ \wedge\ Q(x)$ does not hold for all values except possibly $2$. Since nothing is known about $Q$, we don't know, whether $P$ holds for the point $2$. This point is a gap in the argument. \end{example} @@ -266,7 +266,7 @@ \subsection{Guesses for Universal Quantifiers} \end{definition} Similar to guesses for existential quantification, we are mainly interested in weak universal guesses. Point and gap -universal guesses are stronger than universal ones and allow lifting. +universal guesses are stronger than universal ones and allow lifting. \subsection{Overview} @@ -305,42 +305,42 @@ \subsection{Overview} So, the core of the framework searches for guesses. Once found, the guesses are used as described by the following theorem: \begin{theorem}[Usage of Guesses]\label{lemma_guesses_usage} -Guesses are used to simplify formulae with quantifiers in various ways. In the most basic case, they can +Guesses are used to simplify formulae with quantifiers in various ways. In the most basic case, they can be used to (partially) instantiate quantifiers as follows: \[% \begin{array}[t]{cccrclc} - \GE(i, P) & \Longrightarrow & \Big( & \exists x.\ P(x) & \Leftrightarrow & \exists \fv.\ P(i(\fv)) & \Big) \\ - \GU(i, P) & \Longrightarrow & \Big( & \forall x.\ P(x) & \Leftrightarrow & \forall \fv.\ P(i(\fv)) & \Big) \\ + \GE(i, P) & \Longrightarrow & \Big( & \exists x.\ P(x) & \Leftrightarrow & \exists \fv.\ P(i(\fv)) & \Big) \\ + \GU(i, P) & \Longrightarrow & \Big( & \forall x.\ P(x) & \Leftrightarrow & \forall \fv.\ P(i(\fv)) & \Big) \\ \end{array} \] % If the guess does not depend on a free variable (as denoted by $K\ i_c$), the quantifier can be removed completely: \[ \begin{array}[t]{cccrclc} - \GE(K\ i_c, P) & \Longrightarrow & \Big( & \exists x.\ P(x) & \Leftrightarrow & P(i_c) & \Big) \\ - \GU(K\ i_c, P) & \Longrightarrow & \Big( & \forall x.\ P(x) & \Leftrightarrow & P(i_c) & \Big) \\ + \GE(K\ i_c, P) & \Longrightarrow & \Big( & \exists x.\ P(x) & \Leftrightarrow & P(i_c) & \Big) \\ + \GU(K\ i_c, P) & \Longrightarrow & \Big( & \forall x.\ P(x) & \Leftrightarrow & P(i_c) & \Big) \\ \end{array} \] Point guesses lead to even more simplification: \[ \begin{array}[t]{cccrclc} - \GEP(i, P) & \Longrightarrow & \Big( & \exists x.\ P(x) & \Leftrightarrow & \textit{true} & \Big) \\ - \GUP(i, P) & \Longrightarrow & \Big( & \forall x.\ P(x) & \Leftrightarrow & \textit{false} & \Big) \\ + \GEP(i, P) & \Longrightarrow & \Big( & \exists x.\ P(x) & \Leftrightarrow & \textit{true} & \Big) \\ + \GUP(i, P) & \Longrightarrow & \Big( & \forall x.\ P(x) & \Leftrightarrow & \textit{false} & \Big) \\ \end{array} \] -In contrast, the additional strength of gap guesses +In contrast, the additional strength of gap guesses is mainly important for lifting. For instantiating quantifiers the same rules as for existential and universal guesses apply. However, gap existential guesses are useful for handling unique existential quantification, provided the guess does not contain free variables. \[ \begin{array}[t]{cccrclc} - \GE(K\ i_c, P) & \Longrightarrow & \Big( & \exists! x.\ P(x) & \Leftrightarrow & - (P(i_c)\ \wedge\ \forall v.\ P(v) \Rightarrow v = i_c) & \Big) \\ - \GEG(K\ i_c, P) & \Longrightarrow & \Big( & \exists! x.\ P(x) & \Leftrightarrow & - P(i_c) & \Big) \\ - \GEP(K\ i_c, P) & \Longrightarrow & \Big( & \exists! x.\ P(x) & \Leftrightarrow & - (\forall v.\ P(v) \Rightarrow v = i_c) & \Big) + \GE(K\ i_c, P) & \Longrightarrow & \Big( & \exists! x.\ P(x) & \Leftrightarrow & + (P(i_c)\ \wedge\ \forall v.\ P(v) \Rightarrow v = i_c) & \Big) \\ + \GEG(K\ i_c, P) & \Longrightarrow & \Big( & \exists! x.\ P(x) & \Leftrightarrow & + P(i_c) & \Big) \\ + \GEP(K\ i_c, P) & \Longrightarrow & \Big( & \exists! x.\ P(x) & \Leftrightarrow & + (\forall v.\ P(v) \Rightarrow v = i_c) & \Big) \end{array} \] \end{theorem} @@ -360,32 +360,32 @@ \subsection{Oracle Guesses} An oracle guess carries no semantic information, it just states something like ``\textit{Trust me! This is a sensible guess!}''. Therefore, oracle guesses can only be used to prove implications instead of -equivalences. +equivalences. % \begin{lemma}[Usage of Oracle Guesses] \[ \begin{array}[t]{cccrclc} - \GO(i, P) & \Longrightarrow & \Big( & \exists x.\ P(x) & \Leftarrow & \exists \fv.\ P(i(\fv)) & \Big) \\ - \GO(i, P) & \Longrightarrow & \Big( & \forall x.\ P(x) & \Rightarrow & \forall \fv.\ P(i(\fv)) & \Big) + \GO(i, P) & \Longrightarrow & \Big( & \exists x.\ P(x) & \Leftarrow & \exists \fv.\ P(i(\fv)) & \Big) \\ + \GO(i, P) & \Longrightarrow & \Big( & \forall x.\ P(x) & \Rightarrow & \forall \fv.\ P(i(\fv)) & \Big) \end{array} \] \end{lemma} % -Oracle guesses allow the user to instantiate quantifiers without formal justification. -Therefore, they require hardly any theoretical foundation and +Oracle guesses allow the user to instantiate quantifiers without formal justification. +Therefore, they require hardly any theoretical foundation and are mainly interesting for tool implementation. Therefore, they won't be discussed much below. \section{Base Guesses} \label{sec_base_guesses} After introducing guesses, guess-search can be presented now. -This presentation is twofold. In this section, guesses for basic terms are discussed. Lifting guesses +This presentation is twofold. In this section, guesses for basic terms are discussed. Lifting guesses is presented in the next section. \subsection{Equations} The most basic, but also most common source of guesses are equations: \begin{lemma}[Guesses for Equations with Variables at Top-Level]\label{lemma_guesses_equation_top} -Given an equation $x = t$ such that the variable $x$ +Given an equation $x = t$ such that the variable $x$ does not occur in $t$, the term $t$ is both a point and gap existential guess for $x$: \[% @@ -396,7 +396,7 @@ \subsection{Equations} \end{lemma} % \begin{lemma}[Point Existential Guesses for Equations]\label{lemma_guesses_equation_T} -Given an equation $t_1(x) = t_2(x)$ and a term $i_c$ such that +Given an equation $t_1(x) = t_2(x)$ and a term $i_c$ such that the formula $t_1(i_c) = t_2(i_c)$ holds, the term $i_c$ is a point existential guess for $x$. This means that the following holds. \[ @@ -433,14 +433,14 @@ \subsection{Dichotomies}\label{subsec_base_guesses_dichotomies} \GUP(\lambda \fv.\ c_2(\fv),\ \lambda x.\ (x = c_1)) \\ (\forall x.\ x = c_1\ \vee\ (\exists \fv.\ x = c_2(\fv))) & \Longrightarrow & -\GUG(\lambda \fv.\ c_2(\fv),\ \lambda x.\ (x = c_1)) +\GUG(\lambda \fv.\ c_2(\fv),\ \lambda x.\ (x = c_1)) \end{array} \] \end{lemma} % Exploiting dichotomy is very useful in practice. Holfoot uses it to reason about lists. The variable \textit{pdata'} in the list-reversal example of the introduction can, for example, -be instantiated using the dichotomy of lists. Without this rule, Holfoot's inference rules for +be instantiated using the dichotomy of lists. Without this rule, Holfoot's inference rules for singly-linked list predicates would need to unfold the data-content manually. Many other datatypes unluckily have more than just two @@ -466,15 +466,15 @@ \subsection{Monochotomies} \subsection{Other guesses} The base guesses presented above are at the most important ones. However, other -trivial base guesses are exploited as well for the implementation. -The most important ones are point guesses that can be derived +trivial base guesses are exploited as well for the implementation. +The most important ones are point guesses that can be derived from some context information: % \begin{lemma}[Context Guesses]\label{lemma_guesses_context} \[ \begin{array}{l@{\quad\quad}l} P(c) \Longrightarrow \GEP(K\ c,\ \lambda x.\ P(x)) \\ -\neg P(c) \Longrightarrow \GUP(K\ c,\ \lambda x.\ P(x)) +\neg P(c) \Longrightarrow \GUP(K\ c,\ \lambda x.\ P(x)) \end{array} \] \end{lemma} @@ -484,11 +484,11 @@ \subsection{Other guesses} implement lifting efficiently: % \begin{lemma}[Guesses for Constants]\label{lemma_guesses_const} -Given a term $c$ such that a variable $x$ does not occur in $c$, any term $i$ is a -valid existential and universal guess: +Given a term $c$ such that a variable $x$ does not occur in $c$, any term $i$ is a +valid existential and universal guess: \[ \begin{array}{l@{\quad\quad}l} -\GE(i,\ \lambda x.\ c) & \GU(i,\ \lambda x.\ c) +\GE(i,\ \lambda x.\ c) & \GU(i,\ \lambda x.\ c) \end{array} \] \end{lemma} @@ -528,7 +528,7 @@ \subsection{Disjunction} \[ \begin{array}{l@{\quad}l@{\quad}l} \GEP(i,\ \lambda x.\ P_1(x)) & \Longrightarrow & \GEP(i,\ \lambda x.\ P_1(x) \vee P_2(x)) \\ -\GEP(i,\ \lambda x.\ P_2(x)) & \Longrightarrow & \GEP(i,\ \lambda x.\ P_1(x) \vee P_2(x)) +\GEP(i,\ \lambda x.\ P_2(x)) & \Longrightarrow & \GEP(i,\ \lambda x.\ P_1(x) \vee P_2(x)) \end{array} \] \end{lemma} @@ -556,7 +556,7 @@ \subsection{Disjunction} \[ \begin{array}{l@{\quad}l@{\quad}l} \GUG(i,\ \lambda x.\ P_1(x)) & \Longrightarrow & \GUG(i,\ \lambda x.\ P_1(x) \vee P_2(x)) \\ -\GUG(i,\ \lambda x.\ P_2(x)) & \Longrightarrow & \GUG(i,\ \lambda x.\ P_1(x) \vee P_2(x)) +\GUG(i,\ \lambda x.\ P_2(x)) & \Longrightarrow & \GUG(i,\ \lambda x.\ P_1(x) \vee P_2(x)) \end{array} \] \end{lemma} @@ -576,13 +576,13 @@ \subsection{Disjunction} \end{lemma} For universal guesses it is even more complicated, because the handling of free variables does not fit well. -The guess is not allowed to depend on any free variable (denoted by $K\ i_c$). +The guess is not allowed to depend on any free variable (denoted by $K\ i_c$). \begin{lemma}[Lifting Universal Guesses over Disjunction]\label{lemma_guesses_lift_disj_A} \[ \begin{array}{c@{\quad}c@{\quad}l} \begin{array}{cl} \GU(K\ i_c,\ \lambda x.\ P_1(x)) & \wedge \\ -\GU(K\ i_c,\ \lambda x.\ P_2(x)) +\GU(K\ i_c,\ \lambda x.\ P_2(x)) \end{array} & \Longrightarrow & \GU(K\ i_c,\ \lambda x.\ P_1(x) \vee P_2(x)) \\[1em] \GU(i,\ \lambda x.\ P_1(x)) & \Longrightarrow & \GU(i,\ \lambda x.\ P_1(x) \vee p_2) \\ \GU(i,\ \lambda x.\ P_2(x)) & \Longrightarrow & \GU(i,\ \lambda x.\ p_1 \vee P_2(x)) @@ -648,7 +648,7 @@ \subsection{Other Boolean Operations} \subsection{Quantifiers} -It remains to lift guesses over quantifiers. Let's first consider universal quantification. +It remains to lift guesses over quantifiers. Let's first consider universal quantification. If the guess does depend on the quantified variables, it becomes a free variable of the guess: \begin{lemma}[Lifting Guesses over Universal Quantification (1)]\label{lemma_guesses_lift_forall_1} @@ -680,7 +680,7 @@ \subsection{Quantifiers} (\forall y.\ \GEG(i,\ \lambda x.\ P(x, y)) & \Longrightarrow & \GEG(i,\ \lambda x.\ \forall y.\ P(x, y)) \\ (\forall y.\ \GUP(i,\ \lambda x.\ P(x, y)) & \Longrightarrow & \GUP(i,\ \lambda x.\ \forall y.\ P(x, y)) \\ (\forall y.\ \GU(i,\ \lambda x.\ P(x, y)) & \Longrightarrow & \GU(i,\ \lambda x.\ \forall y.\ P(x, y)) \\ -(\forall y.\ \GUG(i,\ \lambda x.\ P(x, y)) & \Longrightarrow & \GUG(i,\ \lambda x.\ \forall y.\ P(x, y)) +(\forall y.\ \GUG(i,\ \lambda x.\ P(x, y)) & \Longrightarrow & \GUG(i,\ \lambda x.\ \forall y.\ P(x, y)) \end{array} \] \end{lemma} @@ -692,7 +692,7 @@ \subsection{Quantifiers} \[ \begin{array}{c@{\quad}c@{\quad}l} (\forall y.\ \GUP(i,\ \lambda x.\ P(x, y)) & \Longrightarrow & \GUP(i,\ \lambda x.\ \exists! y.\ P(x, y)) \\ -(\forall y.\ \GEG(i,\ \lambda x.\ P(x, y)) & \Longrightarrow & \GEG(i,\ \lambda x.\ \exists! y.\ P(x, y)) +(\forall y.\ \GEG(i,\ \lambda x.\ P(x, y)) & \Longrightarrow & \GEG(i,\ \lambda x.\ \exists! y.\ P(x, y)) \end{array} \] \end{lemma} @@ -701,7 +701,7 @@ \subsection{Quantifiers} \section{Related Techniques}\label{sec_other_techniques} Above base guesses and lifting of guesses have been presented. This section now -briefly discusses other techniques that enhance guess search: +briefly discusses other techniques that enhance guess search: \subsection{Rewrites}\label{subsec_other_techniques_rewrites} @@ -726,7 +726,7 @@ \subsection{Strengthening and Weakening}\label{subsec_other_techniques_imp} \begin{lemma}[Strengthening / Weakening Guesses]\label{lemma_guesses_strengthen_weaken} \[ -\left(\forall x.\ P_1(x) \Rightarrow P_2(x)\right) \Longrightarrow +\left(\forall x.\ P_1(x) \Rightarrow P_2(x)\right) \Longrightarrow \left(\begin{array}{@{}rcl} \forall x.\ \GEP(i, P_1) & \Longrightarrow & \GEP(i,\ \lambda x.\ P_2) \qquad \wedge\\ \forall x.\ \GUG(i, P_1) & \Longrightarrow & \GUG(i,\ \lambda x.\ P_2) \qquad \wedge\\ @@ -742,17 +742,17 @@ \subsection{Strengthening and Weakening}\label{subsec_other_techniques_imp} \subsection{Minimising Variable Occurrences}\label{subsec_varmin} As for example Lemma~\ref{lemma_guesses_lift_disj_E} illustrates, it -is easier to find guesses for a variable if it occurs in fewer +is easier to find guesses for a variable if it occurs in fewer positions. Therefore, the HOL~4 implementation preprocesses the term and tries to minimise the number of occurrences. For example, $\exists x.\ (f (8 + 2) = f (x + 2)) \wedge P (f (x + 2))$ is rewritten to $\exists x.\ (f (8 + 2) = f (x + 2)) \wedge P (f (8 + 2))$ by this prepossessing step. This explains, why this example can be handled, whereas apparently similar ones cannot (see Table~\ref{table_examples}). -The implementation for minimising variable occurrences is based +The implementation for minimising variable occurrences is based on simple rules like $(x = t) \wedge P(x) \ \Longleftrightarrow\ (x = t) \wedge P(t)$ or $x \neq t \vee P(x) -\ \Longleftrightarrow\ x \neq t \vee P(t)$. +\ \Longleftrightarrow\ x \neq t \vee P(t)$. \section{Examples}\label{sec_examples} @@ -761,7 +761,7 @@ \section{Examples}\label{sec_examples} Let's now consider a few examples to see how this methods works in practice. \subsection{Example 1} -Let's start with the example +Let's start with the example $\exists x.\ (\forall y.\ Q(y)\ \wedge\ (x=7)) \ \wedge\ P(x)$. This example cannot be handled by existing tools. However, the lemmata presented above allow to @@ -775,11 +775,11 @@ \subsection{Example 1} \end{array} \] % -With Lemma~\ref{lemma_guesses_usage} we can therefore simplify -$\exists x.\ (\forall y.\ Q(y)\ \wedge\ (x=7)) \ \wedge\ P(x)$ to +With Lemma~\ref{lemma_guesses_usage} we can therefore simplify +$\exists x.\ (\forall y.\ Q(y)\ \wedge\ (x=7)) \ \wedge\ P(x)$ to $(\forall y.\ Q(y)\ \wedge\ (7=7)) \ \wedge\ P(7)$ and with some general infrastructure further to $(\forall y.\ Q(y)) \ \wedge\ P(7)$. -Here, only the trace that succeeds is presented. The search actually produces more guesses. +Here, only the trace that succeeds is presented. The search actually produces more guesses. For example, $\GEP(K\ 7, \lambda x.\ x = 7)$ is derived as well, but then fails to be lifted over the conjunction. @@ -788,11 +788,11 @@ \subsection{Example 2}\label{subsec_Example_2} \[\begin{array}{cc@{\qquad}l} \GUG(\lambda x'.\ \textsf{SOME}(x'), \lambda x.\ x = \textsf{NONE}) & \text{(1)} & \text{from Lemma~\ref{lemma_guesses_dichotomy}} \\ \GUG(\lambda x'.\ \textsf{SOME}(x'), \lambda x.\ \textsf{IS\_NONE}(x)) & \text{(2)} & \text{rewrite of (1)} \\ -\GUG(\lambda x'.\ \textsf{SOME}(x'), \lambda x.\ \textsf{IS\_NONE}(x) \vee P(x)) & \text{(3)} & \text{from (2) and Lemma~\ref{lemma_guesses_lift_disj_SA}} +\GUG(\lambda x'.\ \textsf{SOME}(x'), \lambda x.\ \textsf{IS\_NONE}(x) \vee P(x)) & \text{(3)} & \text{from (2) and Lemma~\ref{lemma_guesses_lift_disj_SA}} \end{array} \] -Therefore, -$\forall x.\ \textsf{IS\_NONE}(x) \vee P(x)$ can be simplified to +Therefore, +$\forall x.\ \textsf{IS\_NONE}(x) \vee P(x)$ can be simplified to $\forall x'.\ P(\textsf{SOME}(x'))$. \subsection{Example 3} @@ -818,8 +818,8 @@ \subsection{Example 3} Thus, we found a guess and can instantiate the quantifier with 8. \subsection{Example 4} -Finally, consider $\big((\forall x.\ P_1(x) \Rightarrow P_2(x)) \wedge P_1(2)\big) \Longrightarrow \exists x.\ P_2(x)$. -First, HOL~4's general infrastructure processes this and allows us to concentrate on +Finally, consider $\big((\forall x.\ P_1(x) \Rightarrow P_2(x)) \wedge P_1(2)\big) \Longrightarrow \exists x.\ P_2(x)$. +First, HOL~4's general infrastructure processes this and allows us to concentrate on $\exists x.\ P_2(x)$, while using (1) $\forall x.\ P_1(x) \Rightarrow P_2(x)$ and (2)~$P_1(2)$ as lemmata. Then guesses can be derived as follows: \[\begin{array}{cc@{\qquad}l} @@ -827,7 +827,7 @@ \subsection{Example 4} \GEP(K\ 2, \lambda x.\ P_2(x)) & \text{(4)} & \text{from (1), (3), Lemma~\ref{lemma_guesses_strengthen_weaken}} \end{array} \] -Thus, we found a guess and can simplify the original goal first to +Thus, we found a guess and can simplify the original goal first to $\big((\forall x.\ P_1(x) \Rightarrow P_2(x)) \wedge P_1(2)\big) \Longrightarrow \textit{true}$ and then further to \textit{true}. @@ -838,7 +838,7 @@ \section{User Interface}\label{sec_interface} The quantifier heuristics library can be found in the sub-directory \texttt{src/quantHeuristics}. The entry point to the framework is the -library \texttt{quantHeuristicsLib}. +library \texttt{quantHeuristicsLib}. \subsection{Conversions} Usually the library is used for @@ -851,15 +851,15 @@ \subsection{Conversions} \texttt{QUANT\_INSTANTIATE\_CONV} & \texttt{: quant\_param list -> conv} \\ \texttt{QUANT\_INST\_ss} & \texttt{: quant\_param list -> ssfrag} \\ \texttt{QUANT\_INSTANTIATE\_TAC} & \texttt{: quant\_param list -> tactic} \\ -\texttt{ASM\_QUANT\_INSTANTIATE\_TAC} & \texttt{: quant\_param list -> tactic} +\texttt{ASM\_QUANT\_INSTANTIATE\_TAC} & \texttt{: quant\_param list -> tactic} \end{tabular} \bigskip All these functions get a list of \emph{quantifier heuristic parameters} as arguments. These parameters essentially configure, which heuristics are used during the guess-search. If an empty list is provided, the tools know about the standard Boolean combinators, equations and context. -\texttt{std\_qp} adds support for common datatypes like pairs or lists. -Quantifier heuristic parameters are explained in more detail in +\texttt{std\_qp} adds support for common datatypes like pairs or lists. +Quantifier heuristic parameters are explained in more detail in Section~\ref{sec_qps}. So, some simple usage of the quantifier heuristic library looks like: @@ -874,7 +874,7 @@ \subsection{Conversions} Usually, the quantifier heuristics library is used together with the simplifier using \texttt{QUANT\_INST\_ss}. Besides interleaving -simplification and quantifier instantiation, this has the benefit of +simplification and quantifier instantiation, this has the benefit of being able to use context information collected by the simplifier: {\scriptsize @@ -917,8 +917,8 @@ \subsection{Unjustified Guesses} However, $2$ looks tempting and is probably sensible in many situations. (Counterexample: $P(2)$, $\neg Q(2)$ and $\neg P(3)$ hold) -\texttt{implication\_concl\_qp} is a quantifier parameter that looks for valid guesses in the conclusion of an implication. -Then, it assumes without justification that these guesses are probably sensible for the whole implication as well. +\texttt{implication\_concl\_qp} is a quantifier parameter that looks for valid guesses in the conclusion of an implication. +Then, it assumes without justification that these guesses are probably sensible for the whole implication as well. Because these guesses might be wrong, one can either use implications or expansion theorems like $\exists x. P(x)\ \Leftrightarrow (\forall x.\ (x \neq c) \Rightarrow \neg P(x)) \Rightarrow P(c)$. @@ -927,7 +927,7 @@ \subsection{Unjustified Guesses} > QUANT_INSTANTIATE_CONV [implication_concl_qp] ``?x. P x ==> (x = 2) /\ Q x`` Exception- UNCHANGED raised -> QUANT_INSTANTIATE_CONSEQ_CONV [implication_concl_qp] CONSEQ_CONV_STRENGTHEN_direction +> QUANT_INSTANTIATE_CONSEQ_CONV [implication_concl_qp] CONSEQ_CONV_STRENGTHEN_direction ``?x. P x ==> (x = 2) /\ Q x`` val it = |- (P 2 ==> Q 2) ==> ?x. P x ==> (x = 2) /\ Q x: thm @@ -950,12 +950,12 @@ \subsection{Unjustified Guesses} \texttt{QUANT\_INSTANTIATE\_CONSEQ\_CONV} & \texttt{: quant\_param list -> directed\_conseq\_conv} \\ \texttt{EXPAND\_QUANT\_INSTANTIATE\_CONV} & \texttt{: quant\_param list -> conv} \\ \texttt{EXPAND\_QUANT\_INST\_ss} & \texttt{: quant\_param list -> ssfrag} \\ -\texttt{QUANT\_INSTANTIATE\_CONSEQ\_TAC} & \texttt{: quant\_param list -> tactic} +\texttt{QUANT\_INSTANTIATE\_CONSEQ\_TAC} & \texttt{: quant\_param list -> tactic} \end{tabular} \subsection{Debugging} -To debug the guess-search, it is possible to print tracing information. +To debug the guess-search, it is possible to print tracing information. This is done by setting the trace \texttt{QUANT\_INSTANTIATE\_HEURISTIC} to 1 or 2. For the example in Sec.~\ref{subsec_Example_2} the debug output looks like: @@ -1019,7 +1019,7 @@ \subsection{Interface Details} \item[\texttt{re\ :\ bool}] redescent into a term after some instantiation has been found? It determines, whether internally \texttt{DEPTH\_CONV} or \texttt{REDEPTH\_CONV} is used. - \item[\texttt{min\_var\_occs\ :\ bool}] add a preprocessing step to minimise the number of occurrences of + \item[\texttt{min\_var\_occs\ :\ bool}] add a preprocessing step to minimise the number of occurrences of a variable (see Sec.\ref{subsec_varmin}). Since this preprocessing might be slow, one might want to skip it. \item[\texttt{expand\ :\ bool}] use expansion to exploit unjustified guesses? @@ -1038,7 +1038,7 @@ \subsection{Interface Details} arguments, except \texttt{expand} and \texttt{ctx}. Since it can use implications, expansion is not needed. Because \texttt{DEPTH\_CONSEQ\_CONV} collects its own context and can't easily -be used with the simplifier anyhow, \texttt{ctx} is unnecessary. +be used with the simplifier anyhow, \texttt{ctx} is unnecessary. \texttt{EXTENSIBLE\_QUANT\_INST\_ss} is a wrapper of the conversion that removes the arguments \texttt{re} and \texttt{ctx}, because they are taken care of by the simplifier. @@ -1055,8 +1055,8 @@ \subsection{Explicit Instantiations} A special (slightly degenerated) use of the framework, is turning guess search off completely and providing instantiations explicitly. The tactic \texttt{QUANT\_TAC} allows this. This means that it allows to partially instantiate quantifiers at subpositions -with explicitly given terms. As such, it can be seen as -a generalisation of \texttt{EXISTS\_TAC}. +with explicitly given terms. As such, it can be seen as +a generalisation of \texttt{EXISTS\_TAC}. % {\scriptsize \begin{verbatim} @@ -1086,8 +1086,8 @@ \section{Quantifier Heuristic Parameters}\label{sec_qps} \subsection{Quantifier Heuristic Parameters for Common Datatypes} -There are \texttt{option\_qp}, \texttt{list\_qp}, \texttt{num\_qp} and \texttt{sum\_qp} for option types, lists, -natural numbers and sum types respectively. +There are \texttt{option\_qp}, \texttt{list\_qp}, \texttt{num\_qp} and \texttt{sum\_qp} for option types, lists, +natural numbers and sum types respectively. Some examples are displayed in the following table: % \[\begin{array}{r@{\quad \Longleftrightarrow \quad}l} @@ -1095,13 +1095,13 @@ \subsection{Quantifier Heuristic Parameters for Common Datatypes} \forall x.\ \texttt{IS\_NONE}(x)& \textit{false} \\ \forall l.\ l \neq [\,] \Rightarrow P(l)& \forall h, l'.\ P(h::l') \\ \forall x.\ x = c + 3& \textit{false} \\ -\forall x.\ x \neq 0 \Rightarrow P(x)& \forall x'.\ P(\texttt{SUC}(x')) +\forall x.\ x \neq 0 \Rightarrow P(x)& \forall x'.\ P(\texttt{SUC}(x')) \end{array}\] \subsection{Quantifier Heuristic Parameters for Tuples} For tuples the situation is peculiar, because each quantifier over a variable of a product type -can be instantiated. The challenge is to decide which quantifiers should be instantiated and +can be instantiated. The challenge is to decide which quantifiers should be instantiated and which new variable names to use for the components of the pair. There is a quantifier heuristic parameter called \texttt{pair\_default\_qp}. It first looks for subterms of the form $(\lambda (x_1, \ldots, x_n).\ \ldots)\ x$. If such a term is found, $x$ is instantiated with @@ -1110,7 +1110,7 @@ \subsection{Quantifier Heuristic Parameters for Tuples} % \[\begin{array}{r@{\quad \Longleftrightarrow \quad}l} \forall p.\ (x = \texttt{SND}(p)) \Rightarrow P(p)& \forall p_1.\ P(p_1, x) \\ -\exists p.\ (\lambda (p_a, p_b, p_c). P(p_a, p_b, p_c))\ p & \exists p_a, p_b, p_c.\ P(p_a, p_b, p_c) +\exists p.\ (\lambda (p_a, p_b, p_c). P(p_a, p_b, p_c))\ p & \exists p_a, p_b, p_c.\ P(p_a, p_b, p_c) \end{array}\] \texttt{pair\_default\_qp} is implemented in terms of the more general @@ -1122,7 +1122,7 @@ \subsection{Quantifier Heuristic Parameters for Tuples} is not instantiated. In the example of $\exists p.\ (\lambda (p_a, p_b, p_c). P(p_a, p_b, p_c))\ p$ these functions are given the variable $p$ and the term $(\lambda (p_a, p_b, p_c). P(p_a, p_b, -p_c))\ p$ and return $\texttt{SOME} (p_a, p_b, p_c)$. +p_c))\ p$ and return $\texttt{SOME} (p_a, p_b, p_c)$. \subsection{Quantifier Heuristic Parameter for Records} @@ -1163,20 +1163,20 @@ \section{User defined Quantifier Heuristic Parameters}\label{sec_qps_user} \subsection{Rewrites / Conversions} -As discussed in Sec.~\ref{subsec_other_techniques_rewrites}, adding +As discussed in Sec.~\ref{subsec_other_techniques_rewrites}, adding rewrites is a very powerful technique. \texttt{rewrite\_qp} allows to provide rewrites in the form of rewrite theorems. For the example of \texttt{IS\_SOME} discussed in Sec.~\label{subsec_other_techniques_rewrites} this looks like: {\scriptsize \begin{verbatim} -> val thm = QUANT_INSTANTIATE_CONV [] ``!x. IS_SOME x ==> P x`` +> val thm = QUANT_INSTANTIATE_CONV [] ``!x. IS_SOME x ==> P x`` Exception- UNCHANGED raised > val IS_SOME_EXISTS = prove (``IS_SOME x = (?x'. x = SOME x')``, Cases_on `x` THEN SIMP_TAC std_ss []); val IS_SOME_EXISTS = |- IS_SOME x <=> ?x'. x = SOME x': thm -> val thm = QUANT_INSTANTIATE_CONV [rewrite_qp[IS_SOME_EXISTS]] ``!x. IS_SOME x ==> P x`` +> val thm = QUANT_INSTANTIATE_CONV [rewrite_qp[IS_SOME_EXISTS]] ``!x. IS_SOME x ==> P x`` val thm = |- (!x. IS_SOME x ==> P x) <=> !x'. IS_SOME (SOME x') ==> P (SOME x'): thm \end{verbatim}} @@ -1185,7 +1185,7 @@ \subsection{Rewrites / Conversions} {\scriptsize \begin{verbatim} -> val thm = QUANT_INSTANTIATE_CONV [rewrite_qp[IS_SOME_EXISTS], final_rewrite_qp[option_CLAUSES]] +> val thm = QUANT_INSTANTIATE_CONV [rewrite_qp[IS_SOME_EXISTS], final_rewrite_qp[option_CLAUSES]] ``!x. IS_SOME x ==> P x`` val thm = |- (!x. IS_SOME x ==> P x) <=> !x'. P (SOME x'): thm \end{verbatim}} @@ -1194,7 +1194,7 @@ \subsection{Rewrites / Conversions} {\scriptsize \begin{verbatim} -> val thm = QUANT_INSTANTIATE_CONV [] ``?x. (\y. y = 2) x`` +> val thm = QUANT_INSTANTIATE_CONV [] ``?x. (\y. y = 2) x`` Exception- UNCHANGED raised > val thm = QUANT_INSTANTIATE_CONV [convs_qp[BETA_CONV]] ``?x. (\y. y = 2) x`` @@ -1209,7 +1209,7 @@ \subsection{Strengthening / Weakening} {\scriptsize \begin{verbatim} -> val thm = QUANT_INSTANTIATE_CONV [list_qp] ``!l. 0 < LENGTH l ==> P l`` +> val thm = QUANT_INSTANTIATE_CONV [list_qp] ``!l. 0 < LENGTH l ==> P l`` Exception- UNCHANGED raised > val LENGTH_LESS_IMP = prove (``!l n. n < LENGTH l ==> l <> []``, Cases_on `l` THEN SIMP_TAC list_ss []); @@ -1220,27 +1220,27 @@ \subsection{Strengthening / Weakening} |- (!l. 0 < LENGTH l ==> P l) <=> !l_t l_h. 0 < LENGTH (l_h::l_t) ==> P (l_h::l_t): thm -> val thm = SIMP_CONV (list_ss ++ QUANT_INST_ss [imp_qp[LENGTH_LESS_IMP], list_qp]) [] +> val thm = SIMP_CONV (list_ss ++ QUANT_INST_ss [imp_qp[LENGTH_LESS_IMP], list_qp]) [] ``!l. SUC (SUC n) < LENGTH l ==> P l`` val thm = |- (!l. SUC (SUC n) < LENGTH l ==> P l) <=> !l_h l_t_h l_t_t_t l_t_t_h. n < SUC (LENGTH l_t_t_t) ==> P (l_h::l_t_h::l_t_t_h::l_t_t_t): thm \end{verbatim}} - + \subsection{Filtering} -Sometimes, one might want to avoid to instantiate certain quantifiers. +Sometimes, one might want to avoid to instantiate certain quantifiers. The function \texttt{filter\_qp} allows to add ML-functions that filter the handled -quantifiers. These functions are given a variable $x$ and a term $P(x)$. +quantifiers. These functions are given a variable $x$ and a term $P(x)$. The tool only tries to find instantiate $x$ in $P(x)$, if all filter functions -return \textit{true}. +return \textit{true}. {\scriptsize \begin{verbatim} > val thm = QUANT_INSTANTIATE_CONV [] ``?x y z. (x = 1) /\ (y = 2) /\ (z = 3) /\ P (x, y, z)`` val thm = |- (?x y z. (x = 1) /\ (y = 2) /\ (z = 3) /\ P (x,y,z)) <=> P (1,2,3): thm -> val thm = QUANT_INSTANTIATE_CONV [filter_qp [fn v => fn t => (v = ``y:num``)]] +> val thm = QUANT_INSTANTIATE_CONV [filter_qp [fn v => fn t => (v = ``y:num``)]] ``?x y z. (x = 1) /\ (y = 2) /\ (z = 3) /\ P (x, y, z)`` val thm = |- (?x y z. (x = 1) /\ (y = 2) /\ (z = 3) /\ P (x,y,z)) <=> ?x z. (x = 1) /\ (z = 3) /\ P (x,2,z): thm @@ -1248,8 +1248,8 @@ \subsection{Filtering} \subsection{Satisfying and Contradicting Instantiations} -As the satisfy library\footnote{see \texttt{src/simp/src/Satisfy.sml}} demonstrates, it is often -useful to use unification and explicitly given theorems to +As the satisfy library\footnote{see \texttt{src/simp/src/Satisfy.sml}} demonstrates, it is often +useful to use unification and explicitly given theorems to find instantiations. In addition to satisfying instantiations, the quantifier heuristics framework is also able to use contradicting ones. The theorems used for finding instantiations usually come from the context. However, \texttt{instantiation\_qp} allows to add additional ones: @@ -1259,7 +1259,7 @@ \subsection{Satisfying and Contradicting Instantiations} > val thm = SIMP_CONV (std_ss++QUANT_INST_ss[]) [] ``P n ==> ?m:num. n <= m /\ P m`` Exception- UNCHANGED raised -> val thm = SIMP_CONV (std_ss++QUANT_INST_ss[instantiation_qp[arithmeticTheory.LESS_EQ_REFL]]) [] +> val thm = SIMP_CONV (std_ss++QUANT_INST_ss[instantiation_qp[arithmeticTheory.LESS_EQ_REFL]]) [] ``P n ==> ?m:num. n <= m /\ P m`` > val thm = |- P n ==> ?m:num. n <= m /\ P m = T : thm @@ -1269,9 +1269,9 @@ \subsection{Di- and Monochotomies} As discussed in Sec.~\ref{subsec_base_guesses_dichotomies}, dichotomies can be exploited for guess search. \texttt{distinct\_qp} provides an interface to add theorems -of the form $\forall x.\ c_1(x) \neq c_2(x)$. +of the form $\forall x.\ c_1(x) \neq c_2(x)$. \texttt{cases\_qp} expects theorems of the form -$\forall x. \ (x = \exists \fv. c_1(\fv))\ \vee \ldots \vee (x = \exists \fv. c_n(\fv))$. +$\forall x. \ (x = \exists \fv. c_1(\fv))\ \vee \ldots \vee (x = \exists \fv. c_n(\fv))$. These theorems are for $n = 2$ used with Lemma~\ref{lemma_guesses_dichotomy} and for $n=1$ with Lemma~\ref{lemma_guesses_monochotomy}. All other cases are currently ignored. @@ -1294,7 +1294,7 @@ \subsection{Lifting Theorems} occurrence of $P_1 \Leftrightarrow P_2$ with for example $(P_1 \wedge P_2) \vee (\neg P_1 \wedge \neg P_2)$. However, this may lead to an exponential blowup of the size of the original term, since both $P_1$ -and $P_2$ occur twice in the result. Therefore, it is more efficient to +and $P_2$ occur twice in the result. Therefore, it is more efficient to provide a new lifting inference for equivalences. Such a rule can easily be derived using the existing rules for basic Boolean operations. \end{example} @@ -1302,7 +1302,7 @@ \subsection{Lifting Theorems} \subsection{Oracle Guesses} Sometimes, the user does not want to justify guesses. The tactic -\texttt{QUANT\_TAC} is implemented using oracle guesses for example. +\texttt{QUANT\_TAC} is implemented using oracle guesses for example. A simple interface to oracle guesses is provided by \texttt{oracle\_qp}. It expects a ML function that given a variable and a term returns an pair of an instantiation and the free variables in this instantiation. @@ -1325,14 +1325,14 @@ \subsection{Oracle Guesses} \noindent Notice, that an option type is returned and that the function is -allowed to throw \texttt{HOL\_ERR} exceptions. +allowed to throw \texttt{HOL\_ERR} exceptions. With this definition, the call \begin{verbatim} -NORE_QUANT_INSTANTIATE_CONSEQ_CONV [dummy_list_qp] +NORE_QUANT_INSTANTIATE_CONSEQ_CONV [dummy_list_qp] CONSEQ_CONV_STRENGTHEN_direction ``?x:'a list y:'b. P (x, y)`` \end{verbatim} -results in -\verb+(?y x_hd x_tl. P (x_hd::x_tl,y)) ==> ?x y. P (x,y) : thm+. +results in +\verb+(?y x_hd x_tl. P (x_hd::x_tl,y)) ==> ?x y. P (x,y) : thm+. \subsection{User defined Quantifier Heuristics}\label{subsec_user_defined_quantheu} @@ -1352,7 +1352,7 @@ \subsection{User defined Quantifier Heuristics}\label{subsec_user_defined_quanth \chapter{Conclusion}\label{sec_conclusion} -The quantifier heuristic is a powerful tool to instantiate quantifiers. +The quantifier heuristic is a powerful tool to instantiate quantifiers. It subsumes the power of the existing unwind and satisfy libraries. More importantly though, it is very flexible and easily extendable by the user. Moreover, it can be used to instantiate quantifiers using unjustified guesses. diff --git a/src/quantHeuristics/selftest.sml b/src/quantHeuristics/selftest.sml index 3fc3cf62b6..ebc57cf621 100644 --- a/src/quantHeuristics/selftest.sml +++ b/src/quantHeuristics/selftest.sml @@ -19,7 +19,7 @@ let val _ = print ("``\n "); val ct = Timer.startCPUTimer(); val thm_opt = SOME (conv t) handle Interrupt => raise Interrupt - | _ => NONE; + | _ => NONE; val ok = if not (isSome r_opt) then not (isSome thm_opt) else isSome thm_opt andalso diff --git a/src/tfl/src/Defn.sml b/src/tfl/src/Defn.sml index 2e403a9363..08832587ae 100644 --- a/src/tfl/src/Defn.sml +++ b/src/tfl/src/Defn.sml @@ -571,8 +571,8 @@ fun elim_triv_literal_CONV tm = fun checkSV pats SV = let fun get_pat (GIVEN(p,_)) = p | get_pat (OMITTED(p,_)) = p - fun strings_of vlist = - Lib.commafy (List.map (Lib.quote o #1 o dest_var) + fun strings_of vlist = + Lib.commafy (List.map (Lib.quote o #1 o dest_var) (Listsort.sort Term.compare vlist)) in if null SV then () @@ -584,7 +584,7 @@ fun checkSV pats SV = of [] => () | probs => raise ERR "wfrec_eqns" - (String.concat + (String.concat (["the following variables occur both free (schematic) ", "and bound in the definition: \n "] @ strings_of probs)) end diff --git a/src/tfl/src/Induction.sml b/src/tfl/src/Induction.sml index c5c0802a06..dab58326cb 100644 --- a/src/tfl/src/Induction.sml +++ b/src/tfl/src/Induction.sml @@ -165,18 +165,18 @@ val mk = mk_case ty_info FV thy mk in_1 val in -hm = mk_case ty_info FV thy {path=[z], rows=rows} +hm = mk_case ty_info FV thy {path=[z], rows=rows} -val arg0 = {path=[z], rows=rows} +val arg0 = {path=[z], rows=rows} val {path=rstp0, rows = rows0} = el 1 news *) -fun mk_case_choose_column i rows = +fun mk_case_choose_column i rows = let val col_i = map (fn (l, _) => el (i+1) l) rows - val col_i_ok = + val col_i_ok = (all is_var col_i) orelse (all (fn p => Literal.is_literal p orelse is_var p) col_i) orelse (all (fn p => not (Literal.is_pure_literal p) andalso not (is_var p)) col_i) @@ -198,9 +198,9 @@ fun mk_case ty_info FV thy = let val col_index = mk_case_choose_column 0 rows0 val rows = map (fn (pL, rhs) => (bring_to_front_list col_index pL, rhs)) rows0 val (pat_rectangle,rights) = unzip rows - val u_rstp = bring_to_front_list col_index rstp0 + val u_rstp = bring_to_front_list col_index rstp0 val (u, rstp) = (hd u_rstp, tl u_rstp) - val p = hd (fst (hd rows)) + val p = hd (fst (hd rows)) val col0 = map (Lib.trye hd) pat_rectangle val pat_rectangle' = map (Lib.trye tl) pat_rectangle in @@ -305,7 +305,7 @@ fun complete_cases thy = val th0 = ASSUME a_eq_z val rows:row list = map (fn x => ([x], (th0,[]))) pats - val cases_thm0 = mk_case ty_info FV thy {path=[z], rows=rows} + val cases_thm0 = mk_case ty_info FV thy {path=[z], rows=rows} fun mk_pat_pred p = list_mk_exists (free_vars_lr p, mk_eq(a, p)) val cases_tm = list_mk_disj (map mk_pat_pred pats) From 876ff199290730573e44bbb033c5f6b0b25689bd Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Thu, 11 Dec 2014 23:04:56 +1100 Subject: [PATCH 047/718] expand_list to interactively work on a list of subgoals also Tactical.VALID_LT, to check that a list-tactical is valid (expand_list checks validity, expand_listf doesn't) also abbreviations elt, eall, eta, enth to apply (list-)tactic to subgoal(s) --- help/Docfiles/Tactical.FAIL_LT.doc | 21 ++++ help/Docfiles/Tactical.NO_LT.doc | 20 ++++ help/Docfiles/Tactical.NULL_OK_LT.doc | 2 +- help/Docfiles/Tactical.ORELSE_LT.doc | 23 +++++ help/Docfiles/Tactical.REPEAT_LT.doc | 23 +++++ help/Docfiles/Tactical.TRYALL.doc | 28 ++++++ help/Docfiles/Tactical.TRY_LT.doc | 23 +++++ help/Docfiles/Tactical.VALID_LT.doc | 31 ++++++ help/Docfiles/proofManagerLib.eall.doc | 26 +++++ help/Docfiles/proofManagerLib.elt.doc | 23 +++++ help/Docfiles/proofManagerLib.enth.doc | 26 +++++ help/Docfiles/proofManagerLib.eta.doc | 28 ++++++ help/Docfiles/proofManagerLib.expand_list.doc | 95 +++++++++++++++++++ .../Docfiles/proofManagerLib.expand_listf.doc | 47 +++++++++ src/0/Overlay.sml | 3 +- src/1/Tactical.sig | 7 ++ src/1/Tactical.sml | 25 ++++- src/proofman/Manager.sig | 2 + src/proofman/Manager.sml | 10 ++ src/proofman/goalStack.sig | 2 + src/proofman/goalStack.sml | 55 +++++++---- src/proofman/proofManagerLib.sig | 6 ++ src/proofman/proofManagerLib.sml | 16 ++++ 23 files changed, 517 insertions(+), 25 deletions(-) create mode 100644 help/Docfiles/Tactical.FAIL_LT.doc create mode 100644 help/Docfiles/Tactical.NO_LT.doc create mode 100644 help/Docfiles/Tactical.ORELSE_LT.doc create mode 100644 help/Docfiles/Tactical.REPEAT_LT.doc create mode 100644 help/Docfiles/Tactical.TRYALL.doc create mode 100644 help/Docfiles/Tactical.TRY_LT.doc create mode 100644 help/Docfiles/Tactical.VALID_LT.doc create mode 100644 help/Docfiles/proofManagerLib.eall.doc create mode 100644 help/Docfiles/proofManagerLib.elt.doc create mode 100644 help/Docfiles/proofManagerLib.enth.doc create mode 100644 help/Docfiles/proofManagerLib.eta.doc create mode 100644 help/Docfiles/proofManagerLib.expand_list.doc create mode 100644 help/Docfiles/proofManagerLib.expand_listf.doc diff --git a/help/Docfiles/Tactical.FAIL_LT.doc b/help/Docfiles/Tactical.FAIL_LT.doc new file mode 100644 index 0000000000..2228736fae --- /dev/null +++ b/help/Docfiles/Tactical.FAIL_LT.doc @@ -0,0 +1,21 @@ +\DOC FAIL_LT + +\TYPE {FAIL_LT : string -> list_tactic} + +\SYNOPSIS +List-tactic which always fails, with the supplied string. + +\KEYWORDS +tactic. + +\DESCRIBE +Whatever goal list it is applied to, {FAIL_LT s} always fails +with the string {s}. + +\FAILURE +The application of {FAIL_LT} to a string never fails; the resulting +list-tactic always fails. + +\SEEALSO +Tactical.FAIL_TAC, Tactical.ALL_LT, Tactical.NO_LT. +\ENDDOC diff --git a/help/Docfiles/Tactical.NO_LT.doc b/help/Docfiles/Tactical.NO_LT.doc new file mode 100644 index 0000000000..ad9c42b972 --- /dev/null +++ b/help/Docfiles/Tactical.NO_LT.doc @@ -0,0 +1,20 @@ +\DOC NO_LT + +\TYPE {NO_LT : list_tactic} + +\SYNOPSIS +List-tactic which always fails. + +\KEYWORDS +list-tactic. + +\DESCRIBE +Whatever goal list it is applied to, {NO_LT} always fails +with string {`NO_LT`}. + +\FAILURE +Always fails. + +\SEEALSO +Tactical.NO_TAC, Tactical.ALL_LT, Tactical.FAIL_LT +\ENDDOC diff --git a/help/Docfiles/Tactical.NULL_OK_LT.doc b/help/Docfiles/Tactical.NULL_OK_LT.doc index 92893e6b43..4f472d5363 100644 --- a/help/Docfiles/Tactical.NULL_OK_LT.doc +++ b/help/Docfiles/Tactical.NULL_OK_LT.doc @@ -16,7 +16,7 @@ effect. \FAILURE The application of {NULL_OK_LT} to a list-tactic {ltac} never fails. -The resulting list-tactic fails if applies to a non-empty goal list on which +The resulting list-tactic fails if applied to a non-empty goal list on which {ltac} fails. \SEEALSO diff --git a/help/Docfiles/Tactical.ORELSE_LT.doc b/help/Docfiles/Tactical.ORELSE_LT.doc new file mode 100644 index 0000000000..28dbe8f2db --- /dev/null +++ b/help/Docfiles/Tactical.ORELSE_LT.doc @@ -0,0 +1,23 @@ +\DOC ORELSE_LT + +\TYPE {op ORELSE_LT : list_tactic * list_tactic -> list_tactic} + +\SYNOPSIS +Applies first list-tactic, and if it fails, applies the second instead. + +\KEYWORDS +tactical. + +\DESCRIBE +If {ltac1} and {ltac2} are list-tactics, {ltac1 ORELSE_LT ltac2} +is a list-tactic which applies {ltac1} to a goal list, and if it fails, +applies {ltac2} to the goals. + +\FAILURE +The application of {ORELSE_LT} to a pair of list-tactics never fails. +The resulting list-tactic fails if both {ltac1} and {ltac2} fail +when applied to the relevant goals. + +\SEEALSO +Tactical.ORELSE, Tactical.THEN_LT +\ENDDOC diff --git a/help/Docfiles/Tactical.REPEAT_LT.doc b/help/Docfiles/Tactical.REPEAT_LT.doc new file mode 100644 index 0000000000..5a678f7fbd --- /dev/null +++ b/help/Docfiles/Tactical.REPEAT_LT.doc @@ -0,0 +1,23 @@ +\DOC REPEAT_LT + +\TYPE {REPEAT_LT : (list_tactic -> list_tactic)} + +\SYNOPSIS +Repeatedly applies a list-tactic until it fails. + +\KEYWORDS +tactical. + +\DESCRIBE +The list-tactic {REPEAT_LT ltac} is a list-tactic which applies {ltac} +to a goal list, and while it succeeds, +continues applying it to the resulting subgoal list. + +\FAILURE +The application of {REPEAT_LT} to a list-tactic never fails, +and neither does the composite list-tactic, +even if the basic list-tactic fails immediately. + +\SEEALSO +Tactical.REPEAT, Tactical.THEN_LT. +\ENDDOC diff --git a/help/Docfiles/Tactical.TRYALL.doc b/help/Docfiles/Tactical.TRYALL.doc new file mode 100644 index 0000000000..5417836052 --- /dev/null +++ b/help/Docfiles/Tactical.TRYALL.doc @@ -0,0 +1,28 @@ +\DOC TRYALL + +\TYPE {TRYALL : tactic -> list_tactic} + +\SYNOPSIS +Tries to apply a tactic to every goal in a list + +\KEYWORDS +tactical, list-tactic. + +\DESCRIBE +If {tac} is a tactic, {TRYALL tac} is a list-tactic which, +when applied to a list of goals, +applies the tactic {tac} to each goal for which it succeeds. +When {tac} fails on a goal, {TRYALL tac} has no effect on that goal. + +\FAILURE +The application of {TRYALL} to a tactic never fails. +The resulting list-tactic never fails. + +\EXAMPLE +Where {tac1} and {tac2} are tactics, +{tac1 THEN_LT TRYALL tac2} is equivalent to {tac1 THEN TRY tac2} + +\SEEALSO +Tactical.TRY, Tactical.THEN_LT, Tactical.THEN, Tactical.TRY, Tactical.ALLGOALS +\ENDDOC + diff --git a/help/Docfiles/Tactical.TRY_LT.doc b/help/Docfiles/Tactical.TRY_LT.doc new file mode 100644 index 0000000000..5ad6518d8a --- /dev/null +++ b/help/Docfiles/Tactical.TRY_LT.doc @@ -0,0 +1,23 @@ +\DOC TRY_LT + +\TYPE {TRY_LT : (list_tactic -> list_tactic)} + +\SYNOPSIS +Makes a list-tactic have no effect rather than fail. + +\KEYWORDS +tactical, failure. + +\DESCRIBE +For any list-tactic {ltac}, the application {TRY_LT ltac} +gives a new list-tactic which has the same effect as {ltac} if that succeeds, +and otherwise has no effect. + +\FAILURE +The application of {TRY_LT} to a list-tactic never fails. The resulting +list-tactic never fails. + +\SEEALSO +Tactical.TRY + +\ENDDOC diff --git a/help/Docfiles/Tactical.VALID_LT.doc b/help/Docfiles/Tactical.VALID_LT.doc new file mode 100644 index 0000000000..fef1355eb9 --- /dev/null +++ b/help/Docfiles/Tactical.VALID_LT.doc @@ -0,0 +1,31 @@ +\DOC VALID_LT + +\TYPE {VALID_LT : tactic -> tactic} + +\SYNOPSIS +Makes a list-tactic fail if it would otherwise return an invalid proof. + +\DESCRIBE +When list-tactic {ltac} is applied to a goal list {gl} +it produces new goal list {gl'} and a justification. +When the justification is applied to a list {thl'} of theorems +which are the new goals {gl'}, proved, it should produce a list {thl} +of theorems which are the goals {gl}, proved. + +Precisely, for each goal {(asl, g)} in {gl}, the corresponding theorem in {thl} +should be {A |- g}, with {A} a subset of {asl}. +If this is not the case, then the list-tactic is invalid, +and {VALID_LT ltac gl} fails (raises an exception). +Otherwise, {VALID_LT ltac gl} behaves the same as {ltac gl}. + +\FAILURE +{VALID_LT ltac gl} fails by design if {ltac gl} produces new goals and +justification which do not prove the given goals {gl}. +Also fails if its {ltac gl} fails. + +\SEEALSO +Tactical.VALID, +proofManagerLib.expand_list. + +\ENDDOC + diff --git a/help/Docfiles/proofManagerLib.eall.doc b/help/Docfiles/proofManagerLib.eall.doc new file mode 100644 index 0000000000..59684655ad --- /dev/null +++ b/help/Docfiles/proofManagerLib.eall.doc @@ -0,0 +1,26 @@ +\DOC eall + +\TYPE {eall : tactic -> proof} + +\SYNOPSIS +Applies a tactic to all goals in the current goal list, +replacing the list with the resulting subgoals. + +\DESCRIBE +{eall tac} applies {tac} to all the goals in the current goal list, +replacing the goal list with the list of all the resulting subgoals. +It is an abbreviation for {expand_list (ALLGOALS tac)}. + +\USES +For interactively constructing suitable compound tactics: +in an interactive proof, the effect of {e (tac1 THEN tac2)} +can be obtained by {e tac1} and then {eall tac2}. + +\SEEALSO +proofManagerLib.expand_list, +proofManagerLib.elt, +Tactical.ALLGOALS, +proofManagerLib.eta, +proofManagerLib.set_goal. + +\ENDDOC diff --git a/help/Docfiles/proofManagerLib.elt.doc b/help/Docfiles/proofManagerLib.elt.doc new file mode 100644 index 0000000000..d015d54264 --- /dev/null +++ b/help/Docfiles/proofManagerLib.elt.doc @@ -0,0 +1,23 @@ +\DOC elt + +\TYPE {elt : list_tactic -> proof} + +\SYNOPSIS +Applies a list-tactic to the current goal list, +replacing it with the resulting subgoals. + +\DESCRIBE +The function {elt} is part of the subgoal package. It is an abbreviation for +{expand_list}. For a description of the subgoal package, see {set_goal}. + +\FAILURE +As for {expand_list}. + +\USES +Doing a step in an interactive goal-directed proof, +where the step may affect the list of goals produced by the previous step. + +\SEEALSO +proofManagerLib.expand_list, proofManagerLib.set_goal. + +\ENDDOC diff --git a/help/Docfiles/proofManagerLib.enth.doc b/help/Docfiles/proofManagerLib.enth.doc new file mode 100644 index 0000000000..89c00c1201 --- /dev/null +++ b/help/Docfiles/proofManagerLib.enth.doc @@ -0,0 +1,26 @@ +\DOC enth + +\TYPE {enth : tactic -> int -> proof} + +\SYNOPSIS +Applies a tactic to one goal, referenced by number, in the current goal list, +replacing that goal with the resulting subgoals. + +\DESCRIBE +{enth tac i} applies {tac} to all the i'th goal in the current goal list, +replacing that goal in the goal list with the subgoals produced by {tac}. +It is an abbreviation for {expand_list (NTH_GOAL tac i)}. + +\USES +For interactively constructing suitable compound tactics, +for example to test whether a particular subgoal can be proved easily, +before attacking the other subgoals. + +\SEEALSO +proofManagerLib.expand_list, +proofManagerLib.elt, +Tactical.NTH_GOAL, +proofManagerLib.set_goal, +proofManagerLib.r. + +\ENDDOC diff --git a/help/Docfiles/proofManagerLib.eta.doc b/help/Docfiles/proofManagerLib.eta.doc new file mode 100644 index 0000000000..b64a4424b7 --- /dev/null +++ b/help/Docfiles/proofManagerLib.eta.doc @@ -0,0 +1,28 @@ +\DOC eta + +\TYPE {eta : tactic -> proof} + +\SYNOPSIS +Applies a tactic to all goals, on which it succeeds, in the current goal list, +replacing the list with the resulting subgoals. + +\DESCRIBE +{eta tac} tries to apply {tac} to all the goals in the current goal list; +replacing the goal list with the list of all the resulting subgoals. +If it fails on a goal, it has no effect on that goal. +It is an abbreviation for {expand_list (TRYALL tac)}. + +\USES +For interactively constructing suitable compound tactics: +in an interactive proof, the effect of {e (tac1 THEN TRY tac2)} +can be obtained by {e tac1} and then {eta tac2}. + +\SEEALSO +proofManagerLib.expand_list, +proofManagerLib.elt, +Tactical.TRYALL, +Tactical.TRY, +proofManagerLib.eall, +proofManagerLib.set_goal. + +\ENDDOC diff --git a/help/Docfiles/proofManagerLib.expand_list.doc b/help/Docfiles/proofManagerLib.expand_list.doc new file mode 100644 index 0000000000..94b71fa0d5 --- /dev/null +++ b/help/Docfiles/proofManagerLib.expand_list.doc @@ -0,0 +1,95 @@ +\DOC expand_list + +\TYPE {expand_list : list_tactic -> proof} + +\SYNOPSIS +Applies a list-tactic to replace the current goal list. + +\DESCRIBE +The function {expand_list} is part of the subgoal package. +It may be abbreviated by the function {elt}. +It applies a tactic to the current goal list (that is, +the list of goals produced by the most recent use of {expand} or {expand_list}) +to give a new proof state. +The previous state is stored on the backup list. If the list-tactic produces +subgoals, the new proof state is formed from the old one by removing the +current goal list from the goal stack and replacing it by the list of subgoals +produced by the list-tactic. +The corresponding justification is modified accordingly, +appropriate to the new goal list. +The new subgoals are printed. If more than one subgoal is produced, they are +printed from the bottom of the stack so that the new current goal is printed +last. + +If a list-tactic solves the current goal list (returns an empty subgoal list), +then its justification is used to prove a corresponding theorem. This theorem +is incorporated into the justification of the parent goal and printed. +That level of goals is removed and the parent +goal is proved using its (new) justification. This process is repeated until a +level with unproven subgoals is reached. The next goal on the goal stack then +becomes the current goal. This goal is printed. If all the subgoals are proved, +the resulting proof state consists of the theorem proved by the justifications. + +The list-tactic applied is a validating version of the list-tactic given. +It ensures that +the justification of the list-tactic does provide a proof of the goals from the +subgoals generated by the tactic. It will cause failure if this is not so. The +tactical {VALID_LT} performs this validation. + +For a description of the subgoal package, see {set_goal}. + +\FAILURE +{expand_list ltac} fails if the tactic {ltac} fails for the current goal list. +It will diverge if the list-tactic diverges for the goal. It will fail if there are no unproven goals. +This could be because no goal has been set using {set_goal} or because +the last goal set has been completely proved. It will also fail in cases when +the list-tactic is invalid. + +\EXAMPLE +{ +> expand_list (ALLGOALS CONJ_TAC) ; +OK.. +NO_PROOFSException- NO_PROOFS raised + +> g `(HD[1;2;3] = 1) /\ (TL[1;2;3] = [2;3])`; +> val it = + Proof manager status: 1 proof. + 1. Incomplete: + Initial goal: + (HD [1; 2; 3] = 1) /\ (TL [1; 2; 3] = [2; 3]) + + : proofs + +> expand CONJ_TAC; +OK.. +2 subgoals: +> val it = + TL [1; 2; 3] = [2; 3] + + + HD [1; 2; 3] = 1 + + : proof + +> expand_list (ALLGOALS (REWRITE_TAC[listTheory.HD,listTheory.TL])) ; +OK.. +val it = + Initial goal proved. + |- (HD [1; 2; 3] = 1) /\ (TL [1; 2; 3] = [2; 3]): + proof + +} + +\USES +Doing a step in an interactive goal-directed proof, +in particular, a step which affects all the subgoals generated by the +preceding step. + +\SEEALSO +proofManagerLib.set_goal, proofManagerLib.restart, +proofManagerLib.backup,proofManagerLib.restore, proofManagerLib.save, +proofManagerLib.set_backup,proofManagerLib.expand, proofManagerLib.expandf, +proofManagerLib.expand_listf, +proofManagerLib.p,proofManagerLib.top_thm, proofManagerLib.top_goal. + +\ENDDOC diff --git a/help/Docfiles/proofManagerLib.expand_listf.doc b/help/Docfiles/proofManagerLib.expand_listf.doc new file mode 100644 index 0000000000..7be69d379e --- /dev/null +++ b/help/Docfiles/proofManagerLib.expand_listf.doc @@ -0,0 +1,47 @@ +\DOC expand_listf + +\TYPE {expand_listf : (list_tactic -> unit)} + +\SYNOPSIS +Applies a list-tactic to the current goal, stacking the resulting subgoals. + +\DESCRIBE +The function {expand_listf} is a faster version of {expand_list}. +It does not use a validated version of the list-tactic. +That is, no check is made that the justification of the list-tactic +does prove the goals from the subgoals it generates. +If an invalid list-tactic is used, +the theorem ultimately proved may not match the goal originally set. +Alternatively, failure may occur when the justifications +are applied in which case the theorem would not be proved. For a description of +the subgoal package, see under {set_goal}. + +\FAILURE +Calling {expand_listf ltac} fails if the list-tactic {ltac} fails +for the current goal list. It will diverge if the list-tactic diverges +for the goals. It will fail if there are no +unproven goals. This could be because no goal has been set using {set_goal} or +because the last goal set has been completely proved. If an invalid tactic, +whose justification actually fails, has been used earlier in the proof, +{expand_listf ltac} may succeed in applying {ltac} and apparently prove +the current goals. It may then fail as it applies the justifications +of the tactics applied earlier. + +\USES +Saving CPU time when doing goal-directed proofs, since the extra validation is +not done. Redoing proofs quickly that are already known to work. + +\COMMENTS +The CPU time saved may cause misery later. +If an invalid tactic or list-tactic is used, this +will only be discovered when the proof has apparently been finished and the +justifications are applied. + +\SEEALSO +proofManagerLib.set_goal, proofManagerLib.restart, +proofManagerLib.backup,proofManagerLib.restore, proofManagerLib.save, +proofManagerLib.set_backup,proofManagerLib.expand, proofManagerLib.expandf, +proofManagerLib.expand_list, +proofManagerLib.p,proofManagerLib.top_thm, proofManagerLib.top_goal. + +\ENDDOC diff --git a/src/0/Overlay.sml b/src/0/Overlay.sml index d8c453f615..b53ff4954a 100644 --- a/src/0/Overlay.sml +++ b/src/0/Overlay.sml @@ -22,7 +22,8 @@ open CoreKernel; between the two. ---------------------------------------------------------------------- *) -infix ++ && |-> THEN THEN1 THENL THEN_LT THENC ORELSE ORELSEC THEN_TCL ORELSE_TCL ?> |> +infix ++ && |-> THEN THEN1 THENL THEN_LT THENC ORELSE ORELSE_LT ORELSEC + THEN_TCL ORELSE_TCL ?> |> (* infixes for THEN shorthands *) infix >> >- >| \\ diff --git a/src/1/Tactical.sig b/src/1/Tactical.sig index 088bbb9597..8abd823372 100644 --- a/src/1/Tactical.sig +++ b/src/1/Tactical.sig @@ -8,6 +8,7 @@ sig val THEN : tactic * tactic -> tactic val THENL : tactic * tactic list -> tactic val ORELSE : tactic * tactic -> tactic + val ORELSE_LT : list_tactic * list_tactic -> list_tactic val THEN1 : tactic * tactic -> tactic val THEN_LT : ('a -> goal list * (thm list -> 'b)) * list_tactic -> 'a -> goal list * (thm list -> 'b) @@ -18,6 +19,7 @@ sig val TACS_TO_LT : tactic list -> list_tactic val NULL_OK_LT : list_tactic -> list_tactic val ALLGOALS : tactic -> list_tactic + val TRYALL : tactic -> list_tactic val NTH_GOAL : tactic -> int -> list_tactic val LASTGOAL : tactic -> list_tactic val HEADGOAL : tactic -> list_tactic @@ -27,11 +29,16 @@ sig val REVERSE_LT : list_tactic val FAIL_TAC : string -> tactic val NO_TAC : tactic + val FAIL_LT : string -> list_tactic + val NO_LT : list_tactic val ALL_TAC : tactic val ALL_LT : list_tactic val TRY : tactic -> tactic + val TRY_LT : list_tactic -> list_tactic val REPEAT : tactic -> tactic + val REPEAT_LT : list_tactic -> list_tactic val VALID : tactic -> tactic + val VALID_LT : list_tactic -> list_tactic val EVERY : tactic list -> tactic val FIRST : tactic list -> tactic val MAP_EVERY : ('a -> tactic) -> 'a list -> tactic diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index 0b73f26e1e..0217fd5358 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -75,7 +75,7 @@ fun store_thm (name, tm, tac) = (print ("Failed to prove theorem " ^ name ^ ".\n"); Raise e) -infix THEN THENL THEN1 ORELSE THEN_LT +infix THEN THENL THEN1 ORELSE ORELSE_LT THEN_LT (*--------------------------------------------------------------------------- * tac1 THEN_LT ltac2: @@ -186,6 +186,7 @@ fun NULL_OK_LT ltac [] = ([], Lib.I) fun tac1 THENL tacs2 = tac1 THEN_LT NULL_OK_LT (TACS_TO_LT tacs2) ; fun (tac1 ORELSE tac2) g = tac1 g handle HOL_ERR _ => tac2 g +fun (ltac1 ORELSE_LT ltac2) gl = ltac1 gl handle HOL_ERR _ => ltac2 gl (*--------------------------------------------------------------------------- * tac1 THEN1 tac2: A tactical like THEN that applies tac2 only to the @@ -290,12 +291,14 @@ fun REVERSE tac = tac THEN_LT REVERSE_LT ; *---------------------------------------------------------------------------*) fun FAIL_TAC tok (g: goal) = raise ERR "FAIL_TAC" tok +fun FAIL_LT tok (gl: goal list) = raise ERR "FAIL_LT" tok (*--------------------------------------------------------------------------- * Tactic that succeeds on no goals; identity for ORELSE. *---------------------------------------------------------------------------*) fun NO_TAC g = FAIL_TAC "NO_TAC" g +fun NO_LT gl = FAIL_LT "NO_LT" gl (* for testing, redefine THEN1 fun tac1 THEN1 tac2 = tac1 THEN_LT NTH_GOAL (tac2 THEN NO_TAC) 1 ; @@ -311,6 +314,8 @@ val ALL_TAC: tactic = fn (g: goal) => ([g], hd) val ALL_LT: list_tactic = fn (gl: goal list) => (gl, Lib.I) fun TRY tac = tac ORELSE ALL_TAC +fun TRY_LT ltac = ltac ORELSE_LT ALL_LT +fun TRYALL tac = ALLGOALS (TRY tac) ; (*--------------------------------------------------------------------------- * The abstraction around g is essential to avoid looping, due to applicative @@ -318,14 +323,20 @@ fun TRY tac = tac ORELSE ALL_TAC *---------------------------------------------------------------------------*) fun REPEAT tac g = ((tac THEN REPEAT tac) ORELSE ALL_TAC) g +fun REPEAT_LT ltac gl = ((ltac THEN_LT REPEAT_LT ltac) ORELSE_LT ALL_LT) gl (*--------------------------------------------------------------------------- - * Tactical to make any tactic valid. + * Tacticals to make any tactic or list_tactic valid. * * VALID tac * * is the same as "tac", except it will fail in the cases where "tac" * returns an invalid proof. + * + * VALID_LT ltac + * + * is the same as "ltac", except it will fail in the cases where "ltac" + * returns an invalid proof. *---------------------------------------------------------------------------*) local @@ -344,6 +355,16 @@ in then result else raise ERR "VALID" "Invalid tactic" end + + fun VALID_LT (ltac: list_tactic) : list_tactic = + fn gl: goal list => + let + val (result as (glist, prf)) = ltac gl + in + if Lib.all2 achieves (prf (map masquerade glist)) gl + then result + else raise ERR "VALID_LT" "Invalid list-tactic" + end end (*--------------------------------------------------------------------------- diff --git a/src/proofman/Manager.sig b/src/proofman/Manager.sig index 7344a5721f..b1fb138712 100644 --- a/src/proofman/Manager.sig +++ b/src/proofman/Manager.sig @@ -27,6 +27,8 @@ sig (* Applying a tactic to a goal *) val expand : tactic -> proof -> proof val expandf : tactic -> proof -> proof + val expand_list : list_tactic -> proof -> proof + val expand_listf : list_tactic -> proof -> proof val expandv : string * tactic -> proof -> proof (* Seeing what the state of the proof manager is *) diff --git a/src/proofman/Manager.sml b/src/proofman/Manager.sml index 793732f82e..f7269fe9a3 100644 --- a/src/proofman/Manager.sml +++ b/src/proofman/Manager.sml @@ -87,6 +87,16 @@ fun expandf tac (GOALSTACK s) = GOALSTACK (apply (goalStack.expandf tac) s) fun expand tac (GOALSTACK s) = GOALSTACK (apply (goalStack.expand tac) s) | expand tac (GOALTREE t) = GOALTREE (apply (goalTree.expand("",tac)) t); +fun expand_listf ltac (GOALSTACK s) = + GOALSTACK (apply (goalStack.expand_listf ltac) s) + | expand_listf _ _ = + raise ERR "expand_listf" "not implemented for goal trees"; + +fun expand_list ltac (GOALSTACK s) = + GOALSTACK (apply (goalStack.expand_list ltac) s) + | expand_list _ _ = + raise ERR "expand_list" "not implemented for goal trees"; + fun expandv (s,tac) (GOALTREE t) = GOALTREE (apply (goalTree.expand (s,tac)) t) | expandv _ _ = raise ERR "expandv" "not implemented for goal stacks"; diff --git a/src/proofman/goalStack.sig b/src/proofman/goalStack.sig index 28465da3d9..ac4fe37357 100644 --- a/src/proofman/goalStack.sig +++ b/src/proofman/goalStack.sig @@ -8,6 +8,8 @@ sig val expand : tactic -> gstk -> gstk val expandf : tactic -> gstk -> gstk + val expand_list : list_tactic -> gstk -> gstk + val expand_listf : list_tactic -> gstk -> gstk val print_tac : string -> tactic val extract_thm : gstk -> thm val initial_goal : gstk -> goal diff --git a/src/proofman/goalStack.sml b/src/proofman/goalStack.sml index 326d8124e8..aa703dbbec 100644 --- a/src/proofman/goalStack.sml +++ b/src/proofman/goalStack.sml @@ -111,9 +111,10 @@ fun rotate(GSTK{prop=PROVED _, ...}) _ = stack={goals=funpow n rotl goals, validation=validation o funpow n rotr} :: rst}; +local + fun imp_err s = + raise ERR "expandf or expand_listf" ("implementation error: "^s) -local - fun imp_err s = raise ERR "expandf" ("implementation error: "^s) fun return(GSTK{stack={goals=[],validation}::rst, prop as POSED g,final}) = let val th = validation [] in case rst @@ -133,6 +134,21 @@ local | otherwise => imp_err (quote "return") end | return gstk = gstk + + fun expand_msg dpth (GSTK{prop = PROVED _, ...}) = () + | expand_msg dpth (GSTK{prop, final, stack as {goals, ...}::_}) = + let val dpth' = length stack + in if dpth' > dpth + then if (dpth+1 = dpth') + then add_string_cr + (case (length goals) + of 0 => imp_err "1" + | 1 => "1 subgoal:" + | n => (int_to_string n)^" subgoals:") + else imp_err "2" + else cr_add_string_cr "Remaining subgoals:" + end + | expand_msg _ _ = imp_err "3" ; in fun expandf _ (GSTK{prop=PROVED _, ...}) = raise ERR "expandf" "goal has already been proved" @@ -142,27 +158,24 @@ fun expandf _ (GSTK{prop=PROVED _, ...}) = val dpth = length stack val gs = return(GSTK{prop=prop,final=final, stack={goals=glist, validation=vf} :: stack}) - in case gs - of GSTK{prop = PROVED _, ...} => () - | GSTK{prop, final, stack as {goals, ...}::_} => - let val dpth' = length stack - in if dpth' > dpth - then if (dpth+1 = dpth') - then add_string_cr - (case (length goals) - of 0 => imp_err "1" - | 1 => "1 subgoal:" - | n => (int_to_string n)^" subgoals:") - else imp_err "2" - else cr_add_string_cr "Remaining subgoals:" - end - | _ => imp_err "3" - ; - gs - end -end; + in expand_msg dpth gs ; gs end + +(* note - expand_listf, unlike expandf, replaces the top member of the stack *) +fun expand_listf ltac (GSTK{prop=PROVED _, ...}) = + raise ERR "expand_listf" "goal has already been proved" + | expand_listf ltac (GSTK{prop as POSED g, stack = [], final}) = + expand_listf ltac (GSTK{prop = POSED g, + stack = [{goals = [g], validation = hd}], final = final}) + | expand_listf ltac (GSTK{prop, stack as {goals,validation}::rst, final}) = + let val (new_goals, new_vf) = ltac goals + val dpth = length stack - 1 (* because we don't augment the stack *) + val new_gs = return (GSTK{prop=prop, final=final, + stack={goals=new_goals, validation=validation o new_vf} :: rst}) + in expand_msg dpth new_gs ; new_gs end ; +end ; fun expand tac gs = expandf (Tactical.VALID tac) gs; +fun expand_list ltac gs = expand_listf (Tactical.VALID_LT ltac) gs; fun extract_thm (GSTK{prop=PROVED(th,_), ...}) = th | extract_thm _ = raise ERR "extract_thm" "no theorem proved"; diff --git a/src/proofman/proofManagerLib.sig b/src/proofman/proofManagerLib.sig index 8a607afa4b..d6d26ddda9 100644 --- a/src/proofman/proofManagerLib.sig +++ b/src/proofman/proofManagerLib.sig @@ -31,9 +31,15 @@ sig (* Applying a tactic to the current goal *) val e : tactic -> proof + val elt : list_tactic -> proof + val eall : tactic -> proof + val eta : tactic -> proof + val enth : tactic -> int -> proof val et : string * tactic -> proof val expand : tactic -> proof val expandf : tactic -> proof + val expand_list : list_tactic -> proof + val expand_listf : list_tactic -> proof val expandv : string * tactic -> proof (* Seeing what the state of the proof manager is *) diff --git a/src/proofman/proofManagerLib.sml b/src/proofman/proofManagerLib.sml index 49002c5063..a5e705db8a 100644 --- a/src/proofman/proofManagerLib.sml +++ b/src/proofman/proofManagerLib.sml @@ -84,12 +84,28 @@ fun expand tac = top_proof()) handle e => Raise e; +fun expand_listf ltac = + (say "OK..\n"; + the_proofs := Manager.hd_opr (Manager.expand_listf ltac) (proofs()); + top_proof()) + handle e => Raise e; + +fun expand_list ltac = + (say "OK..\n"; + the_proofs := Manager.hd_opr (Manager.expand_list ltac) (proofs()); + top_proof()) + handle e => Raise e; + fun expandv (s,tac) = (say "OK..\n"; the_proofs := Manager.hd_opr (Manager.expandv (s,tac)) (proofs()); top_proof()) handle e => Raise e; +val elt = expand_list ; +fun eall tac = expand_list (Tactical.ALLGOALS tac) ; +fun eta tac = expand_list (Tactical.TRYALL tac) ; +fun enth tac i = expand_list (Tactical.NTH_GOAL tac i) ; val e = expand; val et = expandv; From b3a33fbc0d6d89fc3f73f11405036de6c48bda1d Mon Sep 17 00:00:00 2001 From: Anthony Fox Date: Fri, 12 Dec 2014 14:41:40 +0000 Subject: [PATCH 048/718] Add assembly code entry points for some decompiler tools. --- .../l3-machine-code/arm/decompiler/arm_core_decompLib.sig | 1 + .../l3-machine-code/arm/decompiler/arm_core_decompLib.sml | 4 ++++ examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sig | 1 + examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sml | 3 +++ 4 files changed, 9 insertions(+) diff --git a/examples/l3-machine-code/arm/decompiler/arm_core_decompLib.sig b/examples/l3-machine-code/arm/decompiler/arm_core_decompLib.sig index 8e84a6c309..1525c54467 100644 --- a/examples/l3-machine-code/arm/decompiler/arm_core_decompLib.sig +++ b/examples/l3-machine-code/arm/decompiler/arm_core_decompLib.sig @@ -2,6 +2,7 @@ signature arm_core_decompLib = sig val config_for_arm: unit -> unit val l3_triple: string -> helperLib.instruction + val l3_triple_code: string quotation -> helperLib.instruction list val arm_core_decompile: string -> string quotation -> Thm.thm * Thm.thm val arm_core_decompile_code: string -> string quotation -> Thm.thm * Thm.thm end diff --git a/examples/l3-machine-code/arm/decompiler/arm_core_decompLib.sml b/examples/l3-machine-code/arm/decompiler/arm_core_decompLib.sml index 4158ce478c..879e9c738b 100644 --- a/examples/l3-machine-code/arm/decompiler/arm_core_decompLib.sml +++ b/examples/l3-machine-code/arm/decompiler/arm_core_decompLib.sml @@ -19,6 +19,10 @@ val l3_triple = (* utilsLib.cache 10000 String.compare *) (helperLib.instruction_apply rule o spec) +val l3_triple_code = + List.map l3_triple o + (armAssemblerLib.arm_code: string quotation -> string list) + val vars = Term.mk_var ("cond", Type.bool) :: fst (boolSyntax.strip_forall (Thm.concl ARM_ASSERT_def)) diff --git a/examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sig b/examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sig index c1ad4cda37..6b12a784d9 100644 --- a/examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sig +++ b/examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sig @@ -2,6 +2,7 @@ signature m0_core_decompLib = sig val config_for_m0: unit -> unit val m0_triple: string -> helperLib.instruction + val m0_triple_code: string quotation -> helperLib.instruction list val m0_core_decompile: string -> string quotation -> Thm.thm * Thm.thm val m0_core_decompile_code: string -> string quotation -> Thm.thm * Thm.thm end diff --git a/examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sml b/examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sml index 1b816b40a3..14006d8ae4 100644 --- a/examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sml +++ b/examples/l3-machine-code/m0/decompiler/m0_core_decompLib.sml @@ -187,6 +187,9 @@ in [x] => (x, NONE) | [x1, x2] => (x1, SOME x2) | _ => raise ERR "m0_triple" "" + val m0_triple_code = + List.map m0_triple o + (m0AssemblerLib.m0_code: string quotation -> string list) end val vars = Term.mk_var ("cond", Type.bool) :: From 1456dbddb499d2366a9f4cf79fc2de4dba05441a Mon Sep 17 00:00:00 2001 From: Scott Owens Date: Fri, 12 Dec 2014 17:46:15 +0000 Subject: [PATCH 049/718] Add a verified balanced binary tree example This is based on the implementation of weight balanced binary search trees in the ghc Haskell compiler's standard library. comparisonScript.sml has a basic theory of comparisons that return either Less, Greater, or Equal. This is not compatible with the existing totoScript.sml, because I don't require cmp x y = Equal ==> x = y, but it does. osetScript.sml uses the balanced trees to implement sets. Functional correctenss of the operations is verified, along with the balancing properties. --- examples/balanced_bst/balanced_mapScript.sml | 3504 ++++++++++++++++++ examples/balanced_bst/comparisonScript.sml | 327 ++ examples/balanced_bst/osetScript.sml | 357 ++ 3 files changed, 4188 insertions(+) create mode 100644 examples/balanced_bst/balanced_mapScript.sml create mode 100644 examples/balanced_bst/comparisonScript.sml create mode 100644 examples/balanced_bst/osetScript.sml diff --git a/examples/balanced_bst/balanced_mapScript.sml b/examples/balanced_bst/balanced_mapScript.sml new file mode 100644 index 0000000000..5fc12e54d4 --- /dev/null +++ b/examples/balanced_bst/balanced_mapScript.sml @@ -0,0 +1,3504 @@ +open HolKernel boolLib bossLib BasicProvers; +open optionTheory pairTheory stringTheory; +open arithmeticTheory pred_setTheory listTheory finite_mapTheory alistTheory sortingTheory; +open comparisonTheory; +open lcsymtacs; + +val _ = new_theory "balanced_map"; + +(* ------------------------ Preliminaries ------------------------ *) + +val _ = temp_tight_equality (); +val _ = numLib.prefer_num(); + +val list_rel_lem1 = Q.prove ( +`!f l l'. + ~LIST_REL f l l' + ⇒ + ∃n. n ≤ LENGTH l ∧ n ≤ LENGTH l' ∧ LIST_REL f (TAKE n l) (TAKE n l') ∧ + ((n = LENGTH l ∧ n ≠ LENGTH l') ∨ + (n ≠ LENGTH l ∧ n = LENGTH l') ∨ + (n ≠ LENGTH l ∧ n ≠ LENGTH l' ∧ ~f (EL n l) (EL n l')))`, + rw [] >> + `FINITE { n | n ≤ LENGTH l ∧ n ≤ LENGTH l' ∧ LIST_REL f (TAKE n l) (TAKE n l') }` + by (rw [GSPEC_AND, LE_LT1] >> + match_mp_tac FINITE_INTER >> + disj1_tac >> + rw [GSYM count_def]) >> + qabbrev_tac `nset = { n | n ≤ LENGTH l ∧ n ≤ LENGTH l' ∧ LIST_REL f (TAKE n l) (TAKE n l') }` >> + Cases_on `nset = {}` >> + rw [] + >- (fs [markerTheory.Abbrev_def, EXTENSION] >> + qexists_tac `0` >> + rw [] >> + Cases_on `l` >> + Cases_on `l'` >> + fs [] >> + pop_assum (qspecl_then [`0`] mp_tac) >> + rw []) + >- (imp_res_tac MAX_SET_DEF >> + qexists_tac `MAX_SET nset` >> + qabbrev_tac `max_nset = MAX_SET nset` >> + qunabbrev_tac `nset` >> + imp_res_tac in_max_set >> + rfs [] >> + rw [] >> + fs [LESS_OR_EQ] >> + srw_tac [ARITH_ss] [] >> + fs [TAKE_LENGTH_ID] >> + CCONTR_TAC >> + fs [] >> + `LIST_REL f (TAKE (max_nset + 1) l) (TAKE (max_nset + 1) l')` + by (fs [rich_listTheory.TAKE_EL_SNOC, SNOC_APPEND, + rich_listTheory.LIST_REL_APPEND_SING]) >> + `max_nset + 1 ∈ {n | (n < LENGTH l ∨ n = LENGTH l) ∧ (n < LENGTH l' ∨ n = LENGTH l') ∧ LIST_REL f (TAKE n l) (TAKE n l')}` + by srw_tac [ARITH_ss] [] >> + imp_res_tac in_max_set >> + unabbrev_all_tac >> + decide_tac)); + +val list_rel_lem2 = Q.prove ( +`!l l'. + LIST_REL f l l' + ⇒ + ¬∃n. n ≤ LENGTH l ∧ n ≤ LENGTH l' ∧ LIST_REL f (TAKE n l) (TAKE n l') ∧ + ((n = LENGTH l ∧ n ≠ LENGTH l') ∨ + (n ≠ LENGTH l ∧ n = LENGTH l') ∨ + (n ≠ LENGTH l ∧ n ≠ LENGTH l' ∧ ~f (EL n l) (EL n l')))`, + ho_match_mp_tac LIST_REL_ind >> + rw [] >> + CCONTR_TAC >> + fs [] >> + EVERY_CASE_TAC >> + fs [] >> + rw [] + >- (first_x_assum (qspecl_then [`LENGTH l`] mp_tac) >> + rw []) + >- (first_x_assum (qspecl_then [`LENGTH l'`] mp_tac) >> + rw []) + >- (first_x_assum (qspecl_then [`n-1`] mp_tac) >> + rw [] >> + full_simp_tac (srw_ss()++ARITH_ss) [] >> + fs [LIST_REL_EL_EQN] >> + `n - 1 ≤ LENGTH l ∧ n - 1 ≤ LENGTH l'` by decide_tac >> + `n ≤ LENGTH l ∧ n ≤ LENGTH l'` by decide_tac >> + fs [LENGTH_TAKE, rich_listTheory.EL_TAKE] >> + rw [] >> + `0 < n` by decide_tac >> + full_simp_tac (srw_ss()++ARITH_ss) [rich_listTheory.EL_CONS] >> + `PRE n = n - 1` by decide_tac >> + fs [])); + +val list_rel_thm = Q.prove ( +`!f l l'. + LIST_REL f l l' ⇔ + !n. + ¬(n ≤ LENGTH l) ∨ ¬(n ≤ LENGTH l') ∨ ¬LIST_REL f (TAKE n l) (TAKE n l') ∨ + (n ≠ LENGTH l ∨ n = LENGTH l') ∧ + (n = LENGTH l ∨ n ≠ LENGTH l') ∧ + (n = LENGTH l ∨ n = LENGTH l' ∨ f (EL n l) (EL n l'))`, + rw [] >> + eq_tac >> + rw [] >> + imp_res_tac list_rel_lem2 >> + fs [] >> + metis_tac [list_rel_lem1]); + +val list_rel_thm = Q.prove ( +`!f l l'. + LIST_REL f l l' ⇔ + !n. + n ≤ LENGTH l ∧ n ≤ LENGTH l' ∧ LIST_REL f (TAKE n l) (TAKE n l') ∧ + (n ≠ LENGTH l ∨ n ≠ LENGTH l') ⇒ + (n ≠ LENGTH l ∧ n ≠ LENGTH l' ∧ f (EL n l) (EL n l'))`, + metis_tac [list_rel_thm]); + +val _ = bossLib.augment_srw_ss [rewrites + [FUNION_FUPDATE_1,FUNION_ASSOC,FUNION_FEMPTY_2,FUNION_FEMPTY_1,FDOM_DRESTRICT, + DRESTRICT_UNIV]] + +fun fs x = full_simp_tac (srw_ss()++ARITH_ss) x; +fun rfs x = REV_FULL_SIMP_TAC (srw_ss()++ARITH_ss) x; +val rw = srw_tac [ARITH_ss]; + +val fmrw = srw_tac [ARITH_ss, rewrites [FLOOKUP_UPDATE,FLOOKUP_FUNION,FLOOKUP_DRESTRICT, + FUNION_FUPDATE_2,FAPPLY_FUPDATE_THM,FUNION_DEF, DRESTRICT_DEF]]; + +fun inv_to_front_tac tm (g as (asl,w)) = let + val tms = strip_conj w + val (tms1,tms2) = List.partition (fn x => can (find_term (can (match_term tm))) x) tms + val tms = tms1@tms2 + val thm = prove (``^w ⇔ ^(list_mk_conj tms)``, SIMP_TAC (std_ss) [AC CONJ_COMM CONJ_ASSOC]) +in + ONCE_REWRITE_TAC [thm] g +end + +val inv_mp_tac = let + val lemma = PROVE [] ``!A B C D. (A ⇒ B ∧ C) ⇒ (A ∧ (B ∧ C ⇒ D)) ⇒ (B ∧ D)`` +in + fn th => fn (g as (asl,w)) => let + val c = th |> concl + val (xs,b) = strip_forall c + val tm = b |> dest_imp |> snd |> strip_conj |> hd + val tm2 = hd (strip_conj w) + val s = fst (match_term tm tm2) + val th2 = SPECL (map (Term.subst s) xs) th + val th3 = MATCH_MP lemma th2 + in + MATCH_MP_TAC (GEN_ALL th3) g + end +end + +val fdom_eq = PROVE [] ``m1 = m2 ⇒ FDOM m1 = FDOM m2``; + +val TIMES_MIN = Q.prove ( +`!x y z. x * MIN y z = MIN (x * y) (x * z)`, + rw [MIN_DEF] >> + fs []); + +val FCARD_DISJOINT_UNION = Q.prove ( +`!m1 m2. + DISJOINT (FDOM m1) (FDOM m2) ∨ DISJOINT (FDOM m2) (FDOM m1) + ⇒ + FCARD (FUNION m1 m2) = FCARD m1 + FCARD m2`, + rw [DISJOINT_DEF, FCARD_DEF] >> + metis_tac [CARD_UNION, FDOM_FINITE, CARD_DEF, ADD_0, INTER_COMM]); + +val CARD_DISJOINT_UNION = Q.prove ( +`!s1 s2. + FINITE s1 ∧ FINITE s2 + ⇒ + DISJOINT s1 s2 ∨ DISJOINT s2 s1 + ⇒ + CARD (s1 ∪ s2) = CARD s1 + CARD s2`, + rw [DISJOINT_DEF] >> + metis_tac [CARD_UNION, CARD_DEF, ADD_0, INTER_COMM]); + +val FCARD_DRESTRICT = Q.prove ( +`∀m s. FCARD (DRESTRICT m s) = CARD (FDOM m ∩ s)`, + rw [FCARD_DEF, FDOM_DRESTRICT]); + +val DELETE_INTER2 = Q.prove ( +`∀s t x. t ∩ (s DELETE x) = s ∩ t DELETE x`, + metis_tac [DELETE_INTER, INTER_COMM]); + +val POS_CARD_HAS_MEM = Q.prove ( +`!s. FINITE s ⇒ 0 < CARD s ⇒ ?x. x ∈ s`, + Cases_on `s` >> + rw [CARD_INSERT] >> + metis_tac []); + +val all_distinct_up_to_def = Define ` +(all_distinct_up_to cmp [] ⇔ T) ∧ +(all_distinct_up_to cmp (k::t) ⇔ + (∀k'. cmp k k' = Equal ⇒ ~MEM k' t) ∧ all_distinct_up_to cmp t)`; + +val every_case_tac = BasicProvers.EVERY_CASE_TAC; + +(* ------------------------ Finite maps up to key equivalence ------------------------ *) + +val key_set_def = Define ` +key_set cmp k = { k' | cmp k k' = Equal }`; + +val key_set_equiv = Q.store_thm ("key_set_equiv", +`!cmp. + good_cmp cmp + ⇒ + (!k. k ∈ key_set cmp k) ∧ + (!k1 k2. k1 ∈ key_set cmp k2 ⇒ k2 ∈ key_set cmp k1) ∧ + (!k1 k2 k3. k1 ∈ key_set cmp k2 ∧ k2 ∈ key_set cmp k3 ⇒ k1 ∈ key_set cmp k3)`, + rw [key_set_def] >> + metis_tac [good_cmp_def]); + +val key_set_partition = Q.store_thm ("key_set_partition", +`!cmp k1 k2. + good_cmp cmp ∧ + key_set cmp k1 ≠ key_set cmp k2 + ⇒ + DISJOINT (key_set cmp k1) (key_set cmp k2)`, + rw [DISJOINT_DEF, EXTENSION] >> + metis_tac [key_set_equiv]); + +val key_set_eq = Q.store_thm ("key_set_eq", +`!cmp k1 k2. + good_cmp cmp + ⇒ + (key_set cmp k1 = key_set cmp k2 ⇔ cmp k1 k2 = Equal)`, + rw [key_set_def, EXTENSION] >> + metis_tac [cmp_thms, key_set_equiv]); + +val key_set_cmp_def = Define ` +key_set_cmp cmp k ks res ⇔ + !k'. k' ∈ ks ⇒ cmp k k' = res`; + +val key_set_cmp_thm = Q.store_thm ("key_set_cmp_thm", +`!cmp k k' res. + good_cmp cmp + ⇒ + (key_set_cmp cmp k (key_set cmp k') res ⇔ cmp k k' = res)`, + rw [key_set_cmp_def, key_set_def] >> + metis_tac [cmp_thms]); + +val key_set_cmp2_def = Define ` +key_set_cmp2 cmp ks1 ks2 res ⇔ + !k1 k2. k1 ∈ ks1 ∧ k2 ∈ ks2 ⇒ cmp k1 k2 = res`; + +val key_set_cmp2_thm = Q.store_thm ("key_set_cmp2_thm", +`!cmp k k' res. + good_cmp cmp + ⇒ + (key_set_cmp2 cmp (key_set cmp k) (key_set cmp k') res ⇔ cmp k k' = res)`, + rw [key_set_cmp2_def, key_set_def] >> + metis_tac [cmp_thms]); + +(* Maps based on balanced binary trees. Copied from ghc-7.8.3 + * libraries/containers/Data/Map/Base.hs. It starts with the following comment: + +----------------------------------------------------------------------------- +-- | +-- Module : Data.Map.Base +-- Copyright : (c) Daan Leijen 2002 +-- (c) Andriy Palamarchuk 2008 +-- License : BSD-style +-- Maintainer : libraries@haskell.org +-- Stability : provisional +-- Portability : portable +-- +-- An efficient implementation of maps from keys to values (dictionaries). +-- +-- Since many function names (but not the type name) clash with +-- "Prelude" names, this module is usually imported @qualified@, e.g. +-- +-- > import Data.Map (Map) +-- > import qualified Data.Map as Map +-- +-- The implementation of 'Map' is based on /size balanced/ binary trees (or +-- trees of /bounded balance/) as described by: +-- +-- * Stephen Adams, \"/Efficient sets: a balancing act/\", +-- Journal of Functional Programming 3(4):553-562, October 1993, +-- . +-- +-- * J. Nievergelt and E.M. Reingold, +-- \"/Binary search trees of bounded balance/\", +-- SIAM journal of computing 2(1), March 1973. +-- +-- Note that the implementation is /left-biased/ -- the elements of a +-- first argument are always preferred to the second, for example in +-- 'union' or 'insert'. +-- +-- Operation comments contain the operation time complexity in +-- the Big-O notation . +----------------------------------------------------------------------------- + +*) + +val _ = Datatype ` +balanced_map = Tip | Bin num 'k 'v balanced_map balanced_map`; + +val ratio_def = Define ` +ratio = 2`; + +val delta_def = Define ` +delta = 3:num`; + +val size_def = Define ` +(size Tip = 0) ∧ +(size (Bin s k v l r) = s)`; + +val bin_def = Define ` +bin k x l r = Bin (size l + size r + 1) k x l r`; + +val null_def = Define ` +(null Tip = T) ∧ +(null (Bin s k v m1 m2) = F)`; + +val lookup_def = Define ` +(lookup cmp k Tip = NONE) ∧ +(lookup cmp k (Bin s k' v l r) = + case cmp k k' of + | Less => lookup cmp k l + | Greater => lookup cmp k r + | Equal => SOME v)`; + +val member_def = Define ` +(member cmp k Tip = F) ∧ +(member cmp k (Bin s k' v l r) = + case cmp k k' of + | Less => member cmp k l + | Greater => member cmp k r + | Equal => T)`; + +val empty_def = Define ` +empty = Tip`; + +val singleton_def = Define ` +singleton k x = Bin 1 k x Tip Tip`; + +(* Just like the Haskell, but w/o @ patterns *) +val balanceL'_def = Define ` +balanceL' k x l r = + case r of + | Tip => + (case l of + | Tip => Bin 1 k x Tip Tip + | (Bin _ _ _ Tip Tip) => Bin 2 k x l Tip + | (Bin _ lk lx Tip (Bin _ lrk lrx _ _)) => Bin 3 lrk lrx (Bin 1 lk lx Tip Tip) (Bin 1 k x Tip Tip) + | (Bin _ lk lx (Bin s' k' v' l' r') Tip) => Bin 3 lk lx (Bin s' k' v' l' r') (Bin 1 k x Tip Tip) + | (Bin ls lk lx (Bin lls k' v' l' r') (Bin lrs lrk lrx lrl lrr)) => + if lrs < ratio*lls then Bin (1+ls) lk lx (Bin lls k' v' l' r') (Bin (1+lrs) k x (Bin lrs lrk lrx lrl lrr) Tip) + else Bin (1+ls) lrk lrx (Bin (1+lls+size lrl) lk lx (Bin lls k' v' l' r') lrl) (Bin (1+size lrr) k x lrr Tip)) + | (Bin rs _ _ _ _) => + case l of + | Tip => Bin (1+rs) k x Tip r + | (Bin ls lk lx ll lr) => + if ls > delta*rs then + case (ll, lr) of + | (Bin lls _ _ _ _, Bin lrs lrk lrx lrl lrr) => + if lrs < ratio*lls then Bin (1+ls+rs) lk lx ll (Bin (1+rs+lrs) k x lr r) + else Bin (1+ls+rs) lrk lrx (Bin (1+lls+size lrl) lk lx ll lrl) (Bin (1+rs+size lrr) k x lrr r) + | (_, _) => Tip (* error "Failure in Data.Map.balanceL" *) + else Bin (1+ls+rs) k x l r`; + +val balanceR'_def = Define ` +balanceR' k x l r = + case l of + | Tip => + (case r of + | Tip => Bin 1 k x Tip Tip + | (Bin _ _ _ Tip Tip) => Bin 2 k x Tip r + | (Bin _ rk rx Tip (Bin s' k' v' l' r')) => Bin 3 rk rx (Bin 1 k x Tip Tip) (Bin s' k' v' l' r') + | (Bin _ rk rx (Bin _ rlk rlx _ _) Tip) => Bin 3 rlk rlx (Bin 1 k x Tip Tip) (Bin 1 rk rx Tip Tip) + | (Bin rs rk rx (Bin rls rlk rlx rll rlr) (Bin rrs k' v' l' r')) => + if rls < ratio*rrs then Bin (1+rs) rk rx (Bin (1+rls) k x Tip (Bin rls rlk rlx rll rlr)) (Bin rrs k' v' l' r') + else Bin (1+rs) rlk rlx (Bin (1+size rll) k x Tip rll) (Bin (1+rrs+size rlr) rk rx rlr (Bin rrs k' v' l' r'))) + | (Bin ls _ _ _ _) => + case r of + | Tip => Bin (1+ls) k x l Tip + | (Bin rs rk rx rl rr) => + if rs > delta*ls then + case (rl, rr) of + | (Bin rls rlk rlx rll rlr, Bin rrs _ _ _ _) => + if rls < ratio*rrs then Bin (1+ls+rs) rk rx (Bin (1+ls+rls) k x l rl) rr + else Bin (1+ls+rs) rlk rlx (Bin (1+ls+size rll) k x l rll) (Bin (1+rrs+size rlr) rk rx rlr rr) + | (_, _) => Tip (* error "Failure in Data.Map.balanceR" *) + else Bin (1+ls+rs) k x l r`; + +val balanceL_def = Define ` +(balanceL k x Tip Tip = + Bin 1 k x Tip Tip) ∧ +(balanceL k x (Bin s' k' v' Tip Tip) Tip = + Bin 2 k x (Bin s' k' v' Tip Tip) Tip) ∧ +(balanceL k x (Bin _ lk lx Tip (Bin _ lrk lrx _ _)) Tip = + Bin 3 lrk lrx (Bin 1 lk lx Tip Tip) (Bin 1 k x Tip Tip)) ∧ +(balanceL k x (Bin _ lk lx (Bin s' k' v' l' r') Tip) Tip = + Bin 3 lk lx (Bin s' k' v' l' r') (Bin 1 k x Tip Tip)) ∧ +(balanceL k x (Bin ls lk lx (Bin lls k' v' l' r') (Bin lrs lrk lrx lrl lrr)) Tip = + if lrs < ratio*lls then + Bin (1+ls) lk lx (Bin lls k' v' l' r') + (Bin (1+lrs) k x (Bin lrs lrk lrx lrl lrr) Tip) + else + Bin (1+ls) lrk lrx (Bin (1+lls+size lrl) lk lx (Bin lls k' v' l' r') lrl) + (Bin (1+size lrr) k x lrr Tip)) ∧ +(balanceL k x Tip (Bin rs k' v' l' r') = + Bin (1+rs) k x Tip (Bin rs k' v' l' r')) ∧ +(balanceL k x (Bin ls lk lx ll lr) (Bin rs k' v' l' r') = + if ls > delta*rs then + case (ll, lr) of + | (Bin lls _ _ _ _, Bin lrs lrk lrx lrl lrr) => + if lrs < ratio*lls then + Bin (1+ls+rs) lk lx ll (Bin (1+rs+lrs) k x lr (Bin rs k' v' l' r')) + else + Bin (1+ls+rs) lrk lrx (Bin (1+lls+size lrl) lk lx ll lrl) + (Bin (1+rs+size lrr) k x lrr (Bin rs k' v' l' r')) + | (_, _) => Tip (* error "Failure in Data.Map.balanceL" *) + else + Bin (1+ls+rs) k x (Bin ls lk lx ll lr) (Bin rs k' v' l' r'))`; + +val balanceR_def = Define ` +(balanceR k x Tip Tip = + Bin 1 k x Tip Tip) ∧ +(balanceR k x Tip (Bin s' k' v' Tip Tip) = + Bin 2 k x Tip (Bin s' k' v' Tip Tip)) ∧ +(balanceR k x Tip (Bin _ rk rx Tip (Bin s' k' v' l' r')) = + Bin 3 rk rx (Bin 1 k x Tip Tip) (Bin s' k' v' l' r')) ∧ +(balanceR k x Tip (Bin _ rk rx (Bin _ rlk rlx _ _) Tip) = + Bin 3 rlk rlx (Bin 1 k x Tip Tip) (Bin 1 rk rx Tip Tip)) ∧ +(balanceR k x Tip (Bin rs rk rx (Bin rls rlk rlx rll rlr) (Bin rrs k' v' l' r')) = + if rls < ratio*rrs then + Bin (1+rs) rk rx (Bin (1+rls) k x Tip (Bin rls rlk rlx rll rlr)) (Bin rrs k' v' l' r') + else + Bin (1+rs) rlk rlx (Bin (1+size rll) k x Tip rll) + (Bin (1+rrs+size rlr) rk rx rlr (Bin rrs k' v' l' r'))) ∧ +(balanceR k x (Bin ls k' v' l' r') Tip = + Bin (1+ls) k x (Bin ls k' v' l' r') Tip) ∧ +(balanceR k x (Bin ls k' v' l' r') (Bin rs rk rx rl rr) = + if rs > delta*ls then + case (rl, rr) of + | (Bin rls rlk rlx rll rlr, Bin rrs _ _ _ _) => + if rls < ratio*rrs then + Bin (1+ls+rs) rk rx (Bin (1+ls+rls) k x (Bin ls k' v' l' r') rl) rr + else + Bin (1+ls+rs) rlk rlx (Bin (1+ls+size rll) k x (Bin ls k' v' l' r') rll) + (Bin (1+rrs+size rlr) rk rx rlr rr) + | (_, _) => Tip (* error "Failure in Data.Map.balanceR" *) + else + Bin (1+ls+rs) k x (Bin ls k' v' l' r') (Bin rs rk rx rl rr))`; + +val insert_def = Define ` +(insert cmp k v Tip = singleton k v) ∧ +(insert cmp k v (Bin s k' v' l r) = + case cmp k k' of + | Less => balanceL k' v' (insert cmp k v l) r + | Greater => balanceR k' v' l (insert cmp k v r) + | Equal => Bin s k v l r)`; + +val insertR_def = Define ` +(insertR cmp k v Tip = singleton k v) ∧ +(insertR cmp k v (Bin s k' v' l r) = + case cmp k k' of + | Less => balanceL k' v' (insertR cmp k v l) r + | Greater => balanceR k' v' l (insertR cmp k v r) + | Equal => Bin s k' v' l r)`; + +val insertMax_def = Define ` +(insertMax k v Tip = singleton k v) ∧ +(insertMax k v (Bin s k' v' l r) = balanceR k' v' l (insertMax k v r))`; + +val insertMin_def = Define ` +(insertMin k v Tip = singleton k v) ∧ +(insertMin k v (Bin s k' v' l r) = balanceL k' v' (insertMin k v l) r)`; + +val deleteFindMax_def = Define ` +(deleteFindMax (Bin s k x l Tip) = ((k,x),l)) ∧ +(deleteFindMax (Bin s k x l r) = + let (km,r') = deleteFindMax r in + (km,balanceL k x l r')) ∧ +(deleteFindMax Tip = + (ARB,Tip))`; (*(error "Map.deleteFindMax: can not return the maximal element of an empty map", Tip)*) + +val deleteFindMin_def = Define ` +(deleteFindMin (Bin s k x Tip r) = ((k,x),r)) ∧ +(deleteFindMin (Bin s k x l r) = + let (km,l') = deleteFindMin l in + (km,balanceR k x l' r)) ∧ +(deleteFindMin Tip = + (ARB,Tip))`; (*(error "Map.deleteFindMin: can not return the maximal element of an empty map", Tip)*) + +val glue_def = Define ` +(glue Tip r = r) ∧ +(glue l Tip = l) ∧ +(glue l r = + if size l > size r then + let ((km,m),l') = deleteFindMax l in + balanceR km m l' r + else + let ((km,m),r') = deleteFindMin r in + balanceL km m l r')`; + +val delete_def = Define ` +(delete cmp k Tip = Tip) ∧ +(delete cmp k (Bin s k' v l r) = + case cmp k k' of + | Less => balanceR k' v (delete cmp k l) r + | Greater => balanceL k' v l (delete cmp k r) + | Eq => glue l r)`; + +val trim_help_greater_def = Define ` +(trim_help_greater cmp lo (Bin s' k v' l' r) = + if cmp k lo = Less ∨ cmp k lo = Equal then + trim_help_greater cmp lo r + else + Bin s' k v' l' r) ∧ +(trim_help_greater cmp lo Tip = Tip)`; + +val trim_help_lesser_def = Define ` +(trim_help_lesser cmp hi (Bin s' k v' l r') = + if cmp k hi = Greater ∨ cmp k hi = Equal then + trim_help_lesser cmp hi l + else + Bin s' k v' l r') ∧ +(trim_help_lesser cmp lo Tip = Tip)`; + +val trim_help_middle_def = Define ` +(trim_help_middle cmp lo hi (Bin s' k v' l r) = + if cmp k lo = Less ∨ cmp k lo = Equal then + trim_help_middle cmp lo hi r + else if cmp k hi = Greater ∨ cmp k hi = Equal then + trim_help_middle cmp lo hi l + else + Bin s' k v' l r) ∧ +(trim_help_middle lo cmp hi Tip = Tip)`; + +val trim_def = Define ` +(trim cmp NONE NONE t = t) ∧ +(trim cmp (SOME lk) NONE t = trim_help_greater cmp lk t) ∧ +(trim cmp NONE (SOME hk) t = trim_help_lesser cmp hk t) ∧ +(trim cmp (SOME lk) (SOME hk) t = trim_help_middle cmp lk hk t)`; + +val link_def = Define ` +(link k v Tip r = insertMin k v r) ∧ +(link k v l Tip = insertMax k v l) ∧ +(link k v (Bin sizeL ky y ly ry) (Bin sizeR kz z lz rz) = + if delta*sizeL < sizeR then + balanceL kz z (link k v (Bin sizeL ky y ly ry) lz) rz + else if delta*sizeR < sizeL then + balanceR ky y ly (link k v ry (Bin sizeR kz z lz rz)) + else + bin k v (Bin sizeL ky y ly ry) (Bin sizeR kz z lz rz))`; + +val filterLt_help_def = Define ` +(filterLt_help cmp b Tip = Tip) ∧ +(filterLt_help cmp b' (Bin s kx x l r) = + case cmp kx b' of + | Less => link kx x l (filterLt_help cmp b' r) + | Equal => l + | Greater => filterLt_help cmp b' l)`; + +val filterLt_def = Define ` +(filterLt cmp NONE t = t) ∧ +(filterLt cmp (SOME b) t = filterLt_help cmp b t)`; + +val filterGt_help_def = Define ` +(filterGt_help cmp b Tip = Tip) ∧ +(filterGt_help cmp b' (Bin s kx x l r) = + case cmp b' kx of + | Less => link kx x (filterGt_help cmp b' l) r + | Equal => r + | Greater => filterGt_help cmp b' r)`; + +val filterGt_def = Define ` +(filterGt cmp NONE t = t) ∧ +(filterGt cmp (SOME b) t = filterGt_help cmp b t)`; + +val hedgeUnion_def = Define ` +(hedgeUnion cmp blo bhi t1 Tip = t1) ∧ +(hedgeUnion cmp blo bhi Tip (Bin _ kx x l r) = + link kx x (filterGt cmp blo l) (filterLt cmp bhi r)) ∧ +(hedgeUnion cmp blo bhi t1 (Bin _ kx x Tip Tip) = insertR cmp kx x t1) ∧ +(hedgeUnion cmp blo bhi (Bin s kx x l r) t2 = + link kx x (hedgeUnion cmp blo (SOME kx) l (trim cmp blo (SOME kx) t2)) + (hedgeUnion cmp (SOME kx) bhi r (trim cmp (SOME kx) bhi t2)))`; + +val union_def = Define ` +(union cmp Tip t2 = t2) ∧ +(union cmp t1 Tip = t1) ∧ +(union cmp t1 t2 = hedgeUnion cmp NONE NONE t1 t2)`; + +val foldrWithKey_def = Define ` +(foldrWithKey f z' Tip = z') ∧ +(foldrWithKey f z' (Bin _ kx x l r) = + foldrWithKey f (f kx x (foldrWithKey f z' r)) l)`; + +val toAscList_def = Define ` +toAscList t = foldrWithKey (\k x xs. (k,x)::xs) [] t`; + +val compare_def = Define ` +compare cmp1 cmp2 t1 t2 = list_cmp (pair_cmp cmp1 cmp2) (toAscList t1) (toAscList t2)`; + +val map_def = Define ` +(map _ Tip ⇔ Tip) ∧ +(map f (Bin sx kx x l r) ⇔ Bin sx kx (f x) (map f l) (map f r))`; + +val splitLookup_def = Define ` +(splitLookup cmp k Tip = (Tip,NONE,Tip)) ∧ +(splitLookup cmp k (Bin _ kx x l r) = + case cmp k kx of + | Less => + let (lt,z,gt) = splitLookup cmp k l in + let gt' = link kx x gt r in + (lt,z,gt') + | Greater => + let (lt,z,gt) = splitLookup cmp k r in + let lt' = link kx x l lt in + (lt',z,gt) + | Equal => + (l,SOME x,r))`; + +val submap'_def = Define ` +(submap' cmp _ Tip _ = T) ∧ +(submap' cmp _ _ Tip = F) ∧ +(submap' cmp f (Bin _ kx x l r) t = + case splitLookup cmp kx t of + | (lt,NONE,gt) => F + | (lt,SOME y,gt) => f x y ∧ submap' cmp f l lt ∧ submap' cmp f r gt)`; + +val isSubmapOfBy_def = Define ` +isSubmapOfBy cmp f t1 t2 ⇔ size t1 ≤ size t2 ∧ submap' cmp f t1 t2`; + +val isSubmapOf_def = Define ` +isSubmapOf cmp t1 t2 ⇔ isSubmapOfBy cmp (=) t1 t2`; + +(* TODO: The ghc implementation is more complex and efficient *) +val fromList_def = Define ` +fromList cmp l = FOLDR (λ(k,v) t. insert cmp k v t) empty l`; + +(* ----------------------- proofs ------------------------ *) + +val balanceL_ind = fetch "-" "balanceL_ind"; +val balanceR_ind = fetch "-" "balanceR_ind"; + +val balanceL'_thm = Q.prove ( +`!k v l r. balanceL k v l r = balanceL' k v l r`, + ho_match_mp_tac balanceL_ind >> + rw [balanceL_def, balanceL'_def]); + +val balanceR'_thm = Q.prove ( +`!k v l r. balanceR k v l r = balanceR' k v l r`, + ho_match_mp_tac balanceR_ind >> + rw [balanceR_def, balanceR'_def]); + +val to_fmap_def = Define ` +(to_fmap cmp Tip = FEMPTY) ∧ +(to_fmap cmp (Bin s k v l r) = + (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v))`; + +val to_fmap_key_set = Q.store_thm ("to_fmap_key_set", +`!cmp ks t. + ks ∈ FDOM (to_fmap cmp t) ⇒ ?k. ks = key_set cmp k`, + Induct_on `t` >> + rw [to_fmap_def] >> + metis_tac []); + +val balanced_def = Define ` +balanced l r ⇔ + l + r ≤ 1 ∨ MAX l r ≤ delta * MIN l r`; + +val structure_size_def = Define ` +(structure_size Tip = 0) ∧ +(structure_size (Bin n k v l r) = 1 + structure_size l + structure_size r)`; + +val key_ordered_def = Define ` +(key_ordered cmp k Tip res ⇔ T) ∧ +(key_ordered cmp k (Bin n k' v l r) res ⇔ + cmp k k' = res ∧ + key_ordered cmp k l res ∧ + key_ordered cmp k r res)`; + +val key_ordered_to_fmap = Q.prove ( +`!cmp k t res. + good_cmp cmp ⇒ + (key_ordered cmp k t res + ⇔ + (!ks. ks ∈ FDOM (to_fmap cmp t) ⇒ key_set_cmp cmp k ks res))`, + Induct_on `t` >> + rw [key_ordered_def, to_fmap_def] >> + eq_tac >> + rw [] >> + metis_tac [key_set_cmp_thm]); + +val invariant_def = Define ` +(invariant cmp Tip ⇔ T) ∧ +(invariant cmp (Bin s k v l r) ⇔ + s = 1 + structure_size l + structure_size r ∧ + key_ordered cmp k l Greater ∧ + key_ordered cmp k r Less ∧ + balanced (size l) (size r) ∧ + invariant cmp l ∧ + invariant cmp r)`; + +val invariant_eq = Q.store_thm ("invariant_eq", +`(invariant cmp Tip ⇔ T) ∧ + (invariant cmp (Bin s k v l r) ⇔ + (good_cmp cmp ⇒ DISJOINT (FDOM (to_fmap cmp l)) (FDOM (to_fmap cmp r))) ∧ + (good_cmp cmp ⇒ key_set cmp k ∉ FDOM (to_fmap cmp l)) ∧ + (good_cmp cmp ⇒ key_set cmp k ∉ FDOM (to_fmap cmp r)) ∧ + s = 1 + structure_size l + structure_size r ∧ + key_ordered cmp k l Greater ∧ + key_ordered cmp k r Less ∧ + balanced (size l) (size r) ∧ + invariant cmp l ∧ + invariant cmp r)`, + rw [invariant_def] >> + eq_tac >> + rw [DISJOINT_DEF, EXTENSION] >> + CCONTR_TAC >> + fs [] >> + imp_res_tac key_ordered_to_fmap >> + fs [] >> + imp_res_tac to_fmap_key_set >> + rw [] >> + rfs [key_set_cmp_thm] >> + metis_tac [cmp_thms]); + +val inv_props = Q.prove ( +`!cmp s k v l r. + good_cmp cmp ∧ + invariant cmp (Bin s k v l r) + ⇒ + DISJOINT (FDOM (to_fmap cmp l)) (FDOM (to_fmap cmp r)) ∧ + (!x. key_set cmp x ∈ FDOM (to_fmap cmp l) ⇒ cmp k x = Greater) ∧ + (!x. key_set cmp x ∈ FDOM (to_fmap cmp r) ⇒ cmp k x = Less)`, + rw [invariant_eq] >> + imp_res_tac key_ordered_to_fmap >> + rfs [key_set_cmp_thm]); + +val structure_size_thm = Q.prove ( +`!cmp t. invariant cmp t ⇒ size t = structure_size t`, + Cases_on `t` >> + rw [size_def, invariant_def, structure_size_def]); + +val structure_size_to_fmap = Q.prove ( +`!cmp t. good_cmp cmp ∧ invariant cmp t ⇒ FCARD (to_fmap cmp t) = structure_size t`, + Induct_on `t` >> + rw [invariant_eq, structure_size_def, to_fmap_def, FCARD_FEMPTY] >> + rw [FCARD_FUPDATE, FCARD_DISJOINT_UNION]); + +val size_thm = Q.store_thm ("size_thm", +`!cmp t. good_cmp cmp ∧ invariant cmp t ⇒ size t = FCARD (to_fmap cmp t)`, + metis_tac [structure_size_thm, structure_size_to_fmap]); + +val null_thm = Q.store_thm ("null_thm", +`!cmp t. null t ⇔ (to_fmap cmp t = FEMPTY)`, + Cases_on `t` >> + rw [null_def, to_fmap_def]); + +val lookup_thm = Q.store_thm ("lookup_thm", +`!cmp k t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + lookup cmp k t = FLOOKUP (to_fmap cmp t) (key_set cmp k)`, + Induct_on `t` >> + rw [lookup_def, to_fmap_def] >> + imp_res_tac inv_props >> + every_case_tac >> + fs [invariant_eq, FLOOKUP_UPDATE, FLOOKUP_FUNION] >> + every_case_tac >> + fs [] >> + rw [] >> + rfs [key_set_eq] >> + fs [FLOOKUP_DEF] >> + metis_tac [cmp_thms]); + +val member_thm = Q.store_thm ("member_thm", +`!cmp k t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + (member cmp k t ⇔ key_set cmp k ∈ FDOM (to_fmap cmp t))`, + Induct_on `t` >> + rw [member_def, to_fmap_def] >> + imp_res_tac inv_props >> + every_case_tac >> + fs [invariant_def, FLOOKUP_UPDATE, FLOOKUP_FUNION] >> + every_case_tac >> + fs [] >> + rw [] >> + rfs [key_set_eq] >> + fs [FLOOKUP_DEF] >> + metis_tac [cmp_thms]); + +val empty_thm = Q.store_thm ("empty_thm", +`!cmp. invariant cmp empty ∧ to_fmap cmp empty = FEMPTY`, + rw [invariant_def, empty_def, to_fmap_def, FCARD_DEF]); + +val singleton_thm = Q.store_thm ("singleton_thm", +`!cmp k v. invariant cmp (singleton k v) ∧ to_fmap cmp (singleton k v) = FEMPTY |+ (key_set cmp k,v)`, + rw [balanced_def, invariant_def, singleton_def, to_fmap_def, size_def, structure_size_def, + key_ordered_def]); + +(* The balance routine from the comments in the Haskell file *) + +val singleL_def = Define ` +singleL k1 x1 t1 (Bin _ k2 x2 t2 t3) = bin k2 x2 (bin k1 x1 t1 t2) t3`; + +val singleR_def = Define ` +singleR k1 x1 (Bin _ k2 x2 t1 t2) t3 = bin k2 x2 t1 (bin k1 x1 t2 t3)`; + +val doubleL_def = Define ` +doubleL k1 x1 t1 (Bin _ k2 x2 (Bin _ k3 x3 t2 t3) t4) = + bin k3 x3 (bin k1 x1 t1 t2) (bin k2 x2 t3 t4)`; + +val doubleR_def = Define ` +doubleR k1 x1 (Bin _ k2 x2 t1 (Bin _ k3 x3 t2 t3)) t4 = + bin k3 x3 (bin k2 x2 t1 t2) (bin k1 x1 t3 t4)`; + +val rotateL_def = Define ` +(rotateL k x l (Bin s' k' x' ly ry) = + if size ly < ratio * size ry then + singleL k x l (Bin s' k' x' ly ry) + else + doubleL k x l (Bin s' k' x' ly ry)) ∧ +(rotateL k x l Tip = + doubleL k x l Tip)`; + +val rotateR_def = Define ` +(rotateR k x (Bin s' k' x' ly ry) r = + if size ry < ratio * size ly then + singleR k x (Bin s' k' x' ly ry) r + else + doubleR k x (Bin s' k' x' ly ry) r) ∧ +(rotateR k x Tip r = + doubleR k x Tip r)`; + +val bal_def = Define ` +bal k x l r = + if size l + size r ≤ 1 then + Bin (size l + size r + 1) k x l r + else if size r > delta * size l then + rotateL k x l r + else if size l > delta * size r then + rotateR k x l r + else + Bin (size l + size r + 1) k x l r`; + +val balL_def = Define ` +balL k x l r = + if size l + size r ≤ 1 then + Bin (size l + size r + 1) k x l r + else if size l > delta * size r then + rotateR k x l r + else + Bin (size l + size r + 1) k x l r`; + +val balR_def = Define ` +balR k x l r = + if size l + size r ≤ 1 then + Bin (size l + size r + 1) k x l r + else if size r > delta * size l then + rotateL k x l r + else + Bin (size l + size r + 1) k x l r`; + +(* We want a formula that states how unbalanced two trees can be + * and still be re-balanced by the balancer. It also has to allow the + * trees to be as unbalanced as the link, insert and delete functions need. The + * formula below is the result of guesswork. *) +val almost_balancedL_def = Define ` +almost_balancedL l r = + if l + r ≤ 1 ∨ l ≤ delta * r then + balanced l r + else if r = 0 then + l < 5 + else if r = 1 then + l < 8 + else + 2 * l < (2 * delta + 3) * r + 2`; + +val almost_balancedR_def = Define ` +almost_balancedR l r = + if l + r ≤ 1 ∨ r ≤ delta * l then + balanced l r + else if l = 0 then + r < 5 + else if l = 1 then + r < 8 + else + 2 * r < (2 * delta + 3) * l + 2`; + +val balanced_lem1 = Q.prove ( +`!l r. l + r ≤ 1 ⇒ balanced l r`, + rw [balanced_def]); + +val balanced_lem2 = Q.prove ( +`!l r. + ¬(l > delta * r) ∧ + almost_balancedL l r ∧ + ¬(l + r ≤ 1) + ⇒ + balanced l r`, + rw [almost_balancedL_def, balanced_def, NOT_LESS_EQUAL, NOT_GREATER, TIMES_MIN, delta_def]); + +val balanced_lem3 = Q.prove ( +`!b b0 r. + almost_balancedL (b + b0 + 1) r ∧ + b + b0 + 1 > delta * r ∧ + b0 < ratio * b ∧ + balanced b b0 + ⇒ + balanced b (b0 + r + 1) ∧ + balanced b0 r`, + rw [almost_balancedL_def, balanced_def, TIMES_MIN, delta_def, ratio_def] >> + fs [MIN_DEF]); + +val balanced_lem4 = Q.prove ( +`!b b' b0' r. + almost_balancedL (b + b' + b0' + 2) r ∧ + b + b' + b0' + 2 > delta * r ∧ + ¬(b' + b0' + 1 < ratio * b) ∧ + balanced b (b' + b0' + 1) ∧ + balanced b' b0' + ⇒ + balanced (b + b' + 1) (b0' + r + 1) ∧ + balanced b b' ∧ + balanced b0' r`, + rw [almost_balancedL_def, balanced_def, TIMES_MIN, delta_def, ratio_def] >> + fs [MIN_DEF]); + +val balanced_lem5 = Q.prove ( +`!l r. + ¬(r > delta * l) ∧ + almost_balancedR l r + ⇒ + balanced l r`, + rw [almost_balancedR_def, balanced_def, NOT_LESS_EQUAL, NOT_GREATER, TIMES_MIN, delta_def]); + +val balanced_lem6 = Q.prove ( +`!b b0 l. + almost_balancedR l (b + b0 + 1) ∧ + b + b0 + 1 > delta * l ∧ + b < ratio * b0 ∧ + balanced b b0 + ⇒ + balanced (b + l + 1) b0 ∧ balanced l b`, + rw [almost_balancedR_def, balanced_def, TIMES_MIN, delta_def, ratio_def] >> + fs [MIN_DEF]); + +val balanced_lem7 = Q.prove ( +`!b b0 b0' l b'. + almost_balancedR l (b' + b0 + b0' + 2) ∧ + b' + b0 + b0' + 2 > delta * l ∧ + ¬(b' + b0' + 1 < ratio * b0) ∧ + balanced (b' + b0' + 1) b0 ∧ + balanced b' b0' + ⇒ + balanced (b' + l + 1) (b0 + b0' + 1) ∧ + balanced l b' ∧ + balanced b0' b0`, + rw [almost_balancedR_def, balanced_def, TIMES_MIN, delta_def, ratio_def] >> + fs [MIN_DEF]); + +val singleR_thm = Q.prove ( +`!k v r cmp n k' v' b b0. + good_cmp cmp ∧ + key_ordered cmp k (Bin n k' v' b b0) Greater ∧ + key_ordered cmp k r Less ∧ + almost_balancedL n (size r) ∧ + ¬(size r + n ≤ 1) ∧ + n > delta * size r ∧ + size b0 < ratio * size b ∧ + invariant cmp (Bin n k' v' b b0) ∧ + invariant cmp r + ⇒ + invariant cmp (singleR k v (Bin n k' v' b b0) r) ∧ + to_fmap cmp (singleR k v (Bin n k' v' b b0) r) = + (FUNION (to_fmap cmp (Bin n k' v' b b0)) (to_fmap cmp r)) |+ (key_set cmp k,v)`, + rw [singleR_def] >> + imp_res_tac inv_props + >- (fs [invariant_def, bin_def, size_def, structure_size_def, bin_def, key_ordered_def] >> + imp_res_tac structure_size_thm >> + rw [size_def] >> + rfs [size_def, key_ordered_to_fmap] >> + rw [] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms, balanced_lem3, ADD_ASSOC]) + >- (rw [to_fmap_def, bin_def, FUNION_FUPDATE_2, FUNION_FUPDATE_1] >> + fs [to_fmap_def, invariant_def, key_ordered_def] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms, FUPDATE_COMMUTES, FUNION_ASSOC])); + +val doubleR_thm = Q.prove ( +`!k v r cmp n k' v' b b0. + good_cmp cmp ∧ + key_ordered cmp k (Bin n k' v' b b0) Greater ∧ + key_ordered cmp k r Less ∧ + almost_balancedL n (size r) ∧ + ¬(size r + n ≤ 1) ∧ + n > delta * size r ∧ + ¬(size b0 < ratio * size b) ∧ + invariant cmp (Bin n k' v' b b0) ∧ + invariant cmp r + ⇒ + invariant cmp (doubleR k v (Bin n k' v' b b0) r) ∧ + to_fmap cmp (doubleR k v (Bin n k' v' b b0) r) = + (FUNION (to_fmap cmp (Bin n k' v' b b0)) (to_fmap cmp r)) |+ (key_set cmp k,v)`, + rw [] >> + `structure_size b0 ≠ 0` + by (fs [delta_def, ratio_def, invariant_def, size_def, + NOT_LESS_EQUAL, NOT_LESS, NOT_GREATER] >> + imp_res_tac structure_size_thm >> + fs []) >> + Cases_on `b0` >> + fs [structure_size_def, doubleR_def, bin_def] >> + imp_res_tac inv_props >> + fs [Once invariant_def] >> + imp_res_tac inv_props >> + fs [invariant_def, to_fmap_def] + >- (fs [size_def, bin_def, to_fmap_def] >> + imp_res_tac structure_size_thm >> + simp [structure_size_def, key_ordered_def] >> + fs [structure_size_def, to_fmap_def, key_ordered_def] >> + rfs [key_ordered_to_fmap] >> + rw [] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] >> + metis_tac [ADD_ASSOC, balanced_lem4]) + >- (rw [FUNION_FUPDATE_2, FUNION_FUPDATE_1] >> + fs [key_ordered_def] >> + rfs [key_ordered_to_fmap] + >- metis_tac [cmp_thms] + >- metis_tac [cmp_thms] >> + `key_set cmp k' ≠ key_set cmp k'' ∧ + key_set cmp k ≠ key_set cmp k' ∧ + key_set cmp k ≠ key_set cmp k''` + by metis_tac [key_set_eq, cmp_thms] >> + metis_tac [FUPDATE_COMMUTES, FUNION_ASSOC])); + +val rotateR_thm = Q.prove ( +`!k v l r cmp. + good_cmp cmp ∧ + key_ordered cmp k l Greater ∧ + key_ordered cmp k r Less ∧ + ¬(size l + size r ≤ 1) ∧ + size l > delta * size r ∧ + almost_balancedL (size l) (size r) ∧ + invariant cmp l ∧ + invariant cmp r + ⇒ + invariant cmp (rotateR k v l r) ∧ + to_fmap cmp (rotateR k v l r) = + (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, + Cases_on `l` + >- fs [size_def] >> + rw [size_def, rotateR_def] >> + metis_tac [singleR_thm, doubleR_thm, ADD_COMM, NOT_ZERO_LT_ZERO, GREATER_DEF]); + +val balanceL_balL = Q.prove ( +`!k v l r cmp. + good_cmp cmp ∧ + invariant cmp l ∧ + invariant cmp r + ⇒ + balanceL k v l r = balL k v l r`, + ho_match_mp_tac balanceL_ind >> + rw [] >> + rw [balanceL_def, balL_def, rotateR_def, doubleR_def, bin_def, singleR_def] >> + imp_res_tac structure_size_thm >> + fs [size_def, invariant_def, structure_size_def] >> + imp_res_tac structure_size_thm >> + fs [balanced_def] >> + TRY (Cases_on `l` >> fs [structure_size_def, size_def] >> NO_TAC) >> + TRY (Cases_on `r` >> fs [structure_size_def, size_def] >> NO_TAC) >> + TRY (fs [ratio_def] >> NO_TAC) >> + every_case_tac >> + fs [size_def, structure_size_def, ratio_def, delta_def] >> + imp_res_tac structure_size_thm >> + fs [invariant_def, doubleR_def, bin_def, size_def] >> + imp_res_tac structure_size_thm >> + rw []); + +val balanceL_thm = Q.prove ( +`!k v l r cmp. + good_cmp cmp ∧ + key_ordered cmp k l Greater ∧ + key_ordered cmp k r Less ∧ + almost_balancedL (size l) (size r) ∧ + invariant cmp l ∧ + invariant cmp r + ⇒ + invariant cmp (balanceL k v l r) ∧ + to_fmap cmp (balanceL k v l r) = + (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, + rw [] >> + `balanceL k v l r = balL k v l r` by metis_tac [balanceL_balL] >> + rw [] >> + rw [balL_def, invariant_def] >> + imp_res_tac structure_size_thm >> + rw [balanced_lem1, balanced_lem2, to_fmap_def] >> + metis_tac [rotateR_thm]); + +val singleL_thm = Q.prove ( +`!k v l cmp n k' v' b b0. + good_cmp cmp ∧ + key_ordered cmp k (Bin n k' v' b b0) Less ∧ + key_ordered cmp k l Greater ∧ + almost_balancedR (size l) n ∧ + ¬(size l + n ≤ 1) ∧ + n > delta * size l ∧ + size b < ratio * size b0 ∧ + invariant cmp (Bin n k' v' b b0) ∧ + invariant cmp l + ⇒ + invariant cmp (singleL k v l (Bin n k' v' b b0)) ∧ + to_fmap cmp (singleL k v l (Bin n k' v' b b0)) = + (FUNION (to_fmap cmp l) (to_fmap cmp (Bin n k' v' b b0))) |+ (key_set cmp k,v)`, + rw [singleL_def] >> + imp_res_tac inv_props + >- (fs [invariant_def, bin_def, size_def, structure_size_def, bin_def, key_ordered_def] >> + imp_res_tac structure_size_thm >> + rw [size_def] >> + rfs [size_def, key_ordered_to_fmap] >> + rw [] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms, balanced_lem6, ADD_ASSOC]) + >- (rw [to_fmap_def, bin_def, FUNION_FUPDATE_2, FUNION_FUPDATE_1] >> + fs [to_fmap_def, invariant_def, key_ordered_def] >> + rfs [key_ordered_to_fmap] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms, FUPDATE_COMMUTES, FUNION_ASSOC])); + +val doubleL_thm = Q.prove ( +`!k v l cmp n k' v' b b0. + good_cmp cmp ∧ + key_ordered cmp k (Bin n k' v' b b0) Less ∧ + key_ordered cmp k l Greater ∧ + almost_balancedR (size l) n ∧ + ¬(n + size l ≤ 1) ∧ + n > delta * size l ∧ + ¬(size b < ratio * size b0) ∧ + invariant cmp (Bin n k' v' b b0) ∧ + invariant cmp l + ⇒ + invariant cmp (doubleL k v l (Bin n k' v' b b0)) ∧ + to_fmap cmp (doubleL k v l (Bin n k' v' b b0)) = + (FUNION (to_fmap cmp l) (to_fmap cmp (Bin n k' v' b b0))) |+ (key_set cmp k,v)`, + rw [] >> + `structure_size b ≠ 0` + by (fs [delta_def, ratio_def, invariant_def, size_def, + NOT_LESS_EQUAL, NOT_LESS, NOT_GREATER] >> + imp_res_tac structure_size_thm >> + fs []) >> + Cases_on `b` >> + fs [structure_size_def, doubleL_def, bin_def] >> + imp_res_tac inv_props >> + fs [Once invariant_def] >> + imp_res_tac inv_props >> + fs [invariant_def, to_fmap_def] + >- (fs [size_def, bin_def, to_fmap_def] >> + imp_res_tac structure_size_thm >> + simp [structure_size_def, key_ordered_def] >> + fs [structure_size_def, to_fmap_def, key_ordered_def] >> + rfs [key_ordered_to_fmap] >> + rw [] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] >> + metis_tac [ADD_ASSOC, balanced_lem7]) + >- (rw [FUNION_FUPDATE_2, FUNION_FUPDATE_1] >> + fs [key_ordered_def] >> + rfs [key_ordered_to_fmap] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- metis_tac [cmp_thms] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- metis_tac [cmp_thms] + >- metis_tac [cmp_thms] + >- metis_tac [cmp_thms] + >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- (`key_set cmp k' ≠ key_set cmp k'' ∧ + key_set cmp k ≠ key_set cmp k' ∧ + key_set cmp k ≠ key_set cmp k''` + by metis_tac [key_set_eq, cmp_thms] >> + metis_tac [FUPDATE_COMMUTES, FUNION_ASSOC]))); + +val rotateL_thm = Q.prove ( +`!k v l r cmp. + good_cmp cmp ∧ + key_ordered cmp k r Less ∧ + key_ordered cmp k l Greater ∧ + ¬(size l + size r ≤ 1) ∧ + size r > delta * size l ∧ + almost_balancedR (size l) (size r) ∧ + invariant cmp l ∧ + invariant cmp r + ⇒ + invariant cmp (rotateL k v l r) ∧ + to_fmap cmp (rotateL k v l r) = + (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, + Cases_on `r` + >- fs [size_def] >> + rw [size_def, rotateL_def] >> + metis_tac [singleL_thm, doubleL_thm, ADD_COMM, NOT_ZERO_LT_ZERO, GREATER_DEF]); + +val balanceR_balR = Q.prove ( +`!k v l r cmp. + good_cmp cmp ∧ + invariant cmp l ∧ + invariant cmp r + ⇒ + balanceR k v l r = balR k v l r`, + ho_match_mp_tac balanceR_ind >> + rw [] >> + rw [balanceR_def, balR_def, rotateL_def, doubleL_def, bin_def, singleL_def] >> + imp_res_tac structure_size_thm >> + fs [size_def, invariant_def, structure_size_def] >> + imp_res_tac structure_size_thm >> + fs [balanced_def] >> + TRY (Cases_on `l` >> fs [structure_size_def, size_def] >> NO_TAC) >> + TRY (Cases_on `r` >> fs [structure_size_def, size_def] >> NO_TAC) >> + TRY (Cases_on `v4` >> fs [structure_size_def, size_def] >> NO_TAC) >> + TRY (fs [ratio_def] >> NO_TAC) >> + every_case_tac >> + fs [size_def, structure_size_def, ratio_def, delta_def] >> + imp_res_tac structure_size_thm >> + fs [invariant_def, doubleL_def, bin_def, size_def] >> + imp_res_tac structure_size_thm >> + rw []); + +val balanceR_thm = Q.prove ( +`!k v l r cmp. + good_cmp cmp ∧ + key_ordered cmp k r Less ∧ + key_ordered cmp k l Greater ∧ + almost_balancedR (size l) (size r) ∧ + invariant cmp l ∧ + invariant cmp r + ⇒ + invariant cmp (balanceR k v l r) ∧ + to_fmap cmp (balanceR k v l r) = + (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, + rw [] >> + `balanceR k v l r = balR k v l r` by metis_tac [balanceR_balR] >> + rw [balR_def, invariant_def] >> + imp_res_tac structure_size_thm >> + rw [balanced_lem1, balanced_lem5, to_fmap_def] >> + metis_tac [rotateL_thm]); + +val almost_balancedL_thm = Q.prove ( +`!l r. + balanced l r ⇒ + almost_balancedL l r ∧ almost_balancedL (l + 1) r ∧ almost_balancedL l (r - 1)`, + rw [almost_balancedL_def] >> + fs [balanced_def, NOT_LESS_EQUAL, TIMES_MIN] >> + rw [] >> + CCONTR_TAC >> + fs [] >> + fs [NOT_LESS_EQUAL] >> + fs [delta_def, MIN_DEF]); + +val almost_balancedR_thm = Q.prove ( +`!l r. + balanced l r ⇒ + almost_balancedR l r ∧ almost_balancedR l (r + 1) ∧ almost_balancedR (l - 1) r`, + rw [almost_balancedR_def] >> + fs [balanced_def, NOT_LESS_EQUAL, TIMES_MIN] >> + rw [] >> + CCONTR_TAC >> + fs [] >> + fs [NOT_LESS_EQUAL] >> + fs [delta_def, MIN_DEF] >> + fs [NOT_LESS, LESS_OR_EQ] >> + rw [] >> + decide_tac); + +val insert_thm = Q.store_thm ("insert_thm", +`∀t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + invariant cmp (insert cmp k v t) ∧ + to_fmap cmp (insert cmp k v t) = to_fmap cmp t |+ (key_set cmp k,v)`, + Induct_on `t` + >- fs [insert_def, singleton_def, to_fmap_def, invariant_eq, + structure_size_def, balanced_def, size_def, key_ordered_def] >> + simp [invariant_eq] >> + rpt gen_tac >> + strip_tac >> + fs [insert_def] >> + Cases_on `cmp k k'` >> + fs [] >> + simp [] >> + TRY (inv_mp_tac balanceL_thm) >> + TRY (inv_mp_tac balanceR_thm) >> + conj_asm1_tac >> + rw [to_fmap_def] + >- (rfs [key_ordered_to_fmap] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms]) + >- (imp_res_tac size_thm >> + rw [FCARD_FUPDATE] >> + fs [key_ordered_to_fmap] >> + metis_tac [almost_balancedL_thm]) + >- (rfs [key_ordered_to_fmap] >> + rw [] >> + `key_set cmp k ≠ key_set cmp k'` by metis_tac [key_set_eq, cmp_thms] >> + metis_tac [FUPDATE_COMMUTES]) + >- (rfs [key_ordered_to_fmap] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms]) + >- (imp_res_tac size_thm >> + rw [FCARD_FUPDATE] >> + fs [key_ordered_to_fmap] >> + metis_tac [almost_balancedR_thm]) + >- (rw [FUNION_FUPDATE_2, to_fmap_def] >> + rfs [key_ordered_to_fmap] >> + rw [] >> + metis_tac [FUPDATE_COMMUTES, cmp_thms, to_fmap_key_set, key_set_cmp_thm]) + >- (fs [invariant_def] >> + rfs [key_ordered_to_fmap] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms]) + >- metis_tac [key_set_eq, FUPDATE_EQ]); + +val insertR_thm = Q.store_thm ("insertR_thm", +`∀t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + invariant cmp (insertR cmp k v t) ∧ + to_fmap cmp (insertR cmp k v t) = + if key_set cmp k ∈ FDOM (to_fmap cmp t) then to_fmap cmp t else to_fmap cmp t |+ (key_set cmp k,v)`, + Induct_on `t` + >- fs [insertR_def, singleton_def, to_fmap_def, invariant_def, + structure_size_def, balanced_def, size_def, key_ordered_def] >> + rpt gen_tac >> + strip_tac >> + imp_res_tac inv_props >> + fs [insertR_def, invariant_def] >> + Cases_on `cmp k k'` >> + fs [] >> + simp [to_fmap_def] + >- (`almost_balancedL (size (insertR cmp k v t)) (size t')` + by (imp_res_tac size_thm >> + rw [FCARD_FUPDATE] >> + fs [key_ordered_to_fmap] >> + metis_tac [almost_balancedL_thm]) >> + `key_ordered cmp k' (insertR cmp k v t) Greater` + by (rfs [key_ordered_to_fmap] >> + rw [] >> + rw [key_set_cmp_thm] >> + metis_tac [good_cmp_def]) >> + rw [balanceL_thm] >> + imp_res_tac balanceL_thm >> + rw [FUNION_FUPDATE_1] >> + metis_tac [FUPDATE_COMMUTES, good_cmp_def, comparison_distinct]) + >- (`almost_balancedR (size t) (size (insertR cmp k v t'))` + by (imp_res_tac size_thm >> + rw [FCARD_FUPDATE] >> + fs [key_ordered_to_fmap] >> + metis_tac [almost_balancedR_thm]) >> + `key_ordered cmp k' (insertR cmp k v t') Less` + by (fs [key_ordered_to_fmap] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms]) >> + rw [balanceR_thm] >> + imp_res_tac balanceR_thm >> + rw [FUNION_FUPDATE_2] >> + rfs [key_ordered_to_fmap] >> + metis_tac [FUPDATE_COMMUTES, good_cmp_def, comparison_distinct]) + >- (fs [invariant_def] >> + rfs [key_ordered_to_fmap] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms,key_set_eq, FUPDATE_EQ])); + +val insertMax_thm = Q.store_thm ("insertMax_thm", +`∀t. + good_cmp cmp ∧ + invariant cmp t ∧ + (!k1. k1 ∈ FDOM (to_fmap cmp t) ⇒ key_set_cmp cmp k k1 Greater) + ⇒ + invariant cmp (insertMax k v t) ∧ + to_fmap cmp (insertMax k v t) = to_fmap cmp t |+ (key_set cmp k,v)`, + Induct_on `t` + >- fs [insertMax_def, singleton_def, to_fmap_def, invariant_def, + structure_size_def, balanced_def, size_def, key_ordered_def] >> + rpt gen_tac >> + strip_tac >> + fs [insertMax_def, invariant_def, to_fmap_def] >> + inv_mp_tac balanceR_thm >> + conj_asm1_tac >> + simp [] + >- (rfs [key_ordered_to_fmap] >> + imp_res_tac size_thm >> + rw [FCARD_FUPDATE] >> + fs [] >> + metis_tac [almost_balancedR_thm, good_cmp_def, key_set_cmp_thm]) >> + rw [FUNION_FUPDATE_2] >> + rfs [key_ordered_to_fmap] >> + metis_tac [FUPDATE_COMMUTES, cmp_thms, key_set_cmp_thm]); + +val insertMin_thm = Q.store_thm ("insertMin_thm", +`∀t. + good_cmp cmp ∧ + invariant cmp t ∧ + (!k1. k1 ∈ FDOM (to_fmap cmp t) ⇒ key_set_cmp cmp k k1 Less) + ⇒ + invariant cmp (insertMin k v t) ∧ + to_fmap cmp (insertMin k v t) = to_fmap cmp t |+ (key_set cmp k,v)`, + Induct_on `t` + >- fs [insertMin_def, singleton_def, to_fmap_def, invariant_def, + structure_size_def, balanced_def, size_def, key_ordered_def] >> + rpt gen_tac >> + strip_tac >> + fs [insertMin_def, invariant_def, to_fmap_def] >> + simp [] >> + `almost_balancedL (size (insertMin k v t)) (size t')` + by (imp_res_tac size_thm >> + rw [FCARD_FUPDATE] >> + fs [key_ordered_to_fmap] >> + metis_tac [almost_balancedL_thm]) >> + `key_ordered cmp k' (insertMin k v t) Greater` + by (rfs [key_ordered_to_fmap] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms, key_set_cmp_thm]) >> + rw [balanceL_thm] >> + imp_res_tac balanceL_thm >> + rw [FUNION_FUPDATE_1] >> + metis_tac [FUPDATE_COMMUTES, cmp_thms, key_set_cmp_thm]); + +val deleteFindMin_thm = Q.store_thm ("deleteFindMin", +`∀t t' k v. + good_cmp cmp ∧ + invariant cmp t ∧ + ~null t ∧ + deleteFindMin t = ((k,v),t') + ⇒ + invariant cmp t' ∧ + key_ordered cmp k t' Less ∧ + FLOOKUP (to_fmap cmp t) (key_set cmp k) = SOME v ∧ + to_fmap cmp t' = + DRESTRICT (to_fmap cmp t) (FDOM (to_fmap cmp t) DELETE key_set cmp k)`, + ho_match_mp_tac (fetch "-" "deleteFindMin_ind") >> + rpt conj_tac >> + rpt gen_tac >> + strip_tac >> + rpt gen_tac >> + TRY DISCH_TAC >> + fs [deleteFindMin_def, invariant_eq, to_fmap_def] >> + fs [null_def, to_fmap_def, FUNION_FEMPTY_1, deleteFindMin_def] >> + BasicProvers.VAR_EQ_TAC >> + fs [to_fmap_def, FLOOKUP_UPDATE, key_ordered_def, LET_THM, null_def] + >- (rw [] >> + fs [key_ordered_to_fmap] >> + rw [fmap_eq_flookup, FLOOKUP_UPDATE, FLOOKUP_DRESTRICT] >> + rw [flookup_thm] >> + fs [] >> + metis_tac [comparison_distinct, good_cmp_def]) >> + `?km l. deleteFindMin (Bin (structure_size v8 + (structure_size v9 + 1)) v6 v7 v8 v9) = (km,l)` + by metis_tac [pairTheory.pair_CASES] >> + fs [] >> + rpt BasicProvers.VAR_EQ_TAC >> + inv_mp_tac balanceR_thm >> + simp [] >> + Cases_on `key_set cmp v6 = key_set cmp k'` >> + fs [] + >- (`FDOM (to_fmap cmp l) = FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)` + by (FIRST_ASSUM (assume_tac o MATCH_MP (METIS_PROVE [] ``m1 = m2 ⇒ FDOM m1 = FDOM m2``)) >> + fs [FDOM_DRESTRICT, EXTENSION] >> + rfs [key_ordered_to_fmap] >> + metis_tac [cmp_thms]) >> + conj_asm1_tac + >- (rw [] + >- (rfs [key_ordered_to_fmap] >> + metis_tac []) + >- (fs [size_def] >> + imp_res_tac size_thm >> + rw [DELETE_INSERT, FCARD_DRESTRICT] >> + `key_set cmp k' ∉ FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)` + by (fs [key_ordered_to_fmap] >> + metis_tac [good_cmp_def, comparison_distinct]) >> + imp_res_tac DELETE_NON_ELEMENT >> + rw [CARD_DISJOINT_UNION] >> + imp_res_tac almost_balancedR_thm >> + fs [] >> + metis_tac [FCARD_DEF, structure_size_thm, size_thm])) >> + strip_tac >> + simp [] >> + rw [fmap_eq_flookup, FLOOKUP_UPDATE, FLOOKUP_DRESTRICT, FLOOKUP_FUNION] + >- (rfs [key_ordered_to_fmap, FDOM_DRESTRICT] >> + fs [key_ordered_to_fmap, FDOM_DRESTRICT] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm]) >> + every_case_tac >> + fs [flookup_thm,key_ordered_to_fmap] >> + rfs [key_ordered_to_fmap] >> + rw [] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm]) + >- (`key_set cmp k' ∈ FDOM (to_fmap cmp v8 ⊌ to_fmap cmp v9)` + by (every_case_tac >> + fs [FLOOKUP_DEF]) >> + `key_set cmp k ≠ key_set cmp k' ∧ cmp k' k = Less` + by (rfs [key_ordered_to_fmap] >> + fs [key_ordered_to_fmap] >> + metis_tac [cmp_thms, to_fmap_key_set, key_set_cmp_thm]) >> + simp [] >> + `FDOM (to_fmap cmp l) = (key_set cmp v6 INSERT FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)) DELETE key_set cmp k'` + by (FIRST_ASSUM (assume_tac o MATCH_MP (METIS_PROVE [] ``m1 = m2 ⇒ FDOM m1 = FDOM m2``)) >> + fs [FDOM_DRESTRICT, EXTENSION] >> + rfs [key_ordered_to_fmap] >> + metis_tac [cmp_thms]) >> + conj_asm1_tac + >- (rw [] + >- (rfs [key_ordered_to_fmap] >> + fs [key_ordered_to_fmap] >> + rw [key_set_cmp_thm] >> + metis_tac [key_set_cmp_thm, to_fmap_key_set]) + >- (imp_res_tac size_thm >> + rw [FCARD_FUPDATE, FDOM_DRESTRICT] >> + rw [FCARD_DRESTRICT, DELETE_INSERT] >> + `(FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)) ∩ + (key_set cmp v6 INSERT FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9) DELETE key_set cmp k') + = + FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9) DELETE key_set cmp k'` + by (rw [EXTENSION] >> + metis_tac [key_set_eq, EXTENSION]) >> + simp [CARD_UNION_EQN] >> + fs [DISJOINT_DEF] >| + [`CARD (FDOM (to_fmap cmp v8)) ≠ 0` + by (rw [CARD_EQ_0, EXTENSION] >> + metis_tac []) >> + `0 < CARD (FDOM (to_fmap cmp v8))` by decide_tac, + `CARD (FDOM (to_fmap cmp v9)) ≠ 0` + by (rw [CARD_EQ_0, EXTENSION] >> + metis_tac []) >> + `0 < CARD (FDOM (to_fmap cmp v9))` by decide_tac] >> + rw [] >> + imp_res_tac almost_balancedR_thm >> + fs [size_def] >> + metis_tac [FCARD_DEF, structure_size_thm, size_thm])) >> + strip_tac >> + simp [] >> + rw [fmap_eq_flookup, FLOOKUP_UPDATE, FLOOKUP_DRESTRICT, FLOOKUP_FUNION] + >- (rfs [key_ordered_to_fmap, FDOM_DRESTRICT] >> + fs [key_ordered_to_fmap, FDOM_DRESTRICT] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm]) >> + every_case_tac >> + fs [flookup_thm,key_ordered_to_fmap] >> + rfs [key_ordered_to_fmap] >> + rw [] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm])); + +val deleteFindMax_thm = Q.store_thm ("deleteFindMax", +`∀t t' k v. + good_cmp cmp ∧ + invariant cmp t ∧ + ~null t ∧ + deleteFindMax t = ((k,v),t') + ⇒ + invariant cmp t' ∧ + key_ordered cmp k t' Greater ∧ + FLOOKUP (to_fmap cmp t) (key_set cmp k) = SOME v ∧ + to_fmap cmp t' = + DRESTRICT (to_fmap cmp t) (FDOM (to_fmap cmp t) DELETE key_set cmp k)`, + ho_match_mp_tac (fetch "-" "deleteFindMax_ind") >> + rpt conj_tac >> + rpt gen_tac >> + strip_tac >> + rpt gen_tac >> + TRY DISCH_TAC >> + fs [deleteFindMax_def, invariant_eq, to_fmap_def] >> + fs [null_def, to_fmap_def, FUNION_FEMPTY_2, deleteFindMax_def] >> + BasicProvers.VAR_EQ_TAC >> + fs [to_fmap_def, FLOOKUP_UPDATE, key_ordered_def, LET_THM, null_def] + >- (rw [] >> + fs [key_ordered_to_fmap] >> + rw [fmap_eq_flookup, FLOOKUP_UPDATE, FLOOKUP_DRESTRICT] >> + rw [flookup_thm] >> + fs [] >> + metis_tac [comparison_distinct, good_cmp_def]) >> + `?km l. deleteFindMax (Bin (structure_size v8 + (structure_size v9 + 1)) v6 v7 v8 v9) = (km,l)` + by metis_tac [pairTheory.pair_CASES] >> + fs [] >> + rpt BasicProvers.VAR_EQ_TAC >> + inv_mp_tac balanceL_thm >> + simp [] >> + Cases_on `key_set cmp v6 = key_set cmp k'` >> + fs [] + >- (`FDOM (to_fmap cmp l') = FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)` + by (FIRST_ASSUM (assume_tac o MATCH_MP (METIS_PROVE [] ``m1 = m2 ⇒ FDOM m1 = FDOM m2``)) >> + fs [FDOM_DRESTRICT, EXTENSION] >> + rfs [key_ordered_to_fmap] >> + metis_tac [cmp_thms]) >> + conj_asm1_tac + >- (rw [] + >- (rfs [key_ordered_to_fmap] >> + metis_tac []) + >- (fs [size_def] >> + imp_res_tac size_thm >> + rw [DELETE_INSERT, FCARD_DRESTRICT] >> + `key_set cmp k' ∉ FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)` + by (fs [key_ordered_to_fmap] >> + metis_tac [good_cmp_def, comparison_distinct]) >> + imp_res_tac DELETE_NON_ELEMENT >> + rw [CARD_DISJOINT_UNION] >> + imp_res_tac almost_balancedL_thm >> + fs [] >> + metis_tac [FCARD_DEF, structure_size_thm, size_thm])) >> + strip_tac >> + simp [] >> + rw [fmap_eq_flookup, FLOOKUP_UPDATE, FLOOKUP_DRESTRICT, FLOOKUP_FUNION] + >- (rfs [key_ordered_to_fmap, FDOM_DRESTRICT] >> + fs [key_ordered_to_fmap, FDOM_DRESTRICT] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm]) >> + every_case_tac >> + fs [flookup_thm,key_ordered_to_fmap] >> + rfs [key_ordered_to_fmap] >> + rw [] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm]) + >- (`key_set cmp k' ∈ FDOM (to_fmap cmp v8 ⊌ to_fmap cmp v9)` + by (every_case_tac >> + fs [FLOOKUP_DEF]) >> + `key_set cmp k' ≠ key_set cmp k ∧ cmp k' k = Greater` + by (rfs [key_ordered_to_fmap] >> + fs [key_ordered_to_fmap] >> + metis_tac [cmp_thms, to_fmap_key_set, key_set_cmp_thm]) >> + simp [] >> + `FDOM (to_fmap cmp l') = (key_set cmp v6 INSERT FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)) DELETE key_set cmp k'` + by (FIRST_ASSUM (assume_tac o MATCH_MP (METIS_PROVE [] ``m1 = m2 ⇒ FDOM m1 = FDOM m2``)) >> + fs [FDOM_DRESTRICT, EXTENSION] >> + metis_tac [comparison_distinct, key_ordered_to_fmap, good_cmp_def]) >> + conj_asm1_tac + >- (rw [] + >- (rfs [key_ordered_to_fmap] >> + fs [key_ordered_to_fmap] >> + rw [key_set_cmp_thm] >> + metis_tac [key_set_cmp_thm, to_fmap_key_set]) + >- (imp_res_tac size_thm >> + rw [FCARD_FUPDATE, FDOM_DRESTRICT] >> + rw [FCARD_DRESTRICT, DELETE_INSERT] >> + `(FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)) ∩ + (key_set cmp v6 INSERT FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9) DELETE key_set cmp k') + = + FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9) DELETE key_set cmp k'` + by (rw [EXTENSION] >> + metis_tac [key_set_eq, EXTENSION]) >> + simp [CARD_UNION_EQN] >> + fs [DISJOINT_DEF] >| + [`CARD (FDOM (to_fmap cmp v8)) ≠ 0` + by (rw [CARD_EQ_0, EXTENSION] >> + metis_tac []) >> + `0 < CARD (FDOM (to_fmap cmp v8))` by decide_tac, + `CARD (FDOM (to_fmap cmp v9)) ≠ 0` + by (rw [CARD_EQ_0, EXTENSION] >> + metis_tac []) >> + `0 < CARD (FDOM (to_fmap cmp v9))` by decide_tac] >> + rw [] >> + imp_res_tac almost_balancedL_thm >> + fs [size_def] >> + metis_tac [FCARD_DEF, structure_size_thm, size_thm])) >> + strip_tac >> + simp [] >> + rw [fmap_eq_flookup, FLOOKUP_UPDATE, FLOOKUP_DRESTRICT, FLOOKUP_FUNION] + >- (rfs [key_ordered_to_fmap, FDOM_DRESTRICT] >> + fs [key_ordered_to_fmap, FDOM_DRESTRICT] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm]) >> + every_case_tac >> + fs [flookup_thm,key_ordered_to_fmap] >> + rfs [key_ordered_to_fmap] >> + rw [] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm])); + +val glue_thm = Q.store_thm ("glue_thm", +`!l r. + good_cmp cmp ∧ + invariant cmp l ∧ + invariant cmp r ∧ + (!ks ks'. ks ∈ FDOM (to_fmap cmp l) ∧ ks' ∈ FDOM (to_fmap cmp r) ⇒ key_set_cmp2 cmp ks ks' Less) ∧ + balanced (size l) (size r) + ⇒ + invariant cmp (glue l r) ∧ + to_fmap cmp (glue l r) = FUNION (to_fmap cmp l) (to_fmap cmp r)`, + Cases_on `l` >> + Cases_on `r` >> + simp [size_def, glue_def] >> + TRY (simp [to_fmap_def, FUNION_FEMPTY_2, FUNION_FEMPTY_1] >> NO_TAC) >> + strip_tac >> + Cases_on `n > n'` >> + simp [] + >- (`?k' v' l. deleteFindMax (Bin n k v b b0) = ((k',v'),l)` + by metis_tac [pairTheory.pair_CASES] >> + simp [] >> + inv_mp_tac balanceR_thm >> + simp [] >> + inv_to_front_tac ``invariant`` >> + inv_mp_tac deleteFindMax_thm >> + simp [Once SWAP_EXISTS_THM] >> + qexists_tac `Bin n k v b b0` >> + simp [null_def] >> + strip_tac >> + imp_res_tac fdom_eq >> + fs [FDOM_DRESTRICT, DELETE_INSERT, FLOOKUP_UPDATE] >> + fs [DELETE_INTER2] >> + rw [] + >- (rw [fmap_eq_flookup, FLOOKUP_FUNION, FLOOKUP_UPDATE, FLOOKUP_DRESTRICT] >> + every_case_tac >> + fs [invariant_eq, FLOOKUP_DEF] >> + metis_tac [good_cmp_def, comparison_distinct]) + >- (rfs [key_ordered_to_fmap] >> + fs [FLOOKUP_DEF] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms, key_set_cmp2_thm]) + >- (fs [invariant_eq] >> + `size l = size (Bin n k v b b0) - 1` + by (rw [size_def] >> + imp_res_tac size_thm >> + rw [FCARD_DEF, FDOM_FUPDATE, FDOM_DRESTRICT, to_fmap_def, + CARD_DISJOINT_UNION, DELETE_INTER2] >> + fs [to_fmap_def, FLOOKUP_DEF] >> + metis_tac [structure_size_thm, FCARD_DEF]) >> + imp_res_tac almost_balancedR_thm >> + fs [size_def] >> + rw [] >> + FULL_SIMP_TAC (srw_ss()++ARITH_ss) [])) + >- (`?k v l. deleteFindMin (Bin n' k' v' b' b0') = ((k,v),l)` + by metis_tac [pairTheory.pair_CASES] >> + simp [] >> + inv_mp_tac balanceL_thm >> + simp [] >> + inv_to_front_tac ``invariant`` >> + inv_mp_tac deleteFindMin_thm >> + simp [Once SWAP_EXISTS_THM] >> + qexists_tac `Bin n' k' v' b' b0'` >> + simp [null_def] >> + strip_tac >> + imp_res_tac fdom_eq >> + fs [FDOM_DRESTRICT, DELETE_INSERT, FLOOKUP_UPDATE] >> + fs [DELETE_INTER2] >> + rw [] + >- (rw [fmap_eq_flookup, FLOOKUP_FUNION, FLOOKUP_UPDATE, FLOOKUP_DRESTRICT] >> + every_case_tac + >- metis_tac [] >> + fs [invariant_eq, FLOOKUP_DEF] + >- metis_tac [cmp_thms, key_set_cmp2_thm]) + >- (rfs [key_ordered_to_fmap] >> + fs [FLOOKUP_DEF] >> + rw [] >> + imp_res_tac to_fmap_key_set >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms, key_set_cmp2_thm]) + >- (fs [invariant_eq] >> + `size l = size (Bin n' k' v' b' b0') - 1` + by (rw [size_def] >> + imp_res_tac size_thm >> + rw [FCARD_DEF, FDOM_FUPDATE, FDOM_DRESTRICT, to_fmap_def, + CARD_DISJOINT_UNION, DELETE_INTER2] >> + fs [to_fmap_def, FLOOKUP_DEF] >> + metis_tac [structure_size_thm, FCARD_DEF]) >> + imp_res_tac almost_balancedL_thm >> + fs [size_def] >> + rw [] >> + FULL_SIMP_TAC (srw_ss()++ARITH_ss) []))); + +val to_fmap_tac = + rw [to_fmap_def] >> + rw [fmap_eq_flookup, FLOOKUP_DRESTRICT, FLOOKUP_UPDATE, FLOOKUP_FUNION] >> + BasicProvers.EVERY_CASE_TAC >> + fs [FLOOKUP_DEF] >> + fs [to_fmap_def] >> + fs [key_ordered_to_fmap] >> + rfs [key_ordered_to_fmap] >> + metis_tac [cmp_thms, to_fmap_key_set, key_set_eq, key_set_cmp_thm]; + +val delete_thm = Q.store_thm ("delete_thm", +`!t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + invariant cmp (delete cmp k t) ∧ + to_fmap cmp (delete cmp k t) = + DRESTRICT (to_fmap cmp t) (FDOM (to_fmap cmp t) DELETE key_set cmp k)`, + Induct_on `t` + >- rw [delete_def, to_fmap_def] >> + rpt gen_tac >> + strip_tac >> + simp [delete_def] >> + fs [invariant_eq] >> + Cases_on `cmp k k'` >> + simp [] + >- (inv_mp_tac balanceR_thm >> + simp [] >> + rw [] + >- (fs [key_ordered_to_fmap] >> + rfs [key_ordered_to_fmap] >> + rw [FDOM_DRESTRICT] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm]) + >- (imp_res_tac size_thm >> + rw [FCARD_DRESTRICT, DELETE_INTER2] >> + imp_res_tac almost_balancedR_thm >> + metis_tac [FCARD_DEF]) + >- to_fmap_tac) + >- (inv_mp_tac balanceL_thm >> + simp [] >> + rw [] + >- (fs [key_ordered_to_fmap] >> + rfs [key_ordered_to_fmap] >> + rw [FDOM_DRESTRICT] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm]) + >- (imp_res_tac size_thm >> + rw [FCARD_DRESTRICT, DELETE_INTER2] >> + imp_res_tac almost_balancedL_thm >> + metis_tac [FCARD_DEF]) + >- to_fmap_tac) + >- (inv_mp_tac glue_thm >> + rw [] >> + rfs [key_ordered_to_fmap] + >- metis_tac [key_set_cmp2_thm, to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- to_fmap_tac)); + +val restrict_set_def = Define ` +restrict_set cmp lo hi = +{ k | option_cmp cmp lo (SOME k) = Less ∧ + option_cmp2 cmp (SOME k) hi = Less }`; + +val restrict_domain_def = Define ` + restrict_domain cmp lo hi m = + DRESTRICT m (IMAGE (key_set cmp) (restrict_set cmp lo hi))`; + +val restrict_domain_union = Q.prove ( +`restrict_domain cmp lo hi (FUNION m1 m2) = + FUNION (restrict_domain cmp lo hi m1) (restrict_domain cmp lo hi m2)`, + rw [restrict_domain_def, fmap_eq_flookup, FLOOKUP_DRESTRICT, FLOOKUP_FUNION] >> + rw [FLOOKUP_DRESTRICT, FLOOKUP_FUNION]); + +val restrict_domain_update = Q.prove ( +`good_cmp cmp + ⇒ + restrict_domain cmp lo hi (m1 |+ (key_set cmp k,v)) = + if k ∈ restrict_set cmp lo hi then + restrict_domain cmp lo hi m1 |+ (key_set cmp k,v) + else + restrict_domain cmp lo hi m1`, + rw [restrict_domain_def, fmap_eq_flookup, FLOOKUP_DRESTRICT, FLOOKUP_FUNION] >> + rfs [key_set_eq] >> + fs [restrict_set_def] >> + Cases_on `hi` >> + Cases_on `lo` >> + fs [option_cmp_def, option_cmp2_def] >> + metis_tac [cmp_thms]); + +val bounded_root_def = Define ` + bounded_root cmp lk hk t ⇔ + !s k v l r. t = Bin s k v l r ⇒ k ∈ restrict_set cmp lk hk`; + +val trim_thm = Q.prove ( +`!t lk hk cmp. + good_cmp cmp ∧ + invariant cmp t + ⇒ + invariant cmp (trim cmp lk hk t) ∧ + bounded_root cmp lk hk (trim cmp lk hk t) ∧ + to_fmap cmp (trim cmp lk hk t) SUBMAP to_fmap cmp t ∧ + restrict_domain cmp lk hk (to_fmap cmp (trim cmp lk hk t)) = + restrict_domain cmp lk hk (to_fmap cmp t)`, + Cases_on `lk` >> + Cases_on `hk` >> + simp [bounded_root_def, trim_def, restrict_set_def, option_cmp_def, option_cmp2_def] >> + Induct_on `t` >> + simp [trim_help_lesser_def, trim_help_greater_def, trim_help_middle_def, key_ordered_def] >> + fs [invariant_eq] >> + rpt gen_tac >> + strip_tac >> + every_case_tac >> + fs [] >> + simp [to_fmap_def] >> + fs [SUBMAP_DEF, restrict_domain_def, DRESTRICTED_FUNION, DRESTRICT_FUPDATE] >> + rw [invariant_def] >> + rw [FAPPLY_FUPDATE_THM, FUNION_DEF, fmap_eq_flookup, FLOOKUP_DRESTRICT, + FLOOKUP_FUNION, FLOOKUP_UPDATE] >> + rw [] >> + every_case_tac >> + fs [flookup_thm, key_ordered_to_fmap, restrict_set_def, option_cmp_def, option_cmp2_def] >> + rfs [key_ordered_to_fmap] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm, to_fmap_key_set]); + +val link_balanced_lem1 = Q.prove ( +`!r rz l. + balanced r rz ∧ + delta * (l + 1) < r + (rz + 1) + ⇒ + almost_balancedL (l + (r + 2)) rz`, + fs [almost_balancedL_def, balanced_def, TIMES_MIN, LESS_OR_EQ, delta_def, LEFT_ADD_DISTRIB] >> + CCONTR_TAC >> + fs [NOT_LESS, LESS_OR_EQ] >> + fs [MIN_DEF] >> + rw [] >> + every_case_tac >> + fs [NOT_LESS, LESS_OR_EQ]); + +val link_balanced_lem2 = Q.prove ( +`!r l ly. + balanced ly l ∧ + ¬(delta * (l + (ly + 1)) < r + 1) ∧ + delta * (r + 1) < l + (ly + 1) + ⇒ + almost_balancedR ly (SUC (l + r) + 1)`, + fs [ADD1, almost_balancedR_def, balanced_def, TIMES_MIN, LESS_OR_EQ, delta_def, LEFT_ADD_DISTRIB] >> + CCONTR_TAC >> + fs [NOT_LESS, LESS_OR_EQ] >> + fs [MIN_DEF] >> + rw [] >> + every_case_tac >> + fs [NOT_LESS, LESS_OR_EQ]); + +val link_balanced_lem3 = Q.prove ( +`!r l. + ¬(delta * (l + 1) < r + 1) ∧ + ¬(delta * (r + 1) < l + 1) + ⇒ + balanced (l + 1) (r + 1)`, + fs [ADD1, balanced_def, TIMES_MIN, LESS_OR_EQ, delta_def, LEFT_ADD_DISTRIB] >> + CCONTR_TAC >> + fs [NOT_LESS, LESS_OR_EQ, MIN_DEF]); + +val link_thm = Q.prove ( +`!k v l r. + good_cmp cmp ∧ + invariant cmp l ∧ + invariant cmp r ∧ + key_ordered cmp k l Greater ∧ + key_ordered cmp k r Less + ⇒ + invariant cmp (link k v l r) ∧ + to_fmap cmp (link k v l r) = + (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, + ho_match_mp_tac (fetch "-" "link_ind") >> + rpt conj_tac >> + simp [link_def] >> + rpt conj_tac >> + rpt gen_tac >> + strip_tac + >- (inv_mp_tac insertMin_thm >> + rw [] + >- metis_tac [key_ordered_to_fmap] >> + rw [to_fmap_def, FUNION_FEMPTY_1]) + >- (inv_mp_tac insertMax_thm >> + rw [] + >- metis_tac [key_ordered_to_fmap] >> + rw [to_fmap_def, FUNION_FEMPTY_2]) >> + Cases_on `sizeL * delta < sizeR` >> + simp [] >> + fs [] + >- (strip_tac >> + fs [invariant_eq, link_def, key_ordered_def] >> + inv_mp_tac balanceL_thm >> + simp [] >> + rw [] + >- (rfs [key_ordered_to_fmap, to_fmap_def] >> + rw [] >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms, key_set_cmp_thm, to_fmap_key_set]) + >- (imp_res_tac size_thm >> + rw [to_fmap_def] >> + fs [] >> + rfs [key_ordered_to_fmap] >> + simp [FCARD_FUPDATE, key_set_eq] >> + `key_set cmp k ∉ FDOM (to_fmap cmp ly) ∧ + key_set cmp k ∉ FDOM (to_fmap cmp l) ∧ + key_set cmp ky ∉ FDOM (to_fmap cmp r) ∧ + key_set cmp k ∉ FDOM (to_fmap cmp r)` + by metis_tac [cmp_thms, key_set_cmp_thm] >> + simp [FCARD_DEF] >> + `DISJOINT (FDOM (to_fmap cmp ly) ∪ FDOM (to_fmap cmp l)) (FDOM (to_fmap cmp r))` + by (rw [DISJOINT_UNION] >> + rw [DISJOINT_DEF, EXTENSION] >> + metis_tac [cmp_thms, key_set_cmp_thm, to_fmap_key_set]) >> + rw [CARD_DISJOINT_UNION] >> + imp_res_tac structure_size_to_fmap >> + fs [GSYM FCARD_DEF] >> + metis_tac [link_balanced_lem1, ADD_ASSOC]) + >- to_fmap_tac) >> + Cases_on `sizeR * delta < sizeL` >> + simp [] >> + fs [] + >- (strip_tac >> + fs [invariant_eq, link_def, key_ordered_def] >> + inv_mp_tac balanceR_thm >> + simp [] >> + rw [] + >- (rfs [key_ordered_to_fmap, to_fmap_def] >> + rw [] >> + rw [key_set_cmp_thm] >> + metis_tac [cmp_thms, key_set_cmp_thm, to_fmap_key_set]) + >- (imp_res_tac size_thm >> + rw [to_fmap_def] >> + fs [] >> + rfs [key_ordered_to_fmap] >> + simp [FUNION_FUPDATE_2, FCARD_FUPDATE, key_set_eq] >> + `key_set cmp k ∉ FDOM (to_fmap cmp rz) ∧ + key_set cmp k ∉ FDOM (to_fmap cmp l) ∧ + key_set cmp kz ∉ FDOM (to_fmap cmp l) ∧ + key_set cmp k ∉ FDOM (to_fmap cmp r)` + by metis_tac [cmp_thms, key_set_cmp_thm] >> + simp [FCARD_DEF] >> + `DISJOINT (FDOM (to_fmap cmp l) ∪ FDOM (to_fmap cmp r)) (FDOM (to_fmap cmp rz))` + by (rw [DISJOINT_UNION] >> + rw [DISJOINT_DEF, EXTENSION] >> + metis_tac [cmp_thms, key_set_cmp_thm, to_fmap_key_set]) >> + `DISJOINT (FDOM (to_fmap cmp l)) (FDOM (to_fmap cmp r))` + by (rw [DISJOINT_UNION] >> + rw [DISJOINT_DEF, EXTENSION] >> + metis_tac [cmp_thms, key_set_cmp_thm, to_fmap_key_set]) >> + rw [CARD_DISJOINT_UNION] >> + imp_res_tac structure_size_to_fmap >> + fs [GSYM FCARD_DEF] >> + metis_tac [link_balanced_lem2, ADD_ASSOC]) + >- to_fmap_tac) + >- (simp [bin_def, size_def] >> + rw [invariant_def, structure_size_def] >> + fs [invariant_eq, size_def] + >- metis_tac [link_balanced_lem3, structure_size_thm, ADD_ASSOC] >> + to_fmap_tac)); + +val filter_lt_help_thm = Q.prove ( +`!cmp bound t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + invariant cmp (filterLt_help cmp bound t) ∧ + to_fmap cmp (filterLt_help cmp bound t) = restrict_domain cmp NONE (SOME bound) (to_fmap cmp t)`, + Induct_on `t` >> + simp [to_fmap_def, filterLt_help_def, restrict_domain_union, restrict_domain_update] >> + simp [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> + rpt gen_tac >> + strip_tac >> + Cases_on `cmp k bound` >> + simp [] + >- (inv_mp_tac link_thm >> + conj_asm1_tac >> + rw [] >> + fs [invariant_eq] + >- (rfs [key_ordered_to_fmap] >> + rw [restrict_domain_def]) >> + rw [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def] >> + to_fmap_tac) + >- (first_x_assum inv_mp_tac >> + fs [invariant_eq] >> + rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> + to_fmap_tac) + >- (fs [invariant_eq] >> + rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> + to_fmap_tac)); + +val filterLt_thm = Q.prove ( +`!cmp bound t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + invariant cmp (filterLt cmp bound t) ∧ + to_fmap cmp (filterLt cmp bound t) = restrict_domain cmp NONE bound (to_fmap cmp t)`, + Cases_on `bound` >> + simp [to_fmap_def, filterLt_def, restrict_domain_union, restrict_domain_update] >> + simp [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> + rw [] >> + imp_res_tac filter_lt_help_thm + >- (rw [fmap_eq_flookup, FLOOKUP_DRESTRICT] >> + rw [] >> + fs [FLOOKUP_DEF] >> + metis_tac [to_fmap_key_set]) >> + rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def]); + +val filter_gt_help_thm = Q.prove ( +`!cmp bound t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + invariant cmp (filterGt_help cmp bound t) ∧ + to_fmap cmp (filterGt_help cmp bound t) = restrict_domain cmp (SOME bound) NONE (to_fmap cmp t)`, + Induct_on `t` >> + simp [to_fmap_def, filterGt_help_def, restrict_domain_union, restrict_domain_update] >> + simp [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> + rpt gen_tac >> + strip_tac >> + Cases_on `cmp bound k` >> + simp [] + >- (inv_mp_tac link_thm >> + conj_asm1_tac >> + rw [] >> + fs [invariant_eq] + >- (rfs [key_ordered_to_fmap] >> + rw [restrict_domain_def]) >> + rw [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def] >> + to_fmap_tac) + >- (first_x_assum inv_mp_tac >> + fs [invariant_eq] >> + rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> + to_fmap_tac) + >- (fs [invariant_eq] >> + rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> + to_fmap_tac)); + +val filterGt_thm = Q.prove ( +`!cmp bound t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + invariant cmp (filterGt cmp bound t) ∧ + to_fmap cmp (filterGt cmp bound t) = restrict_domain cmp bound NONE (to_fmap cmp t)`, + Cases_on `bound` >> + simp [to_fmap_def, filterGt_def, restrict_domain_union, restrict_domain_update] >> + simp [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> + rw [] >> + imp_res_tac filter_gt_help_thm + >- (rw [fmap_eq_flookup, FLOOKUP_DRESTRICT] >> + rw [] >> + fs [FLOOKUP_DEF] >> + metis_tac [to_fmap_key_set]) >> + rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def]); + +val restrict_domain_partition = Q.prove ( +`!cmp x l h t1 t2. + good_cmp cmp ∧ + x ∈ restrict_set cmp l h ∧ + restrict_domain cmp l (SOME x) t2 SUBMAP t1 ∧ + restrict_domain cmp (SOME x) h t1 SUBMAP t2 ∧ + key_set cmp x ∉ FDOM t1 ∧ + key_set cmp x ∉ FDOM t2 + ⇒ + FUNION (restrict_domain cmp l h t1) (restrict_domain cmp l h t2) = + FUNION (restrict_domain cmp l (SOME x) t1) (restrict_domain cmp (SOME x) h t2)`, + rw [restrict_domain_def, fmap_eq_flookup] >> + every_case_tac >> + rw [] >> + fs [restrict_set_def] >> + `h = NONE ∨ ?h'. h = SOME h'` by Cases_on `h` >> + `l = NONE ∨ ?l'. l = SOME l'` by Cases_on `l` >> + fs [option_cmp_def, option_cmp2_def, SUBMAP_DEF, EXTENSION, FDOM_DRESTRICT, FLOOKUP_DEF, + DRESTRICT_DEF, FAPPLY_FUPDATE_THM] >> + fmrw [] >> + metis_tac [cmp_thms, EXTENSION, key_set_eq]); + +val restrict_domain_union_swap = Q.prove ( +` good_cmp cmp + ⇒ + a ⊌ + restrict_domain cmp blo (SOME kx) (to_fmap cmp r2) ⊌ + restrict_domain cmp (SOME kx) bhi (to_fmap cmp t1') + = + a ⊌ + restrict_domain cmp (SOME kx) bhi (to_fmap cmp t1') ⊌ + restrict_domain cmp blo (SOME kx) (to_fmap cmp r2)`, + rw [restrict_domain_def] >> + Cases_on `blo` >> + Cases_on `bhi` >> + rw [restrict_set_def, fmap_eq_flookup] >> + fmrw [] >> + fs [option_cmp_def, option_cmp2_def] >> + every_case_tac >> + rw [] >> + metis_tac [cmp_thms, key_set_eq]); + +val restrict_domain_extend = Q.prove ( +` good_cmp cmp ∧ + invariant cmp (Bin s kx x t1 t1') ∧ + kx ∈ restrict_set cmp blo bhi + ⇒ + restrict_domain cmp blo (SOME kx) (to_fmap cmp t1) = + restrict_domain cmp blo bhi (to_fmap cmp t1) ∧ + restrict_domain cmp (SOME kx) bhi (to_fmap cmp t1') = + restrict_domain cmp blo bhi (to_fmap cmp t1')`, + rw [invariant_eq, restrict_domain_def] >> + rfs [key_ordered_to_fmap] >> + Cases_on `blo` >> + Cases_on `bhi` >> + rw [restrict_set_def, fmap_eq_flookup] >> + fmrw [] >> + fs [option_cmp_def, option_cmp2_def, restrict_set_def] >> + every_case_tac >> + rw [FLOOKUP_DEF] >> + metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm, to_fmap_key_set]); + +val restrict_domain_combine = Q.prove ( +` good_cmp cmp ∧ + key_set cmp kx ≠ k ∧ + kx ∈ restrict_set cmp blo bhi + ⇒ + FLOOKUP (restrict_domain cmp (SOME kx) bhi (to_fmap cmp r2) ⊌ + restrict_domain cmp blo (SOME kx) (to_fmap cmp r2)) k = + FLOOKUP (restrict_domain cmp blo bhi (to_fmap cmp r2)) k`, + fmrw [restrict_domain_def] >> + every_case_tac >> + rw [] >> + Cases_on `blo` >> + Cases_on `bhi` >> + fs [restrict_set_def, option_cmp2_def, option_cmp_def, FLOOKUP_DEF] >> + metis_tac [key_set_eq, cmp_thms, to_fmap_key_set, key_set_cmp_thm]); + +val bounded_all_def = Define ` +(bounded_all cmp lk hk Tip ⇔ T) ∧ +(bounded_all cmp lk hk (Bin s k v t1 t2) ⇔ + k ∈ restrict_set cmp lk hk ∧ + bounded_all cmp lk hk t1 ∧ + bounded_all cmp lk hk t2)`; + +val bounded_all_shrink1 = Q.prove ( +`!t blo bhi. + good_cmp cmp ∧ + bounded_all cmp blo bhi t ∧ + key_ordered cmp kx t Greater + ⇒ + bounded_all cmp blo (SOME kx) t`, + Induct_on `t` >> + rw [bounded_all_def, key_ordered_def] + >- (Cases_on `blo` >> + fs [restrict_set_def, option_cmp_def, option_cmp2_def] >> + metis_tac [good_cmp_def, comparison_distinct]) >> + metis_tac []); + +val bounded_all_shrink2 = Q.prove ( +`!t blo bhi. + good_cmp cmp ∧ + bounded_all cmp blo bhi t ∧ + key_ordered cmp kx t Less + ⇒ + bounded_all cmp (SOME kx) bhi t`, + Induct_on `t` >> + rw [bounded_all_def, key_ordered_def] + >- (Cases_on `bhi` >> + fs [restrict_set_def, option_cmp_def, option_cmp2_def] >> + metis_tac [good_cmp_def, comparison_distinct]) >> + metis_tac []); + +val bounded_restrict_id = Q.prove ( +`!t. + good_cmp cmp ∧ + bounded_all cmp blo bhi t + ⇒ + restrict_domain cmp blo bhi (to_fmap cmp t) = to_fmap cmp t`, + Induct_on `t` >> + rw [bounded_all_def, to_fmap_def, restrict_domain_union, restrict_domain_update] >> + Cases_on `blo` >> + Cases_on `bhi` >> + fs [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def]); + +val restrict_domain_empty = Q.prove ( +`good_cmp cmp ⇒ + restrict_domain cmp blo (SOME kx) (restrict_domain cmp (SOME kx) bhi t) = FEMPTY ∧ + restrict_domain cmp (SOME kx) bhi (restrict_domain cmp blo (SOME kx) t) = FEMPTY`, + Cases_on `blo` >> + Cases_on `bhi` >> + fmrw [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def, fmap_eq_flookup] >> + metis_tac [good_cmp_def, comparison_distinct, key_set_eq]); + +val hedgeUnion_thm = Q.prove ( +`!cmp blo bhi t1 t2. + good_cmp cmp ∧ + invariant cmp t1 ∧ + invariant cmp t2 ∧ + bounded_all cmp blo bhi t1 ∧ + bounded_root cmp blo bhi t2 + ⇒ + invariant cmp (hedgeUnion cmp blo bhi t1 t2) ∧ + to_fmap cmp (hedgeUnion cmp blo bhi t1 t2) = + restrict_domain cmp blo bhi (to_fmap cmp t1 ⊌ to_fmap cmp t2)`, + ho_match_mp_tac (fetch "-" "hedgeUnion_ind") >> + rpt conj_tac >> + simp [hedgeUnion_def] >> + rpt conj_tac >> + rpt gen_tac >> + strip_tac + >- rw [to_fmap_def, FUNION_FEMPTY_2, bounded_restrict_id] + >- (inv_mp_tac link_thm >> + simp [GSYM CONJ_ASSOC] >> + inv_mp_tac filterGt_thm >> + simp [] >> + fs [invariant_eq] >> + strip_tac >> + inv_mp_tac filterLt_thm >> + simp [] >> + strip_tac >> + conj_tac + >- (rfs [key_ordered_to_fmap, restrict_domain_def] >> + Cases_on `blo` >> + fs [restrict_set_def, option_cmp_def, option_cmp2_def]) >> + conj_tac + >- (rfs [key_ordered_to_fmap, restrict_domain_def] >> + Cases_on `bhi` >> + fs [restrict_set_def, option_cmp_def, option_cmp2_def]) >> + `restrict_domain cmp blo bhi FEMPTY = FEMPTY` by rw [restrict_domain_def] >> + rw [to_fmap_def, restrict_domain_union, restrict_domain_update] >> + fmrw [restrict_domain_def, fmap_eq_flookup] >> + rw [] >> + Cases_on `blo` >> + Cases_on `bhi` >> + fs [restrict_set_def, option_cmp_def, option_cmp2_def, bounded_root_def] >> + fs [] >> + rw [FLOOKUP_DEF] >> + metis_tac [key_ordered_to_fmap, cmp_thms, to_fmap_key_set, key_set_cmp_thm]) + >- (inv_mp_tac insertR_thm >> + imp_res_tac bounded_restrict_id >> + rw [restrict_domain_union, to_fmap_def, restrict_domain_update] >> + rw [restrict_domain_def, fmap_eq_flookup] >> + fmrw [] >> + every_case_tac >> + fs [FLOOKUP_DEF, bounded_root_def]) >| + [qabbrev_tac `r1 = Bin v39 v40 v41 v42 v43` >> + qabbrev_tac `r2 = Bin v9 v10 v11 Tip r1`, + qabbrev_tac `r1 = Bin v29 v30 v31 v32 v33` >> + qabbrev_tac `r2 = Bin v9 v10 v11 r1 v13`] >> +(simp [bounded_all_def] >> + strip_tac >> + inv_mp_tac link_thm >> + `invariant cmp t1'` by metis_tac [invariant_def] >> + `invariant cmp t1` by metis_tac [invariant_def] >> + simp [bounded_all_def, GSYM CONJ_ASSOC] >> + FIRST_X_ASSUM inv_mp_tac >> + simp [GSYM CONJ_ASSOC] >> + inv_mp_tac trim_thm >> + simp [bounded_all_def] >> + strip_tac >> + conj_tac + >- (fs [invariant_eq] >> + metis_tac [bounded_all_shrink1]) >> + strip_tac >> + FIRST_X_ASSUM inv_mp_tac >> + simp [GSYM CONJ_ASSOC] >> + inv_mp_tac trim_thm >> + simp [bounded_all_def] >> + strip_tac >> + conj_tac + >- (fs [invariant_eq] >> + metis_tac [bounded_all_shrink2]) >> + strip_tac >> + qabbrev_tac `m1 = hedgeUnion cmp blo (SOME kx) t1 (trim cmp blo (SOME kx) r2)` >> + qabbrev_tac `m2 = hedgeUnion cmp (SOME kx) bhi t1' (trim cmp (SOME kx) bhi r2)` >> + conj_asm1_tac + >- (rw [key_ordered_to_fmap, restrict_domain_union] >> + Cases_on `blo` >> + fs [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def] >> + metis_tac [good_cmp_def, comparison_distinct, key_set_cmp_thm]) >> + conj_asm1_tac + >- (rw [key_ordered_to_fmap, restrict_domain_union] >> + Cases_on `bhi` >> + fs [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def] >> + metis_tac [good_cmp_def, comparison_distinct, key_set_cmp_thm]) >> + rw [restrict_domain_union, restrict_domain_update] >> + `key_set cmp kx ∉ FDOM (to_fmap cmp m1) ∧ key_set cmp kx ∉ FDOM (to_fmap cmp m2)` + by metis_tac [key_ordered_to_fmap, cmp_thms, to_fmap_key_set, key_set_cmp_thm] >> + `restrict_domain cmp blo (SOME kx) (to_fmap cmp m2) SUBMAP (to_fmap cmp m1) ∧ + restrict_domain cmp (SOME kx) bhi (to_fmap cmp m1) SUBMAP (to_fmap cmp m2)` + by (qunabbrev_tac `m1` >> + qunabbrev_tac `m2` >> + rw [restrict_domain_union, SUBMAP_DEF, restrict_domain_empty]) >> + `restrict_domain cmp blo bhi (to_fmap cmp m1) ⊌ + restrict_domain cmp blo bhi (to_fmap cmp m2) = + restrict_domain cmp blo (SOME kx) (to_fmap cmp m1) ⊌ + restrict_domain cmp (SOME kx) bhi (to_fmap cmp m2)` + by metis_tac [restrict_domain_partition] >> + simp [restrict_domain_union, restrict_domain_update, to_fmap_def] >> + rw [restrict_domain_union_swap] >> + imp_res_tac restrict_domain_extend >> + rw [] >> + simp [fmap_eq_flookup] >> + rw [FLOOKUP_UPDATE] >> + REWRITE_TAC [GSYM FUNION_ASSOC] >> + ONCE_REWRITE_TAC [FLOOKUP_FUNION] >> + every_case_tac >> + ONCE_REWRITE_TAC [FLOOKUP_FUNION] >> + every_case_tac >> + metis_tac [restrict_domain_combine])); + +val bounded_all_NONE = Q.prove ( +`!cmp t. bounded_all cmp NONE NONE t`, + Induct_on `t` >> + rw [bounded_all_def, restrict_set_def, option_cmp_def, option_cmp2_def]); + +val union_thm = Q.store_thm ("union_thm", +`!cmp blo bhi t1 t2. + good_cmp cmp ∧ + invariant cmp t1 ∧ + invariant cmp t2 + ⇒ + invariant cmp (union cmp t1 t2) ∧ + to_fmap cmp (union cmp t1 t2) = (to_fmap cmp t1 ⊌ to_fmap cmp t2)`, + Cases_on `t1` >> + Cases_on `t2` >> + simp [union_def, to_fmap_def] >> + gen_tac >> + strip_tac >> + inv_mp_tac hedgeUnion_thm >> + rw [bounded_all_NONE, bounded_root_def, restrict_set_def, option_cmp_def, + restrict_domain_def, option_cmp2_def, to_fmap_def] >> + rw [fmap_eq_flookup] >> + fmrw [] >> + every_case_tac >> + fs [FLOOKUP_DEF, invariant_eq] >> + rfs [key_ordered_to_fmap] >> + metis_tac [cmp_thms, to_fmap_key_set]); + +val EXT2 = Q.prove ( +`!s1 s2. s1 = s2 ⇔ (!k v. (k,v) ∈ s1 ⇔ (k,v) ∈ s2)`, + rw [EXTENSION] >> + EQ_TAC >> + rw [] >> + PairCases_on `x` >> + rw []); + +val lift_key_def = Define ` +lift_key cmp kvs = IMAGE (\(k,v). (key_set cmp k, v)) kvs`; + +val toAscList_helper = Q.prove ( +`!cmp l t. + good_cmp cmp ∧ + invariant cmp t ∧ + SORTED (\(x,y) (x',y'). cmp x x' = Less) l ∧ + (!k1 v1 k2 v2. MEM (k1,v1) l ∧ FLOOKUP (to_fmap cmp t) (key_set cmp k2) = SOME v2 ⇒ cmp k2 k1 = Less) + ⇒ + SORTED (\(x,y) (x',y'). cmp x x' = Less) (foldrWithKey (λk x xs. (k,x)::xs) l t) ∧ + lift_key cmp (set (foldrWithKey (λk x xs. (k,x)::xs) l t)) = + set (fmap_to_alist (to_fmap cmp t)) ∪ lift_key cmp (set l)`, + Induct_on `t` >> + simp [foldrWithKey_def, to_fmap_def] >> + fs [invariant_eq, EXT2] >> + rpt gen_tac >> + strip_tac >> + simp [FLOOKUP_UPDATE, FLOOKUP_FUNION, PULL_FORALL] >> + rpt gen_tac >> + first_x_assum (qspecl_then [`cmp`, `l`] mp_tac) >> + first_x_assum (qspecl_then [`cmp`, `(k,v)::foldrWithKey (λk x xs. (k,x)::xs) l t'`] mp_tac) >> + simp [] >> + strip_tac >> + strip_tac >> + fs [FLOOKUP_UPDATE, FLOOKUP_FUNION] >> + `SORTED (λ(x,y) (x',y'). cmp x x' = Less) (foldrWithKey (λk x xs. (k,x)::xs) l t') ∧ + ∀k v. + (k,v) ∈ lift_key cmp (set (foldrWithKey (λk x xs. (k,x)::xs) l t')) ⇔ + FLOOKUP (to_fmap cmp t') k = SOME v ∨ (k,v) ∈ lift_key cmp (set l)` + by (first_x_assum match_mp_tac >> + rw [] >> + last_x_assum match_mp_tac >> + rw [] + >- metis_tac [] >> + qexists_tac `v1` >> + rw [] >> + qexists_tac `v2` >> + rw [] >> + every_case_tac >> + fs [DISJOINT_DEF, EXTENSION, FLOOKUP_DEF] >> + metis_tac []) >> + `SORTED (λ(x,y) (x',y'). cmp x x' = Less) + (foldrWithKey (λk x xs. (k,x)::xs) + ((k,v)::foldrWithKey (λk x xs. (k,x)::xs) l t') t) ∧ + ∀k' v'. + (k',v') ∈ lift_key cmp (set (foldrWithKey (λk x xs. (k,x)::xs) ((k,v)::foldrWithKey (λk x xs. (k,x)::xs) l t') t)) ⇔ + FLOOKUP (to_fmap cmp t) k' = SOME v' ∨ + (k',v') ∈ lift_key cmp ((k,v) INSERT set (foldrWithKey (λk x xs. (k,x)::xs) l t'))` + by (first_x_assum match_mp_tac >> + simp [good_cmp_trans, SORTED_EQ, FORALL_PROD] >> + rw [] + >- (`(key_set cmp p_1, p_2) ∈ lift_key cmp (set (foldrWithKey (λk x xs. (k,x)::xs) l t'))` + by (fs [lift_key_def, LAMBDA_PROD, EXISTS_PROD] >> + metis_tac []) >> + rfs [FLOOKUP_DEF] >> + rfs [key_ordered_to_fmap] + >- metis_tac [cmp_thms, key_set_cmp_thm] >> + fs [lift_key_def, LAMBDA_PROD, EXISTS_PROD] >> + metis_tac [cmp_thms, key_set_eq]) + >- (rfs [key_ordered_to_fmap, FLOOKUP_DEF] >> + metis_tac [cmp_thms, key_set_cmp_thm]) + >- (`(key_set cmp k1, v1) ∈ lift_key cmp (set (foldrWithKey (λk x xs. (k,x)::xs) l t'))` + by (fs [lift_key_def, LAMBDA_PROD, EXISTS_PROD] >> + metis_tac []) >> + rfs [FLOOKUP_DEF] >> + rfs [key_ordered_to_fmap] + >- metis_tac [cmp_thms, key_set_cmp_thm] >> + fs [lift_key_def, LAMBDA_PROD, EXISTS_PROD] >> + metis_tac [cmp_thms, key_set_cmp_thm, key_set_eq])) >> + simp [] >> + eq_tac >> + rw [] >> + fs [FLOOKUP_DEF, DISJOINT_DEF, EXTENSION, FLOOKUP_DEF] >> + every_case_tac >> + rw [] >> + fs [lift_key_def, LAMBDA_PROD, EXISTS_PROD] >> + metis_tac []); + +val toAscList_thm = Q.store_thm ("toAscList_thm", +`!cmp t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + SORTED (\(x,y) (x',y'). cmp x x' = Less) (toAscList t) ∧ + lift_key cmp (set (toAscList t)) = set (fmap_to_alist (to_fmap cmp t))`, + rpt gen_tac >> + strip_tac >> + qspecl_then [`cmp`, `[]`, `t`] mp_tac toAscList_helper >> + simp [toAscList_def, lift_key_def]); + +val compare_good_cmp = Q.store_thm ("compare_good_cmp", +`!cmp1 cmp2. good_cmp cmp1 ∧ good_cmp cmp2 ⇒ good_cmp (compare cmp1 cmp2)`, + rw [] >> + imp_res_tac pair_cmp_good >> + imp_res_tac list_cmp_good >> + rpt (pop_assum mp_tac) >> + REWRITE_TAC [good_cmp_def, compare_def] >> + metis_tac []); + +val compare_thm1 = Q.prove ( +`!cmp1 cmp2 t1 t2. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ + invariant cmp1 t1 ∧ + invariant cmp1 t2 ∧ + compare cmp1 cmp2 t1 t2 = Equal + ⇒ + fmap_rel (\x y. cmp2 x y = Equal) (to_fmap cmp1 t1) (to_fmap cmp1 t2)`, + rw [compare_def, fmap_rel_OPTREL_FLOOKUP, OPTREL_def] >> + imp_res_tac toAscList_thm >> + fs [lift_key_def, list_cmp_equal_list_rel, pair_cmp_def] >> + fs [key_set_def, EXTENSION, LAMBDA_PROD, FORALL_PROD, EXISTS_PROD] >> + fs [LIST_REL_EL_EQN] >> + pop_assum (mp_tac o GSYM) >> + pop_assum (mp_tac o GSYM) >> + rw [] >> + Cases_on `FLOOKUP (to_fmap cmp1 t1) k` >> + rw [] + >- (disj1_tac >> + Cases_on `FLOOKUP (to_fmap cmp1 t2) k` >> + fs [] >> + rfs [] >> + fs [MEM_EL] >> + res_tac >> + Cases_on `EL n (toAscList t1)` >> + Cases_on `EL n (toAscList t2)` >> + fs [] >> + every_case_tac >> + fs [] >> + rw [] >> + first_x_assum (qspecl_then [`k`] mp_tac) >> + strip_tac >> + rfs [] >> + pop_assum (qspecl_then [`r`, `q`] mp_tac) >> + rw [] >> + metis_tac [NOT_SOME_NONE, cmp_thms]) + >- (rfs [] >> + fs [MEM_EL] >> + rfs [] >> + res_tac >> + Cases_on `EL n (toAscList t1)` >> + Cases_on `EL n (toAscList t2)` >> + fs [] >> + every_case_tac >> + fs [] >> + rw [] >> + MAP_EVERY qexists_tac [`r`, `r'`] >> + rw [] + >- metis_tac [] >> + qexists_tac `q'` >> + rw [] >> + metis_tac [cmp_thms])); + +val NONE_lem = Q.prove ( +`x = NONE ⇔ ¬?y. x = SOME y`, + Cases_on `x` >> + rw []); + +val pair_cmp_lem = Q.prove ( +`!cmp1 cmp2. pair_cmp cmp1 cmp2 (x1,x2) (y1,y2) = Equal ⇔ cmp1 x1 y1 = Equal ∧ cmp2 x2 y2 = Equal`, + rw [pair_cmp_def] >> + every_case_tac); + +val strict_sorted_unique = Q.prove ( +`!cmp l x1 y1 x2 y2. + good_cmp cmp ∧ + SORTED (λ(x,y) (x',y'). cmp x x' = Less) l ∧ + MEM (x1,y1) l ∧ + MEM (x2,y2) l ∧ + cmp x1 x2 = Equal + ⇒ + x1 = x2 ∧ y1 = y2`, + Induct_on `l` >> + rw [] >> + `transitive (λ(x,y) (x',y'). cmp x x' = Less)` by metis_tac [good_cmp_trans] >> + fs [SORTED_EQ, LAMBDA_PROD, FORALL_PROD] + >- metis_tac [cmp_thms] + >- metis_tac [cmp_thms] + >- metis_tac [cmp_thms] + >- metis_tac [cmp_thms] >> + Cases_on `h` >> + fs [] >> + res_tac); + +val strict_sorted_eq_el = Q.prove ( +`!cmp l m n. + good_cmp cmp ∧ + SORTED (λ(x,y) (x',y'). cmp x x' = Less) l ∧ + cmp (FST (EL m l)) (FST (EL n l)) = Equal ∧ + m < LENGTH l ∧ + n < LENGTH l + ⇒ + m = n`, + Induct_on `l` >> + rw [] >> + `transitive (λ(x,y) (x',y'). cmp x x' = Less)` by metis_tac [good_cmp_trans] >> + fs [SORTED_EQ, LAMBDA_PROD, FORALL_PROD] >> + Cases_on `h` >> + fs [] >> + Cases_on `0 < n` >> + Cases_on `0 < m` >> + fs [rich_listTheory.EL_CONS] >> + full_simp_tac (srw_ss()++ARITH_ss) [] >> + rw [] + >- (res_tac >> + full_simp_tac (srw_ss()++ARITH_ss) []) + >- (`PRE n < LENGTH l` by decide_tac >> + `MEM (EL (PRE n) l) l` by metis_tac [MEM_EL] >> + Cases_on `EL (PRE n) l` >> + fs [] >> + metis_tac [cmp_thms]) + >- (`PRE m < LENGTH l` by decide_tac >> + `MEM (EL (PRE m) l) l` by metis_tac [MEM_EL] >> + Cases_on `EL (PRE m) l` >> + fs [] >> + metis_tac [cmp_thms])); + +val compare_lem2 = Q.prove ( +`!cmp1 cmp2 n l1 l2. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ + (∀k. + (∀y p_1' y' p_1''. + (k ≠ key_set cmp1 p_1' ∨ ¬MEM (p_1',y) l1) ∧ + (k ≠ key_set cmp1 p_1'' ∨ ¬MEM (p_1'',y') l2)) ∨ + ∃x y p_1' p_1''. + (k = key_set cmp1 p_1' ∧ MEM (p_1',x) l1) ∧ + (k = key_set cmp1 p_1'' ∧ MEM (p_1'',y) l2) ∧ cmp2 x y = Equal) ∧ + SORTED (λ(x,y) (x',y'). cmp1 x x' = Less) l2 ∧ + SORTED (λ(x,y) (x',y'). cmp1 x x' = Less) l1 ∧ + n ≤ LENGTH l1 ∧ + n ≤ LENGTH l2 ∧ + LIST_REL (λ(p1,p2) (p1',p2'). pair_cmp cmp1 cmp2 (p1,p2) (p1',p2') = Equal) + (TAKE n l1) (TAKE n l2) ∧ + n ≠ LENGTH l1 + ⇒ + n ≠ LENGTH l2 ∧ + (λ(p1,p2) (p1',p2'). pair_cmp cmp1 cmp2 (p1,p2) (p1',p2') = Equal) + (EL n l1) (EL n l2)`, + rpt GEN_TAC >> + rpt DISCH_TAC >> + fs [] >> + `?kn1 vn1. EL n l1 = (kn1,vn1)` by metis_tac [pair_CASES] >> + simp [] >> + `?kn2 vn2. MEM (kn2,vn2) l2 ∧ cmp1 kn1 kn2 = Equal ∧ cmp2 vn1 vn2 = Equal` + by (first_assum (qspecl_then [`key_set cmp1 kn1`] assume_tac) >> + `MEM (EL n l1) l1` by metis_tac [PAIR, rich_listTheory.EL_MEM, LESS_OR_EQ] >> + fs [] >> + rfs [key_set_eq] + >- metis_tac [PAIR, cmp_thms] >> + `p_1' = kn1 ∧ x = vn1` + by (match_mp_tac strict_sorted_unique >> + rw [] >> + metis_tac [cmp_thms]) >> + rw [] >> + metis_tac []) >> + fs [MEM_EL] >> + `n' < n ∨ n = n' ∨ n < n'` by decide_tac >> + fs [] + >- (fs [LIST_REL_EL_EQN] >> + first_x_assum (qspecl_then [`n'`] mp_tac) >> + simp [rich_listTheory.EL_TAKE] >> + DISCH_TAC >> + fs [] >> + Cases_on `EL n' l1` >> + Cases_on `EL n' l2` >> + fs [pair_cmp_lem] >> + `n' < LENGTH l1 ∧ n < LENGTH l1` by decide_tac >> + imp_res_tac strict_sorted_eq_el >> + `n' = n` by metis_tac [FST, PAIR, cmp_thms] >> + fs []) + >- (rw [pair_cmp_lem] >> + Cases_on `EL n l2` >> + rw [] >> + metis_tac []) + >- (`?kn3 vn3. EL n l2 = (kn3,vn3)` by metis_tac [pair_CASES] >> + simp [] >> + `?kn4 vn4. MEM (kn4,vn4) l1 ∧ cmp1 kn3 kn4 = Equal ∧ cmp2 vn3 vn4 = Equal` + by (first_assum (qspecl_then [`key_set cmp1 kn3`] assume_tac) >> + `n < LENGTH l2` by decide_tac >> + `n < LENGTH l1` by decide_tac >> + `MEM (EL n l2) l2` by metis_tac [PAIR, rich_listTheory.EL_MEM, LESS_OR_EQ] >> + fs [] >> + rfs [key_set_eq] >> + `n < LENGTH l2` by decide_tac >> + `n < LENGTH l1` by decide_tac + >- metis_tac [PAIR, cmp_thms] >> + rw [] >> + `p_1'' = kn3 ∧ y = vn3` + by (match_mp_tac strict_sorted_unique >> + rw [] >> + metis_tac [rich_listTheory.EL_MEM, cmp_thms]) >> + rw [] >> + MAP_EVERY qexists_tac [`p_1'`, `x`] >> + rw [rich_listTheory.EL_MEM] >> + metis_tac [cmp_thms]) >> + fs [MEM_EL] >> + `n < n'' ∨ n = n'' ∨ n'' < n` by decide_tac >> + fs [] >> + `cmp1 kn3 kn2 = Less` + by (`transitive (λ(x,y) (x',y'). cmp1 x x' = Less)` by metis_tac [good_cmp_trans] >> + `(λ(x,y) (x',y'). cmp1 x x' = Less) (EL n l2) (EL n' l2)` + by metis_tac [SORTED_EL_LESS] >> + rfs [] >> + Cases_on `EL n' l2` >> + fs []) + >- (`cmp1 kn1 kn4 = Less` + by (`transitive (λ(x,y) (x',y'). cmp1 x x' = Less)` by metis_tac [good_cmp_trans] >> + `(λ(x,y) (x',y'). cmp1 x x' = Less) (EL n l1) (EL n'' l1)` + by metis_tac [SORTED_EL_LESS] >> + rfs [] >> + Cases_on `EL n'' l1` >> + fs []) >> + metis_tac [cmp_thms]) + >- (rw [] >> + rfs [] >> + metis_tac [cmp_thms]) + >- (fs [LIST_REL_EL_EQN] >> + first_x_assum (qspecl_then [`n''`] mp_tac) >> + simp [rich_listTheory.EL_TAKE] >> + DISCH_TAC >> + fs [] >> + Cases_on `EL n'' l1` >> + Cases_on `EL n'' l2` >> + fs [pair_cmp_lem] >> + rfs [] >> + `n < LENGTH l2` by decide_tac >> + `cmp1 kn1 kn4 = Less` + by (`transitive (λ(x,y) (x',y'). cmp1 x x' = Less)` by metis_tac [good_cmp_trans] >> + `(λ(x,y) (x',y'). cmp1 x x' = Less) (EL n'' l2) (EL n l2)` + by metis_tac [SORTED_EL_LESS] >> + rfs [] >> + Cases_on `EL n'' l2` >> + fs [] >> + metis_tac [cmp_thms]) >> + metis_tac [cmp_thms]))); + +val compare_thm2 = Q.prove ( +`!cmp1 cmp2 t1 t2. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ + invariant cmp1 t1 ∧ + invariant cmp1 t2 ∧ + fmap_rel (\x y. cmp2 x y = Equal) (to_fmap cmp1 t1) (to_fmap cmp1 t2) + ⇒ + compare cmp1 cmp2 t1 t2 = Equal`, + rw [compare_def, fmap_rel_OPTREL_FLOOKUP, OPTREL_def, list_cmp_equal_list_rel] >> + imp_res_tac toAscList_thm >> + fs [EXTENSION] >> + simp [] >> + fs [lift_key_def, PULL_EXISTS, LAMBDA_PROD, FORALL_PROD, EXISTS_PROD] >> + pop_assum (mp_tac o GSYM) >> + pop_assum (mp_tac o GSYM) >> + DISCH_TAC >> + DISCH_TAC >> + fs [NONE_lem] >> + ntac 3 (pop_assum (fn _ => all_tac)) >> + pop_assum mp_tac >> + pop_assum mp_tac >> + pop_assum (fn _ => all_tac) >> + pop_assum mp_tac >> + ntac 2 (pop_assum (fn _ => all_tac)) >> + Q.SPEC_TAC (`toAscList t1`, `l1`) >> + Q.SPEC_TAC (`toAscList t2`, `l2`) >> + fs [PULL_FORALL, PULL_EXISTS] >> + rw [] >> + ONCE_REWRITE_TAC [list_rel_thm] >> + gen_tac >> + DISCH_TAC >> + fs [] + >- (match_mp_tac compare_lem2 >> + rw []) + >- (`n ≠ LENGTH l1 ∧ (λ(p1,p2) (p1',p2'). pair_cmp cmp1 cmp2 (p1,p2) (p1',p2') = Equal) (EL n l2) (EL n l1)` + by (match_mp_tac compare_lem2 >> + rw [] + >- (first_x_assum (qspecl_then [`k`] mp_tac) >> + rw [] >> + metis_tac [good_cmp_def]) + >- (match_mp_tac (SIMP_RULE (srw_ss()) [AND_IMP_INTRO, PULL_FORALL] (GEN_ALL EVERY2_sym)) >> + qexists_tac `(λ(p1,p2) (p1',p2'). pair_cmp cmp1 cmp2 (p1,p2) (p1',p2') = Equal)` >> + rw [] >> + PairCases_on `y'` >> + PairCases_on `x'` >> + fs [] >> + metis_tac [good_cmp_def, pair_cmp_good])) >> + Cases_on `EL n l1` >> + Cases_on `EL n l2` >> + fs [] >> + metis_tac [good_cmp_def, pair_cmp_good])); + +val compare_thm = Q.store_thm ("compare_thm", +`!cmp1 cmp2 t1 t2. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ + invariant cmp1 t1 ∧ + invariant cmp1 t2 + ⇒ + (compare cmp1 cmp2 t1 t2 = Equal + ⇔ + fmap_rel (\x y. cmp2 x y = Equal) (to_fmap cmp1 t1) (to_fmap cmp1 t2))`, + metis_tac [compare_thm1, compare_thm2]); + +val map_thm = Q.store_thm ("map_thm", +`!t. + good_cmp cmp ∧ + invariant cmp t + ⇒ + invariant cmp (map f t) ∧ + to_fmap cmp (map f t) = f o_f to_fmap cmp t`, + Induct_on `t` >> + simp [map_def, to_fmap_def] + >- rw [invariant_def] >> + rpt gen_tac >> + strip_tac >> + simp [invariant_def, GSYM CONJ_ASSOC] >> + inv_to_front_tac ``invariant`` >> + first_x_assum inv_mp_tac >> + simp [] >> + fs [invariant_eq] >> + strip_tac >> + imp_res_tac (GSYM structure_size_thm) >> + imp_res_tac size_thm >> + simp [FCARD_DEF] >> + rw [] + >- rfs [key_ordered_to_fmap] + >- rfs [key_ordered_to_fmap] + >- fs [FCARD_DEF] + >- (fmrw [fmap_eq_flookup] >> + fmrw [FLOOKUP_o_f, DOMSUB_FLOOKUP_THM] >> + every_case_tac >> + fs [])); + +val splitLookup_thm = Q.store_thm ("splitLookup_thm", +`!t lt v gt. + good_cmp cmp ∧ + invariant cmp t ∧ + (lt,v,gt) = splitLookup cmp k t + ⇒ + invariant cmp lt ∧ + invariant cmp gt ∧ + FLOOKUP (to_fmap cmp t) (key_set cmp k) = v ∧ + key_ordered cmp k lt Greater ∧ + key_ordered cmp k gt Less ∧ + to_fmap cmp t = + case v of + | NONE => FUNION (to_fmap cmp lt) (to_fmap cmp gt) + | SOME v => (FUNION (to_fmap cmp lt) (to_fmap cmp gt)) |+ (key_set cmp k, v)`, + Induct_on `t` >> + simp [splitLookup_def, to_fmap_def, key_ordered_to_fmap] >> + rpt gen_tac >> + strip_tac >> + Cases_on `cmp k k'` >> + fs [] + >- (`?lt v gt. splitLookup cmp k t = (lt,v,gt)` by metis_tac [pair_CASES] >> + fs [] >> + last_x_assum inv_mp_tac >> + simp [] >> + fs [invariant_eq] >> + strip_tac >> + inv_mp_tac link_thm >> + simp [] >> + conj_asm1_tac + >- (rfs [key_ordered_to_fmap] >> + rw [] >> + first_x_assum match_mp_tac >> + rw [] >> + every_case_tac >> + fs []) >> + strip_tac >> + Cases_on `v''` >> + fs [] >> + fmrw [] >> + rfs [FLOOKUP_FUNION] >> + every_case_tac >> + fs [] >> + TRY (match_mp_tac FUPDATE_COMMUTES) >> + rfs [key_ordered_to_fmap, flookup_thm] >> + res_tac >> + metis_tac [cmp_thms, key_set_cmp_def, key_set_cmp_thm]) + >- (`?lt v gt. splitLookup cmp k t' = (lt,v,gt)` by metis_tac [pair_CASES] >> + fs [] >> + fs [invariant_eq] >> + inv_mp_tac link_thm >> + simp [] >> + conj_asm1_tac + >- (rfs [key_ordered_to_fmap] >> + rw [] >> + first_x_assum match_mp_tac >> + rw [] >> + every_case_tac >> + fs []) >> + strip_tac >> + Cases_on `v''` >> + fs [] >> + fmrw [] >> + rfs [FLOOKUP_FUNION] >> + every_case_tac >> + fs [] >> + TRY (match_mp_tac FUPDATE_COMMUTES) >> + rfs [key_ordered_to_fmap, flookup_thm] >> + fs [key_ordered_to_fmap, flookup_thm] >> + res_tac >> + metis_tac [cmp_thms, key_set_cmp_def, key_set_cmp_thm]) + >- (fs [invariant_eq] >> + fmrw [key_set_eq] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + fs [key_set_cmp_def] >> + fmrw [fmap_eq_flookup] >> + every_case_tac >> + fs [] >> + rw [] >> + rfs [key_set_eq] >> + metis_tac [cmp_thms])); + +val submap'_thm = Q.prove ( +`!cmp f t1 t2. + good_cmp cmp ∧ + invariant cmp t1 ∧ + invariant cmp t2 + ⇒ + (submap' cmp f t1 t2 ⇔ !k v. lookup cmp k t1 = SOME v ⇒ ?v'. lookup cmp k t2 = SOME v' ∧ f v v')`, + ho_match_mp_tac (fetch "-" "submap'_ind") >> + rpt conj_tac + >- rw [lookup_def, submap'_def] + >- (rw [lookup_def, submap'_def, invariant_eq] >> + qexists_tac `v11` >> + qexists_tac `v12` >> + every_case_tac >> + fs [] >> + metis_tac [cmp_thms]) >> + rw [] >> + qabbrev_tac `t = Bin v20 v21 v22 v23 v24` >> + `?lt v gt. splitLookup cmp kx t = (lt,v,gt)` by metis_tac [pair_CASES] >> + fs [] >> + `invariant cmp lt ∧ invariant cmp gt ∧ + FLOOKUP (to_fmap cmp t) (key_set cmp kx) = v ∧ + key_ordered cmp kx lt Greater ∧ key_ordered cmp kx gt Less ∧ + to_fmap cmp t = + case v of + NONE => to_fmap cmp lt ⊌ to_fmap cmp gt + | SOME v' => (to_fmap cmp lt ⊌ to_fmap cmp gt) |+ (key_set cmp kx,v')` + by metis_tac [splitLookup_thm] >> + unabbrev_all_tac >> + Cases_on `v` >> + fs [] + >- (rw [submap'_def, lookup_def] >> + qexists_tac `kx` >> + qexists_tac `x` >> + rw [] + >- metis_tac [cmp_thms] >> + every_case_tac >> + fs [] >> + CCONTR_TAC >> + fs [] >> + imp_res_tac lookup_thm >> + fs [lookup_def, to_fmap_def] >> + metis_tac [cmp_thms, NOT_SOME_NONE]) + >- (simp [submap'_def] >> + qabbrev_tac `t = Bin v20 v21 v22 v23 v24` >> + pop_assum (fn _ => all_tac) >> + fs [invariant_eq] >> + rw [lookup_def] >> + eq_tac >> + simp [] + >- (rw [] >> + imp_res_tac lookup_thm >> + rw [FLOOKUP_UPDATE] >> + rfs [key_set_eq] >> + fs [] + >- (`cmp k kx = Equal` by metis_tac [cmp_thms] >> + fs []) >> + rw [FLOOKUP_FUNION] >> + Cases_on `cmp k kx` >> + fs [] >> + res_tac + >- (qexists_tac `v''` >> + rw []) + >- (rfs [key_ordered_to_fmap] >> + `FLOOKUP (to_fmap cmp lt) (key_set cmp k) = NONE` + by (fs [FLOOKUP_DEF] >> + CCONTR_TAC >> + fs [] >> + res_tac >> + fs [key_set_cmp_def, key_set_def] >> + metis_tac [cmp_thms]) >> + rw []) + >- metis_tac [cmp_thms]) >> + rw [] + >- (first_assum (qspecl_then [`kx`, `x`] assume_tac) >> + every_case_tac >> + fs [] + >- metis_tac [cmp_thms] + >- metis_tac [cmp_thms] >> + imp_res_tac lookup_thm >> + fs [] >> + rfs [] >> + rw []) + >- (imp_res_tac lookup_thm >> + fs [] >> + rfs [FLOOKUP_UPDATE] >> + rw [] >> + last_assum (qspecl_then [`k`] assume_tac) >> + Cases_on `cmp k kx` >> + fs [] >> + rfs [key_set_eq] + >- (`cmp kx k ≠ Equal` by metis_tac [cmp_thms] >> + fs [FLOOKUP_FUNION] >> + Cases_on `FLOOKUP (to_fmap cmp lt) (key_set cmp k)` >> + fs [FLOOKUP_DEF] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + fs [key_set_cmp_def, key_set_def] >> + metis_tac [cmp_thms]) + >- (`cmp kx k ≠ Equal` by metis_tac [cmp_thms] >> + fs [FLOOKUP_DEF] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + fs [key_set_cmp_def, key_set_def] >> + metis_tac [cmp_thms]) + >- (`cmp kx k = Equal` by metis_tac [cmp_thms] >> + fs [FLOOKUP_DEF] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + fs [key_set_cmp_def, key_set_def] >> + metis_tac [cmp_thms])) + >- (imp_res_tac lookup_thm >> + fs [] >> + rfs [FLOOKUP_UPDATE] >> + rw [] >> + last_assum (qspecl_then [`k`] assume_tac) >> + Cases_on `cmp k kx` >> + fs [] >> + rfs [key_set_eq] + >- (`cmp kx k ≠ Equal` by metis_tac [cmp_thms] >> + fs [FLOOKUP_DEF] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + fs [key_set_cmp_def, key_set_def] >> + metis_tac [cmp_thms]) + >- (`cmp kx k ≠ Equal` by metis_tac [cmp_thms] >> + fs [FLOOKUP_FUNION] >> + Cases_on `FLOOKUP (to_fmap cmp lt) (key_set cmp k)` >> + fs [FLOOKUP_DEF] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + fs [key_set_cmp_def, key_set_def] >> + metis_tac [cmp_thms]) + >- (`cmp kx k = Equal` by metis_tac [cmp_thms] >> + fs [FLOOKUP_DEF] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + fs [key_set_cmp_def, key_set_def] >> + metis_tac [cmp_thms])))); + +val isSubmapOfBy_thm = Q.store_thm ("isSubmapOfBy_thm", +`!cmp f t1 t2. + good_cmp cmp ∧ + invariant cmp t1 ∧ + invariant cmp t2 + ⇒ + (isSubmapOfBy cmp f t1 t2 ⇔ !k v. lookup cmp k t1 = SOME v ⇒ ?v'. lookup cmp k t2 = SOME v' ∧ f v v')`, + rw [isSubmapOfBy_def] >> + Cases_on `size t1 ≤ size t2` >> + rw [submap'_thm] >> + fs [NOT_LESS_EQUAL] >> + imp_res_tac size_thm >> + imp_res_tac lookup_thm >> + fs [FCARD_DEF] >> + `FINITE (FDOM (to_fmap cmp t1)) ∧ FINITE (FDOM (to_fmap cmp t2))` by rw [] >> + imp_res_tac LESS_CARD_DIFF >> + full_simp_tac std_ss [] >> + `FINITE (FDOM (to_fmap cmp t1) DIFF FDOM (to_fmap cmp t2))` by rw [] >> + imp_res_tac POS_CARD_HAS_MEM >> + fs [] >> + rw [FLOOKUP_DEF] >> + imp_res_tac to_fmap_key_set >> + rw [] >> + qexists_tac `k` >> + rw []); + +val isSubmapOf_thm = Q.store_thm ("isSubmapOf_thm", +`!cmp t1 t2. + good_cmp cmp ∧ + invariant cmp t1 ∧ + invariant cmp t2 + ⇒ + (isSubmapOf cmp t1 t2 ⇔ !k v. lookup cmp k t1 = SOME v ⇒ lookup cmp k t2 = SOME v)`, + rw [isSubmapOf_def, isSubmapOfBy_thm]); + +val fromList_thm = Q.store_thm ("fromList_thm", +`!cmp l. + good_cmp cmp + ⇒ + invariant cmp (fromList cmp l) ∧ + to_fmap cmp (fromList cmp l) = alist_to_fmap (MAP (\(k,v). (key_set cmp k, v)) l)`, + Induct_on `l` >> + simp [fromList_def, empty_thm] >> + rpt gen_tac >> + strip_tac >> + PairCases_on `h` >> + simp [] >> + inv_mp_tac insert_thm >> + strip_tac >> + simp [] >> + fs [fromList_def]); + +(* ------------------------ Extra stuff, not from ghc ----------------- *) + +val map_keys_def = Define ` +map_keys cmp f t = fromList cmp (MAP (\(k,v). (f k, v)) (toAscList t))`; + +val in_lift_key = Q.prove ( +`!cmp k v l. + good_cmp cmp ∧ + SORTED (λ(x,y:'a) (x',y':'a). cmp x x' = Less) l ∧ + transitive (λ(x,y:'a) (x',y':'a). cmp x x' = Less) + ⇒ + ((k,v) ∈ lift_key cmp (set l) ⇔ ALOOKUP (MAP (λ(x,y). (key_set cmp x, y)) l) k = SOME v)`, + Induct_on `l` >> + fs [lift_key_def, key_set_def, LAMBDA_PROD, EXISTS_PROD, EXTENSION, FORALL_PROD] >> + rw [] >> + fs [] >> + eq_tac >> + rw [] >> + fs [SORTED_EQ] >> + res_tac >> + fs [] >> + metis_tac [cmp_thms]); + + (* +val alookup_unit_lem = Q.prove ( +`!cmp1 cmp2 f k l x. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ + resp_equiv2 cmp1 cmp2 f + ⇒ + (ALOOKUP (MAP (\(k,v). (key_set cmp1 k, ())) l) (key_set cmp1 x') = + ALOOKUP (MAP (\(k,v). (key_set cmp2 (f k), ())) l) (key_set cmp2 (f x')))`, + + Induct_on `l` >> + rw [] >> + PairCases_on `h` >> + rw [] >> + rfs [key_set_eq, resp_equiv2_def] >> + >- (rfs [] >> + fs [EXTENSION, key_set_def] >> + match_mp_tac (METIS_PROVE [] ``F⇒x``) >> + rw [] >> + pop_assum mp_tac >> + simp [] >> + eq_tac >> + rw [] >> + fs [resp_equiv2_def] + >- (qexists_tac `key_set cmp2 (f h0)` >> + rw [key_set_def] >> + metis_tac [cmp_thms]) + >- metis_tac [cmp_thms]) + >- (rfs [] >> + rw [] >> + fs [EXTENSION, key_set_def] >> + Cases_on `x ∈ k` >> + fs [resp_equiv2_def] >> + first_x_assum (qspecl_then [`f x`] assume_tac) >> + fs [] >> + Cases_on `cmp2 (f h0) (f x) = Equal` >> + fs [] +metis_tac [cmp_thms] + + + rfs [key_set_eq] >> + `IMAGE f (key_set cmp1 h0) ⊆ key_set cmp2 (f h0)` by metis_tac [key_set_map] >> + fs [SUBSET_DEF, EXTENSION] >> + `x ∈ key_set cmp2 (f h0) ∧ ¬?x'. x = f x' ∧ x' ∈ key_set cmp1 h0` by metis_tac [] + fs [] + + fs [key_set_def, resp_equiv2_def, EXTENSION] >> + rw [] >> + rfs [] >> + Cases_on `h1 = v` >> + rw [] >> + + pop_assum mp_tac >> + match_mp_tac (METIS_PROVE [] ``x ⇒ (~x ⇒ y)``) >> + eq_tac >> + rw [] + + metis_tac [cmp_thms] + >- (`IMAGE f k ≠ {}` by cheat >> + imp_res_tac CHOICE_DEF >> + fs [] >> + fs [] >> + + rfs [key_set_eq] >> + fs [key_set_def, resp_equiv2_def] >> + metis_tac [cmp_thms]) + + fs [resp_equiv2_def, key_set_def, EXTENSION] >> + rfs [] + metis_tac [] + *) + +val bigunion_key_sets = Q.prove ( +`!cmp1. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ + resp_equiv2 cmp1 cmp2 f + ⇒ + BIGUNION (IMAGE (\x. key_set cmp2 (f x)) (key_set cmp1 x)) = + key_set cmp2 (CHOICE (IMAGE f (key_set cmp1 x)))`, + rw [EXTENSION] >> + `IMAGE f (key_set cmp1 x) ≠ {}` by (rw [EXTENSION, key_set_def] >> metis_tac [cmp_thms]) >> + imp_res_tac CHOICE_DEF >> + fs [key_set_def] >> + eq_tac >> + rw [] >> + rfs [resp_equiv2_def] + >- metis_tac [cmp_thms] >> + qexists_tac `key_set cmp2 (f x)` >> + rw [key_set_def] >> + metis_tac [cmp_thms]); + +val image_lem = Q.prove ( +`good_cmp cmp1 + ⇒ + IMAGE (λx. key_set cmp2 (f x)) (key_set cmp1 k'') = + { key_set cmp2 (f x) | x | cmp1 x k'' = Equal }`, + rw [EXTENSION,key_set_def] >> + metis_tac [cmp_thms]); + + (* +val map_keys_thm = Q.store_thm ("map_keys_thm", +`!cmp1 cmp2 f t. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ + invariant cmp1 t ∧ + resp_equiv2 cmp1 cmp2 f ∧ + equiv_inj cmp1 cmp2 f + ⇒ + invariant cmp2 (map_keys cmp2 f t) ∧ + to_fmap cmp2 (map_keys cmp2 f t) = MAP_KEYS (BIGUNION o IMAGE (key_set cmp2 o f)) (to_fmap cmp1 t)`, + + simp [map_keys_def] >> + rpt gen_tac >> + DISCH_TAC >> + inv_mp_tac fromList_thm >> + rw [MAP_MAP_o, combinTheory.o_DEF] >> + rw [fmap_eq_flookup] >> + `SORTED (λ(x,y) (x',y'). cmp1 x x' = Less) (toAscList t) ∧ + lift_key cmp1 (set (toAscList t)) = set (fmap_to_alist (to_fmap cmp1 t))` + by metis_tac [toAscList_thm] >> + pop_assum mp_tac >> + simp [EXTENSION, MEM_MAP, LAMBDA_PROD, EXISTS_PROD, FORALL_PROD] >> + `transitive (λ(x,y:'c) (x',y':'c). cmp1 x x' = Less)` by metis_tac [good_cmp_trans] >> + rw [in_lift_key] >> + fs [] >> + rw [FLOOKUP_DEF] >> + `INJ (λx. BIGUNION (IMAGE (λx. key_set cmp2 (f x)) x)) (FDOM (to_fmap cmp1 t)) UNIV` + by rw [INJ_DEF] >> + imp_res_tac to_fmap_key_set + rw [] >> + CCONTR_TAC >> + fs [equiv_inj_def] >> + rfs [key_set_eq] >> + `cmp2 (f k'') (f k') ≠ Equal` by metis_tac [] + rfs [image_lem] + + fs [EXTENSION] + fs [PULL_EXISTS, PULL_FORALL] + + + rfs [bigunion_key_sets] + + fs [resp_equiv2_def, equiv_inj_def] + + rw [key_set_def] + fs [key_set_def] + CCONTR_TAC + Cases_on `cmp1 k' k'' = Equal` >> + fs [] + `cmp2 (f k') (f k'') ≠ Equal` by metis_tac [cmp_thms] +metis_tac [cmp_thms] + + Cases_on `ALOOKUP (MAP (λ(p1,p2). (key_set cmp2 (f p1),())) (toAscList t)) k = NONE` >> + fs [] + + Cases_on `?x. k = key_set cmp2 x` >> + fs [] + >- (Cases_on `?x'. x = f x'` >> + fs [] + >- (first_x_assum (qspecl_then [`key_set cmp1 x'`] mp_tac) >> + rw [] + + rw [] >> + + + fs [lift_key_def] + + Cases_on `FLOOKUP (MAP_KEYS (IMAGE f) (to_fmap cmp1 t)) k` + >- (fs [ALOOKUP_NONE, MEM_MAP, LAMBDA_PROD, EXISTS_PROD] >> + CCONTR_TAC >> + fs [] >> + rw [] >> + fs [lift_key_def, resp_equiv2_def, EXTENSION, LAMBDA_PROD,EXISTS_PROD, FORALL_PROD, + PULL_FORALL, PULL_EXISTS]>> + + fs [PULL_EXISTS, PULL_FORALL, key_set_def, EXTENSION] + + first_x_assum (qspecl_then [`key_set cmp1 p_1'`, `p_2`] assume_tac) >> + fs [FLOOKUP_DEF, MAP_KEYS_def] >> + fs [EXTENSION, key_set_def] >> + metis_tac [cmp_thms] + +val key_set_map = Q.prove ( +`!cmp1 cmp2 f k. + resp_equiv2 cmp1 cmp2 f ⇒ + IMAGE f (key_set cmp1 k) SUBSET key_set cmp2 (f k)`, + rw [key_set_def, SUBSET_DEF, resp_equiv2_def] >> + metis_tac []); + +`good_cmp cmp1 ∧ good_cmp cmp2 ∧ (!x y. cmp1 x y = Equal ⇒ x = y) /\ (!x y. cmp2 x y = Equal ⇒ x = y) ∧ (!x y. f x = f y ⇒ x = y) ⇒ resp_equiv2 cmp1 cmp2 f` + rw [resp_equiv2_def] >> + metis_tac [cmp_thms] + + +val flookup_lem = Q.prove ( +`!cmp1 cmp2 m k v f. + (FLOOKUP m k = + FLOOKUP (MAP_KEYS (BIGUNION o IMAGE (λx. key_set cmp2 (f x))) m) (BIGUNION o IMAGE (λx. key_set cmp2 (f k))))`, + + rw [FLOOKUP_DEF, MAP_KEYS_def] >> + eq_tac >> + rw [] + + +val map_keys_thm = Q.store_thm ("map_keys_thm", +`!cmp1 cmp2 f t. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ + invariant cmp1 t ∧ + resp_equiv2 cmp1 cmp2 f + ⇒ + invariant cmp2 (map_keys cmp2 f t) ∧ + to_fmap cmp2 (map_keys cmp2 f t) = MAP_KEYS (IMAGE f) (to_fmap cmp1 t)`, + + simp [map_keys_def] >> + rpt gen_tac >> + DISCH_TAC >> + inv_mp_tac fromList_thm >> + rw [MAP_MAP_o, combinTheory.o_DEF] >> + rw [LAMBDA_PROD] >> + rw [fmap_eq_flookup] >> + `SORTED (λ(x,y) (x',y'). cmp1 x x' = Less) (toAscList t) ∧ + lift_key cmp1 (set (toAscList t)) = set (fmap_to_alist (to_fmap cmp1 t))` + by metis_tac [toAscList_thm] >> + pop_assum mp_tac >> + simp [EXTENSION, MEM_MAP, LAMBDA_PROD, EXISTS_PROD, FORALL_PROD] >> + `transitive (λ(x,y:'c) (x',y':'c). cmp1 x x' = Less)` by metis_tac [good_cmp_trans] >> + rw [in_lift_key] >> + fs [] + + + fs [lift_key_def] + + Cases_on `FLOOKUP (MAP_KEYS (IMAGE f) (to_fmap cmp1 t)) k` + >- (rw [ALOOKUP_NONE, MEM_MAP, LAMBDA_PROD, EXISTS_PROD] >> + CCONTR_TAC >> + fs [] >> + rw [] >> + fs [lift_key_def, resp_equiv2_def, EXTENSION, LAMBDA_PROD,EXISTS_PROD, FORALL_PROD, + PULL_FORALL, PULL_EXISTS]>> + + fs [PULL_EXISTS, PULL_FORALL, key_set_def, EXTENSION] + + first_x_assum (qspecl_then [`key_set cmp1 p_1'`, `p_2`] assume_tac) >> + fs [FLOOKUP_DEF, MAP_KEYS_def] >> + fs [EXTENSION, key_set_def] >> + metis_tac [cmp_thms] + *) + +val every_def = Define ` +(every f Tip = T) ∧ +(every f (Bin _ kx x l r) = + if f kx x then + if every f l then + if every f r then T else F + else F + else F)`; + +val every_thm = Q.store_thm ("every_thm", +`!f t cmp. + good_cmp cmp ∧ + invariant cmp t ∧ + resp_equiv cmp f + ⇒ + (every f t ⇔ (!k v. lookup cmp k t = SOME v ⇒ f k v))`, + Induct_on `t` >> + rw [every_def, lookup_def] >> + fs [invariant_eq, resp_equiv_def] >> + first_x_assum (qspecl_then [`f`, `cmp`] assume_tac) >> + first_x_assum (qspecl_then [`f`, `cmp`] assume_tac) >> + rfs [] >> + eq_tac >> + rw [] + >- (EVERY_CASE_TAC >> + fs [] >> + metis_tac []) + >- (first_x_assum (qspecl_then [`k`] assume_tac) >> + rfs [] >> + EVERY_CASE_TAC >> + fs [] >> + metis_tac [cmp_thms]) + >- (first_x_assum (qspecl_then [`k'`] assume_tac) >> + EVERY_CASE_TAC >> + fs [] >> + rfs [lookup_thm, flookup_thm] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + imp_res_tac key_set_cmp_thm >> + metis_tac [cmp_thms]) + >- (first_x_assum (qspecl_then [`k'`] assume_tac) >> + EVERY_CASE_TAC >> + fs [] >> + rfs [lookup_thm, flookup_thm] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + imp_res_tac key_set_cmp_thm >> + metis_tac [cmp_thms])); + +val exists_def = Define ` +(exists f Tip = F) ∧ +(exists f (Bin _ kx x l r) = + if f kx x then + T + else if exists f l then + T + else if exists f r then + T + else + F)`; + +val exists_thm = Q.store_thm ("exists_thm", +`!f t cmp. + good_cmp cmp ∧ + invariant cmp t ∧ + resp_equiv cmp f + ⇒ + (exists f t ⇔ (?k v. lookup cmp k t = SOME v ∧ f k v))`, + Induct_on `t` >> + rw [exists_def, lookup_def] >> + fs [invariant_eq, resp_equiv_def] >> + first_x_assum (qspecl_then [`f`, `cmp`] assume_tac) >> + first_x_assum (qspecl_then [`f`, `cmp`] assume_tac) >> + rfs [] >> + eq_tac >> + rw [] + >- metis_tac [cmp_thms] + >- (qexists_tac `k'` >> + rw [] >> + EVERY_CASE_TAC >> + fs [] >> + rfs [lookup_thm, flookup_thm] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + imp_res_tac key_set_cmp_thm >> + metis_tac [cmp_thms]) + >- (qexists_tac `k'` >> + rw [] >> + EVERY_CASE_TAC >> + fs [] >> + rfs [lookup_thm, flookup_thm] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + imp_res_tac key_set_cmp_thm >> + metis_tac [cmp_thms]) + >- (EVERY_CASE_TAC >> + fs [] >> + metis_tac [])); + +val _ = export_theory (); diff --git a/examples/balanced_bst/comparisonScript.sml b/examples/balanced_bst/comparisonScript.sml new file mode 100644 index 0000000000..d563a2dd3c --- /dev/null +++ b/examples/balanced_bst/comparisonScript.sml @@ -0,0 +1,327 @@ +open HolKernel boolLib bossLib BasicProvers; +open optionTheory pairTheory stringTheory listTheory arithmeticTheory; +open lcsymtacs; + +val _ = new_theory "comparison"; + +val _ = temp_tight_equality (); +val every_case_tac = BasicProvers.EVERY_CASE_TAC; + +val _ = Datatype `comparison = Less | Greater | Equal`; + +val comparison_distinct = fetch "-" "comparison_distinct"; +val comparison_case_def = fetch "-" "comparison_case_def"; +val comparison_nchotomy = fetch "-" "comparison_nchotomy"; + +val good_cmp_def = Define ` +good_cmp cmp ⇔ + (!x. cmp x x = Equal) ∧ + (!x y. cmp x y = Equal ⇒ cmp y x = Equal) ∧ + (!x y. cmp x y = Greater ⇔ cmp y x = Less) ∧ + (!x y z. cmp x y = Equal ∧ cmp y z = Less ⇒ cmp x z = Less) ∧ + (!x y z. cmp x y = Less ∧ cmp y z = Equal ⇒ cmp x z = Less) ∧ + (!x y z. cmp x y = Equal ∧ cmp y z = Equal ⇒ cmp x z = Equal) ∧ + (!x y z. cmp x y = Less ∧ cmp y z = Less ⇒ cmp x z = Less)`; + +val good_cmp_thm = Q.store_thm ("good_cmp_thm", +`!cmp. + good_cmp cmp ⇔ + (!x. cmp x x = Equal) ∧ + (!x y z. + (cmp x y = Greater ⇔ cmp y x = Less) ∧ + (cmp x y = Less ∧ cmp y z = Equal ⇒ cmp x z = Less) ∧ + (cmp x y = Less ∧ cmp y z = Less ⇒ cmp x z = Less))`, + rw [good_cmp_def] >> + metis_tac [comparison_distinct, comparison_nchotomy]); + +val cmp_thms = save_thm ("cmp_thms", LIST_CONJ [comparison_distinct, comparison_case_def, comparison_nchotomy, good_cmp_def]) + +val option_cmp_def = Define ` +(option_cmp cmp NONE NONE = Equal) ∧ +(option_cmp cmp NONE (SOME x) = Less) ∧ +(option_cmp cmp (SOME x) NONE = Greater) ∧ +(option_cmp cmp (SOME x) (SOME y) = cmp x y)`; + +val option_cmp2_def = Define ` +(option_cmp2 cmp NONE NONE = Equal) ∧ +(option_cmp2 cmp NONE (SOME x) = Greater) ∧ +(option_cmp2 cmp (SOME x) NONE = Less) ∧ +(option_cmp2 cmp (SOME x) (SOME y) = cmp x y)`; + +val list_cmp_def = Define ` +(list_cmp cmp [] [] = Equal) ∧ +(list_cmp cmp [] (x::y) = Less) ∧ +(list_cmp cmp (x::y) [] = Greater) ∧ +(list_cmp cmp (x1::y1) (x2::y2) = + case cmp x1 x2 of + | Equal => list_cmp cmp y1 y2 + | Less => Less + | Greater => Greater)`; + +val list_cmp_ind = fetch "-" "list_cmp_ind"; + +val pair_cmp_def = Define ` +pair_cmp cmp1 cmp2 x y = + case cmp1 (FST x) (FST y) of + | Equal => cmp2 (SND x) (SND y) + | Less => Less + | Greater => Greater`; + +val bool_cmp_def = Define ` +(bool_cmp T T = Equal) ∧ +(bool_cmp F F = Equal) ∧ +(bool_cmp T F = Greater) ∧ +(bool_cmp F T = Less)`; + +val num_cmp_def = Define ` +num_cmp n1 n2 = + if n1 = n2 then + Equal + else if n1 < n2 then + Less + else + Greater`; + +val char_cmp_def = Define ` +char_cmp c1 c2 = num_cmp (ORD c1) (ORD c2)`; + +val string_cmp_def = Define ` +string_cmp = list_cmp char_cmp`; + +val option_cmp_good = Q.store_thm ("option_cmp_good", +`!cmp. good_cmp cmp ⇒ good_cmp (option_cmp cmp)`, + rw [good_cmp_def] >> + Cases_on `x` >> + TRY (Cases_on `y`) >> + TRY (Cases_on `z`) >> + metis_tac [option_cmp_def, comparison_distinct]); + +val option_cmp2_good = Q.store_thm ("option_cmp2_good", +`!cmp. good_cmp cmp ⇒ good_cmp (option_cmp2 cmp)`, + rw [good_cmp_def] >> + Cases_on `x` >> + TRY (Cases_on `y`) >> + TRY (Cases_on `z`) >> + metis_tac [option_cmp2_def, comparison_distinct]); + +val list_cmp_good = Q.store_thm ("list_cmp_good", +`!cmp. good_cmp cmp ⇒ good_cmp (list_cmp cmp)`, + simp [good_cmp_def] >> + rpt gen_tac >> + strip_tac >> + rpt conj_tac >> + Induct_on `x` >> + TRY (Cases_on `y`) >> + TRY (Cases_on `z`) >> + REWRITE_TAC [list_cmp_def] >> + rpt strip_tac >> + every_case_tac >> + metis_tac [list_cmp_def, comparison_distinct, comparison_case_def, comparison_nchotomy]); + +val pair_cmp_good = Q.store_thm ("pair_cmp_good", +`!cmp1 cmp2. good_cmp cmp1 ∧ good_cmp cmp2 ⇒ good_cmp (pair_cmp cmp1 cmp2)`, + simp [good_cmp_def] >> + rpt gen_tac >> + strip_tac >> + rpt conj_tac >> + TRY (Cases_on `x`) >> + TRY (Cases_on `y`) >> + TRY (Cases_on `z`) >> + REWRITE_TAC [pair_cmp_def] >> + rpt strip_tac >> + every_case_tac >> + metis_tac [pair_cmp_def, comparison_distinct, comparison_case_def, comparison_nchotomy]); + +val bool_cmp_good = Q.store_thm ("bool_cmp_good[simp]", +`good_cmp bool_cmp`, + simp [good_cmp_def] >> + rpt conj_tac >> + TRY (Cases_on `x`) >> + TRY (Cases_on `y`) >> + TRY (Cases_on `z`) >> + REWRITE_TAC [bool_cmp_def] >> + every_case_tac >> + fs []); + +val num_cmp_good = Q.store_thm ("num_cmp_good[simp]", +`good_cmp num_cmp`, + simp [good_cmp_def] >> + rpt conj_tac >> + TRY (Cases_on `x`) >> + TRY (Cases_on `y`) >> + TRY (Cases_on `z`) >> + REWRITE_TAC [num_cmp_def] >> + every_case_tac >> + full_simp_tac (srw_ss()++ARITH_ss) []); + +val char_cmp_good = Q.store_thm ("char_cmp_good[simp]", +`good_cmp char_cmp`, + simp [good_cmp_def] >> + rpt conj_tac >> + TRY (Cases_on `x`) >> + TRY (Cases_on `y`) >> + TRY (Cases_on `z`) >> + REWRITE_TAC [char_cmp_def, num_cmp_def] >> + every_case_tac >> + full_simp_tac (srw_ss()++ARITH_ss) []); + +val string_cmp_good = Q.store_thm ("string_cmp_good[simp]", +`good_cmp string_cmp`, + metis_tac [string_cmp_def, char_cmp_good, list_cmp_good]); + +val list_cmp_cong = Q.store_thm ("list_cmp_cong", +`!cmp l1 l2 cmp' l1' l2'. + (l1 = l1') ∧ + (l2 = l2') ∧ + (!x x'. MEM x l1' ∧ MEM x' l2' ⇒ cmp x x' = cmp' x x') + ⇒ + list_cmp cmp l1 l2 = list_cmp cmp' l1' l2'`, + ho_match_mp_tac list_cmp_ind >> + rw [list_cmp_def] >> + rw [list_cmp_def] >> + every_case_tac >> + rw []); + +val option_cmp_cong = Q.store_thm ("option_cmp_cong", +`!cmp v1 v2 cmp' v1' v2'. + (v1 = v1') ∧ + (v2 = v2') ∧ + (!x x'. v1' = SOME x ∧ v2' = SOME x' ⇒ cmp x x' = cmp' x x') + ⇒ + option_cmp cmp v1 v2 = option_cmp cmp' v1' v2'`, + ho_match_mp_tac (fetch "-" "option_cmp_ind") >> + rw [option_cmp_def] >> + rw [option_cmp_def]); + +val option_cmp2_cong = Q.store_thm ("option_cmp2_cong", +`!cmp v1 v2 cmp' v1' v2'. + (v1 = v1') ∧ + (v2 = v2') ∧ + (!x x'. v1' = SOME x ∧ v2' = SOME x' ⇒ cmp x x' = cmp' x x') + ⇒ + option_cmp2 cmp v1 v2 = option_cmp2 cmp' v1' v2'`, + ho_match_mp_tac (fetch "-" "option_cmp2_ind") >> + rw [option_cmp2_def] >> + rw [option_cmp2_def]); + +val pair_cmp_cong = Q.store_thm ("pair_cmp_cong", +`!cmp1 cmp2 v1 v2 cmp1' cmp2' v1' v2'. + (v1 = v1') ∧ + (v2 = v2') ∧ + (!a b c d. v1' = (a,b) ∧ v2' = (c,d) ⇒ cmp1 a c = cmp1' a c) ∧ + (!a b c d. v1' = (a,b) ∧ v2' = (c,d) ⇒ cmp2 b d = cmp2' b d) + ⇒ + pair_cmp cmp1 cmp2 v1 v2 = pair_cmp cmp1' cmp2' v1' v2'`, + rw [pair_cmp_def] >> + every_case_tac >> + Cases_on `v1` >> + Cases_on `v2` >> + fs []); + +val _ = DefnBase.export_cong "list_cmp_cong"; +val _ = DefnBase.export_cong "option_cmp_cong"; +val _ = DefnBase.export_cong "option_cmp2_cong"; +val _ = DefnBase.export_cong "pair_cmp_cong"; + +val good_cmp_trans = Q.store_thm ("good_cmp_trans", +`!cmp. good_cmp cmp ⇒ transitive (λ(k,v) (k',v'). cmp k k' = Less)`, + rw [relationTheory.transitive_def] >> + Cases_on `x` >> + Cases_on `y` >> + Cases_on `z` >> + fs [] >> + metis_tac [cmp_thms]); + +val bool_cmp_antisym = Q.store_thm ("bool_cmp_antisym[simp]", +`!x y. bool_cmp x y = Equal ⇔ x = y`, + rw [] >> + Cases_on `x` >> + Cases_on `y` >> + rw [bool_cmp_def]); + +val num_cmp_antisym = Q.store_thm ("num_cmp_antisym[simp]", +`!x y. num_cmp x y = Equal ⇔ x = y`, + rw [num_cmp_def]); + +val char_cmp_antisym = Q.store_thm ("char_cmp_antisym[simp]", +`!x y. char_cmp x y = Equal ⇔ x = y`, + rw [char_cmp_def, num_cmp_antisym] >> + rw [ORD_11]); + +val list_cmp_antisym = Q.store_thm ("list_cmp_antisym", +`!cmp x y. (!x y. cmp x y = Equal ⇔ x = y) ⇒ (list_cmp cmp x y = Equal ⇔ x = y)`, + ho_match_mp_tac list_cmp_ind >> + rw [list_cmp_def] >> + every_case_tac >> + rw [] >> + metis_tac [comparison_distinct]); + +val string_cmp_antisym = Q.store_thm ("string_cmp_antisym[simp]", +`!x y. string_cmp x y = Equal ⇔ x = y`, + metis_tac [string_cmp_def, char_cmp_antisym, list_cmp_antisym]); + +val pair_cmp_antisym = Q.store_thm ("pair_cmp_antisym", +`!cmp1 cmp2 x y. + (!x y. cmp1 x y = Equal ⇔ x = y) ∧ + (!x y. cmp2 x y = Equal ⇔ x = y) + ⇒ + (pair_cmp cmp1 cmp2 x y = Equal ⇔ x = y)`, + Cases_on `x` >> + Cases_on `y` >> + rw [pair_cmp_def] >> + every_case_tac >> + rw [] >> + metis_tac [comparison_distinct]); + +val option_cmp_antisym = Q.store_thm ("option_cmp_antisym", +`!cmp x y. + (!x y. cmp x y = Equal ⇔ x = y) + ⇒ + (option_cmp cmp x y = Equal ⇔ x = y)`, + Cases_on `x` >> + Cases_on `y` >> + rw [option_cmp_def] >> + every_case_tac >> + rw [] >> + metis_tac [comparison_distinct]); + +val option_cmp2_antisym = Q.store_thm ("option_cmp2_antisym", +`!cmp x y. + (!x y. cmp x y = Equal ⇔ x = y) + ⇒ + (option_cmp2 cmp x y = Equal ⇔ x = y)`, + Cases_on `x` >> + Cases_on `y` >> + rw [option_cmp2_def] >> + every_case_tac >> + rw [] >> + metis_tac [comparison_distinct]); + +val resp_equiv_def = Define ` +resp_equiv cmp f ⇔ !k1 k2 v. cmp k1 k2 = Equal ⇒ f k1 v = f k2 v`; + +val resp_equiv2_def = Define ` +resp_equiv2 cmp cmp2 f ⇔ (!k1 k2. cmp k1 k2 = Equal ⇒ cmp2 (f k1) (f k2) = Equal)`; + +val equiv_inj_def = Define ` +equiv_inj cmp cmp2 f ⇔ (!k1 k2. cmp2 (f k1) (f k2) = Equal ⇒ cmp k1 k2 = Equal)`; + +val antisym_resp_equiv = Q.store_thm ("antisym_resp_equiv", +`!cmp f. + (!x y. cmp x y = Equal ⇒ x = y) + ⇒ + resp_equiv cmp f ∧ !cmp2. good_cmp cmp2 ⇒ resp_equiv2 cmp cmp2 f`, + rw [resp_equiv_def, resp_equiv2_def] >> + metis_tac [cmp_thms]); + +val list_cmp_equal_list_rel = Q.store_thm ("list_cmp_equal_list_rel", +`!cmp l1 l2. + list_cmp cmp l1 l2 = Equal ⇔ LIST_REL (\x y. cmp x y = Equal) l1 l2`, + Induct_on `l1` >> + rw [] >> + Cases_on `l2` >> + fs [list_cmp_def] >> + every_case_tac >> + fs []); + +val _ = export_theory (); diff --git a/examples/balanced_bst/osetScript.sml b/examples/balanced_bst/osetScript.sml new file mode 100644 index 0000000000..e0f1c7a59e --- /dev/null +++ b/examples/balanced_bst/osetScript.sml @@ -0,0 +1,357 @@ +open HolKernel boolLib bossLib BasicProvers Parse; +open optionTheory pairTheory stringTheory; +open arithmeticTheory pred_setTheory listTheory finite_mapTheory alistTheory sortingTheory; +open balanced_mapTheory comparisonTheory; +open lcsymtacs; + +val _ = new_theory "oset"; + +val _ = temp_tight_equality (); + +(* oset for ordered set *) +val _ = type_abbrev ("oset", ``:('a,unit) balanced_map``); + +(* Basic definitions, that correspond directly to balanced tree operations *) +val good_oset_def = Define ` +good_oset cmp (s:'a oset) ⇔ good_cmp cmp ∧ invariant cmp s`; + +val oempty_def = Define ` +oempty = empty:'a oset`; + +val osingleton_def = Define ` +osingleton v = singleton v ()`; + +val oin_def = Define ` +oin cmp (v:'a) (s:'a oset) ⇔ member cmp v s`; + +val oinsert_def = Define ` +oinsert cmp v s = insert cmp v () s`; + +val odelete_def = Define ` +odelete cmp (s:'a oset) (v:'a) = delete cmp v s`; + +val ounion_def = Define ` +ounion cmp (s1:'a oset) s2 = union cmp s1 s2`; + +val oimage_def = Define ` +oimage cmp f (s:'a oset) = map_keys cmp f s`; + +val osubset_def = Define ` +osubset cmp (s1:'a oset) (s2:'a oset) ⇔ isSubmapOf cmp s1 s2`; + +val ocompare_def = Define ` +ocompare cmp (s1:'a oset) (s2:'a oset) = compare cmp (\x y. Equal) s1 s2`; + +val oevery_def = Define ` +oevery f (s:'a oset) ⇔ every (\x y. f x) s`; + +val oexists_def = Define ` +oexists f (s:'a oset) ⇔ exists (\x y. f x) s`; + +val oset_def = Define ` +oset cmp l = FOLDR (λx t. oinsert cmp x t) oempty l`; + +val oresp_equiv_def = Define ` +oresp_equiv cmp f = resp_equiv cmp (λx y:unit. f x)`; + +(* operations preserve good_set *) + +val good_oset_oempty = Q.store_thm ("good_oset_oempty", +`!cmp. good_cmp cmp ⇒ good_oset cmp oempty`, + rw [empty_thm, good_oset_def, oempty_def]); + +val good_oset_osingleton = Q.store_thm ("good_oset_osingleton", +`!cmp x. good_cmp cmp ⇒ good_oset cmp (osingleton x)`, + rw [singleton_thm, good_oset_def, osingleton_def]); + +val good_oset_oinsert = Q.store_thm ("good_oset_oinsert", +`!cmp s x. good_oset cmp s ⇒ good_oset cmp (oinsert cmp x s)`, + rw [oinsert_def, good_oset_def] >> + metis_tac [insert_thm]); + +val good_oset_odelete = Q.store_thm ("good_oset_odelete", +`!cmp s x. good_oset cmp s ⇒ good_oset cmp (odelete cmp s x)`, + rw [good_oset_def, odelete_def] >> + metis_tac [delete_thm]); + +val good_oset_ounion = Q.store_thm ("good_oset_ounion", +`!cmp s1 s2. good_oset cmp s1 ∧ good_oset cmp s2 ⇒ good_oset cmp (ounion cmp s1 s2)`, + rw [good_oset_def, ounion_def] >> + metis_tac [union_thm]); + +(* +val good_oset_oimage = Q.store_thm ("good_oset_oimage", +`!cmp f s. good_cmp cmp ⇒ good_oset cmp (oimage cmp f s)`, + cheat); + *) + +val good_cmp_ocompare = Q.store_thm ("good_cmp_ocompare", +`!cmp f s. good_cmp cmp ⇒ good_cmp (ocompare cmp)`, + rw [] >> + `good_cmp (\(x:unit) (y:unit). Equal)` + by (rw [good_cmp_def, LAMBDA_PROD, FORALL_PROD] >> + metis_tac [good_cmp_def]) >> + imp_res_tac compare_good_cmp >> + rw [ocompare_def, good_cmp_def] >> + metis_tac [good_cmp_def]); + +val good_oset_oset_help = Q.prove ( +`!cmp s l. good_oset cmp s ⇒ good_oset cmp (FOLDR (λx t. oinsert cmp x t) s l)`, + Induct_on `l` >> + rw [] >> + match_mp_tac good_oset_oinsert >> + metis_tac []); + +val good_oset_oset = Q.store_thm ("good_oset_oset", +`!cmp l. good_cmp cmp ⇒ good_oset cmp (oset cmp l)`, + rw [oset_def] >> + metis_tac [good_oset_oset_help, good_oset_oempty]); + +(* oempty theorems *) + +val oin_oempty = Q.store_thm ("oin_oinsert[simp]", +`!cmp x. oin cmp x oempty = F`, + rw [oin_def, oempty_def, empty_def, member_def]); + +val oimage_oempty = Q.store_thm ("oimage_oempty[simp]", +`!cmp f. oimage cmp f oempty = oempty`, + rw [oimage_def, oempty_def, map_keys_def, empty_def, fromList_def, + toAscList_def, foldrWithKey_def]); + +val oinsert_oempty = Q.store_thm ("oinsert_oempty[simp]", +`!cmp x. oinsert cmp x oempty = osingleton x`, + rw [oinsert_def, oempty_def, osingleton_def, insert_def, empty_def, singleton_def]); + +val odelete_oempty = Q.store_thm ("odelete_oempty[simp]", +`!cmp x. odelete cmp oempty x = oempty`, + rw [odelete_def, oempty_def, delete_def, empty_def]); + +val ounion_oempty = Q.store_thm ("ounion_oempty[simp]", +`!cmp s. ounion cmp oempty s = s ∧ ounion cmp s oempty = s`, + rw [ounion_def, oempty_def, union_def, empty_def] >> + Cases_on `s` >> + rw [union_def]); + +val oempty_subset = Q.store_thm ("oempty_subset[simp]", +`!cmp s. (osubset cmp oempty s ⇔ T) ∧ (osubset cmp s oempty ⇔ s = oempty)`, + rw [osubset_def, oempty_def, isSubmapOf_def, isSubmapOfBy_def, empty_def, + submap'_def, size_def] >> + Cases_on `s` >> + rw [submap'_def, size_def]); + +val oevery_oempty = Q.store_thm ("oevery_oempty[simp]", +`!f. oevery f oempty = T`, + rw [oevery_def, oempty_def, every_def, empty_def]); + +val oexists_oempty = Q.store_thm ("oexists_oempty[simp]", +`!f. oexists f oempty = F`, + rw [oexists_def, oempty_def, exists_def, empty_def]); + +val oset_empty = Q.store_thm ("oset_empty[simp]", +`!cmp. oset cmp [] = oempty`, + rw [oset_def, oempty_def]); + +(* singleton theorems *) + +val oin_singleton = Q.store_thm ("oin_singleton[simp]", +`∀cmp x y. oin cmp x (osingleton y) ⇔ cmp x y = Equal`, + rw [oin_def, osingleton_def, member_def, singleton_def] >> + EVERY_CASE_TAC); + +val oimage_osingleton = Q.store_thm ("oimage_osingleton[simp]", +`!cmp f x. oimage cmp f (osingleton x) = osingleton (f x)`, + rw [oimage_def, osingleton_def, map_keys_def, singleton_def, fromList_def, + toAscList_def, foldrWithKey_def, empty_def, insert_def]); + +val odelete_osingleton = Q.store_thm ("odelete_osingleton[simp]", +`!cmp x y. good_cmp cmp ⇒ odelete cmp (osingleton x) y = if cmp x y = Equal then oempty else osingleton x`, + rw [odelete_def, oempty_def, delete_def, empty_def, singleton_def, osingleton_def] >> + EVERY_CASE_TAC >> + rw [balanceR_def, balanceL_def, glue_def] >> + metis_tac [cmp_thms]); + +val oevery_osingleton = Q.store_thm ("oevery_osingleton[simp]", +`!f x. oevery f (osingleton x) = f x`, + rw [oevery_def, osingleton_def, every_def, singleton_def]); + +val oexists_osingleton = Q.store_thm ("oexists_osingleton[simp]", +`!f x. oexists f (osingleton x) = f x`, + rw [oexists_def, osingleton_def, exists_def, singleton_def]); + +val oset_singleton = Q.store_thm ("oset_singleton[simp]", +`!cmp x. oset cmp [x] = osingleton x`, + rw [oset_def, osingleton_def]); + +(* How oin interacts with other operations *) + +val oin_oinsert = Q.store_thm ("oin_oinsert", +`∀cmp x y s. good_oset cmp s ⇒ (oin cmp x (oinsert cmp y s) ⇔ cmp x y = Equal ∨ oin cmp x s)`, + rw [good_oset_def, oin_def, oinsert_def] >> + imp_res_tac insert_thm >> + last_x_assum (qspecl_then [`()`, `y`] assume_tac) >> + imp_res_tac member_thm >> + rw [FLOOKUP_UPDATE] >> + rfs [key_set_eq] >> + metis_tac [good_cmp_def]); + +val oin_odelete = Q.store_thm ("oin_odelete", +`!cmp s x y. good_oset cmp s ⇒ (oin cmp x (odelete cmp s y) ⇔ oin cmp x s ∧ cmp x y ≠ Equal)`, + rw [oin_def, odelete_def] >> + imp_res_tac good_oset_odelete >> + pop_assum (qspecl_then [`y`] assume_tac) >> + fs [good_oset_def, odelete_def] >> + imp_res_tac delete_thm >> + imp_res_tac member_thm >> + rw [FDOM_DRESTRICT, key_set_eq] >> + eq_tac >> + rw []); + +val oin_ounion = Q.store_thm ("oin_ounion", +`!cmp x s1 s2. good_oset cmp s1 ∧ good_oset cmp s2 ⇒ (oin cmp x (ounion cmp s1 s2) ⇔ oin cmp x s1 ∨ oin cmp x s2)`, + rw [oin_def] >> + `good_oset cmp (ounion cmp s1 s2)` by metis_tac [good_oset_ounion] >> + fs [good_oset_def, ounion_def] >> + imp_res_tac member_thm >> + rw [] >> + `to_fmap cmp (union cmp s1 s2) = to_fmap cmp s1 ⊌ to_fmap cmp s2` by metis_tac [union_thm] >> + rw []); + +(* +val oin_oimage = Q.store_thm ("oin_oimage", +`!cmp y s f. good_cmp cmp ⇒ (oin cmp y (oimage cmp f s) ⇔ ?x. cmp y (f x) = Equal ∧ oin cmp x s)`, + cheat); + *) + +val osubset_thm = Q.store_thm ("osubset_thm", +`!cmp s1 s2. good_oset cmp s1 ∧ good_oset cmp s2 ⇒ (osubset cmp s1 s2 ⇔ (!x. oin cmp x s1 ⇒ oin cmp x s2))`, + rw [osubset_def, good_oset_def, isSubmapOf_thm, oin_def] >> + rw [member_thm, lookup_thm, FLOOKUP_DEF] >> + eq_tac >> + rw []); + +val oextension = Q.store_thm ("oextension", +`!cmp s1 s2. + good_oset cmp s1 ∧ good_oset cmp s2 + ⇒ + (ocompare cmp s1 s2 = Equal ⇔ (!x. oin cmp x s1 ⇔ oin cmp x s2))`, + rw [good_oset_def, ocompare_def] >> + `good_cmp (\(x:unit) (y:unit). Equal)` + by (rw [good_cmp_def, LAMBDA_PROD, FORALL_PROD] >> + metis_tac [good_cmp_def]) >> + rw [compare_thm] >> + rw [oin_def, member_thm, fmap_rel_OPTREL_FLOOKUP, OPTREL_def, FLOOKUP_DEF] >> + eq_tac >> + rw [] + >- metis_tac [] >> + CCONTR_TAC >> + fs [] >> + imp_res_tac to_fmap_key_set >> + fs [] >> + metis_tac []); + +val oevery_oin = Q.store_thm ("oevery_oin", +`!cmp f s. + good_oset cmp s ∧ + oresp_equiv cmp f + ⇒ + (oevery f s ⇔ (!x. oin cmp x s ⇒ f x))`, + rw [good_oset_def, oevery_def, oin_def, oresp_equiv_def] >> + imp_res_tac every_thm >> + rw [lookup_thm, flookup_thm, member_thm]); + +val oexists_oin = Q.store_thm ("oexists_oin", +`!cmp f s. + good_oset cmp s ∧ + oresp_equiv cmp f + ⇒ + (oexists f s ⇔ (?x. oin cmp x s ∧ f x))`, + rw [oresp_equiv_def, good_oset_def, oexists_def, oin_def] >> + imp_res_tac exists_thm >> + rw [lookup_thm, flookup_thm, member_thm]); + +val oin_oset_help = Q.prove ( +`!cmp l x s. + good_oset cmp s + ⇒ + (oin cmp x (FOLDR (λx t. oinsert cmp x t) s l) + ⇔ + oin cmp x s ∨ ?y. MEM y l ∧ cmp x y = Equal)`, + Induct_on `l` >> + rw [] >> + imp_res_tac good_oset_oset_help >> + rw [oin_oinsert] >> + eq_tac >> + rw [] >> + res_tac >> + fs [] >> + metis_tac []); + +val oin_oset = Q.store_thm ("oin_oset", +`!cmp l x. good_cmp cmp ⇒ (oin cmp x (oset cmp l) ⇔ ?y. MEM y l ∧ cmp x y = Equal)`, + rw [oset_def] >> + metis_tac [oin_oset_help, good_oset_oempty, oin_oempty]); + +(* Theorems about oevery and oexists *) + +val oevery_oinsert = Q.store_thm ("oevery_oinsert", +`!f cmp x s. + good_oset cmp s ∧ + oresp_equiv cmp f + ⇒ + (oevery f (oinsert cmp x s) ⇔ f x ∧ oevery f s)`, + rw [] >> + `good_oset cmp (oinsert cmp x s)` by metis_tac [good_oset_oinsert] >> + imp_res_tac oevery_oin >> + rw [oin_oinsert] >> + eq_tac >> + rw [] >> + fs [oresp_equiv_def, resp_equiv_def] >> + metis_tac [good_oset_def, cmp_thms]); + +val oexists_oinsert = Q.store_thm ("oexists_oinsert", +`!f cmp x s. + good_oset cmp s ∧ + oresp_equiv cmp f + ⇒ + (oexists f (oinsert cmp x s) ⇔ f x ∨ oexists f s)`, + rw [] >> + `good_oset cmp (oinsert cmp x s)` by metis_tac [good_oset_oinsert] >> + imp_res_tac oexists_oin >> + rw [oin_oinsert] >> + eq_tac >> + rw [] >> + fs [oresp_equiv_def, resp_equiv_def] >> + metis_tac [good_oset_def, cmp_thms]); + +val oevery_ounion = Q.store_thm ("oevery_ounion", +`!f cmp s1 s2. + good_oset cmp s1 ∧ + good_oset cmp s2 ∧ + oresp_equiv cmp f + ⇒ + (oevery f (ounion cmp s1 s2) ⇔ oevery f s1 ∧ oevery f s2)`, + rw [] >> + `good_oset cmp (ounion cmp s1 s2)` by metis_tac [good_oset_ounion] >> + imp_res_tac oevery_oin >> + rw [oin_ounion] >> + eq_tac >> + rw [] >> + fs [oresp_equiv_def, resp_equiv_def]); + +val oexists_ounion = Q.store_thm ("oexists_ounion", +`!f cmp s1 s2. + good_oset cmp s1 ∧ + good_oset cmp s2 ∧ + oresp_equiv cmp f + ⇒ + (oexists f (ounion cmp s1 s2) ⇔ oexists f s1 ∨ oexists f s2)`, + rw [] >> + `good_oset cmp (ounion cmp s1 s2)` by metis_tac [good_oset_ounion] >> + imp_res_tac oexists_oin >> + rw [oin_ounion] >> + eq_tac >> + rw [] >> + fs [oresp_equiv_def, resp_equiv_def] >> + metis_tac []); + +val _ = export_theory (); From 621c1ebba0c90a304da4668cebce92f8b5c49dc1 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Sat, 13 Dec 2014 18:34:09 +1100 Subject: [PATCH 050/718] VALIDATE and VALIDATE_LT If tac (ltac) is invalid due to proving theorems with extra assumptions, VALIDATE tac and VALIDATE_LT ltac make the tactic valid by returning extra subgoals to prove the extra assumptions --- help/Docfiles/Tactical.VALID.doc | 9 +- help/Docfiles/Tactical.VALIDATE.doc | 102 +++++++++++++++++++++++ help/Docfiles/Tactical.VALIDATE_LT.doc | 92 ++++++++++++++++++++ help/Docfiles/Tactical.VALID_LT.doc | 8 +- help/Docfiles/proofManagerLib.expand.doc | 30 ++++++- src/1/Tactical.sig | 2 + src/1/Tactical.sml | 68 +++++++++++++++ 7 files changed, 301 insertions(+), 10 deletions(-) create mode 100644 help/Docfiles/Tactical.VALIDATE.doc create mode 100644 help/Docfiles/Tactical.VALIDATE_LT.doc diff --git a/help/Docfiles/Tactical.VALID.doc b/help/Docfiles/Tactical.VALID.doc index 0c80870e51..946122cf58 100644 --- a/help/Docfiles/Tactical.VALID.doc +++ b/help/Docfiles/Tactical.VALID.doc @@ -10,14 +10,13 @@ If {tac} applied to the goal {(asl,g)} produces a justification that does not create a theorem {A |- g}, with {A} a subset of {asl}, then {VALID tac (asl,g)} fails (raises an exception). If {tac} produces a valid proof on the goal, then the behaviour of {VALID tac (asl,g)} is -the same +the same as {tac (asl,g)} \FAILURE -Fails by design if its argument produces an invalid proof when applied -to a goal. Also fails if its argument fails when applied to the given -proof. +Fails by design if {tac} produces an invalid proof when applied +to a goal. Also fails if {tac} fails when applied to the given goal. \SEEALSO -proofManagerLib.expand. +proofManagerLib.expand, Tactical.VALIDATE. \ENDDOC diff --git a/help/Docfiles/Tactical.VALIDATE.doc b/help/Docfiles/Tactical.VALIDATE.doc new file mode 100644 index 0000000000..6b677d84ae --- /dev/null +++ b/help/Docfiles/Tactical.VALIDATE.doc @@ -0,0 +1,102 @@ +\DOC VALIDATE + +\TYPE {VALIDATE : tactic -> tactic} + +\SYNOPSIS +Makes a tactic valid if its invalidity is due to relying on assumptions not +present in the goal. + +\DESCRIBE +Suppose {tac} applied to the goal {(asl,g)} produces a justification that +creates a theorem {A |- g'}. +If {A} a not a subset of {asl}, then the tactic is invalid +(and {VALID tac (asl,g)} fails, ie, raises an exception). +But {VALIDATE tac (asl,g)} produces a subgoal list augmented by the +members of {asl} missing from {A}. + +If {g'} differs from {g}, both {VALID tac (asl,g)} and {VALIDATE tac (asl,g)} +fail. + +\FAILURE +Fails by design if {tac}, when applied to a goal, +produces a proof which is invalid on account of proving +a theorem whose conclusion differs from that of the goal. + +Also fails if {tac} fails when applied to the given goal. + +\EXAMPLE +For example, where theorem {uth'} is {[p'] |- q} + +{ +1 subgoal: +val it = + +q +------------------------------------ + p +: + proof + +> e (ACCEPT_TAC uth') ; +OK.. + +Exception raised at Tactical.VALID: +Invalid tactic [...] + +> e (VALIDATE (ACCEPT_TAC uth')) ; +OK.. +1 subgoal: +val it = + +p' +------------------------------------ + p +: + proof +} + +Given a goal with an implication in the assumptions, +one can split it into two subgoals. +{ +1 subgoal: +val it = + +r +------------------------------------ + p ==> q +: + proof + +> e (VALIDATE (POP_ASSUM (ASSUME_TAC o UNDISCH))) ; + +OK.. +2 subgoals: +val it = + +r +------------------------------------ + q + +p +------------------------------------ + p ==> q + +2 subgoals +: + proof +} +Meanwhile, to propose a term, prove it as a subgoal and then use it to prove +the goal, as is done using {SUBGOAL_THEN tm ASSUME_TAC}, +can also be done by {VALIDATE (ASSUME_TAC (ASSUME tm)))} + + +\USES +Where a tactic {tac} requires certain assumptions to be present in the goal, +which are not present but are capable of being proved, +{VALIDATE tac} will conveniently set up new subgoals to prove the missing +assumptions. + +\SEEALSO +proofManagerLib.expand, Tactical.VALID, Tactical.SUBGOAL_THEN. + +\ENDDOC diff --git a/help/Docfiles/Tactical.VALIDATE_LT.doc b/help/Docfiles/Tactical.VALIDATE_LT.doc new file mode 100644 index 0000000000..3995a59f2b --- /dev/null +++ b/help/Docfiles/Tactical.VALIDATE_LT.doc @@ -0,0 +1,92 @@ +\DOC VALIDATE_LT + +\TYPE {VALIDATE_LT : list_tactic -> list_tactic} + +\SYNOPSIS +Makes a list-tactic valid if its invalidity is due to relying on assumptions +not present in one of the goals. + +\DESCRIBE +When list-tactic {ltac} is applied to a goal list {gl} +it produces a new goal list {gl'} and a justification. +When the justification is applied to a list {thl'} of theorems +which are the new goals {gl'}, proved, it should produce a list {thl} +of theorems which are the goals {gl}, proved. + +A list-tactic can be invalid due to proving +a theorem whose conclusion differs from that of the corresponding goal, +or due to proving a theorem which contains extra assumptions relative to the +corresponding goal. +In this latter case, {VALIDATE_LT ltac} makes the list-tactic valid +by returning extra subgoals to prove those extra assumptions. + +See {VALID_LT} for more details. + +\FAILURE +Fails by design if {ltac}, when applied to a goal list, +produces a proof which is invalid on account of proving +a theorem whose conclusion differs from that of the corresponding goal. + +Also fails if {ltac} fails when applied to the given goals. + +\EXAMPLE +Where {uthr'} is {[p', q] |- r} and {uths'} is {[p, q'] |- s} + +{ +2 subgoals: +val it = + +s +------------------------------------ + 0. p + 1. q + +r +------------------------------------ + 0. p + 1. q + +2 subgoals +: + proof + +> elt (ALLGOALS (FIRST (map ACCEPT_TAC [uthr', uths']))) ; +OK.. + +Exception raised at Tactical.VALID_LT: +Invalid list-tactic [...] + +> elt (VALIDATE_LT (ALLGOALS (FIRST (map ACCEPT_TAC [uthr', uths'])))) ; +OK.. +2 subgoals: +val it = + +q' +------------------------------------ + 0. p + 1. q + +p' +------------------------------------ + 0. p + 1. q + +2 subgoals +: + proof +} + +\USES +Where a tactic {ltac} requires certain assumptions to be present in +one of the goals, +which are not present but are capable of being proved, +{VALIDATE_LT ltac} will conveniently set up new subgoals to prove the missing +assumptions. + +\SEEALSO +Tactical.VALID, Tactical.VALID_LT, Tactical.VALIDATE, +proofManagerLib.elt, proofManagerLib.expand_list. + +\ENDDOC + + diff --git a/help/Docfiles/Tactical.VALID_LT.doc b/help/Docfiles/Tactical.VALID_LT.doc index fef1355eb9..d03d5dd517 100644 --- a/help/Docfiles/Tactical.VALID_LT.doc +++ b/help/Docfiles/Tactical.VALID_LT.doc @@ -1,13 +1,13 @@ \DOC VALID_LT -\TYPE {VALID_LT : tactic -> tactic} +\TYPE {VALID_LT : list_tactic -> list_tactic} \SYNOPSIS Makes a list-tactic fail if it would otherwise return an invalid proof. \DESCRIBE When list-tactic {ltac} is applied to a goal list {gl} -it produces new goal list {gl'} and a justification. +it produces a new goal list {gl'} and a justification. When the justification is applied to a list {thl'} of theorems which are the new goals {gl'}, proved, it should produce a list {thl} of theorems which are the goals {gl}, proved. @@ -24,8 +24,8 @@ justification which do not prove the given goals {gl}. Also fails if its {ltac gl} fails. \SEEALSO -Tactical.VALID, -proofManagerLib.expand_list. +Tactical.VALID, Tactical.VALIDATE_LT, +proofManagerLib.elt, proofManagerLib.expand_list. \ENDDOC diff --git a/help/Docfiles/proofManagerLib.expand.doc b/help/Docfiles/proofManagerLib.expand.doc index 75348bf08b..eb029f4ed0 100644 --- a/help/Docfiles/proofManagerLib.expand.doc +++ b/help/Docfiles/proofManagerLib.expand.doc @@ -111,6 +111,33 @@ Invalid tactic ! HOL_ERR } +Note that an invalid tactic may "succeed". +Thus, where {tac1} is invalid, and {tac2} is valid (and both succeed), +{FIRST [tac1, tac2]} is invalid. For example, where +theorem {uth} is {[p] |- q} and {uth'} is {[p'] |- q} + +{ +1 subgoal: +val it = + +q +------------------------------------ + p +: + proof + +> e (FIRST (map ACCEPT_TAC [uth', uth])) ; +OK.. + +Exception raised at Tactical.VALID: +Invalid tactic [...] + +> e (FIRST (map (VALID o ACCEPT_TAC) [uth', uth])) ; +OK.. + +Goal proved. + [p] |- q +} \USES Doing a step in an interactive goal-directed proof. @@ -119,6 +146,7 @@ Doing a step in an interactive goal-directed proof. proofManagerLib.set_goal, proofManagerLib.restart, proofManagerLib.backup,proofManagerLib.restore, proofManagerLib.save, proofManagerLib.set_backup,proofManagerLib.expand, proofManagerLib.expandf, -proofManagerLib.p,proofManagerLib.top_thm, proofManagerLib.top_goal. +proofManagerLib.p,proofManagerLib.top_thm, proofManagerLib.top_goal, +Tactical.VALID, Tactical.VALIDATE \ENDDOC diff --git a/src/1/Tactical.sig b/src/1/Tactical.sig index 8abd823372..9f06979f99 100644 --- a/src/1/Tactical.sig +++ b/src/1/Tactical.sig @@ -39,6 +39,8 @@ sig val REPEAT_LT : list_tactic -> list_tactic val VALID : tactic -> tactic val VALID_LT : list_tactic -> list_tactic + val VALIDATE : tactic -> tactic + val VALIDATE_LT : list_tactic -> list_tactic val EVERY : tactic list -> tactic val FIRST : tactic list -> tactic val MAP_EVERY : ('a -> tactic) -> 'a list -> tactic diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index 0217fd5358..71639fa120 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -367,6 +367,74 @@ in end end +(*--------------------------------------------------------------------------- + * Tacticals to include proofs of necessary hypotheses for an invalid + * tactic or list_tactic valid. + * + * VALIDATE tac + * + * is the same as "tac", except that where "tac" returns a proof which is + * because if proves a theorem with extra hypotheses, it returns those + * hypotheses as extra goals + * + * VALIDATE_LT ltac + * + * is the same as "ltac", except it will return extra goals where this is + * necessary to make a valid list-tactic + *---------------------------------------------------------------------------*) +local val validity_tag = "ValidityCheck" + fun masquerade goal = Thm.mk_oracle_thm validity_tag goal ; + fun achieves_concl th (asl, w) = Term.aconv (concl th) w ; + fun hyps_not_in_goal th (asl, w) = + Lib.filter (fn h => not (Lib.exists (aconv h) asl)) (hyp th) ; + fun extra_goals_tbp th (asl, w) = + List.map (fn eg => (asl, eg)) (hyps_not_in_goal th (asl, w)) ; +in +fun VALIDATE (tac : tactic) (g as (asl, w) : goal) = + let val (glist, prf) = tac g ; + (* pretend new goals are theorems, and apply validation to them *) + val thprf = (prf (map masquerade glist)) ; + val _ = if achieves_concl thprf g then () + else raise ERR "VALIDATE" "Invalid tactic - wrong conclusion" ; + val extra_goals = extra_goals_tbp thprf g ; + val nextra = length extra_goals ; + (* new validation: apply the theorems proving the additional goals to + eliminate the extra hyps in the theorem proved by the given validation *) + fun eprf ethlist = + let val (extra_thms, thlist) = split_after nextra ethlist ; + in itlist PROVE_HYP extra_thms (prf thlist) end ; + in (extra_goals @ glist, eprf) end ; + +(* split_lists : int list -> 'a list -> 'a list list * 'a list *) +fun split_lists (n :: ns) ths = + let val (nths, rest) = split_after n ths ; + val (nsths, left) = split_lists ns rest ; + in (nths :: nsths, left) end + | split_lists [] ths = ([], ths) ; + +(* VALIDATE_LT : list_tactic -> list_tactic *) +fun VALIDATE_LT (ltac : list_tactic) (gl : goal list) = + let val (glist, prf) = ltac gl ; + (* pretend new goals are theorems, and apply validation to them *) + val thsprf = (prf (map masquerade glist)) ; + val _ = if Lib.all2 achieves_concl thsprf gl then () + else raise ERR "VALIDATE_LT" + "Invalid list-tactic - some wrong conclusion" ; + val extra_goal_lists = Lib.map2 extra_goals_tbp thsprf gl ; + val nextras = map length extra_goal_lists ; + (* new validation: apply the theorems proving the additional goals to + eliminate the extra hyps in the theorems proved by the given validation *) + fun eprf ethlist = + let val (extra_thm_lists, thlist) = split_lists nextras ethlist ; + in Lib.map2 (itlist PROVE_HYP) extra_thm_lists (prf thlist) end ; + in (List.concat extra_goal_lists @ glist, eprf) end ; + +end; + +(* could avoid duplication of code in the above by the following +fun VALIDATE tac = ALL_TAC THEN_LT VALIDATE_LT (TACS_TO_LT [tac]) ; +*) + (*--------------------------------------------------------------------------- * Provide a function (tactic) with the current assumption list. *---------------------------------------------------------------------------*) From cbc3e6a385b71f545c12d5fb4b673f03bb0d34ab Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Mon, 15 Dec 2014 15:01:57 +1100 Subject: [PATCH 051/718] Add balanced_bst to build sequence at selftest level 2. --- tools/sequences/large-theories | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/sequences/large-theories b/tools/sequences/large-theories index 25a4b2f8db..2beb78d157 100644 --- a/tools/sequences/large-theories +++ b/tools/sequences/large-theories @@ -20,6 +20,7 @@ src/opentheory !!examples/lambda/typing !!examples/computability/lambda !!examples/computability/register +!!examples/balanced_bst src/Boolify/src src/float [poly]src/floating-point From afb42a28b3ddf7f1f14b80c9137e322b327f0f44 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Mon, 15 Dec 2014 15:03:20 +1100 Subject: [PATCH 052/718] Add deep_matches to build sequence at level 1. --- tools/sequences/large-theories | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/sequences/large-theories b/tools/sequences/large-theories index 2beb78d157..de56034a17 100644 --- a/tools/sequences/large-theories +++ b/tools/sequences/large-theories @@ -21,6 +21,7 @@ src/opentheory !!examples/computability/lambda !!examples/computability/register !!examples/balanced_bst +!examples/deep_matches src/Boolify/src src/float [poly]src/floating-point From 137c5ca931f1123c3b8033f68ba09ceaad0099c2 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Mon, 15 Dec 2014 15:13:40 +1100 Subject: [PATCH 053/718] Mention balanced_bst example in release notes. --- doc/next-release.md | 47 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 doc/next-release.md diff --git a/doc/next-release.md b/doc/next-release.md new file mode 100644 index 0000000000..462769728c --- /dev/null +++ b/doc/next-release.md @@ -0,0 +1,47 @@ +% Release notes for HOL4, ?????? + + + + +(Released: ??????) + +We are pleased to announce the ?????? release of HOL 4. + +Contents +-------- + +- [New features](#new-features) +- [Bugs fixed](#bugs-fixed) +- [New theories](#new-theories) +- [New tools](#new-tools) +- [Examples](#examples) +- [Incompatibilities](#incompatibilities) + +New features: +------------- + +Bugs fixed: +----------- + +New theories: +------------- + +New tools: +---------- + +New examples: +--------- + +- A theory of balanced binary trees (`examples/balanced_bst`), based on Haskell code by Leijen and Palamarchuk, and mechanised by Scott Owens. The type supports operations such as `insert`, `union`, `delete`, filters and folds. Operations are parameterised by comparison operators for comparing keys. Balanced trees can themselves be compared. + +Incompatibilities: +------------------ + +* * * * * + + From ab1ace449a8a4fb2f251eb135e8e7af7a35ef753 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Tue, 16 Dec 2014 09:43:25 +1100 Subject: [PATCH 054/718] Remove trailing whitespace in examples/deep_matches/constrFamiliesLib.sml --- examples/deep_matches/constrFamiliesLib.sml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/examples/deep_matches/constrFamiliesLib.sml b/examples/deep_matches/constrFamiliesLib.sml index bcf87776ef..297925fe21 100644 --- a/examples/deep_matches/constrFamiliesLib.sml +++ b/examples/deep_matches/constrFamiliesLib.sml @@ -3,8 +3,8 @@ struct open Abbrev -(* Contructor families are lists of constructors. - Constructors are functions that are injective and +(* Contructor families are lists of constructors. + Constructors are functions that are injective and pairwise distinct. Moreover, a case-expansion theorem needs to be provided. Let's assume we have a datatype t with @@ -60,7 +60,7 @@ fun gen_case_expand_thm case_def_thm nchotomy_thm = let val t_lhs = mk_comb (ff_tm, a) val t = list_mk_forall([ff_tm, a], mk_eq (t_lhs, t_rhs)) - val res_thm = prove (t, + val res_thm = prove (t, REPEAT GEN_TAC THEN MP_TAC (ISPEC a nchotomy_thm) THEN SIMP_TAC std_ss [DISJ_IMP_THM, case_def_thm, @@ -69,7 +69,7 @@ in res_thm end -fun get_case_expand_thm (v, _) = let +fun get_case_expand_thm (v, _) = let val ty = type_of v val case_def_thm = TypeBase.case_def_of ty val nchotomy_thm = TypeBase.nchotomy_of ty From a40ca685e9b657cf87af3267130ca4225a0c6e30 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Tue, 16 Dec 2014 09:46:35 +1100 Subject: [PATCH 055/718] Get constrFamiliesLib.sml to compile properly. It would load interactively under Poly/ML, but if a dependency for another theory, or if compiled with Moscow ML it would fail to compile. --- examples/deep_matches/constrFamiliesLib.sml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/deep_matches/constrFamiliesLib.sml b/examples/deep_matches/constrFamiliesLib.sml index 297925fe21..6723cf685c 100644 --- a/examples/deep_matches/constrFamiliesLib.sml +++ b/examples/deep_matches/constrFamiliesLib.sml @@ -1,7 +1,7 @@ structure constrFamiliesLib :> constrFamiliesLib = struct -open Abbrev +open HolKernel boolLib simpLib bossLib (* Contructor families are lists of constructors. Constructors are functions that are injective and From d245ffc09b39436e05c21c5f0cccdb144dd00872 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Tue, 16 Dec 2014 14:38:49 +1100 Subject: [PATCH 056/718] Fix quotation-marks in doc-file for Parse.reveal. --- help/Docfiles/Parse.reveal.doc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/help/Docfiles/Parse.reveal.doc b/help/Docfiles/Parse.reveal.doc index 5af96864a0..1958f5d0c6 100644 --- a/help/Docfiles/Parse.reveal.doc +++ b/help/Docfiles/Parse.reveal.doc @@ -9,8 +9,8 @@ Restores recognition of a constant by the quotation parser. Parse \DESCRIBE -A call {reveal c}, where {c} the name of a (perhaps) hidden constant, -will `unhide` the constant, that is, will make the quotation parser map +A call {reveal c}, where {c} the name of a (perhaps) hidden constant, +will `unhide' the constant, that is, will make the quotation parser map the identifier {c} to all current constants with the same name (there may be more than one such as different theories may re-use the same name). From 86b1b4d0ff56e225f6eeb86609021261f19d13bb Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Wed, 17 Dec 2014 09:14:08 +1100 Subject: [PATCH 057/718] Eliminate more trailing whitespace in examples/deep_matches A prelude to another minor bug fix. --- examples/deep_matches/deepMatchesLib.sig | 10 +- examples/deep_matches/deepMatchesLib.sml | 110 ++++++++++---------- examples/deep_matches/deepMatchesSyntax.sml | 34 +++--- 3 files changed, 76 insertions(+), 78 deletions(-) diff --git a/examples/deep_matches/deepMatchesLib.sig b/examples/deep_matches/deepMatchesLib.sig index 8fcb6545de..43eb84b2d1 100644 --- a/examples/deep_matches/deepMatchesLib.sig +++ b/examples/deep_matches/deepMatchesLib.sig @@ -12,14 +12,14 @@ sig @x. SND (SND x = ..) /\ (FST x = ..) /\ (FST (SND x) = ..) - by resorting these conjunctions, one can + by resorting these conjunctions, one can easily derive a form @x. x = .. and therefore eliminate the select operator. This is done by the following conversion + ssfrag. *) - val ELIM_FST_SND_SELECT_CONV : conv + val ELIM_FST_SND_SELECT_CONV : conv val elim_fst_snd_select_ss : ssfrag @@ -39,7 +39,7 @@ sig (* There are various ways of simplifying PMATCH. One can e.g. remove redundant rows or partially evaluate it. The conversion - PMATCH_SIMP_CONV does this. *) + PMATCH_SIMP_CONV does this. *) val PMATCH_SIMP_CONV : conv (* There is also a more generic version that @@ -53,7 +53,7 @@ sig val PMATCH_SIMP_ss : ssfrag (* PMATCH_SIMP_CONV consists of various - component conversions. These can be used + component conversions. These can be used independently as well. *) val PMATCH_REMOVE_ARB_CONV : conv val PMATCH_REMOVE_ARB_CONV_GEN : ssfrag list -> conv @@ -65,7 +65,7 @@ sig val PMATCH_SIMP_COLS_CONV : conv val PMATCH_SIMP_COLS_CONV_GEN : ssfrag list -> conv - + val PMATCH_EXPAND_COLS_CONV : conv diff --git a/examples/deep_matches/deepMatchesLib.sml b/examples/deep_matches/deepMatchesLib.sml index 3270e28c5d..a15afd3e98 100644 --- a/examples/deep_matches/deepMatchesLib.sml +++ b/examples/deep_matches/deepMatchesLib.sml @@ -1,7 +1,7 @@ structure deepMatchesLib :> deepMatchesLib = struct -open deepMatchesTheory bossLib +open deepMatchesTheory bossLib open quantHeuristicsLib open deepMatchesSyntax open constrFamiliesLib @@ -35,7 +35,7 @@ in end handle HOL_ERR _ => raise UNCHANGED fun ELIM_FST_SND_SELECT_CONV t = let - val (v, conj) = boolSyntax.dest_select t + val (v, conj) = boolSyntax.dest_select t val thm0 = FST_SND_CONJUNCT_COLLAPSE v conj val thm1 = RAND_CONV (ABS_CONV (K thm0)) t @@ -63,19 +63,19 @@ val elim_fst_snd_select_ss = key = SOME ([],``$@ (f:'a -> bool)``), conv = K (K ELIM_FST_SND_SELECT_CONV)} -fun rc_ss gl = list_ss ++ simpLib.merge_ss - (gl @ +fun rc_ss gl = list_ss ++ simpLib.merge_ss + (gl @ [pabs_elim_ss, pairSimps.paired_forall_ss, pairSimps.paired_exists_ss, pairSimps.gen_beta_ss, elim_fst_snd_select_ss, simpLib.rewrites [ - pairTheory.EXISTS_PROD, + pairTheory.EXISTS_PROD, pairTheory.FORALL_PROD, - PMATCH_ROW_EQ_NONE, + PMATCH_ROW_EQ_NONE, PMATCH_ROW_COND_def, - PAIR_EQ_COLLAPSE, + PAIR_EQ_COLLAPSE, oneTheory.one]]) fun callback_CONV cb_opt t = (case cb_opt of @@ -84,15 +84,15 @@ fun callback_CONV cb_opt t = (case cb_opt of if (aconv t T) orelse (aconv t F) then (raise UNCHANGED) else (EQT_INTRO (cb t) handle HOL_ERR _ => EQF_INTRO (cb (mk_neg t))))) - -fun rc_conv (gl, callback_opt) = + +fun rc_conv (gl, callback_opt) = SIMP_CONV (rc_ss gl) [] THENC TRY_CONV (callback_CONV callback_opt) fun rc_tac (gl, callback_opt) = CONV_TAC (rc_conv (gl, callback_opt)) -fun PMATCH_ROW_ARGS_CONV c = +fun PMATCH_ROW_ARGS_CONV c = RATOR_CONV (RAND_CONV (TRY_CONV c)) THENC RATOR_CONV (RATOR_CONV (RAND_CONV (TRY_CONV c))) THENC RATOR_CONV (RATOR_CONV (RATOR_CONV (RAND_CONV (TRY_CONV c)))) @@ -102,7 +102,7 @@ fun PMATCH_ROW_ARGS_CONV c = (* converting case-splits to PMATCH *) (***********************************************) -(* +(* val t = ``case x of (NONE, []) => 0`` *) @@ -125,7 +125,7 @@ fun dest_case_fun_aux1 t = let | SOME ti => ti val _ = if (same_const (TypeBasePure.case_const_of ti) f) then - () else failwith "dest_case_fun" + () else failwith "dest_case_fun" val ty_s = match_type (type_of (TypeBasePure.case_const_of ti)) (type_of f) val constrs = List.map (inst ty_s) (TypeBasePure.constructors_of ti) @@ -136,7 +136,7 @@ fun dest_case_fun_aux1 t = let (list_mk_comb (c, vars), res) end) constrs (tl args) in (a, ps) -end +end (* destruct literal cases, see dest_case_fun *) fun dest_case_fun_aux2 t = let @@ -149,9 +149,9 @@ fun dest_case_fun_aux2 t = let fun strip_cond acc b = let val (c, t_t, t_f) = dest_cond b - val (c_l, c_r) = dest_eq c + val (c_l, c_r) = dest_eq c val _ = if (aconv c_l v') then () else failwith "dest_case_fun" - in + in strip_cond ((c_r, t_t)::acc) t_f end handle HOL_ERR _ => (acc, b) @@ -159,7 +159,7 @@ fun dest_case_fun_aux2 t = let val ps = List.rev ((v', c_else) :: ps_rev) in (v, ps) -end +end (* destruct a case-function. @@ -222,7 +222,7 @@ fun PMATCH_INTRO_CONV t = let CASE_TAC THEN FULL_SIMP_TAC (rc_ss []) [PMATCH_EVAL, PMATCH_ROW_COND_def] ) -in +in (* set_goal ([], tm) *) prove (tm, REPEAT my_tac) end handle HOL_ERR _ => raise UNCHANGED @@ -237,7 +237,7 @@ end handle HOL_ERR _ => raise UNCHANGED covered cases. These ARB rows are not needed for PMATCH and can be removed. *) -(* +(* val rc_arg = [] set_trace "parse deep cases" 0 @@ -269,10 +269,10 @@ fun PMATCH_REMOVE_ARB_CONV_GENCALL_SINGLE rc_arg t = let val r_thm = (snd (PMATCH_ROW_PABS_ELIM_CONV r)) handle UNCHANGED => REFL r - val input_rows = - listSyntax.mk_append (rows1_tm, + val input_rows = + listSyntax.mk_append (rows1_tm, listSyntax.mk_cons (rhs (concl r_thm), rows2_tm)) - + val thm0 = PART_MATCH (rand o lhs o snd o dest_imp o #2 o strip_forall) ( ISPEC v (FRESH_TY_VARS_RULE PMATCH_REMOVE_ARB_NO_OVERLAP) ) input_rows @@ -281,13 +281,13 @@ fun PMATCH_REMOVE_ARB_CONV_GENCALL_SINGLE rc_arg t = let val pre = rand (rator (concl thm0)) val pre_thm = prove (pre, rc_tac rc_arg) val thm1 = MP thm0 pre_thm - val thm2 = CONV_RULE + val thm2 = CONV_RULE ((RHS_CONV o RAND_CONV) listLib.APPEND_CONV) - thm1 + thm1 val thm2_lhs_tm = mk_eq (t, lhs (concl thm2)) val thm2_lhs = prove (thm2_lhs_tm, - MP_TAC r_thm THEN + MP_TAC r_thm THEN rc_tac rc_arg) val thm3 = TRANS thm2_lhs thm2 @@ -332,7 +332,7 @@ fun PMATCH_CLEANUP_PVARS_CONV t = let val row' = mk_PMATCH_ROW_PABS filtered_vars (pt, gt, rh) - val eq_tm = mk_eq (row, row') + val eq_tm = mk_eq (row, row') (* set_goal ([], eq_tm) *) val eq_thm = prove (eq_tm, MATCH_MP_TAC PMATCH_ROW_EQ_AUX THEN @@ -387,10 +387,10 @@ fun PMATCH_CLEANUP_CONV_GENCALL rc_arg t = let (if (same_const res_tm F) then SOME (false, r_thm) else NONE) end handle HOL_ERR _ => NONE - val (rows_checked_rev, _) = foldl (fn (r, (acc, abort)) => + val (rows_checked_rev, _) = foldl (fn (r, (acc, abort)) => if abort then ((r, NONE)::acc, true) else ( let - val res = check_row r + val res = check_row r val abort = (case res of (SOME (false, _)) => true | _ => false) @@ -412,14 +412,14 @@ fun PMATCH_CLEANUP_CONV_GENCALL rc_arg t = let val n = index (fn x => case x of (_, SOME (false, _)) => true | _ => false) rows_checked val n_tm = numSyntax.term_of_int n - val thma = ISPECL [v, listSyntax.mk_list (rows, row_ty), n_tm] + val thma = ISPECL [v, listSyntax.mk_list (rows, row_ty), n_tm] (FRESH_TY_VARS_RULE PMATCH_ROWS_DROP_REDUNDANT_TRIVIAL_SOUNDNESS) val precond = fst (dest_imp (concl thma)) - val precond_thm = prove (precond, + val precond_thm = prove (precond, MP_TAC (snd(valOf (snd (el (n+1) rows_checked)))) THEN SIMP_TAC list_ss [quantHeuristicsTheory.IS_SOME_EQ_NOT_NONE]) - + val thmb = MP thma precond_thm val take_conv = RATOR_CONV (RAND_CONV reduceLib.SUC_CONV) THENC @@ -463,20 +463,20 @@ fun PMATCH_CLEANUP_CONV_GENCALL rc_arg t = let val thm2 = let val _ = if (not (List.null rows_checked1) andalso (case hd rows_checked1 of (_, (SOME (false, _))) => true | _ => false)) then () else failwith "nothing to do" - + val thm1_tm = rhs (concl thm1) val thm2a = PART_MATCH (lhs o rand) PMATCH_EVAL_MATCH thm1_tm val pre_thm = EQF_ELIM (snd (valOf(snd (hd rows_checked1)))) val thm2b = MP thm2a pre_thm - val thm2c = CONV_RULE (RHS_CONV + val thm2c = CONV_RULE (RHS_CONV (RAND_CONV (rc_conv rc_arg) THENC pairLib.GEN_BETA_CONV)) thm2b handle HOL_ERR _ => thm2b in thm2c end handle HOL_ERR _ => let val _ = if (List.null rows_checked1) then () else failwith "nothing to do" - in + in (REWR_CONV (CONJUNCT1 PMATCH_def)) (rhs (concl thm1)) end handle HOL_ERR _ => REFL (rhs (concl thm1)) in @@ -558,27 +558,27 @@ fun PMATCH_REMOVE_COL_AUX rc_arg col t = let if (List.null vars') then [variant avoid ``uv:unit``] else vars' end - val vars'_tm = pairSyntax.list_mk_pair vars' + val vars'_tm = pairSyntax.list_mk_pair vars' val g' = let - val vs = List.take (vars, pv_i) @ (c_v :: List.drop (vars, pv_i+1)) + val vs = List.take (vars, pv_i) @ (c_v :: List.drop (vars, pv_i+1)) val vs_tm = pairSyntax.list_mk_pair vs in pairSyntax.mk_pabs (vars'_tm, vs_tm) end - in + in (vars'_tm, g') end) | NONE => (let - (* we eliminate a costant columns *) + (* we eliminate a costant columns *) val (sub, _) = match_term pv c_v val _ = if List.all (fn x => List.exists (aconv (#redex x)) vars) sub then () else failwith "not a constant-col after all" val vars' = filter (fn v => not (List.exists (fn x => (aconv v (#redex x))) sub)) vars val vars' = if (List.null vars') then [genvar ``:unit``] else vars' - val vars'_tm = pairSyntax.list_mk_pair vars' + val vars'_tm = pairSyntax.list_mk_pair vars' val g' = pairSyntax.mk_pabs (vars'_tm, Term.subst sub vars_tm) - in + in (vars'_tm, g') end) @@ -605,7 +605,7 @@ fun PMATCH_REMOVE_COL_AUX rc_arg col t = let fun elim_conv_aux vs = ( (pairTools.PABS_INTRO_CONV vs) THENC (DEPTH_CONV (pairLib.PAIRED_BETA_CONV ORELSEC BETA_CONV)) - ) + ) fun elim_conv vs = PMATCH_ROW_ARGS_CONV (elim_conv_aux vs) val thm = CONV_RULE ((RAND_CONV o RHS_CONV) (elim_conv vars'_tm)) thm @@ -620,7 +620,7 @@ fun PMATCH_REMOVE_COL_AUX rc_arg col t = let val pre_tm = fst (dest_imp (concl thm0)) (* set_goal ([], pre_tm) *) - val pre_thm = prove (pre_tm, rc_tac rc_arg) + val pre_thm = prove (pre_tm, rc_tac rc_arg) val thm1 = MP thm0 pre_thm in thm1 @@ -683,7 +683,7 @@ fun PMATCH_REMOVE_FUN_AUX rc_arg col t = let val (c', args') = strip_comb tt_args val _ = if (aconv c c') then () else failwith "different constr" - + val vars = List.take (tts, col) @ args' @ List.drop (tts, col+1) in @@ -762,7 +762,7 @@ fun PMATCH_REMOVE_FUN_AUX rc_arg col t = let val avoid = vars @ free_vars pt @ free_vars rh @ free_vars gt val (pt', pv, new_vars) = ff_inv_var avoid pt - val pv_i = index (aconv pv) vars + val pv_i = index (aconv pv) vars val vars' = let val vars' = List.take (vars, pv_i) @ new_vars @ List.drop (vars, pv_i+1) @@ -770,10 +770,10 @@ fun PMATCH_REMOVE_FUN_AUX rc_arg col t = let if (List.null vars') then [variant avoid ``uv:unit``] else vars' end - val vars'_tm = pairSyntax.list_mk_pair vars' + val vars'_tm = pairSyntax.list_mk_pair vars' val f_tm = let val c_v = list_mk_comb (c, new_vars) - val vs = List.take (vars, pv_i) @ (c_v :: List.drop (vars, pv_i+1)) + val vs = List.take (vars, pv_i) @ (c_v :: List.drop (vars, pv_i+1)) val vs_tm = pairSyntax.list_mk_pair vs in pairSyntax.mk_pabs (vars'_tm, vs_tm) @@ -811,7 +811,7 @@ fun PMATCH_REMOVE_FUN_AUX rc_arg col t = let val pre_tm = fst (dest_imp (concl thm0)) val pre_thm = prove (pre_tm, rc_tac rc_arg) - + val thm1 = MP thm0 pre_thm in thm1 @@ -903,7 +903,7 @@ val PMATCH_SIMP_COLS_CONV = PMATCH_SIMP_COLS_CONV_GEN [] (* Expand columns *) (***********************************************) -(* Sometimes not all rows of a PMATCH have the same number of +(* Sometimes not all rows of a PMATCH have the same number of explicit columns. This can happen, if some patterns are explicit pairs, while others are not. The following tries to expand columns into explicit ones. *) @@ -926,7 +926,7 @@ fun PMATCH_EXPAND_COLS_CONV t = let val col_no = foldl (fn (r, m) => let val (_, pt, _) = dest_PMATCH_ROW r val m' = length (pairSyntax.strip_pair pt) - val m'' = if m' > m then m' else m + val m'' = if m' > m then m' else m in m'' end) col_no_v rows fun split_var avoid cols l = let @@ -938,7 +938,7 @@ fun PMATCH_EXPAND_COLS_CONV t = let end val types = splits [] (col_no - cols) (type_of l) - + val var_basename = fst (dest_var l) handle HOL_ERR _ => "v" fun gen_var i ty = let val n = var_basename ^ "_"^int_to_string i @@ -976,7 +976,7 @@ fun PMATCH_EXPAND_COLS_CONV t = let val eq_tm = mk_eq(row, row') val eq_thm = prove (eq_tm, rc_tac ([], NONE)) - val thm = AP_THM eq_thm v + val thm = AP_THM eq_thm v in thm end handle HOL_ERR _ => REFL (mk_comb (row, v)) @@ -1043,7 +1043,7 @@ fun PMATCH_SIMP_CONV_GEN ssl = PMATCH_SIMP_CONV_GENCALL (ssl, NONE) val PMATCH_SIMP_CONV = PMATCH_SIMP_CONV_GEN [] -fun PMATCH_SIMP_convdata_conv ssl callback back = +fun PMATCH_SIMP_convdata_conv ssl callback back = PMATCH_SIMP_CONV_GENCALL (ssl, SOME (callback back)) @@ -1069,7 +1069,7 @@ PMATCH (a,x,xs) [PMATCH_ROW (\x. (NONE,x,[])) (\x. T) (\x. x); PMATCH_ROW (\x. (NONE,x,[2])) (\x. T) (\x. x); PMATCH_ROW (\ (x,v18). (NONE,x,[v18])) (\ (x, v18). T) (\ (x, v18). 3); - PMATCH_ROW (\ (x,v12,v16,v17). (NONE,x,v12::v16::v17)) + PMATCH_ROW (\ (x,v12,v16,v17). (NONE,x,v12::v16::v17)) (\ (x,v12,v16,v17). T) (\ (x,v12,v16,v17). 3); PMATCH_ROW (\ (y,x,z,zs). (SOME y,x,[z])) @@ -1112,7 +1112,7 @@ fun PMATCH_CASE_SPLIT_AUX col expand_thm conv t = let fun is_case_conv_end t = is_comb (fst (dest_comb t)) handle HOL_ERR _ => false - fun case_conv conv t = + fun case_conv conv t = if not (is_case_conv_end t) then REFL t else (RAND_CONV (STRIP_ABS_CONV conv) THENC RATOR_CONV (case_conv conv)) t @@ -1130,7 +1130,7 @@ fun PMATCH_CASE_SPLIT_CONV_GENCALL rc_arg col_no t = let val (v, col) = el (col_no+1) (dest_PMATCH_COLS t') - val expand_thm = get_case_expand_thm (v, col) + val expand_thm = get_case_expand_thm (v, col) val thm1 = QCHANGED_CONV (PMATCH_CASE_SPLIT_AUX col_no expand_thm (PMATCH_SIMP_CONV_GENCALL rc_arg)) t' handle HOL_ERR _ => (REFL t') in @@ -1138,5 +1138,3 @@ in end end - - diff --git a/examples/deep_matches/deepMatchesSyntax.sml b/examples/deep_matches/deepMatchesSyntax.sml index d6843885b1..ff41a087cd 100644 --- a/examples/deep_matches/deepMatchesSyntax.sml +++ b/examples/deep_matches/deepMatchesSyntax.sml @@ -1,7 +1,7 @@ structure deepMatchesSyntax :> deepMatchesSyntax = struct -open deepMatchesTheory bossLib +open deepMatchesTheory bossLib @@ -32,7 +32,7 @@ end; val ty_var_subst = [alpha |-> gen_tyvar (), beta |-> gen_tyvar (), - gamma |-> gen_tyvar (), + gamma |-> gen_tyvar (), delta |-> gen_tyvar (), ``:'e`` |-> gen_tyvar (), ``:'f`` |-> gen_tyvar (), @@ -48,7 +48,7 @@ val PMATCH_ROW_gtm = inst ty_var_subst PMATCH_ROW_tm val PMATCH_tm = ``PMATCH`` val PMATCH_gtm = inst ty_var_subst PMATCH_tm -fun FRESH_TY_VARS_RULE thm = +fun FRESH_TY_VARS_RULE thm = INST_TYPE ty_var_subst thm @@ -65,7 +65,7 @@ end fun is_PMATCH_ROW t = can dest_PMATCH_ROW t -fun mk_PMATCH_ROW (p_t, g_t, r_t) = +fun mk_PMATCH_ROW (p_t, g_t, r_t) = list_mk_icomb (PMATCH_ROW_gtm, [p_t, g_t, r_t]) fun mk_PMATCH_ROW_PABS vars (p_t, g_t, r_t) = let @@ -80,7 +80,7 @@ fun mk_PMATCH_ROW_PABS vars (p_t, g_t, r_t) = let in mk_PMATCH_ROW (mk_pabs p_t, mk_pabs g_t, mk_pabs r_t) end - + fun dest_PMATCH_ROW_ABS row = let val (p_t, g_t, r_t) = dest_PMATCH_ROW row @@ -88,7 +88,7 @@ fun dest_PMATCH_ROW_ABS row = let val (g_vars, g_body) = pairSyntax.dest_pabs g_t val (r_vars, r_body) = pairSyntax.dest_pabs r_t - val _ = if (aconv p_vars g_vars) andalso (aconv g_vars r_vars) then + val _ = if (aconv p_vars g_vars) andalso (aconv g_vars r_vars) then () else failwith "dest_PMATCH_ROW_ABS" in (p_vars, p_body, g_body, r_body) @@ -107,9 +107,9 @@ fun PMATCH_ROW_PABS_ELIM_CONV row = let val (p, _, _) = dest_PMATCH_ROW row val (vars, _) = pairSyntax.dest_pabs p - val c = TRY_CONV pairTools.PABS_ELIM_CONV - val thm = ((RAND_CONV c) THENC - (RATOR_CONV (RAND_CONV c)) THENC + val c = TRY_CONV pairTools.PABS_ELIM_CONV + val thm = ((RAND_CONV c) THENC + (RATOR_CONV (RAND_CONV c)) THENC (RATOR_CONV (RATOR_CONV (RAND_CONV c)))) row handle UNCHANGED => REFL row in @@ -122,8 +122,8 @@ fun PMATCH_ROW_PABS_INTRO_CONV vars row = let val (vars', _) = variant_of_term (free_vars row) vars val c = pairTools.PABS_INTRO_CONV vars' - val thm = ((RAND_CONV c) THENC - (RATOR_CONV (RAND_CONV c)) THENC + val thm = ((RAND_CONV c) THENC + (RATOR_CONV (RAND_CONV c)) THENC (RATOR_CONV (RATOR_CONV (RAND_CONV c)))) row in thm @@ -135,7 +135,7 @@ fun PMATCH_ROW_FORCE_SAME_VARS_CONV row = let val (vars, thm0) = PMATCH_ROW_PABS_ELIM_CONV row val thm1 = PMATCH_ROW_PABS_INTRO_CONV vars (rhs (concl thm0)) -in +in TRANS thm0 thm1 end handle HOL_ERR _ => raise UNCHANGED @@ -160,7 +160,7 @@ fun mk_PMATCH v rows = let val (arg_tys, _) = wfrecUtils.strip_fun_type ty0 in el 2 arg_tys end - val ty_subst = match_type rows_ty (type_of rows) + val ty_subst = match_type rows_ty (type_of rows) val b_tm = inst ty_subst PMATCH_tm val t1 = mk_comb (b_tm, v) val t2 = mk_comb (t1, rows) @@ -227,17 +227,17 @@ fun pmatch_printer GS backend sys (ppfns:term_pp_types.ppstream_funs) gravs d t val rows' = map dest_PMATCH_ROW_ABS rows - fun pp_row (vars, pat, guard, rh) = ( + fun pp_row (vars, pat, guard, rh) = ( term_pp_utils.record_bvars (pairSyntax.strip_pair vars) ( ublock PP.CONSISTENT 0 ( add_string "|" >> add_break (1, 0) >> sys (Top, Top, Top) (d - 1) pat >> (if (aconv guard T) then nothing else ( add_break (1, 0) >> add_string "when" >> add_break (1, 0) >> - sys (Top, Top, Top) (d - 1) guard + sys (Top, Top, Top) (d - 1) guard )) >> add_break (1, 0) >> add_string "=>" >> add_break (1, 0) >> - sys (Top, Top, Top) (d - 1) rh + sys (Top, Top, Top) (d - 1) rh )) ) in @@ -265,7 +265,7 @@ fun case_magic_to_deep_case t = let fun process_row row = let val (l,r) = dest_eq row val p = rand l - + val vars = free_vars_lr p in mk_PMATCH_ROW_PABS vars (p, T, r) From 058f11b17140dc5c5173c1ac25d65c8a06b0a1fe Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Wed, 17 Dec 2014 09:30:33 +1100 Subject: [PATCH 058/718] Fix more deep_matches files so that they compile. Check compilation of non-theory files with a selftest file that doesn't do anything except load the "lib" files. --- examples/deep_matches/Holmakefile | 9 +++++++++ examples/deep_matches/deepMatchesLib.sig | 2 +- examples/deep_matches/deepMatchesLib.sml | 3 ++- examples/deep_matches/deepMatchesSyntax.sml | 3 ++- examples/deep_matches/selftest.sml | 3 +++ 5 files changed, 17 insertions(+), 3 deletions(-) create mode 100644 examples/deep_matches/Holmakefile create mode 100644 examples/deep_matches/selftest.sml diff --git a/examples/deep_matches/Holmakefile b/examples/deep_matches/Holmakefile new file mode 100644 index 0000000000..eaeddd064f --- /dev/null +++ b/examples/deep_matches/Holmakefile @@ -0,0 +1,9 @@ +test: selftest.exe + ./$< + +.PHONY: test + +selftest.exe: selftest.uo deepMatchesSyntax.uo deepMatchesTheory.uo deepMatchesLib.uo constrFamiliesLib.uo + $(HOLMOSMLC) -o $@ $< + +EXTRA_CLEANS = selftest.exe diff --git a/examples/deep_matches/deepMatchesLib.sig b/examples/deep_matches/deepMatchesLib.sig index 43eb84b2d1..a7fda89c47 100644 --- a/examples/deep_matches/deepMatchesLib.sig +++ b/examples/deep_matches/deepMatchesLib.sig @@ -1,7 +1,7 @@ signature deepMatchesLib = sig include Abbrev - + type ssfrag = simpLib.ssfrag (********************************) (* eliminating select *) (********************************) diff --git a/examples/deep_matches/deepMatchesLib.sml b/examples/deep_matches/deepMatchesLib.sml index a15afd3e98..7857462df4 100644 --- a/examples/deep_matches/deepMatchesLib.sml +++ b/examples/deep_matches/deepMatchesLib.sml @@ -1,7 +1,8 @@ structure deepMatchesLib :> deepMatchesLib = struct -open deepMatchesTheory bossLib +open HolKernel boolLib bossLib +open deepMatchesTheory open quantHeuristicsLib open deepMatchesSyntax open constrFamiliesLib diff --git a/examples/deep_matches/deepMatchesSyntax.sml b/examples/deep_matches/deepMatchesSyntax.sml index ff41a087cd..9b8390459e 100644 --- a/examples/deep_matches/deepMatchesSyntax.sml +++ b/examples/deep_matches/deepMatchesSyntax.sml @@ -1,7 +1,8 @@ structure deepMatchesSyntax :> deepMatchesSyntax = struct -open deepMatchesTheory bossLib +open HolKernel Parse boolLib bossLib +open deepMatchesTheory diff --git a/examples/deep_matches/selftest.sml b/examples/deep_matches/selftest.sml new file mode 100644 index 0000000000..055a805944 --- /dev/null +++ b/examples/deep_matches/selftest.sml @@ -0,0 +1,3 @@ +open constrFamiliesLib deepMatchesLib + +val _ = print "OK\n" From 15c0b3365bfe6b7367c3adcaee42706fcf2828a0 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Wed, 17 Dec 2014 13:28:16 +1100 Subject: [PATCH 059/718] Fix an indentation glitch --- src/integer/testing/selftest.sml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/integer/testing/selftest.sml b/src/integer/testing/selftest.sml index a7132c597e..8575179430 100644 --- a/src/integer/testing/selftest.sml +++ b/src/integer/testing/selftest.sml @@ -18,7 +18,7 @@ fun usage() = val cooper_result = case CommandLine.arguments() of [] => if Systeml.ML_SYSNAME = "poly" then cooper() else (usage(); true) - | [x] => let + | [x] => let in case Int.fromString x of SOME n => if n >= 2 then cooper() From 1c5ae6b6d733e0e40fdd001f4d469ee47e7bc1b2 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Wed, 17 Dec 2014 13:37:29 +1100 Subject: [PATCH 060/718] Fix & document an infinite loop bug in intSimps.{OMEGA,COOPER}_ss Problem was that the term F was viewed as suitable context for the simplifier's decision procedure. Though superficially reasonable, this leads to problems because the simplifier will rewrite everything it can inside this context to F, using the rewrite [F] |- somegenvar = F (1) but the integer decision procedures will correctly rewrite occurrences of F to T, because the underlying conversion is happy to prove |- (F ==> F) <=> T The natural number procedure in ARITH_ss doesn't suffer from this problem because it doesn't add F as context to the decision procedure's context, and that's the fix taken here. The decision to use (1) above rather than rewrite to true, say, was taken in 9bc4bdaa. --- doc/next-release.md | 2 ++ src/integer/intSimps.sml | 4 +++- src/integer/testing/selftest.sml | 9 +++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/doc/next-release.md b/doc/next-release.md index 462769728c..aaf23c84c6 100644 --- a/doc/next-release.md +++ b/doc/next-release.md @@ -23,6 +23,8 @@ New features: Bugs fixed: ----------- +- An embarrassing infinite loop bug in the integration of the integer decision procedures (the Omega test, Cooper’s algorithm) into the simplifier was fixed. + New theories: ------------- diff --git a/src/integer/intSimps.sml b/src/integer/intSimps.sml index 57de65ee9a..58e34ec7c3 100644 --- a/src/integer/intSimps.sml +++ b/src/integer/intSimps.sml @@ -260,7 +260,9 @@ fun mkSS DPname DP = let exception CTXT of thm list fun get_ctxt e = (raise e) handle CTXT c => c fun add_ctxt(ctxt, newthms) = let - val addthese = filter is_arith_thm (flatten (map CONJUNCTS newthms)) + val addthese = filter (fn th => is_arith_thm th andalso + concl th <> boolSyntax.F) + (flatten (map CONJUNCTS newthms)) in CTXT (addthese @ get_ctxt ctxt) end diff --git a/src/integer/testing/selftest.sml b/src/integer/testing/selftest.sml index 8575179430..547a19a536 100644 --- a/src/integer/testing/selftest.sml +++ b/src/integer/testing/selftest.sml @@ -27,6 +27,15 @@ val cooper_result = end | _ => (usage(); true) +val _ = print "Testing simplifier integration\n" + +open testutils simpLib boolSimps + +val _ = tprint "F ==> F equivalent shouldn't loop" +val th = SIMP_CONV (bool_ss ++ intSimps.OMEGA_ss) [] ``x > 2n /\ F ==> x > 1`` + handle e => die (General.exnMessage e) +val _ = print "OK\n" + val _ = Process.exit (if cooper_result andalso omega_result then Process.success else Process.failure) From 1eb04c9b90dffedf060bd542015f929ffa93e795 Mon Sep 17 00:00:00 2001 From: Magnus Myreen Date: Sat, 20 Dec 2014 10:17:30 +1100 Subject: [PATCH 061/718] exported a useful theorem about the x64 code pool --- .../instruction-set-models/x86_64/prog_x64Script.sml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/machine-code/instruction-set-models/x86_64/prog_x64Script.sml b/examples/machine-code/instruction-set-models/x86_64/prog_x64Script.sml index 18919c8232..595ded223c 100644 --- a/examples/machine-code/instruction-set-models/x86_64/prog_x64Script.sml +++ b/examples/machine-code/instruction-set-models/x86_64/prog_x64Script.sml @@ -1209,7 +1209,7 @@ val X64_SPEC_EXLPODE_CODE_LEMMA = store_thm("X64_SPEC_EXLPODE_CODE_LEMMA", val X64_SPEC_EXLPODE_CODE = save_thm("X64_SPEC_EXLPODE_CODE", RW [UNION_EMPTY] (Q.SPEC `{}` X64_SPEC_EXLPODE_CODE_LEMMA)); -val CODE_POOL_INSERT_INSERT = prove( +val CODE_POOL_INSERT_INSERT = store_thm("CODE_POOL_INSERT_INSERT", ``CODE_POOL X64_INSTR ((a1,xs) INSERT (a1 + n2w (LENGTH xs),ys) INSERT s) = CODE_POOL X64_INSTR ((a1,xs ++ ys) INSERT s)``, SIMP_TAC std_ss [CODE_POOL_def,IMAGE_INSERT] \\ ONCE_REWRITE_TAC [FUN_EQ_THM] From e8e1f70ea89e04872dbc8e092e6e192ae204505a Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Sat, 20 Dec 2014 20:58:56 +1100 Subject: [PATCH 062/718] GEN_VALIDATE(_LT) - flag for adding new subgoals in any event GEN_VALIDATE false is like VALIDATE, but adds subgoals for the assumptions of the theorem produced by the justification, regardless of whether they are among the assumptions of the goal. Advantage of this is that GEN_VALIDATE false (ACCEPT_TAC th) produces predictable subgoals, which may help in coding compound tactics --- help/Docfiles/Tactical.GEN_VALIDATE.doc | 75 ++++++++++++++++++++++ help/Docfiles/Tactical.GEN_VALIDATE_LT.doc | 42 ++++++++++++ help/Docfiles/Tactical.VALIDATE.doc | 5 +- src/1/Tactical.sig | 2 + src/1/Tactical.sml | 33 +++++++--- 5 files changed, 145 insertions(+), 12 deletions(-) create mode 100644 help/Docfiles/Tactical.GEN_VALIDATE.doc create mode 100644 help/Docfiles/Tactical.GEN_VALIDATE_LT.doc diff --git a/help/Docfiles/Tactical.GEN_VALIDATE.doc b/help/Docfiles/Tactical.GEN_VALIDATE.doc new file mode 100644 index 0000000000..2bbcdfbc97 --- /dev/null +++ b/help/Docfiles/Tactical.GEN_VALIDATE.doc @@ -0,0 +1,75 @@ +\DOC GEN_VALIDATE + +\TYPE {GEN_VALIDATE : bool -> tactic -> tactic} + +\SYNOPSIS +Where a tactic requires assumptions to be in the goal, +add those assumptions as new subgoals. + +\DESCRIBE +See {VALIDATE}, which is implemented as {GEN_VALIDATE true}. + +Suppose {tac} applied to the goal {(asl,g)} produces a justification that +creates a theorem {A |- g'}. +Then {GEN_VALIDATE false} adds new subgoals for members of {A}, +regardless of whether they are present in {asl}. + +\FAILURE +Fails by design if {tac}, when applied to a goal, +produces a proof which is invalid on account of proving +a theorem whose conclusion differs from that of the goal. + +Also fails if {tac} fails when applied to the given goal. + +\EXAMPLE +For example, where theorem {uthr'} is {[p', q] |- r} + +{ +1 subgoal: +val it = + +r +------------------------------------ + 0. p + 1. q + +> e (VALIDATE (ACCEPT_TAC uthr')) ; +OK.. +1 subgoal: +val it = + +p' +------------------------------------ + p +: + proof +} +but, instead of that, +{ +> e (GEN_VALIDATE false (ACCEPT_TAC uthr')) ; +OK.. +2 subgoals: +val it = + +q +------------------------------------ + 0. p + 1. q + + +p' +------------------------------------ + 0. p + 1. q +} + +\USES +Use {GEN_VALIDATE false} rather than {VALIDATE} +when programming compound tactics if you want to know +what the resulting subgoals will be, + regardless of what the assumptions of the goal are. + +\SEEALSO +Tactical.VALID, Tactical.VALIDATE + +\ENDDOC diff --git a/help/Docfiles/Tactical.GEN_VALIDATE_LT.doc b/help/Docfiles/Tactical.GEN_VALIDATE_LT.doc new file mode 100644 index 0000000000..c388363552 --- /dev/null +++ b/help/Docfiles/Tactical.GEN_VALIDATE_LT.doc @@ -0,0 +1,42 @@ +\DOC GEN_VALIDATE_LT + +\TYPE {GEN_VALIDATE_LT : bool -> list_tactic -> list_tactic} + +\SYNOPSIS +Where a list-tactic requires assumptions to be in the goal, +add those assumptions as new subgoals. + +\DESCRIBE +See {VALIDATE_LT}, which is implemented as {GEN_VALIDATE_LT true}. + +When list-tactic {ltac} is applied to a goal list {gl} +it produces a new goal list {gl'} and a justification. +When the justification is applied to a list {thl'} of theorems +which are the new goals {gl'}, proved, it produces a list {thl} +of theorems (which, for a valid list-tactic are the goals {gl}, proved). + +But {GEN_VALIDATE_LT false ltac} also returns extra subgoals corresponding to +the assumptions of {thl}. + +See {GEN_VALIDATE} for more details. + +\FAILURE +Fails by design if {ltac}, when applied to a goal list, +produces a proof which is invalid on account of proving +a theorem whose conclusion differs from that of the corresponding goal. + +Also fails if {ltac} fails when applied to the given goals. + +\USES +Compared with {VALIDATE_LT ltac}, {GEN_VALIDATE_LT false ltac} can +produces extra, unnecessary, subgoals. +But since the subgoals produced are predictable, regardless of the assumptions +of the goal, which may be useful when coding compound tactics. + +\SEEALSO +Tactical.VALID, Tactical.VALID_LT, Tactical.VALIDATE, +Tactical.VALIDATE_LT, Tactical.GEN_VALIDATE + +\ENDDOC + + diff --git a/help/Docfiles/Tactical.VALIDATE.doc b/help/Docfiles/Tactical.VALIDATE.doc index 6b677d84ae..291c2fbbb5 100644 --- a/help/Docfiles/Tactical.VALIDATE.doc +++ b/help/Docfiles/Tactical.VALIDATE.doc @@ -12,7 +12,7 @@ creates a theorem {A |- g'}. If {A} a not a subset of {asl}, then the tactic is invalid (and {VALID tac (asl,g)} fails, ie, raises an exception). But {VALIDATE tac (asl,g)} produces a subgoal list augmented by the -members of {asl} missing from {A}. +members of {A} missing from {asl}. If {g'} differs from {g}, both {VALID tac (asl,g)} and {VALIDATE tac (asl,g)} fail. @@ -97,6 +97,7 @@ which are not present but are capable of being proved, assumptions. \SEEALSO -proofManagerLib.expand, Tactical.VALID, Tactical.SUBGOAL_THEN. +proofManagerLib.expand, Tactical.VALID, Tactical.GEN_VALIDATE, +Tactical.SUBGOAL_THEN. \ENDDOC diff --git a/src/1/Tactical.sig b/src/1/Tactical.sig index 9f06979f99..2dbcf35c21 100644 --- a/src/1/Tactical.sig +++ b/src/1/Tactical.sig @@ -41,6 +41,8 @@ sig val VALID_LT : list_tactic -> list_tactic val VALIDATE : tactic -> tactic val VALIDATE_LT : list_tactic -> list_tactic + val GEN_VALIDATE : bool -> tactic -> tactic + val GEN_VALIDATE_LT : bool -> list_tactic -> list_tactic val EVERY : tactic list -> tactic val FIRST : tactic list -> tactic val MAP_EVERY : ('a -> tactic) -> 'a list -> tactic diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index 71639fa120..b2d0cf7dd1 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -372,31 +372,40 @@ end * tactic or list_tactic valid. * * VALIDATE tac + * GEN_VALIDATE true tac * * is the same as "tac", except that where "tac" returns a proof which is * because if proves a theorem with extra hypotheses, it returns those * hypotheses as extra goals * * VALIDATE_LT ltac + * GEN_VALIDATE_LT true ltac * * is the same as "ltac", except it will return extra goals where this is * necessary to make a valid list-tactic + * + * GEN_VALIDATE(_LT) false always returns extra goals corresponding + * to the hypotheses of the theorem proved + * *---------------------------------------------------------------------------*) local val validity_tag = "ValidityCheck" fun masquerade goal = Thm.mk_oracle_thm validity_tag goal ; fun achieves_concl th (asl, w) = Term.aconv (concl th) w ; fun hyps_not_in_goal th (asl, w) = Lib.filter (fn h => not (Lib.exists (aconv h) asl)) (hyp th) ; - fun extra_goals_tbp th (asl, w) = - List.map (fn eg => (asl, eg)) (hyps_not_in_goal th (asl, w)) ; + fun extra_goals_tbp flag th (asl, w) = + List.map (fn eg => (asl, eg)) + (case flag of true => hyps_not_in_goal th (asl, w) + | false => hyp th) ; in -fun VALIDATE (tac : tactic) (g as (asl, w) : goal) = +(* GEN_VALIDATE : bool -> tactic -> tactic *) +fun GEN_VALIDATE (flag : bool) (tac : tactic) (g as (asl, w) : goal) = let val (glist, prf) = tac g ; (* pretend new goals are theorems, and apply validation to them *) val thprf = (prf (map masquerade glist)) ; val _ = if achieves_concl thprf g then () - else raise ERR "VALIDATE" "Invalid tactic - wrong conclusion" ; - val extra_goals = extra_goals_tbp thprf g ; + else raise ERR "GEN_VALIDATE" "Invalid tactic - wrong conclusion" ; + val extra_goals = extra_goals_tbp flag thprf g ; val nextra = length extra_goals ; (* new validation: apply the theorems proving the additional goals to eliminate the extra hyps in the theorem proved by the given validation *) @@ -412,15 +421,15 @@ fun split_lists (n :: ns) ths = in (nths :: nsths, left) end | split_lists [] ths = ([], ths) ; -(* VALIDATE_LT : list_tactic -> list_tactic *) -fun VALIDATE_LT (ltac : list_tactic) (gl : goal list) = +(* GEN_VALIDATE_LT : bool -> list_tactic -> list_tactic *) +fun GEN_VALIDATE_LT (flag : bool) (ltac : list_tactic) (gl : goal list) = let val (glist, prf) = ltac gl ; (* pretend new goals are theorems, and apply validation to them *) val thsprf = (prf (map masquerade glist)) ; val _ = if Lib.all2 achieves_concl thsprf gl then () - else raise ERR "VALIDATE_LT" + else raise ERR "GEN_VALIDATE_LT" "Invalid list-tactic - some wrong conclusion" ; - val extra_goal_lists = Lib.map2 extra_goals_tbp thsprf gl ; + val extra_goal_lists = Lib.map2 (extra_goals_tbp flag) thsprf gl ; val nextras = map length extra_goal_lists ; (* new validation: apply the theorems proving the additional goals to eliminate the extra hyps in the theorems proved by the given validation *) @@ -431,8 +440,12 @@ fun VALIDATE_LT (ltac : list_tactic) (gl : goal list) = end; +val VALIDATE = GEN_VALIDATE true ; +val VALIDATE_LT = GEN_VALIDATE_LT true ; + (* could avoid duplication of code in the above by the following -fun VALIDATE tac = ALL_TAC THEN_LT VALIDATE_LT (TACS_TO_LT [tac]) ; +fun GEN_VALIDATE flag tac = + ALL_TAC THEN_LT GEN_VALIDATE_LT flag (TACS_TO_LT [tac]) ; *) (*--------------------------------------------------------------------------- From fce4b42aaca3feff27380cba13acd9ec3972d50f Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Sat, 20 Dec 2014 23:57:40 +1100 Subject: [PATCH 063/718] added flatn command in proofManagerLib in interactive proof, to flatten subgoal stack, so as to merge current list of subgoals with previous level(s) --- help/Docfiles/proofManagerLib.expand.doc | 4 +- help/Docfiles/proofManagerLib.expand_list.doc | 2 +- help/Docfiles/proofManagerLib.flatn.doc | 37 +++++++++++++++++++ help/Docfiles/proofManagerLib.set_goal.doc | 9 ++++- src/proofman/Manager.sig | 1 + src/proofman/Manager.sml | 4 ++ src/proofman/goalStack.sig | 1 + src/proofman/goalStack.sml | 15 ++++++++ src/proofman/proofManagerLib.sig | 1 + src/proofman/proofManagerLib.sml | 4 ++ 10 files changed, 73 insertions(+), 5 deletions(-) create mode 100644 help/Docfiles/proofManagerLib.flatn.doc diff --git a/help/Docfiles/proofManagerLib.expand.doc b/help/Docfiles/proofManagerLib.expand.doc index eb029f4ed0..e97b42017e 100644 --- a/help/Docfiles/proofManagerLib.expand.doc +++ b/help/Docfiles/proofManagerLib.expand.doc @@ -146,7 +146,7 @@ Doing a step in an interactive goal-directed proof. proofManagerLib.set_goal, proofManagerLib.restart, proofManagerLib.backup,proofManagerLib.restore, proofManagerLib.save, proofManagerLib.set_backup,proofManagerLib.expand, proofManagerLib.expandf, -proofManagerLib.p,proofManagerLib.top_thm, proofManagerLib.top_goal, -Tactical.VALID, Tactical.VALIDATE +proofManagerLib.flatn,proofManagerLib.p,proofManagerLib.top_thm, +proofManagerLib.top_goal, Tactical.VALID, Tactical.VALIDATE \ENDDOC diff --git a/help/Docfiles/proofManagerLib.expand_list.doc b/help/Docfiles/proofManagerLib.expand_list.doc index 94b71fa0d5..7db56b52b3 100644 --- a/help/Docfiles/proofManagerLib.expand_list.doc +++ b/help/Docfiles/proofManagerLib.expand_list.doc @@ -89,7 +89,7 @@ preceding step. proofManagerLib.set_goal, proofManagerLib.restart, proofManagerLib.backup,proofManagerLib.restore, proofManagerLib.save, proofManagerLib.set_backup,proofManagerLib.expand, proofManagerLib.expandf, -proofManagerLib.expand_listf, +proofManagerLib.expand_listf, proofManagerLib.flatn, proofManagerLib.p,proofManagerLib.top_thm, proofManagerLib.top_goal. \ENDDOC diff --git a/help/Docfiles/proofManagerLib.flatn.doc b/help/Docfiles/proofManagerLib.flatn.doc new file mode 100644 index 0000000000..3df347ab4f --- /dev/null +++ b/help/Docfiles/proofManagerLib.flatn.doc @@ -0,0 +1,37 @@ +\DOC flatn + +\TYPE {flatn : int -> unit} + +\SYNOPSIS +Flattens the tree structure of subgoals on the subgoal package goal stack. + +\DESCRIBE +The function {flatn} is part of the subgoal package. +For a general description of the subgoal package, see {set_goal}. + +The {flatn} function's basic step of operation is to take the +the current list of sub-goals and concatenate it with the previous list of +subgoals (excluding the first of that list, from which the current list was +obtained). +The numeric argument passed to {flatn} specifies how many +times this operation is to be performed. + +\FAILURE +Raises the {NO_PROOFS} exception if there is no current proof +manipulated by the subgoal package. + +If {n} is too large, or negative, +the result will be a flat list of all subgoals. + +\USES +To view, reorder, or attack simultaneously, +current and previously obtained subgoals. + +\SEEALSO +proofManagerLib.set_goal, proofManagerLib.restart, +proofManagerLib.backup,proofManagerLib.restore, proofManagerLib.save, +proofManagerLib.set_backup,proofManagerLib.expand, proofManagerLib.expandf, +proofManagerLib.p,proofManagerLib.top_thm, proofManagerLib.top_goal. + +\ENDDOC + diff --git a/help/Docfiles/proofManagerLib.set_goal.doc b/help/Docfiles/proofManagerLib.set_goal.doc index 7a0401cb15..da552bb0fb 100644 --- a/help/Docfiles/proofManagerLib.set_goal.doc +++ b/help/Docfiles/proofManagerLib.set_goal.doc @@ -46,8 +46,12 @@ subgoals and justifications. These are pushed onto the goal stack and justification stack, respectively, to form a new proof state. Several preceding proof states are saved and can be returned to if a mistake is made in the proof. The goal stack is divided into levels, a new level being -created each time a tactic is successfully applied to give new subgoals. The -subgoals of the current level may be considered in any order. +created each time a tactic is successfully applied to give new subgoals. +Alternatively a list-tactic can process the entire list of goals of the current +level to change that level (rather than creating a new level). +The subgoals of the current level may be considered in any order. +Levels of the goal stack may be collapsed so that subgoals of a previous level +appear as part of of the current level. If a tactic solves the current goal (returns an empty subgoal list), then its justification is used to prove a corresponding theorem. This theorem is @@ -66,6 +70,7 @@ saved. proofManagerLib.set_goal, proofManagerLib.restart, proofManagerLib.backup,proofManagerLib.restore, proofManagerLib.save, proofManagerLib.set_backup,proofManagerLib.expand, proofManagerLib.expandf, +proofManagerLib.expand_list, proofManagerLib.flatn, proofManagerLib.p,proofManagerLib.top_thm, proofManagerLib.top_goal. \ENDDOC diff --git a/src/proofman/Manager.sig b/src/proofman/Manager.sig index b1fb138712..d9b2d35108 100644 --- a/src/proofman/Manager.sig +++ b/src/proofman/Manager.sig @@ -41,6 +41,7 @@ sig (* Switch focus to a different subgoal (or proof attempt) *) val rotate : int -> proof -> proof + val flatn : int -> proof -> proof val rotate_proofs : int -> proofs -> proofs (* Operations on proof attempts *) diff --git a/src/proofman/Manager.sml b/src/proofman/Manager.sml index f7269fe9a3..ff4c1b2bce 100644 --- a/src/proofman/Manager.sml +++ b/src/proofman/Manager.sml @@ -120,6 +120,10 @@ fun rotate i (GOALSTACK s) = GOALSTACK(apply (C goalStack.rotate i) s) | rotate i (GOALTREE t) = raise ERR "rotate" "not implemented for goal trees"; +fun flatn i (GOALSTACK s) = GOALSTACK(apply (C goalStack.flatn i) s) + | flatn i (GOALTREE t) = raise ERR "flatn" + "not implemented for goal trees"; + fun restart (GOALSTACK s) = GOALSTACK (new_history_default (initialValue s)) | restart (GOALTREE t) = GOALTREE (new_history_default (initialValue t)); diff --git a/src/proofman/goalStack.sig b/src/proofman/goalStack.sig index ac4fe37357..1125d0e108 100644 --- a/src/proofman/goalStack.sig +++ b/src/proofman/goalStack.sig @@ -17,6 +17,7 @@ sig val is_initial : gstk -> bool val new_goal : goal -> (thm -> thm) -> gstk val rotate : gstk -> int -> gstk + val flatn : gstk -> int -> gstk val top_goal : gstk -> goal val top_goals : gstk -> goal list val depth : gstk -> int diff --git a/src/proofman/goalStack.sml b/src/proofman/goalStack.sml index aa703dbbec..a8460e134f 100644 --- a/src/proofman/goalStack.sml +++ b/src/proofman/goalStack.sml @@ -177,6 +177,21 @@ end ; fun expand tac gs = expandf (Tactical.VALID tac) gs; fun expand_list ltac gs = expand_listf (Tactical.VALID_LT ltac) gs; +fun flat (GSTK{prop, stack as {goals,validation} :: + {goals = g2 :: goals2, validation = validation2} :: rst, final}) = + let fun v thl = + let val (thl1, thl2) = Lib.split_after (length goals) thl ; + in validation2 (validation thl1 :: thl2) end ; + val newgv = {goals = goals @ goals2, validation = v} ; + in GSTK {prop = prop, stack = newgv :: rst, final = final} end ; + +fun flatn (GSTK{prop=PROVED _, ...}) n = + raise ERR "flatn" "goal has already been proved" + | flatn gstk 0 = gstk + | flatn (gstk as GSTK{prop, stack = [], final}) n = gstk + | flatn (gstk as GSTK{prop, stack as [_], final}) n = gstk + | flatn (gstk as GSTK{prop, stack, final}) n = flatn (flat gstk) (n-1) ; + fun extract_thm (GSTK{prop=PROVED(th,_), ...}) = th | extract_thm _ = raise ERR "extract_thm" "no theorem proved"; diff --git a/src/proofman/proofManagerLib.sig b/src/proofman/proofManagerLib.sig index d6d26ddda9..f53cd785af 100644 --- a/src/proofman/proofManagerLib.sig +++ b/src/proofman/proofManagerLib.sig @@ -56,6 +56,7 @@ sig val r : int -> proof val R : int -> proofs val rotate : int -> proof + val flatn : int -> proof val rotate_proofs : int -> proofs (* Switch to a different prettyprinter for all goals *) diff --git a/src/proofman/proofManagerLib.sml b/src/proofman/proofManagerLib.sml index a5e705db8a..1a9d0f581e 100644 --- a/src/proofman/proofManagerLib.sml +++ b/src/proofman/proofManagerLib.sml @@ -121,6 +121,10 @@ fun p () = Manager.hd_proj I (proofs()) val status = proofs; +fun flatn i = + (the_proofs := Manager.hd_opr (Manager.flatn i) (proofs()); + top_proof()); + fun rotate i = (the_proofs := Manager.hd_opr (Manager.rotate i) (proofs()); top_proof()); From 284ce52d3ac95cb5c4814c66fb3d8168c3c46e22 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Sun, 21 Dec 2014 05:20:03 +0000 Subject: [PATCH 064/718] reuse cpn datatype from totoTheory in comparisonTheory rather than creating an isomorphic new type. balanced_mapScript.sml has apparently (but not actually) significant changes because the proofs depend heavily on the order in which the comparison datatype constructors are defined (inasmuch as it affects the order of subgoals from cases/induction). --- examples/balanced_bst/balanced_mapScript.sml | 97 +++++++++++--------- examples/balanced_bst/comparisonScript.sml | 13 +-- examples/balanced_bst/osetScript.sml | 2 + 3 files changed, 61 insertions(+), 51 deletions(-) diff --git a/examples/balanced_bst/balanced_mapScript.sml b/examples/balanced_bst/balanced_mapScript.sml index 5fc12e54d4..eaee1364f6 100644 --- a/examples/balanced_bst/balanced_mapScript.sml +++ b/examples/balanced_bst/balanced_mapScript.sml @@ -11,6 +11,13 @@ val _ = new_theory "balanced_map"; val _ = temp_tight_equality (); val _ = numLib.prefer_num(); +val _ = Parse.temp_overload_on("Less",``LESS``) +val _ = Parse.temp_overload_on("Equal",``EQUAL``) +val _ = Parse.temp_overload_on("Greater",``GREATER``) +val comparison_distinct = totoTheory.cpn_distinct +val comparison_case_def = totoTheory.cpn_case_def +val comparison_nchotomy = totoTheory.cpn_nchotomy + val list_rel_lem1 = Q.prove ( `!f l l'. ~LIST_REL f l l' @@ -1304,6 +1311,10 @@ val insert_thm = Q.store_thm ("insert_thm", rw [] >> `key_set cmp k ≠ key_set cmp k'` by metis_tac [key_set_eq, cmp_thms] >> metis_tac [FUPDATE_COMMUTES]) + >- (fs [invariant_def] >> + rfs [key_ordered_to_fmap] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms]) + >- metis_tac [key_set_eq, FUPDATE_EQ] >- (rfs [key_ordered_to_fmap] >> rw [] >> imp_res_tac to_fmap_key_set >> @@ -1316,11 +1327,7 @@ val insert_thm = Q.store_thm ("insert_thm", >- (rw [FUNION_FUPDATE_2, to_fmap_def] >> rfs [key_ordered_to_fmap] >> rw [] >> - metis_tac [FUPDATE_COMMUTES, cmp_thms, to_fmap_key_set, key_set_cmp_thm]) - >- (fs [invariant_def] >> - rfs [key_ordered_to_fmap] >> - metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms]) - >- metis_tac [key_set_eq, FUPDATE_EQ]); + metis_tac [FUPDATE_COMMUTES, cmp_thms, to_fmap_key_set, key_set_cmp_thm])); val insertR_thm = Q.store_thm ("insertR_thm", `∀t. @@ -1354,6 +1361,9 @@ val insertR_thm = Q.store_thm ("insertR_thm", imp_res_tac balanceL_thm >> rw [FUNION_FUPDATE_1] >> metis_tac [FUPDATE_COMMUTES, good_cmp_def, comparison_distinct]) + >- (fs [invariant_def] >> + rfs [key_ordered_to_fmap] >> + metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms,key_set_eq, FUPDATE_EQ]) >- (`almost_balancedR (size t) (size (insertR cmp k v t'))` by (imp_res_tac size_thm >> rw [FCARD_FUPDATE] >> @@ -1369,10 +1379,7 @@ val insertR_thm = Q.store_thm ("insertR_thm", imp_res_tac balanceR_thm >> rw [FUNION_FUPDATE_2] >> rfs [key_ordered_to_fmap] >> - metis_tac [FUPDATE_COMMUTES, good_cmp_def, comparison_distinct]) - >- (fs [invariant_def] >> - rfs [key_ordered_to_fmap] >> - metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms,key_set_eq, FUPDATE_EQ])); + metis_tac [FUPDATE_COMMUTES, good_cmp_def, comparison_distinct])); val insertMax_thm = Q.store_thm ("insertMax_thm", `∀t. @@ -1815,6 +1822,11 @@ val delete_thm = Q.store_thm ("delete_thm", imp_res_tac almost_balancedR_thm >> metis_tac [FCARD_DEF]) >- to_fmap_tac) + >- (inv_mp_tac glue_thm >> + rw [] >> + rfs [key_ordered_to_fmap] + >- metis_tac [key_set_cmp2_thm, to_fmap_key_set, key_set_cmp_thm, cmp_thms] + >- to_fmap_tac) >- (inv_mp_tac balanceL_thm >> simp [] >> rw [] @@ -1826,11 +1838,6 @@ val delete_thm = Q.store_thm ("delete_thm", rw [FCARD_DRESTRICT, DELETE_INTER2] >> imp_res_tac almost_balancedL_thm >> metis_tac [FCARD_DEF]) - >- to_fmap_tac) - >- (inv_mp_tac glue_thm >> - rw [] >> - rfs [key_ordered_to_fmap] - >- metis_tac [key_set_cmp2_thm, to_fmap_key_set, key_set_cmp_thm, cmp_thms] >- to_fmap_tac)); val restrict_set_def = Define ` @@ -2059,11 +2066,11 @@ val filter_lt_help_thm = Q.prove ( rw [restrict_domain_def]) >> rw [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def] >> to_fmap_tac) - >- (first_x_assum inv_mp_tac >> - fs [invariant_eq] >> + >- (fs [invariant_eq] >> rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> to_fmap_tac) - >- (fs [invariant_eq] >> + >- (first_x_assum inv_mp_tac >> + fs [invariant_eq] >> rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> to_fmap_tac)); @@ -2107,11 +2114,11 @@ val filter_gt_help_thm = Q.prove ( rw [restrict_domain_def]) >> rw [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def] >> to_fmap_tac) - >- (first_x_assum inv_mp_tac >> - fs [invariant_eq] >> + >- (fs [invariant_eq] >> rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> to_fmap_tac) - >- (fs [invariant_eq] >> + >- (first_x_assum inv_mp_tac >> + fs [invariant_eq] >> rw [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> to_fmap_tac)); @@ -2901,6 +2908,17 @@ val splitLookup_thm = Q.store_thm ("splitLookup_thm", rfs [key_ordered_to_fmap, flookup_thm] >> res_tac >> metis_tac [cmp_thms, key_set_cmp_def, key_set_cmp_thm]) + >- (fs [invariant_eq] >> + fmrw [key_set_eq] >> + rfs [key_ordered_to_fmap] >> + res_tac >> + fs [key_set_cmp_def] >> + fmrw [fmap_eq_flookup] >> + every_case_tac >> + fs [] >> + rw [] >> + rfs [key_set_eq] >> + metis_tac [cmp_thms]) >- (`?lt v gt. splitLookup cmp k t' = (lt,v,gt)` by metis_tac [pair_CASES] >> fs [] >> fs [invariant_eq] >> @@ -2924,18 +2942,7 @@ val splitLookup_thm = Q.store_thm ("splitLookup_thm", rfs [key_ordered_to_fmap, flookup_thm] >> fs [key_ordered_to_fmap, flookup_thm] >> res_tac >> - metis_tac [cmp_thms, key_set_cmp_def, key_set_cmp_thm]) - >- (fs [invariant_eq] >> - fmrw [key_set_eq] >> - rfs [key_ordered_to_fmap] >> - res_tac >> - fs [key_set_cmp_def] >> - fmrw [fmap_eq_flookup] >> - every_case_tac >> - fs [] >> - rw [] >> - rfs [key_set_eq] >> - metis_tac [cmp_thms])); + metis_tac [cmp_thms, key_set_cmp_def, key_set_cmp_thm])); val submap'_thm = Q.prove ( `!cmp f t1 t2. @@ -3000,6 +3007,7 @@ val submap'_thm = Q.prove ( res_tac >- (qexists_tac `v''` >> rw []) + >- metis_tac [cmp_thms] >- (rfs [key_ordered_to_fmap] >> `FLOOKUP (to_fmap cmp lt) (key_set cmp k) = NONE` by (fs [FLOOKUP_DEF] >> @@ -3008,18 +3016,17 @@ val submap'_thm = Q.prove ( res_tac >> fs [key_set_cmp_def, key_set_def] >> metis_tac [cmp_thms]) >> - rw []) - >- metis_tac [cmp_thms]) >> + rw [])) >> rw [] >- (first_assum (qspecl_then [`kx`, `x`] assume_tac) >> every_case_tac >> fs [] >- metis_tac [cmp_thms] - >- metis_tac [cmp_thms] >> - imp_res_tac lookup_thm >> - fs [] >> - rfs [] >> - rw []) + >- (imp_res_tac lookup_thm >> + fs [] >> + rfs [] >> + rw []) + >- metis_tac [cmp_thms]) >- (imp_res_tac lookup_thm >> fs [] >> rfs [FLOOKUP_UPDATE] >> @@ -3036,13 +3043,13 @@ val submap'_thm = Q.prove ( res_tac >> fs [key_set_cmp_def, key_set_def] >> metis_tac [cmp_thms]) - >- (`cmp kx k ≠ Equal` by metis_tac [cmp_thms] >> + >- (`cmp kx k = Equal` by metis_tac [cmp_thms] >> fs [FLOOKUP_DEF] >> rfs [key_ordered_to_fmap] >> res_tac >> fs [key_set_cmp_def, key_set_def] >> metis_tac [cmp_thms]) - >- (`cmp kx k = Equal` by metis_tac [cmp_thms] >> + >- (`cmp kx k ≠ Equal` by metis_tac [cmp_thms] >> fs [FLOOKUP_DEF] >> rfs [key_ordered_to_fmap] >> res_tac >> @@ -3062,15 +3069,15 @@ val submap'_thm = Q.prove ( res_tac >> fs [key_set_cmp_def, key_set_def] >> metis_tac [cmp_thms]) - >- (`cmp kx k ≠ Equal` by metis_tac [cmp_thms] >> - fs [FLOOKUP_FUNION] >> - Cases_on `FLOOKUP (to_fmap cmp lt) (key_set cmp k)` >> + >- (`cmp kx k = Equal` by metis_tac [cmp_thms] >> fs [FLOOKUP_DEF] >> rfs [key_ordered_to_fmap] >> res_tac >> fs [key_set_cmp_def, key_set_def] >> metis_tac [cmp_thms]) - >- (`cmp kx k = Equal` by metis_tac [cmp_thms] >> + >- (`cmp kx k ≠ Equal` by metis_tac [cmp_thms] >> + fs [FLOOKUP_FUNION] >> + Cases_on `FLOOKUP (to_fmap cmp lt) (key_set cmp k)` >> fs [FLOOKUP_DEF] >> rfs [key_ordered_to_fmap] >> res_tac >> diff --git a/examples/balanced_bst/comparisonScript.sml b/examples/balanced_bst/comparisonScript.sml index d563a2dd3c..ebb2fddf14 100644 --- a/examples/balanced_bst/comparisonScript.sml +++ b/examples/balanced_bst/comparisonScript.sml @@ -1,5 +1,5 @@ open HolKernel boolLib bossLib BasicProvers; -open optionTheory pairTheory stringTheory listTheory arithmeticTheory; +open optionTheory pairTheory stringTheory listTheory arithmeticTheory totoTheory; open lcsymtacs; val _ = new_theory "comparison"; @@ -7,11 +7,12 @@ val _ = new_theory "comparison"; val _ = temp_tight_equality (); val every_case_tac = BasicProvers.EVERY_CASE_TAC; -val _ = Datatype `comparison = Less | Greater | Equal`; - -val comparison_distinct = fetch "-" "comparison_distinct"; -val comparison_case_def = fetch "-" "comparison_case_def"; -val comparison_nchotomy = fetch "-" "comparison_nchotomy"; +val comparison_distinct = cpn_distinct +val comparison_case_def = cpn_case_def +val comparison_nchotomy = cpn_nchotomy +val _ = Parse.temp_overload_on("Less",``LESS``) +val _ = Parse.temp_overload_on("Equal",``EQUAL``) +val _ = Parse.temp_overload_on("Greater",``GREATER``) val good_cmp_def = Define ` good_cmp cmp ⇔ diff --git a/examples/balanced_bst/osetScript.sml b/examples/balanced_bst/osetScript.sml index e0f1c7a59e..ff3b83c32f 100644 --- a/examples/balanced_bst/osetScript.sml +++ b/examples/balanced_bst/osetScript.sml @@ -8,6 +8,8 @@ val _ = new_theory "oset"; val _ = temp_tight_equality (); +val _ = Parse.temp_overload_on("Equal",``EQUAL``) + (* oset for ordered set *) val _ = type_abbrev ("oset", ``:('a,unit) balanced_map``); From a7c65cf7865374691b18f2ff267de50c59416595 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Sun, 21 Dec 2014 08:32:52 +0000 Subject: [PATCH 065/718] prove TotOrd implies good_cmp --- examples/balanced_bst/comparisonScript.sml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/examples/balanced_bst/comparisonScript.sml b/examples/balanced_bst/comparisonScript.sml index ebb2fddf14..1aecac91ef 100644 --- a/examples/balanced_bst/comparisonScript.sml +++ b/examples/balanced_bst/comparisonScript.sml @@ -35,6 +35,10 @@ val good_cmp_thm = Q.store_thm ("good_cmp_thm", rw [good_cmp_def] >> metis_tac [comparison_distinct, comparison_nchotomy]); +val TotOrd_imp_good_cmp = store_thm("TotOrder_imp_good_cmp", + ``∀cmp. TotOrd cmp ⇒ good_cmp cmp``, + rw[TotOrd,good_cmp_thm] >> metis_tac[]) + val cmp_thms = save_thm ("cmp_thms", LIST_CONJ [comparison_distinct, comparison_case_def, comparison_nchotomy, good_cmp_def]) val option_cmp_def = Define ` From fef315cad9d9c6c9380e4f2bbce1628429d543e7 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Sun, 21 Dec 2014 08:33:40 +0000 Subject: [PATCH 066/718] delete trailing whitespace in examples/balanced_bst --- examples/balanced_bst/balanced_mapScript.sml | 342 +++++++++---------- examples/balanced_bst/comparisonScript.sml | 26 +- examples/balanced_bst/osetScript.sml | 26 +- 3 files changed, 197 insertions(+), 197 deletions(-) diff --git a/examples/balanced_bst/balanced_mapScript.sml b/examples/balanced_bst/balanced_mapScript.sml index eaee1364f6..568c562e1a 100644 --- a/examples/balanced_bst/balanced_mapScript.sml +++ b/examples/balanced_bst/balanced_mapScript.sml @@ -19,9 +19,9 @@ val comparison_case_def = totoTheory.cpn_case_def val comparison_nchotomy = totoTheory.cpn_nchotomy val list_rel_lem1 = Q.prove ( -`!f l l'. - ~LIST_REL f l l' - ⇒ +`!f l l'. + ~LIST_REL f l l' + ⇒ ∃n. n ≤ LENGTH l ∧ n ≤ LENGTH l' ∧ LIST_REL f (TAKE n l) (TAKE n l') ∧ ((n = LENGTH l ∧ n ≠ LENGTH l') ∨ (n ≠ LENGTH l ∧ n = LENGTH l') ∨ @@ -56,18 +56,18 @@ val list_rel_lem1 = Q.prove ( CCONTR_TAC >> fs [] >> `LIST_REL f (TAKE (max_nset + 1) l) (TAKE (max_nset + 1) l')` - by (fs [rich_listTheory.TAKE_EL_SNOC, SNOC_APPEND, + by (fs [rich_listTheory.TAKE_EL_SNOC, SNOC_APPEND, rich_listTheory.LIST_REL_APPEND_SING]) >> - `max_nset + 1 ∈ {n | (n < LENGTH l ∨ n = LENGTH l) ∧ (n < LENGTH l' ∨ n = LENGTH l') ∧ LIST_REL f (TAKE n l) (TAKE n l')}` + `max_nset + 1 ∈ {n | (n < LENGTH l ∨ n = LENGTH l) ∧ (n < LENGTH l' ∨ n = LENGTH l') ∧ LIST_REL f (TAKE n l) (TAKE n l')}` by srw_tac [ARITH_ss] [] >> imp_res_tac in_max_set >> unabbrev_all_tac >> decide_tac)); val list_rel_lem2 = Q.prove ( -`!l l'. - LIST_REL f l l' - ⇒ +`!l l'. + LIST_REL f l l' + ⇒ ¬∃n. n ≤ LENGTH l ∧ n ≤ LENGTH l' ∧ LIST_REL f (TAKE n l) (TAKE n l') ∧ ((n = LENGTH l ∧ n ≠ LENGTH l') ∨ (n ≠ LENGTH l ∧ n = LENGTH l') ∨ @@ -101,7 +101,7 @@ val list_rel_thm = Q.prove ( LIST_REL f l l' ⇔ !n. ¬(n ≤ LENGTH l) ∨ ¬(n ≤ LENGTH l') ∨ ¬LIST_REL f (TAKE n l) (TAKE n l') ∨ - (n ≠ LENGTH l ∨ n = LENGTH l') ∧ + (n ≠ LENGTH l ∨ n = LENGTH l') ∧ (n = LENGTH l ∨ n ≠ LENGTH l') ∧ (n = LENGTH l ∨ n = LENGTH l' ∨ f (EL n l) (EL n l'))`, rw [] >> @@ -120,7 +120,7 @@ val list_rel_thm = Q.prove ( (n ≠ LENGTH l ∧ n ≠ LENGTH l' ∧ f (EL n l) (EL n l'))`, metis_tac [list_rel_thm]); -val _ = bossLib.augment_srw_ss [rewrites +val _ = bossLib.augment_srw_ss [rewrites [FUNION_FUPDATE_1,FUNION_ASSOC,FUNION_FEMPTY_2,FUNION_FEMPTY_1,FDOM_DRESTRICT, DRESTRICT_UNIV]] @@ -140,7 +140,7 @@ in ONCE_REWRITE_TAC [thm] g end -val inv_mp_tac = let +val inv_mp_tac = let val lemma = PROVE [] ``!A B C D. (A ⇒ B ∧ C) ⇒ (A ∧ (B ∧ C ⇒ D)) ⇒ (B ∧ D)`` in fn th => fn (g as (asl,w)) => let @@ -151,9 +151,9 @@ in val s = fst (match_term tm tm2) val th2 = SPECL (map (Term.subst s) xs) th val th3 = MATCH_MP lemma th2 - in + in MATCH_MP_TAC (GEN_ALL th3) g - end + end end val fdom_eq = PROVE [] ``m1 = m2 ⇒ FDOM m1 = FDOM m2``; @@ -209,7 +209,7 @@ key_set cmp k = { k' | cmp k k' = Equal }`; val key_set_equiv = Q.store_thm ("key_set_equiv", `!cmp. - good_cmp cmp + good_cmp cmp ⇒ (!k. k ∈ key_set cmp k) ∧ (!k1 k2. k1 ∈ key_set cmp k2 ⇒ k2 ∈ key_set cmp k1) ∧ @@ -220,8 +220,8 @@ val key_set_equiv = Q.store_thm ("key_set_equiv", val key_set_partition = Q.store_thm ("key_set_partition", `!cmp k1 k2. good_cmp cmp ∧ - key_set cmp k1 ≠ key_set cmp k2 - ⇒ + key_set cmp k1 ≠ key_set cmp k2 + ⇒ DISJOINT (key_set cmp k1) (key_set cmp k2)`, rw [DISJOINT_DEF, EXTENSION] >> metis_tac [key_set_equiv]); @@ -239,7 +239,7 @@ key_set_cmp cmp k ks res ⇔ !k'. k' ∈ ks ⇒ cmp k k' = res`; val key_set_cmp_thm = Q.store_thm ("key_set_cmp_thm", -`!cmp k k' res. +`!cmp k k' res. good_cmp cmp ⇒ (key_set_cmp cmp k (key_set cmp k') res ⇔ cmp k k' = res)`, @@ -251,7 +251,7 @@ key_set_cmp2 cmp ks1 ks2 res ⇔ !k1 k2. k1 ∈ ks1 ∧ k2 ∈ ks2 ⇒ cmp k1 k2 = res`; val key_set_cmp2_thm = Q.store_thm ("key_set_cmp2_thm", -`!cmp k k' res. +`!cmp k k' res. good_cmp cmp ⇒ (key_set_cmp2 cmp (key_set cmp k) (key_set cmp k') res ⇔ cmp k k' = res)`, @@ -260,7 +260,7 @@ val key_set_cmp2_thm = Q.store_thm ("key_set_cmp2_thm", (* Maps based on balanced binary trees. Copied from ghc-7.8.3 * libraries/containers/Data/Map/Base.hs. It starts with the following comment: - + ----------------------------------------------------------------------------- -- | -- Module : Data.Map.Base @@ -298,7 +298,7 @@ val key_set_cmp2_thm = Q.store_thm ("key_set_cmp2_thm", -- the Big-O notation . ----------------------------------------------------------------------------- -*) +*) val _ = Datatype ` balanced_map = Tip | Bin num 'k 'v balanced_map balanced_map`; @@ -344,9 +344,9 @@ singleton k x = Bin 1 k x Tip Tip`; (* Just like the Haskell, but w/o @ patterns *) val balanceL'_def = Define ` -balanceL' k x l r = +balanceL' k x l r = case r of - | Tip => + | Tip => (case l of | Tip => Bin 1 k x Tip Tip | (Bin _ _ _ Tip Tip) => Bin 2 k x l Tip @@ -355,7 +355,7 @@ balanceL' k x l r = | (Bin ls lk lx (Bin lls k' v' l' r') (Bin lrs lrk lrx lrl lrr)) => if lrs < ratio*lls then Bin (1+ls) lk lx (Bin lls k' v' l' r') (Bin (1+lrs) k x (Bin lrs lrk lrx lrl lrr) Tip) else Bin (1+ls) lrk lrx (Bin (1+lls+size lrl) lk lx (Bin lls k' v' l' r') lrl) (Bin (1+size lrr) k x lrr Tip)) - | (Bin rs _ _ _ _) => + | (Bin rs _ _ _ _) => case l of | Tip => Bin (1+rs) k x Tip r | (Bin ls lk lx ll lr) => @@ -368,7 +368,7 @@ balanceL' k x l r = else Bin (1+ls+rs) k x l r`; val balanceR'_def = Define ` -balanceR' k x l r = +balanceR' k x l r = case l of | Tip => (case r of @@ -379,7 +379,7 @@ balanceR' k x l r = | (Bin rs rk rx (Bin rls rlk rlx rll rlr) (Bin rrs k' v' l' r')) => if rls < ratio*rrs then Bin (1+rs) rk rx (Bin (1+rls) k x Tip (Bin rls rlk rlx rll rlr)) (Bin rrs k' v' l' r') else Bin (1+rs) rlk rlx (Bin (1+size rll) k x Tip rll) (Bin (1+rrs+size rlr) rk rx rlr (Bin rrs k' v' l' r'))) - | (Bin ls _ _ _ _) => + | (Bin ls _ _ _ _) => case r of | Tip => Bin (1+ls) k x l Tip | (Bin rs rk rx rl rr) => @@ -392,38 +392,38 @@ balanceR' k x l r = else Bin (1+ls+rs) k x l r`; val balanceL_def = Define ` -(balanceL k x Tip Tip = +(balanceL k x Tip Tip = Bin 1 k x Tip Tip) ∧ -(balanceL k x (Bin s' k' v' Tip Tip) Tip = +(balanceL k x (Bin s' k' v' Tip Tip) Tip = Bin 2 k x (Bin s' k' v' Tip Tip) Tip) ∧ (balanceL k x (Bin _ lk lx Tip (Bin _ lrk lrx _ _)) Tip = Bin 3 lrk lrx (Bin 1 lk lx Tip Tip) (Bin 1 k x Tip Tip)) ∧ (balanceL k x (Bin _ lk lx (Bin s' k' v' l' r') Tip) Tip = Bin 3 lk lx (Bin s' k' v' l' r') (Bin 1 k x Tip Tip)) ∧ (balanceL k x (Bin ls lk lx (Bin lls k' v' l' r') (Bin lrs lrk lrx lrl lrr)) Tip = - if lrs < ratio*lls then - Bin (1+ls) lk lx (Bin lls k' v' l' r') + if lrs < ratio*lls then + Bin (1+ls) lk lx (Bin lls k' v' l' r') (Bin (1+lrs) k x (Bin lrs lrk lrx lrl lrr) Tip) - else - Bin (1+ls) lrk lrx (Bin (1+lls+size lrl) lk lx (Bin lls k' v' l' r') lrl) + else + Bin (1+ls) lrk lrx (Bin (1+lls+size lrl) lk lx (Bin lls k' v' l' r') lrl) (Bin (1+size lrr) k x lrr Tip)) ∧ -(balanceL k x Tip (Bin rs k' v' l' r') = +(balanceL k x Tip (Bin rs k' v' l' r') = Bin (1+rs) k x Tip (Bin rs k' v' l' r')) ∧ (balanceL k x (Bin ls lk lx ll lr) (Bin rs k' v' l' r') = if ls > delta*rs then case (ll, lr) of | (Bin lls _ _ _ _, Bin lrs lrk lrx lrl lrr) => - if lrs < ratio*lls then + if lrs < ratio*lls then Bin (1+ls+rs) lk lx ll (Bin (1+rs+lrs) k x lr (Bin rs k' v' l' r')) - else - Bin (1+ls+rs) lrk lrx (Bin (1+lls+size lrl) lk lx ll lrl) + else + Bin (1+ls+rs) lrk lrx (Bin (1+lls+size lrl) lk lx ll lrl) (Bin (1+rs+size lrr) k x lrr (Bin rs k' v' l' r')) | (_, _) => Tip (* error "Failure in Data.Map.balanceL" *) - else + else Bin (1+ls+rs) k x (Bin ls lk lx ll lr) (Bin rs k' v' l' r'))`; val balanceR_def = Define ` -(balanceR k x Tip Tip = +(balanceR k x Tip Tip = Bin 1 k x Tip Tip) ∧ (balanceR k x Tip (Bin s' k' v' Tip Tip) = Bin 2 k x Tip (Bin s' k' v' Tip Tip)) ∧ @@ -432,10 +432,10 @@ val balanceR_def = Define ` (balanceR k x Tip (Bin _ rk rx (Bin _ rlk rlx _ _) Tip) = Bin 3 rlk rlx (Bin 1 k x Tip Tip) (Bin 1 rk rx Tip Tip)) ∧ (balanceR k x Tip (Bin rs rk rx (Bin rls rlk rlx rll rlr) (Bin rrs k' v' l' r')) = - if rls < ratio*rrs then + if rls < ratio*rrs then Bin (1+rs) rk rx (Bin (1+rls) k x Tip (Bin rls rlk rlx rll rlr)) (Bin rrs k' v' l' r') - else - Bin (1+rs) rlk rlx (Bin (1+size rll) k x Tip rll) + else + Bin (1+rs) rlk rlx (Bin (1+size rll) k x Tip rll) (Bin (1+rrs+size rlr) rk rx rlr (Bin rrs k' v' l' r'))) ∧ (balanceR k x (Bin ls k' v' l' r') Tip = Bin (1+ls) k x (Bin ls k' v' l' r') Tip) ∧ @@ -443,10 +443,10 @@ val balanceR_def = Define ` if rs > delta*ls then case (rl, rr) of | (Bin rls rlk rlx rll rlr, Bin rrs _ _ _ _) => - if rls < ratio*rrs then + if rls < ratio*rrs then Bin (1+ls+rs) rk rx (Bin (1+ls+rls) k x (Bin ls k' v' l' r') rl) rr - else - Bin (1+ls+rs) rlk rlx (Bin (1+ls+size rll) k x (Bin ls k' v' l' r') rll) + else + Bin (1+ls+rs) rlk rlx (Bin (1+ls+size rll) k x (Bin ls k' v' l' r') rll) (Bin (1+rrs+size rlr) rk rx rlr rr) | (_, _) => Tip (* error "Failure in Data.Map.balanceR" *) else @@ -479,7 +479,7 @@ val insertMin_def = Define ` val deleteFindMax_def = Define ` (deleteFindMax (Bin s k x l Tip) = ((k,x),l)) ∧ (deleteFindMax (Bin s k x l r) = - let (km,r') = deleteFindMax r in + let (km,r') = deleteFindMax r in (km,balanceL k x l r')) ∧ (deleteFindMax Tip = (ARB,Tip))`; (*(error "Map.deleteFindMax: can not return the maximal element of an empty map", Tip)*) @@ -487,7 +487,7 @@ val deleteFindMax_def = Define ` val deleteFindMin_def = Define ` (deleteFindMin (Bin s k x Tip r) = ((k,x),r)) ∧ (deleteFindMin (Bin s k x l r) = - let (km,l') = deleteFindMin l in + let (km,l') = deleteFindMin l in (km,balanceR k x l' r)) ∧ (deleteFindMin Tip = (ARB,Tip))`; (*(error "Map.deleteFindMin: can not return the maximal element of an empty map", Tip)*) @@ -497,10 +497,10 @@ val glue_def = Define ` (glue l Tip = l) ∧ (glue l r = if size l > size r then - let ((km,m),l') = deleteFindMax l in + let ((km,m),l') = deleteFindMax l in balanceR km m l' r else - let ((km,m),r') = deleteFindMin r in + let ((km,m),r') = deleteFindMin r in balanceL km m l r')`; val delete_def = Define ` @@ -512,7 +512,7 @@ val delete_def = Define ` | Eq => glue l r)`; val trim_help_greater_def = Define ` -(trim_help_greater cmp lo (Bin s' k v' l' r) = +(trim_help_greater cmp lo (Bin s' k v' l' r) = if cmp k lo = Less ∨ cmp k lo = Equal then trim_help_greater cmp lo r else @@ -520,7 +520,7 @@ val trim_help_greater_def = Define ` (trim_help_greater cmp lo Tip = Tip)`; val trim_help_lesser_def = Define ` -(trim_help_lesser cmp hi (Bin s' k v' l r') = +(trim_help_lesser cmp hi (Bin s' k v' l r') = if cmp k hi = Greater ∨ cmp k hi = Equal then trim_help_lesser cmp hi l else @@ -528,7 +528,7 @@ val trim_help_lesser_def = Define ` (trim_help_lesser cmp lo Tip = Tip)`; val trim_help_middle_def = Define ` -(trim_help_middle cmp lo hi (Bin s' k v' l r) = +(trim_help_middle cmp lo hi (Bin s' k v' l r) = if cmp k lo = Less ∨ cmp k lo = Equal then trim_help_middle cmp lo hi r else if cmp k hi = Greater ∨ cmp k hi = Equal then @@ -580,7 +580,7 @@ val filterGt_def = Define ` val hedgeUnion_def = Define ` (hedgeUnion cmp blo bhi t1 Tip = t1) ∧ -(hedgeUnion cmp blo bhi Tip (Bin _ kx x l r) = +(hedgeUnion cmp blo bhi Tip (Bin _ kx x l r) = link kx x (filterGt cmp blo l) (filterLt cmp bhi r)) ∧ (hedgeUnion cmp blo bhi t1 (Bin _ kx x Tip Tip) = insertR cmp kx x t1) ∧ (hedgeUnion cmp blo bhi (Bin s kx x l r) t2 = @@ -594,7 +594,7 @@ val union_def = Define ` val foldrWithKey_def = Define ` (foldrWithKey f z' Tip = z') ∧ -(foldrWithKey f z' (Bin _ kx x l r) = +(foldrWithKey f z' (Bin _ kx x l r) = foldrWithKey f (f kx x (foldrWithKey f z' r)) l)`; val toAscList_def = Define ` @@ -611,21 +611,21 @@ val splitLookup_def = Define ` (splitLookup cmp k Tip = (Tip,NONE,Tip)) ∧ (splitLookup cmp k (Bin _ kx x l r) = case cmp k kx of - | Less => + | Less => let (lt,z,gt) = splitLookup cmp k l in let gt' = link kx x gt r in (lt,z,gt') - | Greater => + | Greater => let (lt,z,gt) = splitLookup cmp k r in let lt' = link kx x l lt in (lt',z,gt) - | Equal => + | Equal => (l,SOME x,r))`; val submap'_def = Define ` (submap' cmp _ Tip _ = T) ∧ (submap' cmp _ _ Tip = F) ∧ -(submap' cmp f (Bin _ kx x l r) t = +(submap' cmp f (Bin _ kx x l r) t = case splitLookup cmp kx t of | (lt,NONE,gt) => F | (lt,SOME y,gt) => f x y ∧ submap' cmp f l lt ∧ submap' cmp f r gt)`; @@ -677,7 +677,7 @@ val structure_size_def = Define ` val key_ordered_def = Define ` (key_ordered cmp k Tip res ⇔ T) ∧ -(key_ordered cmp k (Bin n k' v l r) res ⇔ +(key_ordered cmp k (Bin n k' v l r) res ⇔ cmp k k' = res ∧ key_ordered cmp k l res ∧ key_ordered cmp k r res)`; @@ -775,7 +775,7 @@ val lookup_thm = Q.store_thm ("lookup_thm", fs [] >> rw [] >> rfs [key_set_eq] >> - fs [FLOOKUP_DEF] >> + fs [FLOOKUP_DEF] >> metis_tac [cmp_thms]); val member_thm = Q.store_thm ("member_thm", @@ -814,11 +814,11 @@ val singleR_def = Define ` singleR k1 x1 (Bin _ k2 x2 t1 t2) t3 = bin k2 x2 t1 (bin k1 x1 t2 t3)`; val doubleL_def = Define ` -doubleL k1 x1 t1 (Bin _ k2 x2 (Bin _ k3 x3 t2 t3) t4) = +doubleL k1 x1 t1 (Bin _ k2 x2 (Bin _ k3 x3 t2 t3) t4) = bin k3 x3 (bin k1 x1 t1 t2) (bin k2 x2 t3 t4)`; val doubleR_def = Define ` -doubleR k1 x1 (Bin _ k2 x2 t1 (Bin _ k3 x3 t2 t3)) t4 = +doubleR k1 x1 (Bin _ k2 x2 t1 (Bin _ k3 x3 t2 t3)) t4 = bin k3 x3 (bin k2 x2 t1 t2) (bin k1 x1 t3 t4)`; val rotateL_def = Define ` @@ -827,7 +827,7 @@ val rotateL_def = Define ` singleL k x l (Bin s' k' x' ly ry) else doubleL k x l (Bin s' k' x' ly ry)) ∧ -(rotateL k x l Tip = +(rotateL k x l Tip = doubleL k x l Tip)`; val rotateR_def = Define ` @@ -836,7 +836,7 @@ val rotateR_def = Define ` singleR k x (Bin s' k' x' ly ry) r else doubleR k x (Bin s' k' x' ly ry) r) ∧ -(rotateR k x Tip r = +(rotateR k x Tip r = doubleR k x Tip r)`; val bal_def = Define ` @@ -849,7 +849,7 @@ bal k x l r = rotateR k x l r else Bin (size l + size r + 1) k x l r`; - + val balL_def = Define ` balL k x l r = if size l + size r ≤ 1 then @@ -868,7 +868,7 @@ balR k x l r = else Bin (size l + size r + 1) k x l r`; -(* We want a formula that states how unbalanced two trees can be +(* We want a formula that states how unbalanced two trees can be * and still be re-balanced by the balancer. It also has to allow the * trees to be as unbalanced as the link, insert and delete functions need. The * formula below is the result of guesswork. *) @@ -899,7 +899,7 @@ val balanced_lem1 = Q.prove ( rw [balanced_def]); val balanced_lem2 = Q.prove ( -`!l r. +`!l r. ¬(l > delta * r) ∧ almost_balancedL l r ∧ ¬(l + r ≤ 1) @@ -914,7 +914,7 @@ val balanced_lem3 = Q.prove ( b0 < ratio * b ∧ balanced b b0 ⇒ - balanced b (b0 + r + 1) ∧ + balanced b (b0 + r + 1) ∧ balanced b0 r`, rw [almost_balancedL_def, balanced_def, TIMES_MIN, delta_def, ratio_def] >> fs [MIN_DEF]); @@ -934,7 +934,7 @@ val balanced_lem4 = Q.prove ( fs [MIN_DEF]); val balanced_lem5 = Q.prove ( -`!l r. +`!l r. ¬(r > delta * l) ∧ almost_balancedR l r ⇒ @@ -979,7 +979,7 @@ val singleR_thm = Q.prove ( invariant cmp r ⇒ invariant cmp (singleR k v (Bin n k' v' b b0) r) ∧ - to_fmap cmp (singleR k v (Bin n k' v' b b0) r) = + to_fmap cmp (singleR k v (Bin n k' v' b b0) r) = (FUNION (to_fmap cmp (Bin n k' v' b b0)) (to_fmap cmp r)) |+ (key_set cmp k,v)`, rw [singleR_def] >> imp_res_tac inv_props @@ -1006,12 +1006,12 @@ val doubleR_thm = Q.prove ( invariant cmp r ⇒ invariant cmp (doubleR k v (Bin n k' v' b b0) r) ∧ - to_fmap cmp (doubleR k v (Bin n k' v' b b0) r) = + to_fmap cmp (doubleR k v (Bin n k' v' b b0) r) = (FUNION (to_fmap cmp (Bin n k' v' b b0)) (to_fmap cmp r)) |+ (key_set cmp k,v)`, rw [] >> - `structure_size b0 ≠ 0` - by (fs [delta_def, ratio_def, invariant_def, size_def, - NOT_LESS_EQUAL, NOT_LESS, NOT_GREATER] >> + `structure_size b0 ≠ 0` + by (fs [delta_def, ratio_def, invariant_def, size_def, + NOT_LESS_EQUAL, NOT_LESS, NOT_GREATER] >> imp_res_tac structure_size_thm >> fs []) >> Cases_on `b0` >> @@ -1036,9 +1036,9 @@ val doubleR_thm = Q.prove ( rfs [key_ordered_to_fmap] >- metis_tac [cmp_thms] >- metis_tac [cmp_thms] >> - `key_set cmp k' ≠ key_set cmp k'' ∧ - key_set cmp k ≠ key_set cmp k' ∧ - key_set cmp k ≠ key_set cmp k''` + `key_set cmp k' ≠ key_set cmp k'' ∧ + key_set cmp k ≠ key_set cmp k' ∧ + key_set cmp k ≠ key_set cmp k''` by metis_tac [key_set_eq, cmp_thms] >> metis_tac [FUPDATE_COMMUTES, FUNION_ASSOC])); @@ -1054,7 +1054,7 @@ val rotateR_thm = Q.prove ( invariant cmp r ⇒ invariant cmp (rotateR k v l r) ∧ - to_fmap cmp (rotateR k v l r) = + to_fmap cmp (rotateR k v l r) = (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, Cases_on `l` >- fs [size_def] >> @@ -1065,7 +1065,7 @@ val balanceL_balL = Q.prove ( `!k v l r cmp. good_cmp cmp ∧ invariant cmp l ∧ - invariant cmp r + invariant cmp r ⇒ balanceL k v l r = balL k v l r`, ho_match_mp_tac balanceL_ind >> @@ -1095,7 +1095,7 @@ val balanceL_thm = Q.prove ( invariant cmp r ⇒ invariant cmp (balanceL k v l r) ∧ - to_fmap cmp (balanceL k v l r) = + to_fmap cmp (balanceL k v l r) = (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, rw [] >> `balanceL k v l r = balL k v l r` by metis_tac [balanceL_balL] >> @@ -1118,7 +1118,7 @@ val singleL_thm = Q.prove ( invariant cmp l ⇒ invariant cmp (singleL k v l (Bin n k' v' b b0)) ∧ - to_fmap cmp (singleL k v l (Bin n k' v' b b0)) = + to_fmap cmp (singleL k v l (Bin n k' v' b b0)) = (FUNION (to_fmap cmp l) (to_fmap cmp (Bin n k' v' b b0))) |+ (key_set cmp k,v)`, rw [singleL_def] >> imp_res_tac inv_props @@ -1146,12 +1146,12 @@ val doubleL_thm = Q.prove ( invariant cmp l ⇒ invariant cmp (doubleL k v l (Bin n k' v' b b0)) ∧ - to_fmap cmp (doubleL k v l (Bin n k' v' b b0)) = + to_fmap cmp (doubleL k v l (Bin n k' v' b b0)) = (FUNION (to_fmap cmp l) (to_fmap cmp (Bin n k' v' b b0))) |+ (key_set cmp k,v)`, rw [] >> - `structure_size b ≠ 0` - by (fs [delta_def, ratio_def, invariant_def, size_def, - NOT_LESS_EQUAL, NOT_LESS, NOT_GREATER] >> + `structure_size b ≠ 0` + by (fs [delta_def, ratio_def, invariant_def, size_def, + NOT_LESS_EQUAL, NOT_LESS, NOT_GREATER] >> imp_res_tac structure_size_thm >> fs []) >> Cases_on `b` >> @@ -1181,9 +1181,9 @@ val doubleL_thm = Q.prove ( >- metis_tac [cmp_thms] >- metis_tac [cmp_thms] >- metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms] - >- (`key_set cmp k' ≠ key_set cmp k'' ∧ - key_set cmp k ≠ key_set cmp k' ∧ - key_set cmp k ≠ key_set cmp k''` + >- (`key_set cmp k' ≠ key_set cmp k'' ∧ + key_set cmp k ≠ key_set cmp k' ∧ + key_set cmp k ≠ key_set cmp k''` by metis_tac [key_set_eq, cmp_thms] >> metis_tac [FUPDATE_COMMUTES, FUNION_ASSOC]))); @@ -1199,7 +1199,7 @@ val rotateL_thm = Q.prove ( invariant cmp r ⇒ invariant cmp (rotateL k v l r) ∧ - to_fmap cmp (rotateL k v l r) = + to_fmap cmp (rotateL k v l r) = (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, Cases_on `r` >- fs [size_def] >> @@ -1210,7 +1210,7 @@ val balanceR_balR = Q.prove ( `!k v l r cmp. good_cmp cmp ∧ invariant cmp l ∧ - invariant cmp r + invariant cmp r ⇒ balanceR k v l r = balR k v l r`, ho_match_mp_tac balanceR_ind >> @@ -1241,7 +1241,7 @@ val balanceR_thm = Q.prove ( invariant cmp r ⇒ invariant cmp (balanceR k v l r) ∧ - to_fmap cmp (balanceR k v l r) = + to_fmap cmp (balanceR k v l r) = (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, rw [] >> `balanceR k v l r = balR k v l r` by metis_tac [balanceR_balR] >> @@ -1251,8 +1251,8 @@ val balanceR_thm = Q.prove ( metis_tac [rotateL_thm]); val almost_balancedL_thm = Q.prove ( -`!l r. - balanced l r ⇒ +`!l r. + balanced l r ⇒ almost_balancedL l r ∧ almost_balancedL (l + 1) r ∧ almost_balancedL l (r - 1)`, rw [almost_balancedL_def] >> fs [balanced_def, NOT_LESS_EQUAL, TIMES_MIN] >> @@ -1263,8 +1263,8 @@ val almost_balancedL_thm = Q.prove ( fs [delta_def, MIN_DEF]); val almost_balancedR_thm = Q.prove ( -`!l r. - balanced l r ⇒ +`!l r. + balanced l r ⇒ almost_balancedR l r ∧ almost_balancedR l (r + 1) ∧ almost_balancedR (l - 1) r`, rw [almost_balancedR_def] >> fs [balanced_def, NOT_LESS_EQUAL, TIMES_MIN] >> @@ -1285,7 +1285,7 @@ val insert_thm = Q.store_thm ("insert_thm", invariant cmp (insert cmp k v t) ∧ to_fmap cmp (insert cmp k v t) = to_fmap cmp t |+ (key_set cmp k,v)`, Induct_on `t` - >- fs [insert_def, singleton_def, to_fmap_def, invariant_eq, + >- fs [insert_def, singleton_def, to_fmap_def, invariant_eq, structure_size_def, balanced_def, size_def, key_ordered_def] >> simp [invariant_eq] >> rpt gen_tac >> @@ -1335,10 +1335,10 @@ val insertR_thm = Q.store_thm ("insertR_thm", invariant cmp t ⇒ invariant cmp (insertR cmp k v t) ∧ - to_fmap cmp (insertR cmp k v t) = + to_fmap cmp (insertR cmp k v t) = if key_set cmp k ∈ FDOM (to_fmap cmp t) then to_fmap cmp t else to_fmap cmp t |+ (key_set cmp k,v)`, Induct_on `t` - >- fs [insertR_def, singleton_def, to_fmap_def, invariant_def, + >- fs [insertR_def, singleton_def, to_fmap_def, invariant_def, structure_size_def, balanced_def, size_def, key_ordered_def] >> rpt gen_tac >> strip_tac >> @@ -1347,12 +1347,12 @@ val insertR_thm = Q.store_thm ("insertR_thm", Cases_on `cmp k k'` >> fs [] >> simp [to_fmap_def] - >- (`almost_balancedL (size (insertR cmp k v t)) (size t')` + >- (`almost_balancedL (size (insertR cmp k v t)) (size t')` by (imp_res_tac size_thm >> rw [FCARD_FUPDATE] >> fs [key_ordered_to_fmap] >> metis_tac [almost_balancedL_thm]) >> - `key_ordered cmp k' (insertR cmp k v t) Greater` + `key_ordered cmp k' (insertR cmp k v t) Greater` by (rfs [key_ordered_to_fmap] >> rw [] >> rw [key_set_cmp_thm] >> @@ -1364,12 +1364,12 @@ val insertR_thm = Q.store_thm ("insertR_thm", >- (fs [invariant_def] >> rfs [key_ordered_to_fmap] >> metis_tac [to_fmap_key_set, key_set_cmp_thm, cmp_thms,key_set_eq, FUPDATE_EQ]) - >- (`almost_balancedR (size t) (size (insertR cmp k v t'))` + >- (`almost_balancedR (size t) (size (insertR cmp k v t'))` by (imp_res_tac size_thm >> rw [FCARD_FUPDATE] >> fs [key_ordered_to_fmap] >> metis_tac [almost_balancedR_thm]) >> - `key_ordered cmp k' (insertR cmp k v t') Less` + `key_ordered cmp k' (insertR cmp k v t') Less` by (fs [key_ordered_to_fmap] >> rw [] >> imp_res_tac to_fmap_key_set >> @@ -1390,7 +1390,7 @@ val insertMax_thm = Q.store_thm ("insertMax_thm", invariant cmp (insertMax k v t) ∧ to_fmap cmp (insertMax k v t) = to_fmap cmp t |+ (key_set cmp k,v)`, Induct_on `t` - >- fs [insertMax_def, singleton_def, to_fmap_def, invariant_def, + >- fs [insertMax_def, singleton_def, to_fmap_def, invariant_def, structure_size_def, balanced_def, size_def, key_ordered_def] >> rpt gen_tac >> strip_tac >> @@ -1416,18 +1416,18 @@ val insertMin_thm = Q.store_thm ("insertMin_thm", invariant cmp (insertMin k v t) ∧ to_fmap cmp (insertMin k v t) = to_fmap cmp t |+ (key_set cmp k,v)`, Induct_on `t` - >- fs [insertMin_def, singleton_def, to_fmap_def, invariant_def, + >- fs [insertMin_def, singleton_def, to_fmap_def, invariant_def, structure_size_def, balanced_def, size_def, key_ordered_def] >> rpt gen_tac >> strip_tac >> fs [insertMin_def, invariant_def, to_fmap_def] >> simp [] >> - `almost_balancedL (size (insertMin k v t)) (size t')` + `almost_balancedL (size (insertMin k v t)) (size t')` by (imp_res_tac size_thm >> rw [FCARD_FUPDATE] >> fs [key_ordered_to_fmap] >> metis_tac [almost_balancedL_thm]) >> - `key_ordered cmp k' (insertMin k v t) Greater` + `key_ordered cmp k' (insertMin k v t) Greater` by (rfs [key_ordered_to_fmap] >> rw [] >> imp_res_tac to_fmap_key_set >> @@ -1448,7 +1448,7 @@ val deleteFindMin_thm = Q.store_thm ("deleteFindMin", invariant cmp t' ∧ key_ordered cmp k t' Less ∧ FLOOKUP (to_fmap cmp t) (key_set cmp k) = SOME v ∧ - to_fmap cmp t' = + to_fmap cmp t' = DRESTRICT (to_fmap cmp t) (FDOM (to_fmap cmp t) DELETE key_set cmp k)`, ho_match_mp_tac (fetch "-" "deleteFindMin_ind") >> rpt conj_tac >> @@ -1468,7 +1468,7 @@ val deleteFindMin_thm = Q.store_thm ("deleteFindMin", metis_tac [comparison_distinct, good_cmp_def]) >> `?km l. deleteFindMin (Bin (structure_size v8 + (structure_size v9 + 1)) v6 v7 v8 v9) = (km,l)` by metis_tac [pairTheory.pair_CASES] >> - fs [] >> + fs [] >> rpt BasicProvers.VAR_EQ_TAC >> inv_mp_tac balanceR_thm >> simp [] >> @@ -1508,7 +1508,7 @@ val deleteFindMin_thm = Q.store_thm ("deleteFindMin", rfs [key_ordered_to_fmap] >> rw [] >> metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm]) - >- (`key_set cmp k' ∈ FDOM (to_fmap cmp v8 ⊌ to_fmap cmp v9)` + >- (`key_set cmp k' ∈ FDOM (to_fmap cmp v8 ⊌ to_fmap cmp v9)` by (every_case_tac >> fs [FLOOKUP_DEF]) >> `key_set cmp k ≠ key_set cmp k' ∧ cmp k' k = Less` @@ -1530,19 +1530,19 @@ val deleteFindMin_thm = Q.store_thm ("deleteFindMin", >- (imp_res_tac size_thm >> rw [FCARD_FUPDATE, FDOM_DRESTRICT] >> rw [FCARD_DRESTRICT, DELETE_INSERT] >> - `(FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)) ∩ + `(FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)) ∩ (key_set cmp v6 INSERT FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9) DELETE key_set cmp k') = FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9) DELETE key_set cmp k'` - by (rw [EXTENSION] >> + by (rw [EXTENSION] >> metis_tac [key_set_eq, EXTENSION]) >> simp [CARD_UNION_EQN] >> fs [DISJOINT_DEF] >| - [`CARD (FDOM (to_fmap cmp v8)) ≠ 0` + [`CARD (FDOM (to_fmap cmp v8)) ≠ 0` by (rw [CARD_EQ_0, EXTENSION] >> metis_tac []) >> `0 < CARD (FDOM (to_fmap cmp v8))` by decide_tac, - `CARD (FDOM (to_fmap cmp v9)) ≠ 0` + `CARD (FDOM (to_fmap cmp v9)) ≠ 0` by (rw [CARD_EQ_0, EXTENSION] >> metis_tac []) >> `0 < CARD (FDOM (to_fmap cmp v9))` by decide_tac] >> @@ -1575,7 +1575,7 @@ val deleteFindMax_thm = Q.store_thm ("deleteFindMax", invariant cmp t' ∧ key_ordered cmp k t' Greater ∧ FLOOKUP (to_fmap cmp t) (key_set cmp k) = SOME v ∧ - to_fmap cmp t' = + to_fmap cmp t' = DRESTRICT (to_fmap cmp t) (FDOM (to_fmap cmp t) DELETE key_set cmp k)`, ho_match_mp_tac (fetch "-" "deleteFindMax_ind") >> rpt conj_tac >> @@ -1595,7 +1595,7 @@ val deleteFindMax_thm = Q.store_thm ("deleteFindMax", metis_tac [comparison_distinct, good_cmp_def]) >> `?km l. deleteFindMax (Bin (structure_size v8 + (structure_size v9 + 1)) v6 v7 v8 v9) = (km,l)` by metis_tac [pairTheory.pair_CASES] >> - fs [] >> + fs [] >> rpt BasicProvers.VAR_EQ_TAC >> inv_mp_tac balanceL_thm >> simp [] >> @@ -1635,7 +1635,7 @@ val deleteFindMax_thm = Q.store_thm ("deleteFindMax", rfs [key_ordered_to_fmap] >> rw [] >> metis_tac [cmp_thms, key_set_eq, key_set_cmp_thm]) - >- (`key_set cmp k' ∈ FDOM (to_fmap cmp v8 ⊌ to_fmap cmp v9)` + >- (`key_set cmp k' ∈ FDOM (to_fmap cmp v8 ⊌ to_fmap cmp v9)` by (every_case_tac >> fs [FLOOKUP_DEF]) >> `key_set cmp k' ≠ key_set cmp k ∧ cmp k' k = Greater` @@ -1656,19 +1656,19 @@ val deleteFindMax_thm = Q.store_thm ("deleteFindMax", >- (imp_res_tac size_thm >> rw [FCARD_FUPDATE, FDOM_DRESTRICT] >> rw [FCARD_DRESTRICT, DELETE_INSERT] >> - `(FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)) ∩ + `(FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9)) ∩ (key_set cmp v6 INSERT FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9) DELETE key_set cmp k') = FDOM (to_fmap cmp v8) ∪ FDOM (to_fmap cmp v9) DELETE key_set cmp k'` - by (rw [EXTENSION] >> + by (rw [EXTENSION] >> metis_tac [key_set_eq, EXTENSION]) >> simp [CARD_UNION_EQN] >> fs [DISJOINT_DEF] >| - [`CARD (FDOM (to_fmap cmp v8)) ≠ 0` + [`CARD (FDOM (to_fmap cmp v8)) ≠ 0` by (rw [CARD_EQ_0, EXTENSION] >> metis_tac []) >> `0 < CARD (FDOM (to_fmap cmp v8))` by decide_tac, - `CARD (FDOM (to_fmap cmp v9)) ≠ 0` + `CARD (FDOM (to_fmap cmp v9)) ≠ 0` by (rw [CARD_EQ_0, EXTENSION] >> metis_tac []) >> `0 < CARD (FDOM (to_fmap cmp v9))` by decide_tac] >> @@ -1800,7 +1800,7 @@ val delete_thm = Q.store_thm ("delete_thm", invariant cmp t ⇒ invariant cmp (delete cmp k t) ∧ - to_fmap cmp (delete cmp k t) = + to_fmap cmp (delete cmp k t) = DRESTRICT (to_fmap cmp t) (FDOM (to_fmap cmp t) DELETE key_set cmp k)`, Induct_on `t` >- rw [delete_def, to_fmap_def] >> @@ -1812,7 +1812,7 @@ val delete_thm = Q.store_thm ("delete_thm", simp [] >- (inv_mp_tac balanceR_thm >> simp [] >> - rw [] + rw [] >- (fs [key_ordered_to_fmap] >> rfs [key_ordered_to_fmap] >> rw [FDOM_DRESTRICT] >> @@ -1829,7 +1829,7 @@ val delete_thm = Q.store_thm ("delete_thm", >- to_fmap_tac) >- (inv_mp_tac balanceL_thm >> simp [] >> - rw [] + rw [] >- (fs [key_ordered_to_fmap] >> rfs [key_ordered_to_fmap] >> rw [FDOM_DRESTRICT] >> @@ -1838,7 +1838,7 @@ val delete_thm = Q.store_thm ("delete_thm", rw [FCARD_DRESTRICT, DELETE_INTER2] >> imp_res_tac almost_balancedL_thm >> metis_tac [FCARD_DEF]) - >- to_fmap_tac)); + >- to_fmap_tac)); val restrict_set_def = Define ` restrict_set cmp lo hi = @@ -1859,7 +1859,7 @@ val restrict_domain_update = Q.prove ( `good_cmp cmp ⇒ restrict_domain cmp lo hi (m1 |+ (key_set cmp k,v)) = - if k ∈ restrict_set cmp lo hi then + if k ∈ restrict_set cmp lo hi then restrict_domain cmp lo hi m1 |+ (key_set cmp k,v) else restrict_domain cmp lo hi m1`, @@ -1883,10 +1883,10 @@ val trim_thm = Q.prove ( invariant cmp (trim cmp lk hk t) ∧ bounded_root cmp lk hk (trim cmp lk hk t) ∧ to_fmap cmp (trim cmp lk hk t) SUBMAP to_fmap cmp t ∧ - restrict_domain cmp lk hk (to_fmap cmp (trim cmp lk hk t)) = + restrict_domain cmp lk hk (to_fmap cmp (trim cmp lk hk t)) = restrict_domain cmp lk hk (to_fmap cmp t)`, - Cases_on `lk` >> - Cases_on `hk` >> + Cases_on `lk` >> + Cases_on `hk` >> simp [bounded_root_def, trim_def, restrict_set_def, option_cmp_def, option_cmp2_def] >> Induct_on `t` >> simp [trim_help_lesser_def, trim_help_greater_def, trim_help_middle_def, key_ordered_def] >> @@ -1898,7 +1898,7 @@ val trim_thm = Q.prove ( simp [to_fmap_def] >> fs [SUBMAP_DEF, restrict_domain_def, DRESTRICTED_FUNION, DRESTRICT_FUPDATE] >> rw [invariant_def] >> - rw [FAPPLY_FUPDATE_THM, FUNION_DEF, fmap_eq_flookup, FLOOKUP_DRESTRICT, + rw [FAPPLY_FUPDATE_THM, FUNION_DEF, fmap_eq_flookup, FLOOKUP_DRESTRICT, FLOOKUP_FUNION, FLOOKUP_UPDATE] >> rw [] >> every_case_tac >> @@ -1954,7 +1954,7 @@ val link_thm = Q.prove ( key_ordered cmp k r Less ⇒ invariant cmp (link k v l r) ∧ - to_fmap cmp (link k v l r) = + to_fmap cmp (link k v l r) = (FUNION (to_fmap cmp l) (to_fmap cmp r)) |+ (key_set cmp k,v)`, ho_match_mp_tac (fetch "-" "link_ind") >> rpt conj_tac >> @@ -1995,7 +1995,7 @@ val link_thm = Q.prove ( simp [FCARD_DEF] >> `DISJOINT (FDOM (to_fmap cmp ly) ∪ FDOM (to_fmap cmp l)) (FDOM (to_fmap cmp r))` by (rw [DISJOINT_UNION] >> - rw [DISJOINT_DEF, EXTENSION] >> + rw [DISJOINT_DEF, EXTENSION] >> metis_tac [cmp_thms, key_set_cmp_thm, to_fmap_key_set]) >> rw [CARD_DISJOINT_UNION] >> imp_res_tac structure_size_to_fmap >> @@ -2027,11 +2027,11 @@ val link_thm = Q.prove ( simp [FCARD_DEF] >> `DISJOINT (FDOM (to_fmap cmp l) ∪ FDOM (to_fmap cmp r)) (FDOM (to_fmap cmp rz))` by (rw [DISJOINT_UNION] >> - rw [DISJOINT_DEF, EXTENSION] >> + rw [DISJOINT_DEF, EXTENSION] >> metis_tac [cmp_thms, key_set_cmp_thm, to_fmap_key_set]) >> `DISJOINT (FDOM (to_fmap cmp l)) (FDOM (to_fmap cmp r))` by (rw [DISJOINT_UNION] >> - rw [DISJOINT_DEF, EXTENSION] >> + rw [DISJOINT_DEF, EXTENSION] >> metis_tac [cmp_thms, key_set_cmp_thm, to_fmap_key_set]) >> rw [CARD_DISJOINT_UNION] >> imp_res_tac structure_size_to_fmap >> @@ -2085,7 +2085,7 @@ val filterLt_thm = Q.prove ( simp [to_fmap_def, filterLt_def, restrict_domain_union, restrict_domain_update] >> simp [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> rw [] >> - imp_res_tac filter_lt_help_thm + imp_res_tac filter_lt_help_thm >- (rw [fmap_eq_flookup, FLOOKUP_DRESTRICT] >> rw [] >> fs [FLOOKUP_DEF] >> @@ -2133,7 +2133,7 @@ val filterGt_thm = Q.prove ( simp [to_fmap_def, filterGt_def, restrict_domain_union, restrict_domain_update] >> simp [restrict_domain_def, restrict_set_def, option_cmp2_def, option_cmp_def] >> rw [] >> - imp_res_tac filter_gt_help_thm + imp_res_tac filter_gt_help_thm >- (rw [fmap_eq_flookup, FLOOKUP_DRESTRICT] >> rw [] >> fs [FLOOKUP_DEF] >> @@ -2148,7 +2148,7 @@ val restrict_domain_partition = Q.prove ( restrict_domain cmp (SOME x) h t1 SUBMAP t2 ∧ key_set cmp x ∉ FDOM t1 ∧ key_set cmp x ∉ FDOM t2 - ⇒ + ⇒ FUNION (restrict_domain cmp l h t1) (restrict_domain cmp l h t2) = FUNION (restrict_domain cmp l (SOME x) t1) (restrict_domain cmp (SOME x) h t2)`, rw [restrict_domain_def, fmap_eq_flookup] >> @@ -2164,7 +2164,7 @@ val restrict_domain_partition = Q.prove ( val restrict_domain_union_swap = Q.prove ( ` good_cmp cmp - ⇒ + ⇒ a ⊌ restrict_domain cmp blo (SOME kx) (to_fmap cmp r2) ⊌ restrict_domain cmp (SOME kx) bhi (to_fmap cmp t1') @@ -2186,7 +2186,7 @@ val restrict_domain_extend = Q.prove ( ` good_cmp cmp ∧ invariant cmp (Bin s kx x t1 t1') ∧ kx ∈ restrict_set cmp blo bhi - ⇒ + ⇒ restrict_domain cmp blo (SOME kx) (to_fmap cmp t1) = restrict_domain cmp blo bhi (to_fmap cmp t1) ∧ restrict_domain cmp (SOME kx) bhi (to_fmap cmp t1') = @@ -2257,7 +2257,7 @@ val bounded_restrict_id = Q.prove ( `!t. good_cmp cmp ∧ bounded_all cmp blo bhi t - ⇒ + ⇒ restrict_domain cmp blo bhi (to_fmap cmp t) = to_fmap cmp t`, Induct_on `t` >> rw [bounded_all_def, to_fmap_def, restrict_domain_union, restrict_domain_update] >> @@ -2266,7 +2266,7 @@ val bounded_restrict_id = Q.prove ( fs [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def]); val restrict_domain_empty = Q.prove ( -`good_cmp cmp ⇒ +`good_cmp cmp ⇒ restrict_domain cmp blo (SOME kx) (restrict_domain cmp (SOME kx) bhi t) = FEMPTY ∧ restrict_domain cmp (SOME kx) bhi (restrict_domain cmp blo (SOME kx) t) = FEMPTY`, Cases_on `blo` >> @@ -2283,14 +2283,14 @@ val hedgeUnion_thm = Q.prove ( bounded_root cmp blo bhi t2 ⇒ invariant cmp (hedgeUnion cmp blo bhi t1 t2) ∧ - to_fmap cmp (hedgeUnion cmp blo bhi t1 t2) = + to_fmap cmp (hedgeUnion cmp blo bhi t1 t2) = restrict_domain cmp blo bhi (to_fmap cmp t1 ⊌ to_fmap cmp t2)`, ho_match_mp_tac (fetch "-" "hedgeUnion_ind") >> rpt conj_tac >> simp [hedgeUnion_def] >> rpt conj_tac >> rpt gen_tac >> - strip_tac + strip_tac >- rw [to_fmap_def, FUNION_FEMPTY_2, bounded_restrict_id] >- (inv_mp_tac link_thm >> simp [GSYM CONJ_ASSOC] >> @@ -2367,7 +2367,7 @@ val hedgeUnion_thm = Q.prove ( fs [restrict_domain_def, restrict_set_def, option_cmp_def, option_cmp2_def] >> metis_tac [good_cmp_def, comparison_distinct, key_set_cmp_thm]) >> rw [restrict_domain_union, restrict_domain_update] >> - `key_set cmp kx ∉ FDOM (to_fmap cmp m1) ∧ key_set cmp kx ∉ FDOM (to_fmap cmp m2)` + `key_set cmp kx ∉ FDOM (to_fmap cmp m1) ∧ key_set cmp kx ∉ FDOM (to_fmap cmp m2)` by metis_tac [key_ordered_to_fmap, cmp_thms, to_fmap_key_set, key_set_cmp_thm] >> `restrict_domain cmp blo (SOME kx) (to_fmap cmp m2) SUBMAP (to_fmap cmp m1) ∧ restrict_domain cmp (SOME kx) bhi (to_fmap cmp m1) SUBMAP (to_fmap cmp m2)` @@ -2439,7 +2439,7 @@ val toAscList_helper = Q.prove ( (!k1 v1 k2 v2. MEM (k1,v1) l ∧ FLOOKUP (to_fmap cmp t) (key_set cmp k2) = SOME v2 ⇒ cmp k2 k1 = Less) ⇒ SORTED (\(x,y) (x',y'). cmp x x' = Less) (foldrWithKey (λk x xs. (k,x)::xs) l t) ∧ - lift_key cmp (set (foldrWithKey (λk x xs. (k,x)::xs) l t)) = + lift_key cmp (set (foldrWithKey (λk x xs. (k,x)::xs) l t)) = set (fmap_to_alist (to_fmap cmp t)) ∪ lift_key cmp (set l)`, Induct_on `t` >> simp [foldrWithKey_def, to_fmap_def] >> @@ -2529,13 +2529,13 @@ val compare_good_cmp = Q.store_thm ("compare_good_cmp", metis_tac []); val compare_thm1 = Q.prove ( -`!cmp1 cmp2 t1 t2. - good_cmp cmp1 ∧ - good_cmp cmp2 ∧ +`!cmp1 cmp2 t1 t2. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ invariant cmp1 t1 ∧ invariant cmp1 t2 ∧ - compare cmp1 cmp2 t1 t2 = Equal - ⇒ + compare cmp1 cmp2 t1 t2 = Equal + ⇒ fmap_rel (\x y. cmp2 x y = Equal) (to_fmap cmp1 t1) (to_fmap cmp1 t2)`, rw [compare_def, fmap_rel_OPTREL_FLOOKUP, OPTREL_def] >> imp_res_tac toAscList_thm >> @@ -2661,7 +2661,7 @@ val compare_lem2 = Q.prove ( SORTED (λ(x,y) (x',y'). cmp1 x x' = Less) l1 ∧ n ≤ LENGTH l1 ∧ n ≤ LENGTH l2 ∧ - LIST_REL (λ(p1,p2) (p1',p2'). pair_cmp cmp1 cmp2 (p1,p2) (p1',p2') = Equal) + LIST_REL (λ(p1,p2) (p1',p2'). pair_cmp cmp1 cmp2 (p1,p2) (p1',p2') = Equal) (TAKE n l1) (TAKE n l2) ∧ n ≠ LENGTH l1 ⇒ @@ -2679,7 +2679,7 @@ val compare_lem2 = Q.prove ( fs [] >> rfs [key_set_eq] >- metis_tac [PAIR, cmp_thms] >> - `p_1' = kn1 ∧ x = vn1` + `p_1' = kn1 ∧ x = vn1` by (match_mp_tac strict_sorted_unique >> rw [] >> metis_tac [cmp_thms]) >> @@ -2717,7 +2717,7 @@ val compare_lem2 = Q.prove ( `n < LENGTH l1` by decide_tac >- metis_tac [PAIR, cmp_thms] >> rw [] >> - `p_1'' = kn3 ∧ y = vn3` + `p_1'' = kn3 ∧ y = vn3` by (match_mp_tac strict_sorted_unique >> rw [] >> metis_tac [rich_listTheory.EL_MEM, cmp_thms]) >> @@ -2767,9 +2767,9 @@ val compare_lem2 = Q.prove ( metis_tac [cmp_thms]))); val compare_thm2 = Q.prove ( -`!cmp1 cmp2 t1 t2. - good_cmp cmp1 ∧ - good_cmp cmp2 ∧ +`!cmp1 cmp2 t1 t2. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ invariant cmp1 t1 ∧ invariant cmp1 t2 ∧ fmap_rel (\x y. cmp2 x y = Equal) (to_fmap cmp1 t1) (to_fmap cmp1 t2) @@ -2820,9 +2820,9 @@ val compare_thm2 = Q.prove ( metis_tac [good_cmp_def, pair_cmp_good])); val compare_thm = Q.store_thm ("compare_thm", -`!cmp1 cmp2 t1 t2. - good_cmp cmp1 ∧ - good_cmp cmp2 ∧ +`!cmp1 cmp2 t1 t2. + good_cmp cmp1 ∧ + good_cmp cmp2 ∧ invariant cmp1 t1 ∧ invariant cmp1 t2 ⇒ @@ -2872,7 +2872,7 @@ val splitLookup_thm = Q.store_thm ("splitLookup_thm", FLOOKUP (to_fmap cmp t) (key_set cmp k) = v ∧ key_ordered cmp k lt Greater ∧ key_ordered cmp k gt Less ∧ - to_fmap cmp t = + to_fmap cmp t = case v of | NONE => FUNION (to_fmap cmp lt) (to_fmap cmp gt) | SOME v => (FUNION (to_fmap cmp lt) (to_fmap cmp gt)) |+ (key_set cmp k, v)`, @@ -3164,9 +3164,9 @@ val alookup_unit_lem = Q.prove ( `!cmp1 cmp2 f k l x. good_cmp cmp1 ∧ good_cmp cmp2 ∧ - resp_equiv2 cmp1 cmp2 f + resp_equiv2 cmp1 cmp2 f ⇒ - (ALOOKUP (MAP (\(k,v). (key_set cmp1 k, ())) l) (key_set cmp1 x') = + (ALOOKUP (MAP (\(k,v). (key_set cmp1 k, ())) l) (key_set cmp1 x') = ALOOKUP (MAP (\(k,v). (key_set cmp2 (f k), ())) l) (key_set cmp2 (f x')))`, Induct_on `l` >> @@ -3245,16 +3245,16 @@ val bigunion_key_sets = Q.prove ( fs [key_set_def] >> eq_tac >> rw [] >> - rfs [resp_equiv2_def] + rfs [resp_equiv2_def] >- metis_tac [cmp_thms] >> qexists_tac `key_set cmp2 (f x)` >> rw [key_set_def] >> metis_tac [cmp_thms]); val image_lem = Q.prove ( -`good_cmp cmp1 +`good_cmp cmp1 ⇒ - IMAGE (λx. key_set cmp2 (f x)) (key_set cmp1 k'') = + IMAGE (λx. key_set cmp2 (f x)) (key_set cmp1 k'') = { key_set cmp2 (f x) | x | cmp1 x k'' = Equal }`, rw [EXTENSION,key_set_def] >> metis_tac [cmp_thms]); @@ -3306,7 +3306,7 @@ val map_keys_thm = Q.store_thm ("map_keys_thm", rw [key_set_def] fs [key_set_def] - CCONTR_TAC + CCONTR_TAC Cases_on `cmp1 k' k'' = Equal` >> fs [] `cmp2 (f k') (f k'') ≠ Equal` by metis_tac [cmp_thms] @@ -3318,7 +3318,7 @@ metis_tac [cmp_thms] Cases_on `?x. k = key_set cmp2 x` >> fs [] >- (Cases_on `?x'. x = f x'` >> - fs [] + fs [] >- (first_x_assum (qspecl_then [`key_set cmp1 x'`] mp_tac) >> rw [] @@ -3356,7 +3356,7 @@ val key_set_map = Q.prove ( val flookup_lem = Q.prove ( `!cmp1 cmp2 m k v f. - (FLOOKUP m k = + (FLOOKUP m k = FLOOKUP (MAP_KEYS (BIGUNION o IMAGE (λx. key_set cmp2 (f x))) m) (BIGUNION o IMAGE (λx. key_set cmp2 (f k))))`, rw [FLOOKUP_DEF, MAP_KEYS_def] >> @@ -3411,7 +3411,7 @@ val map_keys_thm = Q.store_thm ("map_keys_thm", val every_def = Define ` (every f Tip = T) ∧ -(every f (Bin _ kx x l r) = +(every f (Bin _ kx x l r) = if f kx x then if every f l then if every f r then T else F @@ -3419,11 +3419,11 @@ val every_def = Define ` else F)`; val every_thm = Q.store_thm ("every_thm", -`!f t cmp. +`!f t cmp. good_cmp cmp ∧ invariant cmp t ∧ resp_equiv cmp f - ⇒ + ⇒ (every f t ⇔ (!k v. lookup cmp k t = SOME v ⇒ f k v))`, Induct_on `t` >> rw [every_def, lookup_def] >> @@ -3460,7 +3460,7 @@ val every_thm = Q.store_thm ("every_thm", val exists_def = Define ` (exists f Tip = F) ∧ -(exists f (Bin _ kx x l r) = +(exists f (Bin _ kx x l r) = if f kx x then T else if exists f l then @@ -3471,11 +3471,11 @@ val exists_def = Define ` F)`; val exists_thm = Q.store_thm ("exists_thm", -`!f t cmp. +`!f t cmp. good_cmp cmp ∧ invariant cmp t ∧ resp_equiv cmp f - ⇒ + ⇒ (exists f t ⇔ (?k v. lookup cmp k t = SOME v ∧ f k v))`, Induct_on `t` >> rw [exists_def, lookup_def] >> diff --git a/examples/balanced_bst/comparisonScript.sml b/examples/balanced_bst/comparisonScript.sml index 1aecac91ef..9b6dcd9fc4 100644 --- a/examples/balanced_bst/comparisonScript.sml +++ b/examples/balanced_bst/comparisonScript.sml @@ -25,7 +25,7 @@ good_cmp cmp ⇔ (!x y z. cmp x y = Less ∧ cmp y z = Less ⇒ cmp x z = Less)`; val good_cmp_thm = Q.store_thm ("good_cmp_thm", -`!cmp. +`!cmp. good_cmp cmp ⇔ (!x. cmp x x = Equal) ∧ (!x y z. @@ -266,10 +266,10 @@ val string_cmp_antisym = Q.store_thm ("string_cmp_antisym[simp]", metis_tac [string_cmp_def, char_cmp_antisym, list_cmp_antisym]); val pair_cmp_antisym = Q.store_thm ("pair_cmp_antisym", -`!cmp1 cmp2 x y. +`!cmp1 cmp2 x y. (!x y. cmp1 x y = Equal ⇔ x = y) ∧ - (!x y. cmp2 x y = Equal ⇔ x = y) - ⇒ + (!x y. cmp2 x y = Equal ⇔ x = y) + ⇒ (pair_cmp cmp1 cmp2 x y = Equal ⇔ x = y)`, Cases_on `x` >> Cases_on `y` >> @@ -279,9 +279,9 @@ val pair_cmp_antisym = Q.store_thm ("pair_cmp_antisym", metis_tac [comparison_distinct]); val option_cmp_antisym = Q.store_thm ("option_cmp_antisym", -`!cmp x y. - (!x y. cmp x y = Equal ⇔ x = y) - ⇒ +`!cmp x y. + (!x y. cmp x y = Equal ⇔ x = y) + ⇒ (option_cmp cmp x y = Equal ⇔ x = y)`, Cases_on `x` >> Cases_on `y` >> @@ -291,9 +291,9 @@ val option_cmp_antisym = Q.store_thm ("option_cmp_antisym", metis_tac [comparison_distinct]); val option_cmp2_antisym = Q.store_thm ("option_cmp2_antisym", -`!cmp x y. - (!x y. cmp x y = Equal ⇔ x = y) - ⇒ +`!cmp x y. + (!x y. cmp x y = Equal ⇔ x = y) + ⇒ (option_cmp2 cmp x y = Equal ⇔ x = y)`, Cases_on `x` >> Cases_on `y` >> @@ -312,9 +312,9 @@ val equiv_inj_def = Define ` equiv_inj cmp cmp2 f ⇔ (!k1 k2. cmp2 (f k1) (f k2) = Equal ⇒ cmp k1 k2 = Equal)`; val antisym_resp_equiv = Q.store_thm ("antisym_resp_equiv", -`!cmp f. - (!x y. cmp x y = Equal ⇒ x = y) - ⇒ +`!cmp f. + (!x y. cmp x y = Equal ⇒ x = y) + ⇒ resp_equiv cmp f ∧ !cmp2. good_cmp cmp2 ⇒ resp_equiv2 cmp cmp2 f`, rw [resp_equiv_def, resp_equiv2_def] >> metis_tac [cmp_thms]); diff --git a/examples/balanced_bst/osetScript.sml b/examples/balanced_bst/osetScript.sml index ff3b83c32f..4d2a698b7d 100644 --- a/examples/balanced_bst/osetScript.sml +++ b/examples/balanced_bst/osetScript.sml @@ -90,7 +90,7 @@ val good_oset_oimage = Q.store_thm ("good_oset_oimage", val good_cmp_ocompare = Q.store_thm ("good_cmp_ocompare", `!cmp f s. good_cmp cmp ⇒ good_cmp (ocompare cmp)`, rw [] >> - `good_cmp (\(x:unit) (y:unit). Equal)` + `good_cmp (\(x:unit) (y:unit). Equal)` by (rw [good_cmp_def, LAMBDA_PROD, FORALL_PROD] >> metis_tac [good_cmp_def]) >> imp_res_tac compare_good_cmp >> @@ -113,7 +113,7 @@ val good_oset_oset = Q.store_thm ("good_oset_oset", val oin_oempty = Q.store_thm ("oin_oinsert[simp]", `!cmp x. oin cmp x oempty = F`, - rw [oin_def, oempty_def, empty_def, member_def]); + rw [oin_def, oempty_def, empty_def, member_def]); val oimage_oempty = Q.store_thm ("oimage_oempty[simp]", `!cmp f. oimage cmp f oempty = oempty`, @@ -136,7 +136,7 @@ val ounion_oempty = Q.store_thm ("ounion_oempty[simp]", val oempty_subset = Q.store_thm ("oempty_subset[simp]", `!cmp s. (osubset cmp oempty s ⇔ T) ∧ (osubset cmp s oempty ⇔ s = oempty)`, - rw [osubset_def, oempty_def, isSubmapOf_def, isSubmapOfBy_def, empty_def, + rw [osubset_def, oempty_def, isSubmapOf_def, isSubmapOfBy_def, empty_def, submap'_def, size_def] >> Cases_on `s` >> rw [submap'_def, size_def]); @@ -232,12 +232,12 @@ val osubset_thm = Q.store_thm ("osubset_thm", rw []); val oextension = Q.store_thm ("oextension", -`!cmp s1 s2. +`!cmp s1 s2. good_oset cmp s1 ∧ good_oset cmp s2 - ⇒ + ⇒ (ocompare cmp s1 s2 = Equal ⇔ (!x. oin cmp x s1 ⇔ oin cmp x s2))`, rw [good_oset_def, ocompare_def] >> - `good_cmp (\(x:unit) (y:unit). Equal)` + `good_cmp (\(x:unit) (y:unit). Equal)` by (rw [good_cmp_def, LAMBDA_PROD, FORALL_PROD] >> metis_tac [good_cmp_def]) >> rw [compare_thm] >> @@ -252,31 +252,31 @@ val oextension = Q.store_thm ("oextension", metis_tac []); val oevery_oin = Q.store_thm ("oevery_oin", -`!cmp f s. +`!cmp f s. good_oset cmp s ∧ oresp_equiv cmp f - ⇒ + ⇒ (oevery f s ⇔ (!x. oin cmp x s ⇒ f x))`, rw [good_oset_def, oevery_def, oin_def, oresp_equiv_def] >> imp_res_tac every_thm >> rw [lookup_thm, flookup_thm, member_thm]); val oexists_oin = Q.store_thm ("oexists_oin", -`!cmp f s. +`!cmp f s. good_oset cmp s ∧ oresp_equiv cmp f - ⇒ + ⇒ (oexists f s ⇔ (?x. oin cmp x s ∧ f x))`, rw [oresp_equiv_def, good_oset_def, oexists_def, oin_def] >> imp_res_tac exists_thm >> rw [lookup_thm, flookup_thm, member_thm]); val oin_oset_help = Q.prove ( -`!cmp l x s. +`!cmp l x s. good_oset cmp s ⇒ - (oin cmp x (FOLDR (λx t. oinsert cmp x t) s l) - ⇔ + (oin cmp x (FOLDR (λx t. oinsert cmp x t) s l) + ⇔ oin cmp x s ∨ ?y. MEM y l ∧ cmp x y = Equal)`, Induct_on `l` >> rw [] >> From 6a90350b28977aa1258fce6f81efe3091c96b05a Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Mon, 22 Dec 2014 05:00:24 +0000 Subject: [PATCH 067/718] do not export constant t0 from wotTheory I get the impression that none of the definitions in wotTheory were supposed to be exported, so perhaps they all should be deleted at the end. I am not sure, though, so I just remove t0, whose name is particularly annoying outside this theory to be taken by a constant. --- src/enumfset/wotScript.sml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/enumfset/wotScript.sml b/src/enumfset/wotScript.sml index 0b945eb63c..d4bb6d41d5 100644 --- a/src/enumfset/wotScript.sml +++ b/src/enumfset/wotScript.sml @@ -541,6 +541,8 @@ val StrongWellOrderExists = store_thm ("StrongWellOrderExists", Q.EXISTS_TAC `$mex_less` THEN REWRITE_TAC [WellOrd_mex_less, GSYM StrongWellOrder]); +val _ = delete_const"t0"; + val _ = export_theory (); end; From 0f24f23428ee8e13bd6dfa1be75f87f423e51f5c Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Mon, 22 Dec 2014 06:29:26 +0000 Subject: [PATCH 068/718] Move comparisonTheory to src/enumfset (from examples/balanced_bst) Prove a theorem relating most of the definitions in comparisonTheory to something in totoTheory. Also, add a new definition for inverting cpns. Make the overloads on the constructors of cpn permanent in comparisonTheory. Turn on totoTheory's "BigSig" to get more useful exports. This is work towards integration, but the approach has been towards plurality, i.e. keeping multiple definitions around and proving relationships between them. More integration could be possible. Also, the dependency between toto and comparison could be flipped (I wanted to write new proofs in the nicer environment of comparison so did not do that.) It has become apparent that totoTheory is in various minor ways not self-consistent (esp. with regard to its naming schemes). --- examples/balanced_bst/balanced_mapScript.sml | 7 -- examples/balanced_bst/osetScript.sml | 2 - .../enumfset}/comparisonScript.sml | 98 +++++++++++++++---- src/enumfset/totoScript.sml | 2 +- 4 files changed, 81 insertions(+), 28 deletions(-) rename {examples/balanced_bst => src/enumfset}/comparisonScript.sml (77%) diff --git a/examples/balanced_bst/balanced_mapScript.sml b/examples/balanced_bst/balanced_mapScript.sml index 568c562e1a..e630909af7 100644 --- a/examples/balanced_bst/balanced_mapScript.sml +++ b/examples/balanced_bst/balanced_mapScript.sml @@ -11,13 +11,6 @@ val _ = new_theory "balanced_map"; val _ = temp_tight_equality (); val _ = numLib.prefer_num(); -val _ = Parse.temp_overload_on("Less",``LESS``) -val _ = Parse.temp_overload_on("Equal",``EQUAL``) -val _ = Parse.temp_overload_on("Greater",``GREATER``) -val comparison_distinct = totoTheory.cpn_distinct -val comparison_case_def = totoTheory.cpn_case_def -val comparison_nchotomy = totoTheory.cpn_nchotomy - val list_rel_lem1 = Q.prove ( `!f l l'. ~LIST_REL f l l' diff --git a/examples/balanced_bst/osetScript.sml b/examples/balanced_bst/osetScript.sml index 4d2a698b7d..a1ee1ac9cf 100644 --- a/examples/balanced_bst/osetScript.sml +++ b/examples/balanced_bst/osetScript.sml @@ -8,8 +8,6 @@ val _ = new_theory "oset"; val _ = temp_tight_equality (); -val _ = Parse.temp_overload_on("Equal",``EQUAL``) - (* oset for ordered set *) val _ = type_abbrev ("oset", ``:('a,unit) balanced_map``); diff --git a/examples/balanced_bst/comparisonScript.sml b/src/enumfset/comparisonScript.sml similarity index 77% rename from examples/balanced_bst/comparisonScript.sml rename to src/enumfset/comparisonScript.sml index 9b6dcd9fc4..ddce77dc66 100644 --- a/examples/balanced_bst/comparisonScript.sml +++ b/src/enumfset/comparisonScript.sml @@ -7,12 +7,12 @@ val _ = new_theory "comparison"; val _ = temp_tight_equality (); val every_case_tac = BasicProvers.EVERY_CASE_TAC; -val comparison_distinct = cpn_distinct -val comparison_case_def = cpn_case_def -val comparison_nchotomy = cpn_nchotomy -val _ = Parse.temp_overload_on("Less",``LESS``) -val _ = Parse.temp_overload_on("Equal",``EQUAL``) -val _ = Parse.temp_overload_on("Greater",``GREATER``) +val comparison_distinct = save_thm("comparison_distinct",cpn_distinct) +val comparison_case_def = save_thm("comparison_case_def",cpn_case_def) +val comparison_nchotomy = save_thm("comparison_nchotomy",cpn_nchotomy) +val _ = Parse.overload_on("Less",``LESS``) +val _ = Parse.overload_on("Equal",``EQUAL``) +val _ = Parse.overload_on("Greater",``GREATER``) val good_cmp_def = Define ` good_cmp cmp ⇔ @@ -35,10 +35,6 @@ val good_cmp_thm = Q.store_thm ("good_cmp_thm", rw [good_cmp_def] >> metis_tac [comparison_distinct, comparison_nchotomy]); -val TotOrd_imp_good_cmp = store_thm("TotOrder_imp_good_cmp", - ``∀cmp. TotOrd cmp ⇒ good_cmp cmp``, - rw[TotOrd,good_cmp_thm] >> metis_tac[]) - val cmp_thms = save_thm ("cmp_thms", LIST_CONJ [comparison_distinct, comparison_case_def, comparison_nchotomy, good_cmp_def]) val option_cmp_def = Define ` @@ -47,13 +43,13 @@ val option_cmp_def = Define ` (option_cmp cmp (SOME x) NONE = Greater) ∧ (option_cmp cmp (SOME x) (SOME y) = cmp x y)`; -val option_cmp2_def = Define ` -(option_cmp2 cmp NONE NONE = Equal) ∧ -(option_cmp2 cmp NONE (SOME x) = Greater) ∧ -(option_cmp2 cmp (SOME x) NONE = Less) ∧ -(option_cmp2 cmp (SOME x) (SOME y) = cmp x y)`; +val option_cmp2_def = Define` + (option_cmp2 cmp NONE NONE = Equal) ∧ + (option_cmp2 cmp NONE (SOME x) = Greater) ∧ + (option_cmp2 cmp (SOME x) NONE = Less) ∧ + (option_cmp2 cmp (SOME x) (SOME y) = cmp x y)` -val list_cmp_def = Define ` +val list_cmp_def = Define` (list_cmp cmp [] [] = Equal) ∧ (list_cmp cmp [] (x::y) = Less) ∧ (list_cmp cmp (x::y) [] = Greater) ∧ @@ -61,11 +57,11 @@ val list_cmp_def = Define ` case cmp x1 x2 of | Equal => list_cmp cmp y1 y2 | Less => Less - | Greater => Greater)`; + | Greater => Greater)` val list_cmp_ind = fetch "-" "list_cmp_ind"; -val pair_cmp_def = Define ` +val pair_cmp_def = Define` pair_cmp cmp1 cmp2 x y = case cmp1 (FST x) (FST y) of | Equal => cmp2 (SND x) (SND y) @@ -93,6 +89,72 @@ char_cmp c1 c2 = num_cmp (ORD c1) (ORD c2)`; val string_cmp_def = Define ` string_cmp = list_cmp char_cmp`; +(* relationship to toto *) + +val TotOrd_imp_good_cmp = store_thm("TotOrder_imp_good_cmp", + ``∀cmp. TotOrd cmp ⇒ good_cmp cmp``, + rw[TotOrd,good_cmp_thm] >> metis_tac[]) + +val invert_def = Define` + invert GREATER = LESS ∧ + invert LESS = GREATER ∧ + invert EQUAL = EQUAL` +val _ = export_rewrites["invert_def"] + +val invert_eq_EQUAL = store_thm("invert_eq_EQUAL[simp]", + ``∀x. invert x = EQUAL ⇔ x = EQUAL``, + Cases >> simp[]) + +val TO_inv_invert = store_thm("TO_inv_invert", + ``∀c. TotOrd c ⇒ TO_inv c = CURRY (invert o UNCURRY c)``, + simp[FUN_EQ_THM,TO_inv] >> gen_tac >> strip_tac >> + map_every qx_gen_tac[`x`,`y`] >> + Cases_on`c x y`>>simp[]>> + fs[TotOrd] >> metis_tac[]) + +val option_cmp2_TO_inv = store_thm("option_cmp2_TO_inv", + ``∀c. option_cmp2 c = TO_inv (option_cmp (TO_inv c))``, + simp[FUN_EQ_THM,TO_inv] >> + gen_tac >> Cases >> Cases >> + simp[option_cmp2_def,option_cmp_def,TO_inv]); + +val list_cmp_ListOrd = store_thm("list_cmp_ListOrd", + ``∀c. TotOrd c ⇒ list_cmp c = ListOrd (TO c)``, + simp[FUN_EQ_THM,PULL_FORALL] >> + ho_match_mp_tac list_cmp_ind >> + simp[list_cmp_def,ListOrd,TO_of_LinearOrder, + StrongLinearOrder_of_TO,TO_apto_TO_ID,listorder] >> + rw[] >> + fs[GSYM TO_apto_TO_ID,TotOrd] >> + BasicProvers.CASE_TAC >> + metis_tac[cmp_thms]) + +val pair_cmp_lexTO = store_thm("pair_cmp_lexTO", + ``∀R V. TotOrd R ∧ TotOrd V ⇒ pair_cmp R V = R lexTO V``, + simp[FUN_EQ_THM,lexTO_thm,pair_cmp_def]) + +val num_cmp_numOrd = store_thm("num_cmp_numOrd", + ``num_cmp = numOrd``, + simp[FUN_EQ_THM,num_cmp_def,numOrd,TO_of_LinearOrder]) + +val char_cmp_charOrd = store_thm("char_cmp_charOrd", + ``char_cmp = charOrd``, + simp[FUN_EQ_THM,char_cmp_def,charOrd,num_cmp_numOrd]) + +val string_cmp_stringto = store_thm("string_cmp_stringto", + ``string_cmp = apto stringto``, + simp[FUN_EQ_THM,stringto] >> + Induct >- ( Cases >> simp[aplistoto,string_cmp_def,list_cmp_def] ) >> + gen_tac >> Cases >> + simp[aplistoto,string_cmp_def,list_cmp_def,apcharto_thm,char_cmp_charOrd] >> + BasicProvers.CASE_TAC >> + simp[MATCH_MP list_cmp_ListOrd TO_charOrd,listoto,charto] >> + rpt AP_THM_TAC >> + match_mp_tac (GSYM TO_apto_TO_IMP) >> + simp[TO_ListOrd]) + +(* cmps are good *) + val option_cmp_good = Q.store_thm ("option_cmp_good", `!cmp. good_cmp cmp ⇒ good_cmp (option_cmp cmp)`, rw [good_cmp_def] >> diff --git a/src/enumfset/totoScript.sml b/src/enumfset/totoScript.sml index fb11fc2617..3fc0bce3b4 100644 --- a/src/enumfset/totoScript.sml +++ b/src/enumfset/totoScript.sml @@ -38,7 +38,7 @@ val _ = Defn.def_suffix := ""; (* replacing default "_def" *) (* from print_theory and the stuff known to DB.match, DB.find *) (* ***************************************************************** *) -val BigSig = false; +val BigSig = true; fun maybe_thm (s, tm, tac) = if BigSig then store_thm (s, tm, tac) else prove (tm, tac); From 4e0bf360ef5eb3ffb04ddf33ab007a884d2cac01 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Fri, 26 Dec 2014 17:27:46 +1100 Subject: [PATCH 069/718] fix logging-kernel/Holmakefile (it should just be the same as experimental-kernel's, which changed recently) --- src/logging-kernel/Holmakefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/logging-kernel/Holmakefile b/src/logging-kernel/Holmakefile index d5c6fde652..20a1dbb9a6 100644 --- a/src/logging-kernel/Holmakefile +++ b/src/logging-kernel/Holmakefile @@ -18,6 +18,11 @@ LIBD = $(dprot $(SIGOBJ)/Lib.ui) HOLSETD = $(dprot $(SIGOBJ)/HOLset.ui) +UOFILES = $(patsubst %.sml,%.uo,$(wildcard *.sml)) + +all: $(UOFILES) +.PHONY: all + Overlay.uo: Overlay.sml Net.ui Thm.ui $(FTAGD) $(FTYPED) $(FTERMD) $(FTHMD) $(HOLMOSMLC) -c -toplevel $(FTAG) $(FTYPE) $(FTERM) $(FTHM) Net.ui Overlay.sml From d8071b0bef24dd237a2d95a56a8cf21745e34a8d Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Fri, 26 Dec 2014 20:03:01 +1100 Subject: [PATCH 070/718] fix read_buildsequence for kernelnames the comment in build-sequence says the kernel names are "otknl", "stdknl" and "expk", but in the code they have a hyphen at the front. I guess this isn't used for anything apart from otknl so hadn't been tested much. --- tools/buildutils.sml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildutils.sml b/tools/buildutils.sml index a5df10c107..245300e1ab 100644 --- a/tools/buildutils.sml +++ b/tools/buildutils.sml @@ -153,7 +153,7 @@ fun read_buildsequence {kernelname} bseq_fname = let open FileSys in if (mlsys = "" orelse mlsys = Systeml.ML_SYSNAME) andalso - (knl = "" orelse knl = kernelname) then + (knl = "" orelse ("-"^knl) = kernelname) then if access (dirname, [A_READ, A_EXEC]) then if isDir dirname orelse mlsys <> "" then read_file ((dirname,testcount)::acc) From 8fd7f7b965a8d0deef5a3f5b7a4ed6e7023a4d55 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Fri, 26 Dec 2014 20:12:22 +1100 Subject: [PATCH 071/718] move opentheory earlier in build sequence it is not a large theory - indeed there are no theories in these directories, just some libraries, so take very little time to process. --- tools/sequences/large-theories | 2 -- tools/sequences/more-theories | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/sequences/large-theories b/tools/sequences/large-theories index de56034a17..0422644e6d 100644 --- a/tools/sequences/large-theories +++ b/tools/sequences/large-theories @@ -3,8 +3,6 @@ src/complex !!examples/separationLogic/src/ src/HolQbf src/HolSmt -src/opentheory -(otknl)src/opentheory/logging !examples/misc # these examples require Muddy, which is MoscowML specific [mosml]!examples/muddy/muddyC diff --git a/tools/sequences/more-theories b/tools/sequences/more-theories index 0e290fe7c2..f27e9b8e6c 100644 --- a/tools/sequences/more-theories +++ b/tools/sequences/more-theories @@ -1,3 +1,5 @@ +src/opentheory +(otknl)src/opentheory/logging !src/boss/theory_tests !src/tfl/src/test src/TeX From 779739fa3ac29f1b5042f5c099fa212b8f12bcad Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Fri, 26 Dec 2014 20:13:19 +1100 Subject: [PATCH 072/718] update opentheory/logging/Holmakefile for Holmake's new behaviour that does not automatically process all *.sml by default --- src/opentheory/logging/Holmakefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/opentheory/logging/Holmakefile b/src/opentheory/logging/Holmakefile index 552bf33484..004cb3d67f 100644 --- a/src/opentheory/logging/Holmakefile +++ b/src/opentheory/logging/Holmakefile @@ -1,3 +1,5 @@ +all: $(patsubst %.sml,%.uo,$(wildcard *.sml)) +.PHONY: all mkholdecide: holdecide.uo HOLMOSMLC -o $@ $< holdecide.o: mkholdecide From 4871926803af53a6a8ecae7e8f5d7ea2c01ef8a6 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Sat, 27 Dec 2014 05:08:50 +0000 Subject: [PATCH 073/718] remove miniML from the gitignore file --- .gitignore | 4 ---- 1 file changed, 4 deletions(-) diff --git a/.gitignore b/.gitignore index fbf6fbb511..6708364b61 100644 --- a/.gitignore +++ b/.gitignore @@ -133,11 +133,7 @@ examples/set-theory/hol_sets/ordinalML.* examples/theorem-prover/lisp-runtime/bin/*.s - examples/computability/lambda/computability-heap -examples/miniML/hol2miniml/*.txt -examples/miniML/hol2miniml/miniml-heap - local-hol-heap examples/l3-machine-code/**/*-heap From 31b01c1c657f91a231959d32feeb1e645506de72 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Sat, 27 Dec 2014 05:38:05 +0000 Subject: [PATCH 074/718] move opentheory after string since it depends on it. don't know why travis didn't catch this. --- tools/sequences/more-theories | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/sequences/more-theories b/tools/sequences/more-theories index f27e9b8e6c..5281ea8dec 100644 --- a/tools/sequences/more-theories +++ b/tools/sequences/more-theories @@ -1,5 +1,3 @@ -src/opentheory -(otknl)src/opentheory/logging !src/boss/theory_tests !src/tfl/src/test src/TeX @@ -9,6 +7,8 @@ src/TeX src/sort src/string !src/string/theorytesting +src/opentheory +(otknl)src/opentheory/logging !examples/STE src/res_quan/src src/quotient/src From f1369e3002d1cf2f176b2a3166250ba16c4f056b Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Tue, 30 Dec 2014 00:16:51 +1100 Subject: [PATCH 075/718] apropos_in, find_in to search for thms among previous results these functions search for term patterns or name substrings among only the list of values returned previously by listDB, apropos, find, thy --- src/bool/DB.sig | 5 +++++ src/bool/DB.sml | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/src/bool/DB.sig b/src/bool/DB.sig index 58e869d6fc..4a8e894ca8 100644 --- a/src/bool/DB.sig +++ b/src/bool/DB.sig @@ -21,10 +21,13 @@ sig val theorems : string -> (string * thm) list val definitions : string -> (string * thm) list val find : string -> data list + val find_in : string -> data list -> data list val matchp : (thm -> bool) -> string list -> data list val matcher : (term -> term -> 'a) -> string list -> term -> data list val match : string list -> term -> data list + val matches : term -> thm -> bool val apropos : term -> data list + val apropos_in : term -> data list -> data list val listDB : unit -> data list val data_list_to_string : data list -> string @@ -46,6 +49,8 @@ sig val bindl : string -> (string * thm * class) list -> unit + val CT : unit -> (string, (string, data list) Redblackmap.dict * + (string, data list) Redblackmap.dict) Redblackmap.dict end diff --git a/src/bool/DB.sml b/src/bool/DB.sml index 81a8cbb465..b1bdee96ef 100644 --- a/src/bool/DB.sml +++ b/src/bool/DB.sml @@ -207,6 +207,19 @@ fun matcher f thyl pat = val match = matcher (ho_match_term [] empty_tmset); val apropos = match []; +(* matches : term -> thm -> bool + tests whether theorem matches pattern *) +fun matches pat th = + can (find_term (can (ho_match_term [] empty_tmset pat))) (concl th) ; + +fun apropos_in pat dbdata = + List.filter (fn (_, (th, _)) => matches pat th) dbdata ; + +fun find_in s = + let val lows = toLower s ; + fun finds dbdata = + List.filter (fn ((_, name), _) => occurs lows (toLower name)) dbdata ; + in finds end ; fun listDB () = let fun subfold (k,v,acc) = v @ acc From ca62b766d79ed0fd37d12c5a496f48cadf95fb43 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Tue, 30 Dec 2014 11:30:55 +1100 Subject: [PATCH 076/718] docs for find_in, apropos_in --- help/Docfiles/DB.apropos.doc | 2 +- help/Docfiles/DB.apropos_in.doc | 48 +++++++++++++++++++++++++++++++++ help/Docfiles/DB.find.doc | 2 +- help/Docfiles/DB.find_in.doc | 43 +++++++++++++++++++++++++++++ help/Docfiles/DB.match.doc | 2 +- help/Docfiles/DB.matches.doc | 40 +++++++++++++++++++++++++++ 6 files changed, 134 insertions(+), 3 deletions(-) create mode 100644 help/Docfiles/DB.apropos_in.doc create mode 100644 help/Docfiles/DB.find_in.doc create mode 100644 help/Docfiles/DB.matches.doc diff --git a/help/Docfiles/DB.apropos.doc b/help/Docfiles/DB.apropos.doc index ccb2236fb9..10887da8b6 100644 --- a/help/Docfiles/DB.apropos.doc +++ b/help/Docfiles/DB.apropos.doc @@ -34,5 +34,5 @@ The notion of matching is a restricted version of higher-order matching. For finer control over the theories searched, use {DB.match}. \SEEALSO -DB.match, DB.find. +DB.match, DB.find, DB.apropos_in, DB.matches. \ENDDOC diff --git a/help/Docfiles/DB.apropos_in.doc b/help/Docfiles/DB.apropos_in.doc new file mode 100644 index 0000000000..299c68a20d --- /dev/null +++ b/help/Docfiles/DB.apropos_in.doc @@ -0,0 +1,48 @@ +\DOC apropos_in + +\TYPE {apropos_in : term -> data list -> data list} + +\SYNOPSIS +Attempt to select matching theorems among a given list. + +\DESCRIBE +An invocation {DB.apropos_in M data_list} selects all +theorems, definitions, and axioms within {data_list} that have a subterm +that matches {M}. If there are no matches, the empty list is returned. + +\FAILURE +Never fails. + +\EXAMPLE +{ +- DB.apropos (Term `(!x y. P x y) ==> Q`); +<> +> val it = + [(("ind_type", "INJ_INVERSE2"), + (|- !P. + (!x1 y1 x2 y2. (P x1 y1 = P x2 y2) = (x1 = x2) /\ (y1 = y2)) ==> + ?X Y. !x y. (X (P x y) = x) /\ (Y (P x y) = y), Thm)), + (("pair", "pair_induction"), + (|- (!p_1 p_2. P (p_1,p_2)) ==> !p. P p, Thm))] : + ((string * string) * (thm * class)) list + +- DB.apropos_in (Term `(x, y)`) it ; + [(("pair", "pair_induction"), + (|- (!p_1 p_2. P (p_1,p_2)) ==> !p. P p, Thm))] : + ((string * string) * (thm * class)) list +} + + +\COMMENTS +The notion of matching is a restricted version of higher-order matching. +It uses {DB.matches}. + +\USES +Finding theorems in interactive proof sessions. +The second argument will normally be the result of a previous call to +{DB.find, DB.match, DB.apropos, DB.listDB, DB.thy} etc. + +\SEEALSO +DB.apropos, DB.match, DB.matches, DB.find, DB.find_in, DB.listDB, DB.thy, +DB.theorems. +\ENDDOC diff --git a/help/Docfiles/DB.find.doc b/help/Docfiles/DB.find.doc index 9932d1a981..da958e4482 100644 --- a/help/Docfiles/DB.find.doc +++ b/help/Docfiles/DB.find.doc @@ -32,5 +32,5 @@ Never fails. If nothing suitable can be found, the empty list is returned. Finding theorems in interactive proof sessions. \SEEALSO -DB.match, DB.apropos, DB.thy, DB.theorems. +DB.find_in, DB.match, DB.apropos, DB.thy, DB.theorems. \ENDDOC diff --git a/help/Docfiles/DB.find_in.doc b/help/Docfiles/DB.find_in.doc new file mode 100644 index 0000000000..15669043c1 --- /dev/null +++ b/help/Docfiles/DB.find_in.doc @@ -0,0 +1,43 @@ +\DOC find_in + +\TYPE {find_in : string -> data list -> data list} + +\SYNOPSIS +Search for theory element by name fragment, among a given list. + +\DESCRIBE +An invocation {DB.find_in s data_list} +selects from {data_list} those theory elements which have +been stored with a name in which {s} occurs as a proper substring, +ignoring case distinctions. + +\FAILURE +Never fails. If nothing suitable can be found, the empty list is returned. + +\EXAMPLE +{ +- DB.find "inc"; +> val it = + [(("arithmetic", "MULT_INCREASES"), + (|- !m n. 1 < m /\ 0 < n ==> SUC n <= m * n, Thm)), + (("bool", "BOOL_EQ_DISTINCT"), (|- ~(T = F) /\ ~(F = T), Thm)), + (("list", "list_distinct"), (|- !a1 a0. ~([] = a0::a1), Thm)), + (("sum", "sum_distinct"), (|- !x y. ~(INL x = INR y), Thm)), + (("sum", "sum_distinct1"), (|- !x y. ~(INR y = INL x), Thm))] + : ((string * string) * (thm * class)) list + +- DB.find_in "sum" it; +> val it = + [(("sum", "sum_distinct"), (|- !x y. ~(INL x = INR y), Thm)), + (("sum", "sum_distinct1"), (|- !x y. ~(INR y = INL x), Thm))] + : ((string * string) * (thm * class)) list +} + +\USES +Finding theorems in interactive proof sessions. +The second argument will normally be the result of a previous call to +{DB.find, DB.match, DB.apropos, DB.listDB, DB.thy} etc. + +\SEEALSO +DB.find, DB.match, DB.apropos, DB.listDB, DB.thy, DB.theorems. +\ENDDOC diff --git a/help/Docfiles/DB.match.doc b/help/Docfiles/DB.match.doc index 236483fbf2..f2202dd75b 100644 --- a/help/Docfiles/DB.match.doc +++ b/help/Docfiles/DB.match.doc @@ -55,5 +55,5 @@ The notion of matching is a restricted version of higher-order matching. For locating theorems when doing interactive proof. \SEEALSO -DB.matcher, DB.matchp, DB.find, DB.theorems, Db.thy, Db.listDB. +DB.matcher, DB.matchp, DB.find, DB.theorems, DB.thy, DB.listDB. \ENDDOC diff --git a/help/Docfiles/DB.matches.doc b/help/Docfiles/DB.matches.doc new file mode 100644 index 0000000000..2da4f6fe86 --- /dev/null +++ b/help/Docfiles/DB.matches.doc @@ -0,0 +1,40 @@ +\DOC matches + +\TYPE {matches : term -> thm -> bool} + +\SYNOPSIS +Tells whether part of a theorem matches a pattern. + +\KEYWORDS +matching. + +\DESCRIBE +An invocation {DB.match pat th} tells whether the conclusion of {th} +has a subterm matching {pat}. + +\FAILURE +Never fails. + +\EXAMPLE +{ +> DB.matches (Term `(a = b) = c`) EQ_CLAUSES ; +<> +val it = true: bool + +> DB.matches (Term `(a = b) = c`) EQ_TRANS ; +<> +val it = false: bool +} + + +\COMMENTS +The notion of matching is a restricted version of higher-order matching, +as used by {DB.apropos, DB.apropos_in, DB.match}, etc. + +\USES +For locating theorems relevant to a given pattern. + +\SEEALSO +DB.matcher, DB.matchp, DB.apropos, DB.apropos_in +\ENDDOC + From 79fc3d409a9000f799f29c64c5cdaa9f021533a1 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Wed, 31 Dec 2014 20:13:52 +1100 Subject: [PATCH 077/718] relaxing type constraint for THEN and THENL to permit val THEN : list_tactic * tactic -> list_tactic val THENL : list_tactic * tactic list -> list_tactic as well as the usual types --- help/Docfiles/Tactical.EVERY_LT.doc | 31 +++++++++++++++++++++++++++++ help/Docfiles/Tactical.THEN.doc | 8 ++++++-- help/Docfiles/Tactical.THENL.doc | 22 +++++++++++--------- help/Docfiles/Tactical.THEN_LT.doc | 4 ++-- src/1/Tactical.sig | 11 ++++++++++ src/1/Tactical.sml | 11 +++++++++- 6 files changed, 73 insertions(+), 14 deletions(-) create mode 100644 help/Docfiles/Tactical.EVERY_LT.doc diff --git a/help/Docfiles/Tactical.EVERY_LT.doc b/help/Docfiles/Tactical.EVERY_LT.doc new file mode 100644 index 0000000000..3dc9272d61 --- /dev/null +++ b/help/Docfiles/Tactical.EVERY_LT.doc @@ -0,0 +1,31 @@ +\DOC EVERY_LT + +\TYPE {EVERY_LT : (list_tactic list -> list_tactic)} + +\SYNOPSIS +Sequentially applies all the list-tactics in a given list of list-tactics. + +\KEYWORDS +list-tactic, tactical. + +\DESCRIBE +When applied to a list of list-tactics {[LT1; ... ;LTn]}, and a goal {g}, +the tactical {EVERY_LT} applies each list-tactic in sequence to every +subgoal generated by the previous one. This can be represented as: +{ + EVERY_LT [LT1;...;LTn] = LT1 THEN_LT ... THEN_LT LTn +} +If the list-tactic list is empty, the resulting list-tactic has no effect. + +\FAILURE +The application of {EVERY_LT} to a list-tactic list never fails. The resulting +list-tactic fails iff any of the component list-tactics do. + +\COMMENTS +It is possible to use {EVERY_LT} instead of {THEN_LT}, but probably +stylistically inferior. {EVERY_LT} is more useful when applied to a list of +list-tactics generated by a function. + +\SEEALSO +Tactical.THEN_LT. +\ENDDOC diff --git a/help/Docfiles/Tactical.THEN.doc b/help/Docfiles/Tactical.THEN.doc index 4fb9cfc43d..0f580c2608 100644 --- a/help/Docfiles/Tactical.THEN.doc +++ b/help/Docfiles/Tactical.THEN.doc @@ -1,9 +1,10 @@ \DOC THEN \TYPE {op THEN : tactic * tactic -> tactic} +op THEN : list_tactic * tactic -> list_tactic} \SYNOPSIS -Applies two tactics in sequence. +Applies a tactic to all subgoals produced by a tactic or list-tactic. \KEYWORDS tactical. @@ -13,6 +14,9 @@ If {T1} and {T2} are tactics, {T1 THEN T2} is a tactic which applies {T1} to a goal, then applies the tactic {T2} to all the subgoals generated. If {T1} solves the goal then {T2} is never applied. +Alternatively, {T1} may be a list-tactic which is applied to an initial list of +goals. + \FAILURE The application of {THEN} to a pair of tactics never fails. The resulting tactic fails if {T1} fails when applied to the goal, or if @@ -32,5 +36,5 @@ can be replaced by the briefer: \SEEALSO -Tactical.EVERY, Tactical.ORELSE, Tactical.THENL. +Tactical.EVERY, Tactical.ORELSE, Tactical.THENL, Tactical.THEN_LT. \ENDDOC diff --git a/help/Docfiles/Tactical.THENL.doc b/help/Docfiles/Tactical.THENL.doc index b892bd0e85..99583337be 100644 --- a/help/Docfiles/Tactical.THENL.doc +++ b/help/Docfiles/Tactical.THENL.doc @@ -1,21 +1,25 @@ -\DOC +\DOC THENL -\TYPE {op THENL : tactic -> tactic list -> tactic} +\TYPE {op THENL : tactic * tactic list -> tactic +op THENL : list_tactic * tactic list -> list_tactic} \SYNOPSIS -Applies a list of tactics to the corresponding subgoals generated by a tactic. +Applies a list of tactics to the corresponding subgoals generated by a +tactic or a list-tactic. \KEYWORDS tactical. \DESCRIBE -If {T,T1,...,Tn} are tactics, {T THENL [T1,...,Tn]} is a tactic which applies -{T} to a goal, and if it does not fail, applies the tactics {T1,...,Tn} to the -corresponding subgoals, unless {T} completely solves the goal. +If {T} is a tactic or list-tactic and {T1,...,Tn} are tactics, +{T THENL [T1,...,Tn]} is a tactic or list-tactic which applies +{T} to a goal or goal list, and if it does not fail, +applies the tactics {T1,...,Tn} to the corresponding subgoals, +unless {T} completely solves the goal(s). \FAILURE -The application of {THENL} to a tactic and tactic list never fails. -The resulting tactic fails if {T} fails when applied to the goal, or if +The application of {THENL} to a (list-)tactic and tactic list never fails. +The resulting tactic fails if {T} fails when applied to the goal(s), or if the goal list is not empty and its length is not the same as that of the tactic list, or finally if {Ti} fails when applied to the {i}'th subgoal generated by {T}. @@ -24,5 +28,5 @@ generated by {T}. Applying different tactics to different subgoals. \SEEALSO -Tactical.EVERY, Tactical.ORELSE, Tactical.THEN. +Tactical.EVERY, Tactical.ORELSE, Tactical.THEN, Tactical.THEN_LT. \ENDDOC diff --git a/help/Docfiles/Tactical.THEN_LT.doc b/help/Docfiles/Tactical.THEN_LT.doc index 3de3f8f8e4..7609292b8e 100644 --- a/help/Docfiles/Tactical.THEN_LT.doc +++ b/help/Docfiles/Tactical.THEN_LT.doc @@ -1,7 +1,7 @@ \DOC THEN_LT -\TYPE {op THEN_LT : tactic -> list_tactic -> tactic -op THEN_LT : list_tactic -> list_tactic -> list_tactic} +\TYPE {op THEN_LT : tactic * list_tactic -> tactic +op THEN_LT : list_tactic * list_tactic -> list_tactic} \SYNOPSIS Applies a list-tactic to the corresponding subgoals generated by a tactic diff --git a/src/1/Tactical.sig b/src/1/Tactical.sig index 2dbcf35c21..aa9c7e0ba2 100644 --- a/src/1/Tactical.sig +++ b/src/1/Tactical.sig @@ -5,8 +5,18 @@ sig val TAC_PROOF : goal * tactic -> thm val prove : term * tactic -> thm val store_thm : string * term * tactic -> thm + val THEN : ('a -> goal list * (thm list -> 'b)) * tactic -> + 'a -> goal list * (thm list -> 'b) + (* could be used as val THEN : tactic * tactic -> tactic + val THEN : list_tactic * tactic -> list_tactic + *) + val THENL : ('a -> goal list * (thm list -> 'b)) * tactic list -> + 'a -> goal list * (thm list -> 'b) + (* could be used as val THENL : tactic * tactic list -> tactic + val THENL : list_tactic * tactic list -> list_tactic + *) val ORELSE : tactic * tactic -> tactic val ORELSE_LT : list_tactic * list_tactic -> list_tactic val THEN1 : tactic * tactic -> tactic @@ -44,6 +54,7 @@ sig val GEN_VALIDATE : bool -> tactic -> tactic val GEN_VALIDATE_LT : bool -> list_tactic -> list_tactic val EVERY : tactic list -> tactic + val EVERY_LT : list_tactic list -> list_tactic val FIRST : tactic list -> tactic val MAP_EVERY : ('a -> tactic) -> 'a list -> tactic val MAP_FIRST : ('a -> tactic) -> 'a list -> tactic diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index b2d0cf7dd1..78e3bdc945 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -132,6 +132,10 @@ fun ALLGOALS tac2 gl = fun tac1 THEN tac2 = tac1 THEN_LT ALLGOALS tac2 ; +(* first argument can be a tactic or a list-tactic *) +val _ = op THEN : tactic * tactic -> tactic ; +val _ = op THEN : list_tactic * tactic -> list_tactic ; + (*--------------------------------------------------------------------------- * fun TACS_TO_LT (tac2l: tactic list) : list_tactic = fn gl => * let @@ -185,6 +189,10 @@ fun NULL_OK_LT ltac [] = ([], Lib.I) fun tac1 THENL tacs2 = tac1 THEN_LT NULL_OK_LT (TACS_TO_LT tacs2) ; +(* first argument can be a tactic or a list-tactic *) +val _ = op THENL : tactic * tactic list -> tactic ; +val _ = op THENL : list_tactic * tactic list -> list_tactic ; + fun (tac1 ORELSE tac2) g = tac1 g handle HOL_ERR _ => tac2 g fun (ltac1 ORELSE_LT ltac2) gl = ltac1 gl handle HOL_ERR _ => ltac2 gl @@ -511,11 +519,12 @@ end (*-- Tactical quantifiers -- Apply a list of tactics in succession. -------*) (*--------------------------------------------------------------------------- - * Uses every tactic. + * Uses every tactic (similarly EVERY_LT for list_tactics) * EVERY [TAC1;...;TACn] = TAC1 THEN ... THEN TACn *---------------------------------------------------------------------------*) fun EVERY tacl = List.foldr (op THEN) ALL_TAC tacl +fun EVERY_LT ltacl = List.foldr (op THEN_LT) ALL_LT ltacl (*--------------------------------------------------------------------------- * Uses first tactic that succeeds. From ca5c8d4958ead932ab3d1a65591e99813c68a184 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Thu, 1 Jan 2015 00:40:28 +1100 Subject: [PATCH 078/718] new list-tactic USE_SG_THEN makes one subgoal available in the proof of another --- help/Docfiles/Tactical.NTH_GOAL.doc | 3 + help/Docfiles/Tactical.USE_SG_THEN.doc | 124 +++++++++++++++++++++++++ src/1/Tactical.sig | 1 + src/1/Tactical.sml | 31 +++++++ 4 files changed, 159 insertions(+) create mode 100644 help/Docfiles/Tactical.USE_SG_THEN.doc diff --git a/help/Docfiles/Tactical.NTH_GOAL.doc b/help/Docfiles/Tactical.NTH_GOAL.doc index 5dc7a85005..f0be2104bd 100644 --- a/help/Docfiles/Tactical.NTH_GOAL.doc +++ b/help/Docfiles/Tactical.NTH_GOAL.doc @@ -14,6 +14,9 @@ If {tac} is a tactic, {NTH_GOAL n tac} is a list-tactic which applies the tactic {tac} to the {n}'th member of a list of goals. +Note that in the interactive system, +subgoals are printed in reverse order of their numbering. + \FAILURE The application of {NTH_GOAL} to a tactic and integer never fails. The resulting list-tactic fails if {n} is less than 1 or greater than the diff --git a/help/Docfiles/Tactical.USE_SG_THEN.doc b/help/Docfiles/Tactical.USE_SG_THEN.doc new file mode 100644 index 0000000000..4bdeb8c7ff --- /dev/null +++ b/help/Docfiles/Tactical.USE_SG_THEN.doc @@ -0,0 +1,124 @@ +\DOC USE_SG_THEN + +\TYPE {USE_SG_THEN : thm_tactic -> int -> int -> list_tactic} + +\SYNOPSIS +Allows the user to use one subgoal to prove another + +\KEYWORDS +theorem-tactic, lemma. + +\DESCRIBE +In {USE_SG_THEN ttac nu np}, of the current goal list, subgoal number +{nu} can be used in proving subgoal number {np}. +Subgoal number {nu} is used as a lemma by {ttac} +to simplify subgoal number {np}. That is, if +subgoal number {nu} is {A ?- u}, subgoal number {np} is {A1 ?- t1}, and +{ + A1 ?- t1 + ========== ttac (u |- u) + A2 ?- t2 +} +then the list-tactic {USE_SG_THEN ttac nu np} gives this same result +(new subgoal(s)) for subgoal {np}. + +This list-tactic will be invalid unless {A} is a subset of {A1}. + +Note that in the interactive system, +subgoals are printed in reverse order of their numbering. + +\FAILURE +{USE_SG_THEN} will fail {ttac (u |- u)} fails on subgoal number {np}, +or if indices {np} or {nu} are out of range. Note that the subgoals in the +current subgoal list are numbered starting from 1. + +\USES +Where two subgoals are similar and not easy to prove, one can be used to +help prove the other. + +\EXAMPLE +Here subgoal 1 is assumed, so as to help in proving subgoal 2. +{ +r ∨ s +------------------------------------ + 0. p + 1. q + + +r +------------------------------------ + 0. p + 1. q + +2 subgoals +: + proof + +> elt (USE_SG_THEN ASSUME_TAC 1 2) ; +OK.. +2 subgoals: +val it = + +r ∨ s +------------------------------------ + 0. p + 1. q + 2. r + + +r +------------------------------------ + 0. p + 1. q + +2 subgoals +: + proof +} +Here is an example where the assumptions differ. +Subgoal 2 is used to solve subgoal 1, but the assumption {p') of +subgoal 2 remains to be proved. Without {VALIDATE_LT}, the list-tactic would +be invalid. +{ +r +------------------------------------ + 0. p' + 1. q + + +r +------------------------------------ + 0. p + 1. q + +2 subgoals +: + proof + +> elt (VALIDATE_LT (USE_SG_THEN ACCEPT_TAC 2 1)) ; +OK.. +2 subgoals: +val it = + +r +------------------------------------ + 0. p' + 1. q + + +p' +------------------------------------ + 0. p + 1. q + +2 subgoals +: + proof +} + + +\COMMENTS +Some users may expect the generated tactic to be {ttac (A |- u)}, rather +than {ttac (u |- u)}. + +\ENDDOC diff --git a/src/1/Tactical.sig b/src/1/Tactical.sig index aa9c7e0ba2..267ff4d91b 100644 --- a/src/1/Tactical.sig +++ b/src/1/Tactical.sig @@ -70,6 +70,7 @@ sig val PAT_ASSUM : term -> thm_tactic -> tactic val POP_ASSUM_LIST : (thm list -> tactic) -> tactic val SUBGOAL_THEN : term -> thm_tactic -> tactic + val USE_SG_THEN : thm_tactic -> int -> int -> list_tactic val CHANGED_TAC : tactic -> tactic val Q_TAC : (term -> tactic) -> term frag list -> tactic diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index 78e3bdc945..df16a57174 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -610,6 +610,37 @@ fun SUBGOAL_THEN wa ttac (asl, w) = (fn (tha :: thl) => PROVE_HYP tha (p thl) | _ => raise Match)) end +(*--------------------------------------------------------------------------- + * Use another subgoal, providing it as a theorem to a tactic + * + * USE_SG_THEN ttac nu np + * + * assumes subgoal number nu for proving subgoal number np + *---------------------------------------------------------------------------*) + +(* apnth : ('a -> 'a) -> int -> 'a list -> 'a list + apply a function to the nth member of a list *) +fun apnth f 0 (y :: ys) = f y :: ys + | apnth f n (y :: ys) = y :: apnth f (n-1) ys ; + +(* USE_SG_VAL : int -> int -> list_validation *) +fun USE_SG_VAL nu np thl = + let val thu = List.nth (thl, nu - 1) ; + in apnth (PROVE_HYP thu) (np - 1) thl end ; + +(* USE_SG_THEN : thm_tactic -> int -> int -> list_tactic *) +fun USE_SG_THEN ttac nu np gl = + let + val (_, wu) = List.nth (gl, nu - 1) ; + val ltac = NTH_GOAL (ttac (ASSUME wu)) np ; + val (glr, v) = ltac gl ; + val vp = USE_SG_VAL nu np ; + in (glr, vp o v) end ; + +(* USE_SG_TAC : int -> int -> list_tactic +val USE_SG_TAC = USE_SG_THEN ASSUME_TAC ; +*) + (*--------------------------------------------------------------------------- * A tactical that makes a tactic fail if it has no effect. *---------------------------------------------------------------------------*) From d004132040f0f1f0c97061531b553d97bba02ea4 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Thu, 1 Jan 2015 13:36:56 +1100 Subject: [PATCH 079/718] re-implement CONJ_ASM1_TAC, CONJ_ASM2_TAC using USE_SG_THEN now one-line implementation of these tactics --- help/Docfiles/Tactic.CONJ_ASM1_TAC.doc | 2 +- help/Docfiles/Tactic.CONJ_ASM2_TAC.doc | 2 +- src/1/Tactic.sml | 21 ++------------------- 3 files changed, 4 insertions(+), 21 deletions(-) diff --git a/help/Docfiles/Tactic.CONJ_ASM1_TAC.doc b/help/Docfiles/Tactic.CONJ_ASM1_TAC.doc index 90d293fe54..07035a0b40 100644 --- a/help/Docfiles/Tactic.CONJ_ASM1_TAC.doc +++ b/help/Docfiles/Tactic.CONJ_ASM1_TAC.doc @@ -23,5 +23,5 @@ to two subgoals corresponding to the first conjunct then the second conjunct. Fails unless the conclusion of the goal is a conjunction. \SEEALSO -Tactic.CONJ_ASM2_TAC, Tactic.CONJ_TAC. +Tactic.CONJ_ASM2_TAC, Tactic.CONJ_TAC, Tactical.USE_SG_THEN. \ENDDOC diff --git a/help/Docfiles/Tactic.CONJ_ASM2_TAC.doc b/help/Docfiles/Tactic.CONJ_ASM2_TAC.doc index 6b5a733b24..2c36ab798a 100644 --- a/help/Docfiles/Tactic.CONJ_ASM2_TAC.doc +++ b/help/Docfiles/Tactic.CONJ_ASM2_TAC.doc @@ -24,5 +24,5 @@ prove the second. Fails unless the conclusion of the goal is a conjunction. \SEEALSO -Tactic.CONJ_ASM1_TAC, Tactic.CONJ_TAC. +Tactic.CONJ_ASM1_TAC, Tactic.CONJ_TAC, Tactical.USE_SG_THEN. \ENDDOC diff --git a/src/1/Tactic.sml b/src/1/Tactic.sml index 978d8104fe..e199a25272 100644 --- a/src/1/Tactic.sml +++ b/src/1/Tactic.sml @@ -142,25 +142,8 @@ val CONJ_TAC: tactic = (* ASM1 & ASM2 variants assume the given conjunct when proving the other one *) -val CONJ_ASM1_TAC: tactic = - fn (asl, w) => - let - val (conj1, conj2) = dest_conj w - in - ([(asl, conj1), (conj1 :: asl, conj2)], - pairths (fn th1 => fn th2 => CONJ th1 (PROVE_HYP th1 th2))) - end - handle HOL_ERR _ => raise ERR "CONJ_ASM1_TAC" "" - -val CONJ_ASM2_TAC: tactic = - fn (asl, w) => - let - val (conj1, conj2) = dest_conj w - in - ([(conj2 :: asl, conj1), (asl, conj2)], - pairths (fn th1 => fn th2 => CONJ (PROVE_HYP th2 th1) th2)) - end - handle HOL_ERR _ => raise ERR "CONJ_ASM2_TAC" "" +val CONJ_ASM1_TAC = CONJ_TAC THEN_LT USE_SG_THEN ASSUME_TAC 1 2 ; +val CONJ_ASM2_TAC = CONJ_TAC THEN_LT USE_SG_THEN ASSUME_TAC 2 1 ; (*---------------------------------------------------------------------------* * Disjunction introduction * From fc9792d28d169d567b6aedbfe471ed74bbd24bff Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Thu, 1 Jan 2015 14:06:12 +1100 Subject: [PATCH 080/718] fix to help file Tactical.USE_SG_THEN.doc --- help/Docfiles/Tactical.USE_SG_THEN.doc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/help/Docfiles/Tactical.USE_SG_THEN.doc b/help/Docfiles/Tactical.USE_SG_THEN.doc index 4bdeb8c7ff..18963faa25 100644 --- a/help/Docfiles/Tactical.USE_SG_THEN.doc +++ b/help/Docfiles/Tactical.USE_SG_THEN.doc @@ -39,7 +39,7 @@ help prove the other. \EXAMPLE Here subgoal 1 is assumed, so as to help in proving subgoal 2. { -r ∨ s +r \/ s ------------------------------------ 0. p 1. q @@ -59,7 +59,7 @@ OK.. 2 subgoals: val it = -r ∨ s +r \/ s ------------------------------------ 0. p 1. q @@ -76,9 +76,9 @@ r proof } Here is an example where the assumptions differ. -Subgoal 2 is used to solve subgoal 1, but the assumption {p') of -subgoal 2 remains to be proved. Without {VALIDATE_LT}, the list-tactic would -be invalid. +Subgoal 2 is used to solve subgoal 1, +but the assumption {p'} of subgoal 2 remains to be proved. +Without {VALIDATE_LT}, the list-tactic would be invalid. { r ------------------------------------ @@ -116,7 +116,6 @@ p' proof } - \COMMENTS Some users may expect the generated tactic to be {ttac (A |- u)}, rather than {ttac (u |- u)}. From 8663830389d8d1e66108b8bad54cb0fc4147c956 Mon Sep 17 00:00:00 2001 From: Jeremy Dawson Date: Thu, 1 Jan 2015 15:26:58 +1100 Subject: [PATCH 081/718] infix declaration for THEN_LT in Tactic.sml not sure why this is needed - builds here without it, but not on GitHub; and clearly not needed for THEN in Tactic.sml --- src/1/Tactic.sml | 1 + 1 file changed, 1 insertion(+) diff --git a/src/1/Tactic.sml b/src/1/Tactic.sml index e199a25272..128960eeac 100644 --- a/src/1/Tactic.sml +++ b/src/1/Tactic.sml @@ -142,6 +142,7 @@ val CONJ_TAC: tactic = (* ASM1 & ASM2 variants assume the given conjunct when proving the other one *) +infix THEN_LT ; (* why do we need this? Not needed for THEN, below! *) val CONJ_ASM1_TAC = CONJ_TAC THEN_LT USE_SG_THEN ASSUME_TAC 1 2 ; val CONJ_ASM2_TAC = CONJ_TAC THEN_LT USE_SG_THEN ASSUME_TAC 2 1 ; From 21c9098c064d27345d624bee36aa2ac33c91cade Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Sat, 3 Jan 2015 10:11:32 +0800 Subject: [PATCH 082/718] Implement new, somewhat more generic subterm-finding functions. These subsume my previous attempt in the same vein (bvk_find_term). In this form, I believe gen_find_term will help with github issue #81, which is to do matching-and-renaming on sub-terms, not just whole goals or assumptions. --- help/Docfiles/HolKernel.gen_find_term.doc | 53 +++++++++++++++++ help/Docfiles/HolKernel.gen_find_terms.doc | 48 ++++++++++++++++ src/postkernel/HolKernel.sml | 67 +++++++++++++++------- src/postkernel/HolKernelDoc.sig | 2 + 4 files changed, 148 insertions(+), 22 deletions(-) create mode 100644 help/Docfiles/HolKernel.gen_find_term.doc create mode 100644 help/Docfiles/HolKernel.gen_find_terms.doc diff --git a/help/Docfiles/HolKernel.gen_find_term.doc b/help/Docfiles/HolKernel.gen_find_term.doc new file mode 100644 index 0000000000..c7326e1aca --- /dev/null +++ b/help/Docfiles/HolKernel.gen_find_term.doc @@ -0,0 +1,53 @@ +\DOC + +\TYPE {gen_find_term : (term list * term -> 'a option) -> term -> 'a option} + +\SYNOPSIS +Finds first value in range of partial function mapped over sub-terms of a term. + +\KEYWORDS +sub-term, search + +\DESCRIBE + +If a call to {gen_find_term f t} returns {SOME v}, then that result is +the first value returned by a call of function {f} to one of the +sub-terms of term {t}. The function {f} is successively passed +sub-terms of {t} starting with {t} itself and then proceeding in a +top-down, left-to-right traversal. + +The additional list of terms passed to the function {f} is the list of bound variables ``governing'' the sub-term in question, with the innermost bound variable first in the list. + +\FAILURE +A call to {gen_find_term f t} will fail if {f} fails when applied to any of the sub-terms of {t}. + +\EXAMPLE +{ +> gen_find_term (fn x => SOME x) ``SUC x``; +val it = SOME ([], ``SUC x``) : (term list * term) option + +> gen_find_term + (fn (bvs,t) => if null bvs andalso + (is_var t orelse numSyntax.is_numeral t) + then + Lib.total (match_term ``x:num``) t + else NONE) + ``SUC z + (\y. y) 5``; +val it = + SOME ([{redex = ``x``, residue = ``z``}], [])] : + ((term, term) Term.subst * (hol_type, hol_type) Term.subst) option +} + +\COMMENTS + +This function is used to implement {bvk_find_term}. This function +could itself be approximated by returning the last value in the list +returned by {gen_find_terms}. Such an implementation would be less +efficient because it would unnecessarily construct a list of all +possible results. It would also be semantically different if {f} had +side effects. + +\SEEALSO +HolKernel.bvk_find_term, HolKernel.find_term, HolKernel.gen_find_terms. + +\ENDDOC diff --git a/help/Docfiles/HolKernel.gen_find_terms.doc b/help/Docfiles/HolKernel.gen_find_terms.doc new file mode 100644 index 0000000000..087419c387 --- /dev/null +++ b/help/Docfiles/HolKernel.gen_find_terms.doc @@ -0,0 +1,48 @@ +\DOC + +\TYPE {gen_find_terms : (term list * term -> 'a option) -> term -> 'a list} + +\SYNOPSIS +Maps a partial function over sub-terms of a term. + +\KEYWORDS +sub-term, search + +\DESCRIBE +A call to {gen_find_terms f t} returns a list of values derived from +sub-terms of term {t}. The values are those generated by the function +{f} when it returns {SOME v}. The function {f} is successively passed +sub-terms of {t} starting with {t} itself and then proceeding in a +top-down, left-to-right traversal. The list of results returned in the +reverse of this order (but the fact that the traversal is done in the +described order is observable if {f} has side effects). + +The additional list of terms passed to the function {f} is the list of bound variables ``governing'' the sub-term in question, with the innermost bound variable first in the list. + +\FAILURE +A call to {gen_find_terms f t} will fail if {f} fails when applied to any of the sub-terms of {t}. + +\EXAMPLE +{ +> gen_find_terms (fn x => SOME x) ``SUC x``; +val it = + [([], ``x``), ([], ``SUC``), ([], ``SUC x``)]: + (term list * term) list + +> gen_find_terms + (fn (bvs,t) => if null bvs andalso + (is_var t orelse numSyntax.is_numeral t) + then + Lib.total (match_term ``x:num``) t + else NONE) + ``SUC z + (\y. y) 5``; +val it = + [([{redex = ``x``, residue = ``5``}], []), + ([{redex = ``x``, residue = ``z``}], [])]: + ((term, term) Term.subst * (hol_type, hol_type) Term.subst) list +} + +\SEEALSO +HolKernel.bvk_find_term, HolKernel.find_term, HolKernel.gen_find_term. + +\ENDDOC diff --git a/src/postkernel/HolKernel.sml b/src/postkernel/HolKernel.sml index 83ad2458fd..f0d48a2c57 100644 --- a/src/postkernel/HolKernel.sml +++ b/src/postkernel/HolKernel.sml @@ -268,6 +268,48 @@ fun find_term P = find_tm end + +local + datatype action = SEARCH of term | POP +in + fun gen_find_term f t = + let + fun search bvs actions = + case actions of + [] => NONE + | POP :: alist => search (tl bvs) alist + | SEARCH t :: alist => (case f (bvs, t) of + NONE => subterm bvs alist t + | x => x) + and subterm bvs alist t = + case dest_term t of + COMB (t1, t2) => search bvs (SEARCH t1 :: SEARCH t2 :: alist) + | LAMB (bv, t) => search (bv :: bvs) (SEARCH t :: POP :: alist) + | _ => search bvs alist + in + search [] [SEARCH t] + end + fun gen_find_terms f t = + let + fun search bvs actions acc = + case actions of + [] => acc + | POP :: alist => search (tl bvs) alist acc + | SEARCH t :: alist => + (case f (bvs, t) of + NONE => subterm bvs alist acc t + | SOME x => subterm bvs alist (x::acc) t) + and subterm bvs alist acc t = + case dest_term t of + COMB(t1, t2) => search bvs (SEARCH t1 :: SEARCH t2 :: alist) + acc + | LAMB (bv, t) => search (bv::bvs) (SEARCH t :: POP :: alist) acc + | _ => search bvs alist acc + in + search [] [SEARCH t] [] + end +end (* local *) + (* ---------------------------------------------------------------------- bvk_find_term : (term list * term -> bool) -> (term -> 'a) -> term -> 'a option @@ -290,28 +332,9 @@ fun find_term P = bound variables appearing earlier in the list. ---------------------------------------------------------------------- *) -local - datatype action = SEARCH of term | POP -in - fun bvk_find_term P k t = - let - fun search bvs actions = - case actions of - [] => NONE - | POP :: alist => search (tl bvs) alist - | SEARCH t :: alist => - (if P (bvs, t) - then SOME (k t) handle HOL_ERR _ => subterm bvs alist t - else subterm bvs alist t) - and subterm bvs alist t = - case dest_term t of - COMB (t1, t2) => search bvs (SEARCH t1 :: SEARCH t2 :: alist) - | LAMB (bv, t) => search (bv :: bvs) (SEARCH t :: POP :: alist) - | _ => search bvs alist - in - search [] [SEARCH t] - end -end (* local *) +fun bvk_find_term P k = + gen_find_term (fn x => if P x then SOME (k (#2 x)) handle HOL_ERR _ => NONE + else NONE) (*--------------------------------------------------------------------------- * find_terms: (term -> bool) -> term -> term list diff --git a/src/postkernel/HolKernelDoc.sig b/src/postkernel/HolKernelDoc.sig index 01c37bfeee..d65e1b2752 100644 --- a/src/postkernel/HolKernelDoc.sig +++ b/src/postkernel/HolKernelDoc.sig @@ -14,6 +14,8 @@ sig | COMB of term * term | LAMB of term * term + val gen_find_term: (term list * term -> 'a option) -> term -> 'a option + val gen_find_terms: (term list * term -> 'a option) -> term -> 'a list val bvk_find_term: (term list * term -> bool) -> (term -> 'a) -> term -> 'a option val dest_binder: term -> exn -> term -> term * term From acbc902fe3e3cb4ddc072814a52f66b2f64a8861 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Sat, 3 Jan 2015 14:51:01 +0800 Subject: [PATCH 083/718] Fill paragraphs in doc-file to make it appear better in within-HOL help. --- help/Docfiles/Q.MATCH_ASSUM_RENAME_TAC.doc | 43 +++++++++++++--------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/help/Docfiles/Q.MATCH_ASSUM_RENAME_TAC.doc b/help/Docfiles/Q.MATCH_ASSUM_RENAME_TAC.doc index dbd290fe5b..f0ca09e070 100644 --- a/help/Docfiles/Q.MATCH_ASSUM_RENAME_TAC.doc +++ b/help/Docfiles/Q.MATCH_ASSUM_RENAME_TAC.doc @@ -3,40 +3,47 @@ \TYPE {Q.MATCH_ASSUM_RENAME_TAC : term quotation -> string list -> tactic} \SYNOPSIS -Replaces selected terms with new variables by matching a pattern against an assumption. +Replaces selected terms with new variables by matching a pattern +against an assumption. \DESCRIBE -When applied to the goal {(asl, w)}, the tactic {Q.MATCH_ASSUM_RENAME_TAC q ls} -parses the quotation {q} in the context of the goal, producing a term to use as -a pattern. The tactic then attempts a (first order) match of the pattern -against each term in {asl}, stopping on the first matching assumption {a}. -For each variable {v} in the pattern, there will be an instantiation term {t}, -such that the substitution {pattern[v1 |-> t1, v2 |-> t2, ...]} produces {a}. -The effect of the tactic is to then replace each {t} with the corresponding -{v}, yielding a new goal. The list {ls} is of exceptions: if a variable {v}'s -name appears in {ls}, then no replacement of {v} for {t} is made. +When applied to the goal {(asl, w)}, the tactic +{Q.MATCH_ASSUM_RENAME_TAC q ls} parses the quotation {q} in the +context of the goal, producing a term to use as a pattern. The tactic +then attempts a (first order) match of the pattern against each term +in {asl}, stopping on the first matching assumption {a}. + +For each variable {v} in the pattern, there will be an instantiation +term {t}, such that the substitution +{ + pattern[v1 |-> t1, v2 |-> t2, ...] +} +produces {a}. The effect of the tactic is to then replace each {t} +with the corresponding {v}, yielding a new goal. The list {ls} is of +exceptions: if a variable {v}'s name appears in {ls}, then no +replacement of {v} for {t} is made. \FAILURE -{MATCH_ASSUM_RENAME_TAC} fails if the pattern provided does not match any -assumption, or if variables from the goal are used in the pattern in ways that -make the pattern fail to type-check. +{MATCH_ASSUM_RENAME_TAC} fails if the pattern provided does not match +any assumption, or if variables from the goal are used in the pattern +in ways that make the pattern fail to type-check. \EXAMPLE If the current goal is { (f x = Pair C'' C0') ?- (f C'' = f C0') } -then applying the tactic {Q.MATCH_ASSUM_RENAME_TAC `X = Pair c1 c2` ["X"]} results in -the goal +then applying the tactic {Q.MATCH_ASSUM_RENAME_TAC `X = Pair c1 c2` +["X"]} results in the goal { (f x = Pair c1 c2) ?- (f c1 = f c2) } \COMMENTS -This tactic improves on the following tedious workflow: {Q.PAT_ASSUM pat MP_TAC}, -{Q.MATCH_ABBREV_TAC `pat ==> X`}, {Q.UNABBREV_TAC `X`}, -{markerLib.RM_ALL_ABBREVS_TAC}, {STRIP_TAC}. + +This tactic improves on the following tedious workflow: +{Q.PAT_ASSUM pat MP_TAC}, {Q.MATCH_ABBREV_TAC `pat ==> X`}, {Q.UNABBREV_TAC `X`}, {markerLib.RM_ALL_ABBREVS_TAC}, {STRIP_TAC}. \SEEALSO Q.MATCH_RENAME_TAC. From 4e6cbfb2ba007ee4848d62c35d05edf171cc45a5 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Sat, 3 Jan 2015 21:04:15 +0800 Subject: [PATCH 084/718] A renaming/matching tactic that matches against subterms in the goal. Progress with Github issue #81 (which also calls for the same against assumptions and an abbreviation version too). --- help/Docfiles/Q.MATCH_GOALSUB_RENAME_TAC.doc | 48 ++++++++++++++++++ src/q/Q.sig | 1 + src/q/Q.sml | 25 ++++++++++ src/q/selftest.sml | 51 ++++++++++++++++---- 4 files changed, 115 insertions(+), 10 deletions(-) create mode 100644 help/Docfiles/Q.MATCH_GOALSUB_RENAME_TAC.doc diff --git a/help/Docfiles/Q.MATCH_GOALSUB_RENAME_TAC.doc b/help/Docfiles/Q.MATCH_GOALSUB_RENAME_TAC.doc new file mode 100644 index 0000000000..0985f47f81 --- /dev/null +++ b/help/Docfiles/Q.MATCH_GOALSUB_RENAME_TAC.doc @@ -0,0 +1,48 @@ +\DOC + +\TYPE {MATCH_GOALSUB_RENAME_TAC : term quotation -> string list -> tactic} + +\SYNOPSIS +Renames a goal in accordance with a pattern matched against a subterm +of the goal. + +\KEYWORDS +Renaming + +\DESCRIBE + +A call to {MATCH_GOALSUB_RENAME_TAC pat excs} attempts to find a match +for the pattern {pat} in the current goal (using {gen_find_term} to +find a sub-term of the goal that matches). If a match is found, the +goal is adjusted so that the variables occurring in the pattern now +also appear in the goal. This may rename variables in the goal, or +even cause larger sub-terms to be replaced by variables (as with +{SPEC_TAC}). + +\FAILURE + +Fails if there is no sub-term of the goal that matches the pattern. +Fails if the instantiation changes a pattern variable that already +exists in the goal. + +\EXAMPLE + +If the goal is +{ + ?- !x. x * 2 < y * (z + 1) * (y + a) +} +then applying {Q.MATCH_GOALSUB_RENAME_TAC `y + c` []} will match the +pattern {y + c} against the various subterms within the goal. The +first obvious match, with {z + 1} will be rejected because the +variable {y} is free in the goal, and is treated as if it were a local +constant. Because of this, {y + a} is the matching sub-term, and after +renaming the goal becomes +{ + ?- !x. x * 2 < y * (z + 1) * (y + c) +} + + +\SEEALSO +Q.MATCH_RENAME_TAC. + +\ENDDOC diff --git a/src/q/Q.sig b/src/q/Q.sig index 6040439620..a9b5f2473d 100644 --- a/src/q/Q.sig +++ b/src/q/Q.sig @@ -61,5 +61,6 @@ sig val MATCH_RENAME_TAC : tmquote -> string list -> tactic val MATCH_ASSUM_RENAME_TAC : tmquote -> string list -> tactic + val MATCH_GOALSUB_RENAME_TAC : tmquote -> string list -> tactic end diff --git a/src/q/Q.sml b/src/q/Q.sml index a62a147c91..344deb3b29 100644 --- a/src/q/Q.sml +++ b/src/q/Q.sml @@ -361,6 +361,8 @@ let val (sf,sb) = partition (fn {redex=l,residue=r} => mem l fvs) s in (filter (fn {redex=l,residue=r} => not (mem (fst(dest_var l)) except)) sb) end +(* these functions should probably be using raw_match_term in order to + handle the variables that are only allowed to be bound to themselves *) fun MATCH_RENAME_TAC q except (g as (asl,t)) = let val fvs = free_varsl(t::asl) val pat = Parse.parse_in_context fvs q @@ -381,4 +383,27 @@ fun MATCH_ASSUM_RENAME_TAC q except (g as (asl,t)) = let handle HOL_ERR e => find tl in find asl end g +fun MATCH_GOALSUB_RENAME_TAC q except (g as (asl, t)) = let + val ERR = ERR "MATCH_GOALSUB_RENAME_TAC" + val fvs = free_varsl (t::asl) + val pat = Parse.parse_in_context fvs q + val fvs_set = HOLset.fromList Term.compare fvs + fun test (bvs, subt) = + case Lib.total (fn t => raw_match [] fvs_set pat t ([],[])) subt of + SOME ((theta0, _), _) => + let + fun filt1 {redex,...} = not (mem (#1 (dest_var redex)) except) + fun filt2 {residue, ...} = + List.all (fn bv => not (free_in bv residue)) bvs + val theta = filter (fn s => filt1 s andalso filt2 s) theta0 + in + if null theta then NONE else SOME theta + end + | NONE => NONE +in + case gen_find_term test t of + SOME theta => make_rename_tac theta fvs except ERR g + | NONE => raise ERR "No matching sub-term found in goal term" +end + end (* Q *) diff --git a/src/q/selftest.sml b/src/q/selftest.sml index 602676a814..2ebf54635a 100644 --- a/src/q/selftest.sml +++ b/src/q/selftest.sml @@ -1,11 +1,9 @@ -open Parse boolLib HolKernel +open Parse boolLib HolKernel testutils -fun tprint s = print (StringCvt.padRight #" " 65 s) -fun die() = (print "FAILED!\n"; Process.exit Process.failure) val _ = tprint "Testing Q.EXISTS ... " val th = Q.EXISTS (`?f. f T T = T`, `$/\`) (REWRITE_CONV [] ``T /\ T``) - handle HOL_ERR _ => die() + handle HOL_ERR _ => die "FAILED!" val _ = print "OK\n" @@ -13,18 +11,51 @@ val _ = tprint "Testing Q.REFINE_EXISTS_TAC" val asm = ``!x1:'a x2:'a y1:'b y2:'b. (f x1 y1:'c = f x2 y2) <=> (x1 = x2) /\ (y1 = y2)`` val goal = ``?a:'c b:'d. Q a b`` -val (sgs, vfn) = Q.REFINE_EXISTS_TAC `f x y` ([asm], goal) handle _ => die() +val (sgs, vfn) = Q.REFINE_EXISTS_TAC `f x y` ([asm], goal) + handle _ => die "FAILED!" val expected_sg = ``?x:'a y:'b b:'d. Q (f x y:'c) b`` val result = case sgs of [g as ([a],g')] => if aconv a asm andalso aconv g' expected_sg then vfn [mk_thm g] - else die() - | _ => die() + else die "FAILED!" + | _ => die "FAILED!" val _ = if aconv (concl result) goal then case hyp result of - [a] => if aconv a asm then print "OK\n" else die() - | _ => die() - else die() + [a] => if aconv a asm then print "OK\n" else die "FAILED!" + | _ => die "FAILED!" + else die "FAILED!" + +(* fake arithmetic *) +val _ = new_type ("num", 0) +val _ = new_constant ("*", ``:num -> num -> num``) +val _ = new_constant ("+", ``:num -> num -> num``) +val _ = new_constant ("<", ``:num -> num -> bool``) +val _ = new_constant ("SUC", ``:num -> num``) +val _ = new_constant ("zero", ``:num``) +val _ = set_fixity "+" (Infixl 500) +val _ = set_fixity "*" (Infixl 600) +val _ = set_fixity "<" (Infix(NONASSOC, 450)) + +val _ = tprint "Q.MATCH_GOALSUB_RENAME_TAC 1" +val gl1 = ([] : term list, + ``!x. x * SUC (SUC zero) < y * (z + SUC zero) * (y + a)``) +val expected_result1 = + ``!x. x * SUC (SUC zero) < y * (z + SUC zero) * (y + c)`` +val (sgs, _) = Q.MATCH_GOALSUB_RENAME_TAC `y + c` [] gl1 +val _ = case sgs of + [([], t)] => if aconv t expected_result1 then print "OK\n" + else die "FAILED!" + | _ => die "FAILED!" + +val _ = tprint "Q.MATCH_GOALSUB_RENAME_TAC 2" +val gl2 = ([] : term list, + ``!x. x * SUC zero < y * (z + SUC zero) * (z + SUC (SUC zero))``) +val expected_result2 = ``!x. x * c < y * (a + c) * (a + SUC c)`` +val (sgs, _) = Q.MATCH_GOALSUB_RENAME_TAC `a + c` [] gl2 +val _ = case sgs of + [([], t)] => if aconv t expected_result2 then print "OK\n" + else die "FAILED!" + | _ => die "FAILED!" val _ = Process.exit Process.success; From eb627e3179f28e0cf8f2ead4c3d4b6f1b01829b9 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Wed, 7 Jan 2015 16:46:01 +1100 Subject: [PATCH 085/718] prove relationship between foldi and FOLDR This means you can prove something about a fold over sptrees by doing a list proof on the toAList of the tree, rather than messing with the sptree's structure. (But still do the fold directly on the tree when you execute it.) --- src/patricia/sptreeScript.sml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/patricia/sptreeScript.sml b/src/patricia/sptreeScript.sml index e44dd74065..5001a288b6 100644 --- a/src/patricia/sptreeScript.sml +++ b/src/patricia/sptreeScript.sml @@ -613,6 +613,16 @@ val domain_empty = store_thm("domain_empty", val _ = remove_ovl_mapping "lrnext" {Name = "lrnext", Thy = "sptree"} +val foldi_FOLDR_toAList_lemma = prove( + ``∀t n a ls. foldi f n (FOLDR (UNCURRY f) a ls) t = + FOLDR (UNCURRY f) a (foldi (λk v a. (k,v)::a) n ls t)``, + Induct >> simp[foldi_def] >> + rw[] >> pop_assum(assume_tac o GSYM) >> simp[]) + +val foldi_FOLDR_toAList = store_thm("foldi_FOLDR_toAList", + ``∀f a t. foldi f 0 a t = FOLDR (UNCURRY f) a (toAList t)``, + simp[toAList_def,GSYM foldi_FOLDR_toAList_lemma]) + val toListA_def = Define` (toListA acc LN = acc) /\ (toListA acc (LS a) = a::acc) /\ From 2a779459578de3a7aa61cc5140baf18d6aad18e5 Mon Sep 17 00:00:00 2001 From: Ramana Kumar Date: Wed, 7 Jan 2015 22:36:09 +1100 Subject: [PATCH 086/718] prove the keys of toAList of an sptree are ALL_DISTINCT --- src/patricia/sptreeScript.sml | 125 ++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/src/patricia/sptreeScript.sml b/src/patricia/sptreeScript.sml index 5001a288b6..1a7c9703cd 100644 --- a/src/patricia/sptreeScript.sml +++ b/src/patricia/sptreeScript.sml @@ -611,6 +611,131 @@ val domain_empty = store_thm("domain_empty", ``!t. wf t ==> ((t = LN) <=> (domain t = EMPTY))``, simp[] >> Induct >> simp[wf_def] >> metis_tac[]) +val toAList_append = prove( + ``∀t n ls. + foldi (λk v a. (k,v)::a) n ls t = + foldi (λk v a. (k,v)::a) n [] t ++ ls``, + Induct + >- simp[foldi_def] + >- simp[foldi_def] + >- ( + simp_tac std_ss [foldi_def,LET_THM] >> rpt gen_tac >> + first_assum(fn th => + CONV_TAC(LAND_CONV(RATOR_CONV(RAND_CONV(REWR_CONV th))))) >> + first_assum(fn th => + CONV_TAC(LAND_CONV(REWR_CONV th))) >> + first_assum(fn th => + CONV_TAC(RAND_CONV(LAND_CONV(REWR_CONV th)))) >> + metis_tac[APPEND_ASSOC] ) >> + simp_tac std_ss [foldi_def,LET_THM] >> rpt gen_tac >> + first_assum(fn th => + CONV_TAC(LAND_CONV(RATOR_CONV(RAND_CONV(RAND_CONV(REWR_CONV th)))))) >> + first_assum(fn th => + CONV_TAC(LAND_CONV(REWR_CONV th))) >> + first_assum(fn th => + CONV_TAC(RAND_CONV(LAND_CONV(REWR_CONV th)))) >> + metis_tac[APPEND_ASSOC,APPEND] ) + +val toAList_inc = prove( + ``∀t n. + foldi (λk v a. (k,v)::a) n [] t = + MAP (λ(k,v). (n + lrnext n * k,v)) (foldi (λk v a. (k,v)::a) 0 [] t)``, + Induct + >- simp[foldi_def] + >- simp[foldi_def] + >- ( + simp_tac std_ss [foldi_def,LET_THM] >> rpt gen_tac >> + CONV_TAC(LAND_CONV(REWR_CONV toAList_append)) >> + CONV_TAC(RAND_CONV(RAND_CONV(REWR_CONV toAList_append))) >> + first_assum(fn th => + CONV_TAC(LAND_CONV(LAND_CONV(REWR_CONV th)))) >> + first_assum(fn th => + CONV_TAC(LAND_CONV(RAND_CONV(REWR_CONV th)))) >> + first_assum(fn th => + CONV_TAC(RAND_CONV(RAND_CONV(LAND_CONV(REWR_CONV th))))) >> + first_assum(fn th => + CONV_TAC(RAND_CONV(RAND_CONV(RAND_CONV(REWR_CONV th))))) >> + rpt(pop_assum kall_tac) >> + simp[MAP_MAP_o,combinTheory.o_DEF,APPEND_11_LENGTH] >> + simp[MAP_EQ_f] >> + simp[lrnext_thm,pairTheory.UNCURRY,pairTheory.FORALL_PROD] >> + simp[lrlemma1,lrlemma2] ) + >- ( + simp_tac std_ss [foldi_def,LET_THM] >> rpt gen_tac >> + CONV_TAC(LAND_CONV(REWR_CONV toAList_append)) >> + CONV_TAC(RAND_CONV(RAND_CONV(REWR_CONV toAList_append))) >> + first_assum(fn th => + CONV_TAC(LAND_CONV(LAND_CONV(REWR_CONV th)))) >> + first_assum(fn th => + CONV_TAC(LAND_CONV(RAND_CONV(RAND_CONV(REWR_CONV th))))) >> + first_assum(fn th => + CONV_TAC(RAND_CONV(RAND_CONV(LAND_CONV(REWR_CONV th))))) >> + first_assum(fn th => + CONV_TAC(RAND_CONV(RAND_CONV(RAND_CONV(RAND_CONV(REWR_CONV th)))))) >> + rpt(pop_assum kall_tac) >> + simp[MAP_MAP_o,combinTheory.o_DEF,APPEND_11_LENGTH] >> + simp[MAP_EQ_f] >> + simp[lrnext_thm,pairTheory.UNCURRY,pairTheory.FORALL_PROD] >> + simp[lrlemma1,lrlemma2] )) + +val lemmas = prove( + ``(∀x. EVEN (2 * x + 2)) ∧ + (∀x. ODD (2 * x + 1))``, + conj_tac >- ( + simp[EVEN_EXISTS] >> rw[] >> + qexists_tac`SUC x` >> simp[] ) >> + simp[ODD_EXISTS,ADD1] >> + metis_tac[] ) + +val ALL_DISTINCT_MAP_FST_toAList = store_thm("ALL_DISTINCT_MAP_FST_toAList", + ``∀t. ALL_DISTINCT (MAP FST (toAList t))``, + simp[toAList_def] >> + Induct >> simp[foldi_def] >- ( + CONV_TAC(RAND_CONV(RAND_CONV(RATOR_CONV(RAND_CONV(REWR_CONV toAList_inc))))) >> + CONV_TAC(RAND_CONV(RAND_CONV(REWR_CONV toAList_append))) >> + CONV_TAC(RAND_CONV(RAND_CONV(LAND_CONV(REWR_CONV toAList_inc)))) >> + simp[MAP_MAP_o,combinTheory.o_DEF,pairTheory.UNCURRY,lrnext_thm] >> + simp[ALL_DISTINCT_APPEND] >> + rpt conj_tac >- ( + qmatch_abbrev_tac`ALL_DISTINCT (MAP f ls)` >> + `MAP f ls = MAP (λx. 2 * x + 1) (MAP FST ls)` by ( + simp[MAP_MAP_o,combinTheory.o_DEF,Abbr`f`] ) >> + pop_assum SUBST1_TAC >> qunabbrev_tac`f` >> + match_mp_tac ALL_DISTINCT_MAP_INJ >> + simp[] ) + >- ( + qmatch_abbrev_tac`ALL_DISTINCT (MAP f ls)` >> + `MAP f ls = MAP (λx. 2 * x + 2) (MAP FST ls)` by ( + simp[MAP_MAP_o,combinTheory.o_DEF,Abbr`f`] ) >> + pop_assum SUBST1_TAC >> qunabbrev_tac`f` >> + match_mp_tac ALL_DISTINCT_MAP_INJ >> + simp[] ) >> + simp[MEM_MAP,PULL_EXISTS,pairTheory.EXISTS_PROD] >> + metis_tac[ODD_EVEN,lemmas] ) >> + gen_tac >> + CONV_TAC(RAND_CONV(RAND_CONV(RATOR_CONV(RAND_CONV(RAND_CONV(REWR_CONV toAList_inc)))))) >> + CONV_TAC(RAND_CONV(RAND_CONV(REWR_CONV toAList_append))) >> + CONV_TAC(RAND_CONV(RAND_CONV(LAND_CONV(REWR_CONV toAList_inc)))) >> + simp[MAP_MAP_o,combinTheory.o_DEF,pairTheory.UNCURRY,lrnext_thm] >> + simp[ALL_DISTINCT_APPEND] >> + rpt conj_tac >- ( + qmatch_abbrev_tac`ALL_DISTINCT (MAP f ls)` >> + `MAP f ls = MAP (λx. 2 * x + 1) (MAP FST ls)` by ( + simp[MAP_MAP_o,combinTheory.o_DEF,Abbr`f`] ) >> + pop_assum SUBST1_TAC >> qunabbrev_tac`f` >> + match_mp_tac ALL_DISTINCT_MAP_INJ >> + simp[] ) + >- ( simp[MEM_MAP] ) + >- ( + qmatch_abbrev_tac`ALL_DISTINCT (MAP f ls)` >> + `MAP f ls = MAP (λx. 2 * x + 2) (MAP FST ls)` by ( + simp[MAP_MAP_o,combinTheory.o_DEF,Abbr`f`] ) >> + pop_assum SUBST1_TAC >> qunabbrev_tac`f` >> + match_mp_tac ALL_DISTINCT_MAP_INJ >> + simp[] ) >> + simp[MEM_MAP,PULL_EXISTS,pairTheory.EXISTS_PROD] >> + metis_tac[ODD_EVEN,lemmas] ) + val _ = remove_ovl_mapping "lrnext" {Name = "lrnext", Thy = "sptree"} val foldi_FOLDR_toAList_lemma = prove( From 21853aa66f90cce48313ea2285e18adf5fdd971f Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Thu, 8 Jan 2015 12:32:46 +1100 Subject: [PATCH 087/718] Implement Q.MATCH_ASMSUB_RENAME_TAC. Progress with #81. --- src/q/Q.sig | 1 + src/q/Q.sml | 31 ++++++++++++++++++++++++------- src/q/selftest.sml | 16 ++++++++++++++++ 3 files changed, 41 insertions(+), 7 deletions(-) diff --git a/src/q/Q.sig b/src/q/Q.sig index a9b5f2473d..da0ec3bd51 100644 --- a/src/q/Q.sig +++ b/src/q/Q.sig @@ -62,5 +62,6 @@ sig val MATCH_RENAME_TAC : tmquote -> string list -> tactic val MATCH_ASSUM_RENAME_TAC : tmquote -> string list -> tactic val MATCH_GOALSUB_RENAME_TAC : tmquote -> string list -> tactic + val MATCH_ASMSUB_RENAME_TAC : tmquote -> string list -> tactic end diff --git a/src/q/Q.sml b/src/q/Q.sml index 344deb3b29..ef8486eeed 100644 --- a/src/q/Q.sml +++ b/src/q/Q.sml @@ -383,11 +383,10 @@ fun MATCH_ASSUM_RENAME_TAC q except (g as (asl,t)) = let handle HOL_ERR e => find tl in find asl end g -fun MATCH_GOALSUB_RENAME_TAC q except (g as (asl, t)) = let - val ERR = ERR "MATCH_GOALSUB_RENAME_TAC" - val fvs = free_varsl (t::asl) - val pat = Parse.parse_in_context fvs q - val fvs_set = HOLset.fromList Term.compare fvs +(* needs to be eta-expanded so that the possible HOL_ERRs are raised + when applied to a goal, not before, thereby letting FIRST_ASSUM catch + the exception *) +fun subterm_rename_helper except ERR pat fvs fvs_set t g = let fun test (bvs, subt) = case Lib.total (fn t => raw_match [] fvs_set pat t ([],[])) subt of SOME ((theta0, _), _) => @@ -402,8 +401,26 @@ fun MATCH_GOALSUB_RENAME_TAC q except (g as (asl, t)) = let | NONE => NONE in case gen_find_term test t of - SOME theta => make_rename_tac theta fvs except ERR g - | NONE => raise ERR "No matching sub-term found in goal term" + SOME theta => make_rename_tac theta fvs except ERR + | NONE => raise ERR "No matching sub-term found" +end g + +fun MATCH_GOALSUB_RENAME_TAC q except (g as (asl, t)) = let + val ERR = ERR "MATCH_GOALSUB_RENAME_TAC" + val fvs = free_varsl (t::asl) + val pat = Parse.parse_in_context fvs q + val fvs_set = HOLset.fromList Term.compare fvs +in + subterm_rename_helper except ERR pat fvs fvs_set t g +end + +fun MATCH_ASMSUB_RENAME_TAC q except (g as (asl, t)) = let + val ERR = ERR "MATCH_ASMSUB_RENAME_TAC" + val fvs = free_varsl (t::asl) + val fvs_set = HOLset.fromList Term.compare fvs + val pat = Parse.parse_in_context fvs q +in + FIRST_ASSUM (subterm_rename_helper except ERR pat fvs fvs_set o concl) g end end (* Q *) diff --git a/src/q/selftest.sml b/src/q/selftest.sml index 2ebf54635a..f61038184d 100644 --- a/src/q/selftest.sml +++ b/src/q/selftest.sml @@ -58,4 +58,20 @@ val _ = case sgs of else die "FAILED!" | _ => die "FAILED!" +val _ = tprint "Q.MATCH_ASMSUB_RENAME_TAC 1" +val gl3 = ([``P (x:num): bool``, ``Q (x < SUC (SUC (SUC zero))) : bool``], + ``x + y < SUC (SUC zero)``); +val expected_a1 = ``P (x:num) : bool`` +val expected_a2 = ``Q (x < n) : bool`` +val expected_c = ``x + y < SUC (SUC zero)`` +val (sgs, _) = Q.MATCH_ASMSUB_RENAME_TAC `x < n` [] gl3 +val _ = case sgs of + [([a1, a2], c)] => if aconv a1 expected_a1 andalso + aconv a2 expected_a2 andalso + aconv c expected_c + then + print "OK\n" + else die "FAILED!" + | _ => die "FAILED!" + val _ = Process.exit Process.success; From 597f0957bbb9df48ad7597f28efdcb5f097fd2af Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Thu, 8 Jan 2015 12:34:47 +1100 Subject: [PATCH 088/718] Remove non-exhaustive match warning by slight code rewrite --- src/1/Tactical.sml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index df16a57174..c06accdc18 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -222,7 +222,9 @@ fun op THEN1 (tac1: tactic, tac2: tactic) : tactic = (counting goals from 1) *---------------------------------------------------------------------------*) fun NTH_GOAL tac n gl1 = - let val (gl_before, g :: gl_after) = Lib.split_after (n-1) gl1 ; + let + val (gl_before, ggl_after) = Lib.split_after (n-1) gl1 + val (g, gl_after) = valOf (List.getItem ggl_after) val (gl2, vf2) = tac g ; val gl_result = gl_before @ gl2 @ gl_after ; fun vf thl = From 3118e6a78a9c8590859c5ae40ee54bdf14a16b9a Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Thu, 8 Jan 2015 12:35:13 +1100 Subject: [PATCH 089/718] Remove trailing whitespace in Tactical.sml --- src/1/Tactical.sml | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index c06accdc18..5d7145fcbd 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -384,8 +384,8 @@ end * VALIDATE tac * GEN_VALIDATE true tac * - * is the same as "tac", except that where "tac" returns a proof which is - * because if proves a theorem with extra hypotheses, it returns those + * is the same as "tac", except that where "tac" returns a proof which is + * because if proves a theorem with extra hypotheses, it returns those * hypotheses as extra goals * * VALIDATE_LT ltac @@ -395,21 +395,21 @@ end * necessary to make a valid list-tactic * * GEN_VALIDATE(_LT) false always returns extra goals corresponding - * to the hypotheses of the theorem proved + * to the hypotheses of the theorem proved * *---------------------------------------------------------------------------*) local val validity_tag = "ValidityCheck" fun masquerade goal = Thm.mk_oracle_thm validity_tag goal ; fun achieves_concl th (asl, w) = Term.aconv (concl th) w ; - fun hyps_not_in_goal th (asl, w) = + fun hyps_not_in_goal th (asl, w) = Lib.filter (fn h => not (Lib.exists (aconv h) asl)) (hyp th) ; - fun extra_goals_tbp flag th (asl, w) = - List.map (fn eg => (asl, eg)) + fun extra_goals_tbp flag th (asl, w) = + List.map (fn eg => (asl, eg)) (case flag of true => hyps_not_in_goal th (asl, w) | false => hyp th) ; in (* GEN_VALIDATE : bool -> tactic -> tactic *) -fun GEN_VALIDATE (flag : bool) (tac : tactic) (g as (asl, w) : goal) = +fun GEN_VALIDATE (flag : bool) (tac : tactic) (g as (asl, w) : goal) = let val (glist, prf) = tac g ; (* pretend new goals are theorems, and apply validation to them *) val thprf = (prf (map masquerade glist)) ; @@ -425,21 +425,21 @@ fun GEN_VALIDATE (flag : bool) (tac : tactic) (g as (asl, w) : goal) = in (extra_goals @ glist, eprf) end ; (* split_lists : int list -> 'a list -> 'a list list * 'a list *) -fun split_lists (n :: ns) ths = +fun split_lists (n :: ns) ths = let val (nths, rest) = split_after n ths ; val (nsths, left) = split_lists ns rest ; - in (nths :: nsths, left) end + in (nths :: nsths, left) end | split_lists [] ths = ([], ths) ; - + (* GEN_VALIDATE_LT : bool -> list_tactic -> list_tactic *) -fun GEN_VALIDATE_LT (flag : bool) (ltac : list_tactic) (gl : goal list) = +fun GEN_VALIDATE_LT (flag : bool) (ltac : list_tactic) (gl : goal list) = let val (glist, prf) = ltac gl ; (* pretend new goals are theorems, and apply validation to them *) val thsprf = (prf (map masquerade glist)) ; val _ = if Lib.all2 achieves_concl thsprf gl then () - else raise ERR "GEN_VALIDATE_LT" + else raise ERR "GEN_VALIDATE_LT" "Invalid list-tactic - some wrong conclusion" ; - val extra_goal_lists = Lib.map2 (extra_goals_tbp flag) thsprf gl ; + val extra_goal_lists = Lib.map2 (extra_goals_tbp flag) thsprf gl ; val nextras = map length extra_goal_lists ; (* new validation: apply the theorems proving the additional goals to eliminate the extra hyps in the theorems proved by the given validation *) @@ -454,7 +454,7 @@ val VALIDATE = GEN_VALIDATE true ; val VALIDATE_LT = GEN_VALIDATE_LT true ; (* could avoid duplication of code in the above by the following -fun GEN_VALIDATE flag tac = +fun GEN_VALIDATE flag tac = ALL_TAC THEN_LT GEN_VALIDATE_LT flag (TACS_TO_LT [tac]) ; *) @@ -521,7 +521,7 @@ end (*-- Tactical quantifiers -- Apply a list of tactics in succession. -------*) (*--------------------------------------------------------------------------- - * Uses every tactic (similarly EVERY_LT for list_tactics) + * Uses every tactic (similarly EVERY_LT for list_tactics) * EVERY [TAC1;...;TACn] = TAC1 THEN ... THEN TACn *---------------------------------------------------------------------------*) @@ -641,7 +641,7 @@ fun USE_SG_THEN ttac nu np gl = (* USE_SG_TAC : int -> int -> list_tactic val USE_SG_TAC = USE_SG_THEN ASSUME_TAC ; -*) +*) (*--------------------------------------------------------------------------- * A tactical that makes a tactic fail if it has no effect. From 904bab9db4860a0a21bfe0b97a833f25c0f05d27 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Thu, 8 Jan 2015 13:42:12 +1100 Subject: [PATCH 090/718] Move useful apnth function to Lib Also make it raise a HOL_ERR rather than a Bind error if the index is negative or greater than the length of the list. --- src/1/Tactical.sml | 5 ----- src/prekernel/Lib.sig | 1 + src/prekernel/Lib.sml | 6 ++++++ 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/1/Tactical.sml b/src/1/Tactical.sml index 5d7145fcbd..280f8b9346 100644 --- a/src/1/Tactical.sml +++ b/src/1/Tactical.sml @@ -620,11 +620,6 @@ fun SUBGOAL_THEN wa ttac (asl, w) = * assumes subgoal number nu for proving subgoal number np *---------------------------------------------------------------------------*) -(* apnth : ('a -> 'a) -> int -> 'a list -> 'a list - apply a function to the nth member of a list *) -fun apnth f 0 (y :: ys) = f y :: ys - | apnth f n (y :: ys) = y :: apnth f (n-1) ys ; - (* USE_SG_VAL : int -> int -> list_validation *) fun USE_SG_VAL nu np thl = let val thu = List.nth (thl, nu - 1) ; diff --git a/src/prekernel/Lib.sig b/src/prekernel/Lib.sig index a8fa3b71bc..f6165539b3 100644 --- a/src/prekernel/Lib.sig +++ b/src/prekernel/Lib.sig @@ -21,6 +21,7 @@ sig val apfst : ('a -> 'b) -> 'a * 'c -> 'b * 'c val append : 'a list -> 'a list -> 'a list val appi : (int -> 'a -> unit) -> 'a list -> unit + val apnth : ('a -> 'a) -> int -> 'a list -> 'a list val apsnd : ('a -> 'b) -> 'c * 'a -> 'c * 'b val assert : ('a -> bool) -> 'a -> 'a val assert_exn : ('a -> bool) -> 'a -> exn -> 'a diff --git a/src/prekernel/Lib.sml b/src/prekernel/Lib.sml index b4c57bd066..818a74cc40 100644 --- a/src/prekernel/Lib.sml +++ b/src/prekernel/Lib.sml @@ -354,6 +354,12 @@ fun appi f = recurse 0 end +(* apnth : ('a -> 'a) -> int -> 'a list -> 'a list + apply a function to the nth member of a list *) +fun apnth f 0 (y :: ys) = f y :: ys + | apnth f n (y :: ys) = y :: apnth f (n-1) ys + | apnth f n [] = raise ERR "apnth" "list too short (or -ve index)" + fun mapi f lst = let fun recurse n acc lst = From 754a85197ece05d2a55775a0738a3f1796b143e0 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Thu, 8 Jan 2015 13:57:13 +1100 Subject: [PATCH 091/718] Add regression test for issue #214 --- src/1/selftest.sml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/1/selftest.sml b/src/1/selftest.sml index 78ef115b89..2c0d5ff408 100644 --- a/src/1/selftest.sml +++ b/src/1/selftest.sml @@ -496,5 +496,9 @@ in else die "FAILED" end +val _ = tprint "Testing (foo THENL [...]) when foo solves" +val _ = (ACCEPT_TAC TRUTH THENL [ACCEPT_TAC TRUTH]) ([], ``T``) handle HOL_ERR _ => die "FAILED!" +val _ = print "OK\n" + val _ = Process.exit (if List.all substtest tests then Process.success else Process.failure) From 521a5421bb3372631fb914cc889037810ac6afb8 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Thu, 8 Jan 2015 14:01:56 +1100 Subject: [PATCH 092/718] Remove trailing whitespace in proofman/goalStack.sml --- src/proofman/goalStack.sml | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/proofman/goalStack.sml b/src/proofman/goalStack.sml index a8460e134f..f4c9cb6bb9 100644 --- a/src/proofman/goalStack.sml +++ b/src/proofman/goalStack.sml @@ -111,8 +111,8 @@ fun rotate(GSTK{prop=PROVED _, ...}) _ = stack={goals=funpow n rotl goals, validation=validation o funpow n rotr} :: rst}; -local - fun imp_err s = +local + fun imp_err s = raise ERR "expandf or expand_listf" ("implementation error: "^s) fun return(GSTK{stack={goals=[],validation}::rst, prop as POSED g,final}) = @@ -165,7 +165,7 @@ fun expand_listf ltac (GSTK{prop=PROVED _, ...}) = raise ERR "expand_listf" "goal has already been proved" | expand_listf ltac (GSTK{prop as POSED g, stack = [], final}) = expand_listf ltac (GSTK{prop = POSED g, - stack = [{goals = [g], validation = hd}], final = final}) + stack = [{goals = [g], validation = hd}], final = final}) | expand_listf ltac (GSTK{prop, stack as {goals,validation}::rst, final}) = let val (new_goals, new_vf) = ltac goals val dpth = length stack - 1 (* because we don't augment the stack *) @@ -177,21 +177,21 @@ end ; fun expand tac gs = expandf (Tactical.VALID tac) gs; fun expand_list ltac gs = expand_listf (Tactical.VALID_LT ltac) gs; -fun flat (GSTK{prop, stack as {goals,validation} :: - {goals = g2 :: goals2, validation = validation2} :: rst, final}) = - let fun v thl = +fun flat (GSTK{prop, stack as {goals,validation} :: + {goals = g2 :: goals2, validation = validation2} :: rst, final}) = + let fun v thl = let val (thl1, thl2) = Lib.split_after (length goals) thl ; in validation2 (validation thl1 :: thl2) end ; val newgv = {goals = goals @ goals2, validation = v} ; in GSTK {prop = prop, stack = newgv :: rst, final = final} end ; - + fun flatn (GSTK{prop=PROVED _, ...}) n = raise ERR "flatn" "goal has already been proved" | flatn gstk 0 = gstk | flatn (gstk as GSTK{prop, stack = [], final}) n = gstk - | flatn (gstk as GSTK{prop, stack as [_], final}) n = gstk + | flatn (gstk as GSTK{prop, stack as [_], final}) n = gstk | flatn (gstk as GSTK{prop, stack, final}) n = flatn (flat gstk) (n-1) ; - + fun extract_thm (GSTK{prop=PROVED(th,_), ...}) = th | extract_thm _ = raise ERR "extract_thm" "no theorem proved"; From 144b3bd24e03582564d2c327d74d7bd30d15cb1c Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Thu, 8 Jan 2015 14:09:28 +1100 Subject: [PATCH 093/718] Reformat goalStack.sml's flat function to avoid non-exhaustive match warning --- src/proofman/goalStack.sml | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/src/proofman/goalStack.sml b/src/proofman/goalStack.sml index f4c9cb6bb9..b5b9779655 100644 --- a/src/proofman/goalStack.sml +++ b/src/proofman/goalStack.sml @@ -177,13 +177,24 @@ end ; fun expand tac gs = expandf (Tactical.VALID tac) gs; fun expand_list ltac gs = expand_listf (Tactical.VALID_LT ltac) gs; -fun flat (GSTK{prop, stack as {goals,validation} :: - {goals = g2 :: goals2, validation = validation2} :: rst, final}) = - let fun v thl = - let val (thl1, thl2) = Lib.split_after (length goals) thl ; - in validation2 (validation thl1 :: thl2) end ; - val newgv = {goals = goals @ goals2, validation = v} ; - in GSTK {prop = prop, stack = newgv :: rst, final = final} end ; +fun flat gstk = + case gstk of + GSTK{prop, + stack as {goals,validation} :: + {goals = g2 :: goals2, validation = validation2} :: + rst, + final} => + let + fun v thl = let + val (thl1, thl2) = Lib.split_after (length goals) thl + in + validation2 (validation thl1 :: thl2) + end + val newgv = {goals = goals @ goals2, validation = v} + in + GSTK {prop = prop, stack = newgv :: rst, final = final} + end + | _ => raise ERR "flat" "goalstack in wrong shape" fun flatn (GSTK{prop=PROVED _, ...}) n = raise ERR "flatn" "goal has already been proved" From a2d8c621ac33dcc09b020ff68f04cb398a2e7771 Mon Sep 17 00:00:00 2001 From: Michael Norrish Date: Thu, 8 Jan 2015 14:11:40 +1100 Subject: [PATCH 094/718] Modify optionSyntax.dest_none to unwrap the type returned. Closes #215. --- doc/next-release.md | 2 ++ src/option/Holmakefile | 10 ++++++++++ src/option/optionSyntax.sml | 4 +++- src/option/selftest.sml | 9 +++++++++ 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 src/option/Holmakefile create mode 100644 src/option/selftest.sml diff --git a/doc/next-release.md b/doc/next-release.md index aaf23c84c6..4fe687c67f 100644 --- a/doc/next-release.md +++ b/doc/next-release.md @@ -39,6 +39,8 @@ New examples: Incompatibilities: ------------------ +- The function `optionSyntax.dest_none` will now unwrap the type of its result, *e.g.*, returning `:α` rather than `:α option` when applied to `NONE : α option`. This brings it into line with the behaviour of `listSyntax.dest_nil`. See [this github issue](https://github.com/HOL-Theorem-Prover/HOL/issues/215). + * * * * *