diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp
index 61aa72c30a4654..64dfcd47296998 100644
--- a/clang/lib/Parse/ParseOpenMP.cpp
+++ b/clang/lib/Parse/ParseOpenMP.cpp
@@ -2954,8 +2954,6 @@ StmtResult Parser::ParseOpenMPDeclarativeOrExecutableDirective(
     }
     break;
   }
-  case OMPD_reverse:
-  case OMPD_interchange:
   case OMPD_declare_target: {
     SourceLocation DTLoc = ConsumeAnyToken();
     bool HasClauses = Tok.isNot(tok::annot_pragma_openmp_end);
diff --git a/llvm/include/llvm/Config/llvm-config.h.cmake b/llvm/include/llvm/Config/llvm-config.h.cmake
index 6908d67f93a1ba..169890ae29590d 100644
--- a/llvm/include/llvm/Config/llvm-config.h.cmake
+++ b/llvm/include/llvm/Config/llvm-config.h.cmake
@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 509956
+#define LLVM_MAIN_REVISION 509959
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
index a6e224d475a312..cdbca0b874e607 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
@@ -1,15 +1,13 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
-
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+f,+d,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+f,+d,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV64
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+f,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+f,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV64
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfhmin,+f,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+f,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV64
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV32,ZVFHMIN-ZFH-RV32
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV64,ZVFHMIN-ZFH-RV64
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfhmin,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV32,ZVFHMIN-ZFHIN-RV32
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN-RV64,ZVFHMIN-ZFHIN-RV64
 
 define void @fadd_v8f16(ptr %x, ptr %y) {
 ; ZVFH-LABEL: fadd_v8f16:
@@ -3828,6 +3826,422 @@ define void @trunc_v8f16(ptr %x) {
 ; ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
 ; ZVFH-NEXT:    vse16.v v8, (a0)
 ; ZVFH-NEXT:    ret
+;
+; ZVFHMIN-ZFH-RV32-LABEL: trunc_v8f16:
+; ZVFHMIN-ZFH-RV32:       # %bb.0:
+; ZVFHMIN-ZFH-RV32-NEXT:    addi sp, sp, -32
+; ZVFHMIN-ZFH-RV32-NEXT:    .cfi_def_cfa_offset 32
+; ZVFHMIN-ZFH-RV32-NEXT:    vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-ZFH-RV32-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-ZFH-RV32-NEXT:    mv a1, sp
+; ZVFHMIN-ZFH-RV32-NEXT:    vse16.v v8, (a1)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 14(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    lui a1, %hi(.LCPI115_0)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa5, %lo(.LCPI115_0)(a1)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB115_2
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.1:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB115_2:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 30(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 12(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB115_4
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.3:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB115_4:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 28(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 10(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB115_6
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.5:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB115_6:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 26(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 8(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB115_8
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.7:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB115_8:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 24(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 6(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB115_10
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.9:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB115_10:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 22(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 4(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB115_12
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.11:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB115_12:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 20(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 2(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB115_14
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.13:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB115_14:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 18(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 0(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB115_16
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.15:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa5, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa5, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB115_16:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 16(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    addi a1, sp, 16
+; ZVFHMIN-ZFH-RV32-NEXT:    vle16.v v8, (a1)
+; ZVFHMIN-ZFH-RV32-NEXT:    vse16.v v8, (a0)
+; ZVFHMIN-ZFH-RV32-NEXT:    addi sp, sp, 32
+; ZVFHMIN-ZFH-RV32-NEXT:    ret
+;
+; ZVFHMIN-ZFH-RV64-LABEL: trunc_v8f16:
+; ZVFHMIN-ZFH-RV64:       # %bb.0:
+; ZVFHMIN-ZFH-RV64-NEXT:    addi sp, sp, -32
+; ZVFHMIN-ZFH-RV64-NEXT:    .cfi_def_cfa_offset 32
+; ZVFHMIN-ZFH-RV64-NEXT:    vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-ZFH-RV64-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-ZFH-RV64-NEXT:    mv a1, sp
+; ZVFHMIN-ZFH-RV64-NEXT:    vse16.v v8, (a1)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 14(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    lui a1, %hi(.LCPI115_0)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa5, %lo(.LCPI115_0)(a1)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB115_2
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.1:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB115_2:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 30(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 12(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB115_4
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.3:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB115_4:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 28(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 10(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB115_6
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.5:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB115_6:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 26(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 8(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB115_8
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.7:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB115_8:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 24(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 6(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB115_10
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.9:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB115_10:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 22(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 4(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB115_12
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.11:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB115_12:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 20(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 2(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB115_14
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.13:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB115_14:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 18(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 0(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB115_16
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.15:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa5, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa5, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB115_16:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 16(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    addi a1, sp, 16
+; ZVFHMIN-ZFH-RV64-NEXT:    vle16.v v8, (a1)
+; ZVFHMIN-ZFH-RV64-NEXT:    vse16.v v8, (a0)
+; ZVFHMIN-ZFH-RV64-NEXT:    addi sp, sp, 32
+; ZVFHMIN-ZFH-RV64-NEXT:    ret
+;
+; ZVFHMIN-ZFHIN-RV32-LABEL: trunc_v8f16:
+; ZVFHMIN-ZFHIN-RV32:       # %bb.0:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    addi sp, sp, -32
+; ZVFHMIN-ZFHIN-RV32-NEXT:    .cfi_def_cfa_offset 32
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    mv a1, sp
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vse16.v v8, (a1)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa5, 14(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    lui a1, 307200
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fmv.w.x fa5, a1
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB115_2
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.1:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB115_2:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 30(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 12(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB115_4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.3:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB115_4:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 28(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 10(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB115_6
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.5:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB115_6:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 26(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 8(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB115_8
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.7:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB115_8:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 24(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 6(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB115_10
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.9:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB115_10:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 22(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 4(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB115_12
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.11:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB115_12:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 20(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 2(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB115_14
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.13:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB115_14:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 18(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 0(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB115_16
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.15:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa5, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa5, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB115_16:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa5, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa5, 16(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    addi a1, sp, 16
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vle16.v v8, (a1)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vse16.v v8, (a0)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    addi sp, sp, 32
+; ZVFHMIN-ZFHIN-RV32-NEXT:    ret
+;
+; ZVFHMIN-ZFHIN-RV64-LABEL: trunc_v8f16:
+; ZVFHMIN-ZFHIN-RV64:       # %bb.0:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    addi sp, sp, -32
+; ZVFHMIN-ZFHIN-RV64-NEXT:    .cfi_def_cfa_offset 32
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    mv a1, sp
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vse16.v v8, (a1)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa5, 14(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    lui a1, 307200
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fmv.w.x fa5, a1
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB115_2
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.1:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB115_2:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 30(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 12(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB115_4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.3:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB115_4:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 28(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 10(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB115_6
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.5:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB115_6:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 26(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 8(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB115_8
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.7:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB115_8:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 24(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 6(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB115_10
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.9:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB115_10:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 22(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 4(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB115_12
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.11:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB115_12:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 20(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 2(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB115_14
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.13:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB115_14:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 18(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 0(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB115_16
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.15:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa5, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa5, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB115_16:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa5, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa5, 16(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    addi a1, sp, 16
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vle16.v v8, (a1)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vse16.v v8, (a0)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    addi sp, sp, 32
+; ZVFHMIN-ZFHIN-RV64-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = call <8 x half> @llvm.trunc.v8f16(<8 x half> %a)
   store <8 x half> %b, ptr %x
@@ -3851,6 +4265,452 @@ define void @trunc_v6f16(ptr %x) {
 ; ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
 ; ZVFH-NEXT:    vse16.v v8, (a0)
 ; ZVFH-NEXT:    ret
+;
+; ZVFHMIN-ZFH-RV32-LABEL: trunc_v6f16:
+; ZVFHMIN-ZFH-RV32:       # %bb.0:
+; ZVFHMIN-ZFH-RV32-NEXT:    addi sp, sp, -48
+; ZVFHMIN-ZFH-RV32-NEXT:    .cfi_def_cfa_offset 48
+; ZVFHMIN-ZFH-RV32-NEXT:    vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-ZFH-RV32-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-ZFH-RV32-NEXT:    mv a1, sp
+; ZVFHMIN-ZFH-RV32-NEXT:    vse16.v v8, (a1)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 14(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    lui a1, %hi(.LCPI116_0)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa5, %lo(.LCPI116_0)(a1)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB116_2
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.1:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB116_2:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 46(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 12(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB116_4
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.3:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB116_4:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 44(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 10(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB116_6
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.5:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB116_6:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 42(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 8(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB116_8
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.7:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB116_8:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 40(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa4, 6(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB116_10
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.9:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB116_10:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 38(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa3, 4(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa2, fa3
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa2, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB116_12
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.11:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa3, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa2, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa3, fa2, fa3
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB116_12:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa3, 36(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa2, 2(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa1, fa2
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa1, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB116_14
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.13:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa2, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa1, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa2, fa1, fa2
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB116_14:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa2, 34(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    flh fa1, 0(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fabs.h fa0, fa1
+; ZVFHMIN-ZFH-RV32-NEXT:    flt.h a1, fa0, fa5
+; ZVFHMIN-ZFH-RV32-NEXT:    beqz a1, .LBB116_16
+; ZVFHMIN-ZFH-RV32-NEXT:  # %bb.15:
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.w.h a1, fa1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fcvt.h.w fa5, a1, rtz
+; ZVFHMIN-ZFH-RV32-NEXT:    fsgnj.h fa1, fa5, fa1
+; ZVFHMIN-ZFH-RV32-NEXT:  .LBB116_16:
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa1, 32(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    addi a1, sp, 32
+; ZVFHMIN-ZFH-RV32-NEXT:    vle16.v v8, (a1)
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa4, 30(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa3, 28(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa2, 26(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    fsh fa1, 24(sp)
+; ZVFHMIN-ZFH-RV32-NEXT:    addi a1, sp, 24
+; ZVFHMIN-ZFH-RV32-NEXT:    vsetivli zero, 4, e32, mf2, ta, ma
+; ZVFHMIN-ZFH-RV32-NEXT:    vle16.v v9, (a1)
+; ZVFHMIN-ZFH-RV32-NEXT:    vse16.v v9, (a0)
+; ZVFHMIN-ZFH-RV32-NEXT:    addi a0, a0, 8
+; ZVFHMIN-ZFH-RV32-NEXT:    vslidedown.vi v8, v8, 2
+; ZVFHMIN-ZFH-RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; ZVFHMIN-ZFH-RV32-NEXT:    vse32.v v8, (a0)
+; ZVFHMIN-ZFH-RV32-NEXT:    addi sp, sp, 48
+; ZVFHMIN-ZFH-RV32-NEXT:    ret
+;
+; ZVFHMIN-ZFH-RV64-LABEL: trunc_v6f16:
+; ZVFHMIN-ZFH-RV64:       # %bb.0:
+; ZVFHMIN-ZFH-RV64-NEXT:    addi sp, sp, -32
+; ZVFHMIN-ZFH-RV64-NEXT:    .cfi_def_cfa_offset 32
+; ZVFHMIN-ZFH-RV64-NEXT:    vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-ZFH-RV64-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-ZFH-RV64-NEXT:    mv a1, sp
+; ZVFHMIN-ZFH-RV64-NEXT:    vse16.v v8, (a1)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 14(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    lui a1, %hi(.LCPI116_0)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa5, %lo(.LCPI116_0)(a1)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB116_2
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.1:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB116_2:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 30(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 12(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB116_4
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.3:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB116_4:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 28(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 10(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB116_6
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.5:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB116_6:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 26(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 8(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB116_8
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.7:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB116_8:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 24(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 6(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB116_10
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.9:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB116_10:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 22(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 4(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB116_12
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.11:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB116_12:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 20(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 2(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB116_14
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.13:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa3, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB116_14:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 18(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    flh fa4, 0(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    fabs.h fa3, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:    flt.h a1, fa3, fa5
+; ZVFHMIN-ZFH-RV64-NEXT:    beqz a1, .LBB116_16
+; ZVFHMIN-ZFH-RV64-NEXT:  # %bb.15:
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.w.h a1, fa4, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fcvt.h.w fa5, a1, rtz
+; ZVFHMIN-ZFH-RV64-NEXT:    fsgnj.h fa4, fa5, fa4
+; ZVFHMIN-ZFH-RV64-NEXT:  .LBB116_16:
+; ZVFHMIN-ZFH-RV64-NEXT:    fsh fa4, 16(sp)
+; ZVFHMIN-ZFH-RV64-NEXT:    addi a1, sp, 16
+; ZVFHMIN-ZFH-RV64-NEXT:    vle16.v v8, (a1)
+; ZVFHMIN-ZFH-RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; ZVFHMIN-ZFH-RV64-NEXT:    vse64.v v8, (a0)
+; ZVFHMIN-ZFH-RV64-NEXT:    addi a0, a0, 8
+; ZVFHMIN-ZFH-RV64-NEXT:    vslidedown.vi v8, v8, 2
+; ZVFHMIN-ZFH-RV64-NEXT:    vse32.v v8, (a0)
+; ZVFHMIN-ZFH-RV64-NEXT:    addi sp, sp, 32
+; ZVFHMIN-ZFH-RV64-NEXT:    ret
+;
+; ZVFHMIN-ZFHIN-RV32-LABEL: trunc_v6f16:
+; ZVFHMIN-ZFHIN-RV32:       # %bb.0:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    addi sp, sp, -48
+; ZVFHMIN-ZFHIN-RV32-NEXT:    .cfi_def_cfa_offset 48
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    mv a1, sp
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vse16.v v8, (a1)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa5, 14(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    lui a1, 307200
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fmv.w.x fa5, a1
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB116_2
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.1:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB116_2:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 46(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 12(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB116_4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.3:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB116_4:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 44(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 10(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB116_6
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.5:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB116_6:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 42(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 8(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB116_8
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.7:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB116_8:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 40(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa4, 6(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB116_10
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.9:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB116_10:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 38(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa3, 4(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa3, fa3
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa2, fa3
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa2, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB116_12
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.11:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa3, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa2, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa3, fa2, fa3
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB116_12:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa3, fa3
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa3, 36(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa2, 2(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa2, fa2
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa1, fa2
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa1, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB116_14
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.13:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa2, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa1, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa2, fa1, fa2
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB116_14:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa2, fa2
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa2, 34(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flh fa1, 0(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.h fa1, fa1
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fabs.s fa0, fa1
+; ZVFHMIN-ZFHIN-RV32-NEXT:    flt.s a1, fa0, fa5
+; ZVFHMIN-ZFHIN-RV32-NEXT:    beqz a1, .LBB116_16
+; ZVFHMIN-ZFHIN-RV32-NEXT:  # %bb.15:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.w.s a1, fa1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.s.w fa5, a1, rtz
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsgnj.s fa1, fa5, fa1
+; ZVFHMIN-ZFHIN-RV32-NEXT:  .LBB116_16:
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fcvt.h.s fa5, fa1
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa5, 32(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    addi a1, sp, 32
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vle16.v v8, (a1)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa4, 30(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa3, 28(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa2, 26(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    fsh fa5, 24(sp)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    addi a1, sp, 24
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vsetivli zero, 4, e32, mf2, ta, ma
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vle16.v v9, (a1)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vse16.v v9, (a0)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    addi a0, a0, 8
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vslidedown.vi v8, v8, 2
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; ZVFHMIN-ZFHIN-RV32-NEXT:    vse32.v v8, (a0)
+; ZVFHMIN-ZFHIN-RV32-NEXT:    addi sp, sp, 48
+; ZVFHMIN-ZFHIN-RV32-NEXT:    ret
+;
+; ZVFHMIN-ZFHIN-RV64-LABEL: trunc_v6f16:
+; ZVFHMIN-ZFHIN-RV64:       # %bb.0:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    addi sp, sp, -32
+; ZVFHMIN-ZFHIN-RV64-NEXT:    .cfi_def_cfa_offset 32
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vsetivli zero, 8, e16, mf2, ta, ma
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vle16.v v8, (a0)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    mv a1, sp
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vse16.v v8, (a1)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa5, 14(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    lui a1, 307200
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fmv.w.x fa5, a1
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB116_2
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.1:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB116_2:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 30(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 12(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB116_4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.3:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB116_4:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 28(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 10(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB116_6
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.5:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB116_6:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 26(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 8(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB116_8
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.7:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB116_8:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 24(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 6(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB116_10
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.9:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB116_10:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 22(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 4(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB116_12
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.11:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB116_12:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 20(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 2(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB116_14
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.13:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa3, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB116_14:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa4, 18(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flh fa4, 0(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.h fa4, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fabs.s fa3, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    flt.s a1, fa3, fa5
+; ZVFHMIN-ZFHIN-RV64-NEXT:    beqz a1, .LBB116_16
+; ZVFHMIN-ZFHIN-RV64-NEXT:  # %bb.15:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.w.s a1, fa4, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.s.w fa5, a1, rtz
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsgnj.s fa4, fa5, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:  .LBB116_16:
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fcvt.h.s fa5, fa4
+; ZVFHMIN-ZFHIN-RV64-NEXT:    fsh fa5, 16(sp)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    addi a1, sp, 16
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vle16.v v8, (a1)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vse64.v v8, (a0)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    addi a0, a0, 8
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vslidedown.vi v8, v8, 2
+; ZVFHMIN-ZFHIN-RV64-NEXT:    vse32.v v8, (a0)
+; ZVFHMIN-ZFHIN-RV64-NEXT:    addi sp, sp, 32
+; ZVFHMIN-ZFHIN-RV64-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = call <6 x half> @llvm.trunc.v6f16(<6 x half> %a)
   store <6 x half> %b, ptr %x